drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319 #ifdef I40E_ESS_SUPPORT
1320         /* It can take upto 15 secs for GRST steady state */
1321         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1322 #endif
1323         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1324                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1326                         break;
1327                 i40e_msec_delay(100);
1328         }
1329         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330                 DEBUGOUT("Global reset polling failed to complete.\n");
1331                 return I40E_ERR_RESET_FAILED;
1332         }
1333
1334         /* Now Wait for the FW to be ready */
1335         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336                 reg = rd32(hw, I40E_GLNVM_ULD);
1337                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1342                         break;
1343                 }
1344                 i40e_msec_delay(10);
1345         }
1346         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348                 DEBUGOUT("wait for FW Reset complete timedout\n");
1349                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350                 return I40E_ERR_RESET_FAILED;
1351         }
1352
1353         /* If there was a Global Reset in progress when we got here,
1354          * we don't need to do the PF Reset
1355          */
1356         if (!cnt) {
1357                 reg = rd32(hw, I40E_PFGEN_CTRL);
1358                 wr32(hw, I40E_PFGEN_CTRL,
1359                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361                         reg = rd32(hw, I40E_PFGEN_CTRL);
1362                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1363                                 break;
1364                         i40e_msec_delay(1);
1365                 }
1366                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367                         DEBUGOUT("PF reset polling failed to complete.\n");
1368                         return I40E_ERR_RESET_FAILED;
1369                 }
1370         }
1371
1372         i40e_clear_pxe_mode(hw);
1373
1374
1375         return I40E_SUCCESS;
1376 }
1377
1378 /**
1379  * i40e_clear_hw - clear out any left over hw state
1380  * @hw: pointer to the hw struct
1381  *
1382  * Clear queues and interrupts, typically called at init time,
1383  * but after the capabilities have been found so we know how many
1384  * queues and msix vectors have been allocated.
1385  **/
1386 void i40e_clear_hw(struct i40e_hw *hw)
1387 {
1388         u32 num_queues, base_queue;
1389         u32 num_pf_int;
1390         u32 num_vf_int;
1391         u32 num_vfs;
1392         u32 i, j;
1393         u32 val;
1394         u32 eol = 0x7ff;
1395
1396         /* get number of interrupts, queues, and vfs */
1397         val = rd32(hw, I40E_GLPCI_CNF2);
1398         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1402
1403         val = rd32(hw, I40E_PFLAN_QALLOC);
1404         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409                 num_queues = (j - base_queue) + 1;
1410         else
1411                 num_queues = 0;
1412
1413         val = rd32(hw, I40E_PF_VT_PFALLOC);
1414         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419                 num_vfs = (j - i) + 1;
1420         else
1421                 num_vfs = 0;
1422
1423         /* stop all the interrupts */
1424         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426         for (i = 0; i < num_pf_int - 2; i++)
1427                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1428
1429         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431         wr32(hw, I40E_PFINT_LNKLST0, val);
1432         for (i = 0; i < num_pf_int - 2; i++)
1433                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435         for (i = 0; i < num_vfs; i++)
1436                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437         for (i = 0; i < num_vf_int - 2; i++)
1438                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1439
1440         /* warn the HW of the coming Tx disables */
1441         for (i = 0; i < num_queues; i++) {
1442                 u32 abs_queue_idx = base_queue + i;
1443                 u32 reg_block = 0;
1444
1445                 if (abs_queue_idx >= 128) {
1446                         reg_block = abs_queue_idx / 128;
1447                         abs_queue_idx %= 128;
1448                 }
1449
1450                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1454
1455                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1456         }
1457         i40e_usec_delay(400);
1458
1459         /* stop all the queues */
1460         for (i = 0; i < num_queues; i++) {
1461                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462                 wr32(hw, I40E_QTX_ENA(i), 0);
1463                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464                 wr32(hw, I40E_QRX_ENA(i), 0);
1465         }
1466
1467         /* short wait for all queue disables to settle */
1468         i40e_usec_delay(50);
1469 }
1470
1471 /**
1472  * i40e_clear_pxe_mode - clear pxe operations mode
1473  * @hw: pointer to the hw struct
1474  *
1475  * Make sure all PXE mode settings are cleared, including things
1476  * like descriptor fetch/write-back mode.
1477  **/
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1479 {
1480         if (i40e_check_asq_alive(hw))
1481                 i40e_aq_clear_pxe_mode(hw, NULL);
1482 }
1483
1484 /**
1485  * i40e_led_is_mine - helper to find matching led
1486  * @hw: pointer to the hw struct
1487  * @idx: index into GPIO registers
1488  *
1489  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1490  */
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1492 {
1493         u32 gpio_val = 0;
1494         u32 port;
1495
1496         if (!hw->func_caps.led[idx])
1497                 return 0;
1498
1499         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1502
1503         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504          * if it is not our port then ignore
1505          */
1506         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1507             (port != hw->port))
1508                 return 0;
1509
1510         return gpio_val;
1511 }
1512
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1518
1519 /**
1520  * i40e_led_get - return current on/off mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * The value returned is the 'mode' field as defined in the
1524  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525  * values are variations of possible behaviors relating to
1526  * blink, link, and wire.
1527  **/
1528 u32 i40e_led_get(struct i40e_hw *hw)
1529 {
1530         u32 current_mode = 0;
1531         u32 mode = 0;
1532         int i;
1533
1534         /* as per the documentation GPIO 22-29 are the LED
1535          * GPIO pins named LED0..LED7
1536          */
1537         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538                 u32 gpio_val = i40e_led_is_mine(hw, i);
1539
1540                 if (!gpio_val)
1541                         continue;
1542
1543                 /* ignore gpio LED src mode entries related to the activity LEDs */
1544                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546                 switch (current_mode) {
1547                 case I40E_COMBINED_ACTIVITY:
1548                 case I40E_FILTER_ACTIVITY:
1549                 case I40E_MAC_ACTIVITY:
1550                         continue;
1551                 default:
1552                         break;
1553                 }
1554
1555                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1557                 break;
1558         }
1559
1560         return mode;
1561 }
1562
1563 /**
1564  * i40e_led_set - set new on/off mode
1565  * @hw: pointer to the hw struct
1566  * @mode: 0=off, 0xf=on (else see manual for mode details)
1567  * @blink: true if the LED should blink when on, false if steady
1568  *
1569  * if this function is used to turn on the blink it should
1570  * be used to disable the blink when restoring the original state.
1571  **/
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1573 {
1574         u32 current_mode = 0;
1575         int i;
1576
1577         if (mode & 0xfffffff0)
1578                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1579
1580         /* as per the documentation GPIO 22-29 are the LED
1581          * GPIO pins named LED0..LED7
1582          */
1583         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584                 u32 gpio_val = i40e_led_is_mine(hw, i);
1585
1586                 if (!gpio_val)
1587                         continue;
1588
1589                 /* ignore gpio LED src mode entries related to the activity LEDs */
1590                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592                 switch (current_mode) {
1593                 case I40E_COMBINED_ACTIVITY:
1594                 case I40E_FILTER_ACTIVITY:
1595                 case I40E_MAC_ACTIVITY:
1596                         continue;
1597                 default:
1598                         break;
1599                 }
1600
1601                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602                 /* this & is a bit of paranoia, but serves as a range check */
1603                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1605
1606                 if (mode == I40E_LINK_ACTIVITY)
1607                         blink = false;
1608
1609                 if (blink)
1610                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1611                 else
1612                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1613
1614                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1615                 break;
1616         }
1617 }
1618
1619 /* Admin command wrappers */
1620
1621 /**
1622  * i40e_aq_get_phy_capabilities
1623  * @hw: pointer to the hw struct
1624  * @abilities: structure for PHY capabilities to be filled
1625  * @qualified_modules: report Qualified Modules
1626  * @report_init: report init capabilities (active are default)
1627  * @cmd_details: pointer to command details structure or NULL
1628  *
1629  * Returns the various PHY abilities supported on the Port.
1630  **/
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632                         bool qualified_modules, bool report_init,
1633                         struct i40e_aq_get_phy_abilities_resp *abilities,
1634                         struct i40e_asq_cmd_details *cmd_details)
1635 {
1636         struct i40e_aq_desc desc;
1637         enum i40e_status_code status;
1638         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1639
1640         if (!abilities)
1641                 return I40E_ERR_PARAM;
1642
1643         i40e_fill_default_direct_cmd_desc(&desc,
1644                                           i40e_aqc_opc_get_phy_abilities);
1645
1646         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647         if (abilities_size > I40E_AQ_LARGE_BUF)
1648                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1649
1650         if (qualified_modules)
1651                 desc.params.external.param0 |=
1652                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1653
1654         if (report_init)
1655                 desc.params.external.param0 |=
1656                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1657
1658         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1659                                     cmd_details);
1660
1661         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662                 status = I40E_ERR_UNKNOWN_PHY;
1663
1664         if (report_init)
1665                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1666
1667         return status;
1668 }
1669
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683                                 struct i40e_aq_set_phy_config *config,
1684                                 struct i40e_asq_cmd_details *cmd_details)
1685 {
1686         struct i40e_aq_desc desc;
1687         struct i40e_aq_set_phy_config *cmd =
1688                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689         enum i40e_status_code status;
1690
1691         if (!config)
1692                 return I40E_ERR_PARAM;
1693
1694         i40e_fill_default_direct_cmd_desc(&desc,
1695                                           i40e_aqc_opc_set_phy_config);
1696
1697         *cmd = *config;
1698
1699         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700
1701         return status;
1702 }
1703
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  *
1708  * Set the requested flow control mode using set_phy_config.
1709  **/
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711                                   bool atomic_restart)
1712 {
1713         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714         struct i40e_aq_get_phy_abilities_resp abilities;
1715         struct i40e_aq_set_phy_config config;
1716         enum i40e_status_code status;
1717         u8 pause_mask = 0x0;
1718
1719         *aq_failures = 0x0;
1720
1721         switch (fc_mode) {
1722         case I40E_FC_FULL:
1723                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1725                 break;
1726         case I40E_FC_RX_PAUSE:
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1728                 break;
1729         case I40E_FC_TX_PAUSE:
1730                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1731                 break;
1732         default:
1733                 break;
1734         }
1735
1736         /* Get the current phy config */
1737         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1738                                               NULL);
1739         if (status) {
1740                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1741                 return status;
1742         }
1743
1744         memset(&config, 0, sizeof(config));
1745         /* clear the old pause settings */
1746         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748         /* set the new abilities */
1749         config.abilities |= pause_mask;
1750         /* If the abilities have changed, then set the new config */
1751         if (config.abilities != abilities.abilities) {
1752                 /* Auto restart link so settings take effect */
1753                 if (atomic_restart)
1754                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755                 /* Copy over all the old settings */
1756                 config.phy_type = abilities.phy_type;
1757                 config.link_speed = abilities.link_speed;
1758                 config.eee_capability = abilities.eee_capability;
1759                 config.eeer = abilities.eeer_val;
1760                 config.low_power_ctrl = abilities.d3_lpan;
1761                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1762
1763                 if (status)
1764                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1765         }
1766         /* Update the link info */
1767         status = i40e_update_link_info(hw);
1768         if (status) {
1769                 /* Wait a little bit (on 40G cards it sometimes takes a really
1770                  * long time for link to come back from the atomic reset)
1771                  * and try once more
1772                  */
1773                 i40e_msec_delay(1000);
1774                 status = i40e_update_link_info(hw);
1775         }
1776         if (status)
1777                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_aq_set_mac_config
1784  * @hw: pointer to the hw struct
1785  * @max_frame_size: Maximum Frame Size to be supported by the port
1786  * @crc_en: Tell HW to append a CRC to outgoing frames
1787  * @pacing: Pacing configurations
1788  * @cmd_details: pointer to command details structure or NULL
1789  *
1790  * Configure MAC settings for frame size, jumbo frame support and the
1791  * addition of a CRC by the hardware.
1792  **/
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1794                                 u16 max_frame_size,
1795                                 bool crc_en, u16 pacing,
1796                                 struct i40e_asq_cmd_details *cmd_details)
1797 {
1798         struct i40e_aq_desc desc;
1799         struct i40e_aq_set_mac_config *cmd =
1800                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801         enum i40e_status_code status;
1802
1803         if (max_frame_size == 0)
1804                 return I40E_ERR_PARAM;
1805
1806         i40e_fill_default_direct_cmd_desc(&desc,
1807                                           i40e_aqc_opc_set_mac_config);
1808
1809         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810         cmd->params = ((u8)pacing & 0x0F) << 3;
1811         if (crc_en)
1812                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * i40e_aq_clear_pxe_mode
1821  * @hw: pointer to the hw struct
1822  * @cmd_details: pointer to command details structure or NULL
1823  *
1824  * Tell the firmware that the driver is taking over from PXE
1825  **/
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827                         struct i40e_asq_cmd_details *cmd_details)
1828 {
1829         enum i40e_status_code status;
1830         struct i40e_aq_desc desc;
1831         struct i40e_aqc_clear_pxe *cmd =
1832                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1833
1834         i40e_fill_default_direct_cmd_desc(&desc,
1835                                           i40e_aqc_opc_clear_pxe_mode);
1836
1837         cmd->rx_cnt = 0x2;
1838
1839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1840
1841         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1842
1843         return status;
1844 }
1845
1846 /**
1847  * i40e_aq_set_link_restart_an
1848  * @hw: pointer to the hw struct
1849  * @enable_link: if true: enable link, if false: disable link
1850  * @cmd_details: pointer to command details structure or NULL
1851  *
1852  * Sets up the link and restarts the Auto-Negotiation over the link.
1853  **/
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1856 {
1857         struct i40e_aq_desc desc;
1858         struct i40e_aqc_set_link_restart_an *cmd =
1859                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860         enum i40e_status_code status;
1861
1862         i40e_fill_default_direct_cmd_desc(&desc,
1863                                           i40e_aqc_opc_set_link_restart_an);
1864
1865         cmd->command = I40E_AQ_PHY_RESTART_AN;
1866         if (enable_link)
1867                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1868         else
1869                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1870
1871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1872
1873         return status;
1874 }
1875
1876 /**
1877  * i40e_aq_get_link_info
1878  * @hw: pointer to the hw struct
1879  * @enable_lse: enable/disable LinkStatusEvent reporting
1880  * @link: pointer to link status structure - optional
1881  * @cmd_details: pointer to command details structure or NULL
1882  *
1883  * Returns the link status of the adapter.
1884  **/
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886                                 bool enable_lse, struct i40e_link_status *link,
1887                                 struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_get_link_status *resp =
1891                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893         enum i40e_status_code status;
1894         bool tx_pause, rx_pause;
1895         u16 command_flags;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1898
1899         if (enable_lse)
1900                 command_flags = I40E_AQ_LSE_ENABLE;
1901         else
1902                 command_flags = I40E_AQ_LSE_DISABLE;
1903         resp->command_flags = CPU_TO_LE16(command_flags);
1904
1905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1906
1907         if (status != I40E_SUCCESS)
1908                 goto aq_get_link_info_exit;
1909
1910         /* save off old link status information */
1911         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1913
1914         /* update link status */
1915         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916         hw->phy.media_type = i40e_get_media_type(hw);
1917         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918         hw_link_info->link_info = resp->link_info;
1919         hw_link_info->an_info = resp->an_info;
1920         hw_link_info->ext_info = resp->ext_info;
1921         hw_link_info->loopback = resp->loopback;
1922         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1924
1925         /* update fc info */
1926         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928         if (tx_pause & rx_pause)
1929                 hw->fc.current_mode = I40E_FC_FULL;
1930         else if (tx_pause)
1931                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1932         else if (rx_pause)
1933                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1934         else
1935                 hw->fc.current_mode = I40E_FC_NONE;
1936
1937         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938                 hw_link_info->crc_enable = true;
1939         else
1940                 hw_link_info->crc_enable = false;
1941
1942         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943                 hw_link_info->lse_enable = true;
1944         else
1945                 hw_link_info->lse_enable = false;
1946
1947         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1950
1951         /* save link status information */
1952         if (link)
1953                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954                             I40E_NONDMA_TO_NONDMA);
1955
1956         /* flag cleared so helper functions don't call AQ again */
1957         hw->phy.get_link_info = false;
1958
1959 aq_get_link_info_exit:
1960         return status;
1961 }
1962
1963 /**
1964  * i40e_aq_set_phy_int_mask
1965  * @hw: pointer to the hw struct
1966  * @mask: interrupt mask to be set
1967  * @cmd_details: pointer to command details structure or NULL
1968  *
1969  * Set link interrupt mask.
1970  **/
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1972                                 u16 mask,
1973                                 struct i40e_asq_cmd_details *cmd_details)
1974 {
1975         struct i40e_aq_desc desc;
1976         struct i40e_aqc_set_phy_int_mask *cmd =
1977                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978         enum i40e_status_code status;
1979
1980         i40e_fill_default_direct_cmd_desc(&desc,
1981                                           i40e_aqc_opc_set_phy_int_mask);
1982
1983         cmd->event_mask = CPU_TO_LE16(mask);
1984
1985         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1986
1987         return status;
1988 }
1989
1990 /**
1991  * i40e_aq_get_local_advt_reg
1992  * @hw: pointer to the hw struct
1993  * @advt_reg: local AN advertisement register value
1994  * @cmd_details: pointer to command details structure or NULL
1995  *
1996  * Get the Local AN advertisement register value.
1997  **/
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1999                                 u64 *advt_reg,
2000                                 struct i40e_asq_cmd_details *cmd_details)
2001 {
2002         struct i40e_aq_desc desc;
2003         struct i40e_aqc_an_advt_reg *resp =
2004                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005         enum i40e_status_code status;
2006
2007         i40e_fill_default_direct_cmd_desc(&desc,
2008                                           i40e_aqc_opc_get_local_advt_reg);
2009
2010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2011
2012         if (status != I40E_SUCCESS)
2013                 goto aq_get_local_advt_reg_exit;
2014
2015         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2017
2018 aq_get_local_advt_reg_exit:
2019         return status;
2020 }
2021
2022 /**
2023  * i40e_aq_set_local_advt_reg
2024  * @hw: pointer to the hw struct
2025  * @advt_reg: local AN advertisement register value
2026  * @cmd_details: pointer to command details structure or NULL
2027  *
2028  * Get the Local AN advertisement register value.
2029  **/
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2031                                 u64 advt_reg,
2032                                 struct i40e_asq_cmd_details *cmd_details)
2033 {
2034         struct i40e_aq_desc desc;
2035         struct i40e_aqc_an_advt_reg *cmd =
2036                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037         enum i40e_status_code status;
2038
2039         i40e_fill_default_direct_cmd_desc(&desc,
2040                                           i40e_aqc_opc_get_local_advt_reg);
2041
2042         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         return status;
2048 }
2049
2050 /**
2051  * i40e_aq_get_partner_advt
2052  * @hw: pointer to the hw struct
2053  * @advt_reg: AN partner advertisement register value
2054  * @cmd_details: pointer to command details structure or NULL
2055  *
2056  * Get the link partner AN advertisement register value.
2057  **/
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2059                                 u64 *advt_reg,
2060                                 struct i40e_asq_cmd_details *cmd_details)
2061 {
2062         struct i40e_aq_desc desc;
2063         struct i40e_aqc_an_advt_reg *resp =
2064                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065         enum i40e_status_code status;
2066
2067         i40e_fill_default_direct_cmd_desc(&desc,
2068                                           i40e_aqc_opc_get_partner_advt);
2069
2070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071
2072         if (status != I40E_SUCCESS)
2073                 goto aq_get_partner_advt_exit;
2074
2075         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2077
2078 aq_get_partner_advt_exit:
2079         return status;
2080 }
2081
2082 /**
2083  * i40e_aq_set_lb_modes
2084  * @hw: pointer to the hw struct
2085  * @lb_modes: loopback mode to be set
2086  * @cmd_details: pointer to command details structure or NULL
2087  *
2088  * Sets loopback modes.
2089  **/
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2091                                 u16 lb_modes,
2092                                 struct i40e_asq_cmd_details *cmd_details)
2093 {
2094         struct i40e_aq_desc desc;
2095         struct i40e_aqc_set_lb_mode *cmd =
2096                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097         enum i40e_status_code status;
2098
2099         i40e_fill_default_direct_cmd_desc(&desc,
2100                                           i40e_aqc_opc_set_lb_modes);
2101
2102         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2103
2104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2105
2106         return status;
2107 }
2108
2109 /**
2110  * i40e_aq_set_phy_debug
2111  * @hw: pointer to the hw struct
2112  * @cmd_flags: debug command flags
2113  * @cmd_details: pointer to command details structure or NULL
2114  *
2115  * Reset the external PHY.
2116  **/
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118                                 struct i40e_asq_cmd_details *cmd_details)
2119 {
2120         struct i40e_aq_desc desc;
2121         struct i40e_aqc_set_phy_debug *cmd =
2122                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123         enum i40e_status_code status;
2124
2125         i40e_fill_default_direct_cmd_desc(&desc,
2126                                           i40e_aqc_opc_set_phy_debug);
2127
2128         cmd->command_flags = cmd_flags;
2129
2130         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131
2132         return status;
2133 }
2134
2135 /**
2136  * i40e_aq_add_vsi
2137  * @hw: pointer to the hw struct
2138  * @vsi_ctx: pointer to a vsi context struct
2139  * @cmd_details: pointer to command details structure or NULL
2140  *
2141  * Add a VSI context to the hardware.
2142 **/
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144                                 struct i40e_vsi_context *vsi_ctx,
2145                                 struct i40e_asq_cmd_details *cmd_details)
2146 {
2147         struct i40e_aq_desc desc;
2148         struct i40e_aqc_add_get_update_vsi *cmd =
2149                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150         struct i40e_aqc_add_get_update_vsi_completion *resp =
2151                 (struct i40e_aqc_add_get_update_vsi_completion *)
2152                 &desc.params.raw;
2153         enum i40e_status_code status;
2154
2155         i40e_fill_default_direct_cmd_desc(&desc,
2156                                           i40e_aqc_opc_add_vsi);
2157
2158         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159         cmd->connection_type = vsi_ctx->connection_type;
2160         cmd->vf_id = vsi_ctx->vf_num;
2161         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2162
2163         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2164
2165         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166                                     sizeof(vsi_ctx->info), cmd_details);
2167
2168         if (status != I40E_SUCCESS)
2169                 goto aq_add_vsi_exit;
2170
2171         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2175
2176 aq_add_vsi_exit:
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_default_vsi
2182  * @hw: pointer to the hw struct
2183  * @seid: vsi number
2184  * @cmd_details: pointer to command details structure or NULL
2185  **/
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2187                                 u16 seid,
2188                                 struct i40e_asq_cmd_details *cmd_details)
2189 {
2190         struct i40e_aq_desc desc;
2191         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2193                 &desc.params.raw;
2194         enum i40e_status_code status;
2195
2196         i40e_fill_default_direct_cmd_desc(&desc,
2197                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2198
2199         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201         cmd->seid = CPU_TO_LE16(seid);
2202
2203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205         return status;
2206 }
2207
2208 /**
2209  * i40e_aq_set_vsi_unicast_promiscuous
2210  * @hw: pointer to the hw struct
2211  * @seid: vsi number
2212  * @set: set unicast promiscuous enable/disable
2213  * @cmd_details: pointer to command details structure or NULL
2214  **/
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2216                                 u16 seid, bool set,
2217                                 struct i40e_asq_cmd_details *cmd_details)
2218 {
2219         struct i40e_aq_desc desc;
2220         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222         enum i40e_status_code status;
2223         u16 flags = 0;
2224
2225         i40e_fill_default_direct_cmd_desc(&desc,
2226                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2227
2228         if (set) {
2229                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2230                 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2231                      (hw->aq.api_maj_ver > 1))
2232                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2233         }
2234
2235         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2236
2237         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2238         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2239              (hw->aq.api_maj_ver > 1))
2240                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2241
2242         cmd->seid = CPU_TO_LE16(seid);
2243         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2244
2245         return status;
2246 }
2247
2248 /**
2249  * i40e_aq_set_vsi_multicast_promiscuous
2250  * @hw: pointer to the hw struct
2251  * @seid: vsi number
2252  * @set: set multicast promiscuous enable/disable
2253  * @cmd_details: pointer to command details structure or NULL
2254  **/
2255 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2256                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2257 {
2258         struct i40e_aq_desc desc;
2259         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2260                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2261         enum i40e_status_code status;
2262         u16 flags = 0;
2263
2264         i40e_fill_default_direct_cmd_desc(&desc,
2265                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2266
2267         if (set)
2268                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2269
2270         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2271
2272         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2273
2274         cmd->seid = CPU_TO_LE16(seid);
2275         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2276
2277         return status;
2278 }
2279
2280 /**
2281  * i40e_aq_set_vsi_mc_promisc_on_vlan
2282  * @hw: pointer to the hw struct
2283  * @seid: vsi number
2284  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2285  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2286  * @cmd_details: pointer to command details structure or NULL
2287  **/
2288 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2289                                 u16 seid, bool enable, u16 vid,
2290                                 struct i40e_asq_cmd_details *cmd_details)
2291 {
2292         struct i40e_aq_desc desc;
2293         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2294                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2295         enum i40e_status_code status;
2296         u16 flags = 0;
2297
2298         i40e_fill_default_direct_cmd_desc(&desc,
2299                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2300
2301         if (enable)
2302                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2303
2304         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2305         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2306         cmd->seid = CPU_TO_LE16(seid);
2307         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2308
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_uc_promisc_on_vlan
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2319  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2320  * @cmd_details: pointer to command details structure or NULL
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2323                                 u16 seid, bool enable, u16 vid,
2324                                 struct i40e_asq_cmd_details *cmd_details)
2325 {
2326         struct i40e_aq_desc desc;
2327         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2328                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2329         enum i40e_status_code status;
2330         u16 flags = 0;
2331
2332         i40e_fill_default_direct_cmd_desc(&desc,
2333                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2334
2335         if (enable)
2336                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2337
2338         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2339         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2340         cmd->seid = CPU_TO_LE16(seid);
2341         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2342
2343         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2344
2345         return status;
2346 }
2347
2348 /**
2349  * i40e_aq_set_vsi_broadcast
2350  * @hw: pointer to the hw struct
2351  * @seid: vsi number
2352  * @set_filter: true to set filter, false to clear filter
2353  * @cmd_details: pointer to command details structure or NULL
2354  *
2355  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2356  **/
2357 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2358                                 u16 seid, bool set_filter,
2359                                 struct i40e_asq_cmd_details *cmd_details)
2360 {
2361         struct i40e_aq_desc desc;
2362         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2363                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2364         enum i40e_status_code status;
2365
2366         i40e_fill_default_direct_cmd_desc(&desc,
2367                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2368
2369         if (set_filter)
2370                 cmd->promiscuous_flags
2371                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2372         else
2373                 cmd->promiscuous_flags
2374                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2375
2376         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2377         cmd->seid = CPU_TO_LE16(seid);
2378         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2379
2380         return status;
2381 }
2382
2383 /**
2384  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2385  * @hw: pointer to the hw struct
2386  * @seid: vsi number
2387  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2388  * @cmd_details: pointer to command details structure or NULL
2389  **/
2390 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2391                                 u16 seid, bool enable,
2392                                 struct i40e_asq_cmd_details *cmd_details)
2393 {
2394         struct i40e_aq_desc desc;
2395         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2396                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2397         enum i40e_status_code status;
2398         u16 flags = 0;
2399
2400         i40e_fill_default_direct_cmd_desc(&desc,
2401                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2402         if (enable)
2403                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2404
2405         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2406         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2407         cmd->seid = CPU_TO_LE16(seid);
2408
2409         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2410
2411         return status;
2412 }
2413
2414 /**
2415  * i40e_get_vsi_params - get VSI configuration info
2416  * @hw: pointer to the hw struct
2417  * @vsi_ctx: pointer to a vsi context struct
2418  * @cmd_details: pointer to command details structure or NULL
2419  **/
2420 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2421                                 struct i40e_vsi_context *vsi_ctx,
2422                                 struct i40e_asq_cmd_details *cmd_details)
2423 {
2424         struct i40e_aq_desc desc;
2425         struct i40e_aqc_add_get_update_vsi *cmd =
2426                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2427         struct i40e_aqc_add_get_update_vsi_completion *resp =
2428                 (struct i40e_aqc_add_get_update_vsi_completion *)
2429                 &desc.params.raw;
2430         enum i40e_status_code status;
2431
2432         UNREFERENCED_1PARAMETER(cmd_details);
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                                           i40e_aqc_opc_get_vsi_parameters);
2435
2436         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2437
2438         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2439
2440         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2441                                     sizeof(vsi_ctx->info), NULL);
2442
2443         if (status != I40E_SUCCESS)
2444                 goto aq_get_vsi_params_exit;
2445
2446         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2447         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2448         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2449         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2450
2451 aq_get_vsi_params_exit:
2452         return status;
2453 }
2454
2455 /**
2456  * i40e_aq_update_vsi_params
2457  * @hw: pointer to the hw struct
2458  * @vsi_ctx: pointer to a vsi context struct
2459  * @cmd_details: pointer to command details structure or NULL
2460  *
2461  * Update a VSI context.
2462  **/
2463 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2464                                 struct i40e_vsi_context *vsi_ctx,
2465                                 struct i40e_asq_cmd_details *cmd_details)
2466 {
2467         struct i40e_aq_desc desc;
2468         struct i40e_aqc_add_get_update_vsi *cmd =
2469                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2470         enum i40e_status_code status;
2471
2472         i40e_fill_default_direct_cmd_desc(&desc,
2473                                           i40e_aqc_opc_update_vsi_parameters);
2474         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2475
2476         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2477
2478         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2479                                     sizeof(vsi_ctx->info), cmd_details);
2480
2481         return status;
2482 }
2483
2484 /**
2485  * i40e_aq_get_switch_config
2486  * @hw: pointer to the hardware structure
2487  * @buf: pointer to the result buffer
2488  * @buf_size: length of input buffer
2489  * @start_seid: seid to start for the report, 0 == beginning
2490  * @cmd_details: pointer to command details structure or NULL
2491  *
2492  * Fill the buf with switch configuration returned from AdminQ command
2493  **/
2494 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2495                                 struct i40e_aqc_get_switch_config_resp *buf,
2496                                 u16 buf_size, u16 *start_seid,
2497                                 struct i40e_asq_cmd_details *cmd_details)
2498 {
2499         struct i40e_aq_desc desc;
2500         struct i40e_aqc_switch_seid *scfg =
2501                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2502         enum i40e_status_code status;
2503
2504         i40e_fill_default_direct_cmd_desc(&desc,
2505                                           i40e_aqc_opc_get_switch_config);
2506         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2507         if (buf_size > I40E_AQ_LARGE_BUF)
2508                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2509         scfg->seid = CPU_TO_LE16(*start_seid);
2510
2511         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2512         *start_seid = LE16_TO_CPU(scfg->seid);
2513
2514         return status;
2515 }
2516
2517 /**
2518  * i40e_aq_set_switch_config
2519  * @hw: pointer to the hardware structure
2520  * @flags: bit flag values to set
2521  * @valid_flags: which bit flags to set
2522  * @cmd_details: pointer to command details structure or NULL
2523  *
2524  * Set switch configuration bits
2525  **/
2526 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2527                                 u16 flags, u16 valid_flags,
2528                                 struct i40e_asq_cmd_details *cmd_details)
2529 {
2530         struct i40e_aq_desc desc;
2531         struct i40e_aqc_set_switch_config *scfg =
2532                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2533         enum i40e_status_code status;
2534
2535         i40e_fill_default_direct_cmd_desc(&desc,
2536                                           i40e_aqc_opc_set_switch_config);
2537         scfg->flags = CPU_TO_LE16(flags);
2538         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2539
2540         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2541
2542         return status;
2543 }
2544
2545 /**
2546  * i40e_aq_get_firmware_version
2547  * @hw: pointer to the hw struct
2548  * @fw_major_version: firmware major version
2549  * @fw_minor_version: firmware minor version
2550  * @fw_build: firmware build number
2551  * @api_major_version: major queue version
2552  * @api_minor_version: minor queue version
2553  * @cmd_details: pointer to command details structure or NULL
2554  *
2555  * Get the firmware version from the admin queue commands
2556  **/
2557 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2558                                 u16 *fw_major_version, u16 *fw_minor_version,
2559                                 u32 *fw_build,
2560                                 u16 *api_major_version, u16 *api_minor_version,
2561                                 struct i40e_asq_cmd_details *cmd_details)
2562 {
2563         struct i40e_aq_desc desc;
2564         struct i40e_aqc_get_version *resp =
2565                 (struct i40e_aqc_get_version *)&desc.params.raw;
2566         enum i40e_status_code status;
2567
2568         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2569
2570         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2571
2572         if (status == I40E_SUCCESS) {
2573                 if (fw_major_version != NULL)
2574                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2575                 if (fw_minor_version != NULL)
2576                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2577                 if (fw_build != NULL)
2578                         *fw_build = LE32_TO_CPU(resp->fw_build);
2579                 if (api_major_version != NULL)
2580                         *api_major_version = LE16_TO_CPU(resp->api_major);
2581                 if (api_minor_version != NULL)
2582                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2583
2584                 /* A workaround to fix the API version in SW */
2585                 if (api_major_version && api_minor_version &&
2586                     fw_major_version && fw_minor_version &&
2587                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2588                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2589                      (*fw_major_version > 4)))
2590                         *api_minor_version = 2;
2591         }
2592
2593         return status;
2594 }
2595
2596 /**
2597  * i40e_aq_send_driver_version
2598  * @hw: pointer to the hw struct
2599  * @dv: driver's major, minor version
2600  * @cmd_details: pointer to command details structure or NULL
2601  *
2602  * Send the driver version to the firmware
2603  **/
2604 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2605                                 struct i40e_driver_version *dv,
2606                                 struct i40e_asq_cmd_details *cmd_details)
2607 {
2608         struct i40e_aq_desc desc;
2609         struct i40e_aqc_driver_version *cmd =
2610                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2611         enum i40e_status_code status;
2612         u16 len;
2613
2614         if (dv == NULL)
2615                 return I40E_ERR_PARAM;
2616
2617         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2618
2619         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2620         cmd->driver_major_ver = dv->major_version;
2621         cmd->driver_minor_ver = dv->minor_version;
2622         cmd->driver_build_ver = dv->build_version;
2623         cmd->driver_subbuild_ver = dv->subbuild_version;
2624
2625         len = 0;
2626         while (len < sizeof(dv->driver_string) &&
2627                (dv->driver_string[len] < 0x80) &&
2628                dv->driver_string[len])
2629                 len++;
2630         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2631                                        len, cmd_details);
2632
2633         return status;
2634 }
2635
2636 /**
2637  * i40e_get_link_status - get status of the HW network link
2638  * @hw: pointer to the hw struct
2639  * @link_up: pointer to bool (true/false = linkup/linkdown)
2640  *
2641  * Variable link_up true if link is up, false if link is down.
2642  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2643  *
2644  * Side effect: LinkStatusEvent reporting becomes enabled
2645  **/
2646 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2647 {
2648         enum i40e_status_code status = I40E_SUCCESS;
2649
2650         if (hw->phy.get_link_info) {
2651                 status = i40e_update_link_info(hw);
2652
2653                 if (status != I40E_SUCCESS)
2654                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2655                                    status);
2656         }
2657
2658         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2659
2660         return status;
2661 }
2662
2663 /**
2664  * i40e_updatelink_status - update status of the HW network link
2665  * @hw: pointer to the hw struct
2666  **/
2667 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2668 {
2669         struct i40e_aq_get_phy_abilities_resp abilities;
2670         enum i40e_status_code status = I40E_SUCCESS;
2671
2672         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2673         if (status)
2674                 return status;
2675
2676         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2677                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2678                                                       &abilities, NULL);
2679                 if (status)
2680                         return status;
2681
2682                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2683                         sizeof(hw->phy.link_info.module_type));
2684         }
2685         return status;
2686 }
2687
2688
2689 /**
2690  * i40e_get_link_speed
2691  * @hw: pointer to the hw struct
2692  *
2693  * Returns the link speed of the adapter.
2694  **/
2695 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2696 {
2697         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2698         enum i40e_status_code status = I40E_SUCCESS;
2699
2700         if (hw->phy.get_link_info) {
2701                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2702
2703                 if (status != I40E_SUCCESS)
2704                         goto i40e_link_speed_exit;
2705         }
2706
2707         speed = hw->phy.link_info.link_speed;
2708
2709 i40e_link_speed_exit:
2710         return speed;
2711 }
2712
2713 /**
2714  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2715  * @hw: pointer to the hw struct
2716  * @uplink_seid: the MAC or other gizmo SEID
2717  * @downlink_seid: the VSI SEID
2718  * @enabled_tc: bitmap of TCs to be enabled
2719  * @default_port: true for default port VSI, false for control port
2720  * @veb_seid: pointer to where to put the resulting VEB SEID
2721  * @enable_stats: true to turn on VEB stats
2722  * @cmd_details: pointer to command details structure or NULL
2723  *
2724  * This asks the FW to add a VEB between the uplink and downlink
2725  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2726  **/
2727 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2728                                 u16 downlink_seid, u8 enabled_tc,
2729                                 bool default_port, u16 *veb_seid,
2730                                 bool enable_stats,
2731                                 struct i40e_asq_cmd_details *cmd_details)
2732 {
2733         struct i40e_aq_desc desc;
2734         struct i40e_aqc_add_veb *cmd =
2735                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2736         struct i40e_aqc_add_veb_completion *resp =
2737                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2738         enum i40e_status_code status;
2739         u16 veb_flags = 0;
2740
2741         /* SEIDs need to either both be set or both be 0 for floating VEB */
2742         if (!!uplink_seid != !!downlink_seid)
2743                 return I40E_ERR_PARAM;
2744
2745         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2746
2747         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2748         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2749         cmd->enable_tcs = enabled_tc;
2750         if (!uplink_seid)
2751                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2752         if (default_port)
2753                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2754         else
2755                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2756
2757         /* reverse logic here: set the bitflag to disable the stats */
2758         if (!enable_stats)
2759                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2760
2761         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2762
2763         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2764
2765         if (!status && veb_seid)
2766                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2767
2768         return status;
2769 }
2770
2771 /**
2772  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2773  * @hw: pointer to the hw struct
2774  * @veb_seid: the SEID of the VEB to query
2775  * @switch_id: the uplink switch id
2776  * @floating: set to true if the VEB is floating
2777  * @statistic_index: index of the stats counter block for this VEB
2778  * @vebs_used: number of VEB's used by function
2779  * @vebs_free: total VEB's not reserved by any function
2780  * @cmd_details: pointer to command details structure or NULL
2781  *
2782  * This retrieves the parameters for a particular VEB, specified by
2783  * uplink_seid, and returns them to the caller.
2784  **/
2785 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2786                                 u16 veb_seid, u16 *switch_id,
2787                                 bool *floating, u16 *statistic_index,
2788                                 u16 *vebs_used, u16 *vebs_free,
2789                                 struct i40e_asq_cmd_details *cmd_details)
2790 {
2791         struct i40e_aq_desc desc;
2792         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2793                 (struct i40e_aqc_get_veb_parameters_completion *)
2794                 &desc.params.raw;
2795         enum i40e_status_code status;
2796
2797         if (veb_seid == 0)
2798                 return I40E_ERR_PARAM;
2799
2800         i40e_fill_default_direct_cmd_desc(&desc,
2801                                           i40e_aqc_opc_get_veb_parameters);
2802         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2803
2804         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2805         if (status)
2806                 goto get_veb_exit;
2807
2808         if (switch_id)
2809                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2810         if (statistic_index)
2811                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2812         if (vebs_used)
2813                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2814         if (vebs_free)
2815                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2816         if (floating) {
2817                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2818                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2819                         *floating = true;
2820                 else
2821                         *floating = false;
2822         }
2823
2824 get_veb_exit:
2825         return status;
2826 }
2827
2828 /**
2829  * i40e_aq_add_macvlan
2830  * @hw: pointer to the hw struct
2831  * @seid: VSI for the mac address
2832  * @mv_list: list of macvlans to be added
2833  * @count: length of the list
2834  * @cmd_details: pointer to command details structure or NULL
2835  *
2836  * Add MAC/VLAN addresses to the HW filtering
2837  **/
2838 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2839                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2840                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2841 {
2842         struct i40e_aq_desc desc;
2843         struct i40e_aqc_macvlan *cmd =
2844                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2845         enum i40e_status_code status;
2846         u16 buf_size;
2847         int i;
2848
2849         if (count == 0 || !mv_list || !hw)
2850                 return I40E_ERR_PARAM;
2851
2852         buf_size = count * sizeof(*mv_list);
2853
2854         /* prep the rest of the request */
2855         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2856         cmd->num_addresses = CPU_TO_LE16(count);
2857         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2858         cmd->seid[1] = 0;
2859         cmd->seid[2] = 0;
2860
2861         for (i = 0; i < count; i++)
2862                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2863                         mv_list[i].flags |=
2864                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2865
2866         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2867         if (buf_size > I40E_AQ_LARGE_BUF)
2868                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2869
2870         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2871                                        cmd_details);
2872
2873         return status;
2874 }
2875
2876 /**
2877  * i40e_aq_remove_macvlan
2878  * @hw: pointer to the hw struct
2879  * @seid: VSI for the mac address
2880  * @mv_list: list of macvlans to be removed
2881  * @count: length of the list
2882  * @cmd_details: pointer to command details structure or NULL
2883  *
2884  * Remove MAC/VLAN addresses from the HW filtering
2885  **/
2886 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2887                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2888                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2889 {
2890         struct i40e_aq_desc desc;
2891         struct i40e_aqc_macvlan *cmd =
2892                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2893         enum i40e_status_code status;
2894         u16 buf_size;
2895
2896         if (count == 0 || !mv_list || !hw)
2897                 return I40E_ERR_PARAM;
2898
2899         buf_size = count * sizeof(*mv_list);
2900
2901         /* prep the rest of the request */
2902         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2903         cmd->num_addresses = CPU_TO_LE16(count);
2904         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2905         cmd->seid[1] = 0;
2906         cmd->seid[2] = 0;
2907
2908         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2909         if (buf_size > I40E_AQ_LARGE_BUF)
2910                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2911
2912         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2913                                        cmd_details);
2914
2915         return status;
2916 }
2917
2918 /**
2919  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2920  * @hw: pointer to the hw struct
2921  * @opcode: AQ opcode for add or delete mirror rule
2922  * @sw_seid: Switch SEID (to which rule refers)
2923  * @rule_type: Rule Type (ingress/egress/VLAN)
2924  * @id: Destination VSI SEID or Rule ID
2925  * @count: length of the list
2926  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2927  * @cmd_details: pointer to command details structure or NULL
2928  * @rule_id: Rule ID returned from FW
2929  * @rule_used: Number of rules used in internal switch
2930  * @rule_free: Number of rules free in internal switch
2931  *
2932  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2933  * VEBs/VEPA elements only
2934  **/
2935 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2936                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2937                         u16 count, __le16 *mr_list,
2938                         struct i40e_asq_cmd_details *cmd_details,
2939                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2940 {
2941         struct i40e_aq_desc desc;
2942         struct i40e_aqc_add_delete_mirror_rule *cmd =
2943                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2944         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2945         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2946         enum i40e_status_code status;
2947         u16 buf_size;
2948
2949         buf_size = count * sizeof(*mr_list);
2950
2951         /* prep the rest of the request */
2952         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2953         cmd->seid = CPU_TO_LE16(sw_seid);
2954         cmd->rule_type = CPU_TO_LE16(rule_type &
2955                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2956         cmd->num_entries = CPU_TO_LE16(count);
2957         /* Dest VSI for add, rule_id for delete */
2958         cmd->destination = CPU_TO_LE16(id);
2959         if (mr_list) {
2960                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2961                                                 I40E_AQ_FLAG_RD));
2962                 if (buf_size > I40E_AQ_LARGE_BUF)
2963                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2964         }
2965
2966         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2967                                        cmd_details);
2968         if (status == I40E_SUCCESS ||
2969             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2970                 if (rule_id)
2971                         *rule_id = LE16_TO_CPU(resp->rule_id);
2972                 if (rules_used)
2973                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2974                 if (rules_free)
2975                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2976         }
2977         return status;
2978 }
2979
2980 /**
2981  * i40e_aq_add_mirrorrule - add a mirror rule
2982  * @hw: pointer to the hw struct
2983  * @sw_seid: Switch SEID (to which rule refers)
2984  * @rule_type: Rule Type (ingress/egress/VLAN)
2985  * @dest_vsi: SEID of VSI to which packets will be mirrored
2986  * @count: length of the list
2987  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2988  * @cmd_details: pointer to command details structure or NULL
2989  * @rule_id: Rule ID returned from FW
2990  * @rule_used: Number of rules used in internal switch
2991  * @rule_free: Number of rules free in internal switch
2992  *
2993  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2994  **/
2995 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2996                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2997                         struct i40e_asq_cmd_details *cmd_details,
2998                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2999 {
3000         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3001             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3002                 if (count == 0 || !mr_list)
3003                         return I40E_ERR_PARAM;
3004         }
3005
3006         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3007                                   rule_type, dest_vsi, count, mr_list,
3008                                   cmd_details, rule_id, rules_used, rules_free);
3009 }
3010
3011 /**
3012  * i40e_aq_delete_mirrorrule - delete a mirror rule
3013  * @hw: pointer to the hw struct
3014  * @sw_seid: Switch SEID (to which rule refers)
3015  * @rule_type: Rule Type (ingress/egress/VLAN)
3016  * @count: length of the list
3017  * @rule_id: Rule ID that is returned in the receive desc as part of
3018  *              add_mirrorrule.
3019  * @mr_list: list of mirrored VLAN IDs to be removed
3020  * @cmd_details: pointer to command details structure or NULL
3021  * @rule_used: Number of rules used in internal switch
3022  * @rule_free: Number of rules free in internal switch
3023  *
3024  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3025  **/
3026 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3027                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3028                         struct i40e_asq_cmd_details *cmd_details,
3029                         u16 *rules_used, u16 *rules_free)
3030 {
3031         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3032         if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3033                 if (!rule_id)
3034                         return I40E_ERR_PARAM;
3035         } else {
3036                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3037                  * mirroring. For other rule_type, count and rule_type should
3038                  * not matter.
3039                  */
3040                 if (count == 0 || !mr_list)
3041                         return I40E_ERR_PARAM;
3042         }
3043
3044         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3045                                   rule_type, rule_id, count, mr_list,
3046                                   cmd_details, NULL, rules_used, rules_free);
3047 }
3048
3049 /**
3050  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3051  * @hw: pointer to the hw struct
3052  * @seid: VSI for the vlan filters
3053  * @v_list: list of vlan filters to be added
3054  * @count: length of the list
3055  * @cmd_details: pointer to command details structure or NULL
3056  **/
3057 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3058                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3059                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3060 {
3061         struct i40e_aq_desc desc;
3062         struct i40e_aqc_macvlan *cmd =
3063                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3064         enum i40e_status_code status;
3065         u16 buf_size;
3066
3067         if (count == 0 || !v_list || !hw)
3068                 return I40E_ERR_PARAM;
3069
3070         buf_size = count * sizeof(*v_list);
3071
3072         /* prep the rest of the request */
3073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3074         cmd->num_addresses = CPU_TO_LE16(count);
3075         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3076         cmd->seid[1] = 0;
3077         cmd->seid[2] = 0;
3078
3079         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3080         if (buf_size > I40E_AQ_LARGE_BUF)
3081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3082
3083         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3084                                        cmd_details);
3085
3086         return status;
3087 }
3088
3089 /**
3090  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3091  * @hw: pointer to the hw struct
3092  * @seid: VSI for the vlan filters
3093  * @v_list: list of macvlans to be removed
3094  * @count: length of the list
3095  * @cmd_details: pointer to command details structure or NULL
3096  **/
3097 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3098                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3099                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3100 {
3101         struct i40e_aq_desc desc;
3102         struct i40e_aqc_macvlan *cmd =
3103                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3104         enum i40e_status_code status;
3105         u16 buf_size;
3106
3107         if (count == 0 || !v_list || !hw)
3108                 return I40E_ERR_PARAM;
3109
3110         buf_size = count * sizeof(*v_list);
3111
3112         /* prep the rest of the request */
3113         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3114         cmd->num_addresses = CPU_TO_LE16(count);
3115         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3116         cmd->seid[1] = 0;
3117         cmd->seid[2] = 0;
3118
3119         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3120         if (buf_size > I40E_AQ_LARGE_BUF)
3121                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3122
3123         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3124                                        cmd_details);
3125
3126         return status;
3127 }
3128
3129 /**
3130  * i40e_aq_send_msg_to_vf
3131  * @hw: pointer to the hardware structure
3132  * @vfid: vf id to send msg
3133  * @v_opcode: opcodes for VF-PF communication
3134  * @v_retval: return error code
3135  * @msg: pointer to the msg buffer
3136  * @msglen: msg length
3137  * @cmd_details: pointer to command details
3138  *
3139  * send msg to vf
3140  **/
3141 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3142                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3143                                 struct i40e_asq_cmd_details *cmd_details)
3144 {
3145         struct i40e_aq_desc desc;
3146         struct i40e_aqc_pf_vf_message *cmd =
3147                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3148         enum i40e_status_code status;
3149
3150         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3151         cmd->id = CPU_TO_LE32(vfid);
3152         desc.cookie_high = CPU_TO_LE32(v_opcode);
3153         desc.cookie_low = CPU_TO_LE32(v_retval);
3154         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3155         if (msglen) {
3156                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3157                                                 I40E_AQ_FLAG_RD));
3158                 if (msglen > I40E_AQ_LARGE_BUF)
3159                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3160                 desc.datalen = CPU_TO_LE16(msglen);
3161         }
3162         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3163
3164         return status;
3165 }
3166
3167 /**
3168  * i40e_aq_debug_read_register
3169  * @hw: pointer to the hw struct
3170  * @reg_addr: register address
3171  * @reg_val: register value
3172  * @cmd_details: pointer to command details structure or NULL
3173  *
3174  * Read the register using the admin queue commands
3175  **/
3176 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3177                                 u32 reg_addr, u64 *reg_val,
3178                                 struct i40e_asq_cmd_details *cmd_details)
3179 {
3180         struct i40e_aq_desc desc;
3181         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3182                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3183         enum i40e_status_code status;
3184
3185         if (reg_val == NULL)
3186                 return I40E_ERR_PARAM;
3187
3188         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3189
3190         cmd_resp->address = CPU_TO_LE32(reg_addr);
3191
3192         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3193
3194         if (status == I40E_SUCCESS) {
3195                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3196                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3197         }
3198
3199         return status;
3200 }
3201
3202 /**
3203  * i40e_aq_debug_write_register
3204  * @hw: pointer to the hw struct
3205  * @reg_addr: register address
3206  * @reg_val: register value
3207  * @cmd_details: pointer to command details structure or NULL
3208  *
3209  * Write to a register using the admin queue commands
3210  **/
3211 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3212                                 u32 reg_addr, u64 reg_val,
3213                                 struct i40e_asq_cmd_details *cmd_details)
3214 {
3215         struct i40e_aq_desc desc;
3216         struct i40e_aqc_debug_reg_read_write *cmd =
3217                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3218         enum i40e_status_code status;
3219
3220         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3221
3222         cmd->address = CPU_TO_LE32(reg_addr);
3223         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3224         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3225
3226         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3227
3228         return status;
3229 }
3230
3231 /**
3232  * i40e_aq_get_hmc_resource_profile
3233  * @hw: pointer to the hw struct
3234  * @profile: type of profile the HMC is to be set as
3235  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3236  * @cmd_details: pointer to command details structure or NULL
3237  *
3238  * query the HMC profile of the device.
3239  **/
3240 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3241                                 enum i40e_aq_hmc_profile *profile,
3242                                 u8 *pe_vf_enabled_count,
3243                                 struct i40e_asq_cmd_details *cmd_details)
3244 {
3245         struct i40e_aq_desc desc;
3246         struct i40e_aq_get_set_hmc_resource_profile *resp =
3247                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3248         enum i40e_status_code status;
3249
3250         i40e_fill_default_direct_cmd_desc(&desc,
3251                                 i40e_aqc_opc_query_hmc_resource_profile);
3252         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3253
3254         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3255                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3256         *pe_vf_enabled_count = resp->pe_vf_enabled &
3257                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3258
3259         return status;
3260 }
3261
3262 /**
3263  * i40e_aq_set_hmc_resource_profile
3264  * @hw: pointer to the hw struct
3265  * @profile: type of profile the HMC is to be set as
3266  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3267  * @cmd_details: pointer to command details structure or NULL
3268  *
3269  * set the HMC profile of the device.
3270  **/
3271 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3272                                 enum i40e_aq_hmc_profile profile,
3273                                 u8 pe_vf_enabled_count,
3274                                 struct i40e_asq_cmd_details *cmd_details)
3275 {
3276         struct i40e_aq_desc desc;
3277         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3278                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3279         enum i40e_status_code status;
3280
3281         i40e_fill_default_direct_cmd_desc(&desc,
3282                                         i40e_aqc_opc_set_hmc_resource_profile);
3283
3284         cmd->pm_profile = (u8)profile;
3285         cmd->pe_vf_enabled = pe_vf_enabled_count;
3286
3287         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3288
3289         return status;
3290 }
3291
3292 /**
3293  * i40e_aq_request_resource
3294  * @hw: pointer to the hw struct
3295  * @resource: resource id
3296  * @access: access type
3297  * @sdp_number: resource number
3298  * @timeout: the maximum time in ms that the driver may hold the resource
3299  * @cmd_details: pointer to command details structure or NULL
3300  *
3301  * requests common resource using the admin queue commands
3302  **/
3303 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3304                                 enum i40e_aq_resources_ids resource,
3305                                 enum i40e_aq_resource_access_type access,
3306                                 u8 sdp_number, u64 *timeout,
3307                                 struct i40e_asq_cmd_details *cmd_details)
3308 {
3309         struct i40e_aq_desc desc;
3310         struct i40e_aqc_request_resource *cmd_resp =
3311                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3312         enum i40e_status_code status;
3313
3314         DEBUGFUNC("i40e_aq_request_resource");
3315
3316         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3317
3318         cmd_resp->resource_id = CPU_TO_LE16(resource);
3319         cmd_resp->access_type = CPU_TO_LE16(access);
3320         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3321
3322         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3323         /* The completion specifies the maximum time in ms that the driver
3324          * may hold the resource in the Timeout field.
3325          * If the resource is held by someone else, the command completes with
3326          * busy return value and the timeout field indicates the maximum time
3327          * the current owner of the resource has to free it.
3328          */
3329         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3330                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3331
3332         return status;
3333 }
3334
3335 /**
3336  * i40e_aq_release_resource
3337  * @hw: pointer to the hw struct
3338  * @resource: resource id
3339  * @sdp_number: resource number
3340  * @cmd_details: pointer to command details structure or NULL
3341  *
3342  * release common resource using the admin queue commands
3343  **/
3344 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3345                                 enum i40e_aq_resources_ids resource,
3346                                 u8 sdp_number,
3347                                 struct i40e_asq_cmd_details *cmd_details)
3348 {
3349         struct i40e_aq_desc desc;
3350         struct i40e_aqc_request_resource *cmd =
3351                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3352         enum i40e_status_code status;
3353
3354         DEBUGFUNC("i40e_aq_release_resource");
3355
3356         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3357
3358         cmd->resource_id = CPU_TO_LE16(resource);
3359         cmd->resource_number = CPU_TO_LE32(sdp_number);
3360
3361         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3362
3363         return status;
3364 }
3365
3366 /**
3367  * i40e_aq_read_nvm
3368  * @hw: pointer to the hw struct
3369  * @module_pointer: module pointer location in words from the NVM beginning
3370  * @offset: byte offset from the module beginning
3371  * @length: length of the section to be read (in bytes from the offset)
3372  * @data: command buffer (size [bytes] = length)
3373  * @last_command: tells if this is the last command in a series
3374  * @cmd_details: pointer to command details structure or NULL
3375  *
3376  * Read the NVM using the admin queue commands
3377  **/
3378 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3379                                 u32 offset, u16 length, void *data,
3380                                 bool last_command,
3381                                 struct i40e_asq_cmd_details *cmd_details)
3382 {
3383         struct i40e_aq_desc desc;
3384         struct i40e_aqc_nvm_update *cmd =
3385                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3386         enum i40e_status_code status;
3387
3388         DEBUGFUNC("i40e_aq_read_nvm");
3389
3390         /* In offset the highest byte must be zeroed. */
3391         if (offset & 0xFF000000) {
3392                 status = I40E_ERR_PARAM;
3393                 goto i40e_aq_read_nvm_exit;
3394         }
3395
3396         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3397
3398         /* If this is the last command in a series, set the proper flag. */
3399         if (last_command)
3400                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3401         cmd->module_pointer = module_pointer;
3402         cmd->offset = CPU_TO_LE32(offset);
3403         cmd->length = CPU_TO_LE16(length);
3404
3405         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3406         if (length > I40E_AQ_LARGE_BUF)
3407                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3408
3409         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3410
3411 i40e_aq_read_nvm_exit:
3412         return status;
3413 }
3414
3415 /**
3416  * i40e_aq_read_nvm_config - read an nvm config block
3417  * @hw: pointer to the hw struct
3418  * @cmd_flags: NVM access admin command bits
3419  * @field_id: field or feature id
3420  * @data: buffer for result
3421  * @buf_size: buffer size
3422  * @element_count: pointer to count of elements read by FW
3423  * @cmd_details: pointer to command details structure or NULL
3424  **/
3425 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3426                                 u8 cmd_flags, u32 field_id, void *data,
3427                                 u16 buf_size, u16 *element_count,
3428                                 struct i40e_asq_cmd_details *cmd_details)
3429 {
3430         struct i40e_aq_desc desc;
3431         struct i40e_aqc_nvm_config_read *cmd =
3432                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3433         enum i40e_status_code status;
3434
3435         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3436         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3437         if (buf_size > I40E_AQ_LARGE_BUF)
3438                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3439
3440         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3441         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3442         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3443                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3444         else
3445                 cmd->element_id_msw = 0;
3446
3447         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3448
3449         if (!status && element_count)
3450                 *element_count = LE16_TO_CPU(cmd->element_count);
3451
3452         return status;
3453 }
3454
3455 /**
3456  * i40e_aq_write_nvm_config - write an nvm config block
3457  * @hw: pointer to the hw struct
3458  * @cmd_flags: NVM access admin command bits
3459  * @data: buffer for result
3460  * @buf_size: buffer size
3461  * @element_count: count of elements to be written
3462  * @cmd_details: pointer to command details structure or NULL
3463  **/
3464 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3465                                 u8 cmd_flags, void *data, u16 buf_size,
3466                                 u16 element_count,
3467                                 struct i40e_asq_cmd_details *cmd_details)
3468 {
3469         struct i40e_aq_desc desc;
3470         struct i40e_aqc_nvm_config_write *cmd =
3471                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3472         enum i40e_status_code status;
3473
3474         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3475         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3476         if (buf_size > I40E_AQ_LARGE_BUF)
3477                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3478
3479         cmd->element_count = CPU_TO_LE16(element_count);
3480         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3481         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3482
3483         return status;
3484 }
3485
3486 /**
3487  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3488  * @hw: pointer to the hw struct
3489  * @cmd_details: pointer to command details structure or NULL
3490  **/
3491 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3492                                 void *buff, u16 buff_size,
3493                                 struct i40e_asq_cmd_details *cmd_details)
3494 {
3495         struct i40e_aq_desc desc;
3496         enum i40e_status_code status;
3497
3498         UNREFERENCED_2PARAMETER(buff, buff_size);
3499
3500         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3501         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3502         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3503                 status = I40E_ERR_NOT_IMPLEMENTED;
3504
3505         return status;
3506 }
3507
3508 /**
3509  * i40e_aq_erase_nvm
3510  * @hw: pointer to the hw struct
3511  * @module_pointer: module pointer location in words from the NVM beginning
3512  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3513  * @length: length of the section to be erased (expressed in 4 KB)
3514  * @last_command: tells if this is the last command in a series
3515  * @cmd_details: pointer to command details structure or NULL
3516  *
3517  * Erase the NVM sector using the admin queue commands
3518  **/
3519 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3520                                 u32 offset, u16 length, bool last_command,
3521                                 struct i40e_asq_cmd_details *cmd_details)
3522 {
3523         struct i40e_aq_desc desc;
3524         struct i40e_aqc_nvm_update *cmd =
3525                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3526         enum i40e_status_code status;
3527
3528         DEBUGFUNC("i40e_aq_erase_nvm");
3529
3530         /* In offset the highest byte must be zeroed. */
3531         if (offset & 0xFF000000) {
3532                 status = I40E_ERR_PARAM;
3533                 goto i40e_aq_erase_nvm_exit;
3534         }
3535
3536         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3537
3538         /* If this is the last command in a series, set the proper flag. */
3539         if (last_command)
3540                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3541         cmd->module_pointer = module_pointer;
3542         cmd->offset = CPU_TO_LE32(offset);
3543         cmd->length = CPU_TO_LE16(length);
3544
3545         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3546
3547 i40e_aq_erase_nvm_exit:
3548         return status;
3549 }
3550
3551 /**
3552  * i40e_parse_discover_capabilities
3553  * @hw: pointer to the hw struct
3554  * @buff: pointer to a buffer containing device/function capability records
3555  * @cap_count: number of capability records in the list
3556  * @list_type_opc: type of capabilities list to parse
3557  *
3558  * Parse the device/function capabilities list.
3559  **/
3560 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3561                                      u32 cap_count,
3562                                      enum i40e_admin_queue_opc list_type_opc)
3563 {
3564         struct i40e_aqc_list_capabilities_element_resp *cap;
3565         u32 valid_functions, num_functions;
3566         u32 number, logical_id, phys_id;
3567         struct i40e_hw_capabilities *p;
3568         u8 major_rev;
3569         u32 i = 0;
3570         u16 id;
3571
3572         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3573
3574         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3575                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3576         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3577                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3578         else
3579                 return;
3580
3581         for (i = 0; i < cap_count; i++, cap++) {
3582                 id = LE16_TO_CPU(cap->id);
3583                 number = LE32_TO_CPU(cap->number);
3584                 logical_id = LE32_TO_CPU(cap->logical_id);
3585                 phys_id = LE32_TO_CPU(cap->phys_id);
3586                 major_rev = cap->major_rev;
3587
3588                 switch (id) {
3589                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3590                         p->switch_mode = number;
3591                         i40e_debug(hw, I40E_DEBUG_INIT,
3592                                    "HW Capability: Switch mode = %d\n",
3593                                    p->switch_mode);
3594                         break;
3595                 case I40E_AQ_CAP_ID_MNG_MODE:
3596                         p->management_mode = number;
3597                         i40e_debug(hw, I40E_DEBUG_INIT,
3598                                    "HW Capability: Management Mode = %d\n",
3599                                    p->management_mode);
3600                         break;
3601                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3602                         p->npar_enable = number;
3603                         i40e_debug(hw, I40E_DEBUG_INIT,
3604                                    "HW Capability: NPAR enable = %d\n",
3605                                    p->npar_enable);
3606                         break;
3607                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3608                         p->os2bmc = number;
3609                         i40e_debug(hw, I40E_DEBUG_INIT,
3610                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3611                         break;
3612                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3613                         p->valid_functions = number;
3614                         i40e_debug(hw, I40E_DEBUG_INIT,
3615                                    "HW Capability: Valid Functions = %d\n",
3616                                    p->valid_functions);
3617                         break;
3618                 case I40E_AQ_CAP_ID_SRIOV:
3619                         if (number == 1)
3620                                 p->sr_iov_1_1 = true;
3621                         i40e_debug(hw, I40E_DEBUG_INIT,
3622                                    "HW Capability: SR-IOV = %d\n",
3623                                    p->sr_iov_1_1);
3624                         break;
3625                 case I40E_AQ_CAP_ID_VF:
3626                         p->num_vfs = number;
3627                         p->vf_base_id = logical_id;
3628                         i40e_debug(hw, I40E_DEBUG_INIT,
3629                                    "HW Capability: VF count = %d\n",
3630                                    p->num_vfs);
3631                         i40e_debug(hw, I40E_DEBUG_INIT,
3632                                    "HW Capability: VF base_id = %d\n",
3633                                    p->vf_base_id);
3634                         break;
3635                 case I40E_AQ_CAP_ID_VMDQ:
3636                         if (number == 1)
3637                                 p->vmdq = true;
3638                         i40e_debug(hw, I40E_DEBUG_INIT,
3639                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3640                         break;
3641                 case I40E_AQ_CAP_ID_8021QBG:
3642                         if (number == 1)
3643                                 p->evb_802_1_qbg = true;
3644                         i40e_debug(hw, I40E_DEBUG_INIT,
3645                                    "HW Capability: 802.1Qbg = %d\n", number);
3646                         break;
3647                 case I40E_AQ_CAP_ID_8021QBR:
3648                         if (number == 1)
3649                                 p->evb_802_1_qbh = true;
3650                         i40e_debug(hw, I40E_DEBUG_INIT,
3651                                    "HW Capability: 802.1Qbh = %d\n", number);
3652                         break;
3653                 case I40E_AQ_CAP_ID_VSI:
3654                         p->num_vsis = number;
3655                         i40e_debug(hw, I40E_DEBUG_INIT,
3656                                    "HW Capability: VSI count = %d\n",
3657                                    p->num_vsis);
3658                         break;
3659                 case I40E_AQ_CAP_ID_DCB:
3660                         if (number == 1) {
3661                                 p->dcb = true;
3662                                 p->enabled_tcmap = logical_id;
3663                                 p->maxtc = phys_id;
3664                         }
3665                         i40e_debug(hw, I40E_DEBUG_INIT,
3666                                    "HW Capability: DCB = %d\n", p->dcb);
3667                         i40e_debug(hw, I40E_DEBUG_INIT,
3668                                    "HW Capability: TC Mapping = %d\n",
3669                                    logical_id);
3670                         i40e_debug(hw, I40E_DEBUG_INIT,
3671                                    "HW Capability: TC Max = %d\n", p->maxtc);
3672                         break;
3673                 case I40E_AQ_CAP_ID_FCOE:
3674                         if (number == 1)
3675                                 p->fcoe = true;
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: FCOE = %d\n", p->fcoe);
3678                         break;
3679                 case I40E_AQ_CAP_ID_ISCSI:
3680                         if (number == 1)
3681                                 p->iscsi = true;
3682                         i40e_debug(hw, I40E_DEBUG_INIT,
3683                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3684                         break;
3685                 case I40E_AQ_CAP_ID_RSS:
3686                         p->rss = true;
3687                         p->rss_table_size = number;
3688                         p->rss_table_entry_width = logical_id;
3689                         i40e_debug(hw, I40E_DEBUG_INIT,
3690                                    "HW Capability: RSS = %d\n", p->rss);
3691                         i40e_debug(hw, I40E_DEBUG_INIT,
3692                                    "HW Capability: RSS table size = %d\n",
3693                                    p->rss_table_size);
3694                         i40e_debug(hw, I40E_DEBUG_INIT,
3695                                    "HW Capability: RSS table width = %d\n",
3696                                    p->rss_table_entry_width);
3697                         break;
3698                 case I40E_AQ_CAP_ID_RXQ:
3699                         p->num_rx_qp = number;
3700                         p->base_queue = phys_id;
3701                         i40e_debug(hw, I40E_DEBUG_INIT,
3702                                    "HW Capability: Rx QP = %d\n", number);
3703                         i40e_debug(hw, I40E_DEBUG_INIT,
3704                                    "HW Capability: base_queue = %d\n",
3705                                    p->base_queue);
3706                         break;
3707                 case I40E_AQ_CAP_ID_TXQ:
3708                         p->num_tx_qp = number;
3709                         p->base_queue = phys_id;
3710                         i40e_debug(hw, I40E_DEBUG_INIT,
3711                                    "HW Capability: Tx QP = %d\n", number);
3712                         i40e_debug(hw, I40E_DEBUG_INIT,
3713                                    "HW Capability: base_queue = %d\n",
3714                                    p->base_queue);
3715                         break;
3716                 case I40E_AQ_CAP_ID_MSIX:
3717                         p->num_msix_vectors = number;
3718                         i40e_debug(hw, I40E_DEBUG_INIT,
3719                                    "HW Capability: MSIX vector count = %d\n",
3720                                    p->num_msix_vectors_vf);
3721                         break;
3722                 case I40E_AQ_CAP_ID_VF_MSIX:
3723                         p->num_msix_vectors_vf = number;
3724                         i40e_debug(hw, I40E_DEBUG_INIT,
3725                                    "HW Capability: MSIX VF vector count = %d\n",
3726                                    p->num_msix_vectors_vf);
3727                         break;
3728                 case I40E_AQ_CAP_ID_FLEX10:
3729                         if (major_rev == 1) {
3730                                 if (number == 1) {
3731                                         p->flex10_enable = true;
3732                                         p->flex10_capable = true;
3733                                 }
3734                         } else {
3735                                 /* Capability revision >= 2 */
3736                                 if (number & 1)
3737                                         p->flex10_enable = true;
3738                                 if (number & 2)
3739                                         p->flex10_capable = true;
3740                         }
3741                         p->flex10_mode = logical_id;
3742                         p->flex10_status = phys_id;
3743                         i40e_debug(hw, I40E_DEBUG_INIT,
3744                                    "HW Capability: Flex10 mode = %d\n",
3745                                    p->flex10_mode);
3746                         i40e_debug(hw, I40E_DEBUG_INIT,
3747                                    "HW Capability: Flex10 status = %d\n",
3748                                    p->flex10_status);
3749                         break;
3750                 case I40E_AQ_CAP_ID_CEM:
3751                         if (number == 1)
3752                                 p->mgmt_cem = true;
3753                         i40e_debug(hw, I40E_DEBUG_INIT,
3754                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3755                         break;
3756                 case I40E_AQ_CAP_ID_IWARP:
3757                         if (number == 1)
3758                                 p->iwarp = true;
3759                         i40e_debug(hw, I40E_DEBUG_INIT,
3760                                    "HW Capability: iWARP = %d\n", p->iwarp);
3761                         break;
3762                 case I40E_AQ_CAP_ID_LED:
3763                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3764                                 p->led[phys_id] = true;
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: LED - PIN %d\n", phys_id);
3767                         break;
3768                 case I40E_AQ_CAP_ID_SDP:
3769                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3770                                 p->sdp[phys_id] = true;
3771                         i40e_debug(hw, I40E_DEBUG_INIT,
3772                                    "HW Capability: SDP - PIN %d\n", phys_id);
3773                         break;
3774                 case I40E_AQ_CAP_ID_MDIO:
3775                         if (number == 1) {
3776                                 p->mdio_port_num = phys_id;
3777                                 p->mdio_port_mode = logical_id;
3778                         }
3779                         i40e_debug(hw, I40E_DEBUG_INIT,
3780                                    "HW Capability: MDIO port number = %d\n",
3781                                    p->mdio_port_num);
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: MDIO port mode = %d\n",
3784                                    p->mdio_port_mode);
3785                         break;
3786                 case I40E_AQ_CAP_ID_1588:
3787                         if (number == 1)
3788                                 p->ieee_1588 = true;
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: IEEE 1588 = %d\n",
3791                                    p->ieee_1588);
3792                         break;
3793                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3794                         p->fd = true;
3795                         p->fd_filters_guaranteed = number;
3796                         p->fd_filters_best_effort = logical_id;
3797                         i40e_debug(hw, I40E_DEBUG_INIT,
3798                                    "HW Capability: Flow Director = 1\n");
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: Guaranteed FD filters = %d\n",
3801                                    p->fd_filters_guaranteed);
3802                         break;
3803                 case I40E_AQ_CAP_ID_WSR_PROT:
3804                         p->wr_csr_prot = (u64)number;
3805                         p->wr_csr_prot |= (u64)logical_id << 32;
3806                         i40e_debug(hw, I40E_DEBUG_INIT,
3807                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3808                                    (p->wr_csr_prot & 0xffff));
3809                         break;
3810 #ifdef X722_SUPPORT
3811                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3812                         hw->num_wol_proxy_filters = (u16)number;
3813                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3814                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3815                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3816                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3817                         else
3818                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3819                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3820                         p->proxy_support = p->proxy_support;
3821                         i40e_debug(hw, I40E_DEBUG_INIT,
3822                                    "HW Capability: WOL proxy filters = %d\n",
3823                                    hw->num_wol_proxy_filters);
3824                         break;
3825 #endif
3826                 default:
3827                         break;
3828                 }
3829         }
3830
3831         if (p->fcoe)
3832                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3833
3834 #ifdef I40E_FCOE_ENA
3835         /* Software override ensuring FCoE is disabled if npar or mfp
3836          * mode because it is not supported in these modes.
3837          */
3838         if (p->npar_enable || p->flex10_enable)
3839                 p->fcoe = false;
3840 #else
3841         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3842         p->fcoe = false;
3843 #endif
3844
3845         /* count the enabled ports (aka the "not disabled" ports) */
3846         hw->num_ports = 0;
3847         for (i = 0; i < 4; i++) {
3848                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3849                 u64 port_cfg = 0;
3850
3851                 /* use AQ read to get the physical register offset instead
3852                  * of the port relative offset
3853                  */
3854                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3855                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3856                         hw->num_ports++;
3857         }
3858
3859         valid_functions = p->valid_functions;
3860         num_functions = 0;
3861         while (valid_functions) {
3862                 if (valid_functions & 1)
3863                         num_functions++;
3864                 valid_functions >>= 1;
3865         }
3866
3867         /* partition id is 1-based, and functions are evenly spread
3868          * across the ports as partitions
3869          */
3870         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3871         hw->num_partitions = num_functions / hw->num_ports;
3872
3873         /* additional HW specific goodies that might
3874          * someday be HW version specific
3875          */
3876         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3877 }
3878
3879 /**
3880  * i40e_aq_discover_capabilities
3881  * @hw: pointer to the hw struct
3882  * @buff: a virtual buffer to hold the capabilities
3883  * @buff_size: Size of the virtual buffer
3884  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3885  * @list_type_opc: capabilities type to discover - pass in the command opcode
3886  * @cmd_details: pointer to command details structure or NULL
3887  *
3888  * Get the device capabilities descriptions from the firmware
3889  **/
3890 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3891                                 void *buff, u16 buff_size, u16 *data_size,
3892                                 enum i40e_admin_queue_opc list_type_opc,
3893                                 struct i40e_asq_cmd_details *cmd_details)
3894 {
3895         struct i40e_aqc_list_capabilites *cmd;
3896         struct i40e_aq_desc desc;
3897         enum i40e_status_code status = I40E_SUCCESS;
3898
3899         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3900
3901         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3902                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3903                 status = I40E_ERR_PARAM;
3904                 goto exit;
3905         }
3906
3907         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3908
3909         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3910         if (buff_size > I40E_AQ_LARGE_BUF)
3911                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3912
3913         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3914         *data_size = LE16_TO_CPU(desc.datalen);
3915
3916         if (status)
3917                 goto exit;
3918
3919         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3920                                          list_type_opc);
3921
3922 exit:
3923         return status;
3924 }
3925
3926 /**
3927  * i40e_aq_update_nvm
3928  * @hw: pointer to the hw struct
3929  * @module_pointer: module pointer location in words from the NVM beginning
3930  * @offset: byte offset from the module beginning
3931  * @length: length of the section to be written (in bytes from the offset)
3932  * @data: command buffer (size [bytes] = length)
3933  * @last_command: tells if this is the last command in a series
3934  * @cmd_details: pointer to command details structure or NULL
3935  *
3936  * Update the NVM using the admin queue commands
3937  **/
3938 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3939                                 u32 offset, u16 length, void *data,
3940                                 bool last_command,
3941                                 struct i40e_asq_cmd_details *cmd_details)
3942 {
3943         struct i40e_aq_desc desc;
3944         struct i40e_aqc_nvm_update *cmd =
3945                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3946         enum i40e_status_code status;
3947
3948         DEBUGFUNC("i40e_aq_update_nvm");
3949
3950         /* In offset the highest byte must be zeroed. */
3951         if (offset & 0xFF000000) {
3952                 status = I40E_ERR_PARAM;
3953                 goto i40e_aq_update_nvm_exit;
3954         }
3955
3956         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3957
3958         /* If this is the last command in a series, set the proper flag. */
3959         if (last_command)
3960                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3961         cmd->module_pointer = module_pointer;
3962         cmd->offset = CPU_TO_LE32(offset);
3963         cmd->length = CPU_TO_LE16(length);
3964
3965         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3966         if (length > I40E_AQ_LARGE_BUF)
3967                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3968
3969         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3970
3971 i40e_aq_update_nvm_exit:
3972         return status;
3973 }
3974
3975 /**
3976  * i40e_aq_get_lldp_mib
3977  * @hw: pointer to the hw struct
3978  * @bridge_type: type of bridge requested
3979  * @mib_type: Local, Remote or both Local and Remote MIBs
3980  * @buff: pointer to a user supplied buffer to store the MIB block
3981  * @buff_size: size of the buffer (in bytes)
3982  * @local_len : length of the returned Local LLDP MIB
3983  * @remote_len: length of the returned Remote LLDP MIB
3984  * @cmd_details: pointer to command details structure or NULL
3985  *
3986  * Requests the complete LLDP MIB (entire packet).
3987  **/
3988 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3989                                 u8 mib_type, void *buff, u16 buff_size,
3990                                 u16 *local_len, u16 *remote_len,
3991                                 struct i40e_asq_cmd_details *cmd_details)
3992 {
3993         struct i40e_aq_desc desc;
3994         struct i40e_aqc_lldp_get_mib *cmd =
3995                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3996         struct i40e_aqc_lldp_get_mib *resp =
3997                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3998         enum i40e_status_code status;
3999
4000         if (buff_size == 0 || !buff)
4001                 return I40E_ERR_PARAM;
4002
4003         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4004         /* Indirect Command */
4005         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4006
4007         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4008         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4009                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4010
4011         desc.datalen = CPU_TO_LE16(buff_size);
4012
4013         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4014         if (buff_size > I40E_AQ_LARGE_BUF)
4015                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4016
4017         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4018         if (!status) {
4019                 if (local_len != NULL)
4020                         *local_len = LE16_TO_CPU(resp->local_len);
4021                 if (remote_len != NULL)
4022                         *remote_len = LE16_TO_CPU(resp->remote_len);
4023         }
4024
4025         return status;
4026 }
4027
4028  /**
4029  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4030  * @hw: pointer to the hw struct
4031  * @mib_type: Local, Remote or both Local and Remote MIBs
4032  * @buff: pointer to a user supplied buffer to store the MIB block
4033  * @buff_size: size of the buffer (in bytes)
4034  * @cmd_details: pointer to command details structure or NULL
4035  *
4036  * Set the LLDP MIB.
4037  **/
4038 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4039                                 u8 mib_type, void *buff, u16 buff_size,
4040                                 struct i40e_asq_cmd_details *cmd_details)
4041 {
4042         struct i40e_aq_desc desc;
4043         struct i40e_aqc_lldp_set_local_mib *cmd =
4044                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4045         enum i40e_status_code status;
4046
4047         if (buff_size == 0 || !buff)
4048                 return I40E_ERR_PARAM;
4049
4050         i40e_fill_default_direct_cmd_desc(&desc,
4051                                 i40e_aqc_opc_lldp_set_local_mib);
4052         /* Indirect Command */
4053         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4054         if (buff_size > I40E_AQ_LARGE_BUF)
4055                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4056         desc.datalen = CPU_TO_LE16(buff_size);
4057
4058         cmd->type = mib_type;
4059         cmd->length = CPU_TO_LE16(buff_size);
4060         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4061         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4062
4063         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4064         return status;
4065 }
4066
4067 /**
4068  * i40e_aq_cfg_lldp_mib_change_event
4069  * @hw: pointer to the hw struct
4070  * @enable_update: Enable or Disable event posting
4071  * @cmd_details: pointer to command details structure or NULL
4072  *
4073  * Enable or Disable posting of an event on ARQ when LLDP MIB
4074  * associated with the interface changes
4075  **/
4076 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4077                                 bool enable_update,
4078                                 struct i40e_asq_cmd_details *cmd_details)
4079 {
4080         struct i40e_aq_desc desc;
4081         struct i40e_aqc_lldp_update_mib *cmd =
4082                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4083         enum i40e_status_code status;
4084
4085         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4086
4087         if (!enable_update)
4088                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4089
4090         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4091
4092         return status;
4093 }
4094
4095 /**
4096  * i40e_aq_add_lldp_tlv
4097  * @hw: pointer to the hw struct
4098  * @bridge_type: type of bridge
4099  * @buff: buffer with TLV to add
4100  * @buff_size: length of the buffer
4101  * @tlv_len: length of the TLV to be added
4102  * @mib_len: length of the LLDP MIB returned in response
4103  * @cmd_details: pointer to command details structure or NULL
4104  *
4105  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4106  * it is responsibility of the caller to make sure that the TLV is not
4107  * already present in the LLDPDU.
4108  * In return firmware will write the complete LLDP MIB with the newly
4109  * added TLV in the response buffer.
4110  **/
4111 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4112                                 void *buff, u16 buff_size, u16 tlv_len,
4113                                 u16 *mib_len,
4114                                 struct i40e_asq_cmd_details *cmd_details)
4115 {
4116         struct i40e_aq_desc desc;
4117         struct i40e_aqc_lldp_add_tlv *cmd =
4118                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4119         enum i40e_status_code status;
4120
4121         if (buff_size == 0 || !buff || tlv_len == 0)
4122                 return I40E_ERR_PARAM;
4123
4124         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4125
4126         /* Indirect Command */
4127         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4128         if (buff_size > I40E_AQ_LARGE_BUF)
4129                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4130         desc.datalen = CPU_TO_LE16(buff_size);
4131
4132         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4133                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4134         cmd->len = CPU_TO_LE16(tlv_len);
4135
4136         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4137         if (!status) {
4138                 if (mib_len != NULL)
4139                         *mib_len = LE16_TO_CPU(desc.datalen);
4140         }
4141
4142         return status;
4143 }
4144
4145 /**
4146  * i40e_aq_update_lldp_tlv
4147  * @hw: pointer to the hw struct
4148  * @bridge_type: type of bridge
4149  * @buff: buffer with TLV to update
4150  * @buff_size: size of the buffer holding original and updated TLVs
4151  * @old_len: Length of the Original TLV
4152  * @new_len: Length of the Updated TLV
4153  * @offset: offset of the updated TLV in the buff
4154  * @mib_len: length of the returned LLDP MIB
4155  * @cmd_details: pointer to command details structure or NULL
4156  *
4157  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4158  * Firmware will place the complete LLDP MIB in response buffer with the
4159  * updated TLV.
4160  **/
4161 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4162                                 u8 bridge_type, void *buff, u16 buff_size,
4163                                 u16 old_len, u16 new_len, u16 offset,
4164                                 u16 *mib_len,
4165                                 struct i40e_asq_cmd_details *cmd_details)
4166 {
4167         struct i40e_aq_desc desc;
4168         struct i40e_aqc_lldp_update_tlv *cmd =
4169                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4170         enum i40e_status_code status;
4171
4172         if (buff_size == 0 || !buff || offset == 0 ||
4173             old_len == 0 || new_len == 0)
4174                 return I40E_ERR_PARAM;
4175
4176         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4177
4178         /* Indirect Command */
4179         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4180         if (buff_size > I40E_AQ_LARGE_BUF)
4181                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4182         desc.datalen = CPU_TO_LE16(buff_size);
4183
4184         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4185                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4186         cmd->old_len = CPU_TO_LE16(old_len);
4187         cmd->new_offset = CPU_TO_LE16(offset);
4188         cmd->new_len = CPU_TO_LE16(new_len);
4189
4190         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4191         if (!status) {
4192                 if (mib_len != NULL)
4193                         *mib_len = LE16_TO_CPU(desc.datalen);
4194         }
4195
4196         return status;
4197 }
4198
4199 /**
4200  * i40e_aq_delete_lldp_tlv
4201  * @hw: pointer to the hw struct
4202  * @bridge_type: type of bridge
4203  * @buff: pointer to a user supplied buffer that has the TLV
4204  * @buff_size: length of the buffer
4205  * @tlv_len: length of the TLV to be deleted
4206  * @mib_len: length of the returned LLDP MIB
4207  * @cmd_details: pointer to command details structure or NULL
4208  *
4209  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4210  * The firmware places the entire LLDP MIB in the response buffer.
4211  **/
4212 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4213                                 u8 bridge_type, void *buff, u16 buff_size,
4214                                 u16 tlv_len, u16 *mib_len,
4215                                 struct i40e_asq_cmd_details *cmd_details)
4216 {
4217         struct i40e_aq_desc desc;
4218         struct i40e_aqc_lldp_add_tlv *cmd =
4219                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4220         enum i40e_status_code status;
4221
4222         if (buff_size == 0 || !buff)
4223                 return I40E_ERR_PARAM;
4224
4225         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4226
4227         /* Indirect Command */
4228         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4229         if (buff_size > I40E_AQ_LARGE_BUF)
4230                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4231         desc.datalen = CPU_TO_LE16(buff_size);
4232         cmd->len = CPU_TO_LE16(tlv_len);
4233         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4234                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4235
4236         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4237         if (!status) {
4238                 if (mib_len != NULL)
4239                         *mib_len = LE16_TO_CPU(desc.datalen);
4240         }
4241
4242         return status;
4243 }
4244
4245 /**
4246  * i40e_aq_stop_lldp
4247  * @hw: pointer to the hw struct
4248  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4249  * @cmd_details: pointer to command details structure or NULL
4250  *
4251  * Stop or Shutdown the embedded LLDP Agent
4252  **/
4253 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4254                                 struct i40e_asq_cmd_details *cmd_details)
4255 {
4256         struct i40e_aq_desc desc;
4257         struct i40e_aqc_lldp_stop *cmd =
4258                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4259         enum i40e_status_code status;
4260
4261         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4262
4263         if (shutdown_agent)
4264                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4265
4266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4267
4268         return status;
4269 }
4270
4271 /**
4272  * i40e_aq_start_lldp
4273  * @hw: pointer to the hw struct
4274  * @cmd_details: pointer to command details structure or NULL
4275  *
4276  * Start the embedded LLDP Agent on all ports.
4277  **/
4278 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4279                                 struct i40e_asq_cmd_details *cmd_details)
4280 {
4281         struct i40e_aq_desc desc;
4282         struct i40e_aqc_lldp_start *cmd =
4283                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4284         enum i40e_status_code status;
4285
4286         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4287
4288         cmd->command = I40E_AQ_LLDP_AGENT_START;
4289
4290         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4291
4292         return status;
4293 }
4294
4295 /**
4296  * i40e_aq_get_cee_dcb_config
4297  * @hw: pointer to the hw struct
4298  * @buff: response buffer that stores CEE operational configuration
4299  * @buff_size: size of the buffer passed
4300  * @cmd_details: pointer to command details structure or NULL
4301  *
4302  * Get CEE DCBX mode operational configuration from firmware
4303  **/
4304 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4305                                 void *buff, u16 buff_size,
4306                                 struct i40e_asq_cmd_details *cmd_details)
4307 {
4308         struct i40e_aq_desc desc;
4309         enum i40e_status_code status;
4310
4311         if (buff_size == 0 || !buff)
4312                 return I40E_ERR_PARAM;
4313
4314         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4315
4316         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4317         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4318                                        cmd_details);
4319
4320         return status;
4321 }
4322
4323 /**
4324  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4325  * @hw: pointer to the hw struct
4326  * @start_agent: True if DCBx Agent needs to be Started
4327  *                              False if DCBx Agent needs to be Stopped
4328  * @cmd_details: pointer to command details structure or NULL
4329  *
4330  * Start/Stop the embedded dcbx Agent
4331  **/
4332 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4333                                 bool start_agent,
4334                                 struct i40e_asq_cmd_details *cmd_details)
4335 {
4336         struct i40e_aq_desc desc;
4337         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4338                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4339                                 &desc.params.raw;
4340         enum i40e_status_code status;
4341
4342         i40e_fill_default_direct_cmd_desc(&desc,
4343                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4344
4345         if (start_agent)
4346                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4347
4348         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4349
4350         return status;
4351 }
4352
4353 /**
4354  * i40e_aq_add_udp_tunnel
4355  * @hw: pointer to the hw struct
4356  * @udp_port: the UDP port to add
4357  * @header_len: length of the tunneling header length in DWords
4358  * @protocol_index: protocol index type
4359  * @filter_index: pointer to filter index
4360  * @cmd_details: pointer to command details structure or NULL
4361  **/
4362 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4363                                 u16 udp_port, u8 protocol_index,
4364                                 u8 *filter_index,
4365                                 struct i40e_asq_cmd_details *cmd_details)
4366 {
4367         struct i40e_aq_desc desc;
4368         struct i40e_aqc_add_udp_tunnel *cmd =
4369                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4370         struct i40e_aqc_del_udp_tunnel_completion *resp =
4371                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4372         enum i40e_status_code status;
4373
4374         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4375
4376         cmd->udp_port = CPU_TO_LE16(udp_port);
4377         cmd->protocol_type = protocol_index;
4378
4379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4380
4381         if (!status && filter_index)
4382                 *filter_index = resp->index;
4383
4384         return status;
4385 }
4386
4387 /**
4388  * i40e_aq_del_udp_tunnel
4389  * @hw: pointer to the hw struct
4390  * @index: filter index
4391  * @cmd_details: pointer to command details structure or NULL
4392  **/
4393 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4394                                 struct i40e_asq_cmd_details *cmd_details)
4395 {
4396         struct i40e_aq_desc desc;
4397         struct i40e_aqc_remove_udp_tunnel *cmd =
4398                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4399         enum i40e_status_code status;
4400
4401         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4402
4403         cmd->index = index;
4404
4405         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4406
4407         return status;
4408 }
4409
4410 /**
4411  * i40e_aq_get_switch_resource_alloc (0x0204)
4412  * @hw: pointer to the hw struct
4413  * @num_entries: pointer to u8 to store the number of resource entries returned
4414  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4415  *        to store the resource information for all resource types.  Each
4416  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4417  * @count: size, in bytes, of the buffer provided
4418  * @cmd_details: pointer to command details structure or NULL
4419  *
4420  * Query the resources allocated to a function.
4421  **/
4422 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4423                         u8 *num_entries,
4424                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4425                         u16 count,
4426                         struct i40e_asq_cmd_details *cmd_details)
4427 {
4428         struct i40e_aq_desc desc;
4429         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4430                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4431         enum i40e_status_code status;
4432         u16 length = count * sizeof(*buf);
4433
4434         i40e_fill_default_direct_cmd_desc(&desc,
4435                                         i40e_aqc_opc_get_switch_resource_alloc);
4436
4437         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4438         if (length > I40E_AQ_LARGE_BUF)
4439                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4440
4441         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4442
4443         if (!status && num_entries)
4444                 *num_entries = cmd_resp->num_entries;
4445
4446         return status;
4447 }
4448
4449 /**
4450  * i40e_aq_delete_element - Delete switch element
4451  * @hw: pointer to the hw struct
4452  * @seid: the SEID to delete from the switch
4453  * @cmd_details: pointer to command details structure or NULL
4454  *
4455  * This deletes a switch element from the switch.
4456  **/
4457 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4458                                 struct i40e_asq_cmd_details *cmd_details)
4459 {
4460         struct i40e_aq_desc desc;
4461         struct i40e_aqc_switch_seid *cmd =
4462                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4463         enum i40e_status_code status;
4464
4465         if (seid == 0)
4466                 return I40E_ERR_PARAM;
4467
4468         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4469
4470         cmd->seid = CPU_TO_LE16(seid);
4471
4472         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4473
4474         return status;
4475 }
4476
4477 /**
4478  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4479  * @hw: pointer to the hw struct
4480  * @flags: component flags
4481  * @mac_seid: uplink seid (MAC SEID)
4482  * @vsi_seid: connected vsi seid
4483  * @ret_seid: seid of create pv component
4484  *
4485  * This instantiates an i40e port virtualizer with specified flags.
4486  * Depending on specified flags the port virtualizer can act as a
4487  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4488  */
4489 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4490                                        u16 mac_seid, u16 vsi_seid,
4491                                        u16 *ret_seid)
4492 {
4493         struct i40e_aq_desc desc;
4494         struct i40e_aqc_add_update_pv *cmd =
4495                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4496         struct i40e_aqc_add_update_pv_completion *resp =
4497                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4498         enum i40e_status_code status;
4499
4500         if (vsi_seid == 0)
4501                 return I40E_ERR_PARAM;
4502
4503         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4504         cmd->command_flags = CPU_TO_LE16(flags);
4505         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4506         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4507
4508         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4509         if (!status && ret_seid)
4510                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4511
4512         return status;
4513 }
4514
4515 /**
4516  * i40e_aq_add_tag - Add an S/E-tag
4517  * @hw: pointer to the hw struct
4518  * @direct_to_queue: should s-tag direct flow to a specific queue
4519  * @vsi_seid: VSI SEID to use this tag
4520  * @tag: value of the tag
4521  * @queue_num: queue number, only valid is direct_to_queue is true
4522  * @tags_used: return value, number of tags in use by this PF
4523  * @tags_free: return value, number of unallocated tags
4524  * @cmd_details: pointer to command details structure or NULL
4525  *
4526  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4527  * the number of tags allocated by the PF, and the number of unallocated
4528  * tags available.
4529  **/
4530 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4531                                 u16 vsi_seid, u16 tag, u16 queue_num,
4532                                 u16 *tags_used, u16 *tags_free,
4533                                 struct i40e_asq_cmd_details *cmd_details)
4534 {
4535         struct i40e_aq_desc desc;
4536         struct i40e_aqc_add_tag *cmd =
4537                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4538         struct i40e_aqc_add_remove_tag_completion *resp =
4539                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4540         enum i40e_status_code status;
4541
4542         if (vsi_seid == 0)
4543                 return I40E_ERR_PARAM;
4544
4545         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4546
4547         cmd->seid = CPU_TO_LE16(vsi_seid);
4548         cmd->tag = CPU_TO_LE16(tag);
4549         if (direct_to_queue) {
4550                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4551                 cmd->queue_number = CPU_TO_LE16(queue_num);
4552         }
4553
4554         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4555
4556         if (!status) {
4557                 if (tags_used != NULL)
4558                         *tags_used = LE16_TO_CPU(resp->tags_used);
4559                 if (tags_free != NULL)
4560                         *tags_free = LE16_TO_CPU(resp->tags_free);
4561         }
4562
4563         return status;
4564 }
4565
4566 /**
4567  * i40e_aq_remove_tag - Remove an S- or E-tag
4568  * @hw: pointer to the hw struct
4569  * @vsi_seid: VSI SEID this tag is associated with
4570  * @tag: value of the S-tag to delete
4571  * @tags_used: return value, number of tags in use by this PF
4572  * @tags_free: return value, number of unallocated tags
4573  * @cmd_details: pointer to command details structure or NULL
4574  *
4575  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4576  * the number of tags allocated by the PF, and the number of unallocated
4577  * tags available.
4578  **/
4579 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4580                                 u16 tag, u16 *tags_used, u16 *tags_free,
4581                                 struct i40e_asq_cmd_details *cmd_details)
4582 {
4583         struct i40e_aq_desc desc;
4584         struct i40e_aqc_remove_tag *cmd =
4585                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4586         struct i40e_aqc_add_remove_tag_completion *resp =
4587                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4588         enum i40e_status_code status;
4589
4590         if (vsi_seid == 0)
4591                 return I40E_ERR_PARAM;
4592
4593         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4594
4595         cmd->seid = CPU_TO_LE16(vsi_seid);
4596         cmd->tag = CPU_TO_LE16(tag);
4597
4598         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4599
4600         if (!status) {
4601                 if (tags_used != NULL)
4602                         *tags_used = LE16_TO_CPU(resp->tags_used);
4603                 if (tags_free != NULL)
4604                         *tags_free = LE16_TO_CPU(resp->tags_free);
4605         }
4606
4607         return status;
4608 }
4609
4610 /**
4611  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4612  * @hw: pointer to the hw struct
4613  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4614  * @etag: value of E-tag to add
4615  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4616  * @buf: address of indirect buffer
4617  * @tags_used: return value, number of E-tags in use by this port
4618  * @tags_free: return value, number of unallocated M-tags
4619  * @cmd_details: pointer to command details structure or NULL
4620  *
4621  * This associates a multicast E-tag to a port virtualizer.  It will return
4622  * the number of tags allocated by the PF, and the number of unallocated
4623  * tags available.
4624  *
4625  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4626  * num_tags_in_buf long.
4627  **/
4628 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4629                                 u16 etag, u8 num_tags_in_buf, void *buf,
4630                                 u16 *tags_used, u16 *tags_free,
4631                                 struct i40e_asq_cmd_details *cmd_details)
4632 {
4633         struct i40e_aq_desc desc;
4634         struct i40e_aqc_add_remove_mcast_etag *cmd =
4635                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4636         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4637            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4638         enum i40e_status_code status;
4639         u16 length = sizeof(u16) * num_tags_in_buf;
4640
4641         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4642                 return I40E_ERR_PARAM;
4643
4644         i40e_fill_default_direct_cmd_desc(&desc,
4645                                           i40e_aqc_opc_add_multicast_etag);
4646
4647         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4648         cmd->etag = CPU_TO_LE16(etag);
4649         cmd->num_unicast_etags = num_tags_in_buf;
4650
4651         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4652         if (length > I40E_AQ_LARGE_BUF)
4653                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4654
4655         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4656
4657         if (!status) {
4658                 if (tags_used != NULL)
4659                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4660                 if (tags_free != NULL)
4661                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4662         }
4663
4664         return status;
4665 }
4666
4667 /**
4668  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4669  * @hw: pointer to the hw struct
4670  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4671  * @etag: value of the E-tag to remove
4672  * @tags_used: return value, number of tags in use by this port
4673  * @tags_free: return value, number of unallocated tags
4674  * @cmd_details: pointer to command details structure or NULL
4675  *
4676  * This deletes an E-tag from the port virtualizer.  It will return
4677  * the number of tags allocated by the port, and the number of unallocated
4678  * tags available.
4679  **/
4680 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4681                                 u16 etag, u16 *tags_used, u16 *tags_free,
4682                                 struct i40e_asq_cmd_details *cmd_details)
4683 {
4684         struct i40e_aq_desc desc;
4685         struct i40e_aqc_add_remove_mcast_etag *cmd =
4686                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4687         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4688            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4689         enum i40e_status_code status;
4690
4691
4692         if (pv_seid == 0)
4693                 return I40E_ERR_PARAM;
4694
4695         i40e_fill_default_direct_cmd_desc(&desc,
4696                                           i40e_aqc_opc_remove_multicast_etag);
4697
4698         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4699         cmd->etag = CPU_TO_LE16(etag);
4700
4701         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4702
4703         if (!status) {
4704                 if (tags_used != NULL)
4705                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4706                 if (tags_free != NULL)
4707                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4708         }
4709
4710         return status;
4711 }
4712
4713 /**
4714  * i40e_aq_update_tag - Update an S/E-tag
4715  * @hw: pointer to the hw struct
4716  * @vsi_seid: VSI SEID using this S-tag
4717  * @old_tag: old tag value
4718  * @new_tag: new tag value
4719  * @tags_used: return value, number of tags in use by this PF
4720  * @tags_free: return value, number of unallocated tags
4721  * @cmd_details: pointer to command details structure or NULL
4722  *
4723  * This updates the value of the tag currently attached to this VSI
4724  * in the switch complex.  It will return the number of tags allocated
4725  * by the PF, and the number of unallocated tags available.
4726  **/
4727 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4728                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4729                                 u16 *tags_free,
4730                                 struct i40e_asq_cmd_details *cmd_details)
4731 {
4732         struct i40e_aq_desc desc;
4733         struct i40e_aqc_update_tag *cmd =
4734                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4735         struct i40e_aqc_update_tag_completion *resp =
4736                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4737         enum i40e_status_code status;
4738
4739         if (vsi_seid == 0)
4740                 return I40E_ERR_PARAM;
4741
4742         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4743
4744         cmd->seid = CPU_TO_LE16(vsi_seid);
4745         cmd->old_tag = CPU_TO_LE16(old_tag);
4746         cmd->new_tag = CPU_TO_LE16(new_tag);
4747
4748         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4749
4750         if (!status) {
4751                 if (tags_used != NULL)
4752                         *tags_used = LE16_TO_CPU(resp->tags_used);
4753                 if (tags_free != NULL)
4754                         *tags_free = LE16_TO_CPU(resp->tags_free);
4755         }
4756
4757         return status;
4758 }
4759
4760 /**
4761  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4762  * @hw: pointer to the hw struct
4763  * @tcmap: TC map for request/release any ignore PFC condition
4764  * @request: request or release ignore PFC condition
4765  * @tcmap_ret: return TCs for which PFC is currently ignored
4766  * @cmd_details: pointer to command details structure or NULL
4767  *
4768  * This sends out request/release to ignore PFC condition for a TC.
4769  * It will return the TCs for which PFC is currently ignored.
4770  **/
4771 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4772                                 bool request, u8 *tcmap_ret,
4773                                 struct i40e_asq_cmd_details *cmd_details)
4774 {
4775         struct i40e_aq_desc desc;
4776         struct i40e_aqc_pfc_ignore *cmd_resp =
4777                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4778         enum i40e_status_code status;
4779
4780         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4781
4782         if (request)
4783                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4784
4785         cmd_resp->tc_bitmap = tcmap;
4786
4787         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4788
4789         if (!status) {
4790                 if (tcmap_ret != NULL)
4791                         *tcmap_ret = cmd_resp->tc_bitmap;
4792         }
4793
4794         return status;
4795 }
4796
4797 /**
4798  * i40e_aq_dcb_updated - DCB Updated Command
4799  * @hw: pointer to the hw struct
4800  * @cmd_details: pointer to command details structure or NULL
4801  *
4802  * When LLDP is handled in PF this command is used by the PF
4803  * to notify EMP that a DCB setting is modified.
4804  * When LLDP is handled in EMP this command is used by the PF
4805  * to notify EMP whenever one of the following parameters get
4806  * modified:
4807  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4808  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4809  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4810  * EMP will return when the shared RPB settings have been
4811  * recomputed and modified. The retval field in the descriptor
4812  * will be set to 0 when RPB is modified.
4813  **/
4814 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4815                                 struct i40e_asq_cmd_details *cmd_details)
4816 {
4817         struct i40e_aq_desc desc;
4818         enum i40e_status_code status;
4819
4820         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4821
4822         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4823
4824         return status;
4825 }
4826
4827 /**
4828  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4829  * @hw: pointer to the hw struct
4830  * @seid: defines the SEID of the switch for which the stats are requested
4831  * @vlan_id: the VLAN ID for which the statistics are requested
4832  * @stat_index: index of the statistics counters block assigned to this VLAN
4833  * @cmd_details: pointer to command details structure or NULL
4834  *
4835  * XL710 supports 128 smonVlanStats counters.This command is used to
4836  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4837  * switch.
4838  **/
4839 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4840                                 u16 vlan_id, u16 *stat_index,
4841                                 struct i40e_asq_cmd_details *cmd_details)
4842 {
4843         struct i40e_aq_desc desc;
4844         struct i40e_aqc_add_remove_statistics *cmd_resp =
4845                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4846         enum i40e_status_code status;
4847
4848         if ((seid == 0) || (stat_index == NULL))
4849                 return I40E_ERR_PARAM;
4850
4851         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4852
4853         cmd_resp->seid = CPU_TO_LE16(seid);
4854         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4855
4856         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4857
4858         if (!status && stat_index)
4859                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4860
4861         return status;
4862 }
4863
4864 /**
4865  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4866  * @hw: pointer to the hw struct
4867  * @seid: defines the SEID of the switch for which the stats are requested
4868  * @vlan_id: the VLAN ID for which the statistics are requested
4869  * @stat_index: index of the statistics counters block assigned to this VLAN
4870  * @cmd_details: pointer to command details structure or NULL
4871  *
4872  * XL710 supports 128 smonVlanStats counters.This command is used to
4873  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4874  * switch.
4875  **/
4876 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4877                                 u16 vlan_id, u16 stat_index,
4878                                 struct i40e_asq_cmd_details *cmd_details)
4879 {
4880         struct i40e_aq_desc desc;
4881         struct i40e_aqc_add_remove_statistics *cmd =
4882                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4883         enum i40e_status_code status;
4884
4885         if (seid == 0)
4886                 return I40E_ERR_PARAM;
4887
4888         i40e_fill_default_direct_cmd_desc(&desc,
4889                                           i40e_aqc_opc_remove_statistics);
4890
4891         cmd->seid = CPU_TO_LE16(seid);
4892         cmd->vlan  = CPU_TO_LE16(vlan_id);
4893         cmd->stat_index = CPU_TO_LE16(stat_index);
4894
4895         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4896
4897         return status;
4898 }
4899
4900 /**
4901  * i40e_aq_set_port_parameters - set physical port parameters.
4902  * @hw: pointer to the hw struct
4903  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4904  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4905  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4906  * @double_vlan: if set double VLAN is enabled
4907  * @cmd_details: pointer to command details structure or NULL
4908  **/
4909 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4910                                 u16 bad_frame_vsi, bool save_bad_pac,
4911                                 bool pad_short_pac, bool double_vlan,
4912                                 struct i40e_asq_cmd_details *cmd_details)
4913 {
4914         struct i40e_aqc_set_port_parameters *cmd;
4915         enum i40e_status_code status;
4916         struct i40e_aq_desc desc;
4917         u16 command_flags = 0;
4918
4919         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4920
4921         i40e_fill_default_direct_cmd_desc(&desc,
4922                                           i40e_aqc_opc_set_port_parameters);
4923
4924         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4925         if (save_bad_pac)
4926                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4927         if (pad_short_pac)
4928                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4929         if (double_vlan)
4930                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4931         cmd->command_flags = CPU_TO_LE16(command_flags);
4932
4933         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4934
4935         return status;
4936 }
4937
4938 /**
4939  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4940  * @hw: pointer to the hw struct
4941  * @seid: seid for the physical port/switching component/vsi
4942  * @buff: Indirect buffer to hold data parameters and response
4943  * @buff_size: Indirect buffer size
4944  * @opcode: Tx scheduler AQ command opcode
4945  * @cmd_details: pointer to command details structure or NULL
4946  *
4947  * Generic command handler for Tx scheduler AQ commands
4948  **/
4949 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4950                                 void *buff, u16 buff_size,
4951                                  enum i40e_admin_queue_opc opcode,
4952                                 struct i40e_asq_cmd_details *cmd_details)
4953 {
4954         struct i40e_aq_desc desc;
4955         struct i40e_aqc_tx_sched_ind *cmd =
4956                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4957         enum i40e_status_code status;
4958         bool cmd_param_flag = false;
4959
4960         switch (opcode) {
4961         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4962         case i40e_aqc_opc_configure_vsi_tc_bw:
4963         case i40e_aqc_opc_enable_switching_comp_ets:
4964         case i40e_aqc_opc_modify_switching_comp_ets:
4965         case i40e_aqc_opc_disable_switching_comp_ets:
4966         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4967         case i40e_aqc_opc_configure_switching_comp_bw_config:
4968                 cmd_param_flag = true;
4969                 break;
4970         case i40e_aqc_opc_query_vsi_bw_config:
4971         case i40e_aqc_opc_query_vsi_ets_sla_config:
4972         case i40e_aqc_opc_query_switching_comp_ets_config:
4973         case i40e_aqc_opc_query_port_ets_config:
4974         case i40e_aqc_opc_query_switching_comp_bw_config:
4975                 cmd_param_flag = false;
4976                 break;
4977         default:
4978                 return I40E_ERR_PARAM;
4979         }
4980
4981         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4982
4983         /* Indirect command */
4984         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4985         if (cmd_param_flag)
4986                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4987         if (buff_size > I40E_AQ_LARGE_BUF)
4988                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4989
4990         desc.datalen = CPU_TO_LE16(buff_size);
4991
4992         cmd->vsi_seid = CPU_TO_LE16(seid);
4993
4994         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4995
4996         return status;
4997 }
4998
4999 /**
5000  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5001  * @hw: pointer to the hw struct
5002  * @seid: VSI seid
5003  * @credit: BW limit credits (0 = disabled)
5004  * @max_credit: Max BW limit credits
5005  * @cmd_details: pointer to command details structure or NULL
5006  **/
5007 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5008                                 u16 seid, u16 credit, u8 max_credit,
5009                                 struct i40e_asq_cmd_details *cmd_details)
5010 {
5011         struct i40e_aq_desc desc;
5012         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5013                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5014         enum i40e_status_code status;
5015
5016         i40e_fill_default_direct_cmd_desc(&desc,
5017                                           i40e_aqc_opc_configure_vsi_bw_limit);
5018
5019         cmd->vsi_seid = CPU_TO_LE16(seid);
5020         cmd->credit = CPU_TO_LE16(credit);
5021         cmd->max_credit = max_credit;
5022
5023         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5024
5025         return status;
5026 }
5027
5028 /**
5029  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5030  * @hw: pointer to the hw struct
5031  * @seid: switching component seid
5032  * @credit: BW limit credits (0 = disabled)
5033  * @max_bw: Max BW limit credits
5034  * @cmd_details: pointer to command details structure or NULL
5035  **/
5036 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5037                                 u16 seid, u16 credit, u8 max_bw,
5038                                 struct i40e_asq_cmd_details *cmd_details)
5039 {
5040         struct i40e_aq_desc desc;
5041         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5042           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5043         enum i40e_status_code status;
5044
5045         i40e_fill_default_direct_cmd_desc(&desc,
5046                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5047
5048         cmd->seid = CPU_TO_LE16(seid);
5049         cmd->credit = CPU_TO_LE16(credit);
5050         cmd->max_bw = max_bw;
5051
5052         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5053
5054         return status;
5055 }
5056
5057 /**
5058  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5059  * @hw: pointer to the hw struct
5060  * @seid: VSI seid
5061  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5062  * @cmd_details: pointer to command details structure or NULL
5063  **/
5064 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5065                         u16 seid,
5066                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5067                         struct i40e_asq_cmd_details *cmd_details)
5068 {
5069         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5070                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5071                                     cmd_details);
5072 }
5073
5074 /**
5075  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5076  * @hw: pointer to the hw struct
5077  * @seid: VSI seid
5078  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5079  * @cmd_details: pointer to command details structure or NULL
5080  **/
5081 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5082                         u16 seid,
5083                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5084                         struct i40e_asq_cmd_details *cmd_details)
5085 {
5086         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5087                                     i40e_aqc_opc_configure_vsi_tc_bw,
5088                                     cmd_details);
5089 }
5090
5091 /**
5092  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5093  * @hw: pointer to the hw struct
5094  * @seid: seid of the switching component connected to Physical Port
5095  * @ets_data: Buffer holding ETS parameters
5096  * @cmd_details: pointer to command details structure or NULL
5097  **/
5098 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5099                 u16 seid,
5100                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5101                 enum i40e_admin_queue_opc opcode,
5102                 struct i40e_asq_cmd_details *cmd_details)
5103 {
5104         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5105                                     sizeof(*ets_data), opcode, cmd_details);
5106 }
5107
5108 /**
5109  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5110  * @hw: pointer to the hw struct
5111  * @seid: seid of the switching component
5112  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5113  * @cmd_details: pointer to command details structure or NULL
5114  **/
5115 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5116         u16 seid,
5117         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5118         struct i40e_asq_cmd_details *cmd_details)
5119 {
5120         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5121                             i40e_aqc_opc_configure_switching_comp_bw_config,
5122                             cmd_details);
5123 }
5124
5125 /**
5126  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5127  * @hw: pointer to the hw struct
5128  * @seid: seid of the switching component
5129  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5130  * @cmd_details: pointer to command details structure or NULL
5131  **/
5132 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5133         struct i40e_hw *hw, u16 seid,
5134         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5135         struct i40e_asq_cmd_details *cmd_details)
5136 {
5137         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5138                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5139                             cmd_details);
5140 }
5141
5142 /**
5143  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5144  * @hw: pointer to the hw struct
5145  * @seid: seid of the VSI
5146  * @bw_data: Buffer to hold VSI BW configuration
5147  * @cmd_details: pointer to command details structure or NULL
5148  **/
5149 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5150                         u16 seid,
5151                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5152                         struct i40e_asq_cmd_details *cmd_details)
5153 {
5154         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5155                                     i40e_aqc_opc_query_vsi_bw_config,
5156                                     cmd_details);
5157 }
5158
5159 /**
5160  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5161  * @hw: pointer to the hw struct
5162  * @seid: seid of the VSI
5163  * @bw_data: Buffer to hold VSI BW configuration per TC
5164  * @cmd_details: pointer to command details structure or NULL
5165  **/
5166 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5167                         u16 seid,
5168                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5169                         struct i40e_asq_cmd_details *cmd_details)
5170 {
5171         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5172                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5173                                     cmd_details);
5174 }
5175
5176 /**
5177  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5178  * @hw: pointer to the hw struct
5179  * @seid: seid of the switching component
5180  * @bw_data: Buffer to hold switching component's per TC BW config
5181  * @cmd_details: pointer to command details structure or NULL
5182  **/
5183 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5184                 u16 seid,
5185                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5186                 struct i40e_asq_cmd_details *cmd_details)
5187 {
5188         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5189                                    i40e_aqc_opc_query_switching_comp_ets_config,
5190                                    cmd_details);
5191 }
5192
5193 /**
5194  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5195  * @hw: pointer to the hw struct
5196  * @seid: seid of the VSI or switching component connected to Physical Port
5197  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5198  * @cmd_details: pointer to command details structure or NULL
5199  **/
5200 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5201                         u16 seid,
5202                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5203                         struct i40e_asq_cmd_details *cmd_details)
5204 {
5205         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5206                                     i40e_aqc_opc_query_port_ets_config,
5207                                     cmd_details);
5208 }
5209
5210 /**
5211  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5212  * @hw: pointer to the hw struct
5213  * @seid: seid of the switching component
5214  * @bw_data: Buffer to hold switching component's BW configuration
5215  * @cmd_details: pointer to command details structure or NULL
5216  **/
5217 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5218                 u16 seid,
5219                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5220                 struct i40e_asq_cmd_details *cmd_details)
5221 {
5222         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5223                                     i40e_aqc_opc_query_switching_comp_bw_config,
5224                                     cmd_details);
5225 }
5226
5227 /**
5228  * i40e_validate_filter_settings
5229  * @hw: pointer to the hardware structure
5230  * @settings: Filter control settings
5231  *
5232  * Check and validate the filter control settings passed.
5233  * The function checks for the valid filter/context sizes being
5234  * passed for FCoE and PE.
5235  *
5236  * Returns I40E_SUCCESS if the values passed are valid and within
5237  * range else returns an error.
5238  **/
5239 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5240                                 struct i40e_filter_control_settings *settings)
5241 {
5242         u32 fcoe_cntx_size, fcoe_filt_size;
5243         u32 pe_cntx_size, pe_filt_size;
5244         u32 fcoe_fmax;
5245
5246         u32 val;
5247
5248         /* Validate FCoE settings passed */
5249         switch (settings->fcoe_filt_num) {
5250         case I40E_HASH_FILTER_SIZE_1K:
5251         case I40E_HASH_FILTER_SIZE_2K:
5252         case I40E_HASH_FILTER_SIZE_4K:
5253         case I40E_HASH_FILTER_SIZE_8K:
5254         case I40E_HASH_FILTER_SIZE_16K:
5255         case I40E_HASH_FILTER_SIZE_32K:
5256                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5257                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5258                 break;
5259         default:
5260                 return I40E_ERR_PARAM;
5261         }
5262
5263         switch (settings->fcoe_cntx_num) {
5264         case I40E_DMA_CNTX_SIZE_512:
5265         case I40E_DMA_CNTX_SIZE_1K:
5266         case I40E_DMA_CNTX_SIZE_2K:
5267         case I40E_DMA_CNTX_SIZE_4K:
5268                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5269                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5270                 break;
5271         default:
5272                 return I40E_ERR_PARAM;
5273         }
5274
5275         /* Validate PE settings passed */
5276         switch (settings->pe_filt_num) {
5277         case I40E_HASH_FILTER_SIZE_1K:
5278         case I40E_HASH_FILTER_SIZE_2K:
5279         case I40E_HASH_FILTER_SIZE_4K:
5280         case I40E_HASH_FILTER_SIZE_8K:
5281         case I40E_HASH_FILTER_SIZE_16K:
5282         case I40E_HASH_FILTER_SIZE_32K:
5283         case I40E_HASH_FILTER_SIZE_64K:
5284         case I40E_HASH_FILTER_SIZE_128K:
5285         case I40E_HASH_FILTER_SIZE_256K:
5286         case I40E_HASH_FILTER_SIZE_512K:
5287         case I40E_HASH_FILTER_SIZE_1M:
5288                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5289                 pe_filt_size <<= (u32)settings->pe_filt_num;
5290                 break;
5291         default:
5292                 return I40E_ERR_PARAM;
5293         }
5294
5295         switch (settings->pe_cntx_num) {
5296         case I40E_DMA_CNTX_SIZE_512:
5297         case I40E_DMA_CNTX_SIZE_1K:
5298         case I40E_DMA_CNTX_SIZE_2K:
5299         case I40E_DMA_CNTX_SIZE_4K:
5300         case I40E_DMA_CNTX_SIZE_8K:
5301         case I40E_DMA_CNTX_SIZE_16K:
5302         case I40E_DMA_CNTX_SIZE_32K:
5303         case I40E_DMA_CNTX_SIZE_64K:
5304         case I40E_DMA_CNTX_SIZE_128K:
5305         case I40E_DMA_CNTX_SIZE_256K:
5306                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5307                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5308                 break;
5309         default:
5310                 return I40E_ERR_PARAM;
5311         }
5312
5313         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5314         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5315         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5316                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5317         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5318                 return I40E_ERR_INVALID_SIZE;
5319
5320         return I40E_SUCCESS;
5321 }
5322
5323 /**
5324  * i40e_set_filter_control
5325  * @hw: pointer to the hardware structure
5326  * @settings: Filter control settings
5327  *
5328  * Set the Queue Filters for PE/FCoE and enable filters required
5329  * for a single PF. It is expected that these settings are programmed
5330  * at the driver initialization time.
5331  **/
5332 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5333                                 struct i40e_filter_control_settings *settings)
5334 {
5335         enum i40e_status_code ret = I40E_SUCCESS;
5336         u32 hash_lut_size = 0;
5337         u32 val;
5338
5339         if (!settings)
5340                 return I40E_ERR_PARAM;
5341
5342         /* Validate the input settings */
5343         ret = i40e_validate_filter_settings(hw, settings);
5344         if (ret)
5345                 return ret;
5346
5347         /* Read the PF Queue Filter control register */
5348         val = rd32(hw, I40E_PFQF_CTL_0);
5349
5350         /* Program required PE hash buckets for the PF */
5351         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5352         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5353                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5354         /* Program required PE contexts for the PF */
5355         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5356         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5357                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5358
5359         /* Program required FCoE hash buckets for the PF */
5360         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5361         val |= ((u32)settings->fcoe_filt_num <<
5362                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5363                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5364         /* Program required FCoE DDP contexts for the PF */
5365         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5366         val |= ((u32)settings->fcoe_cntx_num <<
5367                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5368                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5369
5370         /* Program Hash LUT size for the PF */
5371         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5372         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5373                 hash_lut_size = 1;
5374         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5375                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5376
5377         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5378         if (settings->enable_fdir)
5379                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5380         if (settings->enable_ethtype)
5381                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5382         if (settings->enable_macvlan)
5383                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5384
5385         wr32(hw, I40E_PFQF_CTL_0, val);
5386
5387         return I40E_SUCCESS;
5388 }
5389
5390 /**
5391  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5392  * @hw: pointer to the hw struct
5393  * @mac_addr: MAC address to use in the filter
5394  * @ethtype: Ethertype to use in the filter
5395  * @flags: Flags that needs to be applied to the filter
5396  * @vsi_seid: seid of the control VSI
5397  * @queue: VSI queue number to send the packet to
5398  * @is_add: Add control packet filter if True else remove
5399  * @stats: Structure to hold information on control filter counts
5400  * @cmd_details: pointer to command details structure or NULL
5401  *
5402  * This command will Add or Remove control packet filter for a control VSI.
5403  * In return it will update the total number of perfect filter count in
5404  * the stats member.
5405  **/
5406 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5407                                 u8 *mac_addr, u16 ethtype, u16 flags,
5408                                 u16 vsi_seid, u16 queue, bool is_add,
5409                                 struct i40e_control_filter_stats *stats,
5410                                 struct i40e_asq_cmd_details *cmd_details)
5411 {
5412         struct i40e_aq_desc desc;
5413         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5414                 (struct i40e_aqc_add_remove_control_packet_filter *)
5415                 &desc.params.raw;
5416         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5417                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5418                 &desc.params.raw;
5419         enum i40e_status_code status;
5420
5421         if (vsi_seid == 0)
5422                 return I40E_ERR_PARAM;
5423
5424         if (is_add) {
5425                 i40e_fill_default_direct_cmd_desc(&desc,
5426                                 i40e_aqc_opc_add_control_packet_filter);
5427                 cmd->queue = CPU_TO_LE16(queue);
5428         } else {
5429                 i40e_fill_default_direct_cmd_desc(&desc,
5430                                 i40e_aqc_opc_remove_control_packet_filter);
5431         }
5432
5433         if (mac_addr)
5434                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5435                             I40E_NONDMA_TO_NONDMA);
5436
5437         cmd->etype = CPU_TO_LE16(ethtype);
5438         cmd->flags = CPU_TO_LE16(flags);
5439         cmd->seid = CPU_TO_LE16(vsi_seid);
5440
5441         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5442
5443         if (!status && stats) {
5444                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5445                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5446                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5447                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5448         }
5449
5450         return status;
5451 }
5452
5453 /**
5454  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5455  * @hw: pointer to the hw struct
5456  * @seid: VSI seid to add ethertype filter from
5457  **/
5458 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5459 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5460                                                     u16 seid)
5461 {
5462         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5463                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5464                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5465         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5466         enum i40e_status_code status;
5467
5468         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5469                                                        seid, 0, true, NULL,
5470                                                        NULL);
5471         if (status)
5472                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5473 }
5474
5475 /**
5476  * i40e_aq_add_cloud_filters
5477  * @hw: pointer to the hardware structure
5478  * @seid: VSI seid to add cloud filters from
5479  * @filters: Buffer which contains the filters to be added
5480  * @filter_count: number of filters contained in the buffer
5481  *
5482  * Set the cloud filters for a given VSI.  The contents of the
5483  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5484  * in by the caller of the function.
5485  *
5486  **/
5487 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5488         u16 seid,
5489         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5490         u8 filter_count)
5491 {
5492         struct i40e_aq_desc desc;
5493         struct i40e_aqc_add_remove_cloud_filters *cmd =
5494         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5495         u16 buff_len;
5496         enum i40e_status_code status;
5497
5498         i40e_fill_default_direct_cmd_desc(&desc,
5499                                           i40e_aqc_opc_add_cloud_filters);
5500
5501         buff_len = filter_count * sizeof(*filters);
5502         desc.datalen = CPU_TO_LE16(buff_len);
5503         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5504         cmd->num_filters = filter_count;
5505         cmd->seid = CPU_TO_LE16(seid);
5506
5507         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5508
5509         return status;
5510 }
5511
5512 /**
5513  * i40e_aq_remove_cloud_filters
5514  * @hw: pointer to the hardware structure
5515  * @seid: VSI seid to remove cloud filters from
5516  * @filters: Buffer which contains the filters to be removed
5517  * @filter_count: number of filters contained in the buffer
5518  *
5519  * Remove the cloud filters for a given VSI.  The contents of the
5520  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5521  * in by the caller of the function.
5522  *
5523  **/
5524 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5525                 u16 seid,
5526                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5527                 u8 filter_count)
5528 {
5529         struct i40e_aq_desc desc;
5530         struct i40e_aqc_add_remove_cloud_filters *cmd =
5531         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5532         enum i40e_status_code status;
5533         u16 buff_len;
5534
5535         i40e_fill_default_direct_cmd_desc(&desc,
5536                                           i40e_aqc_opc_remove_cloud_filters);
5537
5538         buff_len = filter_count * sizeof(*filters);
5539         desc.datalen = CPU_TO_LE16(buff_len);
5540         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5541         cmd->num_filters = filter_count;
5542         cmd->seid = CPU_TO_LE16(seid);
5543
5544         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5545
5546         return status;
5547 }
5548
5549 /**
5550  * i40e_aq_alternate_write
5551  * @hw: pointer to the hardware structure
5552  * @reg_addr0: address of first dword to be read
5553  * @reg_val0: value to be written under 'reg_addr0'
5554  * @reg_addr1: address of second dword to be read
5555  * @reg_val1: value to be written under 'reg_addr1'
5556  *
5557  * Write one or two dwords to alternate structure. Fields are indicated
5558  * by 'reg_addr0' and 'reg_addr1' register numbers.
5559  *
5560  **/
5561 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5562                                 u32 reg_addr0, u32 reg_val0,
5563                                 u32 reg_addr1, u32 reg_val1)
5564 {
5565         struct i40e_aq_desc desc;
5566         struct i40e_aqc_alternate_write *cmd_resp =
5567                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5568         enum i40e_status_code status;
5569
5570         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5571         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5572         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5573         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5574         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5575
5576         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5577
5578         return status;
5579 }
5580
5581 /**
5582  * i40e_aq_alternate_write_indirect
5583  * @hw: pointer to the hardware structure
5584  * @addr: address of a first register to be modified
5585  * @dw_count: number of alternate structure fields to write
5586  * @buffer: pointer to the command buffer
5587  *
5588  * Write 'dw_count' dwords from 'buffer' to alternate structure
5589  * starting at 'addr'.
5590  *
5591  **/
5592 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5593                                 u32 addr, u32 dw_count, void *buffer)
5594 {
5595         struct i40e_aq_desc desc;
5596         struct i40e_aqc_alternate_ind_write *cmd_resp =
5597                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5598         enum i40e_status_code status;
5599
5600         if (buffer == NULL)
5601                 return I40E_ERR_PARAM;
5602
5603         /* Indirect command */
5604         i40e_fill_default_direct_cmd_desc(&desc,
5605                                          i40e_aqc_opc_alternate_write_indirect);
5606
5607         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5608         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5609         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5610                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5611
5612         cmd_resp->address = CPU_TO_LE32(addr);
5613         cmd_resp->length = CPU_TO_LE32(dw_count);
5614
5615         status = i40e_asq_send_command(hw, &desc, buffer,
5616                                        I40E_LO_DWORD(4*dw_count), NULL);
5617
5618         return status;
5619 }
5620
5621 /**
5622  * i40e_aq_alternate_read
5623  * @hw: pointer to the hardware structure
5624  * @reg_addr0: address of first dword to be read
5625  * @reg_val0: pointer for data read from 'reg_addr0'
5626  * @reg_addr1: address of second dword to be read
5627  * @reg_val1: pointer for data read from 'reg_addr1'
5628  *
5629  * Read one or two dwords from alternate structure. Fields are indicated
5630  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5631  * is not passed then only register at 'reg_addr0' is read.
5632  *
5633  **/
5634 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5635                                 u32 reg_addr0, u32 *reg_val0,
5636                                 u32 reg_addr1, u32 *reg_val1)
5637 {
5638         struct i40e_aq_desc desc;
5639         struct i40e_aqc_alternate_write *cmd_resp =
5640                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5641         enum i40e_status_code status;
5642
5643         if (reg_val0 == NULL)
5644                 return I40E_ERR_PARAM;
5645
5646         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5647         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5648         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5649
5650         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5651
5652         if (status == I40E_SUCCESS) {
5653                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5654
5655                 if (reg_val1 != NULL)
5656                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5657         }
5658
5659         return status;
5660 }
5661
5662 /**
5663  * i40e_aq_alternate_read_indirect
5664  * @hw: pointer to the hardware structure
5665  * @addr: address of the alternate structure field
5666  * @dw_count: number of alternate structure fields to read
5667  * @buffer: pointer to the command buffer
5668  *
5669  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5670  * place them in 'buffer'. The buffer should be allocated by caller.
5671  *
5672  **/
5673 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5674                                 u32 addr, u32 dw_count, void *buffer)
5675 {
5676         struct i40e_aq_desc desc;
5677         struct i40e_aqc_alternate_ind_write *cmd_resp =
5678                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5679         enum i40e_status_code status;
5680
5681         if (buffer == NULL)
5682                 return I40E_ERR_PARAM;
5683
5684         /* Indirect command */
5685         i40e_fill_default_direct_cmd_desc(&desc,
5686                 i40e_aqc_opc_alternate_read_indirect);
5687
5688         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5689         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5690         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5691                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5692
5693         cmd_resp->address = CPU_TO_LE32(addr);
5694         cmd_resp->length = CPU_TO_LE32(dw_count);
5695
5696         status = i40e_asq_send_command(hw, &desc, buffer,
5697                                        I40E_LO_DWORD(4*dw_count), NULL);
5698
5699         return status;
5700 }
5701
5702 /**
5703  *  i40e_aq_alternate_clear
5704  *  @hw: pointer to the HW structure.
5705  *
5706  *  Clear the alternate structures of the port from which the function
5707  *  is called.
5708  *
5709  **/
5710 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5711 {
5712         struct i40e_aq_desc desc;
5713         enum i40e_status_code status;
5714
5715         i40e_fill_default_direct_cmd_desc(&desc,
5716                                           i40e_aqc_opc_alternate_clear_port);
5717
5718         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5719
5720         return status;
5721 }
5722
5723 /**
5724  *  i40e_aq_alternate_write_done
5725  *  @hw: pointer to the HW structure.
5726  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5727  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5728  *
5729  *  Indicates to the FW that alternate structures have been changed.
5730  *
5731  **/
5732 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5733                 u8 bios_mode, bool *reset_needed)
5734 {
5735         struct i40e_aq_desc desc;
5736         struct i40e_aqc_alternate_write_done *cmd =
5737                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5738         enum i40e_status_code status;
5739
5740         if (reset_needed == NULL)
5741                 return I40E_ERR_PARAM;
5742
5743         i40e_fill_default_direct_cmd_desc(&desc,
5744                                           i40e_aqc_opc_alternate_write_done);
5745
5746         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5747
5748         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5749         if (!status && reset_needed)
5750                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5751                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5752
5753         return status;
5754 }
5755
5756 /**
5757  *  i40e_aq_set_oem_mode
5758  *  @hw: pointer to the HW structure.
5759  *  @oem_mode: the OEM mode to be used
5760  *
5761  *  Sets the device to a specific operating mode. Currently the only supported
5762  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5763  *
5764  **/
5765 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5766                 u8 oem_mode)
5767 {
5768         struct i40e_aq_desc desc;
5769         struct i40e_aqc_alternate_write_done *cmd =
5770                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5771         enum i40e_status_code status;
5772
5773         i40e_fill_default_direct_cmd_desc(&desc,
5774                                           i40e_aqc_opc_alternate_set_mode);
5775
5776         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5777
5778         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5779
5780         return status;
5781 }
5782
5783 /**
5784  * i40e_aq_resume_port_tx
5785  * @hw: pointer to the hardware structure
5786  * @cmd_details: pointer to command details structure or NULL
5787  *
5788  * Resume port's Tx traffic
5789  **/
5790 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5791                                 struct i40e_asq_cmd_details *cmd_details)
5792 {
5793         struct i40e_aq_desc desc;
5794         enum i40e_status_code status;
5795
5796         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5797
5798         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5799
5800         return status;
5801 }
5802
5803 /**
5804  * i40e_set_pci_config_data - store PCI bus info
5805  * @hw: pointer to hardware structure
5806  * @link_status: the link status word from PCI config space
5807  *
5808  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5809  **/
5810 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5811 {
5812         hw->bus.type = i40e_bus_type_pci_express;
5813
5814         switch (link_status & I40E_PCI_LINK_WIDTH) {
5815         case I40E_PCI_LINK_WIDTH_1:
5816                 hw->bus.width = i40e_bus_width_pcie_x1;
5817                 break;
5818         case I40E_PCI_LINK_WIDTH_2:
5819                 hw->bus.width = i40e_bus_width_pcie_x2;
5820                 break;
5821         case I40E_PCI_LINK_WIDTH_4:
5822                 hw->bus.width = i40e_bus_width_pcie_x4;
5823                 break;
5824         case I40E_PCI_LINK_WIDTH_8:
5825                 hw->bus.width = i40e_bus_width_pcie_x8;
5826                 break;
5827         default:
5828                 hw->bus.width = i40e_bus_width_unknown;
5829                 break;
5830         }
5831
5832         switch (link_status & I40E_PCI_LINK_SPEED) {
5833         case I40E_PCI_LINK_SPEED_2500:
5834                 hw->bus.speed = i40e_bus_speed_2500;
5835                 break;
5836         case I40E_PCI_LINK_SPEED_5000:
5837                 hw->bus.speed = i40e_bus_speed_5000;
5838                 break;
5839         case I40E_PCI_LINK_SPEED_8000:
5840                 hw->bus.speed = i40e_bus_speed_8000;
5841                 break;
5842         default:
5843                 hw->bus.speed = i40e_bus_speed_unknown;
5844                 break;
5845         }
5846 }
5847
5848 /**
5849  * i40e_aq_debug_dump
5850  * @hw: pointer to the hardware structure
5851  * @cluster_id: specific cluster to dump
5852  * @table_id: table id within cluster
5853  * @start_index: index of line in the block to read
5854  * @buff_size: dump buffer size
5855  * @buff: dump buffer
5856  * @ret_buff_size: actual buffer size returned
5857  * @ret_next_table: next block to read
5858  * @ret_next_index: next index to read
5859  *
5860  * Dump internal FW/HW data for debug purposes.
5861  *
5862  **/
5863 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5864                                 u8 table_id, u32 start_index, u16 buff_size,
5865                                 void *buff, u16 *ret_buff_size,
5866                                 u8 *ret_next_table, u32 *ret_next_index,
5867                                 struct i40e_asq_cmd_details *cmd_details)
5868 {
5869         struct i40e_aq_desc desc;
5870         struct i40e_aqc_debug_dump_internals *cmd =
5871                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5872         struct i40e_aqc_debug_dump_internals *resp =
5873                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5874         enum i40e_status_code status;
5875
5876         if (buff_size == 0 || !buff)
5877                 return I40E_ERR_PARAM;
5878
5879         i40e_fill_default_direct_cmd_desc(&desc,
5880                                           i40e_aqc_opc_debug_dump_internals);
5881         /* Indirect Command */
5882         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5883         if (buff_size > I40E_AQ_LARGE_BUF)
5884                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5885
5886         cmd->cluster_id = cluster_id;
5887         cmd->table_id = table_id;
5888         cmd->idx = CPU_TO_LE32(start_index);
5889
5890         desc.datalen = CPU_TO_LE16(buff_size);
5891
5892         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5893         if (!status) {
5894                 if (ret_buff_size != NULL)
5895                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5896                 if (ret_next_table != NULL)
5897                         *ret_next_table = resp->table_id;
5898                 if (ret_next_index != NULL)
5899                         *ret_next_index = LE32_TO_CPU(resp->idx);
5900         }
5901
5902         return status;
5903 }
5904
5905 /**
5906  * i40e_read_bw_from_alt_ram
5907  * @hw: pointer to the hardware structure
5908  * @max_bw: pointer for max_bw read
5909  * @min_bw: pointer for min_bw read
5910  * @min_valid: pointer for bool that is true if min_bw is a valid value
5911  * @max_valid: pointer for bool that is true if max_bw is a valid value
5912  *
5913  * Read bw from the alternate ram for the given pf
5914  **/
5915 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5916                                         u32 *max_bw, u32 *min_bw,
5917                                         bool *min_valid, bool *max_valid)
5918 {
5919         enum i40e_status_code status;
5920         u32 max_bw_addr, min_bw_addr;
5921
5922         /* Calculate the address of the min/max bw registers */
5923         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5924                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5925                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5926         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5927                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5928                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5929
5930         /* Read the bandwidths from alt ram */
5931         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5932                                         min_bw_addr, min_bw);
5933
5934         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5935                 *min_valid = true;
5936         else
5937                 *min_valid = false;
5938
5939         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5940                 *max_valid = true;
5941         else
5942                 *max_valid = false;
5943
5944         return status;
5945 }
5946
5947 /**
5948  * i40e_aq_configure_partition_bw
5949  * @hw: pointer to the hardware structure
5950  * @bw_data: Buffer holding valid pfs and bw limits
5951  * @cmd_details: pointer to command details
5952  *
5953  * Configure partitions guaranteed/max bw
5954  **/
5955 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5956                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5957                         struct i40e_asq_cmd_details *cmd_details)
5958 {
5959         enum i40e_status_code status;
5960         struct i40e_aq_desc desc;
5961         u16 bwd_size = sizeof(*bw_data);
5962
5963         i40e_fill_default_direct_cmd_desc(&desc,
5964                                 i40e_aqc_opc_configure_partition_bw);
5965
5966         /* Indirect command */
5967         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5968         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5969
5970         if (bwd_size > I40E_AQ_LARGE_BUF)
5971                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5972
5973         desc.datalen = CPU_TO_LE16(bwd_size);
5974
5975         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5976
5977         return status;
5978 }
5979
5980 /**
5981  * i40e_read_phy_register
5982  * @hw: pointer to the HW structure
5983  * @page: registers page number
5984  * @reg: register address in the page
5985  * @phy_adr: PHY address on MDIO interface
5986  * @value: PHY register value
5987  *
5988  * Reads specified PHY register value
5989  **/
5990 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5991                                              u8 page, u16 reg, u8 phy_addr,
5992                                              u16 *value)
5993 {
5994         enum i40e_status_code status = I40E_ERR_TIMEOUT;
5995         u32 command  = 0;
5996         u16 retry = 1000;
5997         u8 port_num = (u8)hw->func_caps.mdio_port_num;
5998
5999         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6000                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6001                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6002                   (I40E_MDIO_OPCODE_ADDRESS) |
6003                   (I40E_MDIO_STCODE) |
6004                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6005                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6006         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6007         do {
6008                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6009                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6010                         status = I40E_SUCCESS;
6011                         break;
6012                 }
6013                 i40e_usec_delay(10);
6014                 retry--;
6015         } while (retry);
6016
6017         if (status) {
6018                 i40e_debug(hw, I40E_DEBUG_PHY,
6019                            "PHY: Can't write command to external PHY.\n");
6020                 goto phy_read_end;
6021         }
6022
6023         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6024                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6025                   (I40E_MDIO_OPCODE_READ) |
6026                   (I40E_MDIO_STCODE) |
6027                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6028                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6029         status = I40E_ERR_TIMEOUT;
6030         retry = 1000;
6031         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6032         do {
6033                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6034                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6035                         status = I40E_SUCCESS;
6036                         break;
6037                 }
6038                 i40e_usec_delay(10);
6039                 retry--;
6040         } while (retry);
6041
6042         if (!status) {
6043                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6044                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6045                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6046         } else {
6047                 i40e_debug(hw, I40E_DEBUG_PHY,
6048                            "PHY: Can't read register value from external PHY.\n");
6049         }
6050
6051 phy_read_end:
6052         return status;
6053 }
6054
6055 /**
6056  * i40e_write_phy_register
6057  * @hw: pointer to the HW structure
6058  * @page: registers page number
6059  * @reg: register address in the page
6060  * @phy_adr: PHY address on MDIO interface
6061  * @value: PHY register value
6062  *
6063  * Writes value to specified PHY register
6064  **/
6065 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6066                                               u8 page, u16 reg, u8 phy_addr,
6067                                               u16 value)
6068 {
6069         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6070         u32 command  = 0;
6071         u16 retry = 1000;
6072         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6073
6074         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6075                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6076                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6077                   (I40E_MDIO_OPCODE_ADDRESS) |
6078                   (I40E_MDIO_STCODE) |
6079                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6080                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6081         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6082         do {
6083                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6084                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6085                         status = I40E_SUCCESS;
6086                         break;
6087                 }
6088                 i40e_usec_delay(10);
6089                 retry--;
6090         } while (retry);
6091         if (status) {
6092                 i40e_debug(hw, I40E_DEBUG_PHY,
6093                            "PHY: Can't write command to external PHY.\n");
6094                 goto phy_write_end;
6095         }
6096
6097         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6098         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6099
6100         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6101                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6102                   (I40E_MDIO_OPCODE_WRITE) |
6103                   (I40E_MDIO_STCODE) |
6104                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6105                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6106         status = I40E_ERR_TIMEOUT;
6107         retry = 1000;
6108         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6109         do {
6110                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6111                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6112                         status = I40E_SUCCESS;
6113                         break;
6114                 }
6115                 i40e_usec_delay(10);
6116                 retry--;
6117         } while (retry);
6118
6119 phy_write_end:
6120         return status;
6121 }
6122
6123 /**
6124  * i40e_get_phy_address
6125  * @hw: pointer to the HW structure
6126  * @dev_num: PHY port num that address we want
6127  * @phy_addr: Returned PHY address
6128  *
6129  * Gets PHY address for current port
6130  **/
6131 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6132 {
6133         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6134         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6135
6136         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6137 }
6138
6139 /**
6140  * i40e_blink_phy_led
6141  * @hw: pointer to the HW structure
6142  * @time: time how long led will blinks in secs
6143  * @interval: gap between LED on and off in msecs
6144  *
6145  * Blinks PHY link LED
6146  **/
6147 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6148                                               u32 time, u32 interval)
6149 {
6150         enum i40e_status_code status = I40E_SUCCESS;
6151         u32 i;
6152         u16 led_ctl = 0;
6153         u16 gpio_led_port;
6154         u16 led_reg;
6155         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6156         u8 phy_addr = 0;
6157         u8 port_num;
6158
6159         i = rd32(hw, I40E_PFGEN_PORTNUM);
6160         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6161         phy_addr = i40e_get_phy_address(hw, port_num);
6162
6163         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6164              led_addr++) {
6165                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6166                                                 led_addr, phy_addr, &led_reg);
6167                 if (status)
6168                         goto phy_blinking_end;
6169                 led_ctl = led_reg;
6170                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6171                         led_reg = 0;
6172                         status = i40e_write_phy_register(hw,
6173                                                          I40E_PHY_COM_REG_PAGE,
6174                                                          led_addr, phy_addr,
6175                                                          led_reg);
6176                         if (status)
6177                                 goto phy_blinking_end;
6178                         break;
6179                 }
6180         }
6181
6182         if (time > 0 && interval > 0) {
6183                 for (i = 0; i < time * 1000; i += interval) {
6184                         status = i40e_read_phy_register(hw,
6185                                                         I40E_PHY_COM_REG_PAGE,
6186                                                         led_addr, phy_addr,
6187                                                         &led_reg);
6188                         if (status)
6189                                 goto restore_config;
6190                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6191                                 led_reg = 0;
6192                         else
6193                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6194                         status = i40e_write_phy_register(hw,
6195                                                          I40E_PHY_COM_REG_PAGE,
6196                                                          led_addr, phy_addr,
6197                                                          led_reg);
6198                         if (status)
6199                                 goto restore_config;
6200                         i40e_msec_delay(interval);
6201                 }
6202         }
6203
6204 restore_config:
6205         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6206                                          phy_addr, led_ctl);
6207
6208 phy_blinking_end:
6209         return status;
6210 }
6211
6212 /**
6213  * i40e_led_get_phy - return current on/off mode
6214  * @hw: pointer to the hw struct
6215  * @led_addr: address of led register to use
6216  * @val: original value of register to use
6217  *
6218  **/
6219 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6220                                        u16 *val)
6221 {
6222         enum i40e_status_code status = I40E_SUCCESS;
6223         u16 gpio_led_port;
6224         u8 phy_addr = 0;
6225         u16 reg_val;
6226         u16 temp_addr;
6227         u8 port_num;
6228         u32 i;
6229
6230         temp_addr = I40E_PHY_LED_PROV_REG_1;
6231         i = rd32(hw, I40E_PFGEN_PORTNUM);
6232         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6233         phy_addr = i40e_get_phy_address(hw, port_num);
6234
6235         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6236              temp_addr++) {
6237                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6238                                                 temp_addr, phy_addr, &reg_val);
6239                 if (status)
6240                         return status;
6241                 *val = reg_val;
6242                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6243                         *led_addr = temp_addr;
6244                         break;
6245                 }
6246         }
6247         return status;
6248 }
6249
6250 /**
6251  * i40e_led_set_phy
6252  * @hw: pointer to the HW structure
6253  * @on: true or false
6254  * @mode: original val plus bit for set or ignore
6255  * Set led's on or off when controlled by the PHY
6256  *
6257  **/
6258 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6259                                        u16 led_addr, u32 mode)
6260 {
6261         enum i40e_status_code status = I40E_SUCCESS;
6262         u16 led_ctl = 0;
6263         u16 led_reg = 0;
6264         u8 phy_addr = 0;
6265         u8 port_num;
6266         u32 i;
6267
6268         i = rd32(hw, I40E_PFGEN_PORTNUM);
6269         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6270         phy_addr = i40e_get_phy_address(hw, port_num);
6271
6272         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6273                                         phy_addr, &led_reg);
6274         if (status)
6275                 return status;
6276         led_ctl = led_reg;
6277         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6278                 led_reg = 0;
6279                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6280                                                  led_addr, phy_addr, led_reg);
6281                 if (status)
6282                         return status;
6283         }
6284         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6285                                         led_addr, phy_addr, &led_reg);
6286         if (status)
6287                 goto restore_config;
6288         if (on)
6289                 led_reg = I40E_PHY_LED_MANUAL_ON;
6290         else
6291                 led_reg = 0;
6292         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6293                                          led_addr, phy_addr, led_reg);
6294         if (status)
6295                 goto restore_config;
6296         if (mode & I40E_PHY_LED_MODE_ORIG) {
6297                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6298                 status = i40e_write_phy_register(hw,
6299                                                  I40E_PHY_COM_REG_PAGE,
6300                                                  led_addr, phy_addr, led_ctl);
6301         }
6302         return status;
6303 restore_config:
6304         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6305                                          phy_addr, led_ctl);
6306         return status;
6307 }
6308 #endif /* PF_DRIVER */
6309 #ifdef VF_DRIVER
6310
6311 /**
6312  * i40e_aq_send_msg_to_pf
6313  * @hw: pointer to the hardware structure
6314  * @v_opcode: opcodes for VF-PF communication
6315  * @v_retval: return error code
6316  * @msg: pointer to the msg buffer
6317  * @msglen: msg length
6318  * @cmd_details: pointer to command details
6319  *
6320  * Send message to PF driver using admin queue. By default, this message
6321  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6322  * completion before returning.
6323  **/
6324 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6325                                 enum i40e_virtchnl_ops v_opcode,
6326                                 enum i40e_status_code v_retval,
6327                                 u8 *msg, u16 msglen,
6328                                 struct i40e_asq_cmd_details *cmd_details)
6329 {
6330         struct i40e_aq_desc desc;
6331         struct i40e_asq_cmd_details details;
6332         enum i40e_status_code status;
6333
6334         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6335         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6336         desc.cookie_high = CPU_TO_LE32(v_opcode);
6337         desc.cookie_low = CPU_TO_LE32(v_retval);
6338         if (msglen) {
6339                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6340                                                 | I40E_AQ_FLAG_RD));
6341                 if (msglen > I40E_AQ_LARGE_BUF)
6342                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6343                 desc.datalen = CPU_TO_LE16(msglen);
6344         }
6345         if (!cmd_details) {
6346                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6347                 details.async = true;
6348                 cmd_details = &details;
6349         }
6350         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6351                                        msglen, cmd_details);
6352         return status;
6353 }
6354
6355 /**
6356  * i40e_vf_parse_hw_config
6357  * @hw: pointer to the hardware structure
6358  * @msg: pointer to the virtual channel VF resource structure
6359  *
6360  * Given a VF resource message from the PF, populate the hw struct
6361  * with appropriate information.
6362  **/
6363 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6364                              struct i40e_virtchnl_vf_resource *msg)
6365 {
6366         struct i40e_virtchnl_vsi_resource *vsi_res;
6367         int i;
6368
6369         vsi_res = &msg->vsi_res[0];
6370
6371         hw->dev_caps.num_vsis = msg->num_vsis;
6372         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6373         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6374         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6375         hw->dev_caps.dcb = msg->vf_offload_flags &
6376                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6377         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6378                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6379         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6380                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6381         for (i = 0; i < msg->num_vsis; i++) {
6382                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6383                         i40e_memcpy(hw->mac.perm_addr,
6384                                     vsi_res->default_mac_addr,
6385                                     I40E_ETH_LENGTH_OF_ADDRESS,
6386                                     I40E_NONDMA_TO_NONDMA);
6387                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6388                                     I40E_ETH_LENGTH_OF_ADDRESS,
6389                                     I40E_NONDMA_TO_NONDMA);
6390                 }
6391                 vsi_res++;
6392         }
6393 }
6394
6395 /**
6396  * i40e_vf_reset
6397  * @hw: pointer to the hardware structure
6398  *
6399  * Send a VF_RESET message to the PF. Does not wait for response from PF
6400  * as none will be forthcoming. Immediately after calling this function,
6401  * the admin queue should be shut down and (optionally) reinitialized.
6402  **/
6403 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6404 {
6405         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6406                                       I40E_SUCCESS, NULL, 0, NULL);
6407 }
6408 #endif /* VF_DRIVER */
6409 #ifdef X722_SUPPORT
6410
6411 /**
6412  * i40e_aq_set_arp_proxy_config
6413  * @hw: pointer to the HW structure
6414  * @proxy_config - pointer to proxy config command table struct
6415  * @cmd_details: pointer to command details
6416  *
6417  * Set ARP offload parameters from pre-populated
6418  * i40e_aqc_arp_proxy_data struct
6419  **/
6420 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6421                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6422                                 struct i40e_asq_cmd_details *cmd_details)
6423 {
6424         struct i40e_aq_desc desc;
6425         enum i40e_status_code status;
6426
6427         if (!proxy_config)
6428                 return I40E_ERR_PARAM;
6429
6430         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6431
6432         desc.params.external.addr_high =
6433                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6434         desc.params.external.addr_low =
6435                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6436
6437         status = i40e_asq_send_command(hw, &desc, proxy_config,
6438                                        sizeof(struct i40e_aqc_arp_proxy_data),
6439                                        cmd_details);
6440
6441         return status;
6442 }
6443
6444 /**
6445  * i40e_aq_opc_set_ns_proxy_table_entry
6446  * @hw: pointer to the HW structure
6447  * @ns_proxy_table_entry: pointer to NS table entry command struct
6448  * @cmd_details: pointer to command details
6449  *
6450  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6451  * from pre-populated i40e_aqc_ns_proxy_data struct
6452  **/
6453 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6454                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6455                         struct i40e_asq_cmd_details *cmd_details)
6456 {
6457         struct i40e_aq_desc desc;
6458         enum i40e_status_code status;
6459
6460         if (!ns_proxy_table_entry)
6461                 return I40E_ERR_PARAM;
6462
6463         i40e_fill_default_direct_cmd_desc(&desc,
6464                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6465
6466         desc.params.external.addr_high =
6467                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6468         desc.params.external.addr_low =
6469                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6470
6471         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6472                                        sizeof(struct i40e_aqc_ns_proxy_data),
6473                                        cmd_details);
6474
6475         return status;
6476 }
6477
6478 /**
6479  * i40e_aq_set_clear_wol_filter
6480  * @hw: pointer to the hw struct
6481  * @filter_index: index of filter to modify (0-7)
6482  * @filter: buffer containing filter to be set
6483  * @set_filter: true to set filter, false to clear filter
6484  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6485  *              if false, pass through packets may cause wake-up
6486  * @filter_valid: true if filter action is valid
6487  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6488  * @cmd_details: pointer to command details structure or NULL
6489  *
6490  * Set or clear WoL filter for port attached to the PF
6491  **/
6492 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6493                                 u8 filter_index,
6494                                 struct i40e_aqc_set_wol_filter_data *filter,
6495                                 bool set_filter, bool no_wol_tco,
6496                                 bool filter_valid, bool no_wol_tco_valid,
6497                                 struct i40e_asq_cmd_details *cmd_details)
6498 {
6499         struct i40e_aq_desc desc;
6500         struct i40e_aqc_set_wol_filter *cmd =
6501                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6502         enum i40e_status_code status;
6503         u16 cmd_flags = 0;
6504         u16 valid_flags = 0;
6505         u16 buff_len = 0;
6506
6507         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6508
6509         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6510                 return  I40E_ERR_PARAM;
6511         cmd->filter_index = CPU_TO_LE16(filter_index);
6512
6513         if (set_filter) {
6514                 if (!filter)
6515                         return  I40E_ERR_PARAM;
6516                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6517                 buff_len = sizeof(*filter);
6518         }
6519         if (no_wol_tco)
6520                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6521         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6522
6523         if (filter_valid)
6524                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6525         if (no_wol_tco_valid)
6526                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6527         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6528
6529         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6530         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6531
6532         status = i40e_asq_send_command(hw, &desc, filter,
6533                                        buff_len, cmd_details);
6534
6535         return status;
6536 }
6537
6538 /**
6539  * i40e_aq_get_wake_event_reason
6540  * @hw: pointer to the hw struct
6541  * @wake_reason: return value, index of matching filter
6542  * @cmd_details: pointer to command details structure or NULL
6543  *
6544  * Get information for the reason of a Wake Up event
6545  **/
6546 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6547                                 u16 *wake_reason,
6548                                 struct i40e_asq_cmd_details *cmd_details)
6549 {
6550         struct i40e_aq_desc desc;
6551         struct i40e_aqc_get_wake_reason_completion *resp =
6552                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6553         enum i40e_status_code status;
6554
6555         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6556
6557         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6558
6559         if (status == I40E_SUCCESS)
6560                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6561
6562         return status;
6563 }
6564
6565 #endif /* X722_SUPPORT */