drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u16 len = LE16_TO_CPU(aq_desc->datalen);
 334         u8 *buf = (u8 *)buffer;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         i40e_debug(hw, mask,
 341                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 342                    LE16_TO_CPU(aq_desc->opcode),
 343                    LE16_TO_CPU(aq_desc->flags),
 344                    LE16_TO_CPU(aq_desc->datalen),
 345                    LE16_TO_CPU(aq_desc->retval));
 346         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 347                    LE32_TO_CPU(aq_desc->cookie_high),
 348                    LE32_TO_CPU(aq_desc->cookie_low));
 349         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->params.internal.param0),
 351                    LE32_TO_CPU(aq_desc->params.internal.param1));
 352         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 354                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 355
 356         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 357                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 358                 if (buf_len < len)
 359                         len = buf_len;
 360                 /* write the full 16-byte chunks */
 361                 for (i = 0; i < (len - 16); i += 16)
 362                         i40e_debug(hw, mask,
 363                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 364                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 365                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 366                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 367                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 368                 /* the most we could have left is 16 bytes, pad with zeros */
 369                 if (i < len) {
 370                         char d_buf[16];
 371                         int j, i_sav;
 372
 373                         i_sav = i;
 374                         memset(d_buf, 0, sizeof(d_buf));
 375                         for (j = 0; i < len; j++, i++)
 376                                 d_buf[j] = buf[i];
 377                         i40e_debug(hw, mask,
 378                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 379                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 380                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 381                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 382                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 383                 }
 384         }
 385 }
 386
 387 /**
 388  * i40e_check_asq_alive
 389  * @hw: pointer to the hw struct
 390  *
 391  * Returns true if Queue is enabled else false.
 392  **/
 393 bool i40e_check_asq_alive(struct i40e_hw *hw)
 394 {
 395         if (hw->aq.asq.len)
 396 #ifdef PF_DRIVER
 397 #ifdef INTEGRATED_VF
 398                 if (!i40e_is_vf(hw))
 399                         return !!(rd32(hw, hw->aq.asq.len) &
 400                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 401 #else
 402                 return !!(rd32(hw, hw->aq.asq.len) &
 403                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 404 #endif /* INTEGRATED_VF */
 405 #endif /* PF_DRIVER */
 406 #ifdef VF_DRIVER
 407 #ifdef INTEGRATED_VF
 408                 if (i40e_is_vf(hw))
 409                         return !!(rd32(hw, hw->aq.asq.len) &
 410                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 411 #else
 412                 return !!(rd32(hw, hw->aq.asq.len) &
 413                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 414 #endif /* INTEGRATED_VF */
 415 #endif /* VF_DRIVER */
 416         return false;
 417 }
 418
 419 /**
 420  * i40e_aq_queue_shutdown
 421  * @hw: pointer to the hw struct
 422  * @unloading: is the driver unloading itself
 423  *
 424  * Tell the Firmware that we're shutting down the AdminQ and whether
 425  * or not the driver is unloading as well.
 426  **/
 427 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 428                                              bool unloading)
 429 {
 430         struct i40e_aq_desc desc;
 431         struct i40e_aqc_queue_shutdown *cmd =
 432                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 433         enum i40e_status_code status;
 434
 435         i40e_fill_default_direct_cmd_desc(&desc,
 436                                           i40e_aqc_opc_queue_shutdown);
 437
 438         if (unloading)
 439                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 440         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 441
 442         return status;
 443 }
 444
 445 /**
 446  * i40e_aq_get_set_rss_lut
 447  * @hw: pointer to the hardware structure
 448  * @vsi_id: vsi fw index
 449  * @pf_lut: for PF table set true, for VSI table set false
 450  * @lut: pointer to the lut buffer provided by the caller
 451  * @lut_size: size of the lut buffer
 452  * @set: set true to set the table, false to get the table
 453  *
 454  * Internal function to get or set RSS look up table
 455  **/
 456 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 457                                                      u16 vsi_id, bool pf_lut,
 458                                                      u8 *lut, u16 lut_size,
 459                                                      bool set)
 460 {
 461         enum i40e_status_code status;
 462         struct i40e_aq_desc desc;
 463         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 464                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 465
 466         if (set)
 467                 i40e_fill_default_direct_cmd_desc(&desc,
 468                                                   i40e_aqc_opc_set_rss_lut);
 469         else
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_get_rss_lut);
 472
 473         /* Indirect command */
 474         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 475         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 476
 477         cmd_resp->vsi_id =
 478                         CPU_TO_LE16((u16)((vsi_id <<
 479                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 480                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 481         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 482
 483         if (pf_lut)
 484                 cmd_resp->flags |= CPU_TO_LE16((u16)
 485                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 486                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 487                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 488         else
 489                 cmd_resp->flags |= CPU_TO_LE16((u16)
 490                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 491                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 492                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 493
 494         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 495
 496         return status;
 497 }
 498
 499 /**
 500  * i40e_aq_get_rss_lut
 501  * @hw: pointer to the hardware structure
 502  * @vsi_id: vsi fw index
 503  * @pf_lut: for PF table set true, for VSI table set false
 504  * @lut: pointer to the lut buffer provided by the caller
 505  * @lut_size: size of the lut buffer
 506  *
 507  * get the RSS lookup table, PF or VSI type
 508  **/
 509 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 510                                           bool pf_lut, u8 *lut, u16 lut_size)
 511 {
 512         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 513                                        false);
 514 }
 515
 516 /**
 517  * i40e_aq_set_rss_lut
 518  * @hw: pointer to the hardware structure
 519  * @vsi_id: vsi fw index
 520  * @pf_lut: for PF table set true, for VSI table set false
 521  * @lut: pointer to the lut buffer provided by the caller
 522  * @lut_size: size of the lut buffer
 523  *
 524  * set the RSS lookup table, PF or VSI type
 525  **/
 526 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 527                                           bool pf_lut, u8 *lut, u16 lut_size)
 528 {
 529         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 530 }
 531
 532 /**
 533  * i40e_aq_get_set_rss_key
 534  * @hw: pointer to the hw struct
 535  * @vsi_id: vsi fw index
 536  * @key: pointer to key info struct
 537  * @set: set true to set the key, false to get the key
 538  *
 539  * get the RSS key per VSI
 540  **/
 541 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 542                                       u16 vsi_id,
 543                                       struct i40e_aqc_get_set_rss_key_data *key,
 544                                       bool set)
 545 {
 546         enum i40e_status_code status;
 547         struct i40e_aq_desc desc;
 548         struct i40e_aqc_get_set_rss_key *cmd_resp =
 549                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 550         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 551
 552         if (set)
 553                 i40e_fill_default_direct_cmd_desc(&desc,
 554                                                   i40e_aqc_opc_set_rss_key);
 555         else
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_get_rss_key);
 558
 559         /* Indirect command */
 560         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 562
 563         cmd_resp->vsi_id =
 564                         CPU_TO_LE16((u16)((vsi_id <<
 565                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 566                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 567         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 568
 569         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 570
 571         return status;
 572 }
 573
 574 /**
 575  * i40e_aq_get_rss_key
 576  * @hw: pointer to the hw struct
 577  * @vsi_id: vsi fw index
 578  * @key: pointer to key info struct
 579  *
 580  **/
 581 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 582                                       u16 vsi_id,
 583                                       struct i40e_aqc_get_set_rss_key_data *key)
 584 {
 585         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 586 }
 587
 588 /**
 589  * i40e_aq_set_rss_key
 590  * @hw: pointer to the hw struct
 591  * @vsi_id: vsi fw index
 592  * @key: pointer to key info struct
 593  *
 594  * set the RSS key per VSI
 595  **/
 596 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 597                                       u16 vsi_id,
 598                                       struct i40e_aqc_get_set_rss_key_data *key)
 599 {
 600         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 601 }
 602
 603 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 604  * hardware to a bit-field that can be used by SW to more easily determine the
 605  * packet type.
 606  *
 607  * Macros are used to shorten the table lines and make this table human
 608  * readable.
 609  *
 610  * We store the PTYPE in the top byte of the bit field - this is just so that
 611  * we can check that the table doesn't have a row missing, as the index into
 612  * the table should be the PTYPE.
 613  *
 614  * Typical work flow:
 615  *
 616  * IF NOT i40e_ptype_lookup[ptype].known
 617  * THEN
 618  *      Packet is unknown
 619  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 620  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 621  * ELSE
 622  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 623  * ENDIF
 624  */
 625
 626 /* macro to make the table lines short */
 627 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 628         {       PTYPE, \
 629                 1, \
 630                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 631                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 632                 I40E_RX_PTYPE_##OUTER_FRAG, \
 633                 I40E_RX_PTYPE_TUNNEL_##T, \
 634                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 635                 I40E_RX_PTYPE_##TEF, \
 636                 I40E_RX_PTYPE_INNER_PROT_##I, \
 637                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 638
 639 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 640                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 641
 642 /* shorter macros makes the table fit but are terse */
 643 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 644 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 645 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 646
 647 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 648 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 649         /* L2 Packet types */
 650         I40E_PTT_UNUSED_ENTRY(0),
 651         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 652         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 653         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT_UNUSED_ENTRY(4),
 655         I40E_PTT_UNUSED_ENTRY(5),
 656         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 657         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(8),
 659         I40E_PTT_UNUSED_ENTRY(9),
 660         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 662         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 663         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 664         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672
 673         /* Non Tunneled IPv4 */
 674         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 677         I40E_PTT_UNUSED_ENTRY(25),
 678         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 679         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 680         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 681
 682         /* IPv4 --> IPv4 */
 683         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 684         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 685         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 686         I40E_PTT_UNUSED_ENTRY(32),
 687         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 688         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 689         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 690
 691         /* IPv4 --> IPv6 */
 692         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 693         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 694         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 695         I40E_PTT_UNUSED_ENTRY(39),
 696         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 697         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 698         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 699
 700         /* IPv4 --> GRE/NAT */
 701         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 702
 703         /* IPv4 --> GRE/NAT --> IPv4 */
 704         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 705         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 706         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 707         I40E_PTT_UNUSED_ENTRY(47),
 708         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 709         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 710         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 711
 712         /* IPv4 --> GRE/NAT --> IPv6 */
 713         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 714         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 715         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 716         I40E_PTT_UNUSED_ENTRY(54),
 717         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 718         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 719         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 720
 721         /* IPv4 --> GRE/NAT --> MAC */
 722         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 723
 724         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 725         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 726         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 727         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 728         I40E_PTT_UNUSED_ENTRY(62),
 729         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 730         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 731         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 732
 733         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 734         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 735         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 736         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 737         I40E_PTT_UNUSED_ENTRY(69),
 738         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 739         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 740         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 741
 742         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 743         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 744
 745         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 746         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 747         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 748         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 749         I40E_PTT_UNUSED_ENTRY(77),
 750         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 751         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 752         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 753
 754         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 755         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 756         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 757         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 758         I40E_PTT_UNUSED_ENTRY(84),
 759         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 760         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 761         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 762
 763         /* Non Tunneled IPv6 */
 764         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 765         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 766         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 767         I40E_PTT_UNUSED_ENTRY(91),
 768         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 769         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 770         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 771
 772         /* IPv6 --> IPv4 */
 773         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 774         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 775         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 776         I40E_PTT_UNUSED_ENTRY(98),
 777         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 778         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 779         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 780
 781         /* IPv6 --> IPv6 */
 782         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 783         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 784         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 785         I40E_PTT_UNUSED_ENTRY(105),
 786         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 787         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 788         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 789
 790         /* IPv6 --> GRE/NAT */
 791         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 792
 793         /* IPv6 --> GRE/NAT -> IPv4 */
 794         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 795         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 796         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 797         I40E_PTT_UNUSED_ENTRY(113),
 798         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 799         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 800         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 801
 802         /* IPv6 --> GRE/NAT -> IPv6 */
 803         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 804         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 805         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 806         I40E_PTT_UNUSED_ENTRY(120),
 807         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 808         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 809         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 810
 811         /* IPv6 --> GRE/NAT -> MAC */
 812         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 813
 814         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 815         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 816         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 817         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 818         I40E_PTT_UNUSED_ENTRY(128),
 819         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 820         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 821         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 822
 823         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 824         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 825         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 826         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 827         I40E_PTT_UNUSED_ENTRY(135),
 828         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 829         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 830         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 831
 832         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 833         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 834
 835         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 836         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 837         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 838         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 839         I40E_PTT_UNUSED_ENTRY(143),
 840         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 841         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 842         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 843
 844         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 845         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 846         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 847         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 848         I40E_PTT_UNUSED_ENTRY(150),
 849         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 850         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 851         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 852
 853         /* unused entries */
 854         I40E_PTT_UNUSED_ENTRY(154),
 855         I40E_PTT_UNUSED_ENTRY(155),
 856         I40E_PTT_UNUSED_ENTRY(156),
 857         I40E_PTT_UNUSED_ENTRY(157),
 858         I40E_PTT_UNUSED_ENTRY(158),
 859         I40E_PTT_UNUSED_ENTRY(159),
 860
 861         I40E_PTT_UNUSED_ENTRY(160),
 862         I40E_PTT_UNUSED_ENTRY(161),
 863         I40E_PTT_UNUSED_ENTRY(162),
 864         I40E_PTT_UNUSED_ENTRY(163),
 865         I40E_PTT_UNUSED_ENTRY(164),
 866         I40E_PTT_UNUSED_ENTRY(165),
 867         I40E_PTT_UNUSED_ENTRY(166),
 868         I40E_PTT_UNUSED_ENTRY(167),
 869         I40E_PTT_UNUSED_ENTRY(168),
 870         I40E_PTT_UNUSED_ENTRY(169),
 871
 872         I40E_PTT_UNUSED_ENTRY(170),
 873         I40E_PTT_UNUSED_ENTRY(171),
 874         I40E_PTT_UNUSED_ENTRY(172),
 875         I40E_PTT_UNUSED_ENTRY(173),
 876         I40E_PTT_UNUSED_ENTRY(174),
 877         I40E_PTT_UNUSED_ENTRY(175),
 878         I40E_PTT_UNUSED_ENTRY(176),
 879         I40E_PTT_UNUSED_ENTRY(177),
 880         I40E_PTT_UNUSED_ENTRY(178),
 881         I40E_PTT_UNUSED_ENTRY(179),
 882
 883         I40E_PTT_UNUSED_ENTRY(180),
 884         I40E_PTT_UNUSED_ENTRY(181),
 885         I40E_PTT_UNUSED_ENTRY(182),
 886         I40E_PTT_UNUSED_ENTRY(183),
 887         I40E_PTT_UNUSED_ENTRY(184),
 888         I40E_PTT_UNUSED_ENTRY(185),
 889         I40E_PTT_UNUSED_ENTRY(186),
 890         I40E_PTT_UNUSED_ENTRY(187),
 891         I40E_PTT_UNUSED_ENTRY(188),
 892         I40E_PTT_UNUSED_ENTRY(189),
 893
 894         I40E_PTT_UNUSED_ENTRY(190),
 895         I40E_PTT_UNUSED_ENTRY(191),
 896         I40E_PTT_UNUSED_ENTRY(192),
 897         I40E_PTT_UNUSED_ENTRY(193),
 898         I40E_PTT_UNUSED_ENTRY(194),
 899         I40E_PTT_UNUSED_ENTRY(195),
 900         I40E_PTT_UNUSED_ENTRY(196),
 901         I40E_PTT_UNUSED_ENTRY(197),
 902         I40E_PTT_UNUSED_ENTRY(198),
 903         I40E_PTT_UNUSED_ENTRY(199),
 904
 905         I40E_PTT_UNUSED_ENTRY(200),
 906         I40E_PTT_UNUSED_ENTRY(201),
 907         I40E_PTT_UNUSED_ENTRY(202),
 908         I40E_PTT_UNUSED_ENTRY(203),
 909         I40E_PTT_UNUSED_ENTRY(204),
 910         I40E_PTT_UNUSED_ENTRY(205),
 911         I40E_PTT_UNUSED_ENTRY(206),
 912         I40E_PTT_UNUSED_ENTRY(207),
 913         I40E_PTT_UNUSED_ENTRY(208),
 914         I40E_PTT_UNUSED_ENTRY(209),
 915
 916         I40E_PTT_UNUSED_ENTRY(210),
 917         I40E_PTT_UNUSED_ENTRY(211),
 918         I40E_PTT_UNUSED_ENTRY(212),
 919         I40E_PTT_UNUSED_ENTRY(213),
 920         I40E_PTT_UNUSED_ENTRY(214),
 921         I40E_PTT_UNUSED_ENTRY(215),
 922         I40E_PTT_UNUSED_ENTRY(216),
 923         I40E_PTT_UNUSED_ENTRY(217),
 924         I40E_PTT_UNUSED_ENTRY(218),
 925         I40E_PTT_UNUSED_ENTRY(219),
 926
 927         I40E_PTT_UNUSED_ENTRY(220),
 928         I40E_PTT_UNUSED_ENTRY(221),
 929         I40E_PTT_UNUSED_ENTRY(222),
 930         I40E_PTT_UNUSED_ENTRY(223),
 931         I40E_PTT_UNUSED_ENTRY(224),
 932         I40E_PTT_UNUSED_ENTRY(225),
 933         I40E_PTT_UNUSED_ENTRY(226),
 934         I40E_PTT_UNUSED_ENTRY(227),
 935         I40E_PTT_UNUSED_ENTRY(228),
 936         I40E_PTT_UNUSED_ENTRY(229),
 937
 938         I40E_PTT_UNUSED_ENTRY(230),
 939         I40E_PTT_UNUSED_ENTRY(231),
 940         I40E_PTT_UNUSED_ENTRY(232),
 941         I40E_PTT_UNUSED_ENTRY(233),
 942         I40E_PTT_UNUSED_ENTRY(234),
 943         I40E_PTT_UNUSED_ENTRY(235),
 944         I40E_PTT_UNUSED_ENTRY(236),
 945         I40E_PTT_UNUSED_ENTRY(237),
 946         I40E_PTT_UNUSED_ENTRY(238),
 947         I40E_PTT_UNUSED_ENTRY(239),
 948
 949         I40E_PTT_UNUSED_ENTRY(240),
 950         I40E_PTT_UNUSED_ENTRY(241),
 951         I40E_PTT_UNUSED_ENTRY(242),
 952         I40E_PTT_UNUSED_ENTRY(243),
 953         I40E_PTT_UNUSED_ENTRY(244),
 954         I40E_PTT_UNUSED_ENTRY(245),
 955         I40E_PTT_UNUSED_ENTRY(246),
 956         I40E_PTT_UNUSED_ENTRY(247),
 957         I40E_PTT_UNUSED_ENTRY(248),
 958         I40E_PTT_UNUSED_ENTRY(249),
 959
 960         I40E_PTT_UNUSED_ENTRY(250),
 961         I40E_PTT_UNUSED_ENTRY(251),
 962         I40E_PTT_UNUSED_ENTRY(252),
 963         I40E_PTT_UNUSED_ENTRY(253),
 964         I40E_PTT_UNUSED_ENTRY(254),
 965         I40E_PTT_UNUSED_ENTRY(255)
 966 };
 967
 968
 969 /**
 970  * i40e_validate_mac_addr - Validate unicast MAC address
 971  * @mac_addr: pointer to MAC address
 972  *
 973  * Tests a MAC address to ensure it is a valid Individual Address
 974  **/
 975 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 976 {
 977         enum i40e_status_code status = I40E_SUCCESS;
 978
 979         DEBUGFUNC("i40e_validate_mac_addr");
 980
 981         /* Broadcast addresses ARE multicast addresses
 982          * Make sure it is not a multicast address
 983          * Reject the zero address
 984          */
 985         if (I40E_IS_MULTICAST(mac_addr) ||
 986             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 987               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 988                 status = I40E_ERR_INVALID_MAC_ADDR;
 989
 990         return status;
 991 }
 992 #ifdef PF_DRIVER
 993
 994 /**
 995  * i40e_init_shared_code - Initialize the shared code
 996  * @hw: pointer to hardware structure
 997  *
 998  * This assigns the MAC type and PHY code and inits the NVM.
 999  * Does not touch the hardware. This function must be called prior to any
1000  * other function in the shared code. The i40e_hw structure should be
1001  * memset to 0 prior to calling this function.  The following fields in
1002  * hw structure should be filled in prior to calling this function:
1003  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1004  * subsystem_vendor_id, and revision_id
1005  **/
1006 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1007 {
1008         enum i40e_status_code status = I40E_SUCCESS;
1009         u32 port, ari, func_rid;
1010
1011         DEBUGFUNC("i40e_init_shared_code");
1012
1013         i40e_set_mac_type(hw);
1014
1015         switch (hw->mac.type) {
1016         case I40E_MAC_XL710:
1017         case I40E_MAC_X722:
1018                 break;
1019         default:
1020                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1021         }
1022
1023         hw->phy.get_link_info = true;
1024
1025         /* Determine port number and PF number*/
1026         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1027                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1028         hw->port = (u8)port;
1029         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1030                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1031         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1032         if (ari)
1033                 hw->pf_id = (u8)(func_rid & 0xff);
1034         else
1035                 hw->pf_id = (u8)(func_rid & 0x7);
1036
1037         if (hw->mac.type == I40E_MAC_X722)
1038                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1039
1040         status = i40e_init_nvm(hw);
1041         return status;
1042 }
1043
1044 /**
1045  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046  * @hw: pointer to the hw struct
1047  * @flags: a return indicator of what addresses were added to the addr store
1048  * @addrs: the requestor's mac addr store
1049  * @cmd_details: pointer to command details structure or NULL
1050  **/
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1052                                    u16 *flags,
1053                                    struct i40e_aqc_mac_address_read_data *addrs,
1054                                    struct i40e_asq_cmd_details *cmd_details)
1055 {
1056         struct i40e_aq_desc desc;
1057         struct i40e_aqc_mac_address_read *cmd_data =
1058                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059         enum i40e_status_code status;
1060
1061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1063
1064         status = i40e_asq_send_command(hw, &desc, addrs,
1065                                        sizeof(*addrs), cmd_details);
1066         *flags = LE16_TO_CPU(cmd_data->command_flags);
1067
1068         return status;
1069 }
1070
1071 /**
1072  * i40e_aq_mac_address_write - Change the MAC addresses
1073  * @hw: pointer to the hw struct
1074  * @flags: indicates which MAC to be written
1075  * @mac_addr: address to write
1076  * @cmd_details: pointer to command details structure or NULL
1077  **/
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079                                     u16 flags, u8 *mac_addr,
1080                                     struct i40e_asq_cmd_details *cmd_details)
1081 {
1082         struct i40e_aq_desc desc;
1083         struct i40e_aqc_mac_address_write *cmd_data =
1084                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085         enum i40e_status_code status;
1086
1087         i40e_fill_default_direct_cmd_desc(&desc,
1088                                           i40e_aqc_opc_mac_address_write);
1089         cmd_data->command_flags = CPU_TO_LE16(flags);
1090         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092                                         ((u32)mac_addr[3] << 16) |
1093                                         ((u32)mac_addr[4] << 8) |
1094                                         mac_addr[5]);
1095
1096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1097
1098         return status;
1099 }
1100
1101 /**
1102  * i40e_get_mac_addr - get MAC address
1103  * @hw: pointer to the HW structure
1104  * @mac_addr: pointer to MAC address
1105  *
1106  * Reads the adapter's MAC address from register
1107  **/
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1109 {
1110         struct i40e_aqc_mac_address_read_data addrs;
1111         enum i40e_status_code status;
1112         u16 flags = 0;
1113
1114         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1115
1116         if (flags & I40E_AQC_LAN_ADDR_VALID)
1117                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1118                         I40E_NONDMA_TO_NONDMA);
1119
1120         return status;
1121 }
1122
1123 /**
1124  * i40e_get_port_mac_addr - get Port MAC address
1125  * @hw: pointer to the HW structure
1126  * @mac_addr: pointer to Port MAC address
1127  *
1128  * Reads the adapter's Port MAC address
1129  **/
1130 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1131 {
1132         struct i40e_aqc_mac_address_read_data addrs;
1133         enum i40e_status_code status;
1134         u16 flags = 0;
1135
1136         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1137         if (status)
1138                 return status;
1139
1140         if (flags & I40E_AQC_PORT_ADDR_VALID)
1141                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1142                         I40E_NONDMA_TO_NONDMA);
1143         else
1144                 status = I40E_ERR_INVALID_MAC_ADDR;
1145
1146         return status;
1147 }
1148
1149 /**
1150  * i40e_pre_tx_queue_cfg - pre tx queue configure
1151  * @hw: pointer to the HW structure
1152  * @queue: target pf queue index
1153  * @enable: state change request
1154  *
1155  * Handles hw requirement to indicate intention to enable
1156  * or disable target queue.
1157  **/
1158 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1159 {
1160         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1161         u32 reg_block = 0;
1162         u32 reg_val;
1163
1164         if (abs_queue_idx >= 128) {
1165                 reg_block = abs_queue_idx / 128;
1166                 abs_queue_idx %= 128;
1167         }
1168
1169         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1170         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1171         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1172
1173         if (enable)
1174                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1175         else
1176                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1177
1178         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1179 }
1180
1181 /**
1182  * i40e_get_san_mac_addr - get SAN MAC address
1183  * @hw: pointer to the HW structure
1184  * @mac_addr: pointer to SAN MAC address
1185  *
1186  * Reads the adapter's SAN MAC address from NVM
1187  **/
1188 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1189                                             u8 *mac_addr)
1190 {
1191         struct i40e_aqc_mac_address_read_data addrs;
1192         enum i40e_status_code status;
1193         u16 flags = 0;
1194
1195         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1196         if (status)
1197                 return status;
1198
1199         if (flags & I40E_AQC_SAN_ADDR_VALID)
1200                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1201                         I40E_NONDMA_TO_NONDMA);
1202         else
1203                 status = I40E_ERR_INVALID_MAC_ADDR;
1204
1205         return status;
1206 }
1207
1208 /**
1209  *  i40e_read_pba_string - Reads part number string from EEPROM
1210  *  @hw: pointer to hardware structure
1211  *  @pba_num: stores the part number string from the EEPROM
1212  *  @pba_num_size: part number string buffer length
1213  *
1214  *  Reads the part number string from the EEPROM.
1215  **/
1216 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1217                                             u32 pba_num_size)
1218 {
1219         enum i40e_status_code status = I40E_SUCCESS;
1220         u16 pba_word = 0;
1221         u16 pba_size = 0;
1222         u16 pba_ptr = 0;
1223         u16 i = 0;
1224
1225         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1226         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1227                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1228                 return status;
1229         }
1230
1231         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1232         if (status != I40E_SUCCESS) {
1233                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1234                 return status;
1235         }
1236
1237         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1238         if (status != I40E_SUCCESS) {
1239                 DEBUGOUT("Failed to read PBA Block size.\n");
1240                 return status;
1241         }
1242
1243         /* Subtract one to get PBA word count (PBA Size word is included in
1244          * total size)
1245          */
1246         pba_size--;
1247         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1248                 DEBUGOUT("Buffer to small for PBA data.\n");
1249                 return I40E_ERR_PARAM;
1250         }
1251
1252         for (i = 0; i < pba_size; i++) {
1253                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1254                 if (status != I40E_SUCCESS) {
1255                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1256                         return status;
1257                 }
1258
1259                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1260                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1261         }
1262         pba_num[(pba_size * 2)] = '\0';
1263
1264         return status;
1265 }
1266
1267 /**
1268  * i40e_get_media_type - Gets media type
1269  * @hw: pointer to the hardware structure
1270  **/
1271 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1272 {
1273         enum i40e_media_type media;
1274
1275         switch (hw->phy.link_info.phy_type) {
1276         case I40E_PHY_TYPE_10GBASE_SR:
1277         case I40E_PHY_TYPE_10GBASE_LR:
1278         case I40E_PHY_TYPE_1000BASE_SX:
1279         case I40E_PHY_TYPE_1000BASE_LX:
1280         case I40E_PHY_TYPE_40GBASE_SR4:
1281         case I40E_PHY_TYPE_40GBASE_LR4:
1282         case I40E_PHY_TYPE_25GBASE_LR:
1283         case I40E_PHY_TYPE_25GBASE_SR:
1284                 media = I40E_MEDIA_TYPE_FIBER;
1285                 break;
1286         case I40E_PHY_TYPE_100BASE_TX:
1287         case I40E_PHY_TYPE_1000BASE_T:
1288         case I40E_PHY_TYPE_10GBASE_T:
1289                 media = I40E_MEDIA_TYPE_BASET;
1290                 break;
1291         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1292         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1293         case I40E_PHY_TYPE_10GBASE_CR1:
1294         case I40E_PHY_TYPE_40GBASE_CR4:
1295         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1296         case I40E_PHY_TYPE_40GBASE_AOC:
1297         case I40E_PHY_TYPE_10GBASE_AOC:
1298         case I40E_PHY_TYPE_25GBASE_CR:
1299                 media = I40E_MEDIA_TYPE_DA;
1300                 break;
1301         case I40E_PHY_TYPE_1000BASE_KX:
1302         case I40E_PHY_TYPE_10GBASE_KX4:
1303         case I40E_PHY_TYPE_10GBASE_KR:
1304         case I40E_PHY_TYPE_40GBASE_KR4:
1305         case I40E_PHY_TYPE_20GBASE_KR2:
1306         case I40E_PHY_TYPE_25GBASE_KR:
1307                 media = I40E_MEDIA_TYPE_BACKPLANE;
1308                 break;
1309         case I40E_PHY_TYPE_SGMII:
1310         case I40E_PHY_TYPE_XAUI:
1311         case I40E_PHY_TYPE_XFI:
1312         case I40E_PHY_TYPE_XLAUI:
1313         case I40E_PHY_TYPE_XLPPI:
1314         default:
1315                 media = I40E_MEDIA_TYPE_UNKNOWN;
1316                 break;
1317         }
1318
1319         return media;
1320 }
1321
1322 #define I40E_PF_RESET_WAIT_COUNT        200
1323 /**
1324  * i40e_pf_reset - Reset the PF
1325  * @hw: pointer to the hardware structure
1326  *
1327  * Assuming someone else has triggered a global reset,
1328  * assure the global reset is complete and then reset the PF
1329  **/
1330 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1331 {
1332         u32 cnt = 0;
1333         u32 cnt1 = 0;
1334         u32 reg = 0;
1335         u32 grst_del;
1336
1337         /* Poll for Global Reset steady state in case of recent GRST.
1338          * The grst delay value is in 100ms units, and we'll wait a
1339          * couple counts longer to be sure we don't just miss the end.
1340          */
1341         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1342                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1343                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1344
1345         grst_del = grst_del * 20;
1346
1347         for (cnt = 0; cnt < grst_del; cnt++) {
1348                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1349                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1350                         break;
1351                 i40e_msec_delay(100);
1352         }
1353         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1354                 DEBUGOUT("Global reset polling failed to complete.\n");
1355                 return I40E_ERR_RESET_FAILED;
1356         }
1357
1358         /* Now Wait for the FW to be ready */
1359         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1360                 reg = rd32(hw, I40E_GLNVM_ULD);
1361                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1362                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1363                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1364                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1365                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1366                         break;
1367                 }
1368                 i40e_msec_delay(10);
1369         }
1370         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1372                 DEBUGOUT("wait for FW Reset complete timedout\n");
1373                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1374                 return I40E_ERR_RESET_FAILED;
1375         }
1376
1377         /* If there was a Global Reset in progress when we got here,
1378          * we don't need to do the PF Reset
1379          */
1380         if (!cnt) {
1381                 reg = rd32(hw, I40E_PFGEN_CTRL);
1382                 wr32(hw, I40E_PFGEN_CTRL,
1383                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1384                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1385                         reg = rd32(hw, I40E_PFGEN_CTRL);
1386                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1387                                 break;
1388                         i40e_msec_delay(1);
1389                 }
1390                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1391                         DEBUGOUT("PF reset polling failed to complete.\n");
1392                         return I40E_ERR_RESET_FAILED;
1393                 }
1394         }
1395
1396         i40e_clear_pxe_mode(hw);
1397
1398
1399         return I40E_SUCCESS;
1400 }
1401
1402 /**
1403  * i40e_clear_hw - clear out any left over hw state
1404  * @hw: pointer to the hw struct
1405  *
1406  * Clear queues and interrupts, typically called at init time,
1407  * but after the capabilities have been found so we know how many
1408  * queues and msix vectors have been allocated.
1409  **/
1410 void i40e_clear_hw(struct i40e_hw *hw)
1411 {
1412         u32 num_queues, base_queue;
1413         u32 num_pf_int;
1414         u32 num_vf_int;
1415         u32 num_vfs;
1416         u32 i, j;
1417         u32 val;
1418         u32 eol = 0x7ff;
1419
1420         /* get number of interrupts, queues, and vfs */
1421         val = rd32(hw, I40E_GLPCI_CNF2);
1422         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1423                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1424         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1425                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1426
1427         val = rd32(hw, I40E_PFLAN_QALLOC);
1428         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1429                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1430         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1431                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1432         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1433                 num_queues = (j - base_queue) + 1;
1434         else
1435                 num_queues = 0;
1436
1437         val = rd32(hw, I40E_PF_VT_PFALLOC);
1438         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1439                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1440         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1441                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1442         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1443                 num_vfs = (j - i) + 1;
1444         else
1445                 num_vfs = 0;
1446
1447         /* stop all the interrupts */
1448         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1449         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1450         for (i = 0; i < num_pf_int - 2; i++)
1451                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1452
1453         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1454         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1455         wr32(hw, I40E_PFINT_LNKLST0, val);
1456         for (i = 0; i < num_pf_int - 2; i++)
1457                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1458         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1459         for (i = 0; i < num_vfs; i++)
1460                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1461         for (i = 0; i < num_vf_int - 2; i++)
1462                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1463
1464         /* warn the HW of the coming Tx disables */
1465         for (i = 0; i < num_queues; i++) {
1466                 u32 abs_queue_idx = base_queue + i;
1467                 u32 reg_block = 0;
1468
1469                 if (abs_queue_idx >= 128) {
1470                         reg_block = abs_queue_idx / 128;
1471                         abs_queue_idx %= 128;
1472                 }
1473
1474                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1475                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1476                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1477                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1478
1479                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1480         }
1481         i40e_usec_delay(400);
1482
1483         /* stop all the queues */
1484         for (i = 0; i < num_queues; i++) {
1485                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1486                 wr32(hw, I40E_QTX_ENA(i), 0);
1487                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1488                 wr32(hw, I40E_QRX_ENA(i), 0);
1489         }
1490
1491         /* short wait for all queue disables to settle */
1492         i40e_usec_delay(50);
1493 }
1494
1495 /**
1496  * i40e_clear_pxe_mode - clear pxe operations mode
1497  * @hw: pointer to the hw struct
1498  *
1499  * Make sure all PXE mode settings are cleared, including things
1500  * like descriptor fetch/write-back mode.
1501  **/
1502 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1503 {
1504         if (i40e_check_asq_alive(hw))
1505                 i40e_aq_clear_pxe_mode(hw, NULL);
1506 }
1507
1508 /**
1509  * i40e_led_is_mine - helper to find matching led
1510  * @hw: pointer to the hw struct
1511  * @idx: index into GPIO registers
1512  *
1513  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1514  */
1515 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1516 {
1517         u32 gpio_val = 0;
1518         u32 port;
1519
1520         if (!hw->func_caps.led[idx])
1521                 return 0;
1522
1523         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1524         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1525                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1526
1527         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1528          * if it is not our port then ignore
1529          */
1530         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1531             (port != hw->port))
1532                 return 0;
1533
1534         return gpio_val;
1535 }
1536
1537 #define I40E_COMBINED_ACTIVITY 0xA
1538 #define I40E_FILTER_ACTIVITY 0xE
1539 #define I40E_LINK_ACTIVITY 0xC
1540 #define I40E_MAC_ACTIVITY 0xD
1541 #define I40E_LED0 22
1542
1543 /**
1544  * i40e_led_get - return current on/off mode
1545  * @hw: pointer to the hw struct
1546  *
1547  * The value returned is the 'mode' field as defined in the
1548  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1549  * values are variations of possible behaviors relating to
1550  * blink, link, and wire.
1551  **/
1552 u32 i40e_led_get(struct i40e_hw *hw)
1553 {
1554         u32 current_mode = 0;
1555         u32 mode = 0;
1556         int i;
1557
1558         /* as per the documentation GPIO 22-29 are the LED
1559          * GPIO pins named LED0..LED7
1560          */
1561         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1562                 u32 gpio_val = i40e_led_is_mine(hw, i);
1563
1564                 if (!gpio_val)
1565                         continue;
1566
1567                 /* ignore gpio LED src mode entries related to the activity
1568                  *  LEDs
1569                  */
1570                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1571                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1572                 switch (current_mode) {
1573                 case I40E_COMBINED_ACTIVITY:
1574                 case I40E_FILTER_ACTIVITY:
1575                 case I40E_MAC_ACTIVITY:
1576                         continue;
1577                 default:
1578                         break;
1579                 }
1580
1581                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1582                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1583                 break;
1584         }
1585
1586         return mode;
1587 }
1588
1589 /**
1590  * i40e_led_set - set new on/off mode
1591  * @hw: pointer to the hw struct
1592  * @mode: 0=off, 0xf=on (else see manual for mode details)
1593  * @blink: true if the LED should blink when on, false if steady
1594  *
1595  * if this function is used to turn on the blink it should
1596  * be used to disable the blink when restoring the original state.
1597  **/
1598 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1599 {
1600         u32 current_mode = 0;
1601         int i;
1602
1603         if (mode & 0xfffffff0)
1604                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1605
1606         /* as per the documentation GPIO 22-29 are the LED
1607          * GPIO pins named LED0..LED7
1608          */
1609         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1610                 u32 gpio_val = i40e_led_is_mine(hw, i);
1611
1612                 if (!gpio_val)
1613                         continue;
1614
1615                 /* ignore gpio LED src mode entries related to the activity
1616                  * LEDs
1617                  */
1618                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1619                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1620                 switch (current_mode) {
1621                 case I40E_COMBINED_ACTIVITY:
1622                 case I40E_FILTER_ACTIVITY:
1623                 case I40E_MAC_ACTIVITY:
1624                         continue;
1625                 default:
1626                         break;
1627                 }
1628
1629                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1630                 /* this & is a bit of paranoia, but serves as a range check */
1631                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1632                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1633
1634                 if (mode == I40E_LINK_ACTIVITY)
1635                         blink = false;
1636
1637                 if (blink)
1638                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1639                 else
1640                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1641
1642                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1643                 break;
1644         }
1645 }
1646
1647 /* Admin command wrappers */
1648
1649 /**
1650  * i40e_aq_get_phy_capabilities
1651  * @hw: pointer to the hw struct
1652  * @abilities: structure for PHY capabilities to be filled
1653  * @qualified_modules: report Qualified Modules
1654  * @report_init: report init capabilities (active are default)
1655  * @cmd_details: pointer to command details structure or NULL
1656  *
1657  * Returns the various PHY abilities supported on the Port.
1658  **/
1659 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1660                         bool qualified_modules, bool report_init,
1661                         struct i40e_aq_get_phy_abilities_resp *abilities,
1662                         struct i40e_asq_cmd_details *cmd_details)
1663 {
1664         struct i40e_aq_desc desc;
1665         enum i40e_status_code status;
1666         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1667
1668         if (!abilities)
1669                 return I40E_ERR_PARAM;
1670
1671         i40e_fill_default_direct_cmd_desc(&desc,
1672                                           i40e_aqc_opc_get_phy_abilities);
1673
1674         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1675         if (abilities_size > I40E_AQ_LARGE_BUF)
1676                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1677
1678         if (qualified_modules)
1679                 desc.params.external.param0 |=
1680                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1681
1682         if (report_init)
1683                 desc.params.external.param0 |=
1684                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1685
1686         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1687                                     cmd_details);
1688
1689         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1690                 status = I40E_ERR_UNKNOWN_PHY;
1691
1692         if (report_init) {
1693                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1694                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1695         }
1696
1697         return status;
1698 }
1699
1700 /**
1701  * i40e_aq_set_phy_config
1702  * @hw: pointer to the hw struct
1703  * @config: structure with PHY configuration to be set
1704  * @cmd_details: pointer to command details structure or NULL
1705  *
1706  * Set the various PHY configuration parameters
1707  * supported on the Port.One or more of the Set PHY config parameters may be
1708  * ignored in an MFP mode as the PF may not have the privilege to set some
1709  * of the PHY Config parameters. This status will be indicated by the
1710  * command response.
1711  **/
1712 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1713                                 struct i40e_aq_set_phy_config *config,
1714                                 struct i40e_asq_cmd_details *cmd_details)
1715 {
1716         struct i40e_aq_desc desc;
1717         struct i40e_aq_set_phy_config *cmd =
1718                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1719         enum i40e_status_code status;
1720
1721         if (!config)
1722                 return I40E_ERR_PARAM;
1723
1724         i40e_fill_default_direct_cmd_desc(&desc,
1725                                           i40e_aqc_opc_set_phy_config);
1726
1727         *cmd = *config;
1728
1729         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1730
1731         return status;
1732 }
1733
1734 /**
1735  * i40e_set_fc
1736  * @hw: pointer to the hw struct
1737  *
1738  * Set the requested flow control mode using set_phy_config.
1739  **/
1740 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1741                                   bool atomic_restart)
1742 {
1743         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1744         struct i40e_aq_get_phy_abilities_resp abilities;
1745         struct i40e_aq_set_phy_config config;
1746         enum i40e_status_code status;
1747         u8 pause_mask = 0x0;
1748
1749         *aq_failures = 0x0;
1750
1751         switch (fc_mode) {
1752         case I40E_FC_FULL:
1753                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1754                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1755                 break;
1756         case I40E_FC_RX_PAUSE:
1757                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1758                 break;
1759         case I40E_FC_TX_PAUSE:
1760                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1761                 break;
1762         default:
1763                 break;
1764         }
1765
1766         /* Get the current phy config */
1767         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1768                                               NULL);
1769         if (status) {
1770                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1771                 return status;
1772         }
1773
1774         memset(&config, 0, sizeof(config));
1775         /* clear the old pause settings */
1776         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1777                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1778         /* set the new abilities */
1779         config.abilities |= pause_mask;
1780         /* If the abilities have changed, then set the new config */
1781         if (config.abilities != abilities.abilities) {
1782                 /* Auto restart link so settings take effect */
1783                 if (atomic_restart)
1784                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1785                 /* Copy over all the old settings */
1786                 config.phy_type = abilities.phy_type;
1787                 config.phy_type_ext = abilities.phy_type_ext;
1788                 config.link_speed = abilities.link_speed;
1789                 config.eee_capability = abilities.eee_capability;
1790                 config.eeer = abilities.eeer_val;
1791                 config.low_power_ctrl = abilities.d3_lpan;
1792                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1793                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1794                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1795
1796                 if (status)
1797                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1798         }
1799         /* Update the link info */
1800         status = i40e_update_link_info(hw);
1801         if (status) {
1802                 /* Wait a little bit (on 40G cards it sometimes takes a really
1803                  * long time for link to come back from the atomic reset)
1804                  * and try once more
1805                  */
1806                 i40e_msec_delay(1000);
1807                 status = i40e_update_link_info(hw);
1808         }
1809         if (status)
1810                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1811
1812         return status;
1813 }
1814
1815 /**
1816  * i40e_aq_set_mac_config
1817  * @hw: pointer to the hw struct
1818  * @max_frame_size: Maximum Frame Size to be supported by the port
1819  * @crc_en: Tell HW to append a CRC to outgoing frames
1820  * @pacing: Pacing configurations
1821  * @cmd_details: pointer to command details structure or NULL
1822  *
1823  * Configure MAC settings for frame size, jumbo frame support and the
1824  * addition of a CRC by the hardware.
1825  **/
1826 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1827                                 u16 max_frame_size,
1828                                 bool crc_en, u16 pacing,
1829                                 struct i40e_asq_cmd_details *cmd_details)
1830 {
1831         struct i40e_aq_desc desc;
1832         struct i40e_aq_set_mac_config *cmd =
1833                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1834         enum i40e_status_code status;
1835
1836         if (max_frame_size == 0)
1837                 return I40E_ERR_PARAM;
1838
1839         i40e_fill_default_direct_cmd_desc(&desc,
1840                                           i40e_aqc_opc_set_mac_config);
1841
1842         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1843         cmd->params = ((u8)pacing & 0x0F) << 3;
1844         if (crc_en)
1845                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1846
1847         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1848
1849         return status;
1850 }
1851
1852 /**
1853  * i40e_aq_clear_pxe_mode
1854  * @hw: pointer to the hw struct
1855  * @cmd_details: pointer to command details structure or NULL
1856  *
1857  * Tell the firmware that the driver is taking over from PXE
1858  **/
1859 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1860                         struct i40e_asq_cmd_details *cmd_details)
1861 {
1862         enum i40e_status_code status;
1863         struct i40e_aq_desc desc;
1864         struct i40e_aqc_clear_pxe *cmd =
1865                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1866
1867         i40e_fill_default_direct_cmd_desc(&desc,
1868                                           i40e_aqc_opc_clear_pxe_mode);
1869
1870         cmd->rx_cnt = 0x2;
1871
1872         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1873
1874         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1875
1876         return status;
1877 }
1878
1879 /**
1880  * i40e_aq_set_link_restart_an
1881  * @hw: pointer to the hw struct
1882  * @enable_link: if true: enable link, if false: disable link
1883  * @cmd_details: pointer to command details structure or NULL
1884  *
1885  * Sets up the link and restarts the Auto-Negotiation over the link.
1886  **/
1887 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1888                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1889 {
1890         struct i40e_aq_desc desc;
1891         struct i40e_aqc_set_link_restart_an *cmd =
1892                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1893         enum i40e_status_code status;
1894
1895         i40e_fill_default_direct_cmd_desc(&desc,
1896                                           i40e_aqc_opc_set_link_restart_an);
1897
1898         cmd->command = I40E_AQ_PHY_RESTART_AN;
1899         if (enable_link)
1900                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1901         else
1902                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1903
1904         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1905
1906         return status;
1907 }
1908
1909 /**
1910  * i40e_aq_get_link_info
1911  * @hw: pointer to the hw struct
1912  * @enable_lse: enable/disable LinkStatusEvent reporting
1913  * @link: pointer to link status structure - optional
1914  * @cmd_details: pointer to command details structure or NULL
1915  *
1916  * Returns the link status of the adapter.
1917  **/
1918 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1919                                 bool enable_lse, struct i40e_link_status *link,
1920                                 struct i40e_asq_cmd_details *cmd_details)
1921 {
1922         struct i40e_aq_desc desc;
1923         struct i40e_aqc_get_link_status *resp =
1924                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1925         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1926         enum i40e_status_code status;
1927         bool tx_pause, rx_pause;
1928         u16 command_flags;
1929
1930         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1931
1932         if (enable_lse)
1933                 command_flags = I40E_AQ_LSE_ENABLE;
1934         else
1935                 command_flags = I40E_AQ_LSE_DISABLE;
1936         resp->command_flags = CPU_TO_LE16(command_flags);
1937
1938         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1939
1940         if (status != I40E_SUCCESS)
1941                 goto aq_get_link_info_exit;
1942
1943         /* save off old link status information */
1944         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1945                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1946
1947         /* update link status */
1948         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1949         hw->phy.media_type = i40e_get_media_type(hw);
1950         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1951         hw_link_info->link_info = resp->link_info;
1952         hw_link_info->an_info = resp->an_info;
1953         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1954                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1955         hw_link_info->ext_info = resp->ext_info;
1956         hw_link_info->loopback = resp->loopback;
1957         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1958         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1959
1960         /* update fc info */
1961         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1962         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1963         if (tx_pause & rx_pause)
1964                 hw->fc.current_mode = I40E_FC_FULL;
1965         else if (tx_pause)
1966                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1967         else if (rx_pause)
1968                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1969         else
1970                 hw->fc.current_mode = I40E_FC_NONE;
1971
1972         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1973                 hw_link_info->crc_enable = true;
1974         else
1975                 hw_link_info->crc_enable = false;
1976
1977         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1978                 hw_link_info->lse_enable = true;
1979         else
1980                 hw_link_info->lse_enable = false;
1981
1982         if ((hw->mac.type == I40E_MAC_XL710) &&
1983             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1984              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1985                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1986
1987         /* save link status information */
1988         if (link)
1989                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1990                             I40E_NONDMA_TO_NONDMA);
1991
1992         /* flag cleared so helper functions don't call AQ again */
1993         hw->phy.get_link_info = false;
1994
1995 aq_get_link_info_exit:
1996         return status;
1997 }
1998
1999 /**
2000  * i40e_aq_set_phy_int_mask
2001  * @hw: pointer to the hw struct
2002  * @mask: interrupt mask to be set
2003  * @cmd_details: pointer to command details structure or NULL
2004  *
2005  * Set link interrupt mask.
2006  **/
2007 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2008                                 u16 mask,
2009                                 struct i40e_asq_cmd_details *cmd_details)
2010 {
2011         struct i40e_aq_desc desc;
2012         struct i40e_aqc_set_phy_int_mask *cmd =
2013                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2014         enum i40e_status_code status;
2015
2016         i40e_fill_default_direct_cmd_desc(&desc,
2017                                           i40e_aqc_opc_set_phy_int_mask);
2018
2019         cmd->event_mask = CPU_TO_LE16(mask);
2020
2021         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2022
2023         return status;
2024 }
2025
2026 /**
2027  * i40e_aq_get_local_advt_reg
2028  * @hw: pointer to the hw struct
2029  * @advt_reg: local AN advertisement register value
2030  * @cmd_details: pointer to command details structure or NULL
2031  *
2032  * Get the Local AN advertisement register value.
2033  **/
2034 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2035                                 u64 *advt_reg,
2036                                 struct i40e_asq_cmd_details *cmd_details)
2037 {
2038         struct i40e_aq_desc desc;
2039         struct i40e_aqc_an_advt_reg *resp =
2040                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2041         enum i40e_status_code status;
2042
2043         i40e_fill_default_direct_cmd_desc(&desc,
2044                                           i40e_aqc_opc_get_local_advt_reg);
2045
2046         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2047
2048         if (status != I40E_SUCCESS)
2049                 goto aq_get_local_advt_reg_exit;
2050
2051         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2052         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2053
2054 aq_get_local_advt_reg_exit:
2055         return status;
2056 }
2057
2058 /**
2059  * i40e_aq_set_local_advt_reg
2060  * @hw: pointer to the hw struct
2061  * @advt_reg: local AN advertisement register value
2062  * @cmd_details: pointer to command details structure or NULL
2063  *
2064  * Get the Local AN advertisement register value.
2065  **/
2066 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2067                                 u64 advt_reg,
2068                                 struct i40e_asq_cmd_details *cmd_details)
2069 {
2070         struct i40e_aq_desc desc;
2071         struct i40e_aqc_an_advt_reg *cmd =
2072                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2073         enum i40e_status_code status;
2074
2075         i40e_fill_default_direct_cmd_desc(&desc,
2076                                           i40e_aqc_opc_get_local_advt_reg);
2077
2078         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2079         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2080
2081         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2082
2083         return status;
2084 }
2085
2086 /**
2087  * i40e_aq_get_partner_advt
2088  * @hw: pointer to the hw struct
2089  * @advt_reg: AN partner advertisement register value
2090  * @cmd_details: pointer to command details structure or NULL
2091  *
2092  * Get the link partner AN advertisement register value.
2093  **/
2094 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2095                                 u64 *advt_reg,
2096                                 struct i40e_asq_cmd_details *cmd_details)
2097 {
2098         struct i40e_aq_desc desc;
2099         struct i40e_aqc_an_advt_reg *resp =
2100                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2101         enum i40e_status_code status;
2102
2103         i40e_fill_default_direct_cmd_desc(&desc,
2104                                           i40e_aqc_opc_get_partner_advt);
2105
2106         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2107
2108         if (status != I40E_SUCCESS)
2109                 goto aq_get_partner_advt_exit;
2110
2111         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2112         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2113
2114 aq_get_partner_advt_exit:
2115         return status;
2116 }
2117
2118 /**
2119  * i40e_aq_set_lb_modes
2120  * @hw: pointer to the hw struct
2121  * @lb_modes: loopback mode to be set
2122  * @cmd_details: pointer to command details structure or NULL
2123  *
2124  * Sets loopback modes.
2125  **/
2126 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2127                                 u16 lb_modes,
2128                                 struct i40e_asq_cmd_details *cmd_details)
2129 {
2130         struct i40e_aq_desc desc;
2131         struct i40e_aqc_set_lb_mode *cmd =
2132                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2133         enum i40e_status_code status;
2134
2135         i40e_fill_default_direct_cmd_desc(&desc,
2136                                           i40e_aqc_opc_set_lb_modes);
2137
2138         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2139
2140         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2141
2142         return status;
2143 }
2144
2145 /**
2146  * i40e_aq_set_phy_debug
2147  * @hw: pointer to the hw struct
2148  * @cmd_flags: debug command flags
2149  * @cmd_details: pointer to command details structure or NULL
2150  *
2151  * Reset the external PHY.
2152  **/
2153 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2154                                 struct i40e_asq_cmd_details *cmd_details)
2155 {
2156         struct i40e_aq_desc desc;
2157         struct i40e_aqc_set_phy_debug *cmd =
2158                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2159         enum i40e_status_code status;
2160
2161         i40e_fill_default_direct_cmd_desc(&desc,
2162                                           i40e_aqc_opc_set_phy_debug);
2163
2164         cmd->command_flags = cmd_flags;
2165
2166         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2167
2168         return status;
2169 }
2170
2171 /**
2172  * i40e_aq_add_vsi
2173  * @hw: pointer to the hw struct
2174  * @vsi_ctx: pointer to a vsi context struct
2175  * @cmd_details: pointer to command details structure or NULL
2176  *
2177  * Add a VSI context to the hardware.
2178 **/
2179 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2180                                 struct i40e_vsi_context *vsi_ctx,
2181                                 struct i40e_asq_cmd_details *cmd_details)
2182 {
2183         struct i40e_aq_desc desc;
2184         struct i40e_aqc_add_get_update_vsi *cmd =
2185                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2186         struct i40e_aqc_add_get_update_vsi_completion *resp =
2187                 (struct i40e_aqc_add_get_update_vsi_completion *)
2188                 &desc.params.raw;
2189         enum i40e_status_code status;
2190
2191         i40e_fill_default_direct_cmd_desc(&desc,
2192                                           i40e_aqc_opc_add_vsi);
2193
2194         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2195         cmd->connection_type = vsi_ctx->connection_type;
2196         cmd->vf_id = vsi_ctx->vf_num;
2197         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2198
2199         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2200
2201         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2202                                     sizeof(vsi_ctx->info), cmd_details);
2203
2204         if (status != I40E_SUCCESS)
2205                 goto aq_add_vsi_exit;
2206
2207         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2208         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2209         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2210         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2211
2212 aq_add_vsi_exit:
2213         return status;
2214 }
2215
2216 /**
2217  * i40e_aq_set_default_vsi
2218  * @hw: pointer to the hw struct
2219  * @seid: vsi number
2220  * @cmd_details: pointer to command details structure or NULL
2221  **/
2222 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2223                                 u16 seid,
2224                                 struct i40e_asq_cmd_details *cmd_details)
2225 {
2226         struct i40e_aq_desc desc;
2227         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2228                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2229                 &desc.params.raw;
2230         enum i40e_status_code status;
2231
2232         i40e_fill_default_direct_cmd_desc(&desc,
2233                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2234
2235         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2236         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2237         cmd->seid = CPU_TO_LE16(seid);
2238
2239         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2240
2241         return status;
2242 }
2243
2244 /**
2245  * i40e_aq_clear_default_vsi
2246  * @hw: pointer to the hw struct
2247  * @seid: vsi number
2248  * @cmd_details: pointer to command details structure or NULL
2249  **/
2250 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2251                                 u16 seid,
2252                                 struct i40e_asq_cmd_details *cmd_details)
2253 {
2254         struct i40e_aq_desc desc;
2255         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2256                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2257                 &desc.params.raw;
2258         enum i40e_status_code status;
2259
2260         i40e_fill_default_direct_cmd_desc(&desc,
2261                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2262
2263         cmd->promiscuous_flags = CPU_TO_LE16(0);
2264         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2265         cmd->seid = CPU_TO_LE16(seid);
2266
2267         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2268
2269         return status;
2270 }
2271
2272 /**
2273  * i40e_aq_set_vsi_unicast_promiscuous
2274  * @hw: pointer to the hw struct
2275  * @seid: vsi number
2276  * @set: set unicast promiscuous enable/disable
2277  * @cmd_details: pointer to command details structure or NULL
2278  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2279  **/
2280 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2281                                 u16 seid, bool set,
2282                                 struct i40e_asq_cmd_details *cmd_details,
2283                                 bool rx_only_promisc)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288         enum i40e_status_code status;
2289         u16 flags = 0;
2290
2291         i40e_fill_default_direct_cmd_desc(&desc,
2292                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2293
2294         if (set) {
2295                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2296                 if (rx_only_promisc &&
2297                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2298                      (hw->aq.api_maj_ver > 1)))
2299                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2300         }
2301
2302         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2303
2304         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2305         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2306              (hw->aq.api_maj_ver > 1))
2307                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2308
2309         cmd->seid = CPU_TO_LE16(seid);
2310         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2311
2312         return status;
2313 }
2314
2315 /**
2316  * i40e_aq_set_vsi_multicast_promiscuous
2317  * @hw: pointer to the hw struct
2318  * @seid: vsi number
2319  * @set: set multicast promiscuous enable/disable
2320  * @cmd_details: pointer to command details structure or NULL
2321  **/
2322 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2323                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2324 {
2325         struct i40e_aq_desc desc;
2326         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2327                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2328         enum i40e_status_code status;
2329         u16 flags = 0;
2330
2331         i40e_fill_default_direct_cmd_desc(&desc,
2332                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2333
2334         if (set)
2335                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2336
2337         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2338
2339         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2340
2341         cmd->seid = CPU_TO_LE16(seid);
2342         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2343
2344         return status;
2345 }
2346
2347 /**
2348 * i40e_aq_set_vsi_full_promiscuous
2349 * @hw: pointer to the hw struct
2350 * @seid: VSI number
2351 * @set: set promiscuous enable/disable
2352 * @cmd_details: pointer to command details structure or NULL
2353 **/
2354 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2355                                 u16 seid, bool set,
2356                                 struct i40e_asq_cmd_details *cmd_details)
2357 {
2358         struct i40e_aq_desc desc;
2359         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2360                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2361         enum i40e_status_code status;
2362         u16 flags = 0;
2363
2364         i40e_fill_default_direct_cmd_desc(&desc,
2365                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2366
2367         if (set)
2368                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2369                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2370                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2371
2372         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2373
2374         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2375                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2376                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2377
2378         cmd->seid = CPU_TO_LE16(seid);
2379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2380
2381         return status;
2382 }
2383
2384 /**
2385  * i40e_aq_set_vsi_mc_promisc_on_vlan
2386  * @hw: pointer to the hw struct
2387  * @seid: vsi number
2388  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2389  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2390  * @cmd_details: pointer to command details structure or NULL
2391  **/
2392 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2393                                 u16 seid, bool enable, u16 vid,
2394                                 struct i40e_asq_cmd_details *cmd_details)
2395 {
2396         struct i40e_aq_desc desc;
2397         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2398                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2399         enum i40e_status_code status;
2400         u16 flags = 0;
2401
2402         i40e_fill_default_direct_cmd_desc(&desc,
2403                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2404
2405         if (enable)
2406                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2407
2408         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2409         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2410         cmd->seid = CPU_TO_LE16(seid);
2411         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2412
2413         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2414
2415         return status;
2416 }
2417
2418 /**
2419  * i40e_aq_set_vsi_uc_promisc_on_vlan
2420  * @hw: pointer to the hw struct
2421  * @seid: vsi number
2422  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2423  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2424  * @cmd_details: pointer to command details structure or NULL
2425  **/
2426 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2427                                 u16 seid, bool enable, u16 vid,
2428                                 struct i40e_asq_cmd_details *cmd_details)
2429 {
2430         struct i40e_aq_desc desc;
2431         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2432                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2433         enum i40e_status_code status;
2434         u16 flags = 0;
2435
2436         i40e_fill_default_direct_cmd_desc(&desc,
2437                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2438
2439         if (enable)
2440                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2441
2442         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2443         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2444         cmd->seid = CPU_TO_LE16(seid);
2445         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2446
2447         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2448
2449         return status;
2450 }
2451
2452 /**
2453  * i40e_aq_set_vsi_bc_promisc_on_vlan
2454  * @hw: pointer to the hw struct
2455  * @seid: vsi number
2456  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2457  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2458  * @cmd_details: pointer to command details structure or NULL
2459  **/
2460 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2461                                 u16 seid, bool enable, u16 vid,
2462                                 struct i40e_asq_cmd_details *cmd_details)
2463 {
2464         struct i40e_aq_desc desc;
2465         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2466                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2467         enum i40e_status_code status;
2468         u16 flags = 0;
2469
2470         i40e_fill_default_direct_cmd_desc(&desc,
2471                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2472
2473         if (enable)
2474                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2475
2476         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2477         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2478         cmd->seid = CPU_TO_LE16(seid);
2479         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2480
2481         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2482
2483         return status;
2484 }
2485
2486 /**
2487  * i40e_aq_set_vsi_broadcast
2488  * @hw: pointer to the hw struct
2489  * @seid: vsi number
2490  * @set_filter: true to set filter, false to clear filter
2491  * @cmd_details: pointer to command details structure or NULL
2492  *
2493  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2494  **/
2495 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2496                                 u16 seid, bool set_filter,
2497                                 struct i40e_asq_cmd_details *cmd_details)
2498 {
2499         struct i40e_aq_desc desc;
2500         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2501                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2502         enum i40e_status_code status;
2503
2504         i40e_fill_default_direct_cmd_desc(&desc,
2505                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2506
2507         if (set_filter)
2508                 cmd->promiscuous_flags
2509                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2510         else
2511                 cmd->promiscuous_flags
2512                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2513
2514         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2515         cmd->seid = CPU_TO_LE16(seid);
2516         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2517
2518         return status;
2519 }
2520
2521 /**
2522  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2523  * @hw: pointer to the hw struct
2524  * @seid: vsi number
2525  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2526  * @cmd_details: pointer to command details structure or NULL
2527  **/
2528 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2529                                 u16 seid, bool enable,
2530                                 struct i40e_asq_cmd_details *cmd_details)
2531 {
2532         struct i40e_aq_desc desc;
2533         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2534                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2535         enum i40e_status_code status;
2536         u16 flags = 0;
2537
2538         i40e_fill_default_direct_cmd_desc(&desc,
2539                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2540         if (enable)
2541                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2542
2543         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2544         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2545         cmd->seid = CPU_TO_LE16(seid);
2546
2547         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2548
2549         return status;
2550 }
2551
2552 /**
2553  * i40e_get_vsi_params - get VSI configuration info
2554  * @hw: pointer to the hw struct
2555  * @vsi_ctx: pointer to a vsi context struct
2556  * @cmd_details: pointer to command details structure or NULL
2557  **/
2558 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2559                                 struct i40e_vsi_context *vsi_ctx,
2560                                 struct i40e_asq_cmd_details *cmd_details)
2561 {
2562         struct i40e_aq_desc desc;
2563         struct i40e_aqc_add_get_update_vsi *cmd =
2564                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2565         struct i40e_aqc_add_get_update_vsi_completion *resp =
2566                 (struct i40e_aqc_add_get_update_vsi_completion *)
2567                 &desc.params.raw;
2568         enum i40e_status_code status;
2569
2570         UNREFERENCED_1PARAMETER(cmd_details);
2571         i40e_fill_default_direct_cmd_desc(&desc,
2572                                           i40e_aqc_opc_get_vsi_parameters);
2573
2574         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2575
2576         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2577
2578         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2579                                     sizeof(vsi_ctx->info), NULL);
2580
2581         if (status != I40E_SUCCESS)
2582                 goto aq_get_vsi_params_exit;
2583
2584         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2585         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2586         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2587         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2588
2589 aq_get_vsi_params_exit:
2590         return status;
2591 }
2592
2593 /**
2594  * i40e_aq_update_vsi_params
2595  * @hw: pointer to the hw struct
2596  * @vsi_ctx: pointer to a vsi context struct
2597  * @cmd_details: pointer to command details structure or NULL
2598  *
2599  * Update a VSI context.
2600  **/
2601 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2602                                 struct i40e_vsi_context *vsi_ctx,
2603                                 struct i40e_asq_cmd_details *cmd_details)
2604 {
2605         struct i40e_aq_desc desc;
2606         struct i40e_aqc_add_get_update_vsi *cmd =
2607                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2608         struct i40e_aqc_add_get_update_vsi_completion *resp =
2609                 (struct i40e_aqc_add_get_update_vsi_completion *)
2610                 &desc.params.raw;
2611         enum i40e_status_code status;
2612
2613         i40e_fill_default_direct_cmd_desc(&desc,
2614                                           i40e_aqc_opc_update_vsi_parameters);
2615         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2616
2617         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2618
2619         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2620                                     sizeof(vsi_ctx->info), cmd_details);
2621
2622         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2623         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2624
2625         return status;
2626 }
2627
2628 /**
2629  * i40e_aq_get_switch_config
2630  * @hw: pointer to the hardware structure
2631  * @buf: pointer to the result buffer
2632  * @buf_size: length of input buffer
2633  * @start_seid: seid to start for the report, 0 == beginning
2634  * @cmd_details: pointer to command details structure or NULL
2635  *
2636  * Fill the buf with switch configuration returned from AdminQ command
2637  **/
2638 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2639                                 struct i40e_aqc_get_switch_config_resp *buf,
2640                                 u16 buf_size, u16 *start_seid,
2641                                 struct i40e_asq_cmd_details *cmd_details)
2642 {
2643         struct i40e_aq_desc desc;
2644         struct i40e_aqc_switch_seid *scfg =
2645                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2646         enum i40e_status_code status;
2647
2648         i40e_fill_default_direct_cmd_desc(&desc,
2649                                           i40e_aqc_opc_get_switch_config);
2650         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2651         if (buf_size > I40E_AQ_LARGE_BUF)
2652                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2653         scfg->seid = CPU_TO_LE16(*start_seid);
2654
2655         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2656         *start_seid = LE16_TO_CPU(scfg->seid);
2657
2658         return status;
2659 }
2660
2661 /**
2662  * i40e_aq_set_switch_config
2663  * @hw: pointer to the hardware structure
2664  * @flags: bit flag values to set
2665  * @valid_flags: which bit flags to set
2666  * @cmd_details: pointer to command details structure or NULL
2667  *
2668  * Set switch configuration bits
2669  **/
2670 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2671                                 u16 flags, u16 valid_flags,
2672                                 struct i40e_asq_cmd_details *cmd_details)
2673 {
2674         struct i40e_aq_desc desc;
2675         struct i40e_aqc_set_switch_config *scfg =
2676                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2677         enum i40e_status_code status;
2678
2679         i40e_fill_default_direct_cmd_desc(&desc,
2680                                           i40e_aqc_opc_set_switch_config);
2681         scfg->flags = CPU_TO_LE16(flags);
2682         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2683
2684         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2685
2686         return status;
2687 }
2688
2689 /**
2690  * i40e_aq_get_firmware_version
2691  * @hw: pointer to the hw struct
2692  * @fw_major_version: firmware major version
2693  * @fw_minor_version: firmware minor version
2694  * @fw_build: firmware build number
2695  * @api_major_version: major queue version
2696  * @api_minor_version: minor queue version
2697  * @cmd_details: pointer to command details structure or NULL
2698  *
2699  * Get the firmware version from the admin queue commands
2700  **/
2701 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2702                                 u16 *fw_major_version, u16 *fw_minor_version,
2703                                 u32 *fw_build,
2704                                 u16 *api_major_version, u16 *api_minor_version,
2705                                 struct i40e_asq_cmd_details *cmd_details)
2706 {
2707         struct i40e_aq_desc desc;
2708         struct i40e_aqc_get_version *resp =
2709                 (struct i40e_aqc_get_version *)&desc.params.raw;
2710         enum i40e_status_code status;
2711
2712         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2713
2714         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2715
2716         if (status == I40E_SUCCESS) {
2717                 if (fw_major_version != NULL)
2718                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2719                 if (fw_minor_version != NULL)
2720                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2721                 if (fw_build != NULL)
2722                         *fw_build = LE32_TO_CPU(resp->fw_build);
2723                 if (api_major_version != NULL)
2724                         *api_major_version = LE16_TO_CPU(resp->api_major);
2725                 if (api_minor_version != NULL)
2726                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2727
2728                 /* A workaround to fix the API version in SW */
2729                 if (api_major_version && api_minor_version &&
2730                     fw_major_version && fw_minor_version &&
2731                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2732                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2733                      (*fw_major_version > 4)))
2734                         *api_minor_version = 2;
2735         }
2736
2737         return status;
2738 }
2739
2740 /**
2741  * i40e_aq_send_driver_version
2742  * @hw: pointer to the hw struct
2743  * @dv: driver's major, minor version
2744  * @cmd_details: pointer to command details structure or NULL
2745  *
2746  * Send the driver version to the firmware
2747  **/
2748 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2749                                 struct i40e_driver_version *dv,
2750                                 struct i40e_asq_cmd_details *cmd_details)
2751 {
2752         struct i40e_aq_desc desc;
2753         struct i40e_aqc_driver_version *cmd =
2754                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2755         enum i40e_status_code status;
2756         u16 len;
2757
2758         if (dv == NULL)
2759                 return I40E_ERR_PARAM;
2760
2761         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2762
2763         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2764         cmd->driver_major_ver = dv->major_version;
2765         cmd->driver_minor_ver = dv->minor_version;
2766         cmd->driver_build_ver = dv->build_version;
2767         cmd->driver_subbuild_ver = dv->subbuild_version;
2768
2769         len = 0;
2770         while (len < sizeof(dv->driver_string) &&
2771                (dv->driver_string[len] < 0x80) &&
2772                dv->driver_string[len])
2773                 len++;
2774         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2775                                        len, cmd_details);
2776
2777         return status;
2778 }
2779
2780 /**
2781  * i40e_get_link_status - get status of the HW network link
2782  * @hw: pointer to the hw struct
2783  * @link_up: pointer to bool (true/false = linkup/linkdown)
2784  *
2785  * Variable link_up true if link is up, false if link is down.
2786  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2787  *
2788  * Side effect: LinkStatusEvent reporting becomes enabled
2789  **/
2790 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2791 {
2792         enum i40e_status_code status = I40E_SUCCESS;
2793
2794         if (hw->phy.get_link_info) {
2795                 status = i40e_update_link_info(hw);
2796
2797                 if (status != I40E_SUCCESS)
2798                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2799                                    status);
2800         }
2801
2802         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2803
2804         return status;
2805 }
2806
2807 /**
2808  * i40e_updatelink_status - update status of the HW network link
2809  * @hw: pointer to the hw struct
2810  **/
2811 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2812 {
2813         struct i40e_aq_get_phy_abilities_resp abilities;
2814         enum i40e_status_code status = I40E_SUCCESS;
2815
2816         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2817         if (status)
2818                 return status;
2819
2820         /* extra checking needed to ensure link info to user is timely */
2821         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2822             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2823              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2824                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2825                                                       &abilities, NULL);
2826                 if (status)
2827                         return status;
2828
2829                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2830                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2831         }
2832         return status;
2833 }
2834
2835
2836 /**
2837  * i40e_get_link_speed
2838  * @hw: pointer to the hw struct
2839  *
2840  * Returns the link speed of the adapter.
2841  **/
2842 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2843 {
2844         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2845         enum i40e_status_code status = I40E_SUCCESS;
2846
2847         if (hw->phy.get_link_info) {
2848                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2849
2850                 if (status != I40E_SUCCESS)
2851                         goto i40e_link_speed_exit;
2852         }
2853
2854         speed = hw->phy.link_info.link_speed;
2855
2856 i40e_link_speed_exit:
2857         return speed;
2858 }
2859
2860 /**
2861  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2862  * @hw: pointer to the hw struct
2863  * @uplink_seid: the MAC or other gizmo SEID
2864  * @downlink_seid: the VSI SEID
2865  * @enabled_tc: bitmap of TCs to be enabled
2866  * @default_port: true for default port VSI, false for control port
2867  * @veb_seid: pointer to where to put the resulting VEB SEID
2868  * @enable_stats: true to turn on VEB stats
2869  * @cmd_details: pointer to command details structure or NULL
2870  *
2871  * This asks the FW to add a VEB between the uplink and downlink
2872  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2873  **/
2874 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2875                                 u16 downlink_seid, u8 enabled_tc,
2876                                 bool default_port, u16 *veb_seid,
2877                                 bool enable_stats,
2878                                 struct i40e_asq_cmd_details *cmd_details)
2879 {
2880         struct i40e_aq_desc desc;
2881         struct i40e_aqc_add_veb *cmd =
2882                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2883         struct i40e_aqc_add_veb_completion *resp =
2884                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2885         enum i40e_status_code status;
2886         u16 veb_flags = 0;
2887
2888         /* SEIDs need to either both be set or both be 0 for floating VEB */
2889         if (!!uplink_seid != !!downlink_seid)
2890                 return I40E_ERR_PARAM;
2891
2892         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2893
2894         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2895         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2896         cmd->enable_tcs = enabled_tc;
2897         if (!uplink_seid)
2898                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2899         if (default_port)
2900                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2901         else
2902                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2903
2904         /* reverse logic here: set the bitflag to disable the stats */
2905         if (!enable_stats)
2906                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2907
2908         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2909
2910         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2911
2912         if (!status && veb_seid)
2913                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2914
2915         return status;
2916 }
2917
2918 /**
2919  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2920  * @hw: pointer to the hw struct
2921  * @veb_seid: the SEID of the VEB to query
2922  * @switch_id: the uplink switch id
2923  * @floating: set to true if the VEB is floating
2924  * @statistic_index: index of the stats counter block for this VEB
2925  * @vebs_used: number of VEB's used by function
2926  * @vebs_free: total VEB's not reserved by any function
2927  * @cmd_details: pointer to command details structure or NULL
2928  *
2929  * This retrieves the parameters for a particular VEB, specified by
2930  * uplink_seid, and returns them to the caller.
2931  **/
2932 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2933                                 u16 veb_seid, u16 *switch_id,
2934                                 bool *floating, u16 *statistic_index,
2935                                 u16 *vebs_used, u16 *vebs_free,
2936                                 struct i40e_asq_cmd_details *cmd_details)
2937 {
2938         struct i40e_aq_desc desc;
2939         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2940                 (struct i40e_aqc_get_veb_parameters_completion *)
2941                 &desc.params.raw;
2942         enum i40e_status_code status;
2943
2944         if (veb_seid == 0)
2945                 return I40E_ERR_PARAM;
2946
2947         i40e_fill_default_direct_cmd_desc(&desc,
2948                                           i40e_aqc_opc_get_veb_parameters);
2949         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2950
2951         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2952         if (status)
2953                 goto get_veb_exit;
2954
2955         if (switch_id)
2956                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2957         if (statistic_index)
2958                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2959         if (vebs_used)
2960                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2961         if (vebs_free)
2962                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2963         if (floating) {
2964                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2965
2966                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2967                         *floating = true;
2968                 else
2969                         *floating = false;
2970         }
2971
2972 get_veb_exit:
2973         return status;
2974 }
2975
2976 /**
2977  * i40e_aq_add_macvlan
2978  * @hw: pointer to the hw struct
2979  * @seid: VSI for the mac address
2980  * @mv_list: list of macvlans to be added
2981  * @count: length of the list
2982  * @cmd_details: pointer to command details structure or NULL
2983  *
2984  * Add MAC/VLAN addresses to the HW filtering
2985  **/
2986 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2987                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2988                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2989 {
2990         struct i40e_aq_desc desc;
2991         struct i40e_aqc_macvlan *cmd =
2992                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2993         enum i40e_status_code status;
2994         u16 buf_size;
2995         int i;
2996
2997         if (count == 0 || !mv_list || !hw)
2998                 return I40E_ERR_PARAM;
2999
3000         buf_size = count * sizeof(*mv_list);
3001
3002         /* prep the rest of the request */
3003         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3004         cmd->num_addresses = CPU_TO_LE16(count);
3005         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3006         cmd->seid[1] = 0;
3007         cmd->seid[2] = 0;
3008
3009         for (i = 0; i < count; i++)
3010                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3011                         mv_list[i].flags |=
3012                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3013
3014         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3015         if (buf_size > I40E_AQ_LARGE_BUF)
3016                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3017
3018         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3019                                        cmd_details);
3020
3021         return status;
3022 }
3023
3024 /**
3025  * i40e_aq_remove_macvlan
3026  * @hw: pointer to the hw struct
3027  * @seid: VSI for the mac address
3028  * @mv_list: list of macvlans to be removed
3029  * @count: length of the list
3030  * @cmd_details: pointer to command details structure or NULL
3031  *
3032  * Remove MAC/VLAN addresses from the HW filtering
3033  **/
3034 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3035                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3036                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3037 {
3038         struct i40e_aq_desc desc;
3039         struct i40e_aqc_macvlan *cmd =
3040                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3041         enum i40e_status_code status;
3042         u16 buf_size;
3043
3044         if (count == 0 || !mv_list || !hw)
3045                 return I40E_ERR_PARAM;
3046
3047         buf_size = count * sizeof(*mv_list);
3048
3049         /* prep the rest of the request */
3050         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3051         cmd->num_addresses = CPU_TO_LE16(count);
3052         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3053         cmd->seid[1] = 0;
3054         cmd->seid[2] = 0;
3055
3056         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3057         if (buf_size > I40E_AQ_LARGE_BUF)
3058                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3059
3060         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3061                                        cmd_details);
3062
3063         return status;
3064 }
3065
3066 /**
3067  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3068  * @hw: pointer to the hw struct
3069  * @opcode: AQ opcode for add or delete mirror rule
3070  * @sw_seid: Switch SEID (to which rule refers)
3071  * @rule_type: Rule Type (ingress/egress/VLAN)
3072  * @id: Destination VSI SEID or Rule ID
3073  * @count: length of the list
3074  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3075  * @cmd_details: pointer to command details structure or NULL
3076  * @rule_id: Rule ID returned from FW
3077  * @rule_used: Number of rules used in internal switch
3078  * @rule_free: Number of rules free in internal switch
3079  *
3080  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3081  * VEBs/VEPA elements only
3082  **/
3083 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3084                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3085                         u16 count, __le16 *mr_list,
3086                         struct i40e_asq_cmd_details *cmd_details,
3087                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3088 {
3089         struct i40e_aq_desc desc;
3090         struct i40e_aqc_add_delete_mirror_rule *cmd =
3091                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3092         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3093         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3094         enum i40e_status_code status;
3095         u16 buf_size;
3096
3097         buf_size = count * sizeof(*mr_list);
3098
3099         /* prep the rest of the request */
3100         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3101         cmd->seid = CPU_TO_LE16(sw_seid);
3102         cmd->rule_type = CPU_TO_LE16(rule_type &
3103                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3104         cmd->num_entries = CPU_TO_LE16(count);
3105         /* Dest VSI for add, rule_id for delete */
3106         cmd->destination = CPU_TO_LE16(id);
3107         if (mr_list) {
3108                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3109                                                 I40E_AQ_FLAG_RD));
3110                 if (buf_size > I40E_AQ_LARGE_BUF)
3111                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3112         }
3113
3114         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3115                                        cmd_details);
3116         if (status == I40E_SUCCESS ||
3117             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3118                 if (rule_id)
3119                         *rule_id = LE16_TO_CPU(resp->rule_id);
3120                 if (rules_used)
3121                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3122                 if (rules_free)
3123                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3124         }
3125         return status;
3126 }
3127
3128 /**
3129  * i40e_aq_add_mirrorrule - add a mirror rule
3130  * @hw: pointer to the hw struct
3131  * @sw_seid: Switch SEID (to which rule refers)
3132  * @rule_type: Rule Type (ingress/egress/VLAN)
3133  * @dest_vsi: SEID of VSI to which packets will be mirrored
3134  * @count: length of the list
3135  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3136  * @cmd_details: pointer to command details structure or NULL
3137  * @rule_id: Rule ID returned from FW
3138  * @rule_used: Number of rules used in internal switch
3139  * @rule_free: Number of rules free in internal switch
3140  *
3141  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3142  **/
3143 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3144                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3145                         struct i40e_asq_cmd_details *cmd_details,
3146                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3147 {
3148         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3149             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3150                 if (count == 0 || !mr_list)
3151                         return I40E_ERR_PARAM;
3152         }
3153
3154         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3155                                   rule_type, dest_vsi, count, mr_list,
3156                                   cmd_details, rule_id, rules_used, rules_free);
3157 }
3158
3159 /**
3160  * i40e_aq_delete_mirrorrule - delete a mirror rule
3161  * @hw: pointer to the hw struct
3162  * @sw_seid: Switch SEID (to which rule refers)
3163  * @rule_type: Rule Type (ingress/egress/VLAN)
3164  * @count: length of the list
3165  * @rule_id: Rule ID that is returned in the receive desc as part of
3166  *              add_mirrorrule.
3167  * @mr_list: list of mirrored VLAN IDs to be removed
3168  * @cmd_details: pointer to command details structure or NULL
3169  * @rule_used: Number of rules used in internal switch
3170  * @rule_free: Number of rules free in internal switch
3171  *
3172  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3173  **/
3174 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3175                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3176                         struct i40e_asq_cmd_details *cmd_details,
3177                         u16 *rules_used, u16 *rules_free)
3178 {
3179         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3180         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3181                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3182                  * mirroring. For other rule_type, count and rule_type should
3183                  * not matter.
3184                  */
3185                 if (count == 0 || !mr_list)
3186                         return I40E_ERR_PARAM;
3187         }
3188
3189         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3190                                   rule_type, rule_id, count, mr_list,
3191                                   cmd_details, NULL, rules_used, rules_free);
3192 }
3193
3194 /**
3195  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3196  * @hw: pointer to the hw struct
3197  * @seid: VSI for the vlan filters
3198  * @v_list: list of vlan filters to be added
3199  * @count: length of the list
3200  * @cmd_details: pointer to command details structure or NULL
3201  **/
3202 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3203                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3204                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3205 {
3206         struct i40e_aq_desc desc;
3207         struct i40e_aqc_macvlan *cmd =
3208                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3209         enum i40e_status_code status;
3210         u16 buf_size;
3211
3212         if (count == 0 || !v_list || !hw)
3213                 return I40E_ERR_PARAM;
3214
3215         buf_size = count * sizeof(*v_list);
3216
3217         /* prep the rest of the request */
3218         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3219         cmd->num_addresses = CPU_TO_LE16(count);
3220         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3221         cmd->seid[1] = 0;
3222         cmd->seid[2] = 0;
3223
3224         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3225         if (buf_size > I40E_AQ_LARGE_BUF)
3226                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3227
3228         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3229                                        cmd_details);
3230
3231         return status;
3232 }
3233
3234 /**
3235  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3236  * @hw: pointer to the hw struct
3237  * @seid: VSI for the vlan filters
3238  * @v_list: list of macvlans to be removed
3239  * @count: length of the list
3240  * @cmd_details: pointer to command details structure or NULL
3241  **/
3242 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3243                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3244                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3245 {
3246         struct i40e_aq_desc desc;
3247         struct i40e_aqc_macvlan *cmd =
3248                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3249         enum i40e_status_code status;
3250         u16 buf_size;
3251
3252         if (count == 0 || !v_list || !hw)
3253                 return I40E_ERR_PARAM;
3254
3255         buf_size = count * sizeof(*v_list);
3256
3257         /* prep the rest of the request */
3258         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3259         cmd->num_addresses = CPU_TO_LE16(count);
3260         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3261         cmd->seid[1] = 0;
3262         cmd->seid[2] = 0;
3263
3264         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3265         if (buf_size > I40E_AQ_LARGE_BUF)
3266                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3267
3268         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3269                                        cmd_details);
3270
3271         return status;
3272 }
3273
3274 /**
3275  * i40e_aq_send_msg_to_vf
3276  * @hw: pointer to the hardware structure
3277  * @vfid: vf id to send msg
3278  * @v_opcode: opcodes for VF-PF communication
3279  * @v_retval: return error code
3280  * @msg: pointer to the msg buffer
3281  * @msglen: msg length
3282  * @cmd_details: pointer to command details
3283  *
3284  * send msg to vf
3285  **/
3286 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3287                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3288                                 struct i40e_asq_cmd_details *cmd_details)
3289 {
3290         struct i40e_aq_desc desc;
3291         struct i40e_aqc_pf_vf_message *cmd =
3292                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3293         enum i40e_status_code status;
3294
3295         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3296         cmd->id = CPU_TO_LE32(vfid);
3297         desc.cookie_high = CPU_TO_LE32(v_opcode);
3298         desc.cookie_low = CPU_TO_LE32(v_retval);
3299         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3300         if (msglen) {
3301                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3302                                                 I40E_AQ_FLAG_RD));
3303                 if (msglen > I40E_AQ_LARGE_BUF)
3304                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3305                 desc.datalen = CPU_TO_LE16(msglen);
3306         }
3307         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3308
3309         return status;
3310 }
3311
3312 /**
3313  * i40e_aq_debug_read_register
3314  * @hw: pointer to the hw struct
3315  * @reg_addr: register address
3316  * @reg_val: register value
3317  * @cmd_details: pointer to command details structure or NULL
3318  *
3319  * Read the register using the admin queue commands
3320  **/
3321 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3322                                 u32 reg_addr, u64 *reg_val,
3323                                 struct i40e_asq_cmd_details *cmd_details)
3324 {
3325         struct i40e_aq_desc desc;
3326         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3327                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3328         enum i40e_status_code status;
3329
3330         if (reg_val == NULL)
3331                 return I40E_ERR_PARAM;
3332
3333         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3334
3335         cmd_resp->address = CPU_TO_LE32(reg_addr);
3336
3337         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3338
3339         if (status == I40E_SUCCESS) {
3340                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3341                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3342         }
3343
3344         return status;
3345 }
3346
3347 /**
3348  * i40e_aq_debug_write_register
3349  * @hw: pointer to the hw struct
3350  * @reg_addr: register address
3351  * @reg_val: register value
3352  * @cmd_details: pointer to command details structure or NULL
3353  *
3354  * Write to a register using the admin queue commands
3355  **/
3356 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3357                                 u32 reg_addr, u64 reg_val,
3358                                 struct i40e_asq_cmd_details *cmd_details)
3359 {
3360         struct i40e_aq_desc desc;
3361         struct i40e_aqc_debug_reg_read_write *cmd =
3362                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3363         enum i40e_status_code status;
3364
3365         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3366
3367         cmd->address = CPU_TO_LE32(reg_addr);
3368         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3369         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3370
3371         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3372
3373         return status;
3374 }
3375
3376 /**
3377  * i40e_aq_request_resource
3378  * @hw: pointer to the hw struct
3379  * @resource: resource id
3380  * @access: access type
3381  * @sdp_number: resource number
3382  * @timeout: the maximum time in ms that the driver may hold the resource
3383  * @cmd_details: pointer to command details structure or NULL
3384  *
3385  * requests common resource using the admin queue commands
3386  **/
3387 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3388                                 enum i40e_aq_resources_ids resource,
3389                                 enum i40e_aq_resource_access_type access,
3390                                 u8 sdp_number, u64 *timeout,
3391                                 struct i40e_asq_cmd_details *cmd_details)
3392 {
3393         struct i40e_aq_desc desc;
3394         struct i40e_aqc_request_resource *cmd_resp =
3395                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3396         enum i40e_status_code status;
3397
3398         DEBUGFUNC("i40e_aq_request_resource");
3399
3400         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3401
3402         cmd_resp->resource_id = CPU_TO_LE16(resource);
3403         cmd_resp->access_type = CPU_TO_LE16(access);
3404         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3405
3406         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3407         /* The completion specifies the maximum time in ms that the driver
3408          * may hold the resource in the Timeout field.
3409          * If the resource is held by someone else, the command completes with
3410          * busy return value and the timeout field indicates the maximum time
3411          * the current owner of the resource has to free it.
3412          */
3413         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3414                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3415
3416         return status;
3417 }
3418
3419 /**
3420  * i40e_aq_release_resource
3421  * @hw: pointer to the hw struct
3422  * @resource: resource id
3423  * @sdp_number: resource number
3424  * @cmd_details: pointer to command details structure or NULL
3425  *
3426  * release common resource using the admin queue commands
3427  **/
3428 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3429                                 enum i40e_aq_resources_ids resource,
3430                                 u8 sdp_number,
3431                                 struct i40e_asq_cmd_details *cmd_details)
3432 {
3433         struct i40e_aq_desc desc;
3434         struct i40e_aqc_request_resource *cmd =
3435                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3436         enum i40e_status_code status;
3437
3438         DEBUGFUNC("i40e_aq_release_resource");
3439
3440         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3441
3442         cmd->resource_id = CPU_TO_LE16(resource);
3443         cmd->resource_number = CPU_TO_LE32(sdp_number);
3444
3445         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3446
3447         return status;
3448 }
3449
3450 /**
3451  * i40e_aq_read_nvm
3452  * @hw: pointer to the hw struct
3453  * @module_pointer: module pointer location in words from the NVM beginning
3454  * @offset: byte offset from the module beginning
3455  * @length: length of the section to be read (in bytes from the offset)
3456  * @data: command buffer (size [bytes] = length)
3457  * @last_command: tells if this is the last command in a series
3458  * @cmd_details: pointer to command details structure or NULL
3459  *
3460  * Read the NVM using the admin queue commands
3461  **/
3462 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3463                                 u32 offset, u16 length, void *data,
3464                                 bool last_command,
3465                                 struct i40e_asq_cmd_details *cmd_details)
3466 {
3467         struct i40e_aq_desc desc;
3468         struct i40e_aqc_nvm_update *cmd =
3469                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3470         enum i40e_status_code status;
3471
3472         DEBUGFUNC("i40e_aq_read_nvm");
3473
3474         /* In offset the highest byte must be zeroed. */
3475         if (offset & 0xFF000000) {
3476                 status = I40E_ERR_PARAM;
3477                 goto i40e_aq_read_nvm_exit;
3478         }
3479
3480         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3481
3482         /* If this is the last command in a series, set the proper flag. */
3483         if (last_command)
3484                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3485         cmd->module_pointer = module_pointer;
3486         cmd->offset = CPU_TO_LE32(offset);
3487         cmd->length = CPU_TO_LE16(length);
3488
3489         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3490         if (length > I40E_AQ_LARGE_BUF)
3491                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3492
3493         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3494
3495 i40e_aq_read_nvm_exit:
3496         return status;
3497 }
3498
3499 /**
3500  * i40e_aq_read_nvm_config - read an nvm config block
3501  * @hw: pointer to the hw struct
3502  * @cmd_flags: NVM access admin command bits
3503  * @field_id: field or feature id
3504  * @data: buffer for result
3505  * @buf_size: buffer size
3506  * @element_count: pointer to count of elements read by FW
3507  * @cmd_details: pointer to command details structure or NULL
3508  **/
3509 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3510                                 u8 cmd_flags, u32 field_id, void *data,
3511                                 u16 buf_size, u16 *element_count,
3512                                 struct i40e_asq_cmd_details *cmd_details)
3513 {
3514         struct i40e_aq_desc desc;
3515         struct i40e_aqc_nvm_config_read *cmd =
3516                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3517         enum i40e_status_code status;
3518
3519         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3520         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3521         if (buf_size > I40E_AQ_LARGE_BUF)
3522                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3523
3524         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3525         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3526         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3527                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3528         else
3529                 cmd->element_id_msw = 0;
3530
3531         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3532
3533         if (!status && element_count)
3534                 *element_count = LE16_TO_CPU(cmd->element_count);
3535
3536         return status;
3537 }
3538
3539 /**
3540  * i40e_aq_write_nvm_config - write an nvm config block
3541  * @hw: pointer to the hw struct
3542  * @cmd_flags: NVM access admin command bits
3543  * @data: buffer for result
3544  * @buf_size: buffer size
3545  * @element_count: count of elements to be written
3546  * @cmd_details: pointer to command details structure or NULL
3547  **/
3548 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3549                                 u8 cmd_flags, void *data, u16 buf_size,
3550                                 u16 element_count,
3551                                 struct i40e_asq_cmd_details *cmd_details)
3552 {
3553         struct i40e_aq_desc desc;
3554         struct i40e_aqc_nvm_config_write *cmd =
3555                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3556         enum i40e_status_code status;
3557
3558         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3559         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3560         if (buf_size > I40E_AQ_LARGE_BUF)
3561                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3562
3563         cmd->element_count = CPU_TO_LE16(element_count);
3564         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3565         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3566
3567         return status;
3568 }
3569
3570 /**
3571  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3572  * @hw: pointer to the hw struct
3573  * @cmd_details: pointer to command details structure or NULL
3574  **/
3575 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3576                                 void *buff, u16 buff_size,
3577                                 struct i40e_asq_cmd_details *cmd_details)
3578 {
3579         struct i40e_aq_desc desc;
3580         enum i40e_status_code status;
3581
3582         UNREFERENCED_2PARAMETER(buff, buff_size);
3583
3584         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3585         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3586         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3587                 status = I40E_ERR_NOT_IMPLEMENTED;
3588
3589         return status;
3590 }
3591
3592 /**
3593  * i40e_aq_erase_nvm
3594  * @hw: pointer to the hw struct
3595  * @module_pointer: module pointer location in words from the NVM beginning
3596  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3597  * @length: length of the section to be erased (expressed in 4 KB)
3598  * @last_command: tells if this is the last command in a series
3599  * @cmd_details: pointer to command details structure or NULL
3600  *
3601  * Erase the NVM sector using the admin queue commands
3602  **/
3603 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3604                                 u32 offset, u16 length, bool last_command,
3605                                 struct i40e_asq_cmd_details *cmd_details)
3606 {
3607         struct i40e_aq_desc desc;
3608         struct i40e_aqc_nvm_update *cmd =
3609                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3610         enum i40e_status_code status;
3611
3612         DEBUGFUNC("i40e_aq_erase_nvm");
3613
3614         /* In offset the highest byte must be zeroed. */
3615         if (offset & 0xFF000000) {
3616                 status = I40E_ERR_PARAM;
3617                 goto i40e_aq_erase_nvm_exit;
3618         }
3619
3620         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3621
3622         /* If this is the last command in a series, set the proper flag. */
3623         if (last_command)
3624                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3625         cmd->module_pointer = module_pointer;
3626         cmd->offset = CPU_TO_LE32(offset);
3627         cmd->length = CPU_TO_LE16(length);
3628
3629         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3630
3631 i40e_aq_erase_nvm_exit:
3632         return status;
3633 }
3634
3635 /**
3636  * i40e_parse_discover_capabilities
3637  * @hw: pointer to the hw struct
3638  * @buff: pointer to a buffer containing device/function capability records
3639  * @cap_count: number of capability records in the list
3640  * @list_type_opc: type of capabilities list to parse
3641  *
3642  * Parse the device/function capabilities list.
3643  **/
3644 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3645                                      u32 cap_count,
3646                                      enum i40e_admin_queue_opc list_type_opc)
3647 {
3648         struct i40e_aqc_list_capabilities_element_resp *cap;
3649         u32 valid_functions, num_functions;
3650         u32 number, logical_id, phys_id;
3651         struct i40e_hw_capabilities *p;
3652         u8 major_rev;
3653         u32 i = 0;
3654         u16 id;
3655
3656         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3657
3658         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3659                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3660         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3661                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3662         else
3663                 return;
3664
3665         for (i = 0; i < cap_count; i++, cap++) {
3666                 id = LE16_TO_CPU(cap->id);
3667                 number = LE32_TO_CPU(cap->number);
3668                 logical_id = LE32_TO_CPU(cap->logical_id);
3669                 phys_id = LE32_TO_CPU(cap->phys_id);
3670                 major_rev = cap->major_rev;
3671
3672                 switch (id) {
3673                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3674                         p->switch_mode = number;
3675                         i40e_debug(hw, I40E_DEBUG_INIT,
3676                                    "HW Capability: Switch mode = %d\n",
3677                                    p->switch_mode);
3678                         break;
3679                 case I40E_AQ_CAP_ID_MNG_MODE:
3680                         p->management_mode = number;
3681                         if (major_rev > 1) {
3682                                 p->mng_protocols_over_mctp = logical_id;
3683                                 i40e_debug(hw, I40E_DEBUG_INIT,
3684                                            "HW Capability: Protocols over MCTP = %d\n",
3685                                            p->mng_protocols_over_mctp);
3686                         } else {
3687                                 p->mng_protocols_over_mctp = 0;
3688                         }
3689                         i40e_debug(hw, I40E_DEBUG_INIT,
3690                                    "HW Capability: Management Mode = %d\n",
3691                                    p->management_mode);
3692                         break;
3693                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3694                         p->npar_enable = number;
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: NPAR enable = %d\n",
3697                                    p->npar_enable);
3698                         break;
3699                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3700                         p->os2bmc = number;
3701                         i40e_debug(hw, I40E_DEBUG_INIT,
3702                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3703                         break;
3704                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3705                         p->valid_functions = number;
3706                         i40e_debug(hw, I40E_DEBUG_INIT,
3707                                    "HW Capability: Valid Functions = %d\n",
3708                                    p->valid_functions);
3709                         break;
3710                 case I40E_AQ_CAP_ID_SRIOV:
3711                         if (number == 1)
3712                                 p->sr_iov_1_1 = true;
3713                         i40e_debug(hw, I40E_DEBUG_INIT,
3714                                    "HW Capability: SR-IOV = %d\n",
3715                                    p->sr_iov_1_1);
3716                         break;
3717                 case I40E_AQ_CAP_ID_VF:
3718                         p->num_vfs = number;
3719                         p->vf_base_id = logical_id;
3720                         i40e_debug(hw, I40E_DEBUG_INIT,
3721                                    "HW Capability: VF count = %d\n",
3722                                    p->num_vfs);
3723                         i40e_debug(hw, I40E_DEBUG_INIT,
3724                                    "HW Capability: VF base_id = %d\n",
3725                                    p->vf_base_id);
3726                         break;
3727                 case I40E_AQ_CAP_ID_VMDQ:
3728                         if (number == 1)
3729                                 p->vmdq = true;
3730                         i40e_debug(hw, I40E_DEBUG_INIT,
3731                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3732                         break;
3733                 case I40E_AQ_CAP_ID_8021QBG:
3734                         if (number == 1)
3735                                 p->evb_802_1_qbg = true;
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: 802.1Qbg = %d\n", number);
3738                         break;
3739                 case I40E_AQ_CAP_ID_8021QBR:
3740                         if (number == 1)
3741                                 p->evb_802_1_qbh = true;
3742                         i40e_debug(hw, I40E_DEBUG_INIT,
3743                                    "HW Capability: 802.1Qbh = %d\n", number);
3744                         break;
3745                 case I40E_AQ_CAP_ID_VSI:
3746                         p->num_vsis = number;
3747                         i40e_debug(hw, I40E_DEBUG_INIT,
3748                                    "HW Capability: VSI count = %d\n",
3749                                    p->num_vsis);
3750                         break;
3751                 case I40E_AQ_CAP_ID_DCB:
3752                         if (number == 1) {
3753                                 p->dcb = true;
3754                                 p->enabled_tcmap = logical_id;
3755                                 p->maxtc = phys_id;
3756                         }
3757                         i40e_debug(hw, I40E_DEBUG_INIT,
3758                                    "HW Capability: DCB = %d\n", p->dcb);
3759                         i40e_debug(hw, I40E_DEBUG_INIT,
3760                                    "HW Capability: TC Mapping = %d\n",
3761                                    logical_id);
3762                         i40e_debug(hw, I40E_DEBUG_INIT,
3763                                    "HW Capability: TC Max = %d\n", p->maxtc);
3764                         break;
3765                 case I40E_AQ_CAP_ID_FCOE:
3766                         if (number == 1)
3767                                 p->fcoe = true;
3768                         i40e_debug(hw, I40E_DEBUG_INIT,
3769                                    "HW Capability: FCOE = %d\n", p->fcoe);
3770                         break;
3771                 case I40E_AQ_CAP_ID_ISCSI:
3772                         if (number == 1)
3773                                 p->iscsi = true;
3774                         i40e_debug(hw, I40E_DEBUG_INIT,
3775                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3776                         break;
3777                 case I40E_AQ_CAP_ID_RSS:
3778                         p->rss = true;
3779                         p->rss_table_size = number;
3780                         p->rss_table_entry_width = logical_id;
3781                         i40e_debug(hw, I40E_DEBUG_INIT,
3782                                    "HW Capability: RSS = %d\n", p->rss);
3783                         i40e_debug(hw, I40E_DEBUG_INIT,
3784                                    "HW Capability: RSS table size = %d\n",
3785                                    p->rss_table_size);
3786                         i40e_debug(hw, I40E_DEBUG_INIT,
3787                                    "HW Capability: RSS table width = %d\n",
3788                                    p->rss_table_entry_width);
3789                         break;
3790                 case I40E_AQ_CAP_ID_RXQ:
3791                         p->num_rx_qp = number;
3792                         p->base_queue = phys_id;
3793                         i40e_debug(hw, I40E_DEBUG_INIT,
3794                                    "HW Capability: Rx QP = %d\n", number);
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: base_queue = %d\n",
3797                                    p->base_queue);
3798                         break;
3799                 case I40E_AQ_CAP_ID_TXQ:
3800                         p->num_tx_qp = number;
3801                         p->base_queue = phys_id;
3802                         i40e_debug(hw, I40E_DEBUG_INIT,
3803                                    "HW Capability: Tx QP = %d\n", number);
3804                         i40e_debug(hw, I40E_DEBUG_INIT,
3805                                    "HW Capability: base_queue = %d\n",
3806                                    p->base_queue);
3807                         break;
3808                 case I40E_AQ_CAP_ID_MSIX:
3809                         p->num_msix_vectors = number;
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: MSIX vector count = %d\n",
3812                                    p->num_msix_vectors);
3813                         break;
3814                 case I40E_AQ_CAP_ID_VF_MSIX:
3815                         p->num_msix_vectors_vf = number;
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: MSIX VF vector count = %d\n",
3818                                    p->num_msix_vectors_vf);
3819                         break;
3820                 case I40E_AQ_CAP_ID_FLEX10:
3821                         if (major_rev == 1) {
3822                                 if (number == 1) {
3823                                         p->flex10_enable = true;
3824                                         p->flex10_capable = true;
3825                                 }
3826                         } else {
3827                                 /* Capability revision >= 2 */
3828                                 if (number & 1)
3829                                         p->flex10_enable = true;
3830                                 if (number & 2)
3831                                         p->flex10_capable = true;
3832                         }
3833                         p->flex10_mode = logical_id;
3834                         p->flex10_status = phys_id;
3835                         i40e_debug(hw, I40E_DEBUG_INIT,
3836                                    "HW Capability: Flex10 mode = %d\n",
3837                                    p->flex10_mode);
3838                         i40e_debug(hw, I40E_DEBUG_INIT,
3839                                    "HW Capability: Flex10 status = %d\n",
3840                                    p->flex10_status);
3841                         break;
3842                 case I40E_AQ_CAP_ID_CEM:
3843                         if (number == 1)
3844                                 p->mgmt_cem = true;
3845                         i40e_debug(hw, I40E_DEBUG_INIT,
3846                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3847                         break;
3848                 case I40E_AQ_CAP_ID_IWARP:
3849                         if (number == 1)
3850                                 p->iwarp = true;
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: iWARP = %d\n", p->iwarp);
3853                         break;
3854                 case I40E_AQ_CAP_ID_LED:
3855                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3856                                 p->led[phys_id] = true;
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: LED - PIN %d\n", phys_id);
3859                         break;
3860                 case I40E_AQ_CAP_ID_SDP:
3861                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3862                                 p->sdp[phys_id] = true;
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: SDP - PIN %d\n", phys_id);
3865                         break;
3866                 case I40E_AQ_CAP_ID_MDIO:
3867                         if (number == 1) {
3868                                 p->mdio_port_num = phys_id;
3869                                 p->mdio_port_mode = logical_id;
3870                         }
3871                         i40e_debug(hw, I40E_DEBUG_INIT,
3872                                    "HW Capability: MDIO port number = %d\n",
3873                                    p->mdio_port_num);
3874                         i40e_debug(hw, I40E_DEBUG_INIT,
3875                                    "HW Capability: MDIO port mode = %d\n",
3876                                    p->mdio_port_mode);
3877                         break;
3878                 case I40E_AQ_CAP_ID_1588:
3879                         if (number == 1)
3880                                 p->ieee_1588 = true;
3881                         i40e_debug(hw, I40E_DEBUG_INIT,
3882                                    "HW Capability: IEEE 1588 = %d\n",
3883                                    p->ieee_1588);
3884                         break;
3885                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3886                         p->fd = true;
3887                         p->fd_filters_guaranteed = number;
3888                         p->fd_filters_best_effort = logical_id;
3889                         i40e_debug(hw, I40E_DEBUG_INIT,
3890                                    "HW Capability: Flow Director = 1\n");
3891                         i40e_debug(hw, I40E_DEBUG_INIT,
3892                                    "HW Capability: Guaranteed FD filters = %d\n",
3893                                    p->fd_filters_guaranteed);
3894                         break;
3895                 case I40E_AQ_CAP_ID_WSR_PROT:
3896                         p->wr_csr_prot = (u64)number;
3897                         p->wr_csr_prot |= (u64)logical_id << 32;
3898                         i40e_debug(hw, I40E_DEBUG_INIT,
3899                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3900                                    (p->wr_csr_prot & 0xffff));
3901                         break;
3902                 case I40E_AQ_CAP_ID_NVM_MGMT:
3903                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3904                                 p->sec_rev_disabled = true;
3905                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3906                                 p->update_disabled = true;
3907                         break;
3908                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3909                         hw->num_wol_proxy_filters = (u16)number;
3910                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3911                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3912                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3913                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3914                         else
3915                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3916                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3917                         i40e_debug(hw, I40E_DEBUG_INIT,
3918                                    "HW Capability: WOL proxy filters = %d\n",
3919                                    hw->num_wol_proxy_filters);
3920                         break;
3921                 default:
3922                         break;
3923                 }
3924         }
3925
3926         if (p->fcoe)
3927                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3928
3929         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3930         p->fcoe = false;
3931
3932         /* count the enabled ports (aka the "not disabled" ports) */
3933         hw->num_ports = 0;
3934         for (i = 0; i < 4; i++) {
3935                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3936                 u64 port_cfg = 0;
3937
3938                 /* use AQ read to get the physical register offset instead
3939                  * of the port relative offset
3940                  */
3941                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3942                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3943                         hw->num_ports++;
3944         }
3945
3946         valid_functions = p->valid_functions;
3947         num_functions = 0;
3948         while (valid_functions) {
3949                 if (valid_functions & 1)
3950                         num_functions++;
3951                 valid_functions >>= 1;
3952         }
3953
3954         /* partition id is 1-based, and functions are evenly spread
3955          * across the ports as partitions
3956          */
3957         if (hw->num_ports != 0) {
3958                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3959                 hw->num_partitions = num_functions / hw->num_ports;
3960         }
3961
3962         /* additional HW specific goodies that might
3963          * someday be HW version specific
3964          */
3965         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3966 }
3967
3968 /**
3969  * i40e_aq_discover_capabilities
3970  * @hw: pointer to the hw struct
3971  * @buff: a virtual buffer to hold the capabilities
3972  * @buff_size: Size of the virtual buffer
3973  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3974  * @list_type_opc: capabilities type to discover - pass in the command opcode
3975  * @cmd_details: pointer to command details structure or NULL
3976  *
3977  * Get the device capabilities descriptions from the firmware
3978  **/
3979 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3980                                 void *buff, u16 buff_size, u16 *data_size,
3981                                 enum i40e_admin_queue_opc list_type_opc,
3982                                 struct i40e_asq_cmd_details *cmd_details)
3983 {
3984         struct i40e_aqc_list_capabilites *cmd;
3985         struct i40e_aq_desc desc;
3986         enum i40e_status_code status = I40E_SUCCESS;
3987
3988         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3989
3990         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3991                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3992                 status = I40E_ERR_PARAM;
3993                 goto exit;
3994         }
3995
3996         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3997
3998         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3999         if (buff_size > I40E_AQ_LARGE_BUF)
4000                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4001
4002         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4003         *data_size = LE16_TO_CPU(desc.datalen);
4004
4005         if (status)
4006                 goto exit;
4007
4008         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4009                                          list_type_opc);
4010
4011 exit:
4012         return status;
4013 }
4014
4015 /**
4016  * i40e_aq_update_nvm
4017  * @hw: pointer to the hw struct
4018  * @module_pointer: module pointer location in words from the NVM beginning
4019  * @offset: byte offset from the module beginning
4020  * @length: length of the section to be written (in bytes from the offset)
4021  * @data: command buffer (size [bytes] = length)
4022  * @last_command: tells if this is the last command in a series
4023  * @cmd_details: pointer to command details structure or NULL
4024  *
4025  * Update the NVM using the admin queue commands
4026  **/
4027 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4028                                 u32 offset, u16 length, void *data,
4029                                 bool last_command,
4030                                 struct i40e_asq_cmd_details *cmd_details)
4031 {
4032         struct i40e_aq_desc desc;
4033         struct i40e_aqc_nvm_update *cmd =
4034                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4035         enum i40e_status_code status;
4036
4037         DEBUGFUNC("i40e_aq_update_nvm");
4038
4039         /* In offset the highest byte must be zeroed. */
4040         if (offset & 0xFF000000) {
4041                 status = I40E_ERR_PARAM;
4042                 goto i40e_aq_update_nvm_exit;
4043         }
4044
4045         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4046
4047         /* If this is the last command in a series, set the proper flag. */
4048         if (last_command)
4049                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4050         cmd->module_pointer = module_pointer;
4051         cmd->offset = CPU_TO_LE32(offset);
4052         cmd->length = CPU_TO_LE16(length);
4053
4054         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4055         if (length > I40E_AQ_LARGE_BUF)
4056                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4057
4058         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4059
4060 i40e_aq_update_nvm_exit:
4061         return status;
4062 }
4063
4064 /**
4065  * i40e_aq_get_lldp_mib
4066  * @hw: pointer to the hw struct
4067  * @bridge_type: type of bridge requested
4068  * @mib_type: Local, Remote or both Local and Remote MIBs
4069  * @buff: pointer to a user supplied buffer to store the MIB block
4070  * @buff_size: size of the buffer (in bytes)
4071  * @local_len : length of the returned Local LLDP MIB
4072  * @remote_len: length of the returned Remote LLDP MIB
4073  * @cmd_details: pointer to command details structure or NULL
4074  *
4075  * Requests the complete LLDP MIB (entire packet).
4076  **/
4077 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4078                                 u8 mib_type, void *buff, u16 buff_size,
4079                                 u16 *local_len, u16 *remote_len,
4080                                 struct i40e_asq_cmd_details *cmd_details)
4081 {
4082         struct i40e_aq_desc desc;
4083         struct i40e_aqc_lldp_get_mib *cmd =
4084                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4085         struct i40e_aqc_lldp_get_mib *resp =
4086                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4087         enum i40e_status_code status;
4088
4089         if (buff_size == 0 || !buff)
4090                 return I40E_ERR_PARAM;
4091
4092         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4093         /* Indirect Command */
4094         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4095
4096         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4097         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4098                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4099
4100         desc.datalen = CPU_TO_LE16(buff_size);
4101
4102         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4103         if (buff_size > I40E_AQ_LARGE_BUF)
4104                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4105
4106         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4107         if (!status) {
4108                 if (local_len != NULL)
4109                         *local_len = LE16_TO_CPU(resp->local_len);
4110                 if (remote_len != NULL)
4111                         *remote_len = LE16_TO_CPU(resp->remote_len);
4112         }
4113
4114         return status;
4115 }
4116
4117  /**
4118  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4119  * @hw: pointer to the hw struct
4120  * @mib_type: Local, Remote or both Local and Remote MIBs
4121  * @buff: pointer to a user supplied buffer to store the MIB block
4122  * @buff_size: size of the buffer (in bytes)
4123  * @cmd_details: pointer to command details structure or NULL
4124  *
4125  * Set the LLDP MIB.
4126  **/
4127 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4128                                 u8 mib_type, void *buff, u16 buff_size,
4129                                 struct i40e_asq_cmd_details *cmd_details)
4130 {
4131         struct i40e_aq_desc desc;
4132         struct i40e_aqc_lldp_set_local_mib *cmd =
4133                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4134         enum i40e_status_code status;
4135
4136         if (buff_size == 0 || !buff)
4137                 return I40E_ERR_PARAM;
4138
4139         i40e_fill_default_direct_cmd_desc(&desc,
4140                                 i40e_aqc_opc_lldp_set_local_mib);
4141         /* Indirect Command */
4142         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4143         if (buff_size > I40E_AQ_LARGE_BUF)
4144                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4145         desc.datalen = CPU_TO_LE16(buff_size);
4146
4147         cmd->type = mib_type;
4148         cmd->length = CPU_TO_LE16(buff_size);
4149         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4150         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4151
4152         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4153         return status;
4154 }
4155
4156 /**
4157  * i40e_aq_cfg_lldp_mib_change_event
4158  * @hw: pointer to the hw struct
4159  * @enable_update: Enable or Disable event posting
4160  * @cmd_details: pointer to command details structure or NULL
4161  *
4162  * Enable or Disable posting of an event on ARQ when LLDP MIB
4163  * associated with the interface changes
4164  **/
4165 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4166                                 bool enable_update,
4167                                 struct i40e_asq_cmd_details *cmd_details)
4168 {
4169         struct i40e_aq_desc desc;
4170         struct i40e_aqc_lldp_update_mib *cmd =
4171                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4172         enum i40e_status_code status;
4173
4174         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4175
4176         if (!enable_update)
4177                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4178
4179         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4180
4181         return status;
4182 }
4183
4184 /**
4185  * i40e_aq_add_lldp_tlv
4186  * @hw: pointer to the hw struct
4187  * @bridge_type: type of bridge
4188  * @buff: buffer with TLV to add
4189  * @buff_size: length of the buffer
4190  * @tlv_len: length of the TLV to be added
4191  * @mib_len: length of the LLDP MIB returned in response
4192  * @cmd_details: pointer to command details structure or NULL
4193  *
4194  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4195  * it is responsibility of the caller to make sure that the TLV is not
4196  * already present in the LLDPDU.
4197  * In return firmware will write the complete LLDP MIB with the newly
4198  * added TLV in the response buffer.
4199  **/
4200 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4201                                 void *buff, u16 buff_size, u16 tlv_len,
4202                                 u16 *mib_len,
4203                                 struct i40e_asq_cmd_details *cmd_details)
4204 {
4205         struct i40e_aq_desc desc;
4206         struct i40e_aqc_lldp_add_tlv *cmd =
4207                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4208         enum i40e_status_code status;
4209
4210         if (buff_size == 0 || !buff || tlv_len == 0)
4211                 return I40E_ERR_PARAM;
4212
4213         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4214
4215         /* Indirect Command */
4216         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4217         if (buff_size > I40E_AQ_LARGE_BUF)
4218                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4219         desc.datalen = CPU_TO_LE16(buff_size);
4220
4221         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4222                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4223         cmd->len = CPU_TO_LE16(tlv_len);
4224
4225         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4226         if (!status) {
4227                 if (mib_len != NULL)
4228                         *mib_len = LE16_TO_CPU(desc.datalen);
4229         }
4230
4231         return status;
4232 }
4233
4234 /**
4235  * i40e_aq_update_lldp_tlv
4236  * @hw: pointer to the hw struct
4237  * @bridge_type: type of bridge
4238  * @buff: buffer with TLV to update
4239  * @buff_size: size of the buffer holding original and updated TLVs
4240  * @old_len: Length of the Original TLV
4241  * @new_len: Length of the Updated TLV
4242  * @offset: offset of the updated TLV in the buff
4243  * @mib_len: length of the returned LLDP MIB
4244  * @cmd_details: pointer to command details structure or NULL
4245  *
4246  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4247  * Firmware will place the complete LLDP MIB in response buffer with the
4248  * updated TLV.
4249  **/
4250 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4251                                 u8 bridge_type, void *buff, u16 buff_size,
4252                                 u16 old_len, u16 new_len, u16 offset,
4253                                 u16 *mib_len,
4254                                 struct i40e_asq_cmd_details *cmd_details)
4255 {
4256         struct i40e_aq_desc desc;
4257         struct i40e_aqc_lldp_update_tlv *cmd =
4258                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4259         enum i40e_status_code status;
4260
4261         if (buff_size == 0 || !buff || offset == 0 ||
4262             old_len == 0 || new_len == 0)
4263                 return I40E_ERR_PARAM;
4264
4265         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4266
4267         /* Indirect Command */
4268         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4269         if (buff_size > I40E_AQ_LARGE_BUF)
4270                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4271         desc.datalen = CPU_TO_LE16(buff_size);
4272
4273         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4274                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4275         cmd->old_len = CPU_TO_LE16(old_len);
4276         cmd->new_offset = CPU_TO_LE16(offset);
4277         cmd->new_len = CPU_TO_LE16(new_len);
4278
4279         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4280         if (!status) {
4281                 if (mib_len != NULL)
4282                         *mib_len = LE16_TO_CPU(desc.datalen);
4283         }
4284
4285         return status;
4286 }
4287
4288 /**
4289  * i40e_aq_delete_lldp_tlv
4290  * @hw: pointer to the hw struct
4291  * @bridge_type: type of bridge
4292  * @buff: pointer to a user supplied buffer that has the TLV
4293  * @buff_size: length of the buffer
4294  * @tlv_len: length of the TLV to be deleted
4295  * @mib_len: length of the returned LLDP MIB
4296  * @cmd_details: pointer to command details structure or NULL
4297  *
4298  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4299  * The firmware places the entire LLDP MIB in the response buffer.
4300  **/
4301 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4302                                 u8 bridge_type, void *buff, u16 buff_size,
4303                                 u16 tlv_len, u16 *mib_len,
4304                                 struct i40e_asq_cmd_details *cmd_details)
4305 {
4306         struct i40e_aq_desc desc;
4307         struct i40e_aqc_lldp_add_tlv *cmd =
4308                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4309         enum i40e_status_code status;
4310
4311         if (buff_size == 0 || !buff)
4312                 return I40E_ERR_PARAM;
4313
4314         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4315
4316         /* Indirect Command */
4317         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4318         if (buff_size > I40E_AQ_LARGE_BUF)
4319                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4320         desc.datalen = CPU_TO_LE16(buff_size);
4321         cmd->len = CPU_TO_LE16(tlv_len);
4322         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4323                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4324
4325         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4326         if (!status) {
4327                 if (mib_len != NULL)
4328                         *mib_len = LE16_TO_CPU(desc.datalen);
4329         }
4330
4331         return status;
4332 }
4333
4334 /**
4335  * i40e_aq_stop_lldp
4336  * @hw: pointer to the hw struct
4337  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4338  * @cmd_details: pointer to command details structure or NULL
4339  *
4340  * Stop or Shutdown the embedded LLDP Agent
4341  **/
4342 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4343                                 struct i40e_asq_cmd_details *cmd_details)
4344 {
4345         struct i40e_aq_desc desc;
4346         struct i40e_aqc_lldp_stop *cmd =
4347                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4348         enum i40e_status_code status;
4349
4350         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4351
4352         if (shutdown_agent)
4353                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4354
4355         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4356
4357         return status;
4358 }
4359
4360 /**
4361  * i40e_aq_start_lldp
4362  * @hw: pointer to the hw struct
4363  * @cmd_details: pointer to command details structure or NULL
4364  *
4365  * Start the embedded LLDP Agent on all ports.
4366  **/
4367 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4368                                 struct i40e_asq_cmd_details *cmd_details)
4369 {
4370         struct i40e_aq_desc desc;
4371         struct i40e_aqc_lldp_start *cmd =
4372                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4373         enum i40e_status_code status;
4374
4375         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4376
4377         cmd->command = I40E_AQ_LLDP_AGENT_START;
4378
4379         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4380
4381         return status;
4382 }
4383
4384 /**
4385  * i40e_aq_get_cee_dcb_config
4386  * @hw: pointer to the hw struct
4387  * @buff: response buffer that stores CEE operational configuration
4388  * @buff_size: size of the buffer passed
4389  * @cmd_details: pointer to command details structure or NULL
4390  *
4391  * Get CEE DCBX mode operational configuration from firmware
4392  **/
4393 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4394                                 void *buff, u16 buff_size,
4395                                 struct i40e_asq_cmd_details *cmd_details)
4396 {
4397         struct i40e_aq_desc desc;
4398         enum i40e_status_code status;
4399
4400         if (buff_size == 0 || !buff)
4401                 return I40E_ERR_PARAM;
4402
4403         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4404
4405         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4406         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4407                                        cmd_details);
4408
4409         return status;
4410 }
4411
4412 /**
4413  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4414  * @hw: pointer to the hw struct
4415  * @start_agent: True if DCBx Agent needs to be Started
4416  *                              False if DCBx Agent needs to be Stopped
4417  * @cmd_details: pointer to command details structure or NULL
4418  *
4419  * Start/Stop the embedded dcbx Agent
4420  **/
4421 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4422                                 bool start_agent,
4423                                 struct i40e_asq_cmd_details *cmd_details)
4424 {
4425         struct i40e_aq_desc desc;
4426         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4427                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4428                                 &desc.params.raw;
4429         enum i40e_status_code status;
4430
4431         i40e_fill_default_direct_cmd_desc(&desc,
4432                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4433
4434         if (start_agent)
4435                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4436
4437         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4438
4439         return status;
4440 }
4441
4442 /**
4443  * i40e_aq_add_udp_tunnel
4444  * @hw: pointer to the hw struct
4445  * @udp_port: the UDP port to add in Host byte order
4446  * @header_len: length of the tunneling header length in DWords
4447  * @protocol_index: protocol index type
4448  * @filter_index: pointer to filter index
4449  * @cmd_details: pointer to command details structure or NULL
4450  *
4451  * Note: Firmware expects the udp_port value to be in Little Endian format,
4452  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4453  * Little Endian order.
4454  **/
4455 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4456                                 u16 udp_port, u8 protocol_index,
4457                                 u8 *filter_index,
4458                                 struct i40e_asq_cmd_details *cmd_details)
4459 {
4460         struct i40e_aq_desc desc;
4461         struct i40e_aqc_add_udp_tunnel *cmd =
4462                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4463         struct i40e_aqc_del_udp_tunnel_completion *resp =
4464                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4465         enum i40e_status_code status;
4466
4467         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4468
4469         cmd->udp_port = CPU_TO_LE16(udp_port);
4470         cmd->protocol_type = protocol_index;
4471
4472         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4473
4474         if (!status && filter_index)
4475                 *filter_index = resp->index;
4476
4477         return status;
4478 }
4479
4480 /**
4481  * i40e_aq_del_udp_tunnel
4482  * @hw: pointer to the hw struct
4483  * @index: filter index
4484  * @cmd_details: pointer to command details structure or NULL
4485  **/
4486 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4487                                 struct i40e_asq_cmd_details *cmd_details)
4488 {
4489         struct i40e_aq_desc desc;
4490         struct i40e_aqc_remove_udp_tunnel *cmd =
4491                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4492         enum i40e_status_code status;
4493
4494         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4495
4496         cmd->index = index;
4497
4498         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4499
4500         return status;
4501 }
4502
4503 /**
4504  * i40e_aq_get_switch_resource_alloc (0x0204)
4505  * @hw: pointer to the hw struct
4506  * @num_entries: pointer to u8 to store the number of resource entries returned
4507  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4508  *        to store the resource information for all resource types.  Each
4509  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4510  * @count: size, in bytes, of the buffer provided
4511  * @cmd_details: pointer to command details structure or NULL
4512  *
4513  * Query the resources allocated to a function.
4514  **/
4515 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4516                         u8 *num_entries,
4517                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4518                         u16 count,
4519                         struct i40e_asq_cmd_details *cmd_details)
4520 {
4521         struct i40e_aq_desc desc;
4522         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4523                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4524         enum i40e_status_code status;
4525         u16 length = count * sizeof(*buf);
4526
4527         i40e_fill_default_direct_cmd_desc(&desc,
4528                                         i40e_aqc_opc_get_switch_resource_alloc);
4529
4530         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4531         if (length > I40E_AQ_LARGE_BUF)
4532                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4533
4534         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4535
4536         if (!status && num_entries)
4537                 *num_entries = cmd_resp->num_entries;
4538
4539         return status;
4540 }
4541
4542 /**
4543  * i40e_aq_delete_element - Delete switch element
4544  * @hw: pointer to the hw struct
4545  * @seid: the SEID to delete from the switch
4546  * @cmd_details: pointer to command details structure or NULL
4547  *
4548  * This deletes a switch element from the switch.
4549  **/
4550 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4551                                 struct i40e_asq_cmd_details *cmd_details)
4552 {
4553         struct i40e_aq_desc desc;
4554         struct i40e_aqc_switch_seid *cmd =
4555                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4556         enum i40e_status_code status;
4557
4558         if (seid == 0)
4559                 return I40E_ERR_PARAM;
4560
4561         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4562
4563         cmd->seid = CPU_TO_LE16(seid);
4564
4565         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4566
4567         return status;
4568 }
4569
4570 /**
4571  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4572  * @hw: pointer to the hw struct
4573  * @flags: component flags
4574  * @mac_seid: uplink seid (MAC SEID)
4575  * @vsi_seid: connected vsi seid
4576  * @ret_seid: seid of create pv component
4577  *
4578  * This instantiates an i40e port virtualizer with specified flags.
4579  * Depending on specified flags the port virtualizer can act as a
4580  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4581  */
4582 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4583                                        u16 mac_seid, u16 vsi_seid,
4584                                        u16 *ret_seid)
4585 {
4586         struct i40e_aq_desc desc;
4587         struct i40e_aqc_add_update_pv *cmd =
4588                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4589         struct i40e_aqc_add_update_pv_completion *resp =
4590                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4591         enum i40e_status_code status;
4592
4593         if (vsi_seid == 0)
4594                 return I40E_ERR_PARAM;
4595
4596         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4597         cmd->command_flags = CPU_TO_LE16(flags);
4598         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4599         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4600
4601         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4602         if (!status && ret_seid)
4603                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4604
4605         return status;
4606 }
4607
4608 /**
4609  * i40e_aq_add_tag - Add an S/E-tag
4610  * @hw: pointer to the hw struct
4611  * @direct_to_queue: should s-tag direct flow to a specific queue
4612  * @vsi_seid: VSI SEID to use this tag
4613  * @tag: value of the tag
4614  * @queue_num: queue number, only valid is direct_to_queue is true
4615  * @tags_used: return value, number of tags in use by this PF
4616  * @tags_free: return value, number of unallocated tags
4617  * @cmd_details: pointer to command details structure or NULL
4618  *
4619  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4620  * the number of tags allocated by the PF, and the number of unallocated
4621  * tags available.
4622  **/
4623 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4624                                 u16 vsi_seid, u16 tag, u16 queue_num,
4625                                 u16 *tags_used, u16 *tags_free,
4626                                 struct i40e_asq_cmd_details *cmd_details)
4627 {
4628         struct i40e_aq_desc desc;
4629         struct i40e_aqc_add_tag *cmd =
4630                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4631         struct i40e_aqc_add_remove_tag_completion *resp =
4632                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4633         enum i40e_status_code status;
4634
4635         if (vsi_seid == 0)
4636                 return I40E_ERR_PARAM;
4637
4638         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4639
4640         cmd->seid = CPU_TO_LE16(vsi_seid);
4641         cmd->tag = CPU_TO_LE16(tag);
4642         if (direct_to_queue) {
4643                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4644                 cmd->queue_number = CPU_TO_LE16(queue_num);
4645         }
4646
4647         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4648
4649         if (!status) {
4650                 if (tags_used != NULL)
4651                         *tags_used = LE16_TO_CPU(resp->tags_used);
4652                 if (tags_free != NULL)
4653                         *tags_free = LE16_TO_CPU(resp->tags_free);
4654         }
4655
4656         return status;
4657 }
4658
4659 /**
4660  * i40e_aq_remove_tag - Remove an S- or E-tag
4661  * @hw: pointer to the hw struct
4662  * @vsi_seid: VSI SEID this tag is associated with
4663  * @tag: value of the S-tag to delete
4664  * @tags_used: return value, number of tags in use by this PF
4665  * @tags_free: return value, number of unallocated tags
4666  * @cmd_details: pointer to command details structure or NULL
4667  *
4668  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4669  * the number of tags allocated by the PF, and the number of unallocated
4670  * tags available.
4671  **/
4672 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4673                                 u16 tag, u16 *tags_used, u16 *tags_free,
4674                                 struct i40e_asq_cmd_details *cmd_details)
4675 {
4676         struct i40e_aq_desc desc;
4677         struct i40e_aqc_remove_tag *cmd =
4678                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4679         struct i40e_aqc_add_remove_tag_completion *resp =
4680                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4681         enum i40e_status_code status;
4682
4683         if (vsi_seid == 0)
4684                 return I40E_ERR_PARAM;
4685
4686         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4687
4688         cmd->seid = CPU_TO_LE16(vsi_seid);
4689         cmd->tag = CPU_TO_LE16(tag);
4690
4691         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4692
4693         if (!status) {
4694                 if (tags_used != NULL)
4695                         *tags_used = LE16_TO_CPU(resp->tags_used);
4696                 if (tags_free != NULL)
4697                         *tags_free = LE16_TO_CPU(resp->tags_free);
4698         }
4699
4700         return status;
4701 }
4702
4703 /**
4704  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4705  * @hw: pointer to the hw struct
4706  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4707  * @etag: value of E-tag to add
4708  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4709  * @buf: address of indirect buffer
4710  * @tags_used: return value, number of E-tags in use by this port
4711  * @tags_free: return value, number of unallocated M-tags
4712  * @cmd_details: pointer to command details structure or NULL
4713  *
4714  * This associates a multicast E-tag to a port virtualizer.  It will return
4715  * the number of tags allocated by the PF, and the number of unallocated
4716  * tags available.
4717  *
4718  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4719  * num_tags_in_buf long.
4720  **/
4721 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4722                                 u16 etag, u8 num_tags_in_buf, void *buf,
4723                                 u16 *tags_used, u16 *tags_free,
4724                                 struct i40e_asq_cmd_details *cmd_details)
4725 {
4726         struct i40e_aq_desc desc;
4727         struct i40e_aqc_add_remove_mcast_etag *cmd =
4728                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4729         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4730            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4731         enum i40e_status_code status;
4732         u16 length = sizeof(u16) * num_tags_in_buf;
4733
4734         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4735                 return I40E_ERR_PARAM;
4736
4737         i40e_fill_default_direct_cmd_desc(&desc,
4738                                           i40e_aqc_opc_add_multicast_etag);
4739
4740         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4741         cmd->etag = CPU_TO_LE16(etag);
4742         cmd->num_unicast_etags = num_tags_in_buf;
4743
4744         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4745         if (length > I40E_AQ_LARGE_BUF)
4746                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4747
4748         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4749
4750         if (!status) {
4751                 if (tags_used != NULL)
4752                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4753                 if (tags_free != NULL)
4754                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4755         }
4756
4757         return status;
4758 }
4759
4760 /**
4761  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4762  * @hw: pointer to the hw struct
4763  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4764  * @etag: value of the E-tag to remove
4765  * @tags_used: return value, number of tags in use by this port
4766  * @tags_free: return value, number of unallocated tags
4767  * @cmd_details: pointer to command details structure or NULL
4768  *
4769  * This deletes an E-tag from the port virtualizer.  It will return
4770  * the number of tags allocated by the port, and the number of unallocated
4771  * tags available.
4772  **/
4773 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4774                                 u16 etag, u16 *tags_used, u16 *tags_free,
4775                                 struct i40e_asq_cmd_details *cmd_details)
4776 {
4777         struct i40e_aq_desc desc;
4778         struct i40e_aqc_add_remove_mcast_etag *cmd =
4779                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4780         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4781            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4782         enum i40e_status_code status;
4783
4784
4785         if (pv_seid == 0)
4786                 return I40E_ERR_PARAM;
4787
4788         i40e_fill_default_direct_cmd_desc(&desc,
4789                                           i40e_aqc_opc_remove_multicast_etag);
4790
4791         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4792         cmd->etag = CPU_TO_LE16(etag);
4793
4794         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4795
4796         if (!status) {
4797                 if (tags_used != NULL)
4798                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4799                 if (tags_free != NULL)
4800                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4801         }
4802
4803         return status;
4804 }
4805
4806 /**
4807  * i40e_aq_update_tag - Update an S/E-tag
4808  * @hw: pointer to the hw struct
4809  * @vsi_seid: VSI SEID using this S-tag
4810  * @old_tag: old tag value
4811  * @new_tag: new tag value
4812  * @tags_used: return value, number of tags in use by this PF
4813  * @tags_free: return value, number of unallocated tags
4814  * @cmd_details: pointer to command details structure or NULL
4815  *
4816  * This updates the value of the tag currently attached to this VSI
4817  * in the switch complex.  It will return the number of tags allocated
4818  * by the PF, and the number of unallocated tags available.
4819  **/
4820 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4821                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4822                                 u16 *tags_free,
4823                                 struct i40e_asq_cmd_details *cmd_details)
4824 {
4825         struct i40e_aq_desc desc;
4826         struct i40e_aqc_update_tag *cmd =
4827                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4828         struct i40e_aqc_update_tag_completion *resp =
4829                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4830         enum i40e_status_code status;
4831
4832         if (vsi_seid == 0)
4833                 return I40E_ERR_PARAM;
4834
4835         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4836
4837         cmd->seid = CPU_TO_LE16(vsi_seid);
4838         cmd->old_tag = CPU_TO_LE16(old_tag);
4839         cmd->new_tag = CPU_TO_LE16(new_tag);
4840
4841         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4842
4843         if (!status) {
4844                 if (tags_used != NULL)
4845                         *tags_used = LE16_TO_CPU(resp->tags_used);
4846                 if (tags_free != NULL)
4847                         *tags_free = LE16_TO_CPU(resp->tags_free);
4848         }
4849
4850         return status;
4851 }
4852
4853 /**
4854  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4855  * @hw: pointer to the hw struct
4856  * @tcmap: TC map for request/release any ignore PFC condition
4857  * @request: request or release ignore PFC condition
4858  * @tcmap_ret: return TCs for which PFC is currently ignored
4859  * @cmd_details: pointer to command details structure or NULL
4860  *
4861  * This sends out request/release to ignore PFC condition for a TC.
4862  * It will return the TCs for which PFC is currently ignored.
4863  **/
4864 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4865                                 bool request, u8 *tcmap_ret,
4866                                 struct i40e_asq_cmd_details *cmd_details)
4867 {
4868         struct i40e_aq_desc desc;
4869         struct i40e_aqc_pfc_ignore *cmd_resp =
4870                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4871         enum i40e_status_code status;
4872
4873         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4874
4875         if (request)
4876                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4877
4878         cmd_resp->tc_bitmap = tcmap;
4879
4880         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4881
4882         if (!status) {
4883                 if (tcmap_ret != NULL)
4884                         *tcmap_ret = cmd_resp->tc_bitmap;
4885         }
4886
4887         return status;
4888 }
4889
4890 /**
4891  * i40e_aq_dcb_updated - DCB Updated Command
4892  * @hw: pointer to the hw struct
4893  * @cmd_details: pointer to command details structure or NULL
4894  *
4895  * When LLDP is handled in PF this command is used by the PF
4896  * to notify EMP that a DCB setting is modified.
4897  * When LLDP is handled in EMP this command is used by the PF
4898  * to notify EMP whenever one of the following parameters get
4899  * modified:
4900  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4901  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4902  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4903  * EMP will return when the shared RPB settings have been
4904  * recomputed and modified. The retval field in the descriptor
4905  * will be set to 0 when RPB is modified.
4906  **/
4907 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4908                                 struct i40e_asq_cmd_details *cmd_details)
4909 {
4910         struct i40e_aq_desc desc;
4911         enum i40e_status_code status;
4912
4913         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4914
4915         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4916
4917         return status;
4918 }
4919
4920 /**
4921  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4922  * @hw: pointer to the hw struct
4923  * @seid: defines the SEID of the switch for which the stats are requested
4924  * @vlan_id: the VLAN ID for which the statistics are requested
4925  * @stat_index: index of the statistics counters block assigned to this VLAN
4926  * @cmd_details: pointer to command details structure or NULL
4927  *
4928  * XL710 supports 128 smonVlanStats counters.This command is used to
4929  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4930  * switch.
4931  **/
4932 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4933                                 u16 vlan_id, u16 *stat_index,
4934                                 struct i40e_asq_cmd_details *cmd_details)
4935 {
4936         struct i40e_aq_desc desc;
4937         struct i40e_aqc_add_remove_statistics *cmd_resp =
4938                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4939         enum i40e_status_code status;
4940
4941         if ((seid == 0) || (stat_index == NULL))
4942                 return I40E_ERR_PARAM;
4943
4944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4945
4946         cmd_resp->seid = CPU_TO_LE16(seid);
4947         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4948
4949         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4950
4951         if (!status && stat_index)
4952                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4953
4954         return status;
4955 }
4956
4957 /**
4958  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4959  * @hw: pointer to the hw struct
4960  * @seid: defines the SEID of the switch for which the stats are requested
4961  * @vlan_id: the VLAN ID for which the statistics are requested
4962  * @stat_index: index of the statistics counters block assigned to this VLAN
4963  * @cmd_details: pointer to command details structure or NULL
4964  *
4965  * XL710 supports 128 smonVlanStats counters.This command is used to
4966  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4967  * switch.
4968  **/
4969 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4970                                 u16 vlan_id, u16 stat_index,
4971                                 struct i40e_asq_cmd_details *cmd_details)
4972 {
4973         struct i40e_aq_desc desc;
4974         struct i40e_aqc_add_remove_statistics *cmd =
4975                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4976         enum i40e_status_code status;
4977
4978         if (seid == 0)
4979                 return I40E_ERR_PARAM;
4980
4981         i40e_fill_default_direct_cmd_desc(&desc,
4982                                           i40e_aqc_opc_remove_statistics);
4983
4984         cmd->seid = CPU_TO_LE16(seid);
4985         cmd->vlan  = CPU_TO_LE16(vlan_id);
4986         cmd->stat_index = CPU_TO_LE16(stat_index);
4987
4988         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4989
4990         return status;
4991 }
4992
4993 /**
4994  * i40e_aq_set_port_parameters - set physical port parameters.
4995  * @hw: pointer to the hw struct
4996  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4997  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4998  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4999  * @double_vlan: if set double VLAN is enabled
5000  * @cmd_details: pointer to command details structure or NULL
5001  **/
5002 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5003                                 u16 bad_frame_vsi, bool save_bad_pac,
5004                                 bool pad_short_pac, bool double_vlan,
5005                                 struct i40e_asq_cmd_details *cmd_details)
5006 {
5007         struct i40e_aqc_set_port_parameters *cmd;
5008         enum i40e_status_code status;
5009         struct i40e_aq_desc desc;
5010         u16 command_flags = 0;
5011
5012         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5013
5014         i40e_fill_default_direct_cmd_desc(&desc,
5015                                           i40e_aqc_opc_set_port_parameters);
5016
5017         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5018         if (save_bad_pac)
5019                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5020         if (pad_short_pac)
5021                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5022         if (double_vlan)
5023                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5024         cmd->command_flags = CPU_TO_LE16(command_flags);
5025
5026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5027
5028         return status;
5029 }
5030
5031 /**
5032  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5033  * @hw: pointer to the hw struct
5034  * @seid: seid for the physical port/switching component/vsi
5035  * @buff: Indirect buffer to hold data parameters and response
5036  * @buff_size: Indirect buffer size
5037  * @opcode: Tx scheduler AQ command opcode
5038  * @cmd_details: pointer to command details structure or NULL
5039  *
5040  * Generic command handler for Tx scheduler AQ commands
5041  **/
5042 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5043                                 void *buff, u16 buff_size,
5044                                  enum i40e_admin_queue_opc opcode,
5045                                 struct i40e_asq_cmd_details *cmd_details)
5046 {
5047         struct i40e_aq_desc desc;
5048         struct i40e_aqc_tx_sched_ind *cmd =
5049                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5050         enum i40e_status_code status;
5051         bool cmd_param_flag = false;
5052
5053         switch (opcode) {
5054         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5055         case i40e_aqc_opc_configure_vsi_tc_bw:
5056         case i40e_aqc_opc_enable_switching_comp_ets:
5057         case i40e_aqc_opc_modify_switching_comp_ets:
5058         case i40e_aqc_opc_disable_switching_comp_ets:
5059         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5060         case i40e_aqc_opc_configure_switching_comp_bw_config:
5061                 cmd_param_flag = true;
5062                 break;
5063         case i40e_aqc_opc_query_vsi_bw_config:
5064         case i40e_aqc_opc_query_vsi_ets_sla_config:
5065         case i40e_aqc_opc_query_switching_comp_ets_config:
5066         case i40e_aqc_opc_query_port_ets_config:
5067         case i40e_aqc_opc_query_switching_comp_bw_config:
5068                 cmd_param_flag = false;
5069                 break;
5070         default:
5071                 return I40E_ERR_PARAM;
5072         }
5073
5074         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5075
5076         /* Indirect command */
5077         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5078         if (cmd_param_flag)
5079                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5080         if (buff_size > I40E_AQ_LARGE_BUF)
5081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5082
5083         desc.datalen = CPU_TO_LE16(buff_size);
5084
5085         cmd->vsi_seid = CPU_TO_LE16(seid);
5086
5087         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5088
5089         return status;
5090 }
5091
5092 /**
5093  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5094  * @hw: pointer to the hw struct
5095  * @seid: VSI seid
5096  * @credit: BW limit credits (0 = disabled)
5097  * @max_credit: Max BW limit credits
5098  * @cmd_details: pointer to command details structure or NULL
5099  **/
5100 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5101                                 u16 seid, u16 credit, u8 max_credit,
5102                                 struct i40e_asq_cmd_details *cmd_details)
5103 {
5104         struct i40e_aq_desc desc;
5105         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5106                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5107         enum i40e_status_code status;
5108
5109         i40e_fill_default_direct_cmd_desc(&desc,
5110                                           i40e_aqc_opc_configure_vsi_bw_limit);
5111
5112         cmd->vsi_seid = CPU_TO_LE16(seid);
5113         cmd->credit = CPU_TO_LE16(credit);
5114         cmd->max_credit = max_credit;
5115
5116         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5117
5118         return status;
5119 }
5120
5121 /**
5122  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5123  * @hw: pointer to the hw struct
5124  * @seid: switching component seid
5125  * @credit: BW limit credits (0 = disabled)
5126  * @max_bw: Max BW limit credits
5127  * @cmd_details: pointer to command details structure or NULL
5128  **/
5129 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5130                                 u16 seid, u16 credit, u8 max_bw,
5131                                 struct i40e_asq_cmd_details *cmd_details)
5132 {
5133         struct i40e_aq_desc desc;
5134         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5135           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5136         enum i40e_status_code status;
5137
5138         i40e_fill_default_direct_cmd_desc(&desc,
5139                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5140
5141         cmd->seid = CPU_TO_LE16(seid);
5142         cmd->credit = CPU_TO_LE16(credit);
5143         cmd->max_bw = max_bw;
5144
5145         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5146
5147         return status;
5148 }
5149
5150 /**
5151  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5152  * @hw: pointer to the hw struct
5153  * @seid: VSI seid
5154  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5155  * @cmd_details: pointer to command details structure or NULL
5156  **/
5157 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5158                         u16 seid,
5159                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5160                         struct i40e_asq_cmd_details *cmd_details)
5161 {
5162         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5163                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5164                                     cmd_details);
5165 }
5166
5167 /**
5168  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5169  * @hw: pointer to the hw struct
5170  * @seid: VSI seid
5171  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5172  * @cmd_details: pointer to command details structure or NULL
5173  **/
5174 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5175                         u16 seid,
5176                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5177                         struct i40e_asq_cmd_details *cmd_details)
5178 {
5179         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5180                                     i40e_aqc_opc_configure_vsi_tc_bw,
5181                                     cmd_details);
5182 }
5183
5184 /**
5185  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5186  * @hw: pointer to the hw struct
5187  * @seid: seid of the switching component connected to Physical Port
5188  * @ets_data: Buffer holding ETS parameters
5189  * @cmd_details: pointer to command details structure or NULL
5190  **/
5191 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5192                 u16 seid,
5193                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5194                 enum i40e_admin_queue_opc opcode,
5195                 struct i40e_asq_cmd_details *cmd_details)
5196 {
5197         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5198                                     sizeof(*ets_data), opcode, cmd_details);
5199 }
5200
5201 /**
5202  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5203  * @hw: pointer to the hw struct
5204  * @seid: seid of the switching component
5205  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5206  * @cmd_details: pointer to command details structure or NULL
5207  **/
5208 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5209         u16 seid,
5210         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5211         struct i40e_asq_cmd_details *cmd_details)
5212 {
5213         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5214                             i40e_aqc_opc_configure_switching_comp_bw_config,
5215                             cmd_details);
5216 }
5217
5218 /**
5219  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5220  * @hw: pointer to the hw struct
5221  * @seid: seid of the switching component
5222  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5223  * @cmd_details: pointer to command details structure or NULL
5224  **/
5225 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5226         struct i40e_hw *hw, u16 seid,
5227         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5228         struct i40e_asq_cmd_details *cmd_details)
5229 {
5230         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5231                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5232                             cmd_details);
5233 }
5234
5235 /**
5236  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5237  * @hw: pointer to the hw struct
5238  * @seid: seid of the VSI
5239  * @bw_data: Buffer to hold VSI BW configuration
5240  * @cmd_details: pointer to command details structure or NULL
5241  **/
5242 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5243                         u16 seid,
5244                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5245                         struct i40e_asq_cmd_details *cmd_details)
5246 {
5247         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5248                                     i40e_aqc_opc_query_vsi_bw_config,
5249                                     cmd_details);
5250 }
5251
5252 /**
5253  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5254  * @hw: pointer to the hw struct
5255  * @seid: seid of the VSI
5256  * @bw_data: Buffer to hold VSI BW configuration per TC
5257  * @cmd_details: pointer to command details structure or NULL
5258  **/
5259 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5260                         u16 seid,
5261                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5262                         struct i40e_asq_cmd_details *cmd_details)
5263 {
5264         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5265                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5266                                     cmd_details);
5267 }
5268
5269 /**
5270  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5271  * @hw: pointer to the hw struct
5272  * @seid: seid of the switching component
5273  * @bw_data: Buffer to hold switching component's per TC BW config
5274  * @cmd_details: pointer to command details structure or NULL
5275  **/
5276 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5277                 u16 seid,
5278                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5279                 struct i40e_asq_cmd_details *cmd_details)
5280 {
5281         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5282                                    i40e_aqc_opc_query_switching_comp_ets_config,
5283                                    cmd_details);
5284 }
5285
5286 /**
5287  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5288  * @hw: pointer to the hw struct
5289  * @seid: seid of the VSI or switching component connected to Physical Port
5290  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5291  * @cmd_details: pointer to command details structure or NULL
5292  **/
5293 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5294                         u16 seid,
5295                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5296                         struct i40e_asq_cmd_details *cmd_details)
5297 {
5298         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5299                                     i40e_aqc_opc_query_port_ets_config,
5300                                     cmd_details);
5301 }
5302
5303 /**
5304  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5305  * @hw: pointer to the hw struct
5306  * @seid: seid of the switching component
5307  * @bw_data: Buffer to hold switching component's BW configuration
5308  * @cmd_details: pointer to command details structure or NULL
5309  **/
5310 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5311                 u16 seid,
5312                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5313                 struct i40e_asq_cmd_details *cmd_details)
5314 {
5315         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5316                                     i40e_aqc_opc_query_switching_comp_bw_config,
5317                                     cmd_details);
5318 }
5319
5320 /**
5321  * i40e_validate_filter_settings
5322  * @hw: pointer to the hardware structure
5323  * @settings: Filter control settings
5324  *
5325  * Check and validate the filter control settings passed.
5326  * The function checks for the valid filter/context sizes being
5327  * passed for FCoE and PE.
5328  *
5329  * Returns I40E_SUCCESS if the values passed are valid and within
5330  * range else returns an error.
5331  **/
5332 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5333                                 struct i40e_filter_control_settings *settings)
5334 {
5335         u32 fcoe_cntx_size, fcoe_filt_size;
5336         u32 pe_cntx_size, pe_filt_size;
5337         u32 fcoe_fmax;
5338
5339         u32 val;
5340
5341         /* Validate FCoE settings passed */
5342         switch (settings->fcoe_filt_num) {
5343         case I40E_HASH_FILTER_SIZE_1K:
5344         case I40E_HASH_FILTER_SIZE_2K:
5345         case I40E_HASH_FILTER_SIZE_4K:
5346         case I40E_HASH_FILTER_SIZE_8K:
5347         case I40E_HASH_FILTER_SIZE_16K:
5348         case I40E_HASH_FILTER_SIZE_32K:
5349                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5350                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5351                 break;
5352         default:
5353                 return I40E_ERR_PARAM;
5354         }
5355
5356         switch (settings->fcoe_cntx_num) {
5357         case I40E_DMA_CNTX_SIZE_512:
5358         case I40E_DMA_CNTX_SIZE_1K:
5359         case I40E_DMA_CNTX_SIZE_2K:
5360         case I40E_DMA_CNTX_SIZE_4K:
5361                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5362                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5363                 break;
5364         default:
5365                 return I40E_ERR_PARAM;
5366         }
5367
5368         /* Validate PE settings passed */
5369         switch (settings->pe_filt_num) {
5370         case I40E_HASH_FILTER_SIZE_1K:
5371         case I40E_HASH_FILTER_SIZE_2K:
5372         case I40E_HASH_FILTER_SIZE_4K:
5373         case I40E_HASH_FILTER_SIZE_8K:
5374         case I40E_HASH_FILTER_SIZE_16K:
5375         case I40E_HASH_FILTER_SIZE_32K:
5376         case I40E_HASH_FILTER_SIZE_64K:
5377         case I40E_HASH_FILTER_SIZE_128K:
5378         case I40E_HASH_FILTER_SIZE_256K:
5379         case I40E_HASH_FILTER_SIZE_512K:
5380         case I40E_HASH_FILTER_SIZE_1M:
5381                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5382                 pe_filt_size <<= (u32)settings->pe_filt_num;
5383                 break;
5384         default:
5385                 return I40E_ERR_PARAM;
5386         }
5387
5388         switch (settings->pe_cntx_num) {
5389         case I40E_DMA_CNTX_SIZE_512:
5390         case I40E_DMA_CNTX_SIZE_1K:
5391         case I40E_DMA_CNTX_SIZE_2K:
5392         case I40E_DMA_CNTX_SIZE_4K:
5393         case I40E_DMA_CNTX_SIZE_8K:
5394         case I40E_DMA_CNTX_SIZE_16K:
5395         case I40E_DMA_CNTX_SIZE_32K:
5396         case I40E_DMA_CNTX_SIZE_64K:
5397         case I40E_DMA_CNTX_SIZE_128K:
5398         case I40E_DMA_CNTX_SIZE_256K:
5399                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5400                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5401                 break;
5402         default:
5403                 return I40E_ERR_PARAM;
5404         }
5405
5406         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5407         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5408         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5409                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5410         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5411                 return I40E_ERR_INVALID_SIZE;
5412
5413         return I40E_SUCCESS;
5414 }
5415
5416 /**
5417  * i40e_set_filter_control
5418  * @hw: pointer to the hardware structure
5419  * @settings: Filter control settings
5420  *
5421  * Set the Queue Filters for PE/FCoE and enable filters required
5422  * for a single PF. It is expected that these settings are programmed
5423  * at the driver initialization time.
5424  **/
5425 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5426                                 struct i40e_filter_control_settings *settings)
5427 {
5428         enum i40e_status_code ret = I40E_SUCCESS;
5429         u32 hash_lut_size = 0;
5430         u32 val;
5431
5432         if (!settings)
5433                 return I40E_ERR_PARAM;
5434
5435         /* Validate the input settings */
5436         ret = i40e_validate_filter_settings(hw, settings);
5437         if (ret)
5438                 return ret;
5439
5440         /* Read the PF Queue Filter control register */
5441         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5442
5443         /* Program required PE hash buckets for the PF */
5444         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5445         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5446                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5447         /* Program required PE contexts for the PF */
5448         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5449         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5450                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5451
5452         /* Program required FCoE hash buckets for the PF */
5453         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5454         val |= ((u32)settings->fcoe_filt_num <<
5455                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5456                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5457         /* Program required FCoE DDP contexts for the PF */
5458         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5459         val |= ((u32)settings->fcoe_cntx_num <<
5460                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5461                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5462
5463         /* Program Hash LUT size for the PF */
5464         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5465         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5466                 hash_lut_size = 1;
5467         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5468                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5469
5470         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5471         if (settings->enable_fdir)
5472                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5473         if (settings->enable_ethtype)
5474                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5475         if (settings->enable_macvlan)
5476                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5477
5478         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5479
5480         return I40E_SUCCESS;
5481 }
5482
5483 /**
5484  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5485  * @hw: pointer to the hw struct
5486  * @mac_addr: MAC address to use in the filter
5487  * @ethtype: Ethertype to use in the filter
5488  * @flags: Flags that needs to be applied to the filter
5489  * @vsi_seid: seid of the control VSI
5490  * @queue: VSI queue number to send the packet to
5491  * @is_add: Add control packet filter if True else remove
5492  * @stats: Structure to hold information on control filter counts
5493  * @cmd_details: pointer to command details structure or NULL
5494  *
5495  * This command will Add or Remove control packet filter for a control VSI.
5496  * In return it will update the total number of perfect filter count in
5497  * the stats member.
5498  **/
5499 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5500                                 u8 *mac_addr, u16 ethtype, u16 flags,
5501                                 u16 vsi_seid, u16 queue, bool is_add,
5502                                 struct i40e_control_filter_stats *stats,
5503                                 struct i40e_asq_cmd_details *cmd_details)
5504 {
5505         struct i40e_aq_desc desc;
5506         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5507                 (struct i40e_aqc_add_remove_control_packet_filter *)
5508                 &desc.params.raw;
5509         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5510                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5511                 &desc.params.raw;
5512         enum i40e_status_code status;
5513
5514         if (vsi_seid == 0)
5515                 return I40E_ERR_PARAM;
5516
5517         if (is_add) {
5518                 i40e_fill_default_direct_cmd_desc(&desc,
5519                                 i40e_aqc_opc_add_control_packet_filter);
5520                 cmd->queue = CPU_TO_LE16(queue);
5521         } else {
5522                 i40e_fill_default_direct_cmd_desc(&desc,
5523                                 i40e_aqc_opc_remove_control_packet_filter);
5524         }
5525
5526         if (mac_addr)
5527                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5528                             I40E_NONDMA_TO_NONDMA);
5529
5530         cmd->etype = CPU_TO_LE16(ethtype);
5531         cmd->flags = CPU_TO_LE16(flags);
5532         cmd->seid = CPU_TO_LE16(vsi_seid);
5533
5534         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5535
5536         if (!status && stats) {
5537                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5538                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5539                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5540                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5541         }
5542
5543         return status;
5544 }
5545
5546 /**
5547  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5548  * @hw: pointer to the hw struct
5549  * @seid: VSI seid to add ethertype filter from
5550  **/
5551 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5552 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5553                                                     u16 seid)
5554 {
5555         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5556                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5557                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5558         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5559         enum i40e_status_code status;
5560
5561         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5562                                                        seid, 0, true, NULL,
5563                                                        NULL);
5564         if (status)
5565                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5566 }
5567
5568 /**
5569  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5570  * @filters: list of cloud filters
5571  * @filter_count: length of list
5572  *
5573  * There's an issue in the device where the Geneve VNI layout needs
5574  * to be shifted 1 byte over from the VxLAN VNI
5575  **/
5576 STATIC void i40e_fix_up_geneve_vni(
5577         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5578         u8 filter_count)
5579 {
5580         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5581         int i;
5582
5583         for (i = 0; i < filter_count; i++) {
5584                 u16 tnl_type;
5585                 u32 ti;
5586
5587                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5588                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5589                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5590                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5591                         ti = LE32_TO_CPU(f[i].tenant_id);
5592                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5593                 }
5594         }
5595 }
5596
5597 /**
5598  * i40e_aq_add_cloud_filters
5599  * @hw: pointer to the hardware structure
5600  * @seid: VSI seid to add cloud filters from
5601  * @filters: Buffer which contains the filters to be added
5602  * @filter_count: number of filters contained in the buffer
5603  *
5604  * Set the cloud filters for a given VSI.  The contents of the
5605  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5606  * in by the caller of the function.
5607  *
5608  **/
5609 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5610         u16 seid,
5611         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5612         u8 filter_count)
5613 {
5614         struct i40e_aq_desc desc;
5615         struct i40e_aqc_add_remove_cloud_filters *cmd =
5616         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5617         enum i40e_status_code status;
5618         u16 buff_len;
5619
5620         i40e_fill_default_direct_cmd_desc(&desc,
5621                                           i40e_aqc_opc_add_cloud_filters);
5622
5623         buff_len = filter_count * sizeof(*filters);
5624         desc.datalen = CPU_TO_LE16(buff_len);
5625         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5626         cmd->num_filters = filter_count;
5627         cmd->seid = CPU_TO_LE16(seid);
5628
5629         i40e_fix_up_geneve_vni(filters, filter_count);
5630
5631         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5632
5633         return status;
5634 }
5635
5636 /**
5637  * i40e_aq_add_cloud_filters_big_buffer
5638  * @hw: pointer to the hardware structure
5639  * @seid: VSI seid to add cloud filters from
5640  * @filters: Buffer which contains the filters in big buffer to be added
5641  * @filter_count: number of filters contained in the buffer
5642  *
5643  * Set the cloud filters for a given VSI.  The contents of the
5644  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5645  * the function.
5646  *
5647  **/
5648 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5649         u16 seid,
5650         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5651         u8 filter_count)
5652 {
5653         struct i40e_aq_desc desc;
5654         struct i40e_aqc_add_remove_cloud_filters *cmd =
5655         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5656         enum i40e_status_code status;
5657         u16 buff_len;
5658         int i;
5659
5660         i40e_fill_default_direct_cmd_desc(&desc,
5661                                           i40e_aqc_opc_add_cloud_filters);
5662
5663         buff_len = filter_count * sizeof(*filters);
5664         desc.datalen = CPU_TO_LE16(buff_len);
5665         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5666         cmd->num_filters = filter_count;
5667         cmd->seid = CPU_TO_LE16(seid);
5668         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5669
5670         /* adjust Geneve VNI for HW issue */
5671         for (i = 0; i < filter_count; i++) {
5672                 u16 tnl_type;
5673                 u32 ti;
5674
5675                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5676                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5677                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5678                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5679                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5680                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5681                 }
5682         }
5683
5684         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5685
5686         return status;
5687 }
5688
5689 /**
5690  * i40e_aq_remove_cloud_filters
5691  * @hw: pointer to the hardware structure
5692  * @seid: VSI seid to remove cloud filters from
5693  * @filters: Buffer which contains the filters to be removed
5694  * @filter_count: number of filters contained in the buffer
5695  *
5696  * Remove the cloud filters for a given VSI.  The contents of the
5697  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5698  * in by the caller of the function.
5699  *
5700  **/
5701 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5702         u16 seid,
5703         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5704         u8 filter_count)
5705 {
5706         struct i40e_aq_desc desc;
5707         struct i40e_aqc_add_remove_cloud_filters *cmd =
5708         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5709         enum i40e_status_code status;
5710         u16 buff_len;
5711
5712         i40e_fill_default_direct_cmd_desc(&desc,
5713                                           i40e_aqc_opc_remove_cloud_filters);
5714
5715         buff_len = filter_count * sizeof(*filters);
5716         desc.datalen = CPU_TO_LE16(buff_len);
5717         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5718         cmd->num_filters = filter_count;
5719         cmd->seid = CPU_TO_LE16(seid);
5720
5721         i40e_fix_up_geneve_vni(filters, filter_count);
5722
5723         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5724
5725         return status;
5726 }
5727
5728 /**
5729  * i40e_aq_remove_cloud_filters_big_buffer
5730  * @hw: pointer to the hardware structure
5731  * @seid: VSI seid to remove cloud filters from
5732  * @filters: Buffer which contains the filters in big buffer to be removed
5733  * @filter_count: number of filters contained in the buffer
5734  *
5735  * Remove the cloud filters for a given VSI.  The contents of the
5736  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5737  * the function.
5738  *
5739  **/
5740 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5741         struct i40e_hw *hw,
5742         u16 seid,
5743         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5744         u8 filter_count)
5745 {
5746         struct i40e_aq_desc desc;
5747         struct i40e_aqc_add_remove_cloud_filters *cmd =
5748         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5749         enum i40e_status_code status;
5750         u16 buff_len;
5751         int i;
5752
5753         i40e_fill_default_direct_cmd_desc(&desc,
5754                                           i40e_aqc_opc_remove_cloud_filters);
5755
5756         buff_len = filter_count * sizeof(*filters);
5757         desc.datalen = CPU_TO_LE16(buff_len);
5758         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5759         cmd->num_filters = filter_count;
5760         cmd->seid = CPU_TO_LE16(seid);
5761         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5762
5763         /* adjust Geneve VNI for HW issue */
5764         for (i = 0; i < filter_count; i++) {
5765                 u16 tnl_type;
5766                 u32 ti;
5767
5768                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5769                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5770                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5771                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5772                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5773                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5774                 }
5775         }
5776
5777         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5778
5779         return status;
5780 }
5781
5782 /**
5783  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5784  * @hw: pointer to the hw struct
5785  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5786  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5787  *
5788  **/
5789 enum
5790 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5791         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5792         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5793 {
5794         struct i40e_aq_desc desc;
5795         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5796                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5797         enum i40e_status_code status = I40E_SUCCESS;
5798         int i = 0;
5799
5800         i40e_fill_default_direct_cmd_desc(&desc,
5801                                           i40e_aqc_opc_replace_cloud_filters);
5802
5803         desc.datalen = CPU_TO_LE16(32);
5804         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5805         cmd->old_filter_type = filters->old_filter_type;
5806         cmd->new_filter_type = filters->new_filter_type;
5807         cmd->valid_flags = filters->valid_flags;
5808         cmd->tr_bit = filters->tr_bit;
5809
5810         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5811                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5812
5813         /* for get cloud filters command */
5814         for (i = 0; i < 32; i += 4) {
5815                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5816                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5817                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5818                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5819         }
5820
5821         return status;
5822 }
5823
5824
5825 /**
5826  * i40e_aq_alternate_write
5827  * @hw: pointer to the hardware structure
5828  * @reg_addr0: address of first dword to be read
5829  * @reg_val0: value to be written under 'reg_addr0'
5830  * @reg_addr1: address of second dword to be read
5831  * @reg_val1: value to be written under 'reg_addr1'
5832  *
5833  * Write one or two dwords to alternate structure. Fields are indicated
5834  * by 'reg_addr0' and 'reg_addr1' register numbers.
5835  *
5836  **/
5837 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5838                                 u32 reg_addr0, u32 reg_val0,
5839                                 u32 reg_addr1, u32 reg_val1)
5840 {
5841         struct i40e_aq_desc desc;
5842         struct i40e_aqc_alternate_write *cmd_resp =
5843                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5844         enum i40e_status_code status;
5845
5846         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5847         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5848         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5849         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5850         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5851
5852         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5853
5854         return status;
5855 }
5856
5857 /**
5858  * i40e_aq_alternate_write_indirect
5859  * @hw: pointer to the hardware structure
5860  * @addr: address of a first register to be modified
5861  * @dw_count: number of alternate structure fields to write
5862  * @buffer: pointer to the command buffer
5863  *
5864  * Write 'dw_count' dwords from 'buffer' to alternate structure
5865  * starting at 'addr'.
5866  *
5867  **/
5868 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5869                                 u32 addr, u32 dw_count, void *buffer)
5870 {
5871         struct i40e_aq_desc desc;
5872         struct i40e_aqc_alternate_ind_write *cmd_resp =
5873                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5874         enum i40e_status_code status;
5875
5876         if (buffer == NULL)
5877                 return I40E_ERR_PARAM;
5878
5879         /* Indirect command */
5880         i40e_fill_default_direct_cmd_desc(&desc,
5881                                          i40e_aqc_opc_alternate_write_indirect);
5882
5883         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5884         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5885         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5886                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5887
5888         cmd_resp->address = CPU_TO_LE32(addr);
5889         cmd_resp->length = CPU_TO_LE32(dw_count);
5890
5891         status = i40e_asq_send_command(hw, &desc, buffer,
5892                                        I40E_LO_DWORD(4*dw_count), NULL);
5893
5894         return status;
5895 }
5896
5897 /**
5898  * i40e_aq_alternate_read
5899  * @hw: pointer to the hardware structure
5900  * @reg_addr0: address of first dword to be read
5901  * @reg_val0: pointer for data read from 'reg_addr0'
5902  * @reg_addr1: address of second dword to be read
5903  * @reg_val1: pointer for data read from 'reg_addr1'
5904  *
5905  * Read one or two dwords from alternate structure. Fields are indicated
5906  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5907  * is not passed then only register at 'reg_addr0' is read.
5908  *
5909  **/
5910 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5911                                 u32 reg_addr0, u32 *reg_val0,
5912                                 u32 reg_addr1, u32 *reg_val1)
5913 {
5914         struct i40e_aq_desc desc;
5915         struct i40e_aqc_alternate_write *cmd_resp =
5916                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5917         enum i40e_status_code status;
5918
5919         if (reg_val0 == NULL)
5920                 return I40E_ERR_PARAM;
5921
5922         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5923         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5924         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5925
5926         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5927
5928         if (status == I40E_SUCCESS) {
5929                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5930
5931                 if (reg_val1 != NULL)
5932                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5933         }
5934
5935         return status;
5936 }
5937
5938 /**
5939  * i40e_aq_alternate_read_indirect
5940  * @hw: pointer to the hardware structure
5941  * @addr: address of the alternate structure field
5942  * @dw_count: number of alternate structure fields to read
5943  * @buffer: pointer to the command buffer
5944  *
5945  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5946  * place them in 'buffer'. The buffer should be allocated by caller.
5947  *
5948  **/
5949 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5950                                 u32 addr, u32 dw_count, void *buffer)
5951 {
5952         struct i40e_aq_desc desc;
5953         struct i40e_aqc_alternate_ind_write *cmd_resp =
5954                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5955         enum i40e_status_code status;
5956
5957         if (buffer == NULL)
5958                 return I40E_ERR_PARAM;
5959
5960         /* Indirect command */
5961         i40e_fill_default_direct_cmd_desc(&desc,
5962                 i40e_aqc_opc_alternate_read_indirect);
5963
5964         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5965         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5966         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5967                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5968
5969         cmd_resp->address = CPU_TO_LE32(addr);
5970         cmd_resp->length = CPU_TO_LE32(dw_count);
5971
5972         status = i40e_asq_send_command(hw, &desc, buffer,
5973                                        I40E_LO_DWORD(4*dw_count), NULL);
5974
5975         return status;
5976 }
5977
5978 /**
5979  *  i40e_aq_alternate_clear
5980  *  @hw: pointer to the HW structure.
5981  *
5982  *  Clear the alternate structures of the port from which the function
5983  *  is called.
5984  *
5985  **/
5986 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5987 {
5988         struct i40e_aq_desc desc;
5989         enum i40e_status_code status;
5990
5991         i40e_fill_default_direct_cmd_desc(&desc,
5992                                           i40e_aqc_opc_alternate_clear_port);
5993
5994         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5995
5996         return status;
5997 }
5998
5999 /**
6000  *  i40e_aq_alternate_write_done
6001  *  @hw: pointer to the HW structure.
6002  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6003  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6004  *
6005  *  Indicates to the FW that alternate structures have been changed.
6006  *
6007  **/
6008 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6009                 u8 bios_mode, bool *reset_needed)
6010 {
6011         struct i40e_aq_desc desc;
6012         struct i40e_aqc_alternate_write_done *cmd =
6013                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6014         enum i40e_status_code status;
6015
6016         if (reset_needed == NULL)
6017                 return I40E_ERR_PARAM;
6018
6019         i40e_fill_default_direct_cmd_desc(&desc,
6020                                           i40e_aqc_opc_alternate_write_done);
6021
6022         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6023
6024         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6025         if (!status && reset_needed)
6026                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6027                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6028
6029         return status;
6030 }
6031
6032 /**
6033  *  i40e_aq_set_oem_mode
6034  *  @hw: pointer to the HW structure.
6035  *  @oem_mode: the OEM mode to be used
6036  *
6037  *  Sets the device to a specific operating mode. Currently the only supported
6038  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6039  *
6040  **/
6041 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6042                 u8 oem_mode)
6043 {
6044         struct i40e_aq_desc desc;
6045         struct i40e_aqc_alternate_write_done *cmd =
6046                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6047         enum i40e_status_code status;
6048
6049         i40e_fill_default_direct_cmd_desc(&desc,
6050                                           i40e_aqc_opc_alternate_set_mode);
6051
6052         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6053
6054         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6055
6056         return status;
6057 }
6058
6059 /**
6060  * i40e_aq_resume_port_tx
6061  * @hw: pointer to the hardware structure
6062  * @cmd_details: pointer to command details structure or NULL
6063  *
6064  * Resume port's Tx traffic
6065  **/
6066 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6067                                 struct i40e_asq_cmd_details *cmd_details)
6068 {
6069         struct i40e_aq_desc desc;
6070         enum i40e_status_code status;
6071
6072         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6073
6074         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6075
6076         return status;
6077 }
6078
6079 /**
6080  * i40e_set_pci_config_data - store PCI bus info
6081  * @hw: pointer to hardware structure
6082  * @link_status: the link status word from PCI config space
6083  *
6084  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6085  **/
6086 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6087 {
6088         hw->bus.type = i40e_bus_type_pci_express;
6089
6090         switch (link_status & I40E_PCI_LINK_WIDTH) {
6091         case I40E_PCI_LINK_WIDTH_1:
6092                 hw->bus.width = i40e_bus_width_pcie_x1;
6093                 break;
6094         case I40E_PCI_LINK_WIDTH_2:
6095                 hw->bus.width = i40e_bus_width_pcie_x2;
6096                 break;
6097         case I40E_PCI_LINK_WIDTH_4:
6098                 hw->bus.width = i40e_bus_width_pcie_x4;
6099                 break;
6100         case I40E_PCI_LINK_WIDTH_8:
6101                 hw->bus.width = i40e_bus_width_pcie_x8;
6102                 break;
6103         default:
6104                 hw->bus.width = i40e_bus_width_unknown;
6105                 break;
6106         }
6107
6108         switch (link_status & I40E_PCI_LINK_SPEED) {
6109         case I40E_PCI_LINK_SPEED_2500:
6110                 hw->bus.speed = i40e_bus_speed_2500;
6111                 break;
6112         case I40E_PCI_LINK_SPEED_5000:
6113                 hw->bus.speed = i40e_bus_speed_5000;
6114                 break;
6115         case I40E_PCI_LINK_SPEED_8000:
6116                 hw->bus.speed = i40e_bus_speed_8000;
6117                 break;
6118         default:
6119                 hw->bus.speed = i40e_bus_speed_unknown;
6120                 break;
6121         }
6122 }
6123
6124 /**
6125  * i40e_aq_debug_dump
6126  * @hw: pointer to the hardware structure
6127  * @cluster_id: specific cluster to dump
6128  * @table_id: table id within cluster
6129  * @start_index: index of line in the block to read
6130  * @buff_size: dump buffer size
6131  * @buff: dump buffer
6132  * @ret_buff_size: actual buffer size returned
6133  * @ret_next_table: next block to read
6134  * @ret_next_index: next index to read
6135  *
6136  * Dump internal FW/HW data for debug purposes.
6137  *
6138  **/
6139 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6140                                 u8 table_id, u32 start_index, u16 buff_size,
6141                                 void *buff, u16 *ret_buff_size,
6142                                 u8 *ret_next_table, u32 *ret_next_index,
6143                                 struct i40e_asq_cmd_details *cmd_details)
6144 {
6145         struct i40e_aq_desc desc;
6146         struct i40e_aqc_debug_dump_internals *cmd =
6147                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6148         struct i40e_aqc_debug_dump_internals *resp =
6149                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6150         enum i40e_status_code status;
6151
6152         if (buff_size == 0 || !buff)
6153                 return I40E_ERR_PARAM;
6154
6155         i40e_fill_default_direct_cmd_desc(&desc,
6156                                           i40e_aqc_opc_debug_dump_internals);
6157         /* Indirect Command */
6158         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6159         if (buff_size > I40E_AQ_LARGE_BUF)
6160                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6161
6162         cmd->cluster_id = cluster_id;
6163         cmd->table_id = table_id;
6164         cmd->idx = CPU_TO_LE32(start_index);
6165
6166         desc.datalen = CPU_TO_LE16(buff_size);
6167
6168         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6169         if (!status) {
6170                 if (ret_buff_size != NULL)
6171                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6172                 if (ret_next_table != NULL)
6173                         *ret_next_table = resp->table_id;
6174                 if (ret_next_index != NULL)
6175                         *ret_next_index = LE32_TO_CPU(resp->idx);
6176         }
6177
6178         return status;
6179 }
6180
6181 /**
6182  * i40e_read_bw_from_alt_ram
6183  * @hw: pointer to the hardware structure
6184  * @max_bw: pointer for max_bw read
6185  * @min_bw: pointer for min_bw read
6186  * @min_valid: pointer for bool that is true if min_bw is a valid value
6187  * @max_valid: pointer for bool that is true if max_bw is a valid value
6188  *
6189  * Read bw from the alternate ram for the given pf
6190  **/
6191 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6192                                         u32 *max_bw, u32 *min_bw,
6193                                         bool *min_valid, bool *max_valid)
6194 {
6195         enum i40e_status_code status;
6196         u32 max_bw_addr, min_bw_addr;
6197
6198         /* Calculate the address of the min/max bw registers */
6199         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6200                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6201                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6202         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6203                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6204                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6205
6206         /* Read the bandwidths from alt ram */
6207         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6208                                         min_bw_addr, min_bw);
6209
6210         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6211                 *min_valid = true;
6212         else
6213                 *min_valid = false;
6214
6215         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6216                 *max_valid = true;
6217         else
6218                 *max_valid = false;
6219
6220         return status;
6221 }
6222
6223 /**
6224  * i40e_aq_configure_partition_bw
6225  * @hw: pointer to the hardware structure
6226  * @bw_data: Buffer holding valid pfs and bw limits
6227  * @cmd_details: pointer to command details
6228  *
6229  * Configure partitions guaranteed/max bw
6230  **/
6231 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6232                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6233                         struct i40e_asq_cmd_details *cmd_details)
6234 {
6235         enum i40e_status_code status;
6236         struct i40e_aq_desc desc;
6237         u16 bwd_size = sizeof(*bw_data);
6238
6239         i40e_fill_default_direct_cmd_desc(&desc,
6240                                 i40e_aqc_opc_configure_partition_bw);
6241
6242         /* Indirect command */
6243         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6244         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6245
6246         desc.datalen = CPU_TO_LE16(bwd_size);
6247
6248         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6249
6250         return status;
6251 }
6252
6253 /**
6254  * i40e_read_phy_register_clause22
6255  * @hw: pointer to the HW structure
6256  * @reg: register address in the page
6257  * @phy_adr: PHY address on MDIO interface
6258  * @value: PHY register value
6259  *
6260  * Reads specified PHY register value
6261  **/
6262 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6263                                         u16 reg, u8 phy_addr, u16 *value)
6264 {
6265         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6266         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6267         u32 command = 0;
6268         u16 retry = 1000;
6269
6270         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6271                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6272                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6273                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6274                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6275         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6276         do {
6277                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6278                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6279                         status = I40E_SUCCESS;
6280                         break;
6281                 }
6282                 i40e_usec_delay(10);
6283                 retry--;
6284         } while (retry);
6285
6286         if (status) {
6287                 i40e_debug(hw, I40E_DEBUG_PHY,
6288                            "PHY: Can't write command to external PHY.\n");
6289         } else {
6290                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6291                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6292                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6293         }
6294
6295         return status;
6296 }
6297
6298 /**
6299  * i40e_write_phy_register_clause22
6300  * @hw: pointer to the HW structure
6301  * @reg: register address in the page
6302  * @phy_adr: PHY address on MDIO interface
6303  * @value: PHY register value
6304  *
6305  * Writes specified PHY register value
6306  **/
6307 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6308                                         u16 reg, u8 phy_addr, u16 value)
6309 {
6310         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6311         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6312         u32 command  = 0;
6313         u16 retry = 1000;
6314
6315         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6316         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6317
6318         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6319                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6320                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6321                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6322                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6323
6324         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6325         do {
6326                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6327                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6328                         status = I40E_SUCCESS;
6329                         break;
6330                 }
6331                 i40e_usec_delay(10);
6332                 retry--;
6333         } while (retry);
6334
6335         return status;
6336 }
6337
6338 /**
6339  * i40e_read_phy_register_clause45
6340  * @hw: pointer to the HW structure
6341  * @page: registers page number
6342  * @reg: register address in the page
6343  * @phy_adr: PHY address on MDIO interface
6344  * @value: PHY register value
6345  *
6346  * Reads specified PHY register value
6347  **/
6348 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6349                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6350 {
6351         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6352         u32 command  = 0;
6353         u16 retry = 1000;
6354         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6355
6356         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6357                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6358                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6359                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6360                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6361                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6362                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6363         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6364         do {
6365                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6366                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6367                         status = I40E_SUCCESS;
6368                         break;
6369                 }
6370                 i40e_usec_delay(10);
6371                 retry--;
6372         } while (retry);
6373
6374         if (status) {
6375                 i40e_debug(hw, I40E_DEBUG_PHY,
6376                            "PHY: Can't write command to external PHY.\n");
6377                 goto phy_read_end;
6378         }
6379
6380         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6381                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6382                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6383                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6384                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6385                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6386         status = I40E_ERR_TIMEOUT;
6387         retry = 1000;
6388         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6389         do {
6390                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6391                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6392                         status = I40E_SUCCESS;
6393                         break;
6394                 }
6395                 i40e_usec_delay(10);
6396                 retry--;
6397         } while (retry);
6398
6399         if (!status) {
6400                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6401                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6402                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6403         } else {
6404                 i40e_debug(hw, I40E_DEBUG_PHY,
6405                            "PHY: Can't read register value from external PHY.\n");
6406         }
6407
6408 phy_read_end:
6409         return status;
6410 }
6411
6412 /**
6413  * i40e_write_phy_register_clause45
6414  * @hw: pointer to the HW structure
6415  * @page: registers page number
6416  * @reg: register address in the page
6417  * @phy_adr: PHY address on MDIO interface
6418  * @value: PHY register value
6419  *
6420  * Writes value to specified PHY register
6421  **/
6422 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6423                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6424 {
6425         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6426         u32 command  = 0;
6427         u16 retry = 1000;
6428         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6429
6430         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6431                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6432                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6433                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6434                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6435                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6436                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6437         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6438         do {
6439                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6440                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6441                         status = I40E_SUCCESS;
6442                         break;
6443                 }
6444                 i40e_usec_delay(10);
6445                 retry--;
6446         } while (retry);
6447         if (status) {
6448                 i40e_debug(hw, I40E_DEBUG_PHY,
6449                            "PHY: Can't write command to external PHY.\n");
6450                 goto phy_write_end;
6451         }
6452
6453         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6454         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6455
6456         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6457                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6458                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6459                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6460                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6461                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6462         status = I40E_ERR_TIMEOUT;
6463         retry = 1000;
6464         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6465         do {
6466                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6467                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6468                         status = I40E_SUCCESS;
6469                         break;
6470                 }
6471                 i40e_usec_delay(10);
6472                 retry--;
6473         } while (retry);
6474
6475 phy_write_end:
6476         return status;
6477 }
6478
6479 /**
6480  * i40e_write_phy_register
6481  * @hw: pointer to the HW structure
6482  * @page: registers page number
6483  * @reg: register address in the page
6484  * @phy_adr: PHY address on MDIO interface
6485  * @value: PHY register value
6486  *
6487  * Writes value to specified PHY register
6488  **/
6489 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6490                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6491 {
6492         enum i40e_status_code status;
6493
6494         switch (hw->device_id) {
6495         case I40E_DEV_ID_1G_BASE_T_X722:
6496                 status = i40e_write_phy_register_clause22(hw,
6497                         reg, phy_addr, value);
6498                 break;
6499         case I40E_DEV_ID_10G_BASE_T:
6500         case I40E_DEV_ID_10G_BASE_T4:
6501         case I40E_DEV_ID_10G_BASE_T_X722:
6502         case I40E_DEV_ID_25G_B:
6503         case I40E_DEV_ID_25G_SFP28:
6504                 status = i40e_write_phy_register_clause45(hw,
6505                         page, reg, phy_addr, value);
6506                 break;
6507         default:
6508                 status = I40E_ERR_UNKNOWN_PHY;
6509                 break;
6510         }
6511
6512         return status;
6513 }
6514
6515 /**
6516  * i40e_read_phy_register
6517  * @hw: pointer to the HW structure
6518  * @page: registers page number
6519  * @reg: register address in the page
6520  * @phy_adr: PHY address on MDIO interface
6521  * @value: PHY register value
6522  *
6523  * Reads specified PHY register value
6524  **/
6525 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6526                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6527 {
6528         enum i40e_status_code status;
6529
6530         switch (hw->device_id) {
6531         case I40E_DEV_ID_1G_BASE_T_X722:
6532                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6533                                                          value);
6534                 break;
6535         case I40E_DEV_ID_10G_BASE_T:
6536         case I40E_DEV_ID_10G_BASE_T4:
6537         case I40E_DEV_ID_10G_BASE_T_X722:
6538         case I40E_DEV_ID_25G_B:
6539         case I40E_DEV_ID_25G_SFP28:
6540                 status = i40e_read_phy_register_clause45(hw, page, reg,
6541                                                          phy_addr, value);
6542                 break;
6543         default:
6544                 status = I40E_ERR_UNKNOWN_PHY;
6545                 break;
6546         }
6547
6548         return status;
6549 }
6550
6551 /**
6552  * i40e_get_phy_address
6553  * @hw: pointer to the HW structure
6554  * @dev_num: PHY port num that address we want
6555  * @phy_addr: Returned PHY address
6556  *
6557  * Gets PHY address for current port
6558  **/
6559 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6560 {
6561         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6562         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6563
6564         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6565 }
6566
6567 /**
6568  * i40e_blink_phy_led
6569  * @hw: pointer to the HW structure
6570  * @time: time how long led will blinks in secs
6571  * @interval: gap between LED on and off in msecs
6572  *
6573  * Blinks PHY link LED
6574  **/
6575 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6576                                               u32 time, u32 interval)
6577 {
6578         enum i40e_status_code status = I40E_SUCCESS;
6579         u32 i;
6580         u16 led_ctl = 0;
6581         u16 gpio_led_port;
6582         u16 led_reg;
6583         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6584         u8 phy_addr = 0;
6585         u8 port_num;
6586
6587         i = rd32(hw, I40E_PFGEN_PORTNUM);
6588         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6589         phy_addr = i40e_get_phy_address(hw, port_num);
6590
6591         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6592              led_addr++) {
6593                 status = i40e_read_phy_register_clause45(hw,
6594                                                          I40E_PHY_COM_REG_PAGE,
6595                                                          led_addr, phy_addr,
6596                                                          &led_reg);
6597                 if (status)
6598                         goto phy_blinking_end;
6599                 led_ctl = led_reg;
6600                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6601                         led_reg = 0;
6602                         status = i40e_write_phy_register_clause45(hw,
6603                                                          I40E_PHY_COM_REG_PAGE,
6604                                                          led_addr, phy_addr,
6605                                                          led_reg);
6606                         if (status)
6607                                 goto phy_blinking_end;
6608                         break;
6609                 }
6610         }
6611
6612         if (time > 0 && interval > 0) {
6613                 for (i = 0; i < time * 1000; i += interval) {
6614                         status = i40e_read_phy_register_clause45(hw,
6615                                                 I40E_PHY_COM_REG_PAGE,
6616                                                 led_addr, phy_addr, &led_reg);
6617                         if (status)
6618                                 goto restore_config;
6619                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6620                                 led_reg = 0;
6621                         else
6622                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6623                         status = i40e_write_phy_register_clause45(hw,
6624                                                 I40E_PHY_COM_REG_PAGE,
6625                                                 led_addr, phy_addr, led_reg);
6626                         if (status)
6627                                 goto restore_config;
6628                         i40e_msec_delay(interval);
6629                 }
6630         }
6631
6632 restore_config:
6633         status = i40e_write_phy_register_clause45(hw,
6634                                                   I40E_PHY_COM_REG_PAGE,
6635                                                   led_addr, phy_addr, led_ctl);
6636
6637 phy_blinking_end:
6638         return status;
6639 }
6640
6641 /**
6642  * i40e_led_get_phy - return current on/off mode
6643  * @hw: pointer to the hw struct
6644  * @led_addr: address of led register to use
6645  * @val: original value of register to use
6646  *
6647  **/
6648 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6649                                        u16 *val)
6650 {
6651         enum i40e_status_code status = I40E_SUCCESS;
6652         u16 gpio_led_port;
6653         u8 phy_addr = 0;
6654         u16 reg_val;
6655         u16 temp_addr;
6656         u8 port_num;
6657         u32 i;
6658
6659         temp_addr = I40E_PHY_LED_PROV_REG_1;
6660         i = rd32(hw, I40E_PFGEN_PORTNUM);
6661         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6662         phy_addr = i40e_get_phy_address(hw, port_num);
6663
6664         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6665              temp_addr++) {
6666                 status = i40e_read_phy_register_clause45(hw,
6667                                                          I40E_PHY_COM_REG_PAGE,
6668                                                          temp_addr, phy_addr,
6669                                                          &reg_val);
6670                 if (status)
6671                         return status;
6672                 *val = reg_val;
6673                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6674                         *led_addr = temp_addr;
6675                         break;
6676                 }
6677         }
6678         return status;
6679 }
6680
6681 /**
6682  * i40e_led_set_phy
6683  * @hw: pointer to the HW structure
6684  * @on: true or false
6685  * @mode: original val plus bit for set or ignore
6686  * Set led's on or off when controlled by the PHY
6687  *
6688  **/
6689 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6690                                        u16 led_addr, u32 mode)
6691 {
6692         enum i40e_status_code status = I40E_SUCCESS;
6693         u16 led_ctl = 0;
6694         u16 led_reg = 0;
6695         u8 phy_addr = 0;
6696         u8 port_num;
6697         u32 i;
6698
6699         i = rd32(hw, I40E_PFGEN_PORTNUM);
6700         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6701         phy_addr = i40e_get_phy_address(hw, port_num);
6702         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6703                                                  led_addr, phy_addr, &led_reg);
6704         if (status)
6705                 return status;
6706         led_ctl = led_reg;
6707         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6708                 led_reg = 0;
6709                 status = i40e_write_phy_register_clause45(hw,
6710                                                           I40E_PHY_COM_REG_PAGE,
6711                                                           led_addr, phy_addr,
6712                                                           led_reg);
6713                 if (status)
6714                         return status;
6715         }
6716         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6717                                                  led_addr, phy_addr, &led_reg);
6718         if (status)
6719                 goto restore_config;
6720         if (on)
6721                 led_reg = I40E_PHY_LED_MANUAL_ON;
6722         else
6723                 led_reg = 0;
6724         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6725                                                   led_addr, phy_addr, led_reg);
6726         if (status)
6727                 goto restore_config;
6728         if (mode & I40E_PHY_LED_MODE_ORIG) {
6729                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6730                 status = i40e_write_phy_register_clause45(hw,
6731                                                  I40E_PHY_COM_REG_PAGE,
6732                                                  led_addr, phy_addr, led_ctl);
6733         }
6734         return status;
6735 restore_config:
6736         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6737                                                   led_addr, phy_addr, led_ctl);
6738         return status;
6739 }
6740 #endif /* PF_DRIVER */
6741
6742 /**
6743  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6744  * @hw: pointer to the hw struct
6745  * @reg_addr: register address
6746  * @reg_val: ptr to register value
6747  * @cmd_details: pointer to command details structure or NULL
6748  *
6749  * Use the firmware to read the Rx control register,
6750  * especially useful if the Rx unit is under heavy pressure
6751  **/
6752 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6753                                 u32 reg_addr, u32 *reg_val,
6754                                 struct i40e_asq_cmd_details *cmd_details)
6755 {
6756         struct i40e_aq_desc desc;
6757         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6758                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6759         enum i40e_status_code status;
6760
6761         if (reg_val == NULL)
6762                 return I40E_ERR_PARAM;
6763
6764         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6765
6766         cmd_resp->address = CPU_TO_LE32(reg_addr);
6767
6768         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6769
6770         if (status == I40E_SUCCESS)
6771                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6772
6773         return status;
6774 }
6775
6776 /**
6777  * i40e_read_rx_ctl - read from an Rx control register
6778  * @hw: pointer to the hw struct
6779  * @reg_addr: register address
6780  **/
6781 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6782 {
6783         enum i40e_status_code status = I40E_SUCCESS;
6784         bool use_register;
6785         int retry = 5;
6786         u32 val = 0;
6787
6788         use_register = (((hw->aq.api_maj_ver == 1) &&
6789                         (hw->aq.api_min_ver < 5)) ||
6790                         (hw->mac.type == I40E_MAC_X722));
6791         if (!use_register) {
6792 do_retry:
6793                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6794                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6795                         i40e_msec_delay(1);
6796                         retry--;
6797                         goto do_retry;
6798                 }
6799         }
6800
6801         /* if the AQ access failed, try the old-fashioned way */
6802         if (status || use_register)
6803                 val = rd32(hw, reg_addr);
6804
6805         return val;
6806 }
6807
6808 /**
6809  * i40e_aq_rx_ctl_write_register
6810  * @hw: pointer to the hw struct
6811  * @reg_addr: register address
6812  * @reg_val: register value
6813  * @cmd_details: pointer to command details structure or NULL
6814  *
6815  * Use the firmware to write to an Rx control register,
6816  * especially useful if the Rx unit is under heavy pressure
6817  **/
6818 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6819                                 u32 reg_addr, u32 reg_val,
6820                                 struct i40e_asq_cmd_details *cmd_details)
6821 {
6822         struct i40e_aq_desc desc;
6823         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6824                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6825         enum i40e_status_code status;
6826
6827         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6828
6829         cmd->address = CPU_TO_LE32(reg_addr);
6830         cmd->value = CPU_TO_LE32(reg_val);
6831
6832         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6833
6834         return status;
6835 }
6836
6837 /**
6838  * i40e_write_rx_ctl - write to an Rx control register
6839  * @hw: pointer to the hw struct
6840  * @reg_addr: register address
6841  * @reg_val: register value
6842  **/
6843 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6844 {
6845         enum i40e_status_code status = I40E_SUCCESS;
6846         bool use_register;
6847         int retry = 5;
6848
6849         use_register = (((hw->aq.api_maj_ver == 1) &&
6850                         (hw->aq.api_min_ver < 5)) ||
6851                         (hw->mac.type == I40E_MAC_X722));
6852         if (!use_register) {
6853 do_retry:
6854                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6855                                                        reg_val, NULL);
6856                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6857                         i40e_msec_delay(1);
6858                         retry--;
6859                         goto do_retry;
6860                 }
6861         }
6862
6863         /* if the AQ access failed, try the old-fashioned way */
6864         if (status || use_register)
6865                 wr32(hw, reg_addr, reg_val);
6866 }
6867
6868 /**
6869  * i40e_aq_set_phy_register
6870  * @hw: pointer to the hw struct
6871  * @phy_select: select which phy should be accessed
6872  * @dev_addr: PHY device address
6873  * @reg_addr: PHY register address
6874  * @reg_val: new register value
6875  * @cmd_details: pointer to command details structure or NULL
6876  *
6877  * Write the external PHY register.
6878  **/
6879 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
6880                                 u8 phy_select, u8 dev_addr,
6881                                 u32 reg_addr, u32 reg_val,
6882                                 struct i40e_asq_cmd_details *cmd_details)
6883 {
6884         struct i40e_aq_desc desc;
6885         struct i40e_aqc_phy_register_access *cmd =
6886                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6887         enum i40e_status_code status;
6888
6889         i40e_fill_default_direct_cmd_desc(&desc,
6890                                           i40e_aqc_opc_set_phy_register);
6891
6892         cmd->phy_interface = phy_select;
6893         cmd->dev_addres = dev_addr;
6894         cmd->reg_address = reg_addr;
6895         cmd->reg_value = reg_val;
6896
6897         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6898
6899         return status;
6900 }
6901
6902 /**
6903  * i40e_aq_get_phy_register
6904  * @hw: pointer to the hw struct
6905  * @phy_select: select which phy should be accessed
6906  * @dev_addr: PHY device address
6907  * @reg_addr: PHY register address
6908  * @reg_val: read register value
6909  * @cmd_details: pointer to command details structure or NULL
6910  *
6911  * Read the external PHY register.
6912  **/
6913 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
6914                                 u8 phy_select, u8 dev_addr,
6915                                 u32 reg_addr, u32 *reg_val,
6916                                 struct i40e_asq_cmd_details *cmd_details)
6917 {
6918         struct i40e_aq_desc desc;
6919         struct i40e_aqc_phy_register_access *cmd =
6920                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
6921         enum i40e_status_code status;
6922
6923         i40e_fill_default_direct_cmd_desc(&desc,
6924                                           i40e_aqc_opc_get_phy_register);
6925
6926         cmd->phy_interface = phy_select;
6927         cmd->dev_addres = dev_addr;
6928         cmd->reg_address = reg_addr;
6929
6930         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6931         if (!status)
6932                 *reg_val = cmd->reg_value;
6933
6934         return status;
6935 }
6936
6937 #ifdef VF_DRIVER
6938
6939 /**
6940  * i40e_aq_send_msg_to_pf
6941  * @hw: pointer to the hardware structure
6942  * @v_opcode: opcodes for VF-PF communication
6943  * @v_retval: return error code
6944  * @msg: pointer to the msg buffer
6945  * @msglen: msg length
6946  * @cmd_details: pointer to command details
6947  *
6948  * Send message to PF driver using admin queue. By default, this message
6949  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6950  * completion before returning.
6951  **/
6952 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6953                                 enum virtchnl_ops v_opcode,
6954                                 enum i40e_status_code v_retval,
6955                                 u8 *msg, u16 msglen,
6956                                 struct i40e_asq_cmd_details *cmd_details)
6957 {
6958         struct i40e_aq_desc desc;
6959         struct i40e_asq_cmd_details details;
6960         enum i40e_status_code status;
6961
6962         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6963         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6964         desc.cookie_high = CPU_TO_LE32(v_opcode);
6965         desc.cookie_low = CPU_TO_LE32(v_retval);
6966         if (msglen) {
6967                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6968                                                 | I40E_AQ_FLAG_RD));
6969                 if (msglen > I40E_AQ_LARGE_BUF)
6970                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6971                 desc.datalen = CPU_TO_LE16(msglen);
6972         }
6973         if (!cmd_details) {
6974                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6975                 details.async = true;
6976                 cmd_details = &details;
6977         }
6978         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6979                                        msglen, cmd_details);
6980         return status;
6981 }
6982
6983 /**
6984  * i40e_vf_parse_hw_config
6985  * @hw: pointer to the hardware structure
6986  * @msg: pointer to the virtual channel VF resource structure
6987  *
6988  * Given a VF resource message from the PF, populate the hw struct
6989  * with appropriate information.
6990  **/
6991 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6992                              struct virtchnl_vf_resource *msg)
6993 {
6994         struct virtchnl_vsi_resource *vsi_res;
6995         int i;
6996
6997         vsi_res = &msg->vsi_res[0];
6998
6999         hw->dev_caps.num_vsis = msg->num_vsis;
7000         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7001         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7002         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7003         hw->dev_caps.dcb = msg->vf_offload_flags &
7004                            VIRTCHNL_VF_OFFLOAD_L2;
7005         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7006                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7007         for (i = 0; i < msg->num_vsis; i++) {
7008                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7009                         i40e_memcpy(hw->mac.perm_addr,
7010                                     vsi_res->default_mac_addr,
7011                                     ETH_ALEN,
7012                                     I40E_NONDMA_TO_NONDMA);
7013                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7014                                     ETH_ALEN,
7015                                     I40E_NONDMA_TO_NONDMA);
7016                 }
7017                 vsi_res++;
7018         }
7019 }
7020
7021 /**
7022  * i40e_vf_reset
7023  * @hw: pointer to the hardware structure
7024  *
7025  * Send a VF_RESET message to the PF. Does not wait for response from PF
7026  * as none will be forthcoming. Immediately after calling this function,
7027  * the admin queue should be shut down and (optionally) reinitialized.
7028  **/
7029 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7030 {
7031         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7032                                       I40E_SUCCESS, NULL, 0, NULL);
7033 }
7034 #endif /* VF_DRIVER */
7035
7036 /**
7037  * i40e_aq_set_arp_proxy_config
7038  * @hw: pointer to the HW structure
7039  * @proxy_config - pointer to proxy config command table struct
7040  * @cmd_details: pointer to command details
7041  *
7042  * Set ARP offload parameters from pre-populated
7043  * i40e_aqc_arp_proxy_data struct
7044  **/
7045 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7046                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7047                                 struct i40e_asq_cmd_details *cmd_details)
7048 {
7049         struct i40e_aq_desc desc;
7050         enum i40e_status_code status;
7051
7052         if (!proxy_config)
7053                 return I40E_ERR_PARAM;
7054
7055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7056
7057         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7058         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7059         desc.params.external.addr_high =
7060                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7061         desc.params.external.addr_low =
7062                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7063         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7064
7065         status = i40e_asq_send_command(hw, &desc, proxy_config,
7066                                        sizeof(struct i40e_aqc_arp_proxy_data),
7067                                        cmd_details);
7068
7069         return status;
7070 }
7071
7072 /**
7073  * i40e_aq_opc_set_ns_proxy_table_entry
7074  * @hw: pointer to the HW structure
7075  * @ns_proxy_table_entry: pointer to NS table entry command struct
7076  * @cmd_details: pointer to command details
7077  *
7078  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7079  * from pre-populated i40e_aqc_ns_proxy_data struct
7080  **/
7081 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7082                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7083                         struct i40e_asq_cmd_details *cmd_details)
7084 {
7085         struct i40e_aq_desc desc;
7086         enum i40e_status_code status;
7087
7088         if (!ns_proxy_table_entry)
7089                 return I40E_ERR_PARAM;
7090
7091         i40e_fill_default_direct_cmd_desc(&desc,
7092                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7093
7094         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7095         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7096         desc.params.external.addr_high =
7097                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7098         desc.params.external.addr_low =
7099                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7100         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7101
7102         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7103                                        sizeof(struct i40e_aqc_ns_proxy_data),
7104                                        cmd_details);
7105
7106         return status;
7107 }
7108
7109 /**
7110  * i40e_aq_set_clear_wol_filter
7111  * @hw: pointer to the hw struct
7112  * @filter_index: index of filter to modify (0-7)
7113  * @filter: buffer containing filter to be set
7114  * @set_filter: true to set filter, false to clear filter
7115  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7116  *              if false, pass through packets may cause wake-up
7117  * @filter_valid: true if filter action is valid
7118  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7119  * @cmd_details: pointer to command details structure or NULL
7120  *
7121  * Set or clear WoL filter for port attached to the PF
7122  **/
7123 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7124                                 u8 filter_index,
7125                                 struct i40e_aqc_set_wol_filter_data *filter,
7126                                 bool set_filter, bool no_wol_tco,
7127                                 bool filter_valid, bool no_wol_tco_valid,
7128                                 struct i40e_asq_cmd_details *cmd_details)
7129 {
7130         struct i40e_aq_desc desc;
7131         struct i40e_aqc_set_wol_filter *cmd =
7132                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7133         enum i40e_status_code status;
7134         u16 cmd_flags = 0;
7135         u16 valid_flags = 0;
7136         u16 buff_len = 0;
7137
7138         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7139
7140         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7141                 return  I40E_ERR_PARAM;
7142         cmd->filter_index = CPU_TO_LE16(filter_index);
7143
7144         if (set_filter) {
7145                 if (!filter)
7146                         return  I40E_ERR_PARAM;
7147
7148                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7149                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7150         }
7151
7152         if (no_wol_tco)
7153                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7154         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7155
7156         if (filter_valid)
7157                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7158         if (no_wol_tco_valid)
7159                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7160         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7161
7162         buff_len = sizeof(*filter);
7163         desc.datalen = CPU_TO_LE16(buff_len);
7164
7165         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7166         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7167
7168         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7169         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7170
7171         status = i40e_asq_send_command(hw, &desc, filter,
7172                                        buff_len, cmd_details);
7173
7174         return status;
7175 }
7176
7177 /**
7178  * i40e_aq_get_wake_event_reason
7179  * @hw: pointer to the hw struct
7180  * @wake_reason: return value, index of matching filter
7181  * @cmd_details: pointer to command details structure or NULL
7182  *
7183  * Get information for the reason of a Wake Up event
7184  **/
7185 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7186                                 u16 *wake_reason,
7187                                 struct i40e_asq_cmd_details *cmd_details)
7188 {
7189         struct i40e_aq_desc desc;
7190         struct i40e_aqc_get_wake_reason_completion *resp =
7191                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7192         enum i40e_status_code status;
7193
7194         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7195
7196         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7197
7198         if (status == I40E_SUCCESS)
7199                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7200
7201         return status;
7202 }
7203
7204 /**
7205 * i40e_aq_clear_all_wol_filters
7206 * @hw: pointer to the hw struct
7207 * @cmd_details: pointer to command details structure or NULL
7208 *
7209 * Get information for the reason of a Wake Up event
7210 **/
7211 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7212         struct i40e_asq_cmd_details *cmd_details)
7213 {
7214         struct i40e_aq_desc desc;
7215         enum i40e_status_code status;
7216
7217         i40e_fill_default_direct_cmd_desc(&desc,
7218                                           i40e_aqc_opc_clear_all_wol_filters);
7219
7220         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7221
7222         return status;
7223 }
7224
7225
7226 /**
7227  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7228  * @hw: pointer to the hw struct
7229  * @buff: command buffer (size in bytes = buff_size)
7230  * @buff_size: buffer size in bytes
7231  * @track_id: package tracking id
7232  * @error_offset: returns error offset
7233  * @error_info: returns error information
7234  * @cmd_details: pointer to command details structure or NULL
7235  **/
7236 enum
7237 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7238                                    u16 buff_size, u32 track_id,
7239                                    u32 *error_offset, u32 *error_info,
7240                                    struct i40e_asq_cmd_details *cmd_details)
7241 {
7242         struct i40e_aq_desc desc;
7243         struct i40e_aqc_write_personalization_profile *cmd =
7244                 (struct i40e_aqc_write_personalization_profile *)
7245                 &desc.params.raw;
7246         struct i40e_aqc_write_ddp_resp *resp;
7247         enum i40e_status_code status;
7248
7249         i40e_fill_default_direct_cmd_desc(&desc,
7250                                   i40e_aqc_opc_write_personalization_profile);
7251
7252         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7253         if (buff_size > I40E_AQ_LARGE_BUF)
7254                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7255
7256         desc.datalen = CPU_TO_LE16(buff_size);
7257
7258         cmd->profile_track_id = CPU_TO_LE32(track_id);
7259
7260         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7261         if (!status) {
7262                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7263                 if (error_offset)
7264                         *error_offset = LE32_TO_CPU(resp->error_offset);
7265                 if (error_info)
7266                         *error_info = LE32_TO_CPU(resp->error_info);
7267         }
7268
7269         return status;
7270 }
7271
7272 /**
7273  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7274  * @hw: pointer to the hw struct
7275  * @buff: command buffer (size in bytes = buff_size)
7276  * @buff_size: buffer size in bytes
7277  * @cmd_details: pointer to command details structure or NULL
7278  **/
7279 enum
7280 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7281                                       u16 buff_size, u8 flags,
7282                                       struct i40e_asq_cmd_details *cmd_details)
7283 {
7284         struct i40e_aq_desc desc;
7285         struct i40e_aqc_get_applied_profiles *cmd =
7286                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7287         enum i40e_status_code status;
7288
7289         i40e_fill_default_direct_cmd_desc(&desc,
7290                           i40e_aqc_opc_get_personalization_profile_list);
7291
7292         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7293         if (buff_size > I40E_AQ_LARGE_BUF)
7294                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7295         desc.datalen = CPU_TO_LE16(buff_size);
7296
7297         cmd->flags = flags;
7298
7299         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7300
7301         return status;
7302 }
7303
7304 /**
7305  * i40e_find_segment_in_package
7306  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7307  * @pkg_hdr: pointer to the package header to be searched
7308  *
7309  * This function searches a package file for a particular segment type. On
7310  * success it returns a pointer to the segment header, otherwise it will
7311  * return NULL.
7312  **/
7313 struct i40e_generic_seg_header *
7314 i40e_find_segment_in_package(u32 segment_type,
7315                              struct i40e_package_header *pkg_hdr)
7316 {
7317         struct i40e_generic_seg_header *segment;
7318         u32 i;
7319
7320         /* Search all package segments for the requested segment type */
7321         for (i = 0; i < pkg_hdr->segment_count; i++) {
7322                 segment =
7323                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7324                          pkg_hdr->segment_offset[i]);
7325
7326                 if (segment->type == segment_type)
7327                         return segment;
7328         }
7329
7330         return NULL;
7331 }
7332
7333 /**
7334  * i40e_write_profile
7335  * @hw: pointer to the hardware structure
7336  * @profile: pointer to the profile segment of the package to be downloaded
7337  * @track_id: package tracking id
7338  *
7339  * Handles the download of a complete package.
7340  */
7341 enum i40e_status_code
7342 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7343                    u32 track_id)
7344 {
7345         enum i40e_status_code status = I40E_SUCCESS;
7346         struct i40e_section_table *sec_tbl;
7347         struct i40e_profile_section_header *sec = NULL;
7348         u32 dev_cnt;
7349         u32 vendor_dev_id;
7350         u32 *nvm;
7351         u32 section_size = 0;
7352         u32 offset = 0, info = 0;
7353         u32 i;
7354
7355         if (!track_id) {
7356                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0.");
7357                 return I40E_NOT_SUPPORTED;
7358         }
7359
7360         dev_cnt = profile->device_table_count;
7361
7362         for (i = 0; i < dev_cnt; i++) {
7363                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7364                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7365                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
7366                                 break;
7367         }
7368         if (i == dev_cnt) {
7369                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7370                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7371         }
7372
7373         nvm = (u32 *)&profile->device_table[dev_cnt];
7374         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7375
7376         for (i = 0; i < sec_tbl->section_count; i++) {
7377                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7378                                              sec_tbl->section_offset[i]);
7379
7380                 /* Skip 'AQ', 'note' and 'name' sections */
7381                 if (sec->section.type != SECTION_TYPE_MMIO)
7382                         continue;
7383
7384                 section_size = sec->section.size +
7385                         sizeof(struct i40e_profile_section_header);
7386
7387                 /* Write profile */
7388                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7389                                            track_id, &offset, &info, NULL);
7390                 if (status) {
7391                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7392                                    "Failed to write profile: offset %d, info %d",
7393                                    offset, info);
7394                         break;
7395                 }
7396         }
7397         return status;
7398 }
7399
7400 /**
7401  * i40e_add_pinfo_to_list
7402  * @hw: pointer to the hardware structure
7403  * @profile: pointer to the profile segment of the package
7404  * @profile_info_sec: buffer for information section
7405  * @track_id: package tracking id
7406  *
7407  * Register a profile to the list of loaded profiles.
7408  */
7409 enum i40e_status_code
7410 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7411                        struct i40e_profile_segment *profile,
7412                        u8 *profile_info_sec, u32 track_id)
7413 {
7414         enum i40e_status_code status = I40E_SUCCESS;
7415         struct i40e_profile_section_header *sec = NULL;
7416         struct i40e_profile_info *pinfo;
7417         u32 offset = 0, info = 0;
7418
7419         sec = (struct i40e_profile_section_header *)profile_info_sec;
7420         sec->tbl_size = 1;
7421         sec->data_end = sizeof(struct i40e_profile_section_header) +
7422                         sizeof(struct i40e_profile_info);
7423         sec->section.type = SECTION_TYPE_INFO;
7424         sec->section.offset = sizeof(struct i40e_profile_section_header);
7425         sec->section.size = sizeof(struct i40e_profile_info);
7426         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7427                                              sec->section.offset);
7428         pinfo->track_id = track_id;
7429         pinfo->version = profile->version;
7430         pinfo->op = I40E_DDP_ADD_TRACKID;
7431         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7432
7433         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7434                                 track_id, &offset, &info, NULL);
7435         return status;
7436 }