1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
92 * @hw: debug mask related to admin queue
94 * @desc: pointer to admin queue descriptor
95 * @buffer: pointer to command buffer
96 * @buf_len: max length of buffer
98 * Dumps debug log about adminq command with descriptor contents.
100 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
101 void *buffer, u16 buf_len)
103 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
104 u16 len = LE16_TO_CPU(aq_desc->datalen);
105 u8 *buf = (u8 *)buffer;
108 if ((!(mask & hw->debug_mask)) || (desc == NULL))
112 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
113 LE16_TO_CPU(aq_desc->opcode),
114 LE16_TO_CPU(aq_desc->flags),
115 LE16_TO_CPU(aq_desc->datalen),
116 LE16_TO_CPU(aq_desc->retval));
117 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
118 LE32_TO_CPU(aq_desc->cookie_high),
119 LE32_TO_CPU(aq_desc->cookie_low));
120 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
121 LE32_TO_CPU(aq_desc->params.internal.param0),
122 LE32_TO_CPU(aq_desc->params.internal.param1));
123 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
124 LE32_TO_CPU(aq_desc->params.external.addr_high),
125 LE32_TO_CPU(aq_desc->params.external.addr_low));
127 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
128 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
131 /* write the full 16-byte chunks */
132 for (i = 0; i < (len - 16); i += 16)
134 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
135 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
136 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
137 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
138 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
139 /* write whatever's left over without overrunning the buffer */
144 memset(d_buf, 0, sizeof(d_buf));
145 j += sprintf(d_buf, "\t0x%04X ", i);
147 j += sprintf(&d_buf[j], " %02X", buf[i++]);
148 i40e_debug(hw, mask, "%s\n", d_buf);
154 * i40e_check_asq_alive
155 * @hw: pointer to the hw struct
157 * Returns true if Queue is enabled else false.
159 bool i40e_check_asq_alive(struct i40e_hw *hw)
162 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
168 * i40e_aq_queue_shutdown
169 * @hw: pointer to the hw struct
170 * @unloading: is the driver unloading itself
172 * Tell the Firmware that we're shutting down the AdminQ and whether
173 * or not the driver is unloading as well.
175 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
178 struct i40e_aq_desc desc;
179 struct i40e_aqc_queue_shutdown *cmd =
180 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
181 enum i40e_status_code status;
183 i40e_fill_default_direct_cmd_desc(&desc,
184 i40e_aqc_opc_queue_shutdown);
187 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
188 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
193 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
194 * hardware to a bit-field that can be used by SW to more easily determine the
197 * Macros are used to shorten the table lines and make this table human
200 * We store the PTYPE in the top byte of the bit field - this is just so that
201 * we can check that the table doesn't have a row missing, as the index into
202 * the table should be the PTYPE.
206 * IF NOT i40e_ptype_lookup[ptype].known
209 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
210 * Use the rest of the fields to look at the tunnels, inner protocols, etc
212 * Use the enum i40e_rx_l2_ptype to decode the packet type
216 /* macro to make the table lines short */
217 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
220 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
221 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
222 I40E_RX_PTYPE_##OUTER_FRAG, \
223 I40E_RX_PTYPE_TUNNEL_##T, \
224 I40E_RX_PTYPE_TUNNEL_END_##TE, \
225 I40E_RX_PTYPE_##TEF, \
226 I40E_RX_PTYPE_INNER_PROT_##I, \
227 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
229 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
230 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
232 /* shorter macros makes the table fit but are terse */
233 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
234 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
235 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
237 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
238 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
239 /* L2 Packet types */
240 I40E_PTT_UNUSED_ENTRY(0),
241 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
242 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
243 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
244 I40E_PTT_UNUSED_ENTRY(4),
245 I40E_PTT_UNUSED_ENTRY(5),
246 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
247 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
248 I40E_PTT_UNUSED_ENTRY(8),
249 I40E_PTT_UNUSED_ENTRY(9),
250 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
251 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
252 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
253 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
254 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
255 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
256 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
257 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
258 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
259 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
260 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
261 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
263 /* Non Tunneled IPv4 */
264 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
265 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
266 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
267 I40E_PTT_UNUSED_ENTRY(25),
268 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
269 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
270 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
273 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
274 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
275 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
276 I40E_PTT_UNUSED_ENTRY(32),
277 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
278 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
279 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
282 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
283 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
284 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(39),
286 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
287 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
288 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
290 /* IPv4 --> GRE/NAT */
291 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
293 /* IPv4 --> GRE/NAT --> IPv4 */
294 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
295 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
296 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
297 I40E_PTT_UNUSED_ENTRY(47),
298 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
299 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
300 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
302 /* IPv4 --> GRE/NAT --> IPv6 */
303 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
304 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
305 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(54),
307 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
308 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
309 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
311 /* IPv4 --> GRE/NAT --> MAC */
312 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
314 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
315 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
316 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
317 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
318 I40E_PTT_UNUSED_ENTRY(62),
319 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
320 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
321 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
323 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
324 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
325 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
326 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(69),
328 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
329 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
330 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
332 /* IPv4 --> GRE/NAT --> MAC/VLAN */
333 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
335 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
336 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
337 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
338 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
339 I40E_PTT_UNUSED_ENTRY(77),
340 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
341 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
342 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
344 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
345 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
346 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
347 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
348 I40E_PTT_UNUSED_ENTRY(84),
349 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
350 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
351 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
353 /* Non Tunneled IPv6 */
354 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
355 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
356 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
357 I40E_PTT_UNUSED_ENTRY(91),
358 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
359 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
360 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
363 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
364 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
365 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
366 I40E_PTT_UNUSED_ENTRY(98),
367 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
368 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
369 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
372 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
373 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
374 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(105),
376 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
377 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
378 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
380 /* IPv6 --> GRE/NAT */
381 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
383 /* IPv6 --> GRE/NAT -> IPv4 */
384 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
385 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
386 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
387 I40E_PTT_UNUSED_ENTRY(113),
388 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
389 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
390 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
392 /* IPv6 --> GRE/NAT -> IPv6 */
393 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
394 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
395 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(120),
397 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
398 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
399 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
401 /* IPv6 --> GRE/NAT -> MAC */
402 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
404 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
405 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
406 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
407 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
408 I40E_PTT_UNUSED_ENTRY(128),
409 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
410 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
411 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
413 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
414 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
415 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
416 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(135),
418 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
419 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
420 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
422 /* IPv6 --> GRE/NAT -> MAC/VLAN */
423 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
425 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
426 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
427 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
428 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
429 I40E_PTT_UNUSED_ENTRY(143),
430 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
431 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
432 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
434 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
435 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
436 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
437 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
438 I40E_PTT_UNUSED_ENTRY(150),
439 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
440 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
441 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
444 I40E_PTT_UNUSED_ENTRY(154),
445 I40E_PTT_UNUSED_ENTRY(155),
446 I40E_PTT_UNUSED_ENTRY(156),
447 I40E_PTT_UNUSED_ENTRY(157),
448 I40E_PTT_UNUSED_ENTRY(158),
449 I40E_PTT_UNUSED_ENTRY(159),
451 I40E_PTT_UNUSED_ENTRY(160),
452 I40E_PTT_UNUSED_ENTRY(161),
453 I40E_PTT_UNUSED_ENTRY(162),
454 I40E_PTT_UNUSED_ENTRY(163),
455 I40E_PTT_UNUSED_ENTRY(164),
456 I40E_PTT_UNUSED_ENTRY(165),
457 I40E_PTT_UNUSED_ENTRY(166),
458 I40E_PTT_UNUSED_ENTRY(167),
459 I40E_PTT_UNUSED_ENTRY(168),
460 I40E_PTT_UNUSED_ENTRY(169),
462 I40E_PTT_UNUSED_ENTRY(170),
463 I40E_PTT_UNUSED_ENTRY(171),
464 I40E_PTT_UNUSED_ENTRY(172),
465 I40E_PTT_UNUSED_ENTRY(173),
466 I40E_PTT_UNUSED_ENTRY(174),
467 I40E_PTT_UNUSED_ENTRY(175),
468 I40E_PTT_UNUSED_ENTRY(176),
469 I40E_PTT_UNUSED_ENTRY(177),
470 I40E_PTT_UNUSED_ENTRY(178),
471 I40E_PTT_UNUSED_ENTRY(179),
473 I40E_PTT_UNUSED_ENTRY(180),
474 I40E_PTT_UNUSED_ENTRY(181),
475 I40E_PTT_UNUSED_ENTRY(182),
476 I40E_PTT_UNUSED_ENTRY(183),
477 I40E_PTT_UNUSED_ENTRY(184),
478 I40E_PTT_UNUSED_ENTRY(185),
479 I40E_PTT_UNUSED_ENTRY(186),
480 I40E_PTT_UNUSED_ENTRY(187),
481 I40E_PTT_UNUSED_ENTRY(188),
482 I40E_PTT_UNUSED_ENTRY(189),
484 I40E_PTT_UNUSED_ENTRY(190),
485 I40E_PTT_UNUSED_ENTRY(191),
486 I40E_PTT_UNUSED_ENTRY(192),
487 I40E_PTT_UNUSED_ENTRY(193),
488 I40E_PTT_UNUSED_ENTRY(194),
489 I40E_PTT_UNUSED_ENTRY(195),
490 I40E_PTT_UNUSED_ENTRY(196),
491 I40E_PTT_UNUSED_ENTRY(197),
492 I40E_PTT_UNUSED_ENTRY(198),
493 I40E_PTT_UNUSED_ENTRY(199),
495 I40E_PTT_UNUSED_ENTRY(200),
496 I40E_PTT_UNUSED_ENTRY(201),
497 I40E_PTT_UNUSED_ENTRY(202),
498 I40E_PTT_UNUSED_ENTRY(203),
499 I40E_PTT_UNUSED_ENTRY(204),
500 I40E_PTT_UNUSED_ENTRY(205),
501 I40E_PTT_UNUSED_ENTRY(206),
502 I40E_PTT_UNUSED_ENTRY(207),
503 I40E_PTT_UNUSED_ENTRY(208),
504 I40E_PTT_UNUSED_ENTRY(209),
506 I40E_PTT_UNUSED_ENTRY(210),
507 I40E_PTT_UNUSED_ENTRY(211),
508 I40E_PTT_UNUSED_ENTRY(212),
509 I40E_PTT_UNUSED_ENTRY(213),
510 I40E_PTT_UNUSED_ENTRY(214),
511 I40E_PTT_UNUSED_ENTRY(215),
512 I40E_PTT_UNUSED_ENTRY(216),
513 I40E_PTT_UNUSED_ENTRY(217),
514 I40E_PTT_UNUSED_ENTRY(218),
515 I40E_PTT_UNUSED_ENTRY(219),
517 I40E_PTT_UNUSED_ENTRY(220),
518 I40E_PTT_UNUSED_ENTRY(221),
519 I40E_PTT_UNUSED_ENTRY(222),
520 I40E_PTT_UNUSED_ENTRY(223),
521 I40E_PTT_UNUSED_ENTRY(224),
522 I40E_PTT_UNUSED_ENTRY(225),
523 I40E_PTT_UNUSED_ENTRY(226),
524 I40E_PTT_UNUSED_ENTRY(227),
525 I40E_PTT_UNUSED_ENTRY(228),
526 I40E_PTT_UNUSED_ENTRY(229),
528 I40E_PTT_UNUSED_ENTRY(230),
529 I40E_PTT_UNUSED_ENTRY(231),
530 I40E_PTT_UNUSED_ENTRY(232),
531 I40E_PTT_UNUSED_ENTRY(233),
532 I40E_PTT_UNUSED_ENTRY(234),
533 I40E_PTT_UNUSED_ENTRY(235),
534 I40E_PTT_UNUSED_ENTRY(236),
535 I40E_PTT_UNUSED_ENTRY(237),
536 I40E_PTT_UNUSED_ENTRY(238),
537 I40E_PTT_UNUSED_ENTRY(239),
539 I40E_PTT_UNUSED_ENTRY(240),
540 I40E_PTT_UNUSED_ENTRY(241),
541 I40E_PTT_UNUSED_ENTRY(242),
542 I40E_PTT_UNUSED_ENTRY(243),
543 I40E_PTT_UNUSED_ENTRY(244),
544 I40E_PTT_UNUSED_ENTRY(245),
545 I40E_PTT_UNUSED_ENTRY(246),
546 I40E_PTT_UNUSED_ENTRY(247),
547 I40E_PTT_UNUSED_ENTRY(248),
548 I40E_PTT_UNUSED_ENTRY(249),
550 I40E_PTT_UNUSED_ENTRY(250),
551 I40E_PTT_UNUSED_ENTRY(251),
552 I40E_PTT_UNUSED_ENTRY(252),
553 I40E_PTT_UNUSED_ENTRY(253),
554 I40E_PTT_UNUSED_ENTRY(254),
555 I40E_PTT_UNUSED_ENTRY(255)
560 * i40e_validate_mac_addr - Validate unicast MAC address
561 * @mac_addr: pointer to MAC address
563 * Tests a MAC address to ensure it is a valid Individual Address
565 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
567 enum i40e_status_code status = I40E_SUCCESS;
569 DEBUGFUNC("i40e_validate_mac_addr");
571 /* Broadcast addresses ARE multicast addresses
572 * Make sure it is not a multicast address
573 * Reject the zero address
575 if (I40E_IS_MULTICAST(mac_addr) ||
576 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
577 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
578 status = I40E_ERR_INVALID_MAC_ADDR;
585 * i40e_init_shared_code - Initialize the shared code
586 * @hw: pointer to hardware structure
588 * This assigns the MAC type and PHY code and inits the NVM.
589 * Does not touch the hardware. This function must be called prior to any
590 * other function in the shared code. The i40e_hw structure should be
591 * memset to 0 prior to calling this function. The following fields in
592 * hw structure should be filled in prior to calling this function:
593 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
594 * subsystem_vendor_id, and revision_id
596 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
598 enum i40e_status_code status = I40E_SUCCESS;
599 u32 port, ari, func_rid;
601 DEBUGFUNC("i40e_init_shared_code");
603 i40e_set_mac_type(hw);
605 switch (hw->mac.type) {
609 return I40E_ERR_DEVICE_NOT_SUPPORTED;
612 hw->phy.get_link_info = true;
614 /* Determine port number and PF number*/
615 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
616 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
618 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
619 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
620 func_rid = rd32(hw, I40E_PF_FUNC_RID);
622 hw->pf_id = (u8)(func_rid & 0xff);
624 hw->pf_id = (u8)(func_rid & 0x7);
626 status = i40e_init_nvm(hw);
631 * i40e_aq_mac_address_read - Retrieve the MAC addresses
632 * @hw: pointer to the hw struct
633 * @flags: a return indicator of what addresses were added to the addr store
634 * @addrs: the requestor's mac addr store
635 * @cmd_details: pointer to command details structure or NULL
637 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
639 struct i40e_aqc_mac_address_read_data *addrs,
640 struct i40e_asq_cmd_details *cmd_details)
642 struct i40e_aq_desc desc;
643 struct i40e_aqc_mac_address_read *cmd_data =
644 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
645 enum i40e_status_code status;
647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
648 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
650 status = i40e_asq_send_command(hw, &desc, addrs,
651 sizeof(*addrs), cmd_details);
652 *flags = LE16_TO_CPU(cmd_data->command_flags);
658 * i40e_aq_mac_address_write - Change the MAC addresses
659 * @hw: pointer to the hw struct
660 * @flags: indicates which MAC to be written
661 * @mac_addr: address to write
662 * @cmd_details: pointer to command details structure or NULL
664 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
665 u16 flags, u8 *mac_addr,
666 struct i40e_asq_cmd_details *cmd_details)
668 struct i40e_aq_desc desc;
669 struct i40e_aqc_mac_address_write *cmd_data =
670 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
671 enum i40e_status_code status;
673 i40e_fill_default_direct_cmd_desc(&desc,
674 i40e_aqc_opc_mac_address_write);
675 cmd_data->command_flags = CPU_TO_LE16(flags);
676 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
677 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
678 ((u32)mac_addr[3] << 16) |
679 ((u32)mac_addr[4] << 8) |
682 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
688 * i40e_get_mac_addr - get MAC address
689 * @hw: pointer to the HW structure
690 * @mac_addr: pointer to MAC address
692 * Reads the adapter's MAC address from register
694 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
696 struct i40e_aqc_mac_address_read_data addrs;
697 enum i40e_status_code status;
700 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
702 if (flags & I40E_AQC_LAN_ADDR_VALID)
703 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
709 * i40e_get_port_mac_addr - get Port MAC address
710 * @hw: pointer to the HW structure
711 * @mac_addr: pointer to Port MAC address
713 * Reads the adapter's Port MAC address
715 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
717 struct i40e_aqc_mac_address_read_data addrs;
718 enum i40e_status_code status;
721 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
725 if (flags & I40E_AQC_PORT_ADDR_VALID)
726 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
728 status = I40E_ERR_INVALID_MAC_ADDR;
734 * i40e_pre_tx_queue_cfg - pre tx queue configure
735 * @hw: pointer to the HW structure
736 * @queue: target pf queue index
737 * @enable: state change request
739 * Handles hw requirement to indicate intention to enable
740 * or disable target queue.
742 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
744 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
748 if (abs_queue_idx >= 128) {
749 reg_block = abs_queue_idx / 128;
750 abs_queue_idx %= 128;
753 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
754 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
755 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
758 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
760 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
762 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
766 * i40e_read_pba_string - Reads part number string from EEPROM
767 * @hw: pointer to hardware structure
768 * @pba_num: stores the part number string from the EEPROM
769 * @pba_num_size: part number string buffer length
771 * Reads the part number string from the EEPROM.
773 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
776 enum i40e_status_code status = I40E_SUCCESS;
782 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
783 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
784 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
788 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
789 if (status != I40E_SUCCESS) {
790 DEBUGOUT("Failed to read PBA Block pointer.\n");
794 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
795 if (status != I40E_SUCCESS) {
796 DEBUGOUT("Failed to read PBA Block size.\n");
800 /* Subtract one to get PBA word count (PBA Size word is included in
804 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
805 DEBUGOUT("Buffer to small for PBA data.\n");
806 return I40E_ERR_PARAM;
809 for (i = 0; i < pba_size; i++) {
810 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
811 if (status != I40E_SUCCESS) {
812 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
816 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
817 pba_num[(i * 2) + 1] = pba_word & 0xFF;
819 pba_num[(pba_size * 2)] = '\0';
825 * i40e_get_media_type - Gets media type
826 * @hw: pointer to the hardware structure
828 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
830 enum i40e_media_type media;
832 switch (hw->phy.link_info.phy_type) {
833 case I40E_PHY_TYPE_10GBASE_SR:
834 case I40E_PHY_TYPE_10GBASE_LR:
835 case I40E_PHY_TYPE_1000BASE_SX:
836 case I40E_PHY_TYPE_1000BASE_LX:
837 case I40E_PHY_TYPE_40GBASE_SR4:
838 case I40E_PHY_TYPE_40GBASE_LR4:
839 media = I40E_MEDIA_TYPE_FIBER;
841 case I40E_PHY_TYPE_100BASE_TX:
842 case I40E_PHY_TYPE_1000BASE_T:
843 case I40E_PHY_TYPE_10GBASE_T:
844 media = I40E_MEDIA_TYPE_BASET;
846 case I40E_PHY_TYPE_10GBASE_CR1_CU:
847 case I40E_PHY_TYPE_40GBASE_CR4_CU:
848 case I40E_PHY_TYPE_10GBASE_CR1:
849 case I40E_PHY_TYPE_40GBASE_CR4:
850 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
851 case I40E_PHY_TYPE_40GBASE_AOC:
852 case I40E_PHY_TYPE_10GBASE_AOC:
853 media = I40E_MEDIA_TYPE_DA;
855 case I40E_PHY_TYPE_1000BASE_KX:
856 case I40E_PHY_TYPE_10GBASE_KX4:
857 case I40E_PHY_TYPE_10GBASE_KR:
858 case I40E_PHY_TYPE_40GBASE_KR4:
859 case I40E_PHY_TYPE_20GBASE_KR2:
860 media = I40E_MEDIA_TYPE_BACKPLANE;
862 case I40E_PHY_TYPE_SGMII:
863 case I40E_PHY_TYPE_XAUI:
864 case I40E_PHY_TYPE_XFI:
865 case I40E_PHY_TYPE_XLAUI:
866 case I40E_PHY_TYPE_XLPPI:
868 media = I40E_MEDIA_TYPE_UNKNOWN;
875 #define I40E_PF_RESET_WAIT_COUNT 110
877 * i40e_pf_reset - Reset the PF
878 * @hw: pointer to the hardware structure
880 * Assuming someone else has triggered a global reset,
881 * assure the global reset is complete and then reset the PF
883 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
890 /* Poll for Global Reset steady state in case of recent GRST.
891 * The grst delay value is in 100ms units, and we'll wait a
892 * couple counts longer to be sure we don't just miss the end.
894 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
895 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
896 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
897 for (cnt = 0; cnt < grst_del + 2; cnt++) {
898 reg = rd32(hw, I40E_GLGEN_RSTAT);
899 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
901 i40e_msec_delay(100);
903 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
904 DEBUGOUT("Global reset polling failed to complete.\n");
905 return I40E_ERR_RESET_FAILED;
908 /* Now Wait for the FW to be ready */
909 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
910 reg = rd32(hw, I40E_GLNVM_ULD);
911 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
912 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
913 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
914 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
915 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
920 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
921 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
922 DEBUGOUT("wait for FW Reset complete timedout\n");
923 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
924 return I40E_ERR_RESET_FAILED;
927 /* If there was a Global Reset in progress when we got here,
928 * we don't need to do the PF Reset
931 reg = rd32(hw, I40E_PFGEN_CTRL);
932 wr32(hw, I40E_PFGEN_CTRL,
933 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
934 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
935 reg = rd32(hw, I40E_PFGEN_CTRL);
936 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
940 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
941 DEBUGOUT("PF reset polling failed to complete.\n");
942 return I40E_ERR_RESET_FAILED;
946 i40e_clear_pxe_mode(hw);
953 * i40e_clear_hw - clear out any left over hw state
954 * @hw: pointer to the hw struct
956 * Clear queues and interrupts, typically called at init time,
957 * but after the capabilities have been found so we know how many
958 * queues and msix vectors have been allocated.
960 void i40e_clear_hw(struct i40e_hw *hw)
962 u32 num_queues, base_queue;
970 /* get number of interrupts, queues, and vfs */
971 val = rd32(hw, I40E_GLPCI_CNF2);
972 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
973 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
974 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
975 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
977 val = rd32(hw, I40E_PFLAN_QALLOC);
978 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
979 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
980 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
981 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
982 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
983 num_queues = (j - base_queue) + 1;
987 val = rd32(hw, I40E_PF_VT_PFALLOC);
988 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
989 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
990 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
991 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
992 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
993 num_vfs = (j - i) + 1;
997 /* stop all the interrupts */
998 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
999 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1000 for (i = 0; i < num_pf_int - 2; i++)
1001 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1003 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1004 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1005 wr32(hw, I40E_PFINT_LNKLST0, val);
1006 for (i = 0; i < num_pf_int - 2; i++)
1007 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1008 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1009 for (i = 0; i < num_vfs; i++)
1010 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1011 for (i = 0; i < num_vf_int - 2; i++)
1012 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1014 /* warn the HW of the coming Tx disables */
1015 for (i = 0; i < num_queues; i++) {
1016 u32 abs_queue_idx = base_queue + i;
1019 if (abs_queue_idx >= 128) {
1020 reg_block = abs_queue_idx / 128;
1021 abs_queue_idx %= 128;
1024 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1025 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1026 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1027 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1029 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1031 i40e_usec_delay(400);
1033 /* stop all the queues */
1034 for (i = 0; i < num_queues; i++) {
1035 wr32(hw, I40E_QINT_TQCTL(i), 0);
1036 wr32(hw, I40E_QTX_ENA(i), 0);
1037 wr32(hw, I40E_QINT_RQCTL(i), 0);
1038 wr32(hw, I40E_QRX_ENA(i), 0);
1041 /* short wait for all queue disables to settle */
1042 i40e_usec_delay(50);
1046 * i40e_clear_pxe_mode - clear pxe operations mode
1047 * @hw: pointer to the hw struct
1049 * Make sure all PXE mode settings are cleared, including things
1050 * like descriptor fetch/write-back mode.
1052 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1054 if (i40e_check_asq_alive(hw))
1055 i40e_aq_clear_pxe_mode(hw, NULL);
1059 * i40e_led_is_mine - helper to find matching led
1060 * @hw: pointer to the hw struct
1061 * @idx: index into GPIO registers
1063 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1065 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1070 if (!hw->func_caps.led[idx])
1073 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1074 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1075 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1077 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1078 * if it is not our port then ignore
1080 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1087 #define I40E_COMBINED_ACTIVITY 0xA
1088 #define I40E_FILTER_ACTIVITY 0xE
1089 #define I40E_LINK_ACTIVITY 0xC
1090 #define I40E_MAC_ACTIVITY 0xD
1091 #define I40E_LED0 22
1094 * i40e_led_get - return current on/off mode
1095 * @hw: pointer to the hw struct
1097 * The value returned is the 'mode' field as defined in the
1098 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1099 * values are variations of possible behaviors relating to
1100 * blink, link, and wire.
1102 u32 i40e_led_get(struct i40e_hw *hw)
1104 u32 current_mode = 0;
1108 /* as per the documentation GPIO 22-29 are the LED
1109 * GPIO pins named LED0..LED7
1111 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1112 u32 gpio_val = i40e_led_is_mine(hw, i);
1117 /* ignore gpio LED src mode entries related to the activity LEDs */
1118 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1119 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1120 switch (current_mode) {
1121 case I40E_COMBINED_ACTIVITY:
1122 case I40E_FILTER_ACTIVITY:
1123 case I40E_MAC_ACTIVITY:
1129 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1130 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1138 * i40e_led_set - set new on/off mode
1139 * @hw: pointer to the hw struct
1140 * @mode: 0=off, 0xf=on (else see manual for mode details)
1141 * @blink: true if the LED should blink when on, false if steady
1143 * if this function is used to turn on the blink it should
1144 * be used to disable the blink when restoring the original state.
1146 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1148 u32 current_mode = 0;
1151 if (mode & 0xfffffff0)
1152 DEBUGOUT1("invalid mode passed in %X\n", mode);
1154 /* as per the documentation GPIO 22-29 are the LED
1155 * GPIO pins named LED0..LED7
1157 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1158 u32 gpio_val = i40e_led_is_mine(hw, i);
1163 /* ignore gpio LED src mode entries related to the activity LEDs */
1164 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1165 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1166 switch (current_mode) {
1167 case I40E_COMBINED_ACTIVITY:
1168 case I40E_FILTER_ACTIVITY:
1169 case I40E_MAC_ACTIVITY:
1175 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1176 /* this & is a bit of paranoia, but serves as a range check */
1177 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1178 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1180 if (mode == I40E_LINK_ACTIVITY)
1184 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1186 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1188 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1193 /* Admin command wrappers */
1196 * i40e_aq_get_phy_capabilities
1197 * @hw: pointer to the hw struct
1198 * @abilities: structure for PHY capabilities to be filled
1199 * @qualified_modules: report Qualified Modules
1200 * @report_init: report init capabilities (active are default)
1201 * @cmd_details: pointer to command details structure or NULL
1203 * Returns the various PHY abilities supported on the Port.
1205 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1206 bool qualified_modules, bool report_init,
1207 struct i40e_aq_get_phy_abilities_resp *abilities,
1208 struct i40e_asq_cmd_details *cmd_details)
1210 struct i40e_aq_desc desc;
1211 enum i40e_status_code status;
1212 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1215 return I40E_ERR_PARAM;
1217 i40e_fill_default_direct_cmd_desc(&desc,
1218 i40e_aqc_opc_get_phy_abilities);
1220 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1221 if (abilities_size > I40E_AQ_LARGE_BUF)
1222 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1224 if (qualified_modules)
1225 desc.params.external.param0 |=
1226 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1229 desc.params.external.param0 |=
1230 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1232 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1235 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1236 status = I40E_ERR_UNKNOWN_PHY;
1242 * i40e_aq_set_phy_config
1243 * @hw: pointer to the hw struct
1244 * @config: structure with PHY configuration to be set
1245 * @cmd_details: pointer to command details structure or NULL
1247 * Set the various PHY configuration parameters
1248 * supported on the Port.One or more of the Set PHY config parameters may be
1249 * ignored in an MFP mode as the PF may not have the privilege to set some
1250 * of the PHY Config parameters. This status will be indicated by the
1253 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1254 struct i40e_aq_set_phy_config *config,
1255 struct i40e_asq_cmd_details *cmd_details)
1257 struct i40e_aq_desc desc;
1258 struct i40e_aq_set_phy_config *cmd =
1259 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1260 enum i40e_status_code status;
1263 return I40E_ERR_PARAM;
1265 i40e_fill_default_direct_cmd_desc(&desc,
1266 i40e_aqc_opc_set_phy_config);
1270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1277 * @hw: pointer to the hw struct
1279 * Set the requested flow control mode using set_phy_config.
1281 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1282 bool atomic_restart)
1284 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1285 struct i40e_aq_get_phy_abilities_resp abilities;
1286 struct i40e_aq_set_phy_config config;
1287 enum i40e_status_code status;
1288 u8 pause_mask = 0x0;
1294 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1295 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1297 case I40E_FC_RX_PAUSE:
1298 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1300 case I40E_FC_TX_PAUSE:
1301 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1307 /* Get the current phy config */
1308 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1311 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1315 memset(&config, 0, sizeof(config));
1316 /* clear the old pause settings */
1317 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1318 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1319 /* set the new abilities */
1320 config.abilities |= pause_mask;
1321 /* If the abilities have changed, then set the new config */
1322 if (config.abilities != abilities.abilities) {
1323 /* Auto restart link so settings take effect */
1325 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1326 /* Copy over all the old settings */
1327 config.phy_type = abilities.phy_type;
1328 config.link_speed = abilities.link_speed;
1329 config.eee_capability = abilities.eee_capability;
1330 config.eeer = abilities.eeer_val;
1331 config.low_power_ctrl = abilities.d3_lpan;
1332 status = i40e_aq_set_phy_config(hw, &config, NULL);
1335 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1337 /* Update the link info */
1338 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1340 /* Wait a little bit (on 40G cards it sometimes takes a really
1341 * long time for link to come back from the atomic reset)
1344 i40e_msec_delay(1000);
1345 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1348 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1354 * i40e_aq_set_mac_config
1355 * @hw: pointer to the hw struct
1356 * @max_frame_size: Maximum Frame Size to be supported by the port
1357 * @crc_en: Tell HW to append a CRC to outgoing frames
1358 * @pacing: Pacing configurations
1359 * @cmd_details: pointer to command details structure or NULL
1361 * Configure MAC settings for frame size, jumbo frame support and the
1362 * addition of a CRC by the hardware.
1364 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1366 bool crc_en, u16 pacing,
1367 struct i40e_asq_cmd_details *cmd_details)
1369 struct i40e_aq_desc desc;
1370 struct i40e_aq_set_mac_config *cmd =
1371 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1372 enum i40e_status_code status;
1374 if (max_frame_size == 0)
1375 return I40E_ERR_PARAM;
1377 i40e_fill_default_direct_cmd_desc(&desc,
1378 i40e_aqc_opc_set_mac_config);
1380 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1381 cmd->params = ((u8)pacing & 0x0F) << 3;
1383 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1391 * i40e_aq_clear_pxe_mode
1392 * @hw: pointer to the hw struct
1393 * @cmd_details: pointer to command details structure or NULL
1395 * Tell the firmware that the driver is taking over from PXE
1397 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1398 struct i40e_asq_cmd_details *cmd_details)
1400 enum i40e_status_code status;
1401 struct i40e_aq_desc desc;
1402 struct i40e_aqc_clear_pxe *cmd =
1403 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1405 i40e_fill_default_direct_cmd_desc(&desc,
1406 i40e_aqc_opc_clear_pxe_mode);
1410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1412 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1418 * i40e_aq_set_link_restart_an
1419 * @hw: pointer to the hw struct
1420 * @enable_link: if true: enable link, if false: disable link
1421 * @cmd_details: pointer to command details structure or NULL
1423 * Sets up the link and restarts the Auto-Negotiation over the link.
1425 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1426 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1428 struct i40e_aq_desc desc;
1429 struct i40e_aqc_set_link_restart_an *cmd =
1430 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1431 enum i40e_status_code status;
1433 i40e_fill_default_direct_cmd_desc(&desc,
1434 i40e_aqc_opc_set_link_restart_an);
1436 cmd->command = I40E_AQ_PHY_RESTART_AN;
1438 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1440 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1442 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1448 * i40e_aq_get_link_info
1449 * @hw: pointer to the hw struct
1450 * @enable_lse: enable/disable LinkStatusEvent reporting
1451 * @link: pointer to link status structure - optional
1452 * @cmd_details: pointer to command details structure or NULL
1454 * Returns the link status of the adapter.
1456 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1457 bool enable_lse, struct i40e_link_status *link,
1458 struct i40e_asq_cmd_details *cmd_details)
1460 struct i40e_aq_desc desc;
1461 struct i40e_aqc_get_link_status *resp =
1462 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1463 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1464 enum i40e_status_code status;
1465 bool tx_pause, rx_pause;
1468 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1471 command_flags = I40E_AQ_LSE_ENABLE;
1473 command_flags = I40E_AQ_LSE_DISABLE;
1474 resp->command_flags = CPU_TO_LE16(command_flags);
1476 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1478 if (status != I40E_SUCCESS)
1479 goto aq_get_link_info_exit;
1481 /* save off old link status information */
1482 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1483 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1485 /* update link status */
1486 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1487 hw->phy.media_type = i40e_get_media_type(hw);
1488 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1489 hw_link_info->link_info = resp->link_info;
1490 hw_link_info->an_info = resp->an_info;
1491 hw_link_info->ext_info = resp->ext_info;
1492 hw_link_info->loopback = resp->loopback;
1493 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1494 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1496 /* update fc info */
1497 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1498 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1499 if (tx_pause & rx_pause)
1500 hw->fc.current_mode = I40E_FC_FULL;
1502 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1504 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1506 hw->fc.current_mode = I40E_FC_NONE;
1508 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1509 hw_link_info->crc_enable = true;
1511 hw_link_info->crc_enable = false;
1513 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1514 hw_link_info->lse_enable = true;
1516 hw_link_info->lse_enable = false;
1518 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1519 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1520 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1522 /* save link status information */
1524 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1525 I40E_NONDMA_TO_NONDMA);
1527 /* flag cleared so helper functions don't call AQ again */
1528 hw->phy.get_link_info = false;
1530 aq_get_link_info_exit:
1536 * i40e_aq_set_phy_int_mask
1537 * @hw: pointer to the hw struct
1538 * @mask: interrupt mask to be set
1539 * @cmd_details: pointer to command details structure or NULL
1541 * Set link interrupt mask.
1543 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1545 struct i40e_asq_cmd_details *cmd_details)
1547 struct i40e_aq_desc desc;
1548 struct i40e_aqc_set_phy_int_mask *cmd =
1549 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1550 enum i40e_status_code status;
1552 i40e_fill_default_direct_cmd_desc(&desc,
1553 i40e_aqc_opc_set_phy_int_mask);
1555 cmd->event_mask = CPU_TO_LE16(mask);
1557 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1563 * i40e_aq_get_local_advt_reg
1564 * @hw: pointer to the hw struct
1565 * @advt_reg: local AN advertisement register value
1566 * @cmd_details: pointer to command details structure or NULL
1568 * Get the Local AN advertisement register value.
1570 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1572 struct i40e_asq_cmd_details *cmd_details)
1574 struct i40e_aq_desc desc;
1575 struct i40e_aqc_an_advt_reg *resp =
1576 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1577 enum i40e_status_code status;
1579 i40e_fill_default_direct_cmd_desc(&desc,
1580 i40e_aqc_opc_get_local_advt_reg);
1582 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1584 if (status != I40E_SUCCESS)
1585 goto aq_get_local_advt_reg_exit;
1587 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1588 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1590 aq_get_local_advt_reg_exit:
1595 * i40e_aq_set_local_advt_reg
1596 * @hw: pointer to the hw struct
1597 * @advt_reg: local AN advertisement register value
1598 * @cmd_details: pointer to command details structure or NULL
1600 * Get the Local AN advertisement register value.
1602 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1604 struct i40e_asq_cmd_details *cmd_details)
1606 struct i40e_aq_desc desc;
1607 struct i40e_aqc_an_advt_reg *cmd =
1608 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1609 enum i40e_status_code status;
1611 i40e_fill_default_direct_cmd_desc(&desc,
1612 i40e_aqc_opc_get_local_advt_reg);
1614 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1615 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1617 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1623 * i40e_aq_get_partner_advt
1624 * @hw: pointer to the hw struct
1625 * @advt_reg: AN partner advertisement register value
1626 * @cmd_details: pointer to command details structure or NULL
1628 * Get the link partner AN advertisement register value.
1630 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1632 struct i40e_asq_cmd_details *cmd_details)
1634 struct i40e_aq_desc desc;
1635 struct i40e_aqc_an_advt_reg *resp =
1636 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1637 enum i40e_status_code status;
1639 i40e_fill_default_direct_cmd_desc(&desc,
1640 i40e_aqc_opc_get_partner_advt);
1642 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1644 if (status != I40E_SUCCESS)
1645 goto aq_get_partner_advt_exit;
1647 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1648 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1650 aq_get_partner_advt_exit:
1655 * i40e_aq_set_lb_modes
1656 * @hw: pointer to the hw struct
1657 * @lb_modes: loopback mode to be set
1658 * @cmd_details: pointer to command details structure or NULL
1660 * Sets loopback modes.
1662 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1664 struct i40e_asq_cmd_details *cmd_details)
1666 struct i40e_aq_desc desc;
1667 struct i40e_aqc_set_lb_mode *cmd =
1668 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1669 enum i40e_status_code status;
1671 i40e_fill_default_direct_cmd_desc(&desc,
1672 i40e_aqc_opc_set_lb_modes);
1674 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1682 * i40e_aq_set_phy_debug
1683 * @hw: pointer to the hw struct
1684 * @cmd_flags: debug command flags
1685 * @cmd_details: pointer to command details structure or NULL
1687 * Reset the external PHY.
1689 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1690 struct i40e_asq_cmd_details *cmd_details)
1692 struct i40e_aq_desc desc;
1693 struct i40e_aqc_set_phy_debug *cmd =
1694 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1695 enum i40e_status_code status;
1697 i40e_fill_default_direct_cmd_desc(&desc,
1698 i40e_aqc_opc_set_phy_debug);
1700 cmd->command_flags = cmd_flags;
1702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1709 * @hw: pointer to the hw struct
1710 * @vsi_ctx: pointer to a vsi context struct
1711 * @cmd_details: pointer to command details structure or NULL
1713 * Add a VSI context to the hardware.
1715 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1716 struct i40e_vsi_context *vsi_ctx,
1717 struct i40e_asq_cmd_details *cmd_details)
1719 struct i40e_aq_desc desc;
1720 struct i40e_aqc_add_get_update_vsi *cmd =
1721 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1722 struct i40e_aqc_add_get_update_vsi_completion *resp =
1723 (struct i40e_aqc_add_get_update_vsi_completion *)
1725 enum i40e_status_code status;
1727 i40e_fill_default_direct_cmd_desc(&desc,
1728 i40e_aqc_opc_add_vsi);
1730 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1731 cmd->connection_type = vsi_ctx->connection_type;
1732 cmd->vf_id = vsi_ctx->vf_num;
1733 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1735 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1737 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1738 sizeof(vsi_ctx->info), cmd_details);
1740 if (status != I40E_SUCCESS)
1741 goto aq_add_vsi_exit;
1743 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1744 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1745 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1746 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1753 * i40e_aq_set_default_vsi
1754 * @hw: pointer to the hw struct
1756 * @cmd_details: pointer to command details structure or NULL
1758 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1760 struct i40e_asq_cmd_details *cmd_details)
1762 struct i40e_aq_desc desc;
1763 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1764 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1766 enum i40e_status_code status;
1768 i40e_fill_default_direct_cmd_desc(&desc,
1769 i40e_aqc_opc_set_vsi_promiscuous_modes);
1771 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1772 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1773 cmd->seid = CPU_TO_LE16(seid);
1775 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1781 * i40e_aq_set_vsi_unicast_promiscuous
1782 * @hw: pointer to the hw struct
1784 * @set: set unicast promiscuous enable/disable
1785 * @cmd_details: pointer to command details structure or NULL
1787 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1789 struct i40e_asq_cmd_details *cmd_details)
1791 struct i40e_aq_desc desc;
1792 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1793 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1794 enum i40e_status_code status;
1797 i40e_fill_default_direct_cmd_desc(&desc,
1798 i40e_aqc_opc_set_vsi_promiscuous_modes);
1801 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1803 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1805 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1807 cmd->seid = CPU_TO_LE16(seid);
1808 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1814 * i40e_aq_set_vsi_multicast_promiscuous
1815 * @hw: pointer to the hw struct
1817 * @set: set multicast promiscuous enable/disable
1818 * @cmd_details: pointer to command details structure or NULL
1820 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1821 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1823 struct i40e_aq_desc desc;
1824 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1825 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1826 enum i40e_status_code status;
1829 i40e_fill_default_direct_cmd_desc(&desc,
1830 i40e_aqc_opc_set_vsi_promiscuous_modes);
1833 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1835 cmd->promiscuous_flags = CPU_TO_LE16(flags);
1837 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1839 cmd->seid = CPU_TO_LE16(seid);
1840 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1846 * i40e_aq_set_vsi_broadcast
1847 * @hw: pointer to the hw struct
1849 * @set_filter: true to set filter, false to clear filter
1850 * @cmd_details: pointer to command details structure or NULL
1852 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1854 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1855 u16 seid, bool set_filter,
1856 struct i40e_asq_cmd_details *cmd_details)
1858 struct i40e_aq_desc desc;
1859 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1860 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1861 enum i40e_status_code status;
1863 i40e_fill_default_direct_cmd_desc(&desc,
1864 i40e_aqc_opc_set_vsi_promiscuous_modes);
1867 cmd->promiscuous_flags
1868 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1870 cmd->promiscuous_flags
1871 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1873 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1874 cmd->seid = CPU_TO_LE16(seid);
1875 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1881 * i40e_get_vsi_params - get VSI configuration info
1882 * @hw: pointer to the hw struct
1883 * @vsi_ctx: pointer to a vsi context struct
1884 * @cmd_details: pointer to command details structure or NULL
1886 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
1887 struct i40e_vsi_context *vsi_ctx,
1888 struct i40e_asq_cmd_details *cmd_details)
1890 struct i40e_aq_desc desc;
1891 struct i40e_aqc_add_get_update_vsi *cmd =
1892 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1893 struct i40e_aqc_add_get_update_vsi_completion *resp =
1894 (struct i40e_aqc_add_get_update_vsi_completion *)
1896 enum i40e_status_code status;
1898 UNREFERENCED_1PARAMETER(cmd_details);
1899 i40e_fill_default_direct_cmd_desc(&desc,
1900 i40e_aqc_opc_get_vsi_parameters);
1902 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1904 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1906 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1907 sizeof(vsi_ctx->info), NULL);
1909 if (status != I40E_SUCCESS)
1910 goto aq_get_vsi_params_exit;
1912 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1913 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1914 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1915 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1917 aq_get_vsi_params_exit:
1922 * i40e_aq_update_vsi_params
1923 * @hw: pointer to the hw struct
1924 * @vsi_ctx: pointer to a vsi context struct
1925 * @cmd_details: pointer to command details structure or NULL
1927 * Update a VSI context.
1929 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
1930 struct i40e_vsi_context *vsi_ctx,
1931 struct i40e_asq_cmd_details *cmd_details)
1933 struct i40e_aq_desc desc;
1934 struct i40e_aqc_add_get_update_vsi *cmd =
1935 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1936 enum i40e_status_code status;
1938 i40e_fill_default_direct_cmd_desc(&desc,
1939 i40e_aqc_opc_update_vsi_parameters);
1940 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
1942 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1944 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1945 sizeof(vsi_ctx->info), cmd_details);
1951 * i40e_aq_get_switch_config
1952 * @hw: pointer to the hardware structure
1953 * @buf: pointer to the result buffer
1954 * @buf_size: length of input buffer
1955 * @start_seid: seid to start for the report, 0 == beginning
1956 * @cmd_details: pointer to command details structure or NULL
1958 * Fill the buf with switch configuration returned from AdminQ command
1960 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
1961 struct i40e_aqc_get_switch_config_resp *buf,
1962 u16 buf_size, u16 *start_seid,
1963 struct i40e_asq_cmd_details *cmd_details)
1965 struct i40e_aq_desc desc;
1966 struct i40e_aqc_switch_seid *scfg =
1967 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1968 enum i40e_status_code status;
1970 i40e_fill_default_direct_cmd_desc(&desc,
1971 i40e_aqc_opc_get_switch_config);
1972 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1973 if (buf_size > I40E_AQ_LARGE_BUF)
1974 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1975 scfg->seid = CPU_TO_LE16(*start_seid);
1977 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1978 *start_seid = LE16_TO_CPU(scfg->seid);
1984 * i40e_aq_get_firmware_version
1985 * @hw: pointer to the hw struct
1986 * @fw_major_version: firmware major version
1987 * @fw_minor_version: firmware minor version
1988 * @fw_build: firmware build number
1989 * @api_major_version: major queue version
1990 * @api_minor_version: minor queue version
1991 * @cmd_details: pointer to command details structure or NULL
1993 * Get the firmware version from the admin queue commands
1995 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
1996 u16 *fw_major_version, u16 *fw_minor_version,
1998 u16 *api_major_version, u16 *api_minor_version,
1999 struct i40e_asq_cmd_details *cmd_details)
2001 struct i40e_aq_desc desc;
2002 struct i40e_aqc_get_version *resp =
2003 (struct i40e_aqc_get_version *)&desc.params.raw;
2004 enum i40e_status_code status;
2006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2010 if (status == I40E_SUCCESS) {
2011 if (fw_major_version != NULL)
2012 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2013 if (fw_minor_version != NULL)
2014 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2015 if (fw_build != NULL)
2016 *fw_build = LE32_TO_CPU(resp->fw_build);
2017 if (api_major_version != NULL)
2018 *api_major_version = LE16_TO_CPU(resp->api_major);
2019 if (api_minor_version != NULL)
2020 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2022 /* A workaround to fix the API version in SW */
2023 if (api_major_version && api_minor_version &&
2024 fw_major_version && fw_minor_version &&
2025 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2026 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2027 (*fw_major_version > 4)))
2028 *api_minor_version = 2;
2035 * i40e_aq_send_driver_version
2036 * @hw: pointer to the hw struct
2037 * @dv: driver's major, minor version
2038 * @cmd_details: pointer to command details structure or NULL
2040 * Send the driver version to the firmware
2042 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2043 struct i40e_driver_version *dv,
2044 struct i40e_asq_cmd_details *cmd_details)
2046 struct i40e_aq_desc desc;
2047 struct i40e_aqc_driver_version *cmd =
2048 (struct i40e_aqc_driver_version *)&desc.params.raw;
2049 enum i40e_status_code status;
2053 return I40E_ERR_PARAM;
2055 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2057 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2058 cmd->driver_major_ver = dv->major_version;
2059 cmd->driver_minor_ver = dv->minor_version;
2060 cmd->driver_build_ver = dv->build_version;
2061 cmd->driver_subbuild_ver = dv->subbuild_version;
2064 while (len < sizeof(dv->driver_string) &&
2065 (dv->driver_string[len] < 0x80) &&
2066 dv->driver_string[len])
2068 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2075 * i40e_get_link_status - get status of the HW network link
2076 * @hw: pointer to the hw struct
2078 * Returns true if link is up, false if link is down.
2080 * Side effect: LinkStatusEvent reporting becomes enabled
2082 bool i40e_get_link_status(struct i40e_hw *hw)
2084 enum i40e_status_code status = I40E_SUCCESS;
2085 bool link_status = false;
2087 if (hw->phy.get_link_info) {
2088 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2090 if (status != I40E_SUCCESS)
2091 goto i40e_get_link_status_exit;
2094 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2096 i40e_get_link_status_exit:
2101 * i40e_get_link_speed
2102 * @hw: pointer to the hw struct
2104 * Returns the link speed of the adapter.
2106 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2108 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2109 enum i40e_status_code status = I40E_SUCCESS;
2111 if (hw->phy.get_link_info) {
2112 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2114 if (status != I40E_SUCCESS)
2115 goto i40e_link_speed_exit;
2118 speed = hw->phy.link_info.link_speed;
2120 i40e_link_speed_exit:
2125 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2126 * @hw: pointer to the hw struct
2127 * @uplink_seid: the MAC or other gizmo SEID
2128 * @downlink_seid: the VSI SEID
2129 * @enabled_tc: bitmap of TCs to be enabled
2130 * @default_port: true for default port VSI, false for control port
2131 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2132 * @veb_seid: pointer to where to put the resulting VEB SEID
2133 * @cmd_details: pointer to command details structure or NULL
2135 * This asks the FW to add a VEB between the uplink and downlink
2136 * elements. If the uplink SEID is 0, this will be a floating VEB.
2138 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2139 u16 downlink_seid, u8 enabled_tc,
2140 bool default_port, bool enable_l2_filtering,
2142 struct i40e_asq_cmd_details *cmd_details)
2144 struct i40e_aq_desc desc;
2145 struct i40e_aqc_add_veb *cmd =
2146 (struct i40e_aqc_add_veb *)&desc.params.raw;
2147 struct i40e_aqc_add_veb_completion *resp =
2148 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2149 enum i40e_status_code status;
2152 /* SEIDs need to either both be set or both be 0 for floating VEB */
2153 if (!!uplink_seid != !!downlink_seid)
2154 return I40E_ERR_PARAM;
2156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2158 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2159 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2160 cmd->enable_tcs = enabled_tc;
2162 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2164 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2166 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2168 if (enable_l2_filtering)
2169 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2171 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2173 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2175 if (!status && veb_seid)
2176 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2182 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2183 * @hw: pointer to the hw struct
2184 * @veb_seid: the SEID of the VEB to query
2185 * @switch_id: the uplink switch id
2186 * @floating: set to true if the VEB is floating
2187 * @statistic_index: index of the stats counter block for this VEB
2188 * @vebs_used: number of VEB's used by function
2189 * @vebs_free: total VEB's not reserved by any function
2190 * @cmd_details: pointer to command details structure or NULL
2192 * This retrieves the parameters for a particular VEB, specified by
2193 * uplink_seid, and returns them to the caller.
2195 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2196 u16 veb_seid, u16 *switch_id,
2197 bool *floating, u16 *statistic_index,
2198 u16 *vebs_used, u16 *vebs_free,
2199 struct i40e_asq_cmd_details *cmd_details)
2201 struct i40e_aq_desc desc;
2202 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2203 (struct i40e_aqc_get_veb_parameters_completion *)
2205 enum i40e_status_code status;
2208 return I40E_ERR_PARAM;
2210 i40e_fill_default_direct_cmd_desc(&desc,
2211 i40e_aqc_opc_get_veb_parameters);
2212 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2214 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2219 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2220 if (statistic_index)
2221 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2223 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2225 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2227 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2228 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2239 * i40e_aq_add_macvlan
2240 * @hw: pointer to the hw struct
2241 * @seid: VSI for the mac address
2242 * @mv_list: list of macvlans to be added
2243 * @count: length of the list
2244 * @cmd_details: pointer to command details structure or NULL
2246 * Add MAC/VLAN addresses to the HW filtering
2248 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2249 struct i40e_aqc_add_macvlan_element_data *mv_list,
2250 u16 count, struct i40e_asq_cmd_details *cmd_details)
2252 struct i40e_aq_desc desc;
2253 struct i40e_aqc_macvlan *cmd =
2254 (struct i40e_aqc_macvlan *)&desc.params.raw;
2255 enum i40e_status_code status;
2258 if (count == 0 || !mv_list || !hw)
2259 return I40E_ERR_PARAM;
2261 buf_size = count * sizeof(*mv_list);
2263 /* prep the rest of the request */
2264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2265 cmd->num_addresses = CPU_TO_LE16(count);
2266 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2270 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2271 if (buf_size > I40E_AQ_LARGE_BUF)
2272 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2274 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2281 * i40e_aq_remove_macvlan
2282 * @hw: pointer to the hw struct
2283 * @seid: VSI for the mac address
2284 * @mv_list: list of macvlans to be removed
2285 * @count: length of the list
2286 * @cmd_details: pointer to command details structure or NULL
2288 * Remove MAC/VLAN addresses from the HW filtering
2290 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2291 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2292 u16 count, struct i40e_asq_cmd_details *cmd_details)
2294 struct i40e_aq_desc desc;
2295 struct i40e_aqc_macvlan *cmd =
2296 (struct i40e_aqc_macvlan *)&desc.params.raw;
2297 enum i40e_status_code status;
2300 if (count == 0 || !mv_list || !hw)
2301 return I40E_ERR_PARAM;
2303 buf_size = count * sizeof(*mv_list);
2305 /* prep the rest of the request */
2306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2307 cmd->num_addresses = CPU_TO_LE16(count);
2308 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2312 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2313 if (buf_size > I40E_AQ_LARGE_BUF)
2314 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2316 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2323 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2324 * @hw: pointer to the hw struct
2325 * @seid: VSI for the vlan filters
2326 * @v_list: list of vlan filters to be added
2327 * @count: length of the list
2328 * @cmd_details: pointer to command details structure or NULL
2330 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2331 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2332 u8 count, struct i40e_asq_cmd_details *cmd_details)
2334 struct i40e_aq_desc desc;
2335 struct i40e_aqc_macvlan *cmd =
2336 (struct i40e_aqc_macvlan *)&desc.params.raw;
2337 enum i40e_status_code status;
2340 if (count == 0 || !v_list || !hw)
2341 return I40E_ERR_PARAM;
2343 buf_size = count * sizeof(*v_list);
2345 /* prep the rest of the request */
2346 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2347 cmd->num_addresses = CPU_TO_LE16(count);
2348 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2352 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2353 if (buf_size > I40E_AQ_LARGE_BUF)
2354 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2356 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2363 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2364 * @hw: pointer to the hw struct
2365 * @seid: VSI for the vlan filters
2366 * @v_list: list of macvlans to be removed
2367 * @count: length of the list
2368 * @cmd_details: pointer to command details structure or NULL
2370 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2371 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2372 u8 count, struct i40e_asq_cmd_details *cmd_details)
2374 struct i40e_aq_desc desc;
2375 struct i40e_aqc_macvlan *cmd =
2376 (struct i40e_aqc_macvlan *)&desc.params.raw;
2377 enum i40e_status_code status;
2380 if (count == 0 || !v_list || !hw)
2381 return I40E_ERR_PARAM;
2383 buf_size = count * sizeof(*v_list);
2385 /* prep the rest of the request */
2386 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2387 cmd->num_addresses = CPU_TO_LE16(count);
2388 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2392 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2393 if (buf_size > I40E_AQ_LARGE_BUF)
2394 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2396 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2403 * i40e_aq_send_msg_to_vf
2404 * @hw: pointer to the hardware structure
2405 * @vfid: vf id to send msg
2406 * @v_opcode: opcodes for VF-PF communication
2407 * @v_retval: return error code
2408 * @msg: pointer to the msg buffer
2409 * @msglen: msg length
2410 * @cmd_details: pointer to command details
2414 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2415 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2416 struct i40e_asq_cmd_details *cmd_details)
2418 struct i40e_aq_desc desc;
2419 struct i40e_aqc_pf_vf_message *cmd =
2420 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2421 enum i40e_status_code status;
2423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2424 cmd->id = CPU_TO_LE32(vfid);
2425 desc.cookie_high = CPU_TO_LE32(v_opcode);
2426 desc.cookie_low = CPU_TO_LE32(v_retval);
2427 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2429 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2431 if (msglen > I40E_AQ_LARGE_BUF)
2432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2433 desc.datalen = CPU_TO_LE16(msglen);
2435 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2441 * i40e_aq_debug_read_register
2442 * @hw: pointer to the hw struct
2443 * @reg_addr: register address
2444 * @reg_val: register value
2445 * @cmd_details: pointer to command details structure or NULL
2447 * Read the register using the admin queue commands
2449 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2450 u32 reg_addr, u64 *reg_val,
2451 struct i40e_asq_cmd_details *cmd_details)
2453 struct i40e_aq_desc desc;
2454 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2455 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2456 enum i40e_status_code status;
2458 if (reg_val == NULL)
2459 return I40E_ERR_PARAM;
2461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2463 cmd_resp->address = CPU_TO_LE32(reg_addr);
2465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2467 if (status == I40E_SUCCESS) {
2468 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2469 (u64)LE32_TO_CPU(cmd_resp->value_low);
2476 * i40e_aq_debug_write_register
2477 * @hw: pointer to the hw struct
2478 * @reg_addr: register address
2479 * @reg_val: register value
2480 * @cmd_details: pointer to command details structure or NULL
2482 * Write to a register using the admin queue commands
2484 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2485 u32 reg_addr, u64 reg_val,
2486 struct i40e_asq_cmd_details *cmd_details)
2488 struct i40e_aq_desc desc;
2489 struct i40e_aqc_debug_reg_read_write *cmd =
2490 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2491 enum i40e_status_code status;
2493 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2495 cmd->address = CPU_TO_LE32(reg_addr);
2496 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2497 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2499 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2505 * i40e_aq_get_hmc_resource_profile
2506 * @hw: pointer to the hw struct
2507 * @profile: type of profile the HMC is to be set as
2508 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2509 * @cmd_details: pointer to command details structure or NULL
2511 * query the HMC profile of the device.
2513 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2514 enum i40e_aq_hmc_profile *profile,
2515 u8 *pe_vf_enabled_count,
2516 struct i40e_asq_cmd_details *cmd_details)
2518 struct i40e_aq_desc desc;
2519 struct i40e_aq_get_set_hmc_resource_profile *resp =
2520 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2521 enum i40e_status_code status;
2523 i40e_fill_default_direct_cmd_desc(&desc,
2524 i40e_aqc_opc_query_hmc_resource_profile);
2525 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2527 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2528 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2529 *pe_vf_enabled_count = resp->pe_vf_enabled &
2530 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2536 * i40e_aq_set_hmc_resource_profile
2537 * @hw: pointer to the hw struct
2538 * @profile: type of profile the HMC is to be set as
2539 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2540 * @cmd_details: pointer to command details structure or NULL
2542 * set the HMC profile of the device.
2544 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2545 enum i40e_aq_hmc_profile profile,
2546 u8 pe_vf_enabled_count,
2547 struct i40e_asq_cmd_details *cmd_details)
2549 struct i40e_aq_desc desc;
2550 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2551 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2552 enum i40e_status_code status;
2554 i40e_fill_default_direct_cmd_desc(&desc,
2555 i40e_aqc_opc_set_hmc_resource_profile);
2557 cmd->pm_profile = (u8)profile;
2558 cmd->pe_vf_enabled = pe_vf_enabled_count;
2560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2566 * i40e_aq_request_resource
2567 * @hw: pointer to the hw struct
2568 * @resource: resource id
2569 * @access: access type
2570 * @sdp_number: resource number
2571 * @timeout: the maximum time in ms that the driver may hold the resource
2572 * @cmd_details: pointer to command details structure or NULL
2574 * requests common resource using the admin queue commands
2576 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2577 enum i40e_aq_resources_ids resource,
2578 enum i40e_aq_resource_access_type access,
2579 u8 sdp_number, u64 *timeout,
2580 struct i40e_asq_cmd_details *cmd_details)
2582 struct i40e_aq_desc desc;
2583 struct i40e_aqc_request_resource *cmd_resp =
2584 (struct i40e_aqc_request_resource *)&desc.params.raw;
2585 enum i40e_status_code status;
2587 DEBUGFUNC("i40e_aq_request_resource");
2589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2591 cmd_resp->resource_id = CPU_TO_LE16(resource);
2592 cmd_resp->access_type = CPU_TO_LE16(access);
2593 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2595 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2596 /* The completion specifies the maximum time in ms that the driver
2597 * may hold the resource in the Timeout field.
2598 * If the resource is held by someone else, the command completes with
2599 * busy return value and the timeout field indicates the maximum time
2600 * the current owner of the resource has to free it.
2602 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2603 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2609 * i40e_aq_release_resource
2610 * @hw: pointer to the hw struct
2611 * @resource: resource id
2612 * @sdp_number: resource number
2613 * @cmd_details: pointer to command details structure or NULL
2615 * release common resource using the admin queue commands
2617 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2618 enum i40e_aq_resources_ids resource,
2620 struct i40e_asq_cmd_details *cmd_details)
2622 struct i40e_aq_desc desc;
2623 struct i40e_aqc_request_resource *cmd =
2624 (struct i40e_aqc_request_resource *)&desc.params.raw;
2625 enum i40e_status_code status;
2627 DEBUGFUNC("i40e_aq_release_resource");
2629 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2631 cmd->resource_id = CPU_TO_LE16(resource);
2632 cmd->resource_number = CPU_TO_LE32(sdp_number);
2634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2641 * @hw: pointer to the hw struct
2642 * @module_pointer: module pointer location in words from the NVM beginning
2643 * @offset: byte offset from the module beginning
2644 * @length: length of the section to be read (in bytes from the offset)
2645 * @data: command buffer (size [bytes] = length)
2646 * @last_command: tells if this is the last command in a series
2647 * @cmd_details: pointer to command details structure or NULL
2649 * Read the NVM using the admin queue commands
2651 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2652 u32 offset, u16 length, void *data,
2654 struct i40e_asq_cmd_details *cmd_details)
2656 struct i40e_aq_desc desc;
2657 struct i40e_aqc_nvm_update *cmd =
2658 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2659 enum i40e_status_code status;
2661 DEBUGFUNC("i40e_aq_read_nvm");
2663 /* In offset the highest byte must be zeroed. */
2664 if (offset & 0xFF000000) {
2665 status = I40E_ERR_PARAM;
2666 goto i40e_aq_read_nvm_exit;
2669 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2671 /* If this is the last command in a series, set the proper flag. */
2673 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2674 cmd->module_pointer = module_pointer;
2675 cmd->offset = CPU_TO_LE32(offset);
2676 cmd->length = CPU_TO_LE16(length);
2678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2679 if (length > I40E_AQ_LARGE_BUF)
2680 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2682 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2684 i40e_aq_read_nvm_exit:
2689 * i40e_aq_read_nvm_config - read an nvm config block
2690 * @hw: pointer to the hw struct
2691 * @cmd_flags: NVM access admin command bits
2692 * @field_id: field or feature id
2693 * @data: buffer for result
2694 * @buf_size: buffer size
2695 * @element_count: pointer to count of elements read by FW
2696 * @cmd_details: pointer to command details structure or NULL
2698 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2699 u8 cmd_flags, u32 field_id, void *data,
2700 u16 buf_size, u16 *element_count,
2701 struct i40e_asq_cmd_details *cmd_details)
2703 struct i40e_aq_desc desc;
2704 struct i40e_aqc_nvm_config_read *cmd =
2705 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2706 enum i40e_status_code status;
2708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2709 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2710 if (buf_size > I40E_AQ_LARGE_BUF)
2711 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2713 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2714 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2715 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2716 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2718 cmd->element_id_msw = 0;
2720 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2722 if (!status && element_count)
2723 *element_count = LE16_TO_CPU(cmd->element_count);
2729 * i40e_aq_write_nvm_config - write an nvm config block
2730 * @hw: pointer to the hw struct
2731 * @cmd_flags: NVM access admin command bits
2732 * @data: buffer for result
2733 * @buf_size: buffer size
2734 * @element_count: count of elements to be written
2735 * @cmd_details: pointer to command details structure or NULL
2737 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2738 u8 cmd_flags, void *data, u16 buf_size,
2740 struct i40e_asq_cmd_details *cmd_details)
2742 struct i40e_aq_desc desc;
2743 struct i40e_aqc_nvm_config_write *cmd =
2744 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2745 enum i40e_status_code status;
2747 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2748 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2749 if (buf_size > I40E_AQ_LARGE_BUF)
2750 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2752 cmd->element_count = CPU_TO_LE16(element_count);
2753 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2754 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2761 * @hw: pointer to the hw struct
2762 * @module_pointer: module pointer location in words from the NVM beginning
2763 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2764 * @length: length of the section to be erased (expressed in 4 KB)
2765 * @last_command: tells if this is the last command in a series
2766 * @cmd_details: pointer to command details structure or NULL
2768 * Erase the NVM sector using the admin queue commands
2770 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2771 u32 offset, u16 length, bool last_command,
2772 struct i40e_asq_cmd_details *cmd_details)
2774 struct i40e_aq_desc desc;
2775 struct i40e_aqc_nvm_update *cmd =
2776 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2777 enum i40e_status_code status;
2779 DEBUGFUNC("i40e_aq_erase_nvm");
2781 /* In offset the highest byte must be zeroed. */
2782 if (offset & 0xFF000000) {
2783 status = I40E_ERR_PARAM;
2784 goto i40e_aq_erase_nvm_exit;
2787 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2789 /* If this is the last command in a series, set the proper flag. */
2791 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2792 cmd->module_pointer = module_pointer;
2793 cmd->offset = CPU_TO_LE32(offset);
2794 cmd->length = CPU_TO_LE16(length);
2796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2798 i40e_aq_erase_nvm_exit:
2802 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2803 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2804 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2805 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2806 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2807 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2808 #define I40E_DEV_FUNC_CAP_VF 0x13
2809 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2810 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2811 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2812 #define I40E_DEV_FUNC_CAP_VSI 0x17
2813 #define I40E_DEV_FUNC_CAP_DCB 0x18
2814 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2815 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
2816 #define I40E_DEV_FUNC_CAP_RSS 0x40
2817 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2818 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2819 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2820 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2821 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2822 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2823 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2824 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2825 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2826 #define I40E_DEV_FUNC_CAP_LED 0x61
2827 #define I40E_DEV_FUNC_CAP_SDP 0x62
2828 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2831 * i40e_parse_discover_capabilities
2832 * @hw: pointer to the hw struct
2833 * @buff: pointer to a buffer containing device/function capability records
2834 * @cap_count: number of capability records in the list
2835 * @list_type_opc: type of capabilities list to parse
2837 * Parse the device/function capabilities list.
2839 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2841 enum i40e_admin_queue_opc list_type_opc)
2843 struct i40e_aqc_list_capabilities_element_resp *cap;
2844 u32 valid_functions, num_functions;
2845 u32 number, logical_id, phys_id;
2846 struct i40e_hw_capabilities *p;
2850 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2852 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2853 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
2854 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2855 p = (struct i40e_hw_capabilities *)&hw->func_caps;
2859 for (i = 0; i < cap_count; i++, cap++) {
2860 id = LE16_TO_CPU(cap->id);
2861 number = LE32_TO_CPU(cap->number);
2862 logical_id = LE32_TO_CPU(cap->logical_id);
2863 phys_id = LE32_TO_CPU(cap->phys_id);
2866 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2867 p->switch_mode = number;
2869 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2870 p->management_mode = number;
2872 case I40E_DEV_FUNC_CAP_NPAR:
2873 p->npar_enable = number;
2875 case I40E_DEV_FUNC_CAP_OS2BMC:
2878 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2879 p->valid_functions = number;
2881 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2883 p->sr_iov_1_1 = true;
2885 case I40E_DEV_FUNC_CAP_VF:
2886 p->num_vfs = number;
2887 p->vf_base_id = logical_id;
2889 case I40E_DEV_FUNC_CAP_VMDQ:
2893 case I40E_DEV_FUNC_CAP_802_1_QBG:
2895 p->evb_802_1_qbg = true;
2897 case I40E_DEV_FUNC_CAP_802_1_QBH:
2899 p->evb_802_1_qbh = true;
2901 case I40E_DEV_FUNC_CAP_VSI:
2902 p->num_vsis = number;
2904 case I40E_DEV_FUNC_CAP_DCB:
2907 p->enabled_tcmap = logical_id;
2911 case I40E_DEV_FUNC_CAP_FCOE:
2915 case I40E_DEV_FUNC_CAP_ISCSI:
2919 case I40E_DEV_FUNC_CAP_RSS:
2921 p->rss_table_size = number;
2922 p->rss_table_entry_width = logical_id;
2924 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2925 p->num_rx_qp = number;
2926 p->base_queue = phys_id;
2928 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2929 p->num_tx_qp = number;
2930 p->base_queue = phys_id;
2932 case I40E_DEV_FUNC_CAP_MSIX:
2933 p->num_msix_vectors = number;
2935 case I40E_DEV_FUNC_CAP_MSIX_VF:
2936 p->num_msix_vectors_vf = number;
2938 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2940 p->mfp_mode_1 = true;
2942 case I40E_DEV_FUNC_CAP_CEM:
2946 case I40E_DEV_FUNC_CAP_IWARP:
2950 case I40E_DEV_FUNC_CAP_LED:
2951 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2952 p->led[phys_id] = true;
2954 case I40E_DEV_FUNC_CAP_SDP:
2955 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2956 p->sdp[phys_id] = true;
2958 case I40E_DEV_FUNC_CAP_MDIO:
2960 p->mdio_port_num = phys_id;
2961 p->mdio_port_mode = logical_id;
2964 case I40E_DEV_FUNC_CAP_IEEE_1588:
2966 p->ieee_1588 = true;
2968 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2970 p->fd_filters_guaranteed = number;
2971 p->fd_filters_best_effort = logical_id;
2978 #ifdef I40E_FCOE_ENA
2979 /* Software override ensuring FCoE is disabled if npar or mfp
2980 * mode because it is not supported in these modes.
2982 if (p->npar_enable || p->mfp_mode_1)
2985 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
2989 /* count the enabled ports (aka the "not disabled" ports) */
2991 for (i = 0; i < 4; i++) {
2992 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2995 /* use AQ read to get the physical register offset instead
2996 * of the port relative offset
2998 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2999 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3003 valid_functions = p->valid_functions;
3005 while (valid_functions) {
3006 if (valid_functions & 1)
3008 valid_functions >>= 1;
3011 /* partition id is 1-based, and functions are evenly spread
3012 * across the ports as partitions
3014 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3015 hw->num_partitions = num_functions / hw->num_ports;
3017 /* additional HW specific goodies that might
3018 * someday be HW version specific
3020 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3024 * i40e_aq_discover_capabilities
3025 * @hw: pointer to the hw struct
3026 * @buff: a virtual buffer to hold the capabilities
3027 * @buff_size: Size of the virtual buffer
3028 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3029 * @list_type_opc: capabilities type to discover - pass in the command opcode
3030 * @cmd_details: pointer to command details structure or NULL
3032 * Get the device capabilities descriptions from the firmware
3034 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3035 void *buff, u16 buff_size, u16 *data_size,
3036 enum i40e_admin_queue_opc list_type_opc,
3037 struct i40e_asq_cmd_details *cmd_details)
3039 struct i40e_aqc_list_capabilites *cmd;
3040 struct i40e_aq_desc desc;
3041 enum i40e_status_code status = I40E_SUCCESS;
3043 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3045 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3046 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3047 status = I40E_ERR_PARAM;
3051 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3053 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3054 if (buff_size > I40E_AQ_LARGE_BUF)
3055 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3057 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3058 *data_size = LE16_TO_CPU(desc.datalen);
3063 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3071 * i40e_aq_update_nvm
3072 * @hw: pointer to the hw struct
3073 * @module_pointer: module pointer location in words from the NVM beginning
3074 * @offset: byte offset from the module beginning
3075 * @length: length of the section to be written (in bytes from the offset)
3076 * @data: command buffer (size [bytes] = length)
3077 * @last_command: tells if this is the last command in a series
3078 * @cmd_details: pointer to command details structure or NULL
3080 * Update the NVM using the admin queue commands
3082 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3083 u32 offset, u16 length, void *data,
3085 struct i40e_asq_cmd_details *cmd_details)
3087 struct i40e_aq_desc desc;
3088 struct i40e_aqc_nvm_update *cmd =
3089 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3090 enum i40e_status_code status;
3092 DEBUGFUNC("i40e_aq_update_nvm");
3094 /* In offset the highest byte must be zeroed. */
3095 if (offset & 0xFF000000) {
3096 status = I40E_ERR_PARAM;
3097 goto i40e_aq_update_nvm_exit;
3100 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3102 /* If this is the last command in a series, set the proper flag. */
3104 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3105 cmd->module_pointer = module_pointer;
3106 cmd->offset = CPU_TO_LE32(offset);
3107 cmd->length = CPU_TO_LE16(length);
3109 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3110 if (length > I40E_AQ_LARGE_BUF)
3111 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3113 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3115 i40e_aq_update_nvm_exit:
3120 * i40e_aq_get_lldp_mib
3121 * @hw: pointer to the hw struct
3122 * @bridge_type: type of bridge requested
3123 * @mib_type: Local, Remote or both Local and Remote MIBs
3124 * @buff: pointer to a user supplied buffer to store the MIB block
3125 * @buff_size: size of the buffer (in bytes)
3126 * @local_len : length of the returned Local LLDP MIB
3127 * @remote_len: length of the returned Remote LLDP MIB
3128 * @cmd_details: pointer to command details structure or NULL
3130 * Requests the complete LLDP MIB (entire packet).
3132 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3133 u8 mib_type, void *buff, u16 buff_size,
3134 u16 *local_len, u16 *remote_len,
3135 struct i40e_asq_cmd_details *cmd_details)
3137 struct i40e_aq_desc desc;
3138 struct i40e_aqc_lldp_get_mib *cmd =
3139 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3140 struct i40e_aqc_lldp_get_mib *resp =
3141 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3142 enum i40e_status_code status;
3144 if (buff_size == 0 || !buff)
3145 return I40E_ERR_PARAM;
3147 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3148 /* Indirect Command */
3149 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3151 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3152 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3153 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3155 desc.datalen = CPU_TO_LE16(buff_size);
3157 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3158 if (buff_size > I40E_AQ_LARGE_BUF)
3159 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3161 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3163 if (local_len != NULL)
3164 *local_len = LE16_TO_CPU(resp->local_len);
3165 if (remote_len != NULL)
3166 *remote_len = LE16_TO_CPU(resp->remote_len);
3173 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3174 * @hw: pointer to the hw struct
3175 * @mib_type: Local, Remote or both Local and Remote MIBs
3176 * @buff: pointer to a user supplied buffer to store the MIB block
3177 * @buff_size: size of the buffer (in bytes)
3178 * @cmd_details: pointer to command details structure or NULL
3182 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3183 u8 mib_type, void *buff, u16 buff_size,
3184 struct i40e_asq_cmd_details *cmd_details)
3186 struct i40e_aq_desc desc;
3187 struct i40e_aqc_lldp_set_local_mib *cmd =
3188 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3189 enum i40e_status_code status;
3191 if (buff_size == 0 || !buff)
3192 return I40E_ERR_PARAM;
3194 i40e_fill_default_direct_cmd_desc(&desc,
3195 i40e_aqc_opc_lldp_set_local_mib);
3196 /* Indirect Command */
3197 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3198 if (buff_size > I40E_AQ_LARGE_BUF)
3199 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3200 desc.datalen = CPU_TO_LE16(buff_size);
3202 cmd->type = mib_type;
3203 cmd->length = CPU_TO_LE16(buff_size);
3204 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3205 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3207 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3212 * i40e_aq_cfg_lldp_mib_change_event
3213 * @hw: pointer to the hw struct
3214 * @enable_update: Enable or Disable event posting
3215 * @cmd_details: pointer to command details structure or NULL
3217 * Enable or Disable posting of an event on ARQ when LLDP MIB
3218 * associated with the interface changes
3220 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3222 struct i40e_asq_cmd_details *cmd_details)
3224 struct i40e_aq_desc desc;
3225 struct i40e_aqc_lldp_update_mib *cmd =
3226 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3227 enum i40e_status_code status;
3229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3232 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3234 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3240 * i40e_aq_add_lldp_tlv
3241 * @hw: pointer to the hw struct
3242 * @bridge_type: type of bridge
3243 * @buff: buffer with TLV to add
3244 * @buff_size: length of the buffer
3245 * @tlv_len: length of the TLV to be added
3246 * @mib_len: length of the LLDP MIB returned in response
3247 * @cmd_details: pointer to command details structure or NULL
3249 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3250 * it is responsibility of the caller to make sure that the TLV is not
3251 * already present in the LLDPDU.
3252 * In return firmware will write the complete LLDP MIB with the newly
3253 * added TLV in the response buffer.
3255 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3256 void *buff, u16 buff_size, u16 tlv_len,
3258 struct i40e_asq_cmd_details *cmd_details)
3260 struct i40e_aq_desc desc;
3261 struct i40e_aqc_lldp_add_tlv *cmd =
3262 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3263 enum i40e_status_code status;
3265 if (buff_size == 0 || !buff || tlv_len == 0)
3266 return I40E_ERR_PARAM;
3268 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3270 /* Indirect Command */
3271 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3272 if (buff_size > I40E_AQ_LARGE_BUF)
3273 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3274 desc.datalen = CPU_TO_LE16(buff_size);
3276 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3277 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3278 cmd->len = CPU_TO_LE16(tlv_len);
3280 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3282 if (mib_len != NULL)
3283 *mib_len = LE16_TO_CPU(desc.datalen);
3290 * i40e_aq_update_lldp_tlv
3291 * @hw: pointer to the hw struct
3292 * @bridge_type: type of bridge
3293 * @buff: buffer with TLV to update
3294 * @buff_size: size of the buffer holding original and updated TLVs
3295 * @old_len: Length of the Original TLV
3296 * @new_len: Length of the Updated TLV
3297 * @offset: offset of the updated TLV in the buff
3298 * @mib_len: length of the returned LLDP MIB
3299 * @cmd_details: pointer to command details structure or NULL
3301 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3302 * Firmware will place the complete LLDP MIB in response buffer with the
3305 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3306 u8 bridge_type, void *buff, u16 buff_size,
3307 u16 old_len, u16 new_len, u16 offset,
3309 struct i40e_asq_cmd_details *cmd_details)
3311 struct i40e_aq_desc desc;
3312 struct i40e_aqc_lldp_update_tlv *cmd =
3313 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3314 enum i40e_status_code status;
3316 if (buff_size == 0 || !buff || offset == 0 ||
3317 old_len == 0 || new_len == 0)
3318 return I40E_ERR_PARAM;
3320 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3322 /* Indirect Command */
3323 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3324 if (buff_size > I40E_AQ_LARGE_BUF)
3325 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3326 desc.datalen = CPU_TO_LE16(buff_size);
3328 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3329 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3330 cmd->old_len = CPU_TO_LE16(old_len);
3331 cmd->new_offset = CPU_TO_LE16(offset);
3332 cmd->new_len = CPU_TO_LE16(new_len);
3334 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3336 if (mib_len != NULL)
3337 *mib_len = LE16_TO_CPU(desc.datalen);
3344 * i40e_aq_delete_lldp_tlv
3345 * @hw: pointer to the hw struct
3346 * @bridge_type: type of bridge
3347 * @buff: pointer to a user supplied buffer that has the TLV
3348 * @buff_size: length of the buffer
3349 * @tlv_len: length of the TLV to be deleted
3350 * @mib_len: length of the returned LLDP MIB
3351 * @cmd_details: pointer to command details structure or NULL
3353 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3354 * The firmware places the entire LLDP MIB in the response buffer.
3356 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3357 u8 bridge_type, void *buff, u16 buff_size,
3358 u16 tlv_len, u16 *mib_len,
3359 struct i40e_asq_cmd_details *cmd_details)
3361 struct i40e_aq_desc desc;
3362 struct i40e_aqc_lldp_add_tlv *cmd =
3363 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3364 enum i40e_status_code status;
3366 if (buff_size == 0 || !buff)
3367 return I40E_ERR_PARAM;
3369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3371 /* Indirect Command */
3372 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3373 if (buff_size > I40E_AQ_LARGE_BUF)
3374 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3375 desc.datalen = CPU_TO_LE16(buff_size);
3376 cmd->len = CPU_TO_LE16(tlv_len);
3377 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3378 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3380 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3382 if (mib_len != NULL)
3383 *mib_len = LE16_TO_CPU(desc.datalen);
3391 * @hw: pointer to the hw struct
3392 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3393 * @cmd_details: pointer to command details structure or NULL
3395 * Stop or Shutdown the embedded LLDP Agent
3397 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3398 struct i40e_asq_cmd_details *cmd_details)
3400 struct i40e_aq_desc desc;
3401 struct i40e_aqc_lldp_stop *cmd =
3402 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3403 enum i40e_status_code status;
3405 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3408 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3416 * i40e_aq_start_lldp
3417 * @hw: pointer to the hw struct
3418 * @cmd_details: pointer to command details structure or NULL
3420 * Start the embedded LLDP Agent on all ports.
3422 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3423 struct i40e_asq_cmd_details *cmd_details)
3425 struct i40e_aq_desc desc;
3426 struct i40e_aqc_lldp_start *cmd =
3427 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3428 enum i40e_status_code status;
3430 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3432 cmd->command = I40E_AQ_LLDP_AGENT_START;
3434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3440 * i40e_aq_get_cee_dcb_config
3441 * @hw: pointer to the hw struct
3442 * @buff: response buffer that stores CEE operational configuration
3443 * @buff_size: size of the buffer passed
3444 * @cmd_details: pointer to command details structure or NULL
3446 * Get CEE DCBX mode operational configuration from firmware
3448 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3449 void *buff, u16 buff_size,
3450 struct i40e_asq_cmd_details *cmd_details)
3452 struct i40e_aq_desc desc;
3453 enum i40e_status_code status;
3455 if (buff_size == 0 || !buff)
3456 return I40E_ERR_PARAM;
3458 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3460 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3461 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3468 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3469 * @hw: pointer to the hw struct
3470 * @start_agent: True if DCBx Agent needs to be Started
3471 * False if DCBx Agent needs to be Stopped
3472 * @cmd_details: pointer to command details structure or NULL
3474 * Start/Stop the embedded dcbx Agent
3476 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3478 struct i40e_asq_cmd_details *cmd_details)
3480 struct i40e_aq_desc desc;
3481 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3482 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3484 enum i40e_status_code status;
3486 i40e_fill_default_direct_cmd_desc(&desc,
3487 i40e_aqc_opc_lldp_stop_start_spec_agent);
3490 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3498 * i40e_aq_add_udp_tunnel
3499 * @hw: pointer to the hw struct
3500 * @udp_port: the UDP port to add
3501 * @header_len: length of the tunneling header length in DWords
3502 * @protocol_index: protocol index type
3503 * @filter_index: pointer to filter index
3504 * @cmd_details: pointer to command details structure or NULL
3506 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3507 u16 udp_port, u8 protocol_index,
3509 struct i40e_asq_cmd_details *cmd_details)
3511 struct i40e_aq_desc desc;
3512 struct i40e_aqc_add_udp_tunnel *cmd =
3513 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3514 struct i40e_aqc_del_udp_tunnel_completion *resp =
3515 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3516 enum i40e_status_code status;
3518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3520 cmd->udp_port = CPU_TO_LE16(udp_port);
3521 cmd->protocol_type = protocol_index;
3523 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3525 if (!status && filter_index)
3526 *filter_index = resp->index;
3532 * i40e_aq_del_udp_tunnel
3533 * @hw: pointer to the hw struct
3534 * @index: filter index
3535 * @cmd_details: pointer to command details structure or NULL
3537 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3538 struct i40e_asq_cmd_details *cmd_details)
3540 struct i40e_aq_desc desc;
3541 struct i40e_aqc_remove_udp_tunnel *cmd =
3542 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3543 enum i40e_status_code status;
3545 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3549 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3555 * i40e_aq_get_switch_resource_alloc (0x0204)
3556 * @hw: pointer to the hw struct
3557 * @num_entries: pointer to u8 to store the number of resource entries returned
3558 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3559 * to store the resource information for all resource types. Each
3560 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3561 * @count: size, in bytes, of the buffer provided
3562 * @cmd_details: pointer to command details structure or NULL
3564 * Query the resources allocated to a function.
3566 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3568 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3570 struct i40e_asq_cmd_details *cmd_details)
3572 struct i40e_aq_desc desc;
3573 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3574 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3575 enum i40e_status_code status;
3576 u16 length = count * sizeof(*buf);
3578 i40e_fill_default_direct_cmd_desc(&desc,
3579 i40e_aqc_opc_get_switch_resource_alloc);
3581 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3582 if (length > I40E_AQ_LARGE_BUF)
3583 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3585 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3587 if (!status && num_entries)
3588 *num_entries = cmd_resp->num_entries;
3594 * i40e_aq_delete_element - Delete switch element
3595 * @hw: pointer to the hw struct
3596 * @seid: the SEID to delete from the switch
3597 * @cmd_details: pointer to command details structure or NULL
3599 * This deletes a switch element from the switch.
3601 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3602 struct i40e_asq_cmd_details *cmd_details)
3604 struct i40e_aq_desc desc;
3605 struct i40e_aqc_switch_seid *cmd =
3606 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3607 enum i40e_status_code status;
3610 return I40E_ERR_PARAM;
3612 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3614 cmd->seid = CPU_TO_LE16(seid);
3616 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3622 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3623 * @hw: pointer to the hw struct
3624 * @flags: component flags
3625 * @mac_seid: uplink seid (MAC SEID)
3626 * @vsi_seid: connected vsi seid
3627 * @ret_seid: seid of create pv component
3629 * This instantiates an i40e port virtualizer with specified flags.
3630 * Depending on specified flags the port virtualizer can act as a
3631 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3633 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3634 u16 mac_seid, u16 vsi_seid,
3637 struct i40e_aq_desc desc;
3638 struct i40e_aqc_add_update_pv *cmd =
3639 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3640 struct i40e_aqc_add_update_pv_completion *resp =
3641 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3642 enum i40e_status_code status;
3645 return I40E_ERR_PARAM;
3647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3648 cmd->command_flags = CPU_TO_LE16(flags);
3649 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3650 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3652 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3653 if (!status && ret_seid)
3654 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3660 * i40e_aq_add_tag - Add an S/E-tag
3661 * @hw: pointer to the hw struct
3662 * @direct_to_queue: should s-tag direct flow to a specific queue
3663 * @vsi_seid: VSI SEID to use this tag
3664 * @tag: value of the tag
3665 * @queue_num: queue number, only valid is direct_to_queue is true
3666 * @tags_used: return value, number of tags in use by this PF
3667 * @tags_free: return value, number of unallocated tags
3668 * @cmd_details: pointer to command details structure or NULL
3670 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3671 * the number of tags allocated by the PF, and the number of unallocated
3674 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3675 u16 vsi_seid, u16 tag, u16 queue_num,
3676 u16 *tags_used, u16 *tags_free,
3677 struct i40e_asq_cmd_details *cmd_details)
3679 struct i40e_aq_desc desc;
3680 struct i40e_aqc_add_tag *cmd =
3681 (struct i40e_aqc_add_tag *)&desc.params.raw;
3682 struct i40e_aqc_add_remove_tag_completion *resp =
3683 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3684 enum i40e_status_code status;
3687 return I40E_ERR_PARAM;
3689 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3691 cmd->seid = CPU_TO_LE16(vsi_seid);
3692 cmd->tag = CPU_TO_LE16(tag);
3693 if (direct_to_queue) {
3694 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3695 cmd->queue_number = CPU_TO_LE16(queue_num);
3698 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3701 if (tags_used != NULL)
3702 *tags_used = LE16_TO_CPU(resp->tags_used);
3703 if (tags_free != NULL)
3704 *tags_free = LE16_TO_CPU(resp->tags_free);
3711 * i40e_aq_remove_tag - Remove an S- or E-tag
3712 * @hw: pointer to the hw struct
3713 * @vsi_seid: VSI SEID this tag is associated with
3714 * @tag: value of the S-tag to delete
3715 * @tags_used: return value, number of tags in use by this PF
3716 * @tags_free: return value, number of unallocated tags
3717 * @cmd_details: pointer to command details structure or NULL
3719 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3720 * the number of tags allocated by the PF, and the number of unallocated
3723 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3724 u16 tag, u16 *tags_used, u16 *tags_free,
3725 struct i40e_asq_cmd_details *cmd_details)
3727 struct i40e_aq_desc desc;
3728 struct i40e_aqc_remove_tag *cmd =
3729 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3730 struct i40e_aqc_add_remove_tag_completion *resp =
3731 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3732 enum i40e_status_code status;
3735 return I40E_ERR_PARAM;
3737 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3739 cmd->seid = CPU_TO_LE16(vsi_seid);
3740 cmd->tag = CPU_TO_LE16(tag);
3742 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3745 if (tags_used != NULL)
3746 *tags_used = LE16_TO_CPU(resp->tags_used);
3747 if (tags_free != NULL)
3748 *tags_free = LE16_TO_CPU(resp->tags_free);
3755 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3756 * @hw: pointer to the hw struct
3757 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3758 * @etag: value of E-tag to add
3759 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3760 * @buf: address of indirect buffer
3761 * @tags_used: return value, number of E-tags in use by this port
3762 * @tags_free: return value, number of unallocated M-tags
3763 * @cmd_details: pointer to command details structure or NULL
3765 * This associates a multicast E-tag to a port virtualizer. It will return
3766 * the number of tags allocated by the PF, and the number of unallocated
3769 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3770 * num_tags_in_buf long.
3772 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3773 u16 etag, u8 num_tags_in_buf, void *buf,
3774 u16 *tags_used, u16 *tags_free,
3775 struct i40e_asq_cmd_details *cmd_details)
3777 struct i40e_aq_desc desc;
3778 struct i40e_aqc_add_remove_mcast_etag *cmd =
3779 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3780 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3781 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3782 enum i40e_status_code status;
3783 u16 length = sizeof(u16) * num_tags_in_buf;
3785 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3786 return I40E_ERR_PARAM;
3788 i40e_fill_default_direct_cmd_desc(&desc,
3789 i40e_aqc_opc_add_multicast_etag);
3791 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3792 cmd->etag = CPU_TO_LE16(etag);
3793 cmd->num_unicast_etags = num_tags_in_buf;
3795 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3796 if (length > I40E_AQ_LARGE_BUF)
3797 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3799 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3802 if (tags_used != NULL)
3803 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3804 if (tags_free != NULL)
3805 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3812 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
3813 * @hw: pointer to the hw struct
3814 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
3815 * @etag: value of the E-tag to remove
3816 * @tags_used: return value, number of tags in use by this port
3817 * @tags_free: return value, number of unallocated tags
3818 * @cmd_details: pointer to command details structure or NULL
3820 * This deletes an E-tag from the port virtualizer. It will return
3821 * the number of tags allocated by the port, and the number of unallocated
3824 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3825 u16 etag, u16 *tags_used, u16 *tags_free,
3826 struct i40e_asq_cmd_details *cmd_details)
3828 struct i40e_aq_desc desc;
3829 struct i40e_aqc_add_remove_mcast_etag *cmd =
3830 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3831 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3832 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3833 enum i40e_status_code status;
3837 return I40E_ERR_PARAM;
3839 i40e_fill_default_direct_cmd_desc(&desc,
3840 i40e_aqc_opc_remove_multicast_etag);
3842 cmd->pv_seid = CPU_TO_LE16(pv_seid);
3843 cmd->etag = CPU_TO_LE16(etag);
3845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3848 if (tags_used != NULL)
3849 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
3850 if (tags_free != NULL)
3851 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
3858 * i40e_aq_update_tag - Update an S/E-tag
3859 * @hw: pointer to the hw struct
3860 * @vsi_seid: VSI SEID using this S-tag
3861 * @old_tag: old tag value
3862 * @new_tag: new tag value
3863 * @tags_used: return value, number of tags in use by this PF
3864 * @tags_free: return value, number of unallocated tags
3865 * @cmd_details: pointer to command details structure or NULL
3867 * This updates the value of the tag currently attached to this VSI
3868 * in the switch complex. It will return the number of tags allocated
3869 * by the PF, and the number of unallocated tags available.
3871 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
3872 u16 old_tag, u16 new_tag, u16 *tags_used,
3874 struct i40e_asq_cmd_details *cmd_details)
3876 struct i40e_aq_desc desc;
3877 struct i40e_aqc_update_tag *cmd =
3878 (struct i40e_aqc_update_tag *)&desc.params.raw;
3879 struct i40e_aqc_update_tag_completion *resp =
3880 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
3881 enum i40e_status_code status;
3884 return I40E_ERR_PARAM;
3886 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
3888 cmd->seid = CPU_TO_LE16(vsi_seid);
3889 cmd->old_tag = CPU_TO_LE16(old_tag);
3890 cmd->new_tag = CPU_TO_LE16(new_tag);
3892 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3895 if (tags_used != NULL)
3896 *tags_used = LE16_TO_CPU(resp->tags_used);
3897 if (tags_free != NULL)
3898 *tags_free = LE16_TO_CPU(resp->tags_free);
3905 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
3906 * @hw: pointer to the hw struct
3907 * @tcmap: TC map for request/release any ignore PFC condition
3908 * @request: request or release ignore PFC condition
3909 * @tcmap_ret: return TCs for which PFC is currently ignored
3910 * @cmd_details: pointer to command details structure or NULL
3912 * This sends out request/release to ignore PFC condition for a TC.
3913 * It will return the TCs for which PFC is currently ignored.
3915 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
3916 bool request, u8 *tcmap_ret,
3917 struct i40e_asq_cmd_details *cmd_details)
3919 struct i40e_aq_desc desc;
3920 struct i40e_aqc_pfc_ignore *cmd_resp =
3921 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
3922 enum i40e_status_code status;
3924 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
3927 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
3929 cmd_resp->tc_bitmap = tcmap;
3931 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3934 if (tcmap_ret != NULL)
3935 *tcmap_ret = cmd_resp->tc_bitmap;
3942 * i40e_aq_dcb_updated - DCB Updated Command
3943 * @hw: pointer to the hw struct
3944 * @cmd_details: pointer to command details structure or NULL
3946 * When LLDP is handled in PF this command is used by the PF
3947 * to notify EMP that a DCB setting is modified.
3948 * When LLDP is handled in EMP this command is used by the PF
3949 * to notify EMP whenever one of the following parameters get
3951 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
3952 * - PCIRTT in PRTDCB_GENC.PCIRTT
3953 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
3954 * EMP will return when the shared RPB settings have been
3955 * recomputed and modified. The retval field in the descriptor
3956 * will be set to 0 when RPB is modified.
3958 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
3959 struct i40e_asq_cmd_details *cmd_details)
3961 struct i40e_aq_desc desc;
3962 enum i40e_status_code status;
3964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3966 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3972 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
3973 * @hw: pointer to the hw struct
3974 * @seid: defines the SEID of the switch for which the stats are requested
3975 * @vlan_id: the VLAN ID for which the statistics are requested
3976 * @stat_index: index of the statistics counters block assigned to this VLAN
3977 * @cmd_details: pointer to command details structure or NULL
3979 * XL710 supports 128 smonVlanStats counters.This command is used to
3980 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
3983 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
3984 u16 vlan_id, u16 *stat_index,
3985 struct i40e_asq_cmd_details *cmd_details)
3987 struct i40e_aq_desc desc;
3988 struct i40e_aqc_add_remove_statistics *cmd_resp =
3989 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
3990 enum i40e_status_code status;
3992 if ((seid == 0) || (stat_index == NULL))
3993 return I40E_ERR_PARAM;
3995 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
3997 cmd_resp->seid = CPU_TO_LE16(seid);
3998 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4000 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4002 if (!status && stat_index)
4003 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4009 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4010 * @hw: pointer to the hw struct
4011 * @seid: defines the SEID of the switch for which the stats are requested
4012 * @vlan_id: the VLAN ID for which the statistics are requested
4013 * @stat_index: index of the statistics counters block assigned to this VLAN
4014 * @cmd_details: pointer to command details structure or NULL
4016 * XL710 supports 128 smonVlanStats counters.This command is used to
4017 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4020 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4021 u16 vlan_id, u16 stat_index,
4022 struct i40e_asq_cmd_details *cmd_details)
4024 struct i40e_aq_desc desc;
4025 struct i40e_aqc_add_remove_statistics *cmd =
4026 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4027 enum i40e_status_code status;
4030 return I40E_ERR_PARAM;
4032 i40e_fill_default_direct_cmd_desc(&desc,
4033 i40e_aqc_opc_remove_statistics);
4035 cmd->seid = CPU_TO_LE16(seid);
4036 cmd->vlan = CPU_TO_LE16(vlan_id);
4037 cmd->stat_index = CPU_TO_LE16(stat_index);
4039 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4045 * i40e_aq_set_port_parameters - set physical port parameters.
4046 * @hw: pointer to the hw struct
4047 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4048 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4049 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4050 * @double_vlan: if set double VLAN is enabled
4051 * @cmd_details: pointer to command details structure or NULL
4053 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4054 u16 bad_frame_vsi, bool save_bad_pac,
4055 bool pad_short_pac, bool double_vlan,
4056 struct i40e_asq_cmd_details *cmd_details)
4058 struct i40e_aqc_set_port_parameters *cmd;
4059 enum i40e_status_code status;
4060 struct i40e_aq_desc desc;
4061 u16 command_flags = 0;
4063 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4065 i40e_fill_default_direct_cmd_desc(&desc,
4066 i40e_aqc_opc_set_port_parameters);
4068 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4070 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4072 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4074 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4075 cmd->command_flags = CPU_TO_LE16(command_flags);
4077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4083 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4084 * @hw: pointer to the hw struct
4085 * @seid: seid for the physical port/switching component/vsi
4086 * @buff: Indirect buffer to hold data parameters and response
4087 * @buff_size: Indirect buffer size
4088 * @opcode: Tx scheduler AQ command opcode
4089 * @cmd_details: pointer to command details structure or NULL
4091 * Generic command handler for Tx scheduler AQ commands
4093 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4094 void *buff, u16 buff_size,
4095 enum i40e_admin_queue_opc opcode,
4096 struct i40e_asq_cmd_details *cmd_details)
4098 struct i40e_aq_desc desc;
4099 struct i40e_aqc_tx_sched_ind *cmd =
4100 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4101 enum i40e_status_code status;
4102 bool cmd_param_flag = false;
4105 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4106 case i40e_aqc_opc_configure_vsi_tc_bw:
4107 case i40e_aqc_opc_enable_switching_comp_ets:
4108 case i40e_aqc_opc_modify_switching_comp_ets:
4109 case i40e_aqc_opc_disable_switching_comp_ets:
4110 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4111 case i40e_aqc_opc_configure_switching_comp_bw_config:
4112 cmd_param_flag = true;
4114 case i40e_aqc_opc_query_vsi_bw_config:
4115 case i40e_aqc_opc_query_vsi_ets_sla_config:
4116 case i40e_aqc_opc_query_switching_comp_ets_config:
4117 case i40e_aqc_opc_query_port_ets_config:
4118 case i40e_aqc_opc_query_switching_comp_bw_config:
4119 cmd_param_flag = false;
4122 return I40E_ERR_PARAM;
4125 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4127 /* Indirect command */
4128 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4130 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4131 if (buff_size > I40E_AQ_LARGE_BUF)
4132 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4134 desc.datalen = CPU_TO_LE16(buff_size);
4136 cmd->vsi_seid = CPU_TO_LE16(seid);
4138 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4144 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4145 * @hw: pointer to the hw struct
4147 * @credit: BW limit credits (0 = disabled)
4148 * @max_credit: Max BW limit credits
4149 * @cmd_details: pointer to command details structure or NULL
4151 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4152 u16 seid, u16 credit, u8 max_credit,
4153 struct i40e_asq_cmd_details *cmd_details)
4155 struct i40e_aq_desc desc;
4156 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4157 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4158 enum i40e_status_code status;
4160 i40e_fill_default_direct_cmd_desc(&desc,
4161 i40e_aqc_opc_configure_vsi_bw_limit);
4163 cmd->vsi_seid = CPU_TO_LE16(seid);
4164 cmd->credit = CPU_TO_LE16(credit);
4165 cmd->max_credit = max_credit;
4167 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4173 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4174 * @hw: pointer to the hw struct
4175 * @seid: switching component seid
4176 * @credit: BW limit credits (0 = disabled)
4177 * @max_bw: Max BW limit credits
4178 * @cmd_details: pointer to command details structure or NULL
4180 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4181 u16 seid, u16 credit, u8 max_bw,
4182 struct i40e_asq_cmd_details *cmd_details)
4184 struct i40e_aq_desc desc;
4185 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4186 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4187 enum i40e_status_code status;
4189 i40e_fill_default_direct_cmd_desc(&desc,
4190 i40e_aqc_opc_configure_switching_comp_bw_limit);
4192 cmd->seid = CPU_TO_LE16(seid);
4193 cmd->credit = CPU_TO_LE16(credit);
4194 cmd->max_bw = max_bw;
4196 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4202 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4203 * @hw: pointer to the hw struct
4205 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4206 * @cmd_details: pointer to command details structure or NULL
4208 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4210 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4211 struct i40e_asq_cmd_details *cmd_details)
4213 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4214 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4219 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4220 * @hw: pointer to the hw struct
4222 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4223 * @cmd_details: pointer to command details structure or NULL
4225 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4227 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4228 struct i40e_asq_cmd_details *cmd_details)
4230 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4231 i40e_aqc_opc_configure_vsi_tc_bw,
4236 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4237 * @hw: pointer to the hw struct
4238 * @seid: seid of the switching component
4239 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4240 * @cmd_details: pointer to command details structure or NULL
4242 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4243 struct i40e_hw *hw, u16 seid,
4244 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4245 struct i40e_asq_cmd_details *cmd_details)
4247 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4248 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4253 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4254 * @hw: pointer to the hw struct
4255 * @seid: seid of the VSI
4256 * @bw_data: Buffer to hold VSI BW configuration
4257 * @cmd_details: pointer to command details structure or NULL
4259 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4261 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4262 struct i40e_asq_cmd_details *cmd_details)
4264 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4265 i40e_aqc_opc_query_vsi_bw_config,
4270 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4271 * @hw: pointer to the hw struct
4272 * @seid: seid of the VSI
4273 * @bw_data: Buffer to hold VSI BW configuration per TC
4274 * @cmd_details: pointer to command details structure or NULL
4276 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4278 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4279 struct i40e_asq_cmd_details *cmd_details)
4281 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4282 i40e_aqc_opc_query_vsi_ets_sla_config,
4287 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4288 * @hw: pointer to the hw struct
4289 * @seid: seid of the switching component
4290 * @bw_data: Buffer to hold switching component's per TC BW config
4291 * @cmd_details: pointer to command details structure or NULL
4293 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4295 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4296 struct i40e_asq_cmd_details *cmd_details)
4298 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4299 i40e_aqc_opc_query_switching_comp_ets_config,
4304 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4305 * @hw: pointer to the hw struct
4306 * @seid: seid of the VSI or switching component connected to Physical Port
4307 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4308 * @cmd_details: pointer to command details structure or NULL
4310 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4312 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4313 struct i40e_asq_cmd_details *cmd_details)
4315 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4316 i40e_aqc_opc_query_port_ets_config,
4321 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4322 * @hw: pointer to the hw struct
4323 * @seid: seid of the switching component
4324 * @bw_data: Buffer to hold switching component's BW configuration
4325 * @cmd_details: pointer to command details structure or NULL
4327 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4329 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4330 struct i40e_asq_cmd_details *cmd_details)
4332 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4333 i40e_aqc_opc_query_switching_comp_bw_config,
4338 * i40e_validate_filter_settings
4339 * @hw: pointer to the hardware structure
4340 * @settings: Filter control settings
4342 * Check and validate the filter control settings passed.
4343 * The function checks for the valid filter/context sizes being
4344 * passed for FCoE and PE.
4346 * Returns I40E_SUCCESS if the values passed are valid and within
4347 * range else returns an error.
4349 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4350 struct i40e_filter_control_settings *settings)
4352 u32 fcoe_cntx_size, fcoe_filt_size;
4353 u32 pe_cntx_size, pe_filt_size;
4358 /* Validate FCoE settings passed */
4359 switch (settings->fcoe_filt_num) {
4360 case I40E_HASH_FILTER_SIZE_1K:
4361 case I40E_HASH_FILTER_SIZE_2K:
4362 case I40E_HASH_FILTER_SIZE_4K:
4363 case I40E_HASH_FILTER_SIZE_8K:
4364 case I40E_HASH_FILTER_SIZE_16K:
4365 case I40E_HASH_FILTER_SIZE_32K:
4366 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4367 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4370 return I40E_ERR_PARAM;
4373 switch (settings->fcoe_cntx_num) {
4374 case I40E_DMA_CNTX_SIZE_512:
4375 case I40E_DMA_CNTX_SIZE_1K:
4376 case I40E_DMA_CNTX_SIZE_2K:
4377 case I40E_DMA_CNTX_SIZE_4K:
4378 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4379 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4382 return I40E_ERR_PARAM;
4385 /* Validate PE settings passed */
4386 switch (settings->pe_filt_num) {
4387 case I40E_HASH_FILTER_SIZE_1K:
4388 case I40E_HASH_FILTER_SIZE_2K:
4389 case I40E_HASH_FILTER_SIZE_4K:
4390 case I40E_HASH_FILTER_SIZE_8K:
4391 case I40E_HASH_FILTER_SIZE_16K:
4392 case I40E_HASH_FILTER_SIZE_32K:
4393 case I40E_HASH_FILTER_SIZE_64K:
4394 case I40E_HASH_FILTER_SIZE_128K:
4395 case I40E_HASH_FILTER_SIZE_256K:
4396 case I40E_HASH_FILTER_SIZE_512K:
4397 case I40E_HASH_FILTER_SIZE_1M:
4398 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4399 pe_filt_size <<= (u32)settings->pe_filt_num;
4402 return I40E_ERR_PARAM;
4405 switch (settings->pe_cntx_num) {
4406 case I40E_DMA_CNTX_SIZE_512:
4407 case I40E_DMA_CNTX_SIZE_1K:
4408 case I40E_DMA_CNTX_SIZE_2K:
4409 case I40E_DMA_CNTX_SIZE_4K:
4410 case I40E_DMA_CNTX_SIZE_8K:
4411 case I40E_DMA_CNTX_SIZE_16K:
4412 case I40E_DMA_CNTX_SIZE_32K:
4413 case I40E_DMA_CNTX_SIZE_64K:
4414 case I40E_DMA_CNTX_SIZE_128K:
4415 case I40E_DMA_CNTX_SIZE_256K:
4416 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4417 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4420 return I40E_ERR_PARAM;
4423 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4424 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4425 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4426 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4427 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4428 return I40E_ERR_INVALID_SIZE;
4430 return I40E_SUCCESS;
4434 * i40e_set_filter_control
4435 * @hw: pointer to the hardware structure
4436 * @settings: Filter control settings
4438 * Set the Queue Filters for PE/FCoE and enable filters required
4439 * for a single PF. It is expected that these settings are programmed
4440 * at the driver initialization time.
4442 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4443 struct i40e_filter_control_settings *settings)
4445 enum i40e_status_code ret = I40E_SUCCESS;
4446 u32 hash_lut_size = 0;
4450 return I40E_ERR_PARAM;
4452 /* Validate the input settings */
4453 ret = i40e_validate_filter_settings(hw, settings);
4457 /* Read the PF Queue Filter control register */
4458 val = rd32(hw, I40E_PFQF_CTL_0);
4460 /* Program required PE hash buckets for the PF */
4461 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4462 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4463 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4464 /* Program required PE contexts for the PF */
4465 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4466 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4467 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4469 /* Program required FCoE hash buckets for the PF */
4470 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4471 val |= ((u32)settings->fcoe_filt_num <<
4472 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4473 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4474 /* Program required FCoE DDP contexts for the PF */
4475 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4476 val |= ((u32)settings->fcoe_cntx_num <<
4477 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4478 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4480 /* Program Hash LUT size for the PF */
4481 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4482 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4484 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4485 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4487 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4488 if (settings->enable_fdir)
4489 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4490 if (settings->enable_ethtype)
4491 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4492 if (settings->enable_macvlan)
4493 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4495 wr32(hw, I40E_PFQF_CTL_0, val);
4497 return I40E_SUCCESS;
4501 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4502 * @hw: pointer to the hw struct
4503 * @mac_addr: MAC address to use in the filter
4504 * @ethtype: Ethertype to use in the filter
4505 * @flags: Flags that needs to be applied to the filter
4506 * @vsi_seid: seid of the control VSI
4507 * @queue: VSI queue number to send the packet to
4508 * @is_add: Add control packet filter if True else remove
4509 * @stats: Structure to hold information on control filter counts
4510 * @cmd_details: pointer to command details structure or NULL
4512 * This command will Add or Remove control packet filter for a control VSI.
4513 * In return it will update the total number of perfect filter count in
4516 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4517 u8 *mac_addr, u16 ethtype, u16 flags,
4518 u16 vsi_seid, u16 queue, bool is_add,
4519 struct i40e_control_filter_stats *stats,
4520 struct i40e_asq_cmd_details *cmd_details)
4522 struct i40e_aq_desc desc;
4523 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4524 (struct i40e_aqc_add_remove_control_packet_filter *)
4526 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4527 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4529 enum i40e_status_code status;
4532 return I40E_ERR_PARAM;
4535 i40e_fill_default_direct_cmd_desc(&desc,
4536 i40e_aqc_opc_add_control_packet_filter);
4537 cmd->queue = CPU_TO_LE16(queue);
4539 i40e_fill_default_direct_cmd_desc(&desc,
4540 i40e_aqc_opc_remove_control_packet_filter);
4544 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4545 I40E_NONDMA_TO_NONDMA);
4547 cmd->etype = CPU_TO_LE16(ethtype);
4548 cmd->flags = CPU_TO_LE16(flags);
4549 cmd->seid = CPU_TO_LE16(vsi_seid);
4551 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4553 if (!status && stats) {
4554 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4555 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4556 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4557 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4564 * i40e_aq_add_cloud_filters
4565 * @hw: pointer to the hardware structure
4566 * @seid: VSI seid to add cloud filters from
4567 * @filters: Buffer which contains the filters to be added
4568 * @filter_count: number of filters contained in the buffer
4570 * Set the cloud filters for a given VSI. The contents of the
4571 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4572 * in by the caller of the function.
4575 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4577 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4580 struct i40e_aq_desc desc;
4581 struct i40e_aqc_add_remove_cloud_filters *cmd =
4582 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4584 enum i40e_status_code status;
4586 i40e_fill_default_direct_cmd_desc(&desc,
4587 i40e_aqc_opc_add_cloud_filters);
4589 buff_len = filter_count * sizeof(*filters);
4590 desc.datalen = CPU_TO_LE16(buff_len);
4591 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4592 cmd->num_filters = filter_count;
4593 cmd->seid = CPU_TO_LE16(seid);
4595 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4601 * i40e_aq_remove_cloud_filters
4602 * @hw: pointer to the hardware structure
4603 * @seid: VSI seid to remove cloud filters from
4604 * @filters: Buffer which contains the filters to be removed
4605 * @filter_count: number of filters contained in the buffer
4607 * Remove the cloud filters for a given VSI. The contents of the
4608 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4609 * in by the caller of the function.
4612 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4614 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4617 struct i40e_aq_desc desc;
4618 struct i40e_aqc_add_remove_cloud_filters *cmd =
4619 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4620 enum i40e_status_code status;
4623 i40e_fill_default_direct_cmd_desc(&desc,
4624 i40e_aqc_opc_remove_cloud_filters);
4626 buff_len = filter_count * sizeof(*filters);
4627 desc.datalen = CPU_TO_LE16(buff_len);
4628 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4629 cmd->num_filters = filter_count;
4630 cmd->seid = CPU_TO_LE16(seid);
4632 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4638 * i40e_aq_alternate_write
4639 * @hw: pointer to the hardware structure
4640 * @reg_addr0: address of first dword to be read
4641 * @reg_val0: value to be written under 'reg_addr0'
4642 * @reg_addr1: address of second dword to be read
4643 * @reg_val1: value to be written under 'reg_addr1'
4645 * Write one or two dwords to alternate structure. Fields are indicated
4646 * by 'reg_addr0' and 'reg_addr1' register numbers.
4649 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4650 u32 reg_addr0, u32 reg_val0,
4651 u32 reg_addr1, u32 reg_val1)
4653 struct i40e_aq_desc desc;
4654 struct i40e_aqc_alternate_write *cmd_resp =
4655 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4656 enum i40e_status_code status;
4658 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4659 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4660 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4661 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4662 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4664 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4670 * i40e_aq_alternate_write_indirect
4671 * @hw: pointer to the hardware structure
4672 * @addr: address of a first register to be modified
4673 * @dw_count: number of alternate structure fields to write
4674 * @buffer: pointer to the command buffer
4676 * Write 'dw_count' dwords from 'buffer' to alternate structure
4677 * starting at 'addr'.
4680 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4681 u32 addr, u32 dw_count, void *buffer)
4683 struct i40e_aq_desc desc;
4684 struct i40e_aqc_alternate_ind_write *cmd_resp =
4685 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4686 enum i40e_status_code status;
4689 return I40E_ERR_PARAM;
4691 /* Indirect command */
4692 i40e_fill_default_direct_cmd_desc(&desc,
4693 i40e_aqc_opc_alternate_write_indirect);
4695 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4696 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4697 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4698 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4700 cmd_resp->address = CPU_TO_LE32(addr);
4701 cmd_resp->length = CPU_TO_LE32(dw_count);
4702 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4703 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4705 status = i40e_asq_send_command(hw, &desc, buffer,
4706 I40E_LO_DWORD(4*dw_count), NULL);
4712 * i40e_aq_alternate_read
4713 * @hw: pointer to the hardware structure
4714 * @reg_addr0: address of first dword to be read
4715 * @reg_val0: pointer for data read from 'reg_addr0'
4716 * @reg_addr1: address of second dword to be read
4717 * @reg_val1: pointer for data read from 'reg_addr1'
4719 * Read one or two dwords from alternate structure. Fields are indicated
4720 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4721 * is not passed then only register at 'reg_addr0' is read.
4724 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4725 u32 reg_addr0, u32 *reg_val0,
4726 u32 reg_addr1, u32 *reg_val1)
4728 struct i40e_aq_desc desc;
4729 struct i40e_aqc_alternate_write *cmd_resp =
4730 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4731 enum i40e_status_code status;
4733 if (reg_val0 == NULL)
4734 return I40E_ERR_PARAM;
4736 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4737 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4738 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4740 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4742 if (status == I40E_SUCCESS) {
4743 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4745 if (reg_val1 != NULL)
4746 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4753 * i40e_aq_alternate_read_indirect
4754 * @hw: pointer to the hardware structure
4755 * @addr: address of the alternate structure field
4756 * @dw_count: number of alternate structure fields to read
4757 * @buffer: pointer to the command buffer
4759 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4760 * place them in 'buffer'. The buffer should be allocated by caller.
4763 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4764 u32 addr, u32 dw_count, void *buffer)
4766 struct i40e_aq_desc desc;
4767 struct i40e_aqc_alternate_ind_write *cmd_resp =
4768 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4769 enum i40e_status_code status;
4772 return I40E_ERR_PARAM;
4774 /* Indirect command */
4775 i40e_fill_default_direct_cmd_desc(&desc,
4776 i40e_aqc_opc_alternate_read_indirect);
4778 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4779 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4780 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4781 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4783 cmd_resp->address = CPU_TO_LE32(addr);
4784 cmd_resp->length = CPU_TO_LE32(dw_count);
4785 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4786 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4788 status = i40e_asq_send_command(hw, &desc, buffer,
4789 I40E_LO_DWORD(4*dw_count), NULL);
4795 * i40e_aq_alternate_clear
4796 * @hw: pointer to the HW structure.
4798 * Clear the alternate structures of the port from which the function
4802 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
4804 struct i40e_aq_desc desc;
4805 enum i40e_status_code status;
4807 i40e_fill_default_direct_cmd_desc(&desc,
4808 i40e_aqc_opc_alternate_clear_port);
4810 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4816 * i40e_aq_alternate_write_done
4817 * @hw: pointer to the HW structure.
4818 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
4819 * @reset_needed: indicates the SW should trigger GLOBAL reset
4821 * Indicates to the FW that alternate structures have been changed.
4824 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
4825 u8 bios_mode, bool *reset_needed)
4827 struct i40e_aq_desc desc;
4828 struct i40e_aqc_alternate_write_done *cmd =
4829 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4830 enum i40e_status_code status;
4832 if (reset_needed == NULL)
4833 return I40E_ERR_PARAM;
4835 i40e_fill_default_direct_cmd_desc(&desc,
4836 i40e_aqc_opc_alternate_write_done);
4838 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
4840 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4841 if (!status && reset_needed)
4842 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
4843 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
4849 * i40e_aq_set_oem_mode
4850 * @hw: pointer to the HW structure.
4851 * @oem_mode: the OEM mode to be used
4853 * Sets the device to a specific operating mode. Currently the only supported
4854 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
4857 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
4860 struct i40e_aq_desc desc;
4861 struct i40e_aqc_alternate_write_done *cmd =
4862 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
4863 enum i40e_status_code status;
4865 i40e_fill_default_direct_cmd_desc(&desc,
4866 i40e_aqc_opc_alternate_set_mode);
4868 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
4870 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4876 * i40e_aq_resume_port_tx
4877 * @hw: pointer to the hardware structure
4878 * @cmd_details: pointer to command details structure or NULL
4880 * Resume port's Tx traffic
4882 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
4883 struct i40e_asq_cmd_details *cmd_details)
4885 struct i40e_aq_desc desc;
4886 enum i40e_status_code status;
4888 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4890 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4896 * i40e_set_pci_config_data - store PCI bus info
4897 * @hw: pointer to hardware structure
4898 * @link_status: the link status word from PCI config space
4900 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4902 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4904 hw->bus.type = i40e_bus_type_pci_express;
4906 switch (link_status & I40E_PCI_LINK_WIDTH) {
4907 case I40E_PCI_LINK_WIDTH_1:
4908 hw->bus.width = i40e_bus_width_pcie_x1;
4910 case I40E_PCI_LINK_WIDTH_2:
4911 hw->bus.width = i40e_bus_width_pcie_x2;
4913 case I40E_PCI_LINK_WIDTH_4:
4914 hw->bus.width = i40e_bus_width_pcie_x4;
4916 case I40E_PCI_LINK_WIDTH_8:
4917 hw->bus.width = i40e_bus_width_pcie_x8;
4920 hw->bus.width = i40e_bus_width_unknown;
4924 switch (link_status & I40E_PCI_LINK_SPEED) {
4925 case I40E_PCI_LINK_SPEED_2500:
4926 hw->bus.speed = i40e_bus_speed_2500;
4928 case I40E_PCI_LINK_SPEED_5000:
4929 hw->bus.speed = i40e_bus_speed_5000;
4931 case I40E_PCI_LINK_SPEED_8000:
4932 hw->bus.speed = i40e_bus_speed_8000;
4935 hw->bus.speed = i40e_bus_speed_unknown;
4941 * i40e_read_bw_from_alt_ram
4942 * @hw: pointer to the hardware structure
4943 * @max_bw: pointer for max_bw read
4944 * @min_bw: pointer for min_bw read
4945 * @min_valid: pointer for bool that is true if min_bw is a valid value
4946 * @max_valid: pointer for bool that is true if max_bw is a valid value
4948 * Read bw from the alternate ram for the given pf
4950 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4951 u32 *max_bw, u32 *min_bw,
4952 bool *min_valid, bool *max_valid)
4954 enum i40e_status_code status;
4955 u32 max_bw_addr, min_bw_addr;
4957 /* Calculate the address of the min/max bw registers */
4958 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4959 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4960 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4961 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4962 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4963 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
4965 /* Read the bandwidths from alt ram */
4966 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4967 min_bw_addr, min_bw);
4969 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4974 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4983 * i40e_aq_configure_partition_bw
4984 * @hw: pointer to the hardware structure
4985 * @bw_data: Buffer holding valid pfs and bw limits
4986 * @cmd_details: pointer to command details
4988 * Configure partitions guaranteed/max bw
4990 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4991 struct i40e_aqc_configure_partition_bw_data *bw_data,
4992 struct i40e_asq_cmd_details *cmd_details)
4994 enum i40e_status_code status;
4995 struct i40e_aq_desc desc;
4996 u16 bwd_size = sizeof(*bw_data);
4998 i40e_fill_default_direct_cmd_desc(&desc,
4999 i40e_aqc_opc_configure_partition_bw);
5001 /* Indirect command */
5002 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5005 if (bwd_size > I40E_AQ_LARGE_BUF)
5006 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5008 desc.datalen = CPU_TO_LE16(bwd_size);
5010 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5014 #endif /* PF_DRIVER */
5018 * i40e_aq_send_msg_to_pf
5019 * @hw: pointer to the hardware structure
5020 * @v_opcode: opcodes for VF-PF communication
5021 * @v_retval: return error code
5022 * @msg: pointer to the msg buffer
5023 * @msglen: msg length
5024 * @cmd_details: pointer to command details
5026 * Send message to PF driver using admin queue. By default, this message
5027 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5028 * completion before returning.
5030 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5031 enum i40e_virtchnl_ops v_opcode,
5032 enum i40e_status_code v_retval,
5033 u8 *msg, u16 msglen,
5034 struct i40e_asq_cmd_details *cmd_details)
5036 struct i40e_aq_desc desc;
5037 struct i40e_asq_cmd_details details;
5038 enum i40e_status_code status;
5040 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5041 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5042 desc.cookie_high = CPU_TO_LE32(v_opcode);
5043 desc.cookie_low = CPU_TO_LE32(v_retval);
5045 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5046 | I40E_AQ_FLAG_RD));
5047 if (msglen > I40E_AQ_LARGE_BUF)
5048 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5049 desc.datalen = CPU_TO_LE16(msglen);
5052 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5053 details.async = true;
5054 cmd_details = &details;
5056 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5057 msglen, cmd_details);
5062 * i40e_vf_parse_hw_config
5063 * @hw: pointer to the hardware structure
5064 * @msg: pointer to the virtual channel VF resource structure
5066 * Given a VF resource message from the PF, populate the hw struct
5067 * with appropriate information.
5069 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5070 struct i40e_virtchnl_vf_resource *msg)
5072 struct i40e_virtchnl_vsi_resource *vsi_res;
5075 vsi_res = &msg->vsi_res[0];
5077 hw->dev_caps.num_vsis = msg->num_vsis;
5078 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5079 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5080 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5081 hw->dev_caps.dcb = msg->vf_offload_flags &
5082 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5083 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5084 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5085 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5086 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5087 for (i = 0; i < msg->num_vsis; i++) {
5088 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5089 i40e_memcpy(hw->mac.perm_addr,
5090 vsi_res->default_mac_addr,
5091 I40E_ETH_LENGTH_OF_ADDRESS,
5092 I40E_NONDMA_TO_NONDMA);
5093 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5094 I40E_ETH_LENGTH_OF_ADDRESS,
5095 I40E_NONDMA_TO_NONDMA);
5103 * @hw: pointer to the hardware structure
5105 * Send a VF_RESET message to the PF. Does not wait for response from PF
5106 * as none will be forthcoming. Immediately after calling this function,
5107 * the admin queue should be shut down and (optionally) reinitialized.
5109 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5111 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5112 I40E_SUCCESS, NULL, 0, NULL);
5114 #endif /* VF_DRIVER */