drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90                 case I40E_DEV_ID_X722_VF_HV:
  91 #ifdef X722_A0_SUPPORT
  92                 case I40E_DEV_ID_X722_A0_VF:
  93 #endif
  94                         hw->mac.type = I40E_MAC_X722_VF;
  95                         break;
  96 #endif /* INTEGRATED_VF || VF_DRIVER */
  97 #endif /* X722_SUPPORT */
  98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  99                 case I40E_DEV_ID_VF:
 100                 case I40E_DEV_ID_VF_HV:
 101                         hw->mac.type = I40E_MAC_VF;
 102                         break;
 103 #endif
 104                 default:
 105                         hw->mac.type = I40E_MAC_GENERIC;
 106                         break;
 107                 }
 108         } else {
 109                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 110         }
 111
 112         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 113                   hw->mac.type, status);
 114         return status;
 115 }
 116
 117 #ifndef I40E_NDIS_SUPPORT
 118 /**
 119  * i40e_aq_str - convert AQ err code to a string
 120  * @hw: pointer to the HW structure
 121  * @aq_err: the AQ error code to convert
 122  **/
 123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 124 {
 125         switch (aq_err) {
 126         case I40E_AQ_RC_OK:
 127                 return "OK";
 128         case I40E_AQ_RC_EPERM:
 129                 return "I40E_AQ_RC_EPERM";
 130         case I40E_AQ_RC_ENOENT:
 131                 return "I40E_AQ_RC_ENOENT";
 132         case I40E_AQ_RC_ESRCH:
 133                 return "I40E_AQ_RC_ESRCH";
 134         case I40E_AQ_RC_EINTR:
 135                 return "I40E_AQ_RC_EINTR";
 136         case I40E_AQ_RC_EIO:
 137                 return "I40E_AQ_RC_EIO";
 138         case I40E_AQ_RC_ENXIO:
 139                 return "I40E_AQ_RC_ENXIO";
 140         case I40E_AQ_RC_E2BIG:
 141                 return "I40E_AQ_RC_E2BIG";
 142         case I40E_AQ_RC_EAGAIN:
 143                 return "I40E_AQ_RC_EAGAIN";
 144         case I40E_AQ_RC_ENOMEM:
 145                 return "I40E_AQ_RC_ENOMEM";
 146         case I40E_AQ_RC_EACCES:
 147                 return "I40E_AQ_RC_EACCES";
 148         case I40E_AQ_RC_EFAULT:
 149                 return "I40E_AQ_RC_EFAULT";
 150         case I40E_AQ_RC_EBUSY:
 151                 return "I40E_AQ_RC_EBUSY";
 152         case I40E_AQ_RC_EEXIST:
 153                 return "I40E_AQ_RC_EEXIST";
 154         case I40E_AQ_RC_EINVAL:
 155                 return "I40E_AQ_RC_EINVAL";
 156         case I40E_AQ_RC_ENOTTY:
 157                 return "I40E_AQ_RC_ENOTTY";
 158         case I40E_AQ_RC_ENOSPC:
 159                 return "I40E_AQ_RC_ENOSPC";
 160         case I40E_AQ_RC_ENOSYS:
 161                 return "I40E_AQ_RC_ENOSYS";
 162         case I40E_AQ_RC_ERANGE:
 163                 return "I40E_AQ_RC_ERANGE";
 164         case I40E_AQ_RC_EFLUSHED:
 165                 return "I40E_AQ_RC_EFLUSHED";
 166         case I40E_AQ_RC_BAD_ADDR:
 167                 return "I40E_AQ_RC_BAD_ADDR";
 168         case I40E_AQ_RC_EMODE:
 169                 return "I40E_AQ_RC_EMODE";
 170         case I40E_AQ_RC_EFBIG:
 171                 return "I40E_AQ_RC_EFBIG";
 172         }
 173
 174         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 175         return hw->err_str;
 176 }
 177
 178 /**
 179  * i40e_stat_str - convert status err code to a string
 180  * @hw: pointer to the HW structure
 181  * @stat_err: the status error code to convert
 182  **/
 183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 184 {
 185         switch (stat_err) {
 186         case I40E_SUCCESS:
 187                 return "OK";
 188         case I40E_ERR_NVM:
 189                 return "I40E_ERR_NVM";
 190         case I40E_ERR_NVM_CHECKSUM:
 191                 return "I40E_ERR_NVM_CHECKSUM";
 192         case I40E_ERR_PHY:
 193                 return "I40E_ERR_PHY";
 194         case I40E_ERR_CONFIG:
 195                 return "I40E_ERR_CONFIG";
 196         case I40E_ERR_PARAM:
 197                 return "I40E_ERR_PARAM";
 198         case I40E_ERR_MAC_TYPE:
 199                 return "I40E_ERR_MAC_TYPE";
 200         case I40E_ERR_UNKNOWN_PHY:
 201                 return "I40E_ERR_UNKNOWN_PHY";
 202         case I40E_ERR_LINK_SETUP:
 203                 return "I40E_ERR_LINK_SETUP";
 204         case I40E_ERR_ADAPTER_STOPPED:
 205                 return "I40E_ERR_ADAPTER_STOPPED";
 206         case I40E_ERR_INVALID_MAC_ADDR:
 207                 return "I40E_ERR_INVALID_MAC_ADDR";
 208         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 209                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 210         case I40E_ERR_MASTER_REQUESTS_PENDING:
 211                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 212         case I40E_ERR_INVALID_LINK_SETTINGS:
 213                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 214         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 215                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 216         case I40E_ERR_RESET_FAILED:
 217                 return "I40E_ERR_RESET_FAILED";
 218         case I40E_ERR_SWFW_SYNC:
 219                 return "I40E_ERR_SWFW_SYNC";
 220         case I40E_ERR_NO_AVAILABLE_VSI:
 221                 return "I40E_ERR_NO_AVAILABLE_VSI";
 222         case I40E_ERR_NO_MEMORY:
 223                 return "I40E_ERR_NO_MEMORY";
 224         case I40E_ERR_BAD_PTR:
 225                 return "I40E_ERR_BAD_PTR";
 226         case I40E_ERR_RING_FULL:
 227                 return "I40E_ERR_RING_FULL";
 228         case I40E_ERR_INVALID_PD_ID:
 229                 return "I40E_ERR_INVALID_PD_ID";
 230         case I40E_ERR_INVALID_QP_ID:
 231                 return "I40E_ERR_INVALID_QP_ID";
 232         case I40E_ERR_INVALID_CQ_ID:
 233                 return "I40E_ERR_INVALID_CQ_ID";
 234         case I40E_ERR_INVALID_CEQ_ID:
 235                 return "I40E_ERR_INVALID_CEQ_ID";
 236         case I40E_ERR_INVALID_AEQ_ID:
 237                 return "I40E_ERR_INVALID_AEQ_ID";
 238         case I40E_ERR_INVALID_SIZE:
 239                 return "I40E_ERR_INVALID_SIZE";
 240         case I40E_ERR_INVALID_ARP_INDEX:
 241                 return "I40E_ERR_INVALID_ARP_INDEX";
 242         case I40E_ERR_INVALID_FPM_FUNC_ID:
 243                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 244         case I40E_ERR_QP_INVALID_MSG_SIZE:
 245                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 246         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 247                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 248         case I40E_ERR_INVALID_FRAG_COUNT:
 249                 return "I40E_ERR_INVALID_FRAG_COUNT";
 250         case I40E_ERR_QUEUE_EMPTY:
 251                 return "I40E_ERR_QUEUE_EMPTY";
 252         case I40E_ERR_INVALID_ALIGNMENT:
 253                 return "I40E_ERR_INVALID_ALIGNMENT";
 254         case I40E_ERR_FLUSHED_QUEUE:
 255                 return "I40E_ERR_FLUSHED_QUEUE";
 256         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 257                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 258         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 259                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 260         case I40E_ERR_TIMEOUT:
 261                 return "I40E_ERR_TIMEOUT";
 262         case I40E_ERR_OPCODE_MISMATCH:
 263                 return "I40E_ERR_OPCODE_MISMATCH";
 264         case I40E_ERR_CQP_COMPL_ERROR:
 265                 return "I40E_ERR_CQP_COMPL_ERROR";
 266         case I40E_ERR_INVALID_VF_ID:
 267                 return "I40E_ERR_INVALID_VF_ID";
 268         case I40E_ERR_INVALID_HMCFN_ID:
 269                 return "I40E_ERR_INVALID_HMCFN_ID";
 270         case I40E_ERR_BACKING_PAGE_ERROR:
 271                 return "I40E_ERR_BACKING_PAGE_ERROR";
 272         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 273                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 274         case I40E_ERR_INVALID_PBLE_INDEX:
 275                 return "I40E_ERR_INVALID_PBLE_INDEX";
 276         case I40E_ERR_INVALID_SD_INDEX:
 277                 return "I40E_ERR_INVALID_SD_INDEX";
 278         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 279                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 280         case I40E_ERR_INVALID_SD_TYPE:
 281                 return "I40E_ERR_INVALID_SD_TYPE";
 282         case I40E_ERR_MEMCPY_FAILED:
 283                 return "I40E_ERR_MEMCPY_FAILED";
 284         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 285                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 286         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 287                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 288         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 289                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 290         case I40E_ERR_SRQ_ENABLED:
 291                 return "I40E_ERR_SRQ_ENABLED";
 292         case I40E_ERR_ADMIN_QUEUE_ERROR:
 293                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 294         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 295                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 296         case I40E_ERR_BUF_TOO_SHORT:
 297                 return "I40E_ERR_BUF_TOO_SHORT";
 298         case I40E_ERR_ADMIN_QUEUE_FULL:
 299                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 300         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 301                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 302         case I40E_ERR_BAD_IWARP_CQE:
 303                 return "I40E_ERR_BAD_IWARP_CQE";
 304         case I40E_ERR_NVM_BLANK_MODE:
 305                 return "I40E_ERR_NVM_BLANK_MODE";
 306         case I40E_ERR_NOT_IMPLEMENTED:
 307                 return "I40E_ERR_NOT_IMPLEMENTED";
 308         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 309                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 310         case I40E_ERR_DIAG_TEST_FAILED:
 311                 return "I40E_ERR_DIAG_TEST_FAILED";
 312         case I40E_ERR_NOT_READY:
 313                 return "I40E_ERR_NOT_READY";
 314         case I40E_NOT_SUPPORTED:
 315                 return "I40E_NOT_SUPPORTED";
 316         case I40E_ERR_FIRMWARE_API_VERSION:
 317                 return "I40E_ERR_FIRMWARE_API_VERSION";
 318         }
 319
 320         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 321         return hw->err_str;
 322 }
 323
 324 #endif /* I40E_NDIS_SUPPORT */
 325 /**
 326  * i40e_debug_aq
 327  * @hw: debug mask related to admin queue
 328  * @mask: debug mask
 329  * @desc: pointer to admin queue descriptor
 330  * @buffer: pointer to command buffer
 331  * @buf_len: max length of buffer
 332  *
 333  * Dumps debug log about adminq command with descriptor contents.
 334  **/
 335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 336                    void *buffer, u16 buf_len)
 337 {
 338         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 339         u16 len = LE16_TO_CPU(aq_desc->datalen);
 340         u8 *buf = (u8 *)buffer;
 341         u16 i = 0;
 342
 343         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 344                 return;
 345
 346         i40e_debug(hw, mask,
 347                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 348                    LE16_TO_CPU(aq_desc->opcode),
 349                    LE16_TO_CPU(aq_desc->flags),
 350                    LE16_TO_CPU(aq_desc->datalen),
 351                    LE16_TO_CPU(aq_desc->retval));
 352         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->cookie_high),
 354                    LE32_TO_CPU(aq_desc->cookie_low));
 355         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.internal.param0),
 357                    LE32_TO_CPU(aq_desc->params.internal.param1));
 358         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 359                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 360                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 361
 362         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 363                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 364                 if (buf_len < len)
 365                         len = buf_len;
 366                 /* write the full 16-byte chunks */
 367                 for (i = 0; i < (len - 16); i += 16)
 368                         i40e_debug(hw, mask,
 369                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 370                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 371                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 372                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 373                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 374                 /* the most we could have left is 16 bytes, pad with zeros */
 375                 if (i < len) {
 376                         char d_buf[16];
 377                         int j, i_sav;
 378
 379                         i_sav = i;
 380                         memset(d_buf, 0, sizeof(d_buf));
 381                         for (j = 0; i < len; j++, i++)
 382                                 d_buf[j] = buf[i];
 383                         i40e_debug(hw, mask,
 384                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 385                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 386                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 387                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 388                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 389                 }
 390         }
 391 }
 392
 393 /**
 394  * i40e_check_asq_alive
 395  * @hw: pointer to the hw struct
 396  *
 397  * Returns true if Queue is enabled else false.
 398  **/
 399 bool i40e_check_asq_alive(struct i40e_hw *hw)
 400 {
 401         if (hw->aq.asq.len)
 402 #ifdef PF_DRIVER
 403 #ifdef INTEGRATED_VF
 404                 if (!i40e_is_vf(hw))
 405                         return !!(rd32(hw, hw->aq.asq.len) &
 406                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 407 #else
 408                 return !!(rd32(hw, hw->aq.asq.len) &
 409                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 410 #endif /* INTEGRATED_VF */
 411 #endif /* PF_DRIVER */
 412 #ifdef VF_DRIVER
 413 #ifdef INTEGRATED_VF
 414                 if (i40e_is_vf(hw))
 415                         return !!(rd32(hw, hw->aq.asq.len) &
 416                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 417 #else
 418                 return !!(rd32(hw, hw->aq.asq.len) &
 419                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 420 #endif /* INTEGRATED_VF */
 421 #endif /* VF_DRIVER */
 422         return false;
 423 }
 424
 425 /**
 426  * i40e_aq_queue_shutdown
 427  * @hw: pointer to the hw struct
 428  * @unloading: is the driver unloading itself
 429  *
 430  * Tell the Firmware that we're shutting down the AdminQ and whether
 431  * or not the driver is unloading as well.
 432  **/
 433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 434                                              bool unloading)
 435 {
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_queue_shutdown *cmd =
 438                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 439         enum i40e_status_code status;
 440
 441         i40e_fill_default_direct_cmd_desc(&desc,
 442                                           i40e_aqc_opc_queue_shutdown);
 443
 444         if (unloading)
 445                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 446         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 447
 448         return status;
 449 }
 450 #ifdef X722_SUPPORT
 451
 452 /**
 453  * i40e_aq_get_set_rss_lut
 454  * @hw: pointer to the hardware structure
 455  * @vsi_id: vsi fw index
 456  * @pf_lut: for PF table set true, for VSI table set false
 457  * @lut: pointer to the lut buffer provided by the caller
 458  * @lut_size: size of the lut buffer
 459  * @set: set true to set the table, false to get the table
 460  *
 461  * Internal function to get or set RSS look up table
 462  **/
 463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 464                                                      u16 vsi_id, bool pf_lut,
 465                                                      u8 *lut, u16 lut_size,
 466                                                      bool set)
 467 {
 468         enum i40e_status_code status;
 469         struct i40e_aq_desc desc;
 470         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 471                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 472
 473         if (set)
 474                 i40e_fill_default_direct_cmd_desc(&desc,
 475                                                   i40e_aqc_opc_set_rss_lut);
 476         else
 477                 i40e_fill_default_direct_cmd_desc(&desc,
 478                                                   i40e_aqc_opc_get_rss_lut);
 479
 480         /* Indirect command */
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 482         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 483
 484         cmd_resp->vsi_id =
 485                         CPU_TO_LE16((u16)((vsi_id <<
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 487                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 488         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 489
 490         if (pf_lut)
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495         else
 496                 cmd_resp->flags |= CPU_TO_LE16((u16)
 497                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 499                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 500
 501         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 502
 503         return status;
 504 }
 505
 506 /**
 507  * i40e_aq_get_rss_lut
 508  * @hw: pointer to the hardware structure
 509  * @vsi_id: vsi fw index
 510  * @pf_lut: for PF table set true, for VSI table set false
 511  * @lut: pointer to the lut buffer provided by the caller
 512  * @lut_size: size of the lut buffer
 513  *
 514  * get the RSS lookup table, PF or VSI type
 515  **/
 516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 517                                           bool pf_lut, u8 *lut, u16 lut_size)
 518 {
 519         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 520                                        false);
 521 }
 522
 523 /**
 524  * i40e_aq_set_rss_lut
 525  * @hw: pointer to the hardware structure
 526  * @vsi_id: vsi fw index
 527  * @pf_lut: for PF table set true, for VSI table set false
 528  * @lut: pointer to the lut buffer provided by the caller
 529  * @lut_size: size of the lut buffer
 530  *
 531  * set the RSS lookup table, PF or VSI type
 532  **/
 533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 534                                           bool pf_lut, u8 *lut, u16 lut_size)
 535 {
 536         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 537 }
 538
 539 /**
 540  * i40e_aq_get_set_rss_key
 541  * @hw: pointer to the hw struct
 542  * @vsi_id: vsi fw index
 543  * @key: pointer to key info struct
 544  * @set: set true to set the key, false to get the key
 545  *
 546  * get the RSS key per VSI
 547  **/
 548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 549                                       u16 vsi_id,
 550                                       struct i40e_aqc_get_set_rss_key_data *key,
 551                                       bool set)
 552 {
 553         enum i40e_status_code status;
 554         struct i40e_aq_desc desc;
 555         struct i40e_aqc_get_set_rss_key *cmd_resp =
 556                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 557         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 558
 559         if (set)
 560                 i40e_fill_default_direct_cmd_desc(&desc,
 561                                                   i40e_aqc_opc_set_rss_key);
 562         else
 563                 i40e_fill_default_direct_cmd_desc(&desc,
 564                                                   i40e_aqc_opc_get_rss_key);
 565
 566         /* Indirect command */
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 568         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 569
 570         cmd_resp->vsi_id =
 571                         CPU_TO_LE16((u16)((vsi_id <<
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 573                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 574         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 575
 576         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 577
 578         return status;
 579 }
 580
 581 /**
 582  * i40e_aq_get_rss_key
 583  * @hw: pointer to the hw struct
 584  * @vsi_id: vsi fw index
 585  * @key: pointer to key info struct
 586  *
 587  **/
 588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 589                                       u16 vsi_id,
 590                                       struct i40e_aqc_get_set_rss_key_data *key)
 591 {
 592         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 593 }
 594
 595 /**
 596  * i40e_aq_set_rss_key
 597  * @hw: pointer to the hw struct
 598  * @vsi_id: vsi fw index
 599  * @key: pointer to key info struct
 600  *
 601  * set the RSS key per VSI
 602  **/
 603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 604                                       u16 vsi_id,
 605                                       struct i40e_aqc_get_set_rss_key_data *key)
 606 {
 607         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 608 }
 609 #endif /* X722_SUPPORT */
 610
 611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 612  * hardware to a bit-field that can be used by SW to more easily determine the
 613  * packet type.
 614  *
 615  * Macros are used to shorten the table lines and make this table human
 616  * readable.
 617  *
 618  * We store the PTYPE in the top byte of the bit field - this is just so that
 619  * we can check that the table doesn't have a row missing, as the index into
 620  * the table should be the PTYPE.
 621  *
 622  * Typical work flow:
 623  *
 624  * IF NOT i40e_ptype_lookup[ptype].known
 625  * THEN
 626  *      Packet is unknown
 627  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 628  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 629  * ELSE
 630  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 631  * ENDIF
 632  */
 633
 634 /* macro to make the table lines short */
 635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 636         {       PTYPE, \
 637                 1, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 639                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 640                 I40E_RX_PTYPE_##OUTER_FRAG, \
 641                 I40E_RX_PTYPE_TUNNEL_##T, \
 642                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 643                 I40E_RX_PTYPE_##TEF, \
 644                 I40E_RX_PTYPE_INNER_PROT_##I, \
 645                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 646
 647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 648                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 649
 650 /* shorter macros makes the table fit but are terse */
 651 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 652 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 653 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 654
 655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 657         /* L2 Packet types */
 658         I40E_PTT_UNUSED_ENTRY(0),
 659         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 661         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(4),
 663         I40E_PTT_UNUSED_ENTRY(5),
 664         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 666         I40E_PTT_UNUSED_ENTRY(8),
 667         I40E_PTT_UNUSED_ENTRY(9),
 668         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 669         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 670         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 680
 681         /* Non Tunneled IPv4 */
 682         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 684         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 685         I40E_PTT_UNUSED_ENTRY(25),
 686         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 687         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 688         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 689
 690         /* IPv4 --> IPv4 */
 691         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 692         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 693         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 694         I40E_PTT_UNUSED_ENTRY(32),
 695         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 696         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 697         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 698
 699         /* IPv4 --> IPv6 */
 700         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 701         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 702         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 703         I40E_PTT_UNUSED_ENTRY(39),
 704         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 705         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 706         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 707
 708         /* IPv4 --> GRE/NAT */
 709         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 710
 711         /* IPv4 --> GRE/NAT --> IPv4 */
 712         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 713         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 714         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 715         I40E_PTT_UNUSED_ENTRY(47),
 716         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 717         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 718         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 719
 720         /* IPv4 --> GRE/NAT --> IPv6 */
 721         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 722         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 723         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 724         I40E_PTT_UNUSED_ENTRY(54),
 725         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 726         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 727         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 728
 729         /* IPv4 --> GRE/NAT --> MAC */
 730         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 731
 732         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 733         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 734         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 735         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 736         I40E_PTT_UNUSED_ENTRY(62),
 737         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 738         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 739         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 740
 741         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 742         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 743         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 744         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 745         I40E_PTT_UNUSED_ENTRY(69),
 746         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 747         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 748         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 749
 750         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 751         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 752
 753         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 754         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(77),
 758         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 763         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(84),
 767         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 770
 771         /* Non Tunneled IPv6 */
 772         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 774         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 775         I40E_PTT_UNUSED_ENTRY(91),
 776         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 777         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 778         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 779
 780         /* IPv6 --> IPv4 */
 781         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 782         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 783         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 784         I40E_PTT_UNUSED_ENTRY(98),
 785         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 786         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 787         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 788
 789         /* IPv6 --> IPv6 */
 790         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 791         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 792         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 793         I40E_PTT_UNUSED_ENTRY(105),
 794         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 795         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 796         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 797
 798         /* IPv6 --> GRE/NAT */
 799         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 800
 801         /* IPv6 --> GRE/NAT -> IPv4 */
 802         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 803         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 804         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 805         I40E_PTT_UNUSED_ENTRY(113),
 806         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 807         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 808         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 809
 810         /* IPv6 --> GRE/NAT -> IPv6 */
 811         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 812         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 813         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 814         I40E_PTT_UNUSED_ENTRY(120),
 815         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 816         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 817         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 818
 819         /* IPv6 --> GRE/NAT -> MAC */
 820         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 821
 822         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 823         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 824         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 825         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 826         I40E_PTT_UNUSED_ENTRY(128),
 827         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 828         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 829         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 830
 831         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 832         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 833         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 834         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 835         I40E_PTT_UNUSED_ENTRY(135),
 836         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 837         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 838         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 839
 840         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 841         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 842
 843         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 844         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 845         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 846         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 847         I40E_PTT_UNUSED_ENTRY(143),
 848         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 849         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 850         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 851
 852         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 853         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 854         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 855         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 856         I40E_PTT_UNUSED_ENTRY(150),
 857         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 858         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 859         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 860
 861         /* unused entries */
 862         I40E_PTT_UNUSED_ENTRY(154),
 863         I40E_PTT_UNUSED_ENTRY(155),
 864         I40E_PTT_UNUSED_ENTRY(156),
 865         I40E_PTT_UNUSED_ENTRY(157),
 866         I40E_PTT_UNUSED_ENTRY(158),
 867         I40E_PTT_UNUSED_ENTRY(159),
 868
 869         I40E_PTT_UNUSED_ENTRY(160),
 870         I40E_PTT_UNUSED_ENTRY(161),
 871         I40E_PTT_UNUSED_ENTRY(162),
 872         I40E_PTT_UNUSED_ENTRY(163),
 873         I40E_PTT_UNUSED_ENTRY(164),
 874         I40E_PTT_UNUSED_ENTRY(165),
 875         I40E_PTT_UNUSED_ENTRY(166),
 876         I40E_PTT_UNUSED_ENTRY(167),
 877         I40E_PTT_UNUSED_ENTRY(168),
 878         I40E_PTT_UNUSED_ENTRY(169),
 879
 880         I40E_PTT_UNUSED_ENTRY(170),
 881         I40E_PTT_UNUSED_ENTRY(171),
 882         I40E_PTT_UNUSED_ENTRY(172),
 883         I40E_PTT_UNUSED_ENTRY(173),
 884         I40E_PTT_UNUSED_ENTRY(174),
 885         I40E_PTT_UNUSED_ENTRY(175),
 886         I40E_PTT_UNUSED_ENTRY(176),
 887         I40E_PTT_UNUSED_ENTRY(177),
 888         I40E_PTT_UNUSED_ENTRY(178),
 889         I40E_PTT_UNUSED_ENTRY(179),
 890
 891         I40E_PTT_UNUSED_ENTRY(180),
 892         I40E_PTT_UNUSED_ENTRY(181),
 893         I40E_PTT_UNUSED_ENTRY(182),
 894         I40E_PTT_UNUSED_ENTRY(183),
 895         I40E_PTT_UNUSED_ENTRY(184),
 896         I40E_PTT_UNUSED_ENTRY(185),
 897         I40E_PTT_UNUSED_ENTRY(186),
 898         I40E_PTT_UNUSED_ENTRY(187),
 899         I40E_PTT_UNUSED_ENTRY(188),
 900         I40E_PTT_UNUSED_ENTRY(189),
 901
 902         I40E_PTT_UNUSED_ENTRY(190),
 903         I40E_PTT_UNUSED_ENTRY(191),
 904         I40E_PTT_UNUSED_ENTRY(192),
 905         I40E_PTT_UNUSED_ENTRY(193),
 906         I40E_PTT_UNUSED_ENTRY(194),
 907         I40E_PTT_UNUSED_ENTRY(195),
 908         I40E_PTT_UNUSED_ENTRY(196),
 909         I40E_PTT_UNUSED_ENTRY(197),
 910         I40E_PTT_UNUSED_ENTRY(198),
 911         I40E_PTT_UNUSED_ENTRY(199),
 912
 913         I40E_PTT_UNUSED_ENTRY(200),
 914         I40E_PTT_UNUSED_ENTRY(201),
 915         I40E_PTT_UNUSED_ENTRY(202),
 916         I40E_PTT_UNUSED_ENTRY(203),
 917         I40E_PTT_UNUSED_ENTRY(204),
 918         I40E_PTT_UNUSED_ENTRY(205),
 919         I40E_PTT_UNUSED_ENTRY(206),
 920         I40E_PTT_UNUSED_ENTRY(207),
 921         I40E_PTT_UNUSED_ENTRY(208),
 922         I40E_PTT_UNUSED_ENTRY(209),
 923
 924         I40E_PTT_UNUSED_ENTRY(210),
 925         I40E_PTT_UNUSED_ENTRY(211),
 926         I40E_PTT_UNUSED_ENTRY(212),
 927         I40E_PTT_UNUSED_ENTRY(213),
 928         I40E_PTT_UNUSED_ENTRY(214),
 929         I40E_PTT_UNUSED_ENTRY(215),
 930         I40E_PTT_UNUSED_ENTRY(216),
 931         I40E_PTT_UNUSED_ENTRY(217),
 932         I40E_PTT_UNUSED_ENTRY(218),
 933         I40E_PTT_UNUSED_ENTRY(219),
 934
 935         I40E_PTT_UNUSED_ENTRY(220),
 936         I40E_PTT_UNUSED_ENTRY(221),
 937         I40E_PTT_UNUSED_ENTRY(222),
 938         I40E_PTT_UNUSED_ENTRY(223),
 939         I40E_PTT_UNUSED_ENTRY(224),
 940         I40E_PTT_UNUSED_ENTRY(225),
 941         I40E_PTT_UNUSED_ENTRY(226),
 942         I40E_PTT_UNUSED_ENTRY(227),
 943         I40E_PTT_UNUSED_ENTRY(228),
 944         I40E_PTT_UNUSED_ENTRY(229),
 945
 946         I40E_PTT_UNUSED_ENTRY(230),
 947         I40E_PTT_UNUSED_ENTRY(231),
 948         I40E_PTT_UNUSED_ENTRY(232),
 949         I40E_PTT_UNUSED_ENTRY(233),
 950         I40E_PTT_UNUSED_ENTRY(234),
 951         I40E_PTT_UNUSED_ENTRY(235),
 952         I40E_PTT_UNUSED_ENTRY(236),
 953         I40E_PTT_UNUSED_ENTRY(237),
 954         I40E_PTT_UNUSED_ENTRY(238),
 955         I40E_PTT_UNUSED_ENTRY(239),
 956
 957         I40E_PTT_UNUSED_ENTRY(240),
 958         I40E_PTT_UNUSED_ENTRY(241),
 959         I40E_PTT_UNUSED_ENTRY(242),
 960         I40E_PTT_UNUSED_ENTRY(243),
 961         I40E_PTT_UNUSED_ENTRY(244),
 962         I40E_PTT_UNUSED_ENTRY(245),
 963         I40E_PTT_UNUSED_ENTRY(246),
 964         I40E_PTT_UNUSED_ENTRY(247),
 965         I40E_PTT_UNUSED_ENTRY(248),
 966         I40E_PTT_UNUSED_ENTRY(249),
 967
 968         I40E_PTT_UNUSED_ENTRY(250),
 969         I40E_PTT_UNUSED_ENTRY(251),
 970         I40E_PTT_UNUSED_ENTRY(252),
 971         I40E_PTT_UNUSED_ENTRY(253),
 972         I40E_PTT_UNUSED_ENTRY(254),
 973         I40E_PTT_UNUSED_ENTRY(255)
 974 };
 975
 976
 977 /**
 978  * i40e_validate_mac_addr - Validate unicast MAC address
 979  * @mac_addr: pointer to MAC address
 980  *
 981  * Tests a MAC address to ensure it is a valid Individual Address
 982  **/
 983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 984 {
 985         enum i40e_status_code status = I40E_SUCCESS;
 986
 987         DEBUGFUNC("i40e_validate_mac_addr");
 988
 989         /* Broadcast addresses ARE multicast addresses
 990          * Make sure it is not a multicast address
 991          * Reject the zero address
 992          */
 993         if (I40E_IS_MULTICAST(mac_addr) ||
 994             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 995               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 996                 status = I40E_ERR_INVALID_MAC_ADDR;
 997
 998         return status;
 999 }
1000 #ifdef PF_DRIVER
1001
1002 /**
1003  * i40e_init_shared_code - Initialize the shared code
1004  * @hw: pointer to hardware structure
1005  *
1006  * This assigns the MAC type and PHY code and inits the NVM.
1007  * Does not touch the hardware. This function must be called prior to any
1008  * other function in the shared code. The i40e_hw structure should be
1009  * memset to 0 prior to calling this function.  The following fields in
1010  * hw structure should be filled in prior to calling this function:
1011  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012  * subsystem_vendor_id, and revision_id
1013  **/
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 {
1016         enum i40e_status_code status = I40E_SUCCESS;
1017         u32 port, ari, func_rid;
1018
1019         DEBUGFUNC("i40e_init_shared_code");
1020
1021         i40e_set_mac_type(hw);
1022
1023         switch (hw->mac.type) {
1024         case I40E_MAC_XL710:
1025 #ifdef X722_SUPPORT
1026         case I40E_MAC_X722:
1027 #endif
1028                 break;
1029         default:
1030                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1031         }
1032
1033         hw->phy.get_link_info = true;
1034
1035         /* Determine port number and PF number*/
1036         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038         hw->port = (u8)port;
1039         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042         if (ari)
1043                 hw->pf_id = (u8)(func_rid & 0xff);
1044         else
1045                 hw->pf_id = (u8)(func_rid & 0x7);
1046
1047 #ifdef X722_SUPPORT
1048         if (hw->mac.type == I40E_MAC_X722)
1049                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1050
1051 #endif
1052         status = i40e_init_nvm(hw);
1053         return status;
1054 }
1055
1056 /**
1057  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058  * @hw: pointer to the hw struct
1059  * @flags: a return indicator of what addresses were added to the addr store
1060  * @addrs: the requestor's mac addr store
1061  * @cmd_details: pointer to command details structure or NULL
1062  **/
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064                                    u16 *flags,
1065                                    struct i40e_aqc_mac_address_read_data *addrs,
1066                                    struct i40e_asq_cmd_details *cmd_details)
1067 {
1068         struct i40e_aq_desc desc;
1069         struct i40e_aqc_mac_address_read *cmd_data =
1070                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071         enum i40e_status_code status;
1072
1073         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075
1076         status = i40e_asq_send_command(hw, &desc, addrs,
1077                                        sizeof(*addrs), cmd_details);
1078         *flags = LE16_TO_CPU(cmd_data->command_flags);
1079
1080         return status;
1081 }
1082
1083 /**
1084  * i40e_aq_mac_address_write - Change the MAC addresses
1085  * @hw: pointer to the hw struct
1086  * @flags: indicates which MAC to be written
1087  * @mac_addr: address to write
1088  * @cmd_details: pointer to command details structure or NULL
1089  **/
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091                                     u16 flags, u8 *mac_addr,
1092                                     struct i40e_asq_cmd_details *cmd_details)
1093 {
1094         struct i40e_aq_desc desc;
1095         struct i40e_aqc_mac_address_write *cmd_data =
1096                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097         enum i40e_status_code status;
1098
1099         i40e_fill_default_direct_cmd_desc(&desc,
1100                                           i40e_aqc_opc_mac_address_write);
1101         cmd_data->command_flags = CPU_TO_LE16(flags);
1102         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104                                         ((u32)mac_addr[3] << 16) |
1105                                         ((u32)mac_addr[4] << 8) |
1106                                         mac_addr[5]);
1107
1108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1109
1110         return status;
1111 }
1112
1113 /**
1114  * i40e_get_mac_addr - get MAC address
1115  * @hw: pointer to the HW structure
1116  * @mac_addr: pointer to MAC address
1117  *
1118  * Reads the adapter's MAC address from register
1119  **/
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 {
1122         struct i40e_aqc_mac_address_read_data addrs;
1123         enum i40e_status_code status;
1124         u16 flags = 0;
1125
1126         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127
1128         if (flags & I40E_AQC_LAN_ADDR_VALID)
1129                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1130
1131         return status;
1132 }
1133
1134 /**
1135  * i40e_get_port_mac_addr - get Port MAC address
1136  * @hw: pointer to the HW structure
1137  * @mac_addr: pointer to Port MAC address
1138  *
1139  * Reads the adapter's Port MAC address
1140  **/
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1142 {
1143         struct i40e_aqc_mac_address_read_data addrs;
1144         enum i40e_status_code status;
1145         u16 flags = 0;
1146
1147         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1148         if (status)
1149                 return status;
1150
1151         if (flags & I40E_AQC_PORT_ADDR_VALID)
1152                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1153         else
1154                 status = I40E_ERR_INVALID_MAC_ADDR;
1155
1156         return status;
1157 }
1158
1159 /**
1160  * i40e_pre_tx_queue_cfg - pre tx queue configure
1161  * @hw: pointer to the HW structure
1162  * @queue: target pf queue index
1163  * @enable: state change request
1164  *
1165  * Handles hw requirement to indicate intention to enable
1166  * or disable target queue.
1167  **/
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1169 {
1170         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1171         u32 reg_block = 0;
1172         u32 reg_val;
1173
1174         if (abs_queue_idx >= 128) {
1175                 reg_block = abs_queue_idx / 128;
1176                 abs_queue_idx %= 128;
1177         }
1178
1179         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1182
1183         if (enable)
1184                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1185         else
1186                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1187
1188         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1189 }
1190
1191 /**
1192  *  i40e_read_pba_string - Reads part number string from EEPROM
1193  *  @hw: pointer to hardware structure
1194  *  @pba_num: stores the part number string from the EEPROM
1195  *  @pba_num_size: part number string buffer length
1196  *
1197  *  Reads the part number string from the EEPROM.
1198  **/
1199 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1200                                             u32 pba_num_size)
1201 {
1202         enum i40e_status_code status = I40E_SUCCESS;
1203         u16 pba_word = 0;
1204         u16 pba_size = 0;
1205         u16 pba_ptr = 0;
1206         u16 i = 0;
1207
1208         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1209         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1210                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1211                 return status;
1212         }
1213
1214         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1215         if (status != I40E_SUCCESS) {
1216                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1217                 return status;
1218         }
1219
1220         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1221         if (status != I40E_SUCCESS) {
1222                 DEBUGOUT("Failed to read PBA Block size.\n");
1223                 return status;
1224         }
1225
1226         /* Subtract one to get PBA word count (PBA Size word is included in
1227          * total size)
1228          */
1229         pba_size--;
1230         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1231                 DEBUGOUT("Buffer to small for PBA data.\n");
1232                 return I40E_ERR_PARAM;
1233         }
1234
1235         for (i = 0; i < pba_size; i++) {
1236                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1237                 if (status != I40E_SUCCESS) {
1238                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1239                         return status;
1240                 }
1241
1242                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1243                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1244         }
1245         pba_num[(pba_size * 2)] = '\0';
1246
1247         return status;
1248 }
1249
1250 /**
1251  * i40e_get_media_type - Gets media type
1252  * @hw: pointer to the hardware structure
1253  **/
1254 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1255 {
1256         enum i40e_media_type media;
1257
1258         switch (hw->phy.link_info.phy_type) {
1259         case I40E_PHY_TYPE_10GBASE_SR:
1260         case I40E_PHY_TYPE_10GBASE_LR:
1261         case I40E_PHY_TYPE_1000BASE_SX:
1262         case I40E_PHY_TYPE_1000BASE_LX:
1263         case I40E_PHY_TYPE_40GBASE_SR4:
1264         case I40E_PHY_TYPE_40GBASE_LR4:
1265                 media = I40E_MEDIA_TYPE_FIBER;
1266                 break;
1267         case I40E_PHY_TYPE_100BASE_TX:
1268         case I40E_PHY_TYPE_1000BASE_T:
1269         case I40E_PHY_TYPE_10GBASE_T:
1270                 media = I40E_MEDIA_TYPE_BASET;
1271                 break;
1272         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1273         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1274         case I40E_PHY_TYPE_10GBASE_CR1:
1275         case I40E_PHY_TYPE_40GBASE_CR4:
1276         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1277         case I40E_PHY_TYPE_40GBASE_AOC:
1278         case I40E_PHY_TYPE_10GBASE_AOC:
1279                 media = I40E_MEDIA_TYPE_DA;
1280                 break;
1281         case I40E_PHY_TYPE_1000BASE_KX:
1282         case I40E_PHY_TYPE_10GBASE_KX4:
1283         case I40E_PHY_TYPE_10GBASE_KR:
1284         case I40E_PHY_TYPE_40GBASE_KR4:
1285         case I40E_PHY_TYPE_20GBASE_KR2:
1286                 media = I40E_MEDIA_TYPE_BACKPLANE;
1287                 break;
1288         case I40E_PHY_TYPE_SGMII:
1289         case I40E_PHY_TYPE_XAUI:
1290         case I40E_PHY_TYPE_XFI:
1291         case I40E_PHY_TYPE_XLAUI:
1292         case I40E_PHY_TYPE_XLPPI:
1293         default:
1294                 media = I40E_MEDIA_TYPE_UNKNOWN;
1295                 break;
1296         }
1297
1298         return media;
1299 }
1300
1301 #define I40E_PF_RESET_WAIT_COUNT        200
1302 /**
1303  * i40e_pf_reset - Reset the PF
1304  * @hw: pointer to the hardware structure
1305  *
1306  * Assuming someone else has triggered a global reset,
1307  * assure the global reset is complete and then reset the PF
1308  **/
1309 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1310 {
1311         u32 cnt = 0;
1312         u32 cnt1 = 0;
1313         u32 reg = 0;
1314         u32 grst_del;
1315
1316         /* Poll for Global Reset steady state in case of recent GRST.
1317          * The grst delay value is in 100ms units, and we'll wait a
1318          * couple counts longer to be sure we don't just miss the end.
1319          */
1320         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1321                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1322                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1323
1324         grst_del = grst_del * 20;
1325
1326         for (cnt = 0; cnt < grst_del; cnt++) {
1327                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1328                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1329                         break;
1330                 i40e_msec_delay(100);
1331         }
1332         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1333                 DEBUGOUT("Global reset polling failed to complete.\n");
1334                 return I40E_ERR_RESET_FAILED;
1335         }
1336
1337         /* Now Wait for the FW to be ready */
1338         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1339                 reg = rd32(hw, I40E_GLNVM_ULD);
1340                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1341                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1342                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1343                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1344                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1345                         break;
1346                 }
1347                 i40e_msec_delay(10);
1348         }
1349         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1350                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1351                 DEBUGOUT("wait for FW Reset complete timedout\n");
1352                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1353                 return I40E_ERR_RESET_FAILED;
1354         }
1355
1356         /* If there was a Global Reset in progress when we got here,
1357          * we don't need to do the PF Reset
1358          */
1359         if (!cnt) {
1360                 reg = rd32(hw, I40E_PFGEN_CTRL);
1361                 wr32(hw, I40E_PFGEN_CTRL,
1362                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1363                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1364                         reg = rd32(hw, I40E_PFGEN_CTRL);
1365                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1366                                 break;
1367                         i40e_msec_delay(1);
1368                 }
1369                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1370                         DEBUGOUT("PF reset polling failed to complete.\n");
1371                         return I40E_ERR_RESET_FAILED;
1372                 }
1373         }
1374
1375         i40e_clear_pxe_mode(hw);
1376
1377
1378         return I40E_SUCCESS;
1379 }
1380
1381 /**
1382  * i40e_clear_hw - clear out any left over hw state
1383  * @hw: pointer to the hw struct
1384  *
1385  * Clear queues and interrupts, typically called at init time,
1386  * but after the capabilities have been found so we know how many
1387  * queues and msix vectors have been allocated.
1388  **/
1389 void i40e_clear_hw(struct i40e_hw *hw)
1390 {
1391         u32 num_queues, base_queue;
1392         u32 num_pf_int;
1393         u32 num_vf_int;
1394         u32 num_vfs;
1395         u32 i, j;
1396         u32 val;
1397         u32 eol = 0x7ff;
1398
1399         /* get number of interrupts, queues, and vfs */
1400         val = rd32(hw, I40E_GLPCI_CNF2);
1401         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1402                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1403         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1404                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1405
1406         val = rd32(hw, I40E_PFLAN_QALLOC);
1407         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1408                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1409         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1410                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1411         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1412                 num_queues = (j - base_queue) + 1;
1413         else
1414                 num_queues = 0;
1415
1416         val = rd32(hw, I40E_PF_VT_PFALLOC);
1417         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1418                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1419         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1420                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1421         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1422                 num_vfs = (j - i) + 1;
1423         else
1424                 num_vfs = 0;
1425
1426         /* stop all the interrupts */
1427         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1428         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1429         for (i = 0; i < num_pf_int - 2; i++)
1430                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1431
1432         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1433         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1434         wr32(hw, I40E_PFINT_LNKLST0, val);
1435         for (i = 0; i < num_pf_int - 2; i++)
1436                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1437         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1438         for (i = 0; i < num_vfs; i++)
1439                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1440         for (i = 0; i < num_vf_int - 2; i++)
1441                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1442
1443         /* warn the HW of the coming Tx disables */
1444         for (i = 0; i < num_queues; i++) {
1445                 u32 abs_queue_idx = base_queue + i;
1446                 u32 reg_block = 0;
1447
1448                 if (abs_queue_idx >= 128) {
1449                         reg_block = abs_queue_idx / 128;
1450                         abs_queue_idx %= 128;
1451                 }
1452
1453                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1454                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1455                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1456                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1457
1458                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1459         }
1460         i40e_usec_delay(400);
1461
1462         /* stop all the queues */
1463         for (i = 0; i < num_queues; i++) {
1464                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1465                 wr32(hw, I40E_QTX_ENA(i), 0);
1466                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1467                 wr32(hw, I40E_QRX_ENA(i), 0);
1468         }
1469
1470         /* short wait for all queue disables to settle */
1471         i40e_usec_delay(50);
1472 }
1473
1474 /**
1475  * i40e_clear_pxe_mode - clear pxe operations mode
1476  * @hw: pointer to the hw struct
1477  *
1478  * Make sure all PXE mode settings are cleared, including things
1479  * like descriptor fetch/write-back mode.
1480  **/
1481 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1482 {
1483         if (i40e_check_asq_alive(hw))
1484                 i40e_aq_clear_pxe_mode(hw, NULL);
1485 }
1486
1487 /**
1488  * i40e_led_is_mine - helper to find matching led
1489  * @hw: pointer to the hw struct
1490  * @idx: index into GPIO registers
1491  *
1492  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1493  */
1494 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1495 {
1496         u32 gpio_val = 0;
1497         u32 port;
1498
1499         if (!hw->func_caps.led[idx])
1500                 return 0;
1501
1502         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1503         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1504                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1505
1506         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1507          * if it is not our port then ignore
1508          */
1509         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1510             (port != hw->port))
1511                 return 0;
1512
1513         return gpio_val;
1514 }
1515
1516 #define I40E_COMBINED_ACTIVITY 0xA
1517 #define I40E_FILTER_ACTIVITY 0xE
1518 #define I40E_LINK_ACTIVITY 0xC
1519 #define I40E_MAC_ACTIVITY 0xD
1520 #define I40E_LED0 22
1521
1522 /**
1523  * i40e_led_get - return current on/off mode
1524  * @hw: pointer to the hw struct
1525  *
1526  * The value returned is the 'mode' field as defined in the
1527  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1528  * values are variations of possible behaviors relating to
1529  * blink, link, and wire.
1530  **/
1531 u32 i40e_led_get(struct i40e_hw *hw)
1532 {
1533         u32 current_mode = 0;
1534         u32 mode = 0;
1535         int i;
1536
1537         /* as per the documentation GPIO 22-29 are the LED
1538          * GPIO pins named LED0..LED7
1539          */
1540         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1541                 u32 gpio_val = i40e_led_is_mine(hw, i);
1542
1543                 if (!gpio_val)
1544                         continue;
1545
1546                 /* ignore gpio LED src mode entries related to the activity
1547                  *  LEDs
1548                  */
1549                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1550                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1551                 switch (current_mode) {
1552                 case I40E_COMBINED_ACTIVITY:
1553                 case I40E_FILTER_ACTIVITY:
1554                 case I40E_MAC_ACTIVITY:
1555                         continue;
1556                 default:
1557                         break;
1558                 }
1559
1560                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1561                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1562                 break;
1563         }
1564
1565         return mode;
1566 }
1567
1568 /**
1569  * i40e_led_set - set new on/off mode
1570  * @hw: pointer to the hw struct
1571  * @mode: 0=off, 0xf=on (else see manual for mode details)
1572  * @blink: true if the LED should blink when on, false if steady
1573  *
1574  * if this function is used to turn on the blink it should
1575  * be used to disable the blink when restoring the original state.
1576  **/
1577 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1578 {
1579         u32 current_mode = 0;
1580         int i;
1581
1582         if (mode & 0xfffffff0)
1583                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1584
1585         /* as per the documentation GPIO 22-29 are the LED
1586          * GPIO pins named LED0..LED7
1587          */
1588         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1589                 u32 gpio_val = i40e_led_is_mine(hw, i);
1590
1591                 if (!gpio_val)
1592                         continue;
1593
1594                 /* ignore gpio LED src mode entries related to the activity
1595                  * LEDs
1596                  */
1597                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1598                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1599                 switch (current_mode) {
1600                 case I40E_COMBINED_ACTIVITY:
1601                 case I40E_FILTER_ACTIVITY:
1602                 case I40E_MAC_ACTIVITY:
1603                         continue;
1604                 default:
1605                         break;
1606                 }
1607
1608                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1609                 /* this & is a bit of paranoia, but serves as a range check */
1610                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1611                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1612
1613                 if (mode == I40E_LINK_ACTIVITY)
1614                         blink = false;
1615
1616                 if (blink)
1617                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1618                 else
1619                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1620
1621                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1622                 break;
1623         }
1624 }
1625
1626 /* Admin command wrappers */
1627
1628 /**
1629  * i40e_aq_get_phy_capabilities
1630  * @hw: pointer to the hw struct
1631  * @abilities: structure for PHY capabilities to be filled
1632  * @qualified_modules: report Qualified Modules
1633  * @report_init: report init capabilities (active are default)
1634  * @cmd_details: pointer to command details structure or NULL
1635  *
1636  * Returns the various PHY abilities supported on the Port.
1637  **/
1638 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1639                         bool qualified_modules, bool report_init,
1640                         struct i40e_aq_get_phy_abilities_resp *abilities,
1641                         struct i40e_asq_cmd_details *cmd_details)
1642 {
1643         struct i40e_aq_desc desc;
1644         enum i40e_status_code status;
1645         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1646
1647         if (!abilities)
1648                 return I40E_ERR_PARAM;
1649
1650         i40e_fill_default_direct_cmd_desc(&desc,
1651                                           i40e_aqc_opc_get_phy_abilities);
1652
1653         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1654         if (abilities_size > I40E_AQ_LARGE_BUF)
1655                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1656
1657         if (qualified_modules)
1658                 desc.params.external.param0 |=
1659                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1660
1661         if (report_init)
1662                 desc.params.external.param0 |=
1663                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1664
1665         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1666                                     cmd_details);
1667
1668         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1669                 status = I40E_ERR_UNKNOWN_PHY;
1670
1671         if (report_init) {
1672                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1673                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1674         }
1675
1676         return status;
1677 }
1678
1679 /**
1680  * i40e_aq_set_phy_config
1681  * @hw: pointer to the hw struct
1682  * @config: structure with PHY configuration to be set
1683  * @cmd_details: pointer to command details structure or NULL
1684  *
1685  * Set the various PHY configuration parameters
1686  * supported on the Port.One or more of the Set PHY config parameters may be
1687  * ignored in an MFP mode as the PF may not have the privilege to set some
1688  * of the PHY Config parameters. This status will be indicated by the
1689  * command response.
1690  **/
1691 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1692                                 struct i40e_aq_set_phy_config *config,
1693                                 struct i40e_asq_cmd_details *cmd_details)
1694 {
1695         struct i40e_aq_desc desc;
1696         struct i40e_aq_set_phy_config *cmd =
1697                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1698         enum i40e_status_code status;
1699
1700         if (!config)
1701                 return I40E_ERR_PARAM;
1702
1703         i40e_fill_default_direct_cmd_desc(&desc,
1704                                           i40e_aqc_opc_set_phy_config);
1705
1706         *cmd = *config;
1707
1708         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1709
1710         return status;
1711 }
1712
1713 /**
1714  * i40e_set_fc
1715  * @hw: pointer to the hw struct
1716  *
1717  * Set the requested flow control mode using set_phy_config.
1718  **/
1719 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1720                                   bool atomic_restart)
1721 {
1722         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1723         struct i40e_aq_get_phy_abilities_resp abilities;
1724         struct i40e_aq_set_phy_config config;
1725         enum i40e_status_code status;
1726         u8 pause_mask = 0x0;
1727
1728         *aq_failures = 0x0;
1729
1730         switch (fc_mode) {
1731         case I40E_FC_FULL:
1732                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1733                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1734                 break;
1735         case I40E_FC_RX_PAUSE:
1736                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1737                 break;
1738         case I40E_FC_TX_PAUSE:
1739                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1740                 break;
1741         default:
1742                 break;
1743         }
1744
1745         /* Get the current phy config */
1746         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1747                                               NULL);
1748         if (status) {
1749                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1750                 return status;
1751         }
1752
1753         memset(&config, 0, sizeof(config));
1754         /* clear the old pause settings */
1755         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1756                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1757         /* set the new abilities */
1758         config.abilities |= pause_mask;
1759         /* If the abilities have changed, then set the new config */
1760         if (config.abilities != abilities.abilities) {
1761                 /* Auto restart link so settings take effect */
1762                 if (atomic_restart)
1763                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1764                 /* Copy over all the old settings */
1765                 config.phy_type = abilities.phy_type;
1766                 config.link_speed = abilities.link_speed;
1767                 config.eee_capability = abilities.eee_capability;
1768                 config.eeer = abilities.eeer_val;
1769                 config.low_power_ctrl = abilities.d3_lpan;
1770                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1771
1772                 if (status)
1773                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1774         }
1775         /* Update the link info */
1776         status = i40e_update_link_info(hw);
1777         if (status) {
1778                 /* Wait a little bit (on 40G cards it sometimes takes a really
1779                  * long time for link to come back from the atomic reset)
1780                  * and try once more
1781                  */
1782                 i40e_msec_delay(1000);
1783                 status = i40e_update_link_info(hw);
1784         }
1785         if (status)
1786                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1787
1788         return status;
1789 }
1790
1791 /**
1792  * i40e_aq_set_mac_config
1793  * @hw: pointer to the hw struct
1794  * @max_frame_size: Maximum Frame Size to be supported by the port
1795  * @crc_en: Tell HW to append a CRC to outgoing frames
1796  * @pacing: Pacing configurations
1797  * @cmd_details: pointer to command details structure or NULL
1798  *
1799  * Configure MAC settings for frame size, jumbo frame support and the
1800  * addition of a CRC by the hardware.
1801  **/
1802 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1803                                 u16 max_frame_size,
1804                                 bool crc_en, u16 pacing,
1805                                 struct i40e_asq_cmd_details *cmd_details)
1806 {
1807         struct i40e_aq_desc desc;
1808         struct i40e_aq_set_mac_config *cmd =
1809                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1810         enum i40e_status_code status;
1811
1812         if (max_frame_size == 0)
1813                 return I40E_ERR_PARAM;
1814
1815         i40e_fill_default_direct_cmd_desc(&desc,
1816                                           i40e_aqc_opc_set_mac_config);
1817
1818         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1819         cmd->params = ((u8)pacing & 0x0F) << 3;
1820         if (crc_en)
1821                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1822
1823         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1824
1825         return status;
1826 }
1827
1828 /**
1829  * i40e_aq_clear_pxe_mode
1830  * @hw: pointer to the hw struct
1831  * @cmd_details: pointer to command details structure or NULL
1832  *
1833  * Tell the firmware that the driver is taking over from PXE
1834  **/
1835 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1836                         struct i40e_asq_cmd_details *cmd_details)
1837 {
1838         enum i40e_status_code status;
1839         struct i40e_aq_desc desc;
1840         struct i40e_aqc_clear_pxe *cmd =
1841                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1842
1843         i40e_fill_default_direct_cmd_desc(&desc,
1844                                           i40e_aqc_opc_clear_pxe_mode);
1845
1846         cmd->rx_cnt = 0x2;
1847
1848         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1849
1850         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1851
1852         return status;
1853 }
1854
1855 /**
1856  * i40e_aq_set_link_restart_an
1857  * @hw: pointer to the hw struct
1858  * @enable_link: if true: enable link, if false: disable link
1859  * @cmd_details: pointer to command details structure or NULL
1860  *
1861  * Sets up the link and restarts the Auto-Negotiation over the link.
1862  **/
1863 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1864                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1865 {
1866         struct i40e_aq_desc desc;
1867         struct i40e_aqc_set_link_restart_an *cmd =
1868                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1869         enum i40e_status_code status;
1870
1871         i40e_fill_default_direct_cmd_desc(&desc,
1872                                           i40e_aqc_opc_set_link_restart_an);
1873
1874         cmd->command = I40E_AQ_PHY_RESTART_AN;
1875         if (enable_link)
1876                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1877         else
1878                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1879
1880         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1881
1882         return status;
1883 }
1884
1885 /**
1886  * i40e_aq_get_link_info
1887  * @hw: pointer to the hw struct
1888  * @enable_lse: enable/disable LinkStatusEvent reporting
1889  * @link: pointer to link status structure - optional
1890  * @cmd_details: pointer to command details structure or NULL
1891  *
1892  * Returns the link status of the adapter.
1893  **/
1894 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1895                                 bool enable_lse, struct i40e_link_status *link,
1896                                 struct i40e_asq_cmd_details *cmd_details)
1897 {
1898         struct i40e_aq_desc desc;
1899         struct i40e_aqc_get_link_status *resp =
1900                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1901         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1902         enum i40e_status_code status;
1903         bool tx_pause, rx_pause;
1904         u16 command_flags;
1905
1906         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1907
1908         if (enable_lse)
1909                 command_flags = I40E_AQ_LSE_ENABLE;
1910         else
1911                 command_flags = I40E_AQ_LSE_DISABLE;
1912         resp->command_flags = CPU_TO_LE16(command_flags);
1913
1914         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1915
1916         if (status != I40E_SUCCESS)
1917                 goto aq_get_link_info_exit;
1918
1919         /* save off old link status information */
1920         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1921                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1922
1923         /* update link status */
1924         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1925         hw->phy.media_type = i40e_get_media_type(hw);
1926         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1927         hw_link_info->link_info = resp->link_info;
1928         hw_link_info->an_info = resp->an_info;
1929         hw_link_info->ext_info = resp->ext_info;
1930         hw_link_info->loopback = resp->loopback;
1931         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1932         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1933
1934         /* update fc info */
1935         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1936         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1937         if (tx_pause & rx_pause)
1938                 hw->fc.current_mode = I40E_FC_FULL;
1939         else if (tx_pause)
1940                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1941         else if (rx_pause)
1942                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1943         else
1944                 hw->fc.current_mode = I40E_FC_NONE;
1945
1946         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1947                 hw_link_info->crc_enable = true;
1948         else
1949                 hw_link_info->crc_enable = false;
1950
1951         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1952                 hw_link_info->lse_enable = true;
1953         else
1954                 hw_link_info->lse_enable = false;
1955
1956         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1957              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1958                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1959
1960         /* save link status information */
1961         if (link)
1962                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1963                             I40E_NONDMA_TO_NONDMA);
1964
1965         /* flag cleared so helper functions don't call AQ again */
1966         hw->phy.get_link_info = false;
1967
1968 aq_get_link_info_exit:
1969         return status;
1970 }
1971
1972 /**
1973  * i40e_aq_set_phy_int_mask
1974  * @hw: pointer to the hw struct
1975  * @mask: interrupt mask to be set
1976  * @cmd_details: pointer to command details structure or NULL
1977  *
1978  * Set link interrupt mask.
1979  **/
1980 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1981                                 u16 mask,
1982                                 struct i40e_asq_cmd_details *cmd_details)
1983 {
1984         struct i40e_aq_desc desc;
1985         struct i40e_aqc_set_phy_int_mask *cmd =
1986                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1987         enum i40e_status_code status;
1988
1989         i40e_fill_default_direct_cmd_desc(&desc,
1990                                           i40e_aqc_opc_set_phy_int_mask);
1991
1992         cmd->event_mask = CPU_TO_LE16(mask);
1993
1994         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1995
1996         return status;
1997 }
1998
1999 /**
2000  * i40e_aq_get_local_advt_reg
2001  * @hw: pointer to the hw struct
2002  * @advt_reg: local AN advertisement register value
2003  * @cmd_details: pointer to command details structure or NULL
2004  *
2005  * Get the Local AN advertisement register value.
2006  **/
2007 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2008                                 u64 *advt_reg,
2009                                 struct i40e_asq_cmd_details *cmd_details)
2010 {
2011         struct i40e_aq_desc desc;
2012         struct i40e_aqc_an_advt_reg *resp =
2013                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2014         enum i40e_status_code status;
2015
2016         i40e_fill_default_direct_cmd_desc(&desc,
2017                                           i40e_aqc_opc_get_local_advt_reg);
2018
2019         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2020
2021         if (status != I40E_SUCCESS)
2022                 goto aq_get_local_advt_reg_exit;
2023
2024         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2025         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2026
2027 aq_get_local_advt_reg_exit:
2028         return status;
2029 }
2030
2031 /**
2032  * i40e_aq_set_local_advt_reg
2033  * @hw: pointer to the hw struct
2034  * @advt_reg: local AN advertisement register value
2035  * @cmd_details: pointer to command details structure or NULL
2036  *
2037  * Get the Local AN advertisement register value.
2038  **/
2039 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2040                                 u64 advt_reg,
2041                                 struct i40e_asq_cmd_details *cmd_details)
2042 {
2043         struct i40e_aq_desc desc;
2044         struct i40e_aqc_an_advt_reg *cmd =
2045                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2046         enum i40e_status_code status;
2047
2048         i40e_fill_default_direct_cmd_desc(&desc,
2049                                           i40e_aqc_opc_get_local_advt_reg);
2050
2051         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2052         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2053
2054         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2055
2056         return status;
2057 }
2058
2059 /**
2060  * i40e_aq_get_partner_advt
2061  * @hw: pointer to the hw struct
2062  * @advt_reg: AN partner advertisement register value
2063  * @cmd_details: pointer to command details structure or NULL
2064  *
2065  * Get the link partner AN advertisement register value.
2066  **/
2067 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2068                                 u64 *advt_reg,
2069                                 struct i40e_asq_cmd_details *cmd_details)
2070 {
2071         struct i40e_aq_desc desc;
2072         struct i40e_aqc_an_advt_reg *resp =
2073                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2074         enum i40e_status_code status;
2075
2076         i40e_fill_default_direct_cmd_desc(&desc,
2077                                           i40e_aqc_opc_get_partner_advt);
2078
2079         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2080
2081         if (status != I40E_SUCCESS)
2082                 goto aq_get_partner_advt_exit;
2083
2084         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2085         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2086
2087 aq_get_partner_advt_exit:
2088         return status;
2089 }
2090
2091 /**
2092  * i40e_aq_set_lb_modes
2093  * @hw: pointer to the hw struct
2094  * @lb_modes: loopback mode to be set
2095  * @cmd_details: pointer to command details structure or NULL
2096  *
2097  * Sets loopback modes.
2098  **/
2099 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2100                                 u16 lb_modes,
2101                                 struct i40e_asq_cmd_details *cmd_details)
2102 {
2103         struct i40e_aq_desc desc;
2104         struct i40e_aqc_set_lb_mode *cmd =
2105                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2106         enum i40e_status_code status;
2107
2108         i40e_fill_default_direct_cmd_desc(&desc,
2109                                           i40e_aqc_opc_set_lb_modes);
2110
2111         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2112
2113         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2114
2115         return status;
2116 }
2117
2118 /**
2119  * i40e_aq_set_phy_debug
2120  * @hw: pointer to the hw struct
2121  * @cmd_flags: debug command flags
2122  * @cmd_details: pointer to command details structure or NULL
2123  *
2124  * Reset the external PHY.
2125  **/
2126 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2127                                 struct i40e_asq_cmd_details *cmd_details)
2128 {
2129         struct i40e_aq_desc desc;
2130         struct i40e_aqc_set_phy_debug *cmd =
2131                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2132         enum i40e_status_code status;
2133
2134         i40e_fill_default_direct_cmd_desc(&desc,
2135                                           i40e_aqc_opc_set_phy_debug);
2136
2137         cmd->command_flags = cmd_flags;
2138
2139         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2140
2141         return status;
2142 }
2143
2144 /**
2145  * i40e_aq_add_vsi
2146  * @hw: pointer to the hw struct
2147  * @vsi_ctx: pointer to a vsi context struct
2148  * @cmd_details: pointer to command details structure or NULL
2149  *
2150  * Add a VSI context to the hardware.
2151 **/
2152 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2153                                 struct i40e_vsi_context *vsi_ctx,
2154                                 struct i40e_asq_cmd_details *cmd_details)
2155 {
2156         struct i40e_aq_desc desc;
2157         struct i40e_aqc_add_get_update_vsi *cmd =
2158                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2159         struct i40e_aqc_add_get_update_vsi_completion *resp =
2160                 (struct i40e_aqc_add_get_update_vsi_completion *)
2161                 &desc.params.raw;
2162         enum i40e_status_code status;
2163
2164         i40e_fill_default_direct_cmd_desc(&desc,
2165                                           i40e_aqc_opc_add_vsi);
2166
2167         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2168         cmd->connection_type = vsi_ctx->connection_type;
2169         cmd->vf_id = vsi_ctx->vf_num;
2170         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2171
2172         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2173
2174         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2175                                     sizeof(vsi_ctx->info), cmd_details);
2176
2177         if (status != I40E_SUCCESS)
2178                 goto aq_add_vsi_exit;
2179
2180         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2181         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2182         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2183         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2184
2185 aq_add_vsi_exit:
2186         return status;
2187 }
2188
2189 /**
2190  * i40e_aq_set_default_vsi
2191  * @hw: pointer to the hw struct
2192  * @seid: vsi number
2193  * @cmd_details: pointer to command details structure or NULL
2194  **/
2195 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2196                                 u16 seid,
2197                                 struct i40e_asq_cmd_details *cmd_details)
2198 {
2199         struct i40e_aq_desc desc;
2200         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2201                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2202                 &desc.params.raw;
2203         enum i40e_status_code status;
2204
2205         i40e_fill_default_direct_cmd_desc(&desc,
2206                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2207
2208         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2209         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2210         cmd->seid = CPU_TO_LE16(seid);
2211
2212         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2213
2214         return status;
2215 }
2216
2217 /**
2218  * i40e_aq_clear_default_vsi
2219  * @hw: pointer to the hw struct
2220  * @seid: vsi number
2221  * @cmd_details: pointer to command details structure or NULL
2222  **/
2223 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2224                                 u16 seid,
2225                                 struct i40e_asq_cmd_details *cmd_details)
2226 {
2227         struct i40e_aq_desc desc;
2228         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2229                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2230                 &desc.params.raw;
2231         enum i40e_status_code status;
2232
2233         i40e_fill_default_direct_cmd_desc(&desc,
2234                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2235
2236         cmd->promiscuous_flags = CPU_TO_LE16(0);
2237         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2238         cmd->seid = CPU_TO_LE16(seid);
2239
2240         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2241
2242         return status;
2243 }
2244
2245 /**
2246  * i40e_aq_set_vsi_unicast_promiscuous
2247  * @hw: pointer to the hw struct
2248  * @seid: vsi number
2249  * @set: set unicast promiscuous enable/disable
2250  * @cmd_details: pointer to command details structure or NULL
2251  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2252  **/
2253 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2254                                 u16 seid, bool set,
2255                                 struct i40e_asq_cmd_details *cmd_details,
2256                                 bool rx_only_promisc)
2257 {
2258         struct i40e_aq_desc desc;
2259         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2260                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2261         enum i40e_status_code status;
2262         u16 flags = 0;
2263
2264         i40e_fill_default_direct_cmd_desc(&desc,
2265                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2266
2267         if (set) {
2268                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2269                 if (rx_only_promisc &&
2270                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2271                      (hw->aq.api_maj_ver > 1)))
2272                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2273         }
2274
2275         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2276
2277         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2278         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2279              (hw->aq.api_maj_ver > 1))
2280                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2281
2282         cmd->seid = CPU_TO_LE16(seid);
2283         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2284
2285         return status;
2286 }
2287
2288 /**
2289  * i40e_aq_set_vsi_multicast_promiscuous
2290  * @hw: pointer to the hw struct
2291  * @seid: vsi number
2292  * @set: set multicast promiscuous enable/disable
2293  * @cmd_details: pointer to command details structure or NULL
2294  **/
2295 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2296                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2297 {
2298         struct i40e_aq_desc desc;
2299         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2300                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2301         enum i40e_status_code status;
2302         u16 flags = 0;
2303
2304         i40e_fill_default_direct_cmd_desc(&desc,
2305                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2306
2307         if (set)
2308                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2309
2310         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2311
2312         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2313
2314         cmd->seid = CPU_TO_LE16(seid);
2315         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2316
2317         return status;
2318 }
2319
2320 /**
2321  * i40e_aq_set_vsi_mc_promisc_on_vlan
2322  * @hw: pointer to the hw struct
2323  * @seid: vsi number
2324  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2325  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2326  * @cmd_details: pointer to command details structure or NULL
2327  **/
2328 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2329                                 u16 seid, bool enable, u16 vid,
2330                                 struct i40e_asq_cmd_details *cmd_details)
2331 {
2332         struct i40e_aq_desc desc;
2333         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2334                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2335         enum i40e_status_code status;
2336         u16 flags = 0;
2337
2338         i40e_fill_default_direct_cmd_desc(&desc,
2339                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2340
2341         if (enable)
2342                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2343
2344         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2345         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2346         cmd->seid = CPU_TO_LE16(seid);
2347         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2348
2349         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2350
2351         return status;
2352 }
2353
2354 /**
2355  * i40e_aq_set_vsi_uc_promisc_on_vlan
2356  * @hw: pointer to the hw struct
2357  * @seid: vsi number
2358  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2359  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2360  * @cmd_details: pointer to command details structure or NULL
2361  **/
2362 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2363                                 u16 seid, bool enable, u16 vid,
2364                                 struct i40e_asq_cmd_details *cmd_details)
2365 {
2366         struct i40e_aq_desc desc;
2367         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2368                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2369         enum i40e_status_code status;
2370         u16 flags = 0;
2371
2372         i40e_fill_default_direct_cmd_desc(&desc,
2373                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2374
2375         if (enable)
2376                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2377
2378         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2379         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2380         cmd->seid = CPU_TO_LE16(seid);
2381         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2382
2383         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2384
2385         return status;
2386 }
2387
2388 /**
2389  * i40e_aq_set_vsi_broadcast
2390  * @hw: pointer to the hw struct
2391  * @seid: vsi number
2392  * @set_filter: true to set filter, false to clear filter
2393  * @cmd_details: pointer to command details structure or NULL
2394  *
2395  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2396  **/
2397 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2398                                 u16 seid, bool set_filter,
2399                                 struct i40e_asq_cmd_details *cmd_details)
2400 {
2401         struct i40e_aq_desc desc;
2402         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2403                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2404         enum i40e_status_code status;
2405
2406         i40e_fill_default_direct_cmd_desc(&desc,
2407                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2408
2409         if (set_filter)
2410                 cmd->promiscuous_flags
2411                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2412         else
2413                 cmd->promiscuous_flags
2414                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2415
2416         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2417         cmd->seid = CPU_TO_LE16(seid);
2418         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2419
2420         return status;
2421 }
2422
2423 /**
2424  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2425  * @hw: pointer to the hw struct
2426  * @seid: vsi number
2427  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2428  * @cmd_details: pointer to command details structure or NULL
2429  **/
2430 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2431                                 u16 seid, bool enable,
2432                                 struct i40e_asq_cmd_details *cmd_details)
2433 {
2434         struct i40e_aq_desc desc;
2435         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2436                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2437         enum i40e_status_code status;
2438         u16 flags = 0;
2439
2440         i40e_fill_default_direct_cmd_desc(&desc,
2441                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2442         if (enable)
2443                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2444
2445         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2446         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2447         cmd->seid = CPU_TO_LE16(seid);
2448
2449         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2450
2451         return status;
2452 }
2453
2454 /**
2455  * i40e_get_vsi_params - get VSI configuration info
2456  * @hw: pointer to the hw struct
2457  * @vsi_ctx: pointer to a vsi context struct
2458  * @cmd_details: pointer to command details structure or NULL
2459  **/
2460 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2461                                 struct i40e_vsi_context *vsi_ctx,
2462                                 struct i40e_asq_cmd_details *cmd_details)
2463 {
2464         struct i40e_aq_desc desc;
2465         struct i40e_aqc_add_get_update_vsi *cmd =
2466                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2467         struct i40e_aqc_add_get_update_vsi_completion *resp =
2468                 (struct i40e_aqc_add_get_update_vsi_completion *)
2469                 &desc.params.raw;
2470         enum i40e_status_code status;
2471
2472         UNREFERENCED_1PARAMETER(cmd_details);
2473         i40e_fill_default_direct_cmd_desc(&desc,
2474                                           i40e_aqc_opc_get_vsi_parameters);
2475
2476         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2477
2478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2479
2480         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2481                                     sizeof(vsi_ctx->info), NULL);
2482
2483         if (status != I40E_SUCCESS)
2484                 goto aq_get_vsi_params_exit;
2485
2486         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2487         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2488         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2489         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2490
2491 aq_get_vsi_params_exit:
2492         return status;
2493 }
2494
2495 /**
2496  * i40e_aq_update_vsi_params
2497  * @hw: pointer to the hw struct
2498  * @vsi_ctx: pointer to a vsi context struct
2499  * @cmd_details: pointer to command details structure or NULL
2500  *
2501  * Update a VSI context.
2502  **/
2503 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2504                                 struct i40e_vsi_context *vsi_ctx,
2505                                 struct i40e_asq_cmd_details *cmd_details)
2506 {
2507         struct i40e_aq_desc desc;
2508         struct i40e_aqc_add_get_update_vsi *cmd =
2509                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2510         struct i40e_aqc_add_get_update_vsi_completion *resp =
2511                 (struct i40e_aqc_add_get_update_vsi_completion *)
2512                 &desc.params.raw;
2513         enum i40e_status_code status;
2514
2515         i40e_fill_default_direct_cmd_desc(&desc,
2516                                           i40e_aqc_opc_update_vsi_parameters);
2517         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2518
2519         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2520
2521         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2522                                     sizeof(vsi_ctx->info), cmd_details);
2523
2524         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2525         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2526
2527         return status;
2528 }
2529
2530 /**
2531  * i40e_aq_get_switch_config
2532  * @hw: pointer to the hardware structure
2533  * @buf: pointer to the result buffer
2534  * @buf_size: length of input buffer
2535  * @start_seid: seid to start for the report, 0 == beginning
2536  * @cmd_details: pointer to command details structure or NULL
2537  *
2538  * Fill the buf with switch configuration returned from AdminQ command
2539  **/
2540 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2541                                 struct i40e_aqc_get_switch_config_resp *buf,
2542                                 u16 buf_size, u16 *start_seid,
2543                                 struct i40e_asq_cmd_details *cmd_details)
2544 {
2545         struct i40e_aq_desc desc;
2546         struct i40e_aqc_switch_seid *scfg =
2547                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2548         enum i40e_status_code status;
2549
2550         i40e_fill_default_direct_cmd_desc(&desc,
2551                                           i40e_aqc_opc_get_switch_config);
2552         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2553         if (buf_size > I40E_AQ_LARGE_BUF)
2554                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2555         scfg->seid = CPU_TO_LE16(*start_seid);
2556
2557         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2558         *start_seid = LE16_TO_CPU(scfg->seid);
2559
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_aq_set_switch_config
2565  * @hw: pointer to the hardware structure
2566  * @flags: bit flag values to set
2567  * @valid_flags: which bit flags to set
2568  * @cmd_details: pointer to command details structure or NULL
2569  *
2570  * Set switch configuration bits
2571  **/
2572 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2573                                 u16 flags, u16 valid_flags,
2574                                 struct i40e_asq_cmd_details *cmd_details)
2575 {
2576         struct i40e_aq_desc desc;
2577         struct i40e_aqc_set_switch_config *scfg =
2578                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2579         enum i40e_status_code status;
2580
2581         i40e_fill_default_direct_cmd_desc(&desc,
2582                                           i40e_aqc_opc_set_switch_config);
2583         scfg->flags = CPU_TO_LE16(flags);
2584         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2585
2586         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2587
2588         return status;
2589 }
2590
2591 /**
2592  * i40e_aq_get_firmware_version
2593  * @hw: pointer to the hw struct
2594  * @fw_major_version: firmware major version
2595  * @fw_minor_version: firmware minor version
2596  * @fw_build: firmware build number
2597  * @api_major_version: major queue version
2598  * @api_minor_version: minor queue version
2599  * @cmd_details: pointer to command details structure or NULL
2600  *
2601  * Get the firmware version from the admin queue commands
2602  **/
2603 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2604                                 u16 *fw_major_version, u16 *fw_minor_version,
2605                                 u32 *fw_build,
2606                                 u16 *api_major_version, u16 *api_minor_version,
2607                                 struct i40e_asq_cmd_details *cmd_details)
2608 {
2609         struct i40e_aq_desc desc;
2610         struct i40e_aqc_get_version *resp =
2611                 (struct i40e_aqc_get_version *)&desc.params.raw;
2612         enum i40e_status_code status;
2613
2614         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2615
2616         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2617
2618         if (status == I40E_SUCCESS) {
2619                 if (fw_major_version != NULL)
2620                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2621                 if (fw_minor_version != NULL)
2622                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2623                 if (fw_build != NULL)
2624                         *fw_build = LE32_TO_CPU(resp->fw_build);
2625                 if (api_major_version != NULL)
2626                         *api_major_version = LE16_TO_CPU(resp->api_major);
2627                 if (api_minor_version != NULL)
2628                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2629
2630                 /* A workaround to fix the API version in SW */
2631                 if (api_major_version && api_minor_version &&
2632                     fw_major_version && fw_minor_version &&
2633                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2634                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2635                      (*fw_major_version > 4)))
2636                         *api_minor_version = 2;
2637         }
2638
2639         return status;
2640 }
2641
2642 /**
2643  * i40e_aq_send_driver_version
2644  * @hw: pointer to the hw struct
2645  * @dv: driver's major, minor version
2646  * @cmd_details: pointer to command details structure or NULL
2647  *
2648  * Send the driver version to the firmware
2649  **/
2650 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2651                                 struct i40e_driver_version *dv,
2652                                 struct i40e_asq_cmd_details *cmd_details)
2653 {
2654         struct i40e_aq_desc desc;
2655         struct i40e_aqc_driver_version *cmd =
2656                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2657         enum i40e_status_code status;
2658         u16 len;
2659
2660         if (dv == NULL)
2661                 return I40E_ERR_PARAM;
2662
2663         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2664
2665         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2666         cmd->driver_major_ver = dv->major_version;
2667         cmd->driver_minor_ver = dv->minor_version;
2668         cmd->driver_build_ver = dv->build_version;
2669         cmd->driver_subbuild_ver = dv->subbuild_version;
2670
2671         len = 0;
2672         while (len < sizeof(dv->driver_string) &&
2673                (dv->driver_string[len] < 0x80) &&
2674                dv->driver_string[len])
2675                 len++;
2676         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2677                                        len, cmd_details);
2678
2679         return status;
2680 }
2681
2682 /**
2683  * i40e_get_link_status - get status of the HW network link
2684  * @hw: pointer to the hw struct
2685  * @link_up: pointer to bool (true/false = linkup/linkdown)
2686  *
2687  * Variable link_up true if link is up, false if link is down.
2688  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2689  *
2690  * Side effect: LinkStatusEvent reporting becomes enabled
2691  **/
2692 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2693 {
2694         enum i40e_status_code status = I40E_SUCCESS;
2695
2696         if (hw->phy.get_link_info) {
2697                 status = i40e_update_link_info(hw);
2698
2699                 if (status != I40E_SUCCESS)
2700                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2701                                    status);
2702         }
2703
2704         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2705
2706         return status;
2707 }
2708
2709 /**
2710  * i40e_updatelink_status - update status of the HW network link
2711  * @hw: pointer to the hw struct
2712  **/
2713 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2714 {
2715         struct i40e_aq_get_phy_abilities_resp abilities;
2716         enum i40e_status_code status = I40E_SUCCESS;
2717
2718         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2719         if (status)
2720                 return status;
2721
2722         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2723                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2724                                                       &abilities, NULL);
2725                 if (status)
2726                         return status;
2727
2728                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2729                         sizeof(hw->phy.link_info.module_type));
2730         }
2731         return status;
2732 }
2733
2734
2735 /**
2736  * i40e_get_link_speed
2737  * @hw: pointer to the hw struct
2738  *
2739  * Returns the link speed of the adapter.
2740  **/
2741 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2742 {
2743         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2744         enum i40e_status_code status = I40E_SUCCESS;
2745
2746         if (hw->phy.get_link_info) {
2747                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2748
2749                 if (status != I40E_SUCCESS)
2750                         goto i40e_link_speed_exit;
2751         }
2752
2753         speed = hw->phy.link_info.link_speed;
2754
2755 i40e_link_speed_exit:
2756         return speed;
2757 }
2758
2759 /**
2760  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2761  * @hw: pointer to the hw struct
2762  * @uplink_seid: the MAC or other gizmo SEID
2763  * @downlink_seid: the VSI SEID
2764  * @enabled_tc: bitmap of TCs to be enabled
2765  * @default_port: true for default port VSI, false for control port
2766  * @veb_seid: pointer to where to put the resulting VEB SEID
2767  * @enable_stats: true to turn on VEB stats
2768  * @cmd_details: pointer to command details structure or NULL
2769  *
2770  * This asks the FW to add a VEB between the uplink and downlink
2771  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2772  **/
2773 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2774                                 u16 downlink_seid, u8 enabled_tc,
2775                                 bool default_port, u16 *veb_seid,
2776                                 bool enable_stats,
2777                                 struct i40e_asq_cmd_details *cmd_details)
2778 {
2779         struct i40e_aq_desc desc;
2780         struct i40e_aqc_add_veb *cmd =
2781                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2782         struct i40e_aqc_add_veb_completion *resp =
2783                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2784         enum i40e_status_code status;
2785         u16 veb_flags = 0;
2786
2787         /* SEIDs need to either both be set or both be 0 for floating VEB */
2788         if (!!uplink_seid != !!downlink_seid)
2789                 return I40E_ERR_PARAM;
2790
2791         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2792
2793         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2794         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2795         cmd->enable_tcs = enabled_tc;
2796         if (!uplink_seid)
2797                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2798         if (default_port)
2799                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2800         else
2801                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2802
2803         /* reverse logic here: set the bitflag to disable the stats */
2804         if (!enable_stats)
2805                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2806
2807         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2808
2809         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2810
2811         if (!status && veb_seid)
2812                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2813
2814         return status;
2815 }
2816
2817 /**
2818  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2819  * @hw: pointer to the hw struct
2820  * @veb_seid: the SEID of the VEB to query
2821  * @switch_id: the uplink switch id
2822  * @floating: set to true if the VEB is floating
2823  * @statistic_index: index of the stats counter block for this VEB
2824  * @vebs_used: number of VEB's used by function
2825  * @vebs_free: total VEB's not reserved by any function
2826  * @cmd_details: pointer to command details structure or NULL
2827  *
2828  * This retrieves the parameters for a particular VEB, specified by
2829  * uplink_seid, and returns them to the caller.
2830  **/
2831 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2832                                 u16 veb_seid, u16 *switch_id,
2833                                 bool *floating, u16 *statistic_index,
2834                                 u16 *vebs_used, u16 *vebs_free,
2835                                 struct i40e_asq_cmd_details *cmd_details)
2836 {
2837         struct i40e_aq_desc desc;
2838         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2839                 (struct i40e_aqc_get_veb_parameters_completion *)
2840                 &desc.params.raw;
2841         enum i40e_status_code status;
2842
2843         if (veb_seid == 0)
2844                 return I40E_ERR_PARAM;
2845
2846         i40e_fill_default_direct_cmd_desc(&desc,
2847                                           i40e_aqc_opc_get_veb_parameters);
2848         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2849
2850         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2851         if (status)
2852                 goto get_veb_exit;
2853
2854         if (switch_id)
2855                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2856         if (statistic_index)
2857                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2858         if (vebs_used)
2859                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2860         if (vebs_free)
2861                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2862         if (floating) {
2863                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2864
2865                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2866                         *floating = true;
2867                 else
2868                         *floating = false;
2869         }
2870
2871 get_veb_exit:
2872         return status;
2873 }
2874
2875 /**
2876  * i40e_aq_add_macvlan
2877  * @hw: pointer to the hw struct
2878  * @seid: VSI for the mac address
2879  * @mv_list: list of macvlans to be added
2880  * @count: length of the list
2881  * @cmd_details: pointer to command details structure or NULL
2882  *
2883  * Add MAC/VLAN addresses to the HW filtering
2884  **/
2885 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2886                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2887                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2888 {
2889         struct i40e_aq_desc desc;
2890         struct i40e_aqc_macvlan *cmd =
2891                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2892         enum i40e_status_code status;
2893         u16 buf_size;
2894         int i;
2895
2896         if (count == 0 || !mv_list || !hw)
2897                 return I40E_ERR_PARAM;
2898
2899         buf_size = count * sizeof(*mv_list);
2900
2901         /* prep the rest of the request */
2902         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2903         cmd->num_addresses = CPU_TO_LE16(count);
2904         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2905         cmd->seid[1] = 0;
2906         cmd->seid[2] = 0;
2907
2908         for (i = 0; i < count; i++)
2909                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2910                         mv_list[i].flags |=
2911                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2912
2913         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2914         if (buf_size > I40E_AQ_LARGE_BUF)
2915                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2916
2917         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2918                                        cmd_details);
2919
2920         return status;
2921 }
2922
2923 /**
2924  * i40e_aq_remove_macvlan
2925  * @hw: pointer to the hw struct
2926  * @seid: VSI for the mac address
2927  * @mv_list: list of macvlans to be removed
2928  * @count: length of the list
2929  * @cmd_details: pointer to command details structure or NULL
2930  *
2931  * Remove MAC/VLAN addresses from the HW filtering
2932  **/
2933 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2934                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2935                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2936 {
2937         struct i40e_aq_desc desc;
2938         struct i40e_aqc_macvlan *cmd =
2939                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2940         enum i40e_status_code status;
2941         u16 buf_size;
2942
2943         if (count == 0 || !mv_list || !hw)
2944                 return I40E_ERR_PARAM;
2945
2946         buf_size = count * sizeof(*mv_list);
2947
2948         /* prep the rest of the request */
2949         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2950         cmd->num_addresses = CPU_TO_LE16(count);
2951         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2952         cmd->seid[1] = 0;
2953         cmd->seid[2] = 0;
2954
2955         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2956         if (buf_size > I40E_AQ_LARGE_BUF)
2957                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2958
2959         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2960                                        cmd_details);
2961
2962         return status;
2963 }
2964
2965 /**
2966  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2967  * @hw: pointer to the hw struct
2968  * @opcode: AQ opcode for add or delete mirror rule
2969  * @sw_seid: Switch SEID (to which rule refers)
2970  * @rule_type: Rule Type (ingress/egress/VLAN)
2971  * @id: Destination VSI SEID or Rule ID
2972  * @count: length of the list
2973  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2974  * @cmd_details: pointer to command details structure or NULL
2975  * @rule_id: Rule ID returned from FW
2976  * @rule_used: Number of rules used in internal switch
2977  * @rule_free: Number of rules free in internal switch
2978  *
2979  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2980  * VEBs/VEPA elements only
2981  **/
2982 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2983                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2984                         u16 count, __le16 *mr_list,
2985                         struct i40e_asq_cmd_details *cmd_details,
2986                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2987 {
2988         struct i40e_aq_desc desc;
2989         struct i40e_aqc_add_delete_mirror_rule *cmd =
2990                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2991         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2992         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2993         enum i40e_status_code status;
2994         u16 buf_size;
2995
2996         buf_size = count * sizeof(*mr_list);
2997
2998         /* prep the rest of the request */
2999         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3000         cmd->seid = CPU_TO_LE16(sw_seid);
3001         cmd->rule_type = CPU_TO_LE16(rule_type &
3002                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3003         cmd->num_entries = CPU_TO_LE16(count);
3004         /* Dest VSI for add, rule_id for delete */
3005         cmd->destination = CPU_TO_LE16(id);
3006         if (mr_list) {
3007                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3008                                                 I40E_AQ_FLAG_RD));
3009                 if (buf_size > I40E_AQ_LARGE_BUF)
3010                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3011         }
3012
3013         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3014                                        cmd_details);
3015         if (status == I40E_SUCCESS ||
3016             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3017                 if (rule_id)
3018                         *rule_id = LE16_TO_CPU(resp->rule_id);
3019                 if (rules_used)
3020                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3021                 if (rules_free)
3022                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3023         }
3024         return status;
3025 }
3026
3027 /**
3028  * i40e_aq_add_mirrorrule - add a mirror rule
3029  * @hw: pointer to the hw struct
3030  * @sw_seid: Switch SEID (to which rule refers)
3031  * @rule_type: Rule Type (ingress/egress/VLAN)
3032  * @dest_vsi: SEID of VSI to which packets will be mirrored
3033  * @count: length of the list
3034  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3035  * @cmd_details: pointer to command details structure or NULL
3036  * @rule_id: Rule ID returned from FW
3037  * @rule_used: Number of rules used in internal switch
3038  * @rule_free: Number of rules free in internal switch
3039  *
3040  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3041  **/
3042 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3043                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3044                         struct i40e_asq_cmd_details *cmd_details,
3045                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3046 {
3047         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3048             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3049                 if (count == 0 || !mr_list)
3050                         return I40E_ERR_PARAM;
3051         }
3052
3053         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3054                                   rule_type, dest_vsi, count, mr_list,
3055                                   cmd_details, rule_id, rules_used, rules_free);
3056 }
3057
3058 /**
3059  * i40e_aq_delete_mirrorrule - delete a mirror rule
3060  * @hw: pointer to the hw struct
3061  * @sw_seid: Switch SEID (to which rule refers)
3062  * @rule_type: Rule Type (ingress/egress/VLAN)
3063  * @count: length of the list
3064  * @rule_id: Rule ID that is returned in the receive desc as part of
3065  *              add_mirrorrule.
3066  * @mr_list: list of mirrored VLAN IDs to be removed
3067  * @cmd_details: pointer to command details structure or NULL
3068  * @rule_used: Number of rules used in internal switch
3069  * @rule_free: Number of rules free in internal switch
3070  *
3071  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3072  **/
3073 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3074                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3075                         struct i40e_asq_cmd_details *cmd_details,
3076                         u16 *rules_used, u16 *rules_free)
3077 {
3078         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3079         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3080                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3081                  * mirroring. For other rule_type, count and rule_type should
3082                  * not matter.
3083                  */
3084                 if (count == 0 || !mr_list)
3085                         return I40E_ERR_PARAM;
3086         }
3087
3088         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3089                                   rule_type, rule_id, count, mr_list,
3090                                   cmd_details, NULL, rules_used, rules_free);
3091 }
3092
3093 /**
3094  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3095  * @hw: pointer to the hw struct
3096  * @seid: VSI for the vlan filters
3097  * @v_list: list of vlan filters to be added
3098  * @count: length of the list
3099  * @cmd_details: pointer to command details structure or NULL
3100  **/
3101 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3102                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3103                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3104 {
3105         struct i40e_aq_desc desc;
3106         struct i40e_aqc_macvlan *cmd =
3107                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3108         enum i40e_status_code status;
3109         u16 buf_size;
3110
3111         if (count == 0 || !v_list || !hw)
3112                 return I40E_ERR_PARAM;
3113
3114         buf_size = count * sizeof(*v_list);
3115
3116         /* prep the rest of the request */
3117         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3118         cmd->num_addresses = CPU_TO_LE16(count);
3119         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3120         cmd->seid[1] = 0;
3121         cmd->seid[2] = 0;
3122
3123         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3124         if (buf_size > I40E_AQ_LARGE_BUF)
3125                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3126
3127         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3128                                        cmd_details);
3129
3130         return status;
3131 }
3132
3133 /**
3134  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3135  * @hw: pointer to the hw struct
3136  * @seid: VSI for the vlan filters
3137  * @v_list: list of macvlans to be removed
3138  * @count: length of the list
3139  * @cmd_details: pointer to command details structure or NULL
3140  **/
3141 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3142                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3143                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3144 {
3145         struct i40e_aq_desc desc;
3146         struct i40e_aqc_macvlan *cmd =
3147                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3148         enum i40e_status_code status;
3149         u16 buf_size;
3150
3151         if (count == 0 || !v_list || !hw)
3152                 return I40E_ERR_PARAM;
3153
3154         buf_size = count * sizeof(*v_list);
3155
3156         /* prep the rest of the request */
3157         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3158         cmd->num_addresses = CPU_TO_LE16(count);
3159         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3160         cmd->seid[1] = 0;
3161         cmd->seid[2] = 0;
3162
3163         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3164         if (buf_size > I40E_AQ_LARGE_BUF)
3165                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3166
3167         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3168                                        cmd_details);
3169
3170         return status;
3171 }
3172
3173 /**
3174  * i40e_aq_send_msg_to_vf
3175  * @hw: pointer to the hardware structure
3176  * @vfid: vf id to send msg
3177  * @v_opcode: opcodes for VF-PF communication
3178  * @v_retval: return error code
3179  * @msg: pointer to the msg buffer
3180  * @msglen: msg length
3181  * @cmd_details: pointer to command details
3182  *
3183  * send msg to vf
3184  **/
3185 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3186                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3187                                 struct i40e_asq_cmd_details *cmd_details)
3188 {
3189         struct i40e_aq_desc desc;
3190         struct i40e_aqc_pf_vf_message *cmd =
3191                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3192         enum i40e_status_code status;
3193
3194         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3195         cmd->id = CPU_TO_LE32(vfid);
3196         desc.cookie_high = CPU_TO_LE32(v_opcode);
3197         desc.cookie_low = CPU_TO_LE32(v_retval);
3198         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3199         if (msglen) {
3200                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3201                                                 I40E_AQ_FLAG_RD));
3202                 if (msglen > I40E_AQ_LARGE_BUF)
3203                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3204                 desc.datalen = CPU_TO_LE16(msglen);
3205         }
3206         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3207
3208         return status;
3209 }
3210
3211 /**
3212  * i40e_aq_debug_read_register
3213  * @hw: pointer to the hw struct
3214  * @reg_addr: register address
3215  * @reg_val: register value
3216  * @cmd_details: pointer to command details structure or NULL
3217  *
3218  * Read the register using the admin queue commands
3219  **/
3220 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3221                                 u32 reg_addr, u64 *reg_val,
3222                                 struct i40e_asq_cmd_details *cmd_details)
3223 {
3224         struct i40e_aq_desc desc;
3225         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3226                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3227         enum i40e_status_code status;
3228
3229         if (reg_val == NULL)
3230                 return I40E_ERR_PARAM;
3231
3232         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3233
3234         cmd_resp->address = CPU_TO_LE32(reg_addr);
3235
3236         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3237
3238         if (status == I40E_SUCCESS) {
3239                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3240                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3241         }
3242
3243         return status;
3244 }
3245
3246 /**
3247  * i40e_aq_debug_write_register
3248  * @hw: pointer to the hw struct
3249  * @reg_addr: register address
3250  * @reg_val: register value
3251  * @cmd_details: pointer to command details structure or NULL
3252  *
3253  * Write to a register using the admin queue commands
3254  **/
3255 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3256                                 u32 reg_addr, u64 reg_val,
3257                                 struct i40e_asq_cmd_details *cmd_details)
3258 {
3259         struct i40e_aq_desc desc;
3260         struct i40e_aqc_debug_reg_read_write *cmd =
3261                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3262         enum i40e_status_code status;
3263
3264         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3265
3266         cmd->address = CPU_TO_LE32(reg_addr);
3267         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3268         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3269
3270         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3271
3272         return status;
3273 }
3274
3275 /**
3276  * i40e_aq_request_resource
3277  * @hw: pointer to the hw struct
3278  * @resource: resource id
3279  * @access: access type
3280  * @sdp_number: resource number
3281  * @timeout: the maximum time in ms that the driver may hold the resource
3282  * @cmd_details: pointer to command details structure or NULL
3283  *
3284  * requests common resource using the admin queue commands
3285  **/
3286 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3287                                 enum i40e_aq_resources_ids resource,
3288                                 enum i40e_aq_resource_access_type access,
3289                                 u8 sdp_number, u64 *timeout,
3290                                 struct i40e_asq_cmd_details *cmd_details)
3291 {
3292         struct i40e_aq_desc desc;
3293         struct i40e_aqc_request_resource *cmd_resp =
3294                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3295         enum i40e_status_code status;
3296
3297         DEBUGFUNC("i40e_aq_request_resource");
3298
3299         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3300
3301         cmd_resp->resource_id = CPU_TO_LE16(resource);
3302         cmd_resp->access_type = CPU_TO_LE16(access);
3303         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3304
3305         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3306         /* The completion specifies the maximum time in ms that the driver
3307          * may hold the resource in the Timeout field.
3308          * If the resource is held by someone else, the command completes with
3309          * busy return value and the timeout field indicates the maximum time
3310          * the current owner of the resource has to free it.
3311          */
3312         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3313                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3314
3315         return status;
3316 }
3317
3318 /**
3319  * i40e_aq_release_resource
3320  * @hw: pointer to the hw struct
3321  * @resource: resource id
3322  * @sdp_number: resource number
3323  * @cmd_details: pointer to command details structure or NULL
3324  *
3325  * release common resource using the admin queue commands
3326  **/
3327 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3328                                 enum i40e_aq_resources_ids resource,
3329                                 u8 sdp_number,
3330                                 struct i40e_asq_cmd_details *cmd_details)
3331 {
3332         struct i40e_aq_desc desc;
3333         struct i40e_aqc_request_resource *cmd =
3334                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3335         enum i40e_status_code status;
3336
3337         DEBUGFUNC("i40e_aq_release_resource");
3338
3339         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3340
3341         cmd->resource_id = CPU_TO_LE16(resource);
3342         cmd->resource_number = CPU_TO_LE32(sdp_number);
3343
3344         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3345
3346         return status;
3347 }
3348
3349 /**
3350  * i40e_aq_read_nvm
3351  * @hw: pointer to the hw struct
3352  * @module_pointer: module pointer location in words from the NVM beginning
3353  * @offset: byte offset from the module beginning
3354  * @length: length of the section to be read (in bytes from the offset)
3355  * @data: command buffer (size [bytes] = length)
3356  * @last_command: tells if this is the last command in a series
3357  * @cmd_details: pointer to command details structure or NULL
3358  *
3359  * Read the NVM using the admin queue commands
3360  **/
3361 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3362                                 u32 offset, u16 length, void *data,
3363                                 bool last_command,
3364                                 struct i40e_asq_cmd_details *cmd_details)
3365 {
3366         struct i40e_aq_desc desc;
3367         struct i40e_aqc_nvm_update *cmd =
3368                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3369         enum i40e_status_code status;
3370
3371         DEBUGFUNC("i40e_aq_read_nvm");
3372
3373         /* In offset the highest byte must be zeroed. */
3374         if (offset & 0xFF000000) {
3375                 status = I40E_ERR_PARAM;
3376                 goto i40e_aq_read_nvm_exit;
3377         }
3378
3379         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3380
3381         /* If this is the last command in a series, set the proper flag. */
3382         if (last_command)
3383                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3384         cmd->module_pointer = module_pointer;
3385         cmd->offset = CPU_TO_LE32(offset);
3386         cmd->length = CPU_TO_LE16(length);
3387
3388         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3389         if (length > I40E_AQ_LARGE_BUF)
3390                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3391
3392         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3393
3394 i40e_aq_read_nvm_exit:
3395         return status;
3396 }
3397
3398 /**
3399  * i40e_aq_read_nvm_config - read an nvm config block
3400  * @hw: pointer to the hw struct
3401  * @cmd_flags: NVM access admin command bits
3402  * @field_id: field or feature id
3403  * @data: buffer for result
3404  * @buf_size: buffer size
3405  * @element_count: pointer to count of elements read by FW
3406  * @cmd_details: pointer to command details structure or NULL
3407  **/
3408 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3409                                 u8 cmd_flags, u32 field_id, void *data,
3410                                 u16 buf_size, u16 *element_count,
3411                                 struct i40e_asq_cmd_details *cmd_details)
3412 {
3413         struct i40e_aq_desc desc;
3414         struct i40e_aqc_nvm_config_read *cmd =
3415                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3416         enum i40e_status_code status;
3417
3418         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3419         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3420         if (buf_size > I40E_AQ_LARGE_BUF)
3421                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3422
3423         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3424         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3425         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3426                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3427         else
3428                 cmd->element_id_msw = 0;
3429
3430         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3431
3432         if (!status && element_count)
3433                 *element_count = LE16_TO_CPU(cmd->element_count);
3434
3435         return status;
3436 }
3437
3438 /**
3439  * i40e_aq_write_nvm_config - write an nvm config block
3440  * @hw: pointer to the hw struct
3441  * @cmd_flags: NVM access admin command bits
3442  * @data: buffer for result
3443  * @buf_size: buffer size
3444  * @element_count: count of elements to be written
3445  * @cmd_details: pointer to command details structure or NULL
3446  **/
3447 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3448                                 u8 cmd_flags, void *data, u16 buf_size,
3449                                 u16 element_count,
3450                                 struct i40e_asq_cmd_details *cmd_details)
3451 {
3452         struct i40e_aq_desc desc;
3453         struct i40e_aqc_nvm_config_write *cmd =
3454                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3455         enum i40e_status_code status;
3456
3457         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3458         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3459         if (buf_size > I40E_AQ_LARGE_BUF)
3460                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3461
3462         cmd->element_count = CPU_TO_LE16(element_count);
3463         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3464         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3465
3466         return status;
3467 }
3468
3469 /**
3470  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3471  * @hw: pointer to the hw struct
3472  * @cmd_details: pointer to command details structure or NULL
3473  **/
3474 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3475                                 void *buff, u16 buff_size,
3476                                 struct i40e_asq_cmd_details *cmd_details)
3477 {
3478         struct i40e_aq_desc desc;
3479         enum i40e_status_code status;
3480
3481         UNREFERENCED_2PARAMETER(buff, buff_size);
3482
3483         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3484         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3485         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3486                 status = I40E_ERR_NOT_IMPLEMENTED;
3487
3488         return status;
3489 }
3490
3491 /**
3492  * i40e_aq_erase_nvm
3493  * @hw: pointer to the hw struct
3494  * @module_pointer: module pointer location in words from the NVM beginning
3495  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3496  * @length: length of the section to be erased (expressed in 4 KB)
3497  * @last_command: tells if this is the last command in a series
3498  * @cmd_details: pointer to command details structure or NULL
3499  *
3500  * Erase the NVM sector using the admin queue commands
3501  **/
3502 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3503                                 u32 offset, u16 length, bool last_command,
3504                                 struct i40e_asq_cmd_details *cmd_details)
3505 {
3506         struct i40e_aq_desc desc;
3507         struct i40e_aqc_nvm_update *cmd =
3508                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3509         enum i40e_status_code status;
3510
3511         DEBUGFUNC("i40e_aq_erase_nvm");
3512
3513         /* In offset the highest byte must be zeroed. */
3514         if (offset & 0xFF000000) {
3515                 status = I40E_ERR_PARAM;
3516                 goto i40e_aq_erase_nvm_exit;
3517         }
3518
3519         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3520
3521         /* If this is the last command in a series, set the proper flag. */
3522         if (last_command)
3523                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3524         cmd->module_pointer = module_pointer;
3525         cmd->offset = CPU_TO_LE32(offset);
3526         cmd->length = CPU_TO_LE16(length);
3527
3528         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3529
3530 i40e_aq_erase_nvm_exit:
3531         return status;
3532 }
3533
3534 /**
3535  * i40e_parse_discover_capabilities
3536  * @hw: pointer to the hw struct
3537  * @buff: pointer to a buffer containing device/function capability records
3538  * @cap_count: number of capability records in the list
3539  * @list_type_opc: type of capabilities list to parse
3540  *
3541  * Parse the device/function capabilities list.
3542  **/
3543 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3544                                      u32 cap_count,
3545                                      enum i40e_admin_queue_opc list_type_opc)
3546 {
3547         struct i40e_aqc_list_capabilities_element_resp *cap;
3548         u32 valid_functions, num_functions;
3549         u32 number, logical_id, phys_id;
3550         struct i40e_hw_capabilities *p;
3551         u8 major_rev;
3552         u32 i = 0;
3553         u16 id;
3554
3555         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3556
3557         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3558                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3559         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3560                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3561         else
3562                 return;
3563
3564         for (i = 0; i < cap_count; i++, cap++) {
3565                 id = LE16_TO_CPU(cap->id);
3566                 number = LE32_TO_CPU(cap->number);
3567                 logical_id = LE32_TO_CPU(cap->logical_id);
3568                 phys_id = LE32_TO_CPU(cap->phys_id);
3569                 major_rev = cap->major_rev;
3570
3571                 switch (id) {
3572                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3573                         p->switch_mode = number;
3574                         i40e_debug(hw, I40E_DEBUG_INIT,
3575                                    "HW Capability: Switch mode = %d\n",
3576                                    p->switch_mode);
3577                         break;
3578                 case I40E_AQ_CAP_ID_MNG_MODE:
3579                         p->management_mode = number;
3580                         i40e_debug(hw, I40E_DEBUG_INIT,
3581                                    "HW Capability: Management Mode = %d\n",
3582                                    p->management_mode);
3583                         break;
3584                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3585                         p->npar_enable = number;
3586                         i40e_debug(hw, I40E_DEBUG_INIT,
3587                                    "HW Capability: NPAR enable = %d\n",
3588                                    p->npar_enable);
3589                         break;
3590                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3591                         p->os2bmc = number;
3592                         i40e_debug(hw, I40E_DEBUG_INIT,
3593                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3594                         break;
3595                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3596                         p->valid_functions = number;
3597                         i40e_debug(hw, I40E_DEBUG_INIT,
3598                                    "HW Capability: Valid Functions = %d\n",
3599                                    p->valid_functions);
3600                         break;
3601                 case I40E_AQ_CAP_ID_SRIOV:
3602                         if (number == 1)
3603                                 p->sr_iov_1_1 = true;
3604                         i40e_debug(hw, I40E_DEBUG_INIT,
3605                                    "HW Capability: SR-IOV = %d\n",
3606                                    p->sr_iov_1_1);
3607                         break;
3608                 case I40E_AQ_CAP_ID_VF:
3609                         p->num_vfs = number;
3610                         p->vf_base_id = logical_id;
3611                         i40e_debug(hw, I40E_DEBUG_INIT,
3612                                    "HW Capability: VF count = %d\n",
3613                                    p->num_vfs);
3614                         i40e_debug(hw, I40E_DEBUG_INIT,
3615                                    "HW Capability: VF base_id = %d\n",
3616                                    p->vf_base_id);
3617                         break;
3618                 case I40E_AQ_CAP_ID_VMDQ:
3619                         if (number == 1)
3620                                 p->vmdq = true;
3621                         i40e_debug(hw, I40E_DEBUG_INIT,
3622                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3623                         break;
3624                 case I40E_AQ_CAP_ID_8021QBG:
3625                         if (number == 1)
3626                                 p->evb_802_1_qbg = true;
3627                         i40e_debug(hw, I40E_DEBUG_INIT,
3628                                    "HW Capability: 802.1Qbg = %d\n", number);
3629                         break;
3630                 case I40E_AQ_CAP_ID_8021QBR:
3631                         if (number == 1)
3632                                 p->evb_802_1_qbh = true;
3633                         i40e_debug(hw, I40E_DEBUG_INIT,
3634                                    "HW Capability: 802.1Qbh = %d\n", number);
3635                         break;
3636                 case I40E_AQ_CAP_ID_VSI:
3637                         p->num_vsis = number;
3638                         i40e_debug(hw, I40E_DEBUG_INIT,
3639                                    "HW Capability: VSI count = %d\n",
3640                                    p->num_vsis);
3641                         break;
3642                 case I40E_AQ_CAP_ID_DCB:
3643                         if (number == 1) {
3644                                 p->dcb = true;
3645                                 p->enabled_tcmap = logical_id;
3646                                 p->maxtc = phys_id;
3647                         }
3648                         i40e_debug(hw, I40E_DEBUG_INIT,
3649                                    "HW Capability: DCB = %d\n", p->dcb);
3650                         i40e_debug(hw, I40E_DEBUG_INIT,
3651                                    "HW Capability: TC Mapping = %d\n",
3652                                    logical_id);
3653                         i40e_debug(hw, I40E_DEBUG_INIT,
3654                                    "HW Capability: TC Max = %d\n", p->maxtc);
3655                         break;
3656                 case I40E_AQ_CAP_ID_FCOE:
3657                         if (number == 1)
3658                                 p->fcoe = true;
3659                         i40e_debug(hw, I40E_DEBUG_INIT,
3660                                    "HW Capability: FCOE = %d\n", p->fcoe);
3661                         break;
3662                 case I40E_AQ_CAP_ID_ISCSI:
3663                         if (number == 1)
3664                                 p->iscsi = true;
3665                         i40e_debug(hw, I40E_DEBUG_INIT,
3666                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3667                         break;
3668                 case I40E_AQ_CAP_ID_RSS:
3669                         p->rss = true;
3670                         p->rss_table_size = number;
3671                         p->rss_table_entry_width = logical_id;
3672                         i40e_debug(hw, I40E_DEBUG_INIT,
3673                                    "HW Capability: RSS = %d\n", p->rss);
3674                         i40e_debug(hw, I40E_DEBUG_INIT,
3675                                    "HW Capability: RSS table size = %d\n",
3676                                    p->rss_table_size);
3677                         i40e_debug(hw, I40E_DEBUG_INIT,
3678                                    "HW Capability: RSS table width = %d\n",
3679                                    p->rss_table_entry_width);
3680                         break;
3681                 case I40E_AQ_CAP_ID_RXQ:
3682                         p->num_rx_qp = number;
3683                         p->base_queue = phys_id;
3684                         i40e_debug(hw, I40E_DEBUG_INIT,
3685                                    "HW Capability: Rx QP = %d\n", number);
3686                         i40e_debug(hw, I40E_DEBUG_INIT,
3687                                    "HW Capability: base_queue = %d\n",
3688                                    p->base_queue);
3689                         break;
3690                 case I40E_AQ_CAP_ID_TXQ:
3691                         p->num_tx_qp = number;
3692                         p->base_queue = phys_id;
3693                         i40e_debug(hw, I40E_DEBUG_INIT,
3694                                    "HW Capability: Tx QP = %d\n", number);
3695                         i40e_debug(hw, I40E_DEBUG_INIT,
3696                                    "HW Capability: base_queue = %d\n",
3697                                    p->base_queue);
3698                         break;
3699                 case I40E_AQ_CAP_ID_MSIX:
3700                         p->num_msix_vectors = number;
3701                         i40e_debug(hw, I40E_DEBUG_INIT,
3702                                    "HW Capability: MSIX vector count = %d\n",
3703                                    p->num_msix_vectors);
3704                         break;
3705                 case I40E_AQ_CAP_ID_VF_MSIX:
3706                         p->num_msix_vectors_vf = number;
3707                         i40e_debug(hw, I40E_DEBUG_INIT,
3708                                    "HW Capability: MSIX VF vector count = %d\n",
3709                                    p->num_msix_vectors_vf);
3710                         break;
3711                 case I40E_AQ_CAP_ID_FLEX10:
3712                         if (major_rev == 1) {
3713                                 if (number == 1) {
3714                                         p->flex10_enable = true;
3715                                         p->flex10_capable = true;
3716                                 }
3717                         } else {
3718                                 /* Capability revision >= 2 */
3719                                 if (number & 1)
3720                                         p->flex10_enable = true;
3721                                 if (number & 2)
3722                                         p->flex10_capable = true;
3723                         }
3724                         p->flex10_mode = logical_id;
3725                         p->flex10_status = phys_id;
3726                         i40e_debug(hw, I40E_DEBUG_INIT,
3727                                    "HW Capability: Flex10 mode = %d\n",
3728                                    p->flex10_mode);
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: Flex10 status = %d\n",
3731                                    p->flex10_status);
3732                         break;
3733                 case I40E_AQ_CAP_ID_CEM:
3734                         if (number == 1)
3735                                 p->mgmt_cem = true;
3736                         i40e_debug(hw, I40E_DEBUG_INIT,
3737                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3738                         break;
3739                 case I40E_AQ_CAP_ID_IWARP:
3740                         if (number == 1)
3741                                 p->iwarp = true;
3742                         i40e_debug(hw, I40E_DEBUG_INIT,
3743                                    "HW Capability: iWARP = %d\n", p->iwarp);
3744                         break;
3745                 case I40E_AQ_CAP_ID_LED:
3746                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3747                                 p->led[phys_id] = true;
3748                         i40e_debug(hw, I40E_DEBUG_INIT,
3749                                    "HW Capability: LED - PIN %d\n", phys_id);
3750                         break;
3751                 case I40E_AQ_CAP_ID_SDP:
3752                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3753                                 p->sdp[phys_id] = true;
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: SDP - PIN %d\n", phys_id);
3756                         break;
3757                 case I40E_AQ_CAP_ID_MDIO:
3758                         if (number == 1) {
3759                                 p->mdio_port_num = phys_id;
3760                                 p->mdio_port_mode = logical_id;
3761                         }
3762                         i40e_debug(hw, I40E_DEBUG_INIT,
3763                                    "HW Capability: MDIO port number = %d\n",
3764                                    p->mdio_port_num);
3765                         i40e_debug(hw, I40E_DEBUG_INIT,
3766                                    "HW Capability: MDIO port mode = %d\n",
3767                                    p->mdio_port_mode);
3768                         break;
3769                 case I40E_AQ_CAP_ID_1588:
3770                         if (number == 1)
3771                                 p->ieee_1588 = true;
3772                         i40e_debug(hw, I40E_DEBUG_INIT,
3773                                    "HW Capability: IEEE 1588 = %d\n",
3774                                    p->ieee_1588);
3775                         break;
3776                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3777                         p->fd = true;
3778                         p->fd_filters_guaranteed = number;
3779                         p->fd_filters_best_effort = logical_id;
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: Flow Director = 1\n");
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: Guaranteed FD filters = %d\n",
3784                                    p->fd_filters_guaranteed);
3785                         break;
3786                 case I40E_AQ_CAP_ID_WSR_PROT:
3787                         p->wr_csr_prot = (u64)number;
3788                         p->wr_csr_prot |= (u64)logical_id << 32;
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3791                                    (p->wr_csr_prot & 0xffff));
3792                         break;
3793                 case I40E_AQ_CAP_ID_NVM_MGMT:
3794                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3795                                 p->sec_rev_disabled = true;
3796                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3797                                 p->update_disabled = true;
3798                         break;
3799 #ifdef X722_SUPPORT
3800                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3801                         hw->num_wol_proxy_filters = (u16)number;
3802                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3803                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3804                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3805                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3806                         else
3807                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3808                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3809                         p->proxy_support = p->proxy_support;
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: WOL proxy filters = %d\n",
3812                                    hw->num_wol_proxy_filters);
3813                         break;
3814 #endif
3815                 default:
3816                         break;
3817                 }
3818         }
3819
3820         if (p->fcoe)
3821                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3822
3823         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3824         p->fcoe = false;
3825
3826         /* count the enabled ports (aka the "not disabled" ports) */
3827         hw->num_ports = 0;
3828         for (i = 0; i < 4; i++) {
3829                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3830                 u64 port_cfg = 0;
3831
3832                 /* use AQ read to get the physical register offset instead
3833                  * of the port relative offset
3834                  */
3835                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3836                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3837                         hw->num_ports++;
3838         }
3839
3840         valid_functions = p->valid_functions;
3841         num_functions = 0;
3842         while (valid_functions) {
3843                 if (valid_functions & 1)
3844                         num_functions++;
3845                 valid_functions >>= 1;
3846         }
3847
3848         /* partition id is 1-based, and functions are evenly spread
3849          * across the ports as partitions
3850          */
3851         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3852         hw->num_partitions = num_functions / hw->num_ports;
3853
3854         /* additional HW specific goodies that might
3855          * someday be HW version specific
3856          */
3857         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3858 }
3859
3860 /**
3861  * i40e_aq_discover_capabilities
3862  * @hw: pointer to the hw struct
3863  * @buff: a virtual buffer to hold the capabilities
3864  * @buff_size: Size of the virtual buffer
3865  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3866  * @list_type_opc: capabilities type to discover - pass in the command opcode
3867  * @cmd_details: pointer to command details structure or NULL
3868  *
3869  * Get the device capabilities descriptions from the firmware
3870  **/
3871 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3872                                 void *buff, u16 buff_size, u16 *data_size,
3873                                 enum i40e_admin_queue_opc list_type_opc,
3874                                 struct i40e_asq_cmd_details *cmd_details)
3875 {
3876         struct i40e_aqc_list_capabilites *cmd;
3877         struct i40e_aq_desc desc;
3878         enum i40e_status_code status = I40E_SUCCESS;
3879
3880         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3881
3882         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3883                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3884                 status = I40E_ERR_PARAM;
3885                 goto exit;
3886         }
3887
3888         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3889
3890         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3891         if (buff_size > I40E_AQ_LARGE_BUF)
3892                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3893
3894         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3895         *data_size = LE16_TO_CPU(desc.datalen);
3896
3897         if (status)
3898                 goto exit;
3899
3900         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3901                                          list_type_opc);
3902
3903 exit:
3904         return status;
3905 }
3906
3907 /**
3908  * i40e_aq_update_nvm
3909  * @hw: pointer to the hw struct
3910  * @module_pointer: module pointer location in words from the NVM beginning
3911  * @offset: byte offset from the module beginning
3912  * @length: length of the section to be written (in bytes from the offset)
3913  * @data: command buffer (size [bytes] = length)
3914  * @last_command: tells if this is the last command in a series
3915  * @cmd_details: pointer to command details structure or NULL
3916  *
3917  * Update the NVM using the admin queue commands
3918  **/
3919 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3920                                 u32 offset, u16 length, void *data,
3921                                 bool last_command,
3922                                 struct i40e_asq_cmd_details *cmd_details)
3923 {
3924         struct i40e_aq_desc desc;
3925         struct i40e_aqc_nvm_update *cmd =
3926                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3927         enum i40e_status_code status;
3928
3929         DEBUGFUNC("i40e_aq_update_nvm");
3930
3931         /* In offset the highest byte must be zeroed. */
3932         if (offset & 0xFF000000) {
3933                 status = I40E_ERR_PARAM;
3934                 goto i40e_aq_update_nvm_exit;
3935         }
3936
3937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3938
3939         /* If this is the last command in a series, set the proper flag. */
3940         if (last_command)
3941                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3942         cmd->module_pointer = module_pointer;
3943         cmd->offset = CPU_TO_LE32(offset);
3944         cmd->length = CPU_TO_LE16(length);
3945
3946         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3947         if (length > I40E_AQ_LARGE_BUF)
3948                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3949
3950         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3951
3952 i40e_aq_update_nvm_exit:
3953         return status;
3954 }
3955
3956 /**
3957  * i40e_aq_get_lldp_mib
3958  * @hw: pointer to the hw struct
3959  * @bridge_type: type of bridge requested
3960  * @mib_type: Local, Remote or both Local and Remote MIBs
3961  * @buff: pointer to a user supplied buffer to store the MIB block
3962  * @buff_size: size of the buffer (in bytes)
3963  * @local_len : length of the returned Local LLDP MIB
3964  * @remote_len: length of the returned Remote LLDP MIB
3965  * @cmd_details: pointer to command details structure or NULL
3966  *
3967  * Requests the complete LLDP MIB (entire packet).
3968  **/
3969 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3970                                 u8 mib_type, void *buff, u16 buff_size,
3971                                 u16 *local_len, u16 *remote_len,
3972                                 struct i40e_asq_cmd_details *cmd_details)
3973 {
3974         struct i40e_aq_desc desc;
3975         struct i40e_aqc_lldp_get_mib *cmd =
3976                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3977         struct i40e_aqc_lldp_get_mib *resp =
3978                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3979         enum i40e_status_code status;
3980
3981         if (buff_size == 0 || !buff)
3982                 return I40E_ERR_PARAM;
3983
3984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3985         /* Indirect Command */
3986         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3987
3988         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3989         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3990                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3991
3992         desc.datalen = CPU_TO_LE16(buff_size);
3993
3994         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3995         if (buff_size > I40E_AQ_LARGE_BUF)
3996                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3997
3998         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3999         if (!status) {
4000                 if (local_len != NULL)
4001                         *local_len = LE16_TO_CPU(resp->local_len);
4002                 if (remote_len != NULL)
4003                         *remote_len = LE16_TO_CPU(resp->remote_len);
4004         }
4005
4006         return status;
4007 }
4008
4009  /**
4010  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4011  * @hw: pointer to the hw struct
4012  * @mib_type: Local, Remote or both Local and Remote MIBs
4013  * @buff: pointer to a user supplied buffer to store the MIB block
4014  * @buff_size: size of the buffer (in bytes)
4015  * @cmd_details: pointer to command details structure or NULL
4016  *
4017  * Set the LLDP MIB.
4018  **/
4019 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4020                                 u8 mib_type, void *buff, u16 buff_size,
4021                                 struct i40e_asq_cmd_details *cmd_details)
4022 {
4023         struct i40e_aq_desc desc;
4024         struct i40e_aqc_lldp_set_local_mib *cmd =
4025                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4026         enum i40e_status_code status;
4027
4028         if (buff_size == 0 || !buff)
4029                 return I40E_ERR_PARAM;
4030
4031         i40e_fill_default_direct_cmd_desc(&desc,
4032                                 i40e_aqc_opc_lldp_set_local_mib);
4033         /* Indirect Command */
4034         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4035         if (buff_size > I40E_AQ_LARGE_BUF)
4036                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4037         desc.datalen = CPU_TO_LE16(buff_size);
4038
4039         cmd->type = mib_type;
4040         cmd->length = CPU_TO_LE16(buff_size);
4041         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4042         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4043
4044         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4045         return status;
4046 }
4047
4048 /**
4049  * i40e_aq_cfg_lldp_mib_change_event
4050  * @hw: pointer to the hw struct
4051  * @enable_update: Enable or Disable event posting
4052  * @cmd_details: pointer to command details structure or NULL
4053  *
4054  * Enable or Disable posting of an event on ARQ when LLDP MIB
4055  * associated with the interface changes
4056  **/
4057 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4058                                 bool enable_update,
4059                                 struct i40e_asq_cmd_details *cmd_details)
4060 {
4061         struct i40e_aq_desc desc;
4062         struct i40e_aqc_lldp_update_mib *cmd =
4063                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4064         enum i40e_status_code status;
4065
4066         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4067
4068         if (!enable_update)
4069                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4070
4071         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4072
4073         return status;
4074 }
4075
4076 /**
4077  * i40e_aq_add_lldp_tlv
4078  * @hw: pointer to the hw struct
4079  * @bridge_type: type of bridge
4080  * @buff: buffer with TLV to add
4081  * @buff_size: length of the buffer
4082  * @tlv_len: length of the TLV to be added
4083  * @mib_len: length of the LLDP MIB returned in response
4084  * @cmd_details: pointer to command details structure or NULL
4085  *
4086  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4087  * it is responsibility of the caller to make sure that the TLV is not
4088  * already present in the LLDPDU.
4089  * In return firmware will write the complete LLDP MIB with the newly
4090  * added TLV in the response buffer.
4091  **/
4092 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4093                                 void *buff, u16 buff_size, u16 tlv_len,
4094                                 u16 *mib_len,
4095                                 struct i40e_asq_cmd_details *cmd_details)
4096 {
4097         struct i40e_aq_desc desc;
4098         struct i40e_aqc_lldp_add_tlv *cmd =
4099                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4100         enum i40e_status_code status;
4101
4102         if (buff_size == 0 || !buff || tlv_len == 0)
4103                 return I40E_ERR_PARAM;
4104
4105         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4106
4107         /* Indirect Command */
4108         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4109         if (buff_size > I40E_AQ_LARGE_BUF)
4110                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4111         desc.datalen = CPU_TO_LE16(buff_size);
4112
4113         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4114                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4115         cmd->len = CPU_TO_LE16(tlv_len);
4116
4117         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4118         if (!status) {
4119                 if (mib_len != NULL)
4120                         *mib_len = LE16_TO_CPU(desc.datalen);
4121         }
4122
4123         return status;
4124 }
4125
4126 /**
4127  * i40e_aq_update_lldp_tlv
4128  * @hw: pointer to the hw struct
4129  * @bridge_type: type of bridge
4130  * @buff: buffer with TLV to update
4131  * @buff_size: size of the buffer holding original and updated TLVs
4132  * @old_len: Length of the Original TLV
4133  * @new_len: Length of the Updated TLV
4134  * @offset: offset of the updated TLV in the buff
4135  * @mib_len: length of the returned LLDP MIB
4136  * @cmd_details: pointer to command details structure or NULL
4137  *
4138  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4139  * Firmware will place the complete LLDP MIB in response buffer with the
4140  * updated TLV.
4141  **/
4142 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4143                                 u8 bridge_type, void *buff, u16 buff_size,
4144                                 u16 old_len, u16 new_len, u16 offset,
4145                                 u16 *mib_len,
4146                                 struct i40e_asq_cmd_details *cmd_details)
4147 {
4148         struct i40e_aq_desc desc;
4149         struct i40e_aqc_lldp_update_tlv *cmd =
4150                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4151         enum i40e_status_code status;
4152
4153         if (buff_size == 0 || !buff || offset == 0 ||
4154             old_len == 0 || new_len == 0)
4155                 return I40E_ERR_PARAM;
4156
4157         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4158
4159         /* Indirect Command */
4160         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4161         if (buff_size > I40E_AQ_LARGE_BUF)
4162                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4163         desc.datalen = CPU_TO_LE16(buff_size);
4164
4165         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4166                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4167         cmd->old_len = CPU_TO_LE16(old_len);
4168         cmd->new_offset = CPU_TO_LE16(offset);
4169         cmd->new_len = CPU_TO_LE16(new_len);
4170
4171         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4172         if (!status) {
4173                 if (mib_len != NULL)
4174                         *mib_len = LE16_TO_CPU(desc.datalen);
4175         }
4176
4177         return status;
4178 }
4179
4180 /**
4181  * i40e_aq_delete_lldp_tlv
4182  * @hw: pointer to the hw struct
4183  * @bridge_type: type of bridge
4184  * @buff: pointer to a user supplied buffer that has the TLV
4185  * @buff_size: length of the buffer
4186  * @tlv_len: length of the TLV to be deleted
4187  * @mib_len: length of the returned LLDP MIB
4188  * @cmd_details: pointer to command details structure or NULL
4189  *
4190  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4191  * The firmware places the entire LLDP MIB in the response buffer.
4192  **/
4193 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4194                                 u8 bridge_type, void *buff, u16 buff_size,
4195                                 u16 tlv_len, u16 *mib_len,
4196                                 struct i40e_asq_cmd_details *cmd_details)
4197 {
4198         struct i40e_aq_desc desc;
4199         struct i40e_aqc_lldp_add_tlv *cmd =
4200                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4201         enum i40e_status_code status;
4202
4203         if (buff_size == 0 || !buff)
4204                 return I40E_ERR_PARAM;
4205
4206         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4207
4208         /* Indirect Command */
4209         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4210         if (buff_size > I40E_AQ_LARGE_BUF)
4211                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4212         desc.datalen = CPU_TO_LE16(buff_size);
4213         cmd->len = CPU_TO_LE16(tlv_len);
4214         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4215                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4216
4217         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4218         if (!status) {
4219                 if (mib_len != NULL)
4220                         *mib_len = LE16_TO_CPU(desc.datalen);
4221         }
4222
4223         return status;
4224 }
4225
4226 /**
4227  * i40e_aq_stop_lldp
4228  * @hw: pointer to the hw struct
4229  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4230  * @cmd_details: pointer to command details structure or NULL
4231  *
4232  * Stop or Shutdown the embedded LLDP Agent
4233  **/
4234 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4235                                 struct i40e_asq_cmd_details *cmd_details)
4236 {
4237         struct i40e_aq_desc desc;
4238         struct i40e_aqc_lldp_stop *cmd =
4239                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4240         enum i40e_status_code status;
4241
4242         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4243
4244         if (shutdown_agent)
4245                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4246
4247         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4248
4249         return status;
4250 }
4251
4252 /**
4253  * i40e_aq_start_lldp
4254  * @hw: pointer to the hw struct
4255  * @cmd_details: pointer to command details structure or NULL
4256  *
4257  * Start the embedded LLDP Agent on all ports.
4258  **/
4259 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4260                                 struct i40e_asq_cmd_details *cmd_details)
4261 {
4262         struct i40e_aq_desc desc;
4263         struct i40e_aqc_lldp_start *cmd =
4264                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4265         enum i40e_status_code status;
4266
4267         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4268
4269         cmd->command = I40E_AQ_LLDP_AGENT_START;
4270
4271         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4272
4273         return status;
4274 }
4275
4276 /**
4277  * i40e_aq_get_cee_dcb_config
4278  * @hw: pointer to the hw struct
4279  * @buff: response buffer that stores CEE operational configuration
4280  * @buff_size: size of the buffer passed
4281  * @cmd_details: pointer to command details structure or NULL
4282  *
4283  * Get CEE DCBX mode operational configuration from firmware
4284  **/
4285 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4286                                 void *buff, u16 buff_size,
4287                                 struct i40e_asq_cmd_details *cmd_details)
4288 {
4289         struct i40e_aq_desc desc;
4290         enum i40e_status_code status;
4291
4292         if (buff_size == 0 || !buff)
4293                 return I40E_ERR_PARAM;
4294
4295         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4296
4297         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4298         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4299                                        cmd_details);
4300
4301         return status;
4302 }
4303
4304 /**
4305  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4306  * @hw: pointer to the hw struct
4307  * @start_agent: True if DCBx Agent needs to be Started
4308  *                              False if DCBx Agent needs to be Stopped
4309  * @cmd_details: pointer to command details structure or NULL
4310  *
4311  * Start/Stop the embedded dcbx Agent
4312  **/
4313 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4314                                 bool start_agent,
4315                                 struct i40e_asq_cmd_details *cmd_details)
4316 {
4317         struct i40e_aq_desc desc;
4318         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4319                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4320                                 &desc.params.raw;
4321         enum i40e_status_code status;
4322
4323         i40e_fill_default_direct_cmd_desc(&desc,
4324                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4325
4326         if (start_agent)
4327                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4328
4329         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4330
4331         return status;
4332 }
4333
4334 /**
4335  * i40e_aq_add_udp_tunnel
4336  * @hw: pointer to the hw struct
4337  * @udp_port: the UDP port to add
4338  * @header_len: length of the tunneling header length in DWords
4339  * @protocol_index: protocol index type
4340  * @filter_index: pointer to filter index
4341  * @cmd_details: pointer to command details structure or NULL
4342  **/
4343 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4344                                 u16 udp_port, u8 protocol_index,
4345                                 u8 *filter_index,
4346                                 struct i40e_asq_cmd_details *cmd_details)
4347 {
4348         struct i40e_aq_desc desc;
4349         struct i40e_aqc_add_udp_tunnel *cmd =
4350                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4351         struct i40e_aqc_del_udp_tunnel_completion *resp =
4352                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4353         enum i40e_status_code status;
4354
4355         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4356
4357         cmd->udp_port = CPU_TO_LE16(udp_port);
4358         cmd->protocol_type = protocol_index;
4359
4360         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4361
4362         if (!status && filter_index)
4363                 *filter_index = resp->index;
4364
4365         return status;
4366 }
4367
4368 /**
4369  * i40e_aq_del_udp_tunnel
4370  * @hw: pointer to the hw struct
4371  * @index: filter index
4372  * @cmd_details: pointer to command details structure or NULL
4373  **/
4374 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4375                                 struct i40e_asq_cmd_details *cmd_details)
4376 {
4377         struct i40e_aq_desc desc;
4378         struct i40e_aqc_remove_udp_tunnel *cmd =
4379                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4380         enum i40e_status_code status;
4381
4382         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4383
4384         cmd->index = index;
4385
4386         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4387
4388         return status;
4389 }
4390
4391 /**
4392  * i40e_aq_get_switch_resource_alloc (0x0204)
4393  * @hw: pointer to the hw struct
4394  * @num_entries: pointer to u8 to store the number of resource entries returned
4395  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4396  *        to store the resource information for all resource types.  Each
4397  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4398  * @count: size, in bytes, of the buffer provided
4399  * @cmd_details: pointer to command details structure or NULL
4400  *
4401  * Query the resources allocated to a function.
4402  **/
4403 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4404                         u8 *num_entries,
4405                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4406                         u16 count,
4407                         struct i40e_asq_cmd_details *cmd_details)
4408 {
4409         struct i40e_aq_desc desc;
4410         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4411                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4412         enum i40e_status_code status;
4413         u16 length = count * sizeof(*buf);
4414
4415         i40e_fill_default_direct_cmd_desc(&desc,
4416                                         i40e_aqc_opc_get_switch_resource_alloc);
4417
4418         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4419         if (length > I40E_AQ_LARGE_BUF)
4420                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4421
4422         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4423
4424         if (!status && num_entries)
4425                 *num_entries = cmd_resp->num_entries;
4426
4427         return status;
4428 }
4429
4430 /**
4431  * i40e_aq_delete_element - Delete switch element
4432  * @hw: pointer to the hw struct
4433  * @seid: the SEID to delete from the switch
4434  * @cmd_details: pointer to command details structure or NULL
4435  *
4436  * This deletes a switch element from the switch.
4437  **/
4438 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4439                                 struct i40e_asq_cmd_details *cmd_details)
4440 {
4441         struct i40e_aq_desc desc;
4442         struct i40e_aqc_switch_seid *cmd =
4443                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4444         enum i40e_status_code status;
4445
4446         if (seid == 0)
4447                 return I40E_ERR_PARAM;
4448
4449         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4450
4451         cmd->seid = CPU_TO_LE16(seid);
4452
4453         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4454
4455         return status;
4456 }
4457
4458 /**
4459  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4460  * @hw: pointer to the hw struct
4461  * @flags: component flags
4462  * @mac_seid: uplink seid (MAC SEID)
4463  * @vsi_seid: connected vsi seid
4464  * @ret_seid: seid of create pv component
4465  *
4466  * This instantiates an i40e port virtualizer with specified flags.
4467  * Depending on specified flags the port virtualizer can act as a
4468  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4469  */
4470 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4471                                        u16 mac_seid, u16 vsi_seid,
4472                                        u16 *ret_seid)
4473 {
4474         struct i40e_aq_desc desc;
4475         struct i40e_aqc_add_update_pv *cmd =
4476                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4477         struct i40e_aqc_add_update_pv_completion *resp =
4478                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4479         enum i40e_status_code status;
4480
4481         if (vsi_seid == 0)
4482                 return I40E_ERR_PARAM;
4483
4484         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4485         cmd->command_flags = CPU_TO_LE16(flags);
4486         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4487         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4488
4489         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4490         if (!status && ret_seid)
4491                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4492
4493         return status;
4494 }
4495
4496 /**
4497  * i40e_aq_add_tag - Add an S/E-tag
4498  * @hw: pointer to the hw struct
4499  * @direct_to_queue: should s-tag direct flow to a specific queue
4500  * @vsi_seid: VSI SEID to use this tag
4501  * @tag: value of the tag
4502  * @queue_num: queue number, only valid is direct_to_queue is true
4503  * @tags_used: return value, number of tags in use by this PF
4504  * @tags_free: return value, number of unallocated tags
4505  * @cmd_details: pointer to command details structure or NULL
4506  *
4507  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4508  * the number of tags allocated by the PF, and the number of unallocated
4509  * tags available.
4510  **/
4511 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4512                                 u16 vsi_seid, u16 tag, u16 queue_num,
4513                                 u16 *tags_used, u16 *tags_free,
4514                                 struct i40e_asq_cmd_details *cmd_details)
4515 {
4516         struct i40e_aq_desc desc;
4517         struct i40e_aqc_add_tag *cmd =
4518                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4519         struct i40e_aqc_add_remove_tag_completion *resp =
4520                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4521         enum i40e_status_code status;
4522
4523         if (vsi_seid == 0)
4524                 return I40E_ERR_PARAM;
4525
4526         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4527
4528         cmd->seid = CPU_TO_LE16(vsi_seid);
4529         cmd->tag = CPU_TO_LE16(tag);
4530         if (direct_to_queue) {
4531                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4532                 cmd->queue_number = CPU_TO_LE16(queue_num);
4533         }
4534
4535         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4536
4537         if (!status) {
4538                 if (tags_used != NULL)
4539                         *tags_used = LE16_TO_CPU(resp->tags_used);
4540                 if (tags_free != NULL)
4541                         *tags_free = LE16_TO_CPU(resp->tags_free);
4542         }
4543
4544         return status;
4545 }
4546
4547 /**
4548  * i40e_aq_remove_tag - Remove an S- or E-tag
4549  * @hw: pointer to the hw struct
4550  * @vsi_seid: VSI SEID this tag is associated with
4551  * @tag: value of the S-tag to delete
4552  * @tags_used: return value, number of tags in use by this PF
4553  * @tags_free: return value, number of unallocated tags
4554  * @cmd_details: pointer to command details structure or NULL
4555  *
4556  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4557  * the number of tags allocated by the PF, and the number of unallocated
4558  * tags available.
4559  **/
4560 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4561                                 u16 tag, u16 *tags_used, u16 *tags_free,
4562                                 struct i40e_asq_cmd_details *cmd_details)
4563 {
4564         struct i40e_aq_desc desc;
4565         struct i40e_aqc_remove_tag *cmd =
4566                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4567         struct i40e_aqc_add_remove_tag_completion *resp =
4568                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4569         enum i40e_status_code status;
4570
4571         if (vsi_seid == 0)
4572                 return I40E_ERR_PARAM;
4573
4574         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4575
4576         cmd->seid = CPU_TO_LE16(vsi_seid);
4577         cmd->tag = CPU_TO_LE16(tag);
4578
4579         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4580
4581         if (!status) {
4582                 if (tags_used != NULL)
4583                         *tags_used = LE16_TO_CPU(resp->tags_used);
4584                 if (tags_free != NULL)
4585                         *tags_free = LE16_TO_CPU(resp->tags_free);
4586         }
4587
4588         return status;
4589 }
4590
4591 /**
4592  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4593  * @hw: pointer to the hw struct
4594  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4595  * @etag: value of E-tag to add
4596  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4597  * @buf: address of indirect buffer
4598  * @tags_used: return value, number of E-tags in use by this port
4599  * @tags_free: return value, number of unallocated M-tags
4600  * @cmd_details: pointer to command details structure or NULL
4601  *
4602  * This associates a multicast E-tag to a port virtualizer.  It will return
4603  * the number of tags allocated by the PF, and the number of unallocated
4604  * tags available.
4605  *
4606  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4607  * num_tags_in_buf long.
4608  **/
4609 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4610                                 u16 etag, u8 num_tags_in_buf, void *buf,
4611                                 u16 *tags_used, u16 *tags_free,
4612                                 struct i40e_asq_cmd_details *cmd_details)
4613 {
4614         struct i40e_aq_desc desc;
4615         struct i40e_aqc_add_remove_mcast_etag *cmd =
4616                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4617         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4618            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4619         enum i40e_status_code status;
4620         u16 length = sizeof(u16) * num_tags_in_buf;
4621
4622         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4623                 return I40E_ERR_PARAM;
4624
4625         i40e_fill_default_direct_cmd_desc(&desc,
4626                                           i40e_aqc_opc_add_multicast_etag);
4627
4628         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4629         cmd->etag = CPU_TO_LE16(etag);
4630         cmd->num_unicast_etags = num_tags_in_buf;
4631
4632         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4633         if (length > I40E_AQ_LARGE_BUF)
4634                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4635
4636         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4637
4638         if (!status) {
4639                 if (tags_used != NULL)
4640                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4641                 if (tags_free != NULL)
4642                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4643         }
4644
4645         return status;
4646 }
4647
4648 /**
4649  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4650  * @hw: pointer to the hw struct
4651  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4652  * @etag: value of the E-tag to remove
4653  * @tags_used: return value, number of tags in use by this port
4654  * @tags_free: return value, number of unallocated tags
4655  * @cmd_details: pointer to command details structure or NULL
4656  *
4657  * This deletes an E-tag from the port virtualizer.  It will return
4658  * the number of tags allocated by the port, and the number of unallocated
4659  * tags available.
4660  **/
4661 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4662                                 u16 etag, u16 *tags_used, u16 *tags_free,
4663                                 struct i40e_asq_cmd_details *cmd_details)
4664 {
4665         struct i40e_aq_desc desc;
4666         struct i40e_aqc_add_remove_mcast_etag *cmd =
4667                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4668         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4669            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4670         enum i40e_status_code status;
4671
4672
4673         if (pv_seid == 0)
4674                 return I40E_ERR_PARAM;
4675
4676         i40e_fill_default_direct_cmd_desc(&desc,
4677                                           i40e_aqc_opc_remove_multicast_etag);
4678
4679         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4680         cmd->etag = CPU_TO_LE16(etag);
4681
4682         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4683
4684         if (!status) {
4685                 if (tags_used != NULL)
4686                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4687                 if (tags_free != NULL)
4688                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4689         }
4690
4691         return status;
4692 }
4693
4694 /**
4695  * i40e_aq_update_tag - Update an S/E-tag
4696  * @hw: pointer to the hw struct
4697  * @vsi_seid: VSI SEID using this S-tag
4698  * @old_tag: old tag value
4699  * @new_tag: new tag value
4700  * @tags_used: return value, number of tags in use by this PF
4701  * @tags_free: return value, number of unallocated tags
4702  * @cmd_details: pointer to command details structure or NULL
4703  *
4704  * This updates the value of the tag currently attached to this VSI
4705  * in the switch complex.  It will return the number of tags allocated
4706  * by the PF, and the number of unallocated tags available.
4707  **/
4708 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4709                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4710                                 u16 *tags_free,
4711                                 struct i40e_asq_cmd_details *cmd_details)
4712 {
4713         struct i40e_aq_desc desc;
4714         struct i40e_aqc_update_tag *cmd =
4715                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4716         struct i40e_aqc_update_tag_completion *resp =
4717                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4718         enum i40e_status_code status;
4719
4720         if (vsi_seid == 0)
4721                 return I40E_ERR_PARAM;
4722
4723         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4724
4725         cmd->seid = CPU_TO_LE16(vsi_seid);
4726         cmd->old_tag = CPU_TO_LE16(old_tag);
4727         cmd->new_tag = CPU_TO_LE16(new_tag);
4728
4729         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4730
4731         if (!status) {
4732                 if (tags_used != NULL)
4733                         *tags_used = LE16_TO_CPU(resp->tags_used);
4734                 if (tags_free != NULL)
4735                         *tags_free = LE16_TO_CPU(resp->tags_free);
4736         }
4737
4738         return status;
4739 }
4740
4741 /**
4742  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4743  * @hw: pointer to the hw struct
4744  * @tcmap: TC map for request/release any ignore PFC condition
4745  * @request: request or release ignore PFC condition
4746  * @tcmap_ret: return TCs for which PFC is currently ignored
4747  * @cmd_details: pointer to command details structure or NULL
4748  *
4749  * This sends out request/release to ignore PFC condition for a TC.
4750  * It will return the TCs for which PFC is currently ignored.
4751  **/
4752 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4753                                 bool request, u8 *tcmap_ret,
4754                                 struct i40e_asq_cmd_details *cmd_details)
4755 {
4756         struct i40e_aq_desc desc;
4757         struct i40e_aqc_pfc_ignore *cmd_resp =
4758                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4759         enum i40e_status_code status;
4760
4761         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4762
4763         if (request)
4764                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4765
4766         cmd_resp->tc_bitmap = tcmap;
4767
4768         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4769
4770         if (!status) {
4771                 if (tcmap_ret != NULL)
4772                         *tcmap_ret = cmd_resp->tc_bitmap;
4773         }
4774
4775         return status;
4776 }
4777
4778 /**
4779  * i40e_aq_dcb_updated - DCB Updated Command
4780  * @hw: pointer to the hw struct
4781  * @cmd_details: pointer to command details structure or NULL
4782  *
4783  * When LLDP is handled in PF this command is used by the PF
4784  * to notify EMP that a DCB setting is modified.
4785  * When LLDP is handled in EMP this command is used by the PF
4786  * to notify EMP whenever one of the following parameters get
4787  * modified:
4788  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4789  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4790  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4791  * EMP will return when the shared RPB settings have been
4792  * recomputed and modified. The retval field in the descriptor
4793  * will be set to 0 when RPB is modified.
4794  **/
4795 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4796                                 struct i40e_asq_cmd_details *cmd_details)
4797 {
4798         struct i40e_aq_desc desc;
4799         enum i40e_status_code status;
4800
4801         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4802
4803         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4804
4805         return status;
4806 }
4807
4808 /**
4809  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4810  * @hw: pointer to the hw struct
4811  * @seid: defines the SEID of the switch for which the stats are requested
4812  * @vlan_id: the VLAN ID for which the statistics are requested
4813  * @stat_index: index of the statistics counters block assigned to this VLAN
4814  * @cmd_details: pointer to command details structure or NULL
4815  *
4816  * XL710 supports 128 smonVlanStats counters.This command is used to
4817  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4818  * switch.
4819  **/
4820 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4821                                 u16 vlan_id, u16 *stat_index,
4822                                 struct i40e_asq_cmd_details *cmd_details)
4823 {
4824         struct i40e_aq_desc desc;
4825         struct i40e_aqc_add_remove_statistics *cmd_resp =
4826                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4827         enum i40e_status_code status;
4828
4829         if ((seid == 0) || (stat_index == NULL))
4830                 return I40E_ERR_PARAM;
4831
4832         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4833
4834         cmd_resp->seid = CPU_TO_LE16(seid);
4835         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4836
4837         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4838
4839         if (!status && stat_index)
4840                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4841
4842         return status;
4843 }
4844
4845 /**
4846  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4847  * @hw: pointer to the hw struct
4848  * @seid: defines the SEID of the switch for which the stats are requested
4849  * @vlan_id: the VLAN ID for which the statistics are requested
4850  * @stat_index: index of the statistics counters block assigned to this VLAN
4851  * @cmd_details: pointer to command details structure or NULL
4852  *
4853  * XL710 supports 128 smonVlanStats counters.This command is used to
4854  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4855  * switch.
4856  **/
4857 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4858                                 u16 vlan_id, u16 stat_index,
4859                                 struct i40e_asq_cmd_details *cmd_details)
4860 {
4861         struct i40e_aq_desc desc;
4862         struct i40e_aqc_add_remove_statistics *cmd =
4863                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4864         enum i40e_status_code status;
4865
4866         if (seid == 0)
4867                 return I40E_ERR_PARAM;
4868
4869         i40e_fill_default_direct_cmd_desc(&desc,
4870                                           i40e_aqc_opc_remove_statistics);
4871
4872         cmd->seid = CPU_TO_LE16(seid);
4873         cmd->vlan  = CPU_TO_LE16(vlan_id);
4874         cmd->stat_index = CPU_TO_LE16(stat_index);
4875
4876         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4877
4878         return status;
4879 }
4880
4881 /**
4882  * i40e_aq_set_port_parameters - set physical port parameters.
4883  * @hw: pointer to the hw struct
4884  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4885  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4886  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4887  * @double_vlan: if set double VLAN is enabled
4888  * @cmd_details: pointer to command details structure or NULL
4889  **/
4890 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4891                                 u16 bad_frame_vsi, bool save_bad_pac,
4892                                 bool pad_short_pac, bool double_vlan,
4893                                 struct i40e_asq_cmd_details *cmd_details)
4894 {
4895         struct i40e_aqc_set_port_parameters *cmd;
4896         enum i40e_status_code status;
4897         struct i40e_aq_desc desc;
4898         u16 command_flags = 0;
4899
4900         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4901
4902         i40e_fill_default_direct_cmd_desc(&desc,
4903                                           i40e_aqc_opc_set_port_parameters);
4904
4905         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4906         if (save_bad_pac)
4907                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4908         if (pad_short_pac)
4909                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4910         if (double_vlan)
4911                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4912         cmd->command_flags = CPU_TO_LE16(command_flags);
4913
4914         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4915
4916         return status;
4917 }
4918
4919 /**
4920  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4921  * @hw: pointer to the hw struct
4922  * @seid: seid for the physical port/switching component/vsi
4923  * @buff: Indirect buffer to hold data parameters and response
4924  * @buff_size: Indirect buffer size
4925  * @opcode: Tx scheduler AQ command opcode
4926  * @cmd_details: pointer to command details structure or NULL
4927  *
4928  * Generic command handler for Tx scheduler AQ commands
4929  **/
4930 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4931                                 void *buff, u16 buff_size,
4932                                  enum i40e_admin_queue_opc opcode,
4933                                 struct i40e_asq_cmd_details *cmd_details)
4934 {
4935         struct i40e_aq_desc desc;
4936         struct i40e_aqc_tx_sched_ind *cmd =
4937                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4938         enum i40e_status_code status;
4939         bool cmd_param_flag = false;
4940
4941         switch (opcode) {
4942         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4943         case i40e_aqc_opc_configure_vsi_tc_bw:
4944         case i40e_aqc_opc_enable_switching_comp_ets:
4945         case i40e_aqc_opc_modify_switching_comp_ets:
4946         case i40e_aqc_opc_disable_switching_comp_ets:
4947         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4948         case i40e_aqc_opc_configure_switching_comp_bw_config:
4949                 cmd_param_flag = true;
4950                 break;
4951         case i40e_aqc_opc_query_vsi_bw_config:
4952         case i40e_aqc_opc_query_vsi_ets_sla_config:
4953         case i40e_aqc_opc_query_switching_comp_ets_config:
4954         case i40e_aqc_opc_query_port_ets_config:
4955         case i40e_aqc_opc_query_switching_comp_bw_config:
4956                 cmd_param_flag = false;
4957                 break;
4958         default:
4959                 return I40E_ERR_PARAM;
4960         }
4961
4962         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4963
4964         /* Indirect command */
4965         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4966         if (cmd_param_flag)
4967                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4968         if (buff_size > I40E_AQ_LARGE_BUF)
4969                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4970
4971         desc.datalen = CPU_TO_LE16(buff_size);
4972
4973         cmd->vsi_seid = CPU_TO_LE16(seid);
4974
4975         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4976
4977         return status;
4978 }
4979
4980 /**
4981  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4982  * @hw: pointer to the hw struct
4983  * @seid: VSI seid
4984  * @credit: BW limit credits (0 = disabled)
4985  * @max_credit: Max BW limit credits
4986  * @cmd_details: pointer to command details structure or NULL
4987  **/
4988 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4989                                 u16 seid, u16 credit, u8 max_credit,
4990                                 struct i40e_asq_cmd_details *cmd_details)
4991 {
4992         struct i40e_aq_desc desc;
4993         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4994                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4995         enum i40e_status_code status;
4996
4997         i40e_fill_default_direct_cmd_desc(&desc,
4998                                           i40e_aqc_opc_configure_vsi_bw_limit);
4999
5000         cmd->vsi_seid = CPU_TO_LE16(seid);
5001         cmd->credit = CPU_TO_LE16(credit);
5002         cmd->max_credit = max_credit;
5003
5004         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5005
5006         return status;
5007 }
5008
5009 /**
5010  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5011  * @hw: pointer to the hw struct
5012  * @seid: switching component seid
5013  * @credit: BW limit credits (0 = disabled)
5014  * @max_bw: Max BW limit credits
5015  * @cmd_details: pointer to command details structure or NULL
5016  **/
5017 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5018                                 u16 seid, u16 credit, u8 max_bw,
5019                                 struct i40e_asq_cmd_details *cmd_details)
5020 {
5021         struct i40e_aq_desc desc;
5022         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5023           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5024         enum i40e_status_code status;
5025
5026         i40e_fill_default_direct_cmd_desc(&desc,
5027                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5028
5029         cmd->seid = CPU_TO_LE16(seid);
5030         cmd->credit = CPU_TO_LE16(credit);
5031         cmd->max_bw = max_bw;
5032
5033         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5034
5035         return status;
5036 }
5037
5038 /**
5039  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5040  * @hw: pointer to the hw struct
5041  * @seid: VSI seid
5042  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5043  * @cmd_details: pointer to command details structure or NULL
5044  **/
5045 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5046                         u16 seid,
5047                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5048                         struct i40e_asq_cmd_details *cmd_details)
5049 {
5050         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5051                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5052                                     cmd_details);
5053 }
5054
5055 /**
5056  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5057  * @hw: pointer to the hw struct
5058  * @seid: VSI seid
5059  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5060  * @cmd_details: pointer to command details structure or NULL
5061  **/
5062 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5063                         u16 seid,
5064                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5065                         struct i40e_asq_cmd_details *cmd_details)
5066 {
5067         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5068                                     i40e_aqc_opc_configure_vsi_tc_bw,
5069                                     cmd_details);
5070 }
5071
5072 /**
5073  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5074  * @hw: pointer to the hw struct
5075  * @seid: seid of the switching component connected to Physical Port
5076  * @ets_data: Buffer holding ETS parameters
5077  * @cmd_details: pointer to command details structure or NULL
5078  **/
5079 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5080                 u16 seid,
5081                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5082                 enum i40e_admin_queue_opc opcode,
5083                 struct i40e_asq_cmd_details *cmd_details)
5084 {
5085         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5086                                     sizeof(*ets_data), opcode, cmd_details);
5087 }
5088
5089 /**
5090  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5091  * @hw: pointer to the hw struct
5092  * @seid: seid of the switching component
5093  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5094  * @cmd_details: pointer to command details structure or NULL
5095  **/
5096 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5097         u16 seid,
5098         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5099         struct i40e_asq_cmd_details *cmd_details)
5100 {
5101         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5102                             i40e_aqc_opc_configure_switching_comp_bw_config,
5103                             cmd_details);
5104 }
5105
5106 /**
5107  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5108  * @hw: pointer to the hw struct
5109  * @seid: seid of the switching component
5110  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5111  * @cmd_details: pointer to command details structure or NULL
5112  **/
5113 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5114         struct i40e_hw *hw, u16 seid,
5115         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5116         struct i40e_asq_cmd_details *cmd_details)
5117 {
5118         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5119                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5120                             cmd_details);
5121 }
5122
5123 /**
5124  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5125  * @hw: pointer to the hw struct
5126  * @seid: seid of the VSI
5127  * @bw_data: Buffer to hold VSI BW configuration
5128  * @cmd_details: pointer to command details structure or NULL
5129  **/
5130 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5131                         u16 seid,
5132                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5133                         struct i40e_asq_cmd_details *cmd_details)
5134 {
5135         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5136                                     i40e_aqc_opc_query_vsi_bw_config,
5137                                     cmd_details);
5138 }
5139
5140 /**
5141  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5142  * @hw: pointer to the hw struct
5143  * @seid: seid of the VSI
5144  * @bw_data: Buffer to hold VSI BW configuration per TC
5145  * @cmd_details: pointer to command details structure or NULL
5146  **/
5147 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5148                         u16 seid,
5149                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5150                         struct i40e_asq_cmd_details *cmd_details)
5151 {
5152         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5153                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5154                                     cmd_details);
5155 }
5156
5157 /**
5158  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5159  * @hw: pointer to the hw struct
5160  * @seid: seid of the switching component
5161  * @bw_data: Buffer to hold switching component's per TC BW config
5162  * @cmd_details: pointer to command details structure or NULL
5163  **/
5164 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5165                 u16 seid,
5166                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5167                 struct i40e_asq_cmd_details *cmd_details)
5168 {
5169         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5170                                    i40e_aqc_opc_query_switching_comp_ets_config,
5171                                    cmd_details);
5172 }
5173
5174 /**
5175  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5176  * @hw: pointer to the hw struct
5177  * @seid: seid of the VSI or switching component connected to Physical Port
5178  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5179  * @cmd_details: pointer to command details structure or NULL
5180  **/
5181 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5182                         u16 seid,
5183                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5184                         struct i40e_asq_cmd_details *cmd_details)
5185 {
5186         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5187                                     i40e_aqc_opc_query_port_ets_config,
5188                                     cmd_details);
5189 }
5190
5191 /**
5192  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5193  * @hw: pointer to the hw struct
5194  * @seid: seid of the switching component
5195  * @bw_data: Buffer to hold switching component's BW configuration
5196  * @cmd_details: pointer to command details structure or NULL
5197  **/
5198 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5199                 u16 seid,
5200                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5201                 struct i40e_asq_cmd_details *cmd_details)
5202 {
5203         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5204                                     i40e_aqc_opc_query_switching_comp_bw_config,
5205                                     cmd_details);
5206 }
5207
5208 /**
5209  * i40e_validate_filter_settings
5210  * @hw: pointer to the hardware structure
5211  * @settings: Filter control settings
5212  *
5213  * Check and validate the filter control settings passed.
5214  * The function checks for the valid filter/context sizes being
5215  * passed for FCoE and PE.
5216  *
5217  * Returns I40E_SUCCESS if the values passed are valid and within
5218  * range else returns an error.
5219  **/
5220 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5221                                 struct i40e_filter_control_settings *settings)
5222 {
5223         u32 fcoe_cntx_size, fcoe_filt_size;
5224         u32 pe_cntx_size, pe_filt_size;
5225         u32 fcoe_fmax;
5226
5227         u32 val;
5228
5229         /* Validate FCoE settings passed */
5230         switch (settings->fcoe_filt_num) {
5231         case I40E_HASH_FILTER_SIZE_1K:
5232         case I40E_HASH_FILTER_SIZE_2K:
5233         case I40E_HASH_FILTER_SIZE_4K:
5234         case I40E_HASH_FILTER_SIZE_8K:
5235         case I40E_HASH_FILTER_SIZE_16K:
5236         case I40E_HASH_FILTER_SIZE_32K:
5237                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5238                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5239                 break;
5240         default:
5241                 return I40E_ERR_PARAM;
5242         }
5243
5244         switch (settings->fcoe_cntx_num) {
5245         case I40E_DMA_CNTX_SIZE_512:
5246         case I40E_DMA_CNTX_SIZE_1K:
5247         case I40E_DMA_CNTX_SIZE_2K:
5248         case I40E_DMA_CNTX_SIZE_4K:
5249                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5250                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5251                 break;
5252         default:
5253                 return I40E_ERR_PARAM;
5254         }
5255
5256         /* Validate PE settings passed */
5257         switch (settings->pe_filt_num) {
5258         case I40E_HASH_FILTER_SIZE_1K:
5259         case I40E_HASH_FILTER_SIZE_2K:
5260         case I40E_HASH_FILTER_SIZE_4K:
5261         case I40E_HASH_FILTER_SIZE_8K:
5262         case I40E_HASH_FILTER_SIZE_16K:
5263         case I40E_HASH_FILTER_SIZE_32K:
5264         case I40E_HASH_FILTER_SIZE_64K:
5265         case I40E_HASH_FILTER_SIZE_128K:
5266         case I40E_HASH_FILTER_SIZE_256K:
5267         case I40E_HASH_FILTER_SIZE_512K:
5268         case I40E_HASH_FILTER_SIZE_1M:
5269                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5270                 pe_filt_size <<= (u32)settings->pe_filt_num;
5271                 break;
5272         default:
5273                 return I40E_ERR_PARAM;
5274         }
5275
5276         switch (settings->pe_cntx_num) {
5277         case I40E_DMA_CNTX_SIZE_512:
5278         case I40E_DMA_CNTX_SIZE_1K:
5279         case I40E_DMA_CNTX_SIZE_2K:
5280         case I40E_DMA_CNTX_SIZE_4K:
5281         case I40E_DMA_CNTX_SIZE_8K:
5282         case I40E_DMA_CNTX_SIZE_16K:
5283         case I40E_DMA_CNTX_SIZE_32K:
5284         case I40E_DMA_CNTX_SIZE_64K:
5285         case I40E_DMA_CNTX_SIZE_128K:
5286         case I40E_DMA_CNTX_SIZE_256K:
5287                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5288                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5289                 break;
5290         default:
5291                 return I40E_ERR_PARAM;
5292         }
5293
5294         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5295         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5296         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5297                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5298         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5299                 return I40E_ERR_INVALID_SIZE;
5300
5301         return I40E_SUCCESS;
5302 }
5303
5304 /**
5305  * i40e_set_filter_control
5306  * @hw: pointer to the hardware structure
5307  * @settings: Filter control settings
5308  *
5309  * Set the Queue Filters for PE/FCoE and enable filters required
5310  * for a single PF. It is expected that these settings are programmed
5311  * at the driver initialization time.
5312  **/
5313 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5314                                 struct i40e_filter_control_settings *settings)
5315 {
5316         enum i40e_status_code ret = I40E_SUCCESS;
5317         u32 hash_lut_size = 0;
5318         u32 val;
5319
5320         if (!settings)
5321                 return I40E_ERR_PARAM;
5322
5323         /* Validate the input settings */
5324         ret = i40e_validate_filter_settings(hw, settings);
5325         if (ret)
5326                 return ret;
5327
5328         /* Read the PF Queue Filter control register */
5329         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5330
5331         /* Program required PE hash buckets for the PF */
5332         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5333         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5334                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5335         /* Program required PE contexts for the PF */
5336         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5337         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5338                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5339
5340         /* Program required FCoE hash buckets for the PF */
5341         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5342         val |= ((u32)settings->fcoe_filt_num <<
5343                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5344                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5345         /* Program required FCoE DDP contexts for the PF */
5346         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5347         val |= ((u32)settings->fcoe_cntx_num <<
5348                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5349                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5350
5351         /* Program Hash LUT size for the PF */
5352         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5353         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5354                 hash_lut_size = 1;
5355         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5356                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5357
5358         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5359         if (settings->enable_fdir)
5360                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5361         if (settings->enable_ethtype)
5362                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5363         if (settings->enable_macvlan)
5364                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5365
5366         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5367
5368         return I40E_SUCCESS;
5369 }
5370
5371 /**
5372  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5373  * @hw: pointer to the hw struct
5374  * @mac_addr: MAC address to use in the filter
5375  * @ethtype: Ethertype to use in the filter
5376  * @flags: Flags that needs to be applied to the filter
5377  * @vsi_seid: seid of the control VSI
5378  * @queue: VSI queue number to send the packet to
5379  * @is_add: Add control packet filter if True else remove
5380  * @stats: Structure to hold information on control filter counts
5381  * @cmd_details: pointer to command details structure or NULL
5382  *
5383  * This command will Add or Remove control packet filter for a control VSI.
5384  * In return it will update the total number of perfect filter count in
5385  * the stats member.
5386  **/
5387 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5388                                 u8 *mac_addr, u16 ethtype, u16 flags,
5389                                 u16 vsi_seid, u16 queue, bool is_add,
5390                                 struct i40e_control_filter_stats *stats,
5391                                 struct i40e_asq_cmd_details *cmd_details)
5392 {
5393         struct i40e_aq_desc desc;
5394         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5395                 (struct i40e_aqc_add_remove_control_packet_filter *)
5396                 &desc.params.raw;
5397         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5398                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5399                 &desc.params.raw;
5400         enum i40e_status_code status;
5401
5402         if (vsi_seid == 0)
5403                 return I40E_ERR_PARAM;
5404
5405         if (is_add) {
5406                 i40e_fill_default_direct_cmd_desc(&desc,
5407                                 i40e_aqc_opc_add_control_packet_filter);
5408                 cmd->queue = CPU_TO_LE16(queue);
5409         } else {
5410                 i40e_fill_default_direct_cmd_desc(&desc,
5411                                 i40e_aqc_opc_remove_control_packet_filter);
5412         }
5413
5414         if (mac_addr)
5415                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5416                             I40E_NONDMA_TO_NONDMA);
5417
5418         cmd->etype = CPU_TO_LE16(ethtype);
5419         cmd->flags = CPU_TO_LE16(flags);
5420         cmd->seid = CPU_TO_LE16(vsi_seid);
5421
5422         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5423
5424         if (!status && stats) {
5425                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5426                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5427                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5428                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5429         }
5430
5431         return status;
5432 }
5433
5434 /**
5435  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5436  * @hw: pointer to the hw struct
5437  * @seid: VSI seid to add ethertype filter from
5438  **/
5439 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5440 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5441                                                     u16 seid)
5442 {
5443         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5444                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5445                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5446         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5447         enum i40e_status_code status;
5448
5449         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5450                                                        seid, 0, true, NULL,
5451                                                        NULL);
5452         if (status)
5453                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5454 }
5455
5456 /**
5457  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5458  * @filters: list of cloud filters
5459  * @filter_count: length of list
5460  *
5461  * There's an issue in the device where the Geneve VNI layout needs
5462  * to be shifted 1 byte over from the VxLAN VNI
5463  **/
5464 STATIC void i40e_fix_up_geneve_vni(
5465         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5466         u8 filter_count)
5467 {
5468         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5469         int i;
5470
5471         for (i = 0; i < filter_count; i++) {
5472                 u16 tnl_type;
5473                 u32 ti;
5474
5475                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5476                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5477                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5478                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5479                         ti = LE32_TO_CPU(f[i].tenant_id);
5480                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5481                 }
5482         }
5483 }
5484
5485 /**
5486  * i40e_aq_add_cloud_filters
5487  * @hw: pointer to the hardware structure
5488  * @seid: VSI seid to add cloud filters from
5489  * @filters: Buffer which contains the filters to be added
5490  * @filter_count: number of filters contained in the buffer
5491  *
5492  * Set the cloud filters for a given VSI.  The contents of the
5493  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5494  * in by the caller of the function.
5495  *
5496  **/
5497 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5498         u16 seid,
5499         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5500         u8 filter_count)
5501 {
5502         struct i40e_aq_desc desc;
5503         struct i40e_aqc_add_remove_cloud_filters *cmd =
5504         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5505         enum i40e_status_code status;
5506         u16 buff_len;
5507
5508         i40e_fill_default_direct_cmd_desc(&desc,
5509                                           i40e_aqc_opc_add_cloud_filters);
5510
5511         buff_len = filter_count * sizeof(*filters);
5512         desc.datalen = CPU_TO_LE16(buff_len);
5513         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5514         cmd->num_filters = filter_count;
5515         cmd->seid = CPU_TO_LE16(seid);
5516
5517         i40e_fix_up_geneve_vni(filters, filter_count);
5518
5519         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5520
5521         return status;
5522 }
5523
5524 /**
5525  * i40e_aq_remove_cloud_filters
5526  * @hw: pointer to the hardware structure
5527  * @seid: VSI seid to remove cloud filters from
5528  * @filters: Buffer which contains the filters to be removed
5529  * @filter_count: number of filters contained in the buffer
5530  *
5531  * Remove the cloud filters for a given VSI.  The contents of the
5532  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5533  * in by the caller of the function.
5534  *
5535  **/
5536 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5537                 u16 seid,
5538                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5539                 u8 filter_count)
5540 {
5541         struct i40e_aq_desc desc;
5542         struct i40e_aqc_add_remove_cloud_filters *cmd =
5543         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5544         enum i40e_status_code status;
5545         u16 buff_len;
5546
5547         i40e_fill_default_direct_cmd_desc(&desc,
5548                                           i40e_aqc_opc_remove_cloud_filters);
5549
5550         buff_len = filter_count * sizeof(*filters);
5551         desc.datalen = CPU_TO_LE16(buff_len);
5552         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5553         cmd->num_filters = filter_count;
5554         cmd->seid = CPU_TO_LE16(seid);
5555
5556         i40e_fix_up_geneve_vni(filters, filter_count);
5557
5558         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5559
5560         return status;
5561 }
5562
5563 /**
5564  * i40e_aq_alternate_write
5565  * @hw: pointer to the hardware structure
5566  * @reg_addr0: address of first dword to be read
5567  * @reg_val0: value to be written under 'reg_addr0'
5568  * @reg_addr1: address of second dword to be read
5569  * @reg_val1: value to be written under 'reg_addr1'
5570  *
5571  * Write one or two dwords to alternate structure. Fields are indicated
5572  * by 'reg_addr0' and 'reg_addr1' register numbers.
5573  *
5574  **/
5575 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5576                                 u32 reg_addr0, u32 reg_val0,
5577                                 u32 reg_addr1, u32 reg_val1)
5578 {
5579         struct i40e_aq_desc desc;
5580         struct i40e_aqc_alternate_write *cmd_resp =
5581                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5582         enum i40e_status_code status;
5583
5584         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5585         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5586         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5587         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5588         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5589
5590         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5591
5592         return status;
5593 }
5594
5595 /**
5596  * i40e_aq_alternate_write_indirect
5597  * @hw: pointer to the hardware structure
5598  * @addr: address of a first register to be modified
5599  * @dw_count: number of alternate structure fields to write
5600  * @buffer: pointer to the command buffer
5601  *
5602  * Write 'dw_count' dwords from 'buffer' to alternate structure
5603  * starting at 'addr'.
5604  *
5605  **/
5606 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5607                                 u32 addr, u32 dw_count, void *buffer)
5608 {
5609         struct i40e_aq_desc desc;
5610         struct i40e_aqc_alternate_ind_write *cmd_resp =
5611                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5612         enum i40e_status_code status;
5613
5614         if (buffer == NULL)
5615                 return I40E_ERR_PARAM;
5616
5617         /* Indirect command */
5618         i40e_fill_default_direct_cmd_desc(&desc,
5619                                          i40e_aqc_opc_alternate_write_indirect);
5620
5621         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5622         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5623         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5624                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5625
5626         cmd_resp->address = CPU_TO_LE32(addr);
5627         cmd_resp->length = CPU_TO_LE32(dw_count);
5628
5629         status = i40e_asq_send_command(hw, &desc, buffer,
5630                                        I40E_LO_DWORD(4*dw_count), NULL);
5631
5632         return status;
5633 }
5634
5635 /**
5636  * i40e_aq_alternate_read
5637  * @hw: pointer to the hardware structure
5638  * @reg_addr0: address of first dword to be read
5639  * @reg_val0: pointer for data read from 'reg_addr0'
5640  * @reg_addr1: address of second dword to be read
5641  * @reg_val1: pointer for data read from 'reg_addr1'
5642  *
5643  * Read one or two dwords from alternate structure. Fields are indicated
5644  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5645  * is not passed then only register at 'reg_addr0' is read.
5646  *
5647  **/
5648 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5649                                 u32 reg_addr0, u32 *reg_val0,
5650                                 u32 reg_addr1, u32 *reg_val1)
5651 {
5652         struct i40e_aq_desc desc;
5653         struct i40e_aqc_alternate_write *cmd_resp =
5654                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5655         enum i40e_status_code status;
5656
5657         if (reg_val0 == NULL)
5658                 return I40E_ERR_PARAM;
5659
5660         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5661         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5662         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5663
5664         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5665
5666         if (status == I40E_SUCCESS) {
5667                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5668
5669                 if (reg_val1 != NULL)
5670                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5671         }
5672
5673         return status;
5674 }
5675
5676 /**
5677  * i40e_aq_alternate_read_indirect
5678  * @hw: pointer to the hardware structure
5679  * @addr: address of the alternate structure field
5680  * @dw_count: number of alternate structure fields to read
5681  * @buffer: pointer to the command buffer
5682  *
5683  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5684  * place them in 'buffer'. The buffer should be allocated by caller.
5685  *
5686  **/
5687 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5688                                 u32 addr, u32 dw_count, void *buffer)
5689 {
5690         struct i40e_aq_desc desc;
5691         struct i40e_aqc_alternate_ind_write *cmd_resp =
5692                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5693         enum i40e_status_code status;
5694
5695         if (buffer == NULL)
5696                 return I40E_ERR_PARAM;
5697
5698         /* Indirect command */
5699         i40e_fill_default_direct_cmd_desc(&desc,
5700                 i40e_aqc_opc_alternate_read_indirect);
5701
5702         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5703         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5704         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5705                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5706
5707         cmd_resp->address = CPU_TO_LE32(addr);
5708         cmd_resp->length = CPU_TO_LE32(dw_count);
5709
5710         status = i40e_asq_send_command(hw, &desc, buffer,
5711                                        I40E_LO_DWORD(4*dw_count), NULL);
5712
5713         return status;
5714 }
5715
5716 /**
5717  *  i40e_aq_alternate_clear
5718  *  @hw: pointer to the HW structure.
5719  *
5720  *  Clear the alternate structures of the port from which the function
5721  *  is called.
5722  *
5723  **/
5724 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5725 {
5726         struct i40e_aq_desc desc;
5727         enum i40e_status_code status;
5728
5729         i40e_fill_default_direct_cmd_desc(&desc,
5730                                           i40e_aqc_opc_alternate_clear_port);
5731
5732         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5733
5734         return status;
5735 }
5736
5737 /**
5738  *  i40e_aq_alternate_write_done
5739  *  @hw: pointer to the HW structure.
5740  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5741  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5742  *
5743  *  Indicates to the FW that alternate structures have been changed.
5744  *
5745  **/
5746 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5747                 u8 bios_mode, bool *reset_needed)
5748 {
5749         struct i40e_aq_desc desc;
5750         struct i40e_aqc_alternate_write_done *cmd =
5751                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5752         enum i40e_status_code status;
5753
5754         if (reset_needed == NULL)
5755                 return I40E_ERR_PARAM;
5756
5757         i40e_fill_default_direct_cmd_desc(&desc,
5758                                           i40e_aqc_opc_alternate_write_done);
5759
5760         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5761
5762         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5763         if (!status && reset_needed)
5764                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5765                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5766
5767         return status;
5768 }
5769
5770 /**
5771  *  i40e_aq_set_oem_mode
5772  *  @hw: pointer to the HW structure.
5773  *  @oem_mode: the OEM mode to be used
5774  *
5775  *  Sets the device to a specific operating mode. Currently the only supported
5776  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5777  *
5778  **/
5779 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5780                 u8 oem_mode)
5781 {
5782         struct i40e_aq_desc desc;
5783         struct i40e_aqc_alternate_write_done *cmd =
5784                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5785         enum i40e_status_code status;
5786
5787         i40e_fill_default_direct_cmd_desc(&desc,
5788                                           i40e_aqc_opc_alternate_set_mode);
5789
5790         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5791
5792         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5793
5794         return status;
5795 }
5796
5797 /**
5798  * i40e_aq_resume_port_tx
5799  * @hw: pointer to the hardware structure
5800  * @cmd_details: pointer to command details structure or NULL
5801  *
5802  * Resume port's Tx traffic
5803  **/
5804 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5805                                 struct i40e_asq_cmd_details *cmd_details)
5806 {
5807         struct i40e_aq_desc desc;
5808         enum i40e_status_code status;
5809
5810         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5811
5812         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5813
5814         return status;
5815 }
5816
5817 /**
5818  * i40e_set_pci_config_data - store PCI bus info
5819  * @hw: pointer to hardware structure
5820  * @link_status: the link status word from PCI config space
5821  *
5822  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5823  **/
5824 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5825 {
5826         hw->bus.type = i40e_bus_type_pci_express;
5827
5828         switch (link_status & I40E_PCI_LINK_WIDTH) {
5829         case I40E_PCI_LINK_WIDTH_1:
5830                 hw->bus.width = i40e_bus_width_pcie_x1;
5831                 break;
5832         case I40E_PCI_LINK_WIDTH_2:
5833                 hw->bus.width = i40e_bus_width_pcie_x2;
5834                 break;
5835         case I40E_PCI_LINK_WIDTH_4:
5836                 hw->bus.width = i40e_bus_width_pcie_x4;
5837                 break;
5838         case I40E_PCI_LINK_WIDTH_8:
5839                 hw->bus.width = i40e_bus_width_pcie_x8;
5840                 break;
5841         default:
5842                 hw->bus.width = i40e_bus_width_unknown;
5843                 break;
5844         }
5845
5846         switch (link_status & I40E_PCI_LINK_SPEED) {
5847         case I40E_PCI_LINK_SPEED_2500:
5848                 hw->bus.speed = i40e_bus_speed_2500;
5849                 break;
5850         case I40E_PCI_LINK_SPEED_5000:
5851                 hw->bus.speed = i40e_bus_speed_5000;
5852                 break;
5853         case I40E_PCI_LINK_SPEED_8000:
5854                 hw->bus.speed = i40e_bus_speed_8000;
5855                 break;
5856         default:
5857                 hw->bus.speed = i40e_bus_speed_unknown;
5858                 break;
5859         }
5860 }
5861
5862 /**
5863  * i40e_aq_debug_dump
5864  * @hw: pointer to the hardware structure
5865  * @cluster_id: specific cluster to dump
5866  * @table_id: table id within cluster
5867  * @start_index: index of line in the block to read
5868  * @buff_size: dump buffer size
5869  * @buff: dump buffer
5870  * @ret_buff_size: actual buffer size returned
5871  * @ret_next_table: next block to read
5872  * @ret_next_index: next index to read
5873  *
5874  * Dump internal FW/HW data for debug purposes.
5875  *
5876  **/
5877 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5878                                 u8 table_id, u32 start_index, u16 buff_size,
5879                                 void *buff, u16 *ret_buff_size,
5880                                 u8 *ret_next_table, u32 *ret_next_index,
5881                                 struct i40e_asq_cmd_details *cmd_details)
5882 {
5883         struct i40e_aq_desc desc;
5884         struct i40e_aqc_debug_dump_internals *cmd =
5885                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5886         struct i40e_aqc_debug_dump_internals *resp =
5887                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5888         enum i40e_status_code status;
5889
5890         if (buff_size == 0 || !buff)
5891                 return I40E_ERR_PARAM;
5892
5893         i40e_fill_default_direct_cmd_desc(&desc,
5894                                           i40e_aqc_opc_debug_dump_internals);
5895         /* Indirect Command */
5896         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5897         if (buff_size > I40E_AQ_LARGE_BUF)
5898                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5899
5900         cmd->cluster_id = cluster_id;
5901         cmd->table_id = table_id;
5902         cmd->idx = CPU_TO_LE32(start_index);
5903
5904         desc.datalen = CPU_TO_LE16(buff_size);
5905
5906         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5907         if (!status) {
5908                 if (ret_buff_size != NULL)
5909                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5910                 if (ret_next_table != NULL)
5911                         *ret_next_table = resp->table_id;
5912                 if (ret_next_index != NULL)
5913                         *ret_next_index = LE32_TO_CPU(resp->idx);
5914         }
5915
5916         return status;
5917 }
5918
5919 /**
5920  * i40e_read_bw_from_alt_ram
5921  * @hw: pointer to the hardware structure
5922  * @max_bw: pointer for max_bw read
5923  * @min_bw: pointer for min_bw read
5924  * @min_valid: pointer for bool that is true if min_bw is a valid value
5925  * @max_valid: pointer for bool that is true if max_bw is a valid value
5926  *
5927  * Read bw from the alternate ram for the given pf
5928  **/
5929 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5930                                         u32 *max_bw, u32 *min_bw,
5931                                         bool *min_valid, bool *max_valid)
5932 {
5933         enum i40e_status_code status;
5934         u32 max_bw_addr, min_bw_addr;
5935
5936         /* Calculate the address of the min/max bw registers */
5937         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5938                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5939                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5940         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5941                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5942                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5943
5944         /* Read the bandwidths from alt ram */
5945         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5946                                         min_bw_addr, min_bw);
5947
5948         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5949                 *min_valid = true;
5950         else
5951                 *min_valid = false;
5952
5953         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5954                 *max_valid = true;
5955         else
5956                 *max_valid = false;
5957
5958         return status;
5959 }
5960
5961 /**
5962  * i40e_aq_configure_partition_bw
5963  * @hw: pointer to the hardware structure
5964  * @bw_data: Buffer holding valid pfs and bw limits
5965  * @cmd_details: pointer to command details
5966  *
5967  * Configure partitions guaranteed/max bw
5968  **/
5969 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5970                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5971                         struct i40e_asq_cmd_details *cmd_details)
5972 {
5973         enum i40e_status_code status;
5974         struct i40e_aq_desc desc;
5975         u16 bwd_size = sizeof(*bw_data);
5976
5977         i40e_fill_default_direct_cmd_desc(&desc,
5978                                 i40e_aqc_opc_configure_partition_bw);
5979
5980         /* Indirect command */
5981         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5982         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5983
5984         if (bwd_size > I40E_AQ_LARGE_BUF)
5985                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5986
5987         desc.datalen = CPU_TO_LE16(bwd_size);
5988
5989         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5990
5991         return status;
5992 }
5993
5994 /**
5995  * i40e_read_phy_register
5996  * @hw: pointer to the HW structure
5997  * @page: registers page number
5998  * @reg: register address in the page
5999  * @phy_adr: PHY address on MDIO interface
6000  * @value: PHY register value
6001  *
6002  * Reads specified PHY register value
6003  **/
6004 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6005                                              u8 page, u16 reg, u8 phy_addr,
6006                                              u16 *value)
6007 {
6008         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6009         u32 command  = 0;
6010         u16 retry = 1000;
6011         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6012
6013         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6014                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6015                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6016                   (I40E_MDIO_OPCODE_ADDRESS) |
6017                   (I40E_MDIO_STCODE) |
6018                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6019                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6020         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6021         do {
6022                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6023                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6024                         status = I40E_SUCCESS;
6025                         break;
6026                 }
6027                 i40e_usec_delay(10);
6028                 retry--;
6029         } while (retry);
6030
6031         if (status) {
6032                 i40e_debug(hw, I40E_DEBUG_PHY,
6033                            "PHY: Can't write command to external PHY.\n");
6034                 goto phy_read_end;
6035         }
6036
6037         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6038                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6039                   (I40E_MDIO_OPCODE_READ) |
6040                   (I40E_MDIO_STCODE) |
6041                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6042                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6043         status = I40E_ERR_TIMEOUT;
6044         retry = 1000;
6045         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6046         do {
6047                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6048                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6049                         status = I40E_SUCCESS;
6050                         break;
6051                 }
6052                 i40e_usec_delay(10);
6053                 retry--;
6054         } while (retry);
6055
6056         if (!status) {
6057                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6058                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6059                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6060         } else {
6061                 i40e_debug(hw, I40E_DEBUG_PHY,
6062                            "PHY: Can't read register value from external PHY.\n");
6063         }
6064
6065 phy_read_end:
6066         return status;
6067 }
6068
6069 /**
6070  * i40e_write_phy_register
6071  * @hw: pointer to the HW structure
6072  * @page: registers page number
6073  * @reg: register address in the page
6074  * @phy_adr: PHY address on MDIO interface
6075  * @value: PHY register value
6076  *
6077  * Writes value to specified PHY register
6078  **/
6079 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6080                                               u8 page, u16 reg, u8 phy_addr,
6081                                               u16 value)
6082 {
6083         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6084         u32 command  = 0;
6085         u16 retry = 1000;
6086         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6087
6088         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6089                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6090                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6091                   (I40E_MDIO_OPCODE_ADDRESS) |
6092                   (I40E_MDIO_STCODE) |
6093                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6094                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6095         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6096         do {
6097                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6098                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6099                         status = I40E_SUCCESS;
6100                         break;
6101                 }
6102                 i40e_usec_delay(10);
6103                 retry--;
6104         } while (retry);
6105         if (status) {
6106                 i40e_debug(hw, I40E_DEBUG_PHY,
6107                            "PHY: Can't write command to external PHY.\n");
6108                 goto phy_write_end;
6109         }
6110
6111         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6112         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6113
6114         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6115                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6116                   (I40E_MDIO_OPCODE_WRITE) |
6117                   (I40E_MDIO_STCODE) |
6118                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6119                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6120         status = I40E_ERR_TIMEOUT;
6121         retry = 1000;
6122         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6123         do {
6124                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6125                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6126                         status = I40E_SUCCESS;
6127                         break;
6128                 }
6129                 i40e_usec_delay(10);
6130                 retry--;
6131         } while (retry);
6132
6133 phy_write_end:
6134         return status;
6135 }
6136
6137 /**
6138  * i40e_get_phy_address
6139  * @hw: pointer to the HW structure
6140  * @dev_num: PHY port num that address we want
6141  * @phy_addr: Returned PHY address
6142  *
6143  * Gets PHY address for current port
6144  **/
6145 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6146 {
6147         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6148         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6149
6150         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6151 }
6152
6153 /**
6154  * i40e_blink_phy_led
6155  * @hw: pointer to the HW structure
6156  * @time: time how long led will blinks in secs
6157  * @interval: gap between LED on and off in msecs
6158  *
6159  * Blinks PHY link LED
6160  **/
6161 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6162                                               u32 time, u32 interval)
6163 {
6164         enum i40e_status_code status = I40E_SUCCESS;
6165         u32 i;
6166         u16 led_ctl = 0;
6167         u16 gpio_led_port;
6168         u16 led_reg;
6169         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6170         u8 phy_addr = 0;
6171         u8 port_num;
6172
6173         i = rd32(hw, I40E_PFGEN_PORTNUM);
6174         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6175         phy_addr = i40e_get_phy_address(hw, port_num);
6176
6177         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6178              led_addr++) {
6179                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6180                                                 led_addr, phy_addr, &led_reg);
6181                 if (status)
6182                         goto phy_blinking_end;
6183                 led_ctl = led_reg;
6184                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6185                         led_reg = 0;
6186                         status = i40e_write_phy_register(hw,
6187                                                          I40E_PHY_COM_REG_PAGE,
6188                                                          led_addr, phy_addr,
6189                                                          led_reg);
6190                         if (status)
6191                                 goto phy_blinking_end;
6192                         break;
6193                 }
6194         }
6195
6196         if (time > 0 && interval > 0) {
6197                 for (i = 0; i < time * 1000; i += interval) {
6198                         status = i40e_read_phy_register(hw,
6199                                                         I40E_PHY_COM_REG_PAGE,
6200                                                         led_addr, phy_addr,
6201                                                         &led_reg);
6202                         if (status)
6203                                 goto restore_config;
6204                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6205                                 led_reg = 0;
6206                         else
6207                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6208                         status = i40e_write_phy_register(hw,
6209                                                          I40E_PHY_COM_REG_PAGE,
6210                                                          led_addr, phy_addr,
6211                                                          led_reg);
6212                         if (status)
6213                                 goto restore_config;
6214                         i40e_msec_delay(interval);
6215                 }
6216         }
6217
6218 restore_config:
6219         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6220                                          phy_addr, led_ctl);
6221
6222 phy_blinking_end:
6223         return status;
6224 }
6225
6226 /**
6227  * i40e_led_get_phy - return current on/off mode
6228  * @hw: pointer to the hw struct
6229  * @led_addr: address of led register to use
6230  * @val: original value of register to use
6231  *
6232  **/
6233 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6234                                        u16 *val)
6235 {
6236         enum i40e_status_code status = I40E_SUCCESS;
6237         u16 gpio_led_port;
6238         u8 phy_addr = 0;
6239         u16 reg_val;
6240         u16 temp_addr;
6241         u8 port_num;
6242         u32 i;
6243
6244         temp_addr = I40E_PHY_LED_PROV_REG_1;
6245         i = rd32(hw, I40E_PFGEN_PORTNUM);
6246         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6247         phy_addr = i40e_get_phy_address(hw, port_num);
6248
6249         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6250              temp_addr++) {
6251                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6252                                                 temp_addr, phy_addr, &reg_val);
6253                 if (status)
6254                         return status;
6255                 *val = reg_val;
6256                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6257                         *led_addr = temp_addr;
6258                         break;
6259                 }
6260         }
6261         return status;
6262 }
6263
6264 /**
6265  * i40e_led_set_phy
6266  * @hw: pointer to the HW structure
6267  * @on: true or false
6268  * @mode: original val plus bit for set or ignore
6269  * Set led's on or off when controlled by the PHY
6270  *
6271  **/
6272 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6273                                        u16 led_addr, u32 mode)
6274 {
6275         enum i40e_status_code status = I40E_SUCCESS;
6276         u16 led_ctl = 0;
6277         u16 led_reg = 0;
6278         u8 phy_addr = 0;
6279         u8 port_num;
6280         u32 i;
6281
6282         i = rd32(hw, I40E_PFGEN_PORTNUM);
6283         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6284         phy_addr = i40e_get_phy_address(hw, port_num);
6285
6286         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6287                                         phy_addr, &led_reg);
6288         if (status)
6289                 return status;
6290         led_ctl = led_reg;
6291         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6292                 led_reg = 0;
6293                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6294                                                  led_addr, phy_addr, led_reg);
6295                 if (status)
6296                         return status;
6297         }
6298         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6299                                         led_addr, phy_addr, &led_reg);
6300         if (status)
6301                 goto restore_config;
6302         if (on)
6303                 led_reg = I40E_PHY_LED_MANUAL_ON;
6304         else
6305                 led_reg = 0;
6306         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6307                                          led_addr, phy_addr, led_reg);
6308         if (status)
6309                 goto restore_config;
6310         if (mode & I40E_PHY_LED_MODE_ORIG) {
6311                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6312                 status = i40e_write_phy_register(hw,
6313                                                  I40E_PHY_COM_REG_PAGE,
6314                                                  led_addr, phy_addr, led_ctl);
6315         }
6316         return status;
6317 restore_config:
6318         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6319                                          phy_addr, led_ctl);
6320         return status;
6321 }
6322 #endif /* PF_DRIVER */
6323
6324 /**
6325  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6326  * @hw: pointer to the hw struct
6327  * @reg_addr: register address
6328  * @reg_val: ptr to register value
6329  * @cmd_details: pointer to command details structure or NULL
6330  *
6331  * Use the firmware to read the Rx control register,
6332  * especially useful if the Rx unit is under heavy pressure
6333  **/
6334 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6335                                 u32 reg_addr, u32 *reg_val,
6336                                 struct i40e_asq_cmd_details *cmd_details)
6337 {
6338         struct i40e_aq_desc desc;
6339         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6340                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6341         enum i40e_status_code status;
6342
6343         if (reg_val == NULL)
6344                 return I40E_ERR_PARAM;
6345
6346         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6347
6348         cmd_resp->address = CPU_TO_LE32(reg_addr);
6349
6350         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6351
6352         if (status == I40E_SUCCESS)
6353                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6354
6355         return status;
6356 }
6357
6358 /**
6359  * i40e_read_rx_ctl - read from an Rx control register
6360  * @hw: pointer to the hw struct
6361  * @reg_addr: register address
6362  **/
6363 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6364 {
6365         enum i40e_status_code status = I40E_SUCCESS;
6366         bool use_register;
6367         int retry = 5;
6368         u32 val = 0;
6369
6370         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6371         if (!use_register) {
6372 do_retry:
6373                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6374                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6375                         i40e_msec_delay(1);
6376                         retry--;
6377                         goto do_retry;
6378                 }
6379         }
6380
6381         /* if the AQ access failed, try the old-fashioned way */
6382         if (status || use_register)
6383                 val = rd32(hw, reg_addr);
6384
6385         return val;
6386 }
6387
6388 /**
6389  * i40e_aq_rx_ctl_write_register
6390  * @hw: pointer to the hw struct
6391  * @reg_addr: register address
6392  * @reg_val: register value
6393  * @cmd_details: pointer to command details structure or NULL
6394  *
6395  * Use the firmware to write to an Rx control register,
6396  * especially useful if the Rx unit is under heavy pressure
6397  **/
6398 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6399                                 u32 reg_addr, u32 reg_val,
6400                                 struct i40e_asq_cmd_details *cmd_details)
6401 {
6402         struct i40e_aq_desc desc;
6403         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6404                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6405         enum i40e_status_code status;
6406
6407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6408
6409         cmd->address = CPU_TO_LE32(reg_addr);
6410         cmd->value = CPU_TO_LE32(reg_val);
6411
6412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6413
6414         return status;
6415 }
6416
6417 /**
6418  * i40e_write_rx_ctl - write to an Rx control register
6419  * @hw: pointer to the hw struct
6420  * @reg_addr: register address
6421  * @reg_val: register value
6422  **/
6423 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6424 {
6425         enum i40e_status_code status = I40E_SUCCESS;
6426         bool use_register;
6427         int retry = 5;
6428
6429         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6430         if (!use_register) {
6431 do_retry:
6432                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6433                                                        reg_val, NULL);
6434                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6435                         i40e_msec_delay(1);
6436                         retry--;
6437                         goto do_retry;
6438                 }
6439         }
6440
6441         /* if the AQ access failed, try the old-fashioned way */
6442         if (status || use_register)
6443                 wr32(hw, reg_addr, reg_val);
6444 }
6445 #ifdef VF_DRIVER
6446
6447 /**
6448  * i40e_aq_send_msg_to_pf
6449  * @hw: pointer to the hardware structure
6450  * @v_opcode: opcodes for VF-PF communication
6451  * @v_retval: return error code
6452  * @msg: pointer to the msg buffer
6453  * @msglen: msg length
6454  * @cmd_details: pointer to command details
6455  *
6456  * Send message to PF driver using admin queue. By default, this message
6457  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6458  * completion before returning.
6459  **/
6460 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6461                                 enum i40e_virtchnl_ops v_opcode,
6462                                 enum i40e_status_code v_retval,
6463                                 u8 *msg, u16 msglen,
6464                                 struct i40e_asq_cmd_details *cmd_details)
6465 {
6466         struct i40e_aq_desc desc;
6467         struct i40e_asq_cmd_details details;
6468         enum i40e_status_code status;
6469
6470         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6471         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6472         desc.cookie_high = CPU_TO_LE32(v_opcode);
6473         desc.cookie_low = CPU_TO_LE32(v_retval);
6474         if (msglen) {
6475                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6476                                                 | I40E_AQ_FLAG_RD));
6477                 if (msglen > I40E_AQ_LARGE_BUF)
6478                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6479                 desc.datalen = CPU_TO_LE16(msglen);
6480         }
6481         if (!cmd_details) {
6482                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6483                 details.async = true;
6484                 cmd_details = &details;
6485         }
6486         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6487                                        msglen, cmd_details);
6488         return status;
6489 }
6490
6491 /**
6492  * i40e_vf_parse_hw_config
6493  * @hw: pointer to the hardware structure
6494  * @msg: pointer to the virtual channel VF resource structure
6495  *
6496  * Given a VF resource message from the PF, populate the hw struct
6497  * with appropriate information.
6498  **/
6499 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6500                              struct i40e_virtchnl_vf_resource *msg)
6501 {
6502         struct i40e_virtchnl_vsi_resource *vsi_res;
6503         int i;
6504
6505         vsi_res = &msg->vsi_res[0];
6506
6507         hw->dev_caps.num_vsis = msg->num_vsis;
6508         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6509         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6510         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6511         hw->dev_caps.dcb = msg->vf_offload_flags &
6512                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6513         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6514                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6515         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6516                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6517         for (i = 0; i < msg->num_vsis; i++) {
6518                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6519                         i40e_memcpy(hw->mac.perm_addr,
6520                                     vsi_res->default_mac_addr,
6521                                     I40E_ETH_LENGTH_OF_ADDRESS,
6522                                     I40E_NONDMA_TO_NONDMA);
6523                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6524                                     I40E_ETH_LENGTH_OF_ADDRESS,
6525                                     I40E_NONDMA_TO_NONDMA);
6526                 }
6527                 vsi_res++;
6528         }
6529 }
6530
6531 /**
6532  * i40e_vf_reset
6533  * @hw: pointer to the hardware structure
6534  *
6535  * Send a VF_RESET message to the PF. Does not wait for response from PF
6536  * as none will be forthcoming. Immediately after calling this function,
6537  * the admin queue should be shut down and (optionally) reinitialized.
6538  **/
6539 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6540 {
6541         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6542                                       I40E_SUCCESS, NULL, 0, NULL);
6543 }
6544 #endif /* VF_DRIVER */
6545 #ifdef X722_SUPPORT
6546
6547 /**
6548  * i40e_aq_set_arp_proxy_config
6549  * @hw: pointer to the HW structure
6550  * @proxy_config - pointer to proxy config command table struct
6551  * @cmd_details: pointer to command details
6552  *
6553  * Set ARP offload parameters from pre-populated
6554  * i40e_aqc_arp_proxy_data struct
6555  **/
6556 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6557                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6558                                 struct i40e_asq_cmd_details *cmd_details)
6559 {
6560         struct i40e_aq_desc desc;
6561         enum i40e_status_code status;
6562
6563         if (!proxy_config)
6564                 return I40E_ERR_PARAM;
6565
6566         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6567
6568         desc.params.external.addr_high =
6569                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6570         desc.params.external.addr_low =
6571                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6572
6573         status = i40e_asq_send_command(hw, &desc, proxy_config,
6574                                        sizeof(struct i40e_aqc_arp_proxy_data),
6575                                        cmd_details);
6576
6577         return status;
6578 }
6579
6580 /**
6581  * i40e_aq_opc_set_ns_proxy_table_entry
6582  * @hw: pointer to the HW structure
6583  * @ns_proxy_table_entry: pointer to NS table entry command struct
6584  * @cmd_details: pointer to command details
6585  *
6586  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6587  * from pre-populated i40e_aqc_ns_proxy_data struct
6588  **/
6589 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6590                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6591                         struct i40e_asq_cmd_details *cmd_details)
6592 {
6593         struct i40e_aq_desc desc;
6594         enum i40e_status_code status;
6595
6596         if (!ns_proxy_table_entry)
6597                 return I40E_ERR_PARAM;
6598
6599         i40e_fill_default_direct_cmd_desc(&desc,
6600                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6601
6602         desc.params.external.addr_high =
6603                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6604         desc.params.external.addr_low =
6605                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6606
6607         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6608                                        sizeof(struct i40e_aqc_ns_proxy_data),
6609                                        cmd_details);
6610
6611         return status;
6612 }
6613
6614 /**
6615  * i40e_aq_set_clear_wol_filter
6616  * @hw: pointer to the hw struct
6617  * @filter_index: index of filter to modify (0-7)
6618  * @filter: buffer containing filter to be set
6619  * @set_filter: true to set filter, false to clear filter
6620  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6621  *              if false, pass through packets may cause wake-up
6622  * @filter_valid: true if filter action is valid
6623  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6624  * @cmd_details: pointer to command details structure or NULL
6625  *
6626  * Set or clear WoL filter for port attached to the PF
6627  **/
6628 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6629                                 u8 filter_index,
6630                                 struct i40e_aqc_set_wol_filter_data *filter,
6631                                 bool set_filter, bool no_wol_tco,
6632                                 bool filter_valid, bool no_wol_tco_valid,
6633                                 struct i40e_asq_cmd_details *cmd_details)
6634 {
6635         struct i40e_aq_desc desc;
6636         struct i40e_aqc_set_wol_filter *cmd =
6637                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6638         enum i40e_status_code status;
6639         u16 cmd_flags = 0;
6640         u16 valid_flags = 0;
6641         u16 buff_len = 0;
6642
6643         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6644
6645         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6646                 return  I40E_ERR_PARAM;
6647         cmd->filter_index = CPU_TO_LE16(filter_index);
6648
6649         if (set_filter) {
6650                 if (!filter)
6651                         return  I40E_ERR_PARAM;
6652                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6653                 buff_len = sizeof(*filter);
6654         }
6655         if (no_wol_tco)
6656                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6657         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6658
6659         if (filter_valid)
6660                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6661         if (no_wol_tco_valid)
6662                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6663         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6664
6665         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6666         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6667
6668         status = i40e_asq_send_command(hw, &desc, filter,
6669                                        buff_len, cmd_details);
6670
6671         return status;
6672 }
6673
6674 /**
6675  * i40e_aq_get_wake_event_reason
6676  * @hw: pointer to the hw struct
6677  * @wake_reason: return value, index of matching filter
6678  * @cmd_details: pointer to command details structure or NULL
6679  *
6680  * Get information for the reason of a Wake Up event
6681  **/
6682 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6683                                 u16 *wake_reason,
6684                                 struct i40e_asq_cmd_details *cmd_details)
6685 {
6686         struct i40e_aq_desc desc;
6687         struct i40e_aqc_get_wake_reason_completion *resp =
6688                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6689         enum i40e_status_code status;
6690
6691         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6692
6693         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6694
6695         if (status == I40E_SUCCESS)
6696                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6697
6698         return status;
6699 }
6700
6701 #endif /* X722_SUPPORT */