1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
352 memset(d_buf, 0, sizeof(d_buf));
353 for (j = 0; i < len; j++, i++)
356 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
357 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
358 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
359 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
360 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 * i40e_check_asq_alive
367 * @hw: pointer to the hw struct
369 * Returns true if Queue is enabled else false.
371 bool i40e_check_asq_alive(struct i40e_hw *hw)
374 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
380 * i40e_aq_queue_shutdown
381 * @hw: pointer to the hw struct
382 * @unloading: is the driver unloading itself
384 * Tell the Firmware that we're shutting down the AdminQ and whether
385 * or not the driver is unloading as well.
387 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
390 struct i40e_aq_desc desc;
391 struct i40e_aqc_queue_shutdown *cmd =
392 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
393 enum i40e_status_code status;
395 i40e_fill_default_direct_cmd_desc(&desc,
396 i40e_aqc_opc_queue_shutdown);
399 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
400 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
405 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
406 * hardware to a bit-field that can be used by SW to more easily determine the
409 * Macros are used to shorten the table lines and make this table human
412 * We store the PTYPE in the top byte of the bit field - this is just so that
413 * we can check that the table doesn't have a row missing, as the index into
414 * the table should be the PTYPE.
418 * IF NOT i40e_ptype_lookup[ptype].known
421 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
422 * Use the rest of the fields to look at the tunnels, inner protocols, etc
424 * Use the enum i40e_rx_l2_ptype to decode the packet type
428 /* macro to make the table lines short */
429 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
432 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
433 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
434 I40E_RX_PTYPE_##OUTER_FRAG, \
435 I40E_RX_PTYPE_TUNNEL_##T, \
436 I40E_RX_PTYPE_TUNNEL_END_##TE, \
437 I40E_RX_PTYPE_##TEF, \
438 I40E_RX_PTYPE_INNER_PROT_##I, \
439 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
441 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
442 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
444 /* shorter macros makes the table fit but are terse */
445 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
446 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
447 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
449 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
450 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
451 /* L2 Packet types */
452 I40E_PTT_UNUSED_ENTRY(0),
453 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
454 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
455 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
456 I40E_PTT_UNUSED_ENTRY(4),
457 I40E_PTT_UNUSED_ENTRY(5),
458 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
459 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
460 I40E_PTT_UNUSED_ENTRY(8),
461 I40E_PTT_UNUSED_ENTRY(9),
462 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
463 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
464 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
465 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
466 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
467 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
468 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
469 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
470 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
471 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
472 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
473 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
475 /* Non Tunneled IPv4 */
476 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
477 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
478 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
479 I40E_PTT_UNUSED_ENTRY(25),
480 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
481 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
482 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
485 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
486 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
487 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
488 I40E_PTT_UNUSED_ENTRY(32),
489 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
490 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
491 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
494 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
495 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
496 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
497 I40E_PTT_UNUSED_ENTRY(39),
498 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
499 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
500 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
502 /* IPv4 --> GRE/NAT */
503 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
505 /* IPv4 --> GRE/NAT --> IPv4 */
506 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
507 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
508 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
509 I40E_PTT_UNUSED_ENTRY(47),
510 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
511 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
512 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
514 /* IPv4 --> GRE/NAT --> IPv6 */
515 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
516 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
517 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
518 I40E_PTT_UNUSED_ENTRY(54),
519 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
520 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
521 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
523 /* IPv4 --> GRE/NAT --> MAC */
524 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
526 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
527 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
528 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
529 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
530 I40E_PTT_UNUSED_ENTRY(62),
531 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
532 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
533 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
535 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
536 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
537 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
538 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
539 I40E_PTT_UNUSED_ENTRY(69),
540 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
541 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
542 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
544 /* IPv4 --> GRE/NAT --> MAC/VLAN */
545 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
547 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
548 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
549 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
550 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
551 I40E_PTT_UNUSED_ENTRY(77),
552 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
553 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
554 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
556 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
557 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
558 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
559 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
560 I40E_PTT_UNUSED_ENTRY(84),
561 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
562 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
563 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
565 /* Non Tunneled IPv6 */
566 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
567 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
568 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
569 I40E_PTT_UNUSED_ENTRY(91),
570 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
571 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
572 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
575 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
576 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
577 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
578 I40E_PTT_UNUSED_ENTRY(98),
579 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
580 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
581 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
584 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
585 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
586 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
587 I40E_PTT_UNUSED_ENTRY(105),
588 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
589 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
590 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
592 /* IPv6 --> GRE/NAT */
593 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
595 /* IPv6 --> GRE/NAT -> IPv4 */
596 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
597 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
598 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
599 I40E_PTT_UNUSED_ENTRY(113),
600 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
601 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
602 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
604 /* IPv6 --> GRE/NAT -> IPv6 */
605 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
606 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
607 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(120),
609 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
610 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
611 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
613 /* IPv6 --> GRE/NAT -> MAC */
614 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
616 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
617 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
618 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
619 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
620 I40E_PTT_UNUSED_ENTRY(128),
621 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
622 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
623 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
625 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
626 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
627 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
628 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
629 I40E_PTT_UNUSED_ENTRY(135),
630 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
631 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
632 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
634 /* IPv6 --> GRE/NAT -> MAC/VLAN */
635 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
637 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
638 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
639 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
640 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
641 I40E_PTT_UNUSED_ENTRY(143),
642 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
643 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
644 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
646 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
647 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
648 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
649 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
650 I40E_PTT_UNUSED_ENTRY(150),
651 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
652 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
653 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(154),
657 I40E_PTT_UNUSED_ENTRY(155),
658 I40E_PTT_UNUSED_ENTRY(156),
659 I40E_PTT_UNUSED_ENTRY(157),
660 I40E_PTT_UNUSED_ENTRY(158),
661 I40E_PTT_UNUSED_ENTRY(159),
663 I40E_PTT_UNUSED_ENTRY(160),
664 I40E_PTT_UNUSED_ENTRY(161),
665 I40E_PTT_UNUSED_ENTRY(162),
666 I40E_PTT_UNUSED_ENTRY(163),
667 I40E_PTT_UNUSED_ENTRY(164),
668 I40E_PTT_UNUSED_ENTRY(165),
669 I40E_PTT_UNUSED_ENTRY(166),
670 I40E_PTT_UNUSED_ENTRY(167),
671 I40E_PTT_UNUSED_ENTRY(168),
672 I40E_PTT_UNUSED_ENTRY(169),
674 I40E_PTT_UNUSED_ENTRY(170),
675 I40E_PTT_UNUSED_ENTRY(171),
676 I40E_PTT_UNUSED_ENTRY(172),
677 I40E_PTT_UNUSED_ENTRY(173),
678 I40E_PTT_UNUSED_ENTRY(174),
679 I40E_PTT_UNUSED_ENTRY(175),
680 I40E_PTT_UNUSED_ENTRY(176),
681 I40E_PTT_UNUSED_ENTRY(177),
682 I40E_PTT_UNUSED_ENTRY(178),
683 I40E_PTT_UNUSED_ENTRY(179),
685 I40E_PTT_UNUSED_ENTRY(180),
686 I40E_PTT_UNUSED_ENTRY(181),
687 I40E_PTT_UNUSED_ENTRY(182),
688 I40E_PTT_UNUSED_ENTRY(183),
689 I40E_PTT_UNUSED_ENTRY(184),
690 I40E_PTT_UNUSED_ENTRY(185),
691 I40E_PTT_UNUSED_ENTRY(186),
692 I40E_PTT_UNUSED_ENTRY(187),
693 I40E_PTT_UNUSED_ENTRY(188),
694 I40E_PTT_UNUSED_ENTRY(189),
696 I40E_PTT_UNUSED_ENTRY(190),
697 I40E_PTT_UNUSED_ENTRY(191),
698 I40E_PTT_UNUSED_ENTRY(192),
699 I40E_PTT_UNUSED_ENTRY(193),
700 I40E_PTT_UNUSED_ENTRY(194),
701 I40E_PTT_UNUSED_ENTRY(195),
702 I40E_PTT_UNUSED_ENTRY(196),
703 I40E_PTT_UNUSED_ENTRY(197),
704 I40E_PTT_UNUSED_ENTRY(198),
705 I40E_PTT_UNUSED_ENTRY(199),
707 I40E_PTT_UNUSED_ENTRY(200),
708 I40E_PTT_UNUSED_ENTRY(201),
709 I40E_PTT_UNUSED_ENTRY(202),
710 I40E_PTT_UNUSED_ENTRY(203),
711 I40E_PTT_UNUSED_ENTRY(204),
712 I40E_PTT_UNUSED_ENTRY(205),
713 I40E_PTT_UNUSED_ENTRY(206),
714 I40E_PTT_UNUSED_ENTRY(207),
715 I40E_PTT_UNUSED_ENTRY(208),
716 I40E_PTT_UNUSED_ENTRY(209),
718 I40E_PTT_UNUSED_ENTRY(210),
719 I40E_PTT_UNUSED_ENTRY(211),
720 I40E_PTT_UNUSED_ENTRY(212),
721 I40E_PTT_UNUSED_ENTRY(213),
722 I40E_PTT_UNUSED_ENTRY(214),
723 I40E_PTT_UNUSED_ENTRY(215),
724 I40E_PTT_UNUSED_ENTRY(216),
725 I40E_PTT_UNUSED_ENTRY(217),
726 I40E_PTT_UNUSED_ENTRY(218),
727 I40E_PTT_UNUSED_ENTRY(219),
729 I40E_PTT_UNUSED_ENTRY(220),
730 I40E_PTT_UNUSED_ENTRY(221),
731 I40E_PTT_UNUSED_ENTRY(222),
732 I40E_PTT_UNUSED_ENTRY(223),
733 I40E_PTT_UNUSED_ENTRY(224),
734 I40E_PTT_UNUSED_ENTRY(225),
735 I40E_PTT_UNUSED_ENTRY(226),
736 I40E_PTT_UNUSED_ENTRY(227),
737 I40E_PTT_UNUSED_ENTRY(228),
738 I40E_PTT_UNUSED_ENTRY(229),
740 I40E_PTT_UNUSED_ENTRY(230),
741 I40E_PTT_UNUSED_ENTRY(231),
742 I40E_PTT_UNUSED_ENTRY(232),
743 I40E_PTT_UNUSED_ENTRY(233),
744 I40E_PTT_UNUSED_ENTRY(234),
745 I40E_PTT_UNUSED_ENTRY(235),
746 I40E_PTT_UNUSED_ENTRY(236),
747 I40E_PTT_UNUSED_ENTRY(237),
748 I40E_PTT_UNUSED_ENTRY(238),
749 I40E_PTT_UNUSED_ENTRY(239),
751 I40E_PTT_UNUSED_ENTRY(240),
752 I40E_PTT_UNUSED_ENTRY(241),
753 I40E_PTT_UNUSED_ENTRY(242),
754 I40E_PTT_UNUSED_ENTRY(243),
755 I40E_PTT_UNUSED_ENTRY(244),
756 I40E_PTT_UNUSED_ENTRY(245),
757 I40E_PTT_UNUSED_ENTRY(246),
758 I40E_PTT_UNUSED_ENTRY(247),
759 I40E_PTT_UNUSED_ENTRY(248),
760 I40E_PTT_UNUSED_ENTRY(249),
762 I40E_PTT_UNUSED_ENTRY(250),
763 I40E_PTT_UNUSED_ENTRY(251),
764 I40E_PTT_UNUSED_ENTRY(252),
765 I40E_PTT_UNUSED_ENTRY(253),
766 I40E_PTT_UNUSED_ENTRY(254),
767 I40E_PTT_UNUSED_ENTRY(255)
772 * i40e_validate_mac_addr - Validate unicast MAC address
773 * @mac_addr: pointer to MAC address
775 * Tests a MAC address to ensure it is a valid Individual Address
777 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
779 enum i40e_status_code status = I40E_SUCCESS;
781 DEBUGFUNC("i40e_validate_mac_addr");
783 /* Broadcast addresses ARE multicast addresses
784 * Make sure it is not a multicast address
785 * Reject the zero address
787 if (I40E_IS_MULTICAST(mac_addr) ||
788 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
789 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
790 status = I40E_ERR_INVALID_MAC_ADDR;
797 * i40e_init_shared_code - Initialize the shared code
798 * @hw: pointer to hardware structure
800 * This assigns the MAC type and PHY code and inits the NVM.
801 * Does not touch the hardware. This function must be called prior to any
802 * other function in the shared code. The i40e_hw structure should be
803 * memset to 0 prior to calling this function. The following fields in
804 * hw structure should be filled in prior to calling this function:
805 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
806 * subsystem_vendor_id, and revision_id
808 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
810 enum i40e_status_code status = I40E_SUCCESS;
811 u32 port, ari, func_rid;
813 DEBUGFUNC("i40e_init_shared_code");
815 i40e_set_mac_type(hw);
817 switch (hw->mac.type) {
821 return I40E_ERR_DEVICE_NOT_SUPPORTED;
824 hw->phy.get_link_info = true;
826 /* Determine port number and PF number*/
827 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
828 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
830 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
831 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
832 func_rid = rd32(hw, I40E_PF_FUNC_RID);
834 hw->pf_id = (u8)(func_rid & 0xff);
836 hw->pf_id = (u8)(func_rid & 0x7);
838 status = i40e_init_nvm(hw);
843 * i40e_aq_mac_address_read - Retrieve the MAC addresses
844 * @hw: pointer to the hw struct
845 * @flags: a return indicator of what addresses were added to the addr store
846 * @addrs: the requestor's mac addr store
847 * @cmd_details: pointer to command details structure or NULL
849 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
851 struct i40e_aqc_mac_address_read_data *addrs,
852 struct i40e_asq_cmd_details *cmd_details)
854 struct i40e_aq_desc desc;
855 struct i40e_aqc_mac_address_read *cmd_data =
856 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
857 enum i40e_status_code status;
859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
860 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
862 status = i40e_asq_send_command(hw, &desc, addrs,
863 sizeof(*addrs), cmd_details);
864 *flags = LE16_TO_CPU(cmd_data->command_flags);
870 * i40e_aq_mac_address_write - Change the MAC addresses
871 * @hw: pointer to the hw struct
872 * @flags: indicates which MAC to be written
873 * @mac_addr: address to write
874 * @cmd_details: pointer to command details structure or NULL
876 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
877 u16 flags, u8 *mac_addr,
878 struct i40e_asq_cmd_details *cmd_details)
880 struct i40e_aq_desc desc;
881 struct i40e_aqc_mac_address_write *cmd_data =
882 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
883 enum i40e_status_code status;
885 i40e_fill_default_direct_cmd_desc(&desc,
886 i40e_aqc_opc_mac_address_write);
887 cmd_data->command_flags = CPU_TO_LE16(flags);
888 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
889 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
890 ((u32)mac_addr[3] << 16) |
891 ((u32)mac_addr[4] << 8) |
894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
900 * i40e_get_mac_addr - get MAC address
901 * @hw: pointer to the HW structure
902 * @mac_addr: pointer to MAC address
904 * Reads the adapter's MAC address from register
906 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
908 struct i40e_aqc_mac_address_read_data addrs;
909 enum i40e_status_code status;
912 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
914 if (flags & I40E_AQC_LAN_ADDR_VALID)
915 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
921 * i40e_get_port_mac_addr - get Port MAC address
922 * @hw: pointer to the HW structure
923 * @mac_addr: pointer to Port MAC address
925 * Reads the adapter's Port MAC address
927 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
929 struct i40e_aqc_mac_address_read_data addrs;
930 enum i40e_status_code status;
933 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
937 if (flags & I40E_AQC_PORT_ADDR_VALID)
938 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
940 status = I40E_ERR_INVALID_MAC_ADDR;
946 * i40e_pre_tx_queue_cfg - pre tx queue configure
947 * @hw: pointer to the HW structure
948 * @queue: target pf queue index
949 * @enable: state change request
951 * Handles hw requirement to indicate intention to enable
952 * or disable target queue.
954 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
956 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
960 if (abs_queue_idx >= 128) {
961 reg_block = abs_queue_idx / 128;
962 abs_queue_idx %= 128;
965 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
966 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
967 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
970 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
972 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
974 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
978 * i40e_read_pba_string - Reads part number string from EEPROM
979 * @hw: pointer to hardware structure
980 * @pba_num: stores the part number string from the EEPROM
981 * @pba_num_size: part number string buffer length
983 * Reads the part number string from the EEPROM.
985 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
988 enum i40e_status_code status = I40E_SUCCESS;
994 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
995 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
996 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1000 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1001 if (status != I40E_SUCCESS) {
1002 DEBUGOUT("Failed to read PBA Block pointer.\n");
1006 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1007 if (status != I40E_SUCCESS) {
1008 DEBUGOUT("Failed to read PBA Block size.\n");
1012 /* Subtract one to get PBA word count (PBA Size word is included in
1016 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1017 DEBUGOUT("Buffer to small for PBA data.\n");
1018 return I40E_ERR_PARAM;
1021 for (i = 0; i < pba_size; i++) {
1022 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1023 if (status != I40E_SUCCESS) {
1024 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1028 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1029 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1031 pba_num[(pba_size * 2)] = '\0';
1037 * i40e_get_media_type - Gets media type
1038 * @hw: pointer to the hardware structure
1040 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1042 enum i40e_media_type media;
1044 switch (hw->phy.link_info.phy_type) {
1045 case I40E_PHY_TYPE_10GBASE_SR:
1046 case I40E_PHY_TYPE_10GBASE_LR:
1047 case I40E_PHY_TYPE_1000BASE_SX:
1048 case I40E_PHY_TYPE_1000BASE_LX:
1049 case I40E_PHY_TYPE_40GBASE_SR4:
1050 case I40E_PHY_TYPE_40GBASE_LR4:
1051 media = I40E_MEDIA_TYPE_FIBER;
1053 case I40E_PHY_TYPE_100BASE_TX:
1054 case I40E_PHY_TYPE_1000BASE_T:
1055 case I40E_PHY_TYPE_10GBASE_T:
1056 media = I40E_MEDIA_TYPE_BASET;
1058 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1059 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1060 case I40E_PHY_TYPE_10GBASE_CR1:
1061 case I40E_PHY_TYPE_40GBASE_CR4:
1062 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1063 case I40E_PHY_TYPE_40GBASE_AOC:
1064 case I40E_PHY_TYPE_10GBASE_AOC:
1065 media = I40E_MEDIA_TYPE_DA;
1067 case I40E_PHY_TYPE_1000BASE_KX:
1068 case I40E_PHY_TYPE_10GBASE_KX4:
1069 case I40E_PHY_TYPE_10GBASE_KR:
1070 case I40E_PHY_TYPE_40GBASE_KR4:
1071 case I40E_PHY_TYPE_20GBASE_KR2:
1072 media = I40E_MEDIA_TYPE_BACKPLANE;
1074 case I40E_PHY_TYPE_SGMII:
1075 case I40E_PHY_TYPE_XAUI:
1076 case I40E_PHY_TYPE_XFI:
1077 case I40E_PHY_TYPE_XLAUI:
1078 case I40E_PHY_TYPE_XLPPI:
1080 media = I40E_MEDIA_TYPE_UNKNOWN;
1087 #define I40E_PF_RESET_WAIT_COUNT 110
1089 * i40e_pf_reset - Reset the PF
1090 * @hw: pointer to the hardware structure
1092 * Assuming someone else has triggered a global reset,
1093 * assure the global reset is complete and then reset the PF
1095 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1102 /* Poll for Global Reset steady state in case of recent GRST.
1103 * The grst delay value is in 100ms units, and we'll wait a
1104 * couple counts longer to be sure we don't just miss the end.
1106 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1107 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1108 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1109 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1110 reg = rd32(hw, I40E_GLGEN_RSTAT);
1111 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1113 i40e_msec_delay(100);
1115 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1116 DEBUGOUT("Global reset polling failed to complete.\n");
1117 return I40E_ERR_RESET_FAILED;
1120 /* Now Wait for the FW to be ready */
1121 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1122 reg = rd32(hw, I40E_GLNVM_ULD);
1123 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1124 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1125 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1126 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1127 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1130 i40e_msec_delay(10);
1132 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1133 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1134 DEBUGOUT("wait for FW Reset complete timedout\n");
1135 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1136 return I40E_ERR_RESET_FAILED;
1139 /* If there was a Global Reset in progress when we got here,
1140 * we don't need to do the PF Reset
1143 reg = rd32(hw, I40E_PFGEN_CTRL);
1144 wr32(hw, I40E_PFGEN_CTRL,
1145 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1146 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1147 reg = rd32(hw, I40E_PFGEN_CTRL);
1148 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1152 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1153 DEBUGOUT("PF reset polling failed to complete.\n");
1154 return I40E_ERR_RESET_FAILED;
1158 i40e_clear_pxe_mode(hw);
1161 return I40E_SUCCESS;
1165 * i40e_clear_hw - clear out any left over hw state
1166 * @hw: pointer to the hw struct
1168 * Clear queues and interrupts, typically called at init time,
1169 * but after the capabilities have been found so we know how many
1170 * queues and msix vectors have been allocated.
1172 void i40e_clear_hw(struct i40e_hw *hw)
1174 u32 num_queues, base_queue;
1182 /* get number of interrupts, queues, and vfs */
1183 val = rd32(hw, I40E_GLPCI_CNF2);
1184 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1185 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1186 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1187 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1189 val = rd32(hw, I40E_PFLAN_QALLOC);
1190 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1191 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1192 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1193 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1194 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1195 num_queues = (j - base_queue) + 1;
1199 val = rd32(hw, I40E_PF_VT_PFALLOC);
1200 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1201 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1202 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1203 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1204 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1205 num_vfs = (j - i) + 1;
1209 /* stop all the interrupts */
1210 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1211 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1212 for (i = 0; i < num_pf_int - 2; i++)
1213 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1215 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1216 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1217 wr32(hw, I40E_PFINT_LNKLST0, val);
1218 for (i = 0; i < num_pf_int - 2; i++)
1219 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1220 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1221 for (i = 0; i < num_vfs; i++)
1222 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1223 for (i = 0; i < num_vf_int - 2; i++)
1224 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1226 /* warn the HW of the coming Tx disables */
1227 for (i = 0; i < num_queues; i++) {
1228 u32 abs_queue_idx = base_queue + i;
1231 if (abs_queue_idx >= 128) {
1232 reg_block = abs_queue_idx / 128;
1233 abs_queue_idx %= 128;
1236 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1237 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1238 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1239 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1241 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1243 i40e_usec_delay(400);
1245 /* stop all the queues */
1246 for (i = 0; i < num_queues; i++) {
1247 wr32(hw, I40E_QINT_TQCTL(i), 0);
1248 wr32(hw, I40E_QTX_ENA(i), 0);
1249 wr32(hw, I40E_QINT_RQCTL(i), 0);
1250 wr32(hw, I40E_QRX_ENA(i), 0);
1253 /* short wait for all queue disables to settle */
1254 i40e_usec_delay(50);
1258 * i40e_clear_pxe_mode - clear pxe operations mode
1259 * @hw: pointer to the hw struct
1261 * Make sure all PXE mode settings are cleared, including things
1262 * like descriptor fetch/write-back mode.
1264 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1266 if (i40e_check_asq_alive(hw))
1267 i40e_aq_clear_pxe_mode(hw, NULL);
1271 * i40e_led_is_mine - helper to find matching led
1272 * @hw: pointer to the hw struct
1273 * @idx: index into GPIO registers
1275 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1277 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1282 if (!hw->func_caps.led[idx])
1285 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1286 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1287 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1289 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1290 * if it is not our port then ignore
1292 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1299 #define I40E_COMBINED_ACTIVITY 0xA
1300 #define I40E_FILTER_ACTIVITY 0xE
1301 #define I40E_LINK_ACTIVITY 0xC
1302 #define I40E_MAC_ACTIVITY 0xD
1303 #define I40E_LED0 22
1306 * i40e_led_get - return current on/off mode
1307 * @hw: pointer to the hw struct
1309 * The value returned is the 'mode' field as defined in the
1310 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1311 * values are variations of possible behaviors relating to
1312 * blink, link, and wire.
1314 u32 i40e_led_get(struct i40e_hw *hw)
1316 u32 current_mode = 0;
1320 /* as per the documentation GPIO 22-29 are the LED
1321 * GPIO pins named LED0..LED7
1323 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1324 u32 gpio_val = i40e_led_is_mine(hw, i);
1329 /* ignore gpio LED src mode entries related to the activity LEDs */
1330 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1331 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1332 switch (current_mode) {
1333 case I40E_COMBINED_ACTIVITY:
1334 case I40E_FILTER_ACTIVITY:
1335 case I40E_MAC_ACTIVITY:
1341 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1342 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1350 * i40e_led_set - set new on/off mode
1351 * @hw: pointer to the hw struct
1352 * @mode: 0=off, 0xf=on (else see manual for mode details)
1353 * @blink: true if the LED should blink when on, false if steady
1355 * if this function is used to turn on the blink it should
1356 * be used to disable the blink when restoring the original state.
1358 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1360 u32 current_mode = 0;
1363 if (mode & 0xfffffff0)
1364 DEBUGOUT1("invalid mode passed in %X\n", mode);
1366 /* as per the documentation GPIO 22-29 are the LED
1367 * GPIO pins named LED0..LED7
1369 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1370 u32 gpio_val = i40e_led_is_mine(hw, i);
1375 /* ignore gpio LED src mode entries related to the activity LEDs */
1376 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1377 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1378 switch (current_mode) {
1379 case I40E_COMBINED_ACTIVITY:
1380 case I40E_FILTER_ACTIVITY:
1381 case I40E_MAC_ACTIVITY:
1387 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1388 /* this & is a bit of paranoia, but serves as a range check */
1389 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1390 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1392 if (mode == I40E_LINK_ACTIVITY)
1396 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1398 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1400 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1405 /* Admin command wrappers */
1408 * i40e_aq_get_phy_capabilities
1409 * @hw: pointer to the hw struct
1410 * @abilities: structure for PHY capabilities to be filled
1411 * @qualified_modules: report Qualified Modules
1412 * @report_init: report init capabilities (active are default)
1413 * @cmd_details: pointer to command details structure or NULL
1415 * Returns the various PHY abilities supported on the Port.
1417 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1418 bool qualified_modules, bool report_init,
1419 struct i40e_aq_get_phy_abilities_resp *abilities,
1420 struct i40e_asq_cmd_details *cmd_details)
1422 struct i40e_aq_desc desc;
1423 enum i40e_status_code status;
1424 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1427 return I40E_ERR_PARAM;
1429 i40e_fill_default_direct_cmd_desc(&desc,
1430 i40e_aqc_opc_get_phy_abilities);
1432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1433 if (abilities_size > I40E_AQ_LARGE_BUF)
1434 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1436 if (qualified_modules)
1437 desc.params.external.param0 |=
1438 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1441 desc.params.external.param0 |=
1442 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1444 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1447 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1448 status = I40E_ERR_UNKNOWN_PHY;
1454 * i40e_aq_set_phy_config
1455 * @hw: pointer to the hw struct
1456 * @config: structure with PHY configuration to be set
1457 * @cmd_details: pointer to command details structure or NULL
1459 * Set the various PHY configuration parameters
1460 * supported on the Port.One or more of the Set PHY config parameters may be
1461 * ignored in an MFP mode as the PF may not have the privilege to set some
1462 * of the PHY Config parameters. This status will be indicated by the
1465 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1466 struct i40e_aq_set_phy_config *config,
1467 struct i40e_asq_cmd_details *cmd_details)
1469 struct i40e_aq_desc desc;
1470 struct i40e_aq_set_phy_config *cmd =
1471 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1472 enum i40e_status_code status;
1475 return I40E_ERR_PARAM;
1477 i40e_fill_default_direct_cmd_desc(&desc,
1478 i40e_aqc_opc_set_phy_config);
1482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1489 * @hw: pointer to the hw struct
1491 * Set the requested flow control mode using set_phy_config.
1493 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1494 bool atomic_restart)
1496 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1497 struct i40e_aq_get_phy_abilities_resp abilities;
1498 struct i40e_aq_set_phy_config config;
1499 enum i40e_status_code status;
1500 u8 pause_mask = 0x0;
1506 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1507 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1509 case I40E_FC_RX_PAUSE:
1510 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1512 case I40E_FC_TX_PAUSE:
1513 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1519 /* Get the current phy config */
1520 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1523 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1527 memset(&config, 0, sizeof(config));
1528 /* clear the old pause settings */
1529 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1530 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1531 /* set the new abilities */
1532 config.abilities |= pause_mask;
1533 /* If the abilities have changed, then set the new config */
1534 if (config.abilities != abilities.abilities) {
1535 /* Auto restart link so settings take effect */
1537 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1538 /* Copy over all the old settings */
1539 config.phy_type = abilities.phy_type;
1540 config.link_speed = abilities.link_speed;
1541 config.eee_capability = abilities.eee_capability;
1542 config.eeer = abilities.eeer_val;
1543 config.low_power_ctrl = abilities.d3_lpan;
1544 status = i40e_aq_set_phy_config(hw, &config, NULL);
1547 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1549 /* Update the link info */
1550 status = i40e_update_link_info(hw);
1552 /* Wait a little bit (on 40G cards it sometimes takes a really
1553 * long time for link to come back from the atomic reset)
1556 i40e_msec_delay(1000);
1557 status = i40e_update_link_info(hw);
1560 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1566 * i40e_aq_set_mac_config
1567 * @hw: pointer to the hw struct
1568 * @max_frame_size: Maximum Frame Size to be supported by the port
1569 * @crc_en: Tell HW to append a CRC to outgoing frames
1570 * @pacing: Pacing configurations
1571 * @cmd_details: pointer to command details structure or NULL
1573 * Configure MAC settings for frame size, jumbo frame support and the
1574 * addition of a CRC by the hardware.
1576 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1578 bool crc_en, u16 pacing,
1579 struct i40e_asq_cmd_details *cmd_details)
1581 struct i40e_aq_desc desc;
1582 struct i40e_aq_set_mac_config *cmd =
1583 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1584 enum i40e_status_code status;
1586 if (max_frame_size == 0)
1587 return I40E_ERR_PARAM;
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_set_mac_config);
1592 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1593 cmd->params = ((u8)pacing & 0x0F) << 3;
1595 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1597 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1603 * i40e_aq_clear_pxe_mode
1604 * @hw: pointer to the hw struct
1605 * @cmd_details: pointer to command details structure or NULL
1607 * Tell the firmware that the driver is taking over from PXE
1609 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1610 struct i40e_asq_cmd_details *cmd_details)
1612 enum i40e_status_code status;
1613 struct i40e_aq_desc desc;
1614 struct i40e_aqc_clear_pxe *cmd =
1615 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1617 i40e_fill_default_direct_cmd_desc(&desc,
1618 i40e_aqc_opc_clear_pxe_mode);
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1624 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1630 * i40e_aq_set_link_restart_an
1631 * @hw: pointer to the hw struct
1632 * @enable_link: if true: enable link, if false: disable link
1633 * @cmd_details: pointer to command details structure or NULL
1635 * Sets up the link and restarts the Auto-Negotiation over the link.
1637 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1638 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1640 struct i40e_aq_desc desc;
1641 struct i40e_aqc_set_link_restart_an *cmd =
1642 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1643 enum i40e_status_code status;
1645 i40e_fill_default_direct_cmd_desc(&desc,
1646 i40e_aqc_opc_set_link_restart_an);
1648 cmd->command = I40E_AQ_PHY_RESTART_AN;
1650 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1652 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1660 * i40e_aq_get_link_info
1661 * @hw: pointer to the hw struct
1662 * @enable_lse: enable/disable LinkStatusEvent reporting
1663 * @link: pointer to link status structure - optional
1664 * @cmd_details: pointer to command details structure or NULL
1666 * Returns the link status of the adapter.
1668 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1669 bool enable_lse, struct i40e_link_status *link,
1670 struct i40e_asq_cmd_details *cmd_details)
1672 struct i40e_aq_desc desc;
1673 struct i40e_aqc_get_link_status *resp =
1674 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1675 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1676 enum i40e_status_code status;
1677 bool tx_pause, rx_pause;
1680 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1683 command_flags = I40E_AQ_LSE_ENABLE;
1685 command_flags = I40E_AQ_LSE_DISABLE;
1686 resp->command_flags = CPU_TO_LE16(command_flags);
1688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1690 if (status != I40E_SUCCESS)
1691 goto aq_get_link_info_exit;
1693 /* save off old link status information */
1694 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1695 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1697 /* update link status */
1698 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1699 hw->phy.media_type = i40e_get_media_type(hw);
1700 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1701 hw_link_info->link_info = resp->link_info;
1702 hw_link_info->an_info = resp->an_info;
1703 hw_link_info->ext_info = resp->ext_info;
1704 hw_link_info->loopback = resp->loopback;
1705 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1706 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1708 /* update fc info */
1709 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1710 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1711 if (tx_pause & rx_pause)
1712 hw->fc.current_mode = I40E_FC_FULL;
1714 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1716 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1718 hw->fc.current_mode = I40E_FC_NONE;
1720 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1721 hw_link_info->crc_enable = true;
1723 hw_link_info->crc_enable = false;
1725 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1726 hw_link_info->lse_enable = true;
1728 hw_link_info->lse_enable = false;
1730 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1731 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1732 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1734 /* save link status information */
1736 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1737 I40E_NONDMA_TO_NONDMA);
1739 /* flag cleared so helper functions don't call AQ again */
1740 hw->phy.get_link_info = false;
1742 aq_get_link_info_exit:
1747 * i40e_aq_set_phy_int_mask
1748 * @hw: pointer to the hw struct
1749 * @mask: interrupt mask to be set
1750 * @cmd_details: pointer to command details structure or NULL
1752 * Set link interrupt mask.
1754 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1756 struct i40e_asq_cmd_details *cmd_details)
1758 struct i40e_aq_desc desc;
1759 struct i40e_aqc_set_phy_int_mask *cmd =
1760 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1761 enum i40e_status_code status;
1763 i40e_fill_default_direct_cmd_desc(&desc,
1764 i40e_aqc_opc_set_phy_int_mask);
1766 cmd->event_mask = CPU_TO_LE16(mask);
1768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1774 * i40e_aq_get_local_advt_reg
1775 * @hw: pointer to the hw struct
1776 * @advt_reg: local AN advertisement register value
1777 * @cmd_details: pointer to command details structure or NULL
1779 * Get the Local AN advertisement register value.
1781 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1783 struct i40e_asq_cmd_details *cmd_details)
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_an_advt_reg *resp =
1787 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1788 enum i40e_status_code status;
1790 i40e_fill_default_direct_cmd_desc(&desc,
1791 i40e_aqc_opc_get_local_advt_reg);
1793 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1795 if (status != I40E_SUCCESS)
1796 goto aq_get_local_advt_reg_exit;
1798 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1799 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1801 aq_get_local_advt_reg_exit:
1806 * i40e_aq_set_local_advt_reg
1807 * @hw: pointer to the hw struct
1808 * @advt_reg: local AN advertisement register value
1809 * @cmd_details: pointer to command details structure or NULL
1811 * Get the Local AN advertisement register value.
1813 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1815 struct i40e_asq_cmd_details *cmd_details)
1817 struct i40e_aq_desc desc;
1818 struct i40e_aqc_an_advt_reg *cmd =
1819 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1820 enum i40e_status_code status;
1822 i40e_fill_default_direct_cmd_desc(&desc,
1823 i40e_aqc_opc_get_local_advt_reg);
1825 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1826 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1834 * i40e_aq_get_partner_advt
1835 * @hw: pointer to the hw struct
1836 * @advt_reg: AN partner advertisement register value
1837 * @cmd_details: pointer to command details structure or NULL
1839 * Get the link partner AN advertisement register value.
1841 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1843 struct i40e_asq_cmd_details *cmd_details)
1845 struct i40e_aq_desc desc;
1846 struct i40e_aqc_an_advt_reg *resp =
1847 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1848 enum i40e_status_code status;
1850 i40e_fill_default_direct_cmd_desc(&desc,
1851 i40e_aqc_opc_get_partner_advt);
1853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1855 if (status != I40E_SUCCESS)
1856 goto aq_get_partner_advt_exit;
1858 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1859 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1861 aq_get_partner_advt_exit:
1866 * i40e_aq_set_lb_modes
1867 * @hw: pointer to the hw struct
1868 * @lb_modes: loopback mode to be set
1869 * @cmd_details: pointer to command details structure or NULL
1871 * Sets loopback modes.
1873 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1875 struct i40e_asq_cmd_details *cmd_details)
1877 struct i40e_aq_desc desc;
1878 struct i40e_aqc_set_lb_mode *cmd =
1879 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1880 enum i40e_status_code status;
1882 i40e_fill_default_direct_cmd_desc(&desc,
1883 i40e_aqc_opc_set_lb_modes);
1885 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1887 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1893 * i40e_aq_set_phy_debug
1894 * @hw: pointer to the hw struct
1895 * @cmd_flags: debug command flags
1896 * @cmd_details: pointer to command details structure or NULL
1898 * Reset the external PHY.
1900 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1901 struct i40e_asq_cmd_details *cmd_details)
1903 struct i40e_aq_desc desc;
1904 struct i40e_aqc_set_phy_debug *cmd =
1905 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1906 enum i40e_status_code status;
1908 i40e_fill_default_direct_cmd_desc(&desc,
1909 i40e_aqc_opc_set_phy_debug);
1911 cmd->command_flags = cmd_flags;
1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1920 * @hw: pointer to the hw struct
1921 * @vsi_ctx: pointer to a vsi context struct
1922 * @cmd_details: pointer to command details structure or NULL
1924 * Add a VSI context to the hardware.
1926 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1927 struct i40e_vsi_context *vsi_ctx,
1928 struct i40e_asq_cmd_details *cmd_details)
1930 struct i40e_aq_desc desc;
1931 struct i40e_aqc_add_get_update_vsi *cmd =
1932 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1933 struct i40e_aqc_add_get_update_vsi_completion *resp =
1934 (struct i40e_aqc_add_get_update_vsi_completion *)
1936 enum i40e_status_code status;
1938 i40e_fill_default_direct_cmd_desc(&desc,
1939 i40e_aqc_opc_add_vsi);
1941 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1942 cmd->connection_type = vsi_ctx->connection_type;
1943 cmd->vf_id = vsi_ctx->vf_num;
1944 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1946 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1948 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1949 sizeof(vsi_ctx->info), cmd_details);
1951 if (status != I40E_SUCCESS)
1952 goto aq_add_vsi_exit;
1954 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1955 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1956 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1957 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1964 * i40e_aq_set_default_vsi
1965 * @hw: pointer to the hw struct
1967 * @cmd_details: pointer to command details structure or NULL
1969 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1971 struct i40e_asq_cmd_details *cmd_details)
1973 struct i40e_aq_desc desc;
1974 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1975 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1977 enum i40e_status_code status;
1979 i40e_fill_default_direct_cmd_desc(&desc,
1980 i40e_aqc_opc_set_vsi_promiscuous_modes);
1982 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1983 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1984 cmd->seid = CPU_TO_LE16(seid);
1986 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1992 * i40e_aq_set_vsi_unicast_promiscuous
1993 * @hw: pointer to the hw struct
1995 * @set: set unicast promiscuous enable/disable
1996 * @cmd_details: pointer to command details structure or NULL
1998 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2000 struct i40e_asq_cmd_details *cmd_details)
2002 struct i40e_aq_desc desc;
2003 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2004 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2005 enum i40e_status_code status;
2008 i40e_fill_default_direct_cmd_desc(&desc,
2009 i40e_aqc_opc_set_vsi_promiscuous_modes);
2012 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2014 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2016 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2018 cmd->seid = CPU_TO_LE16(seid);
2019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2025 * i40e_aq_set_vsi_multicast_promiscuous
2026 * @hw: pointer to the hw struct
2028 * @set: set multicast promiscuous enable/disable
2029 * @cmd_details: pointer to command details structure or NULL
2031 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2032 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2034 struct i40e_aq_desc desc;
2035 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2036 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2037 enum i40e_status_code status;
2040 i40e_fill_default_direct_cmd_desc(&desc,
2041 i40e_aqc_opc_set_vsi_promiscuous_modes);
2044 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2046 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2048 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2050 cmd->seid = CPU_TO_LE16(seid);
2051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2057 * i40e_aq_set_vsi_broadcast
2058 * @hw: pointer to the hw struct
2060 * @set_filter: true to set filter, false to clear filter
2061 * @cmd_details: pointer to command details structure or NULL
2063 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2065 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2066 u16 seid, bool set_filter,
2067 struct i40e_asq_cmd_details *cmd_details)
2069 struct i40e_aq_desc desc;
2070 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2071 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2072 enum i40e_status_code status;
2074 i40e_fill_default_direct_cmd_desc(&desc,
2075 i40e_aqc_opc_set_vsi_promiscuous_modes);
2078 cmd->promiscuous_flags
2079 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2081 cmd->promiscuous_flags
2082 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2084 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2085 cmd->seid = CPU_TO_LE16(seid);
2086 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2092 * i40e_get_vsi_params - get VSI configuration info
2093 * @hw: pointer to the hw struct
2094 * @vsi_ctx: pointer to a vsi context struct
2095 * @cmd_details: pointer to command details structure or NULL
2097 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2098 struct i40e_vsi_context *vsi_ctx,
2099 struct i40e_asq_cmd_details *cmd_details)
2101 struct i40e_aq_desc desc;
2102 struct i40e_aqc_add_get_update_vsi *cmd =
2103 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2104 struct i40e_aqc_add_get_update_vsi_completion *resp =
2105 (struct i40e_aqc_add_get_update_vsi_completion *)
2107 enum i40e_status_code status;
2109 UNREFERENCED_1PARAMETER(cmd_details);
2110 i40e_fill_default_direct_cmd_desc(&desc,
2111 i40e_aqc_opc_get_vsi_parameters);
2113 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2117 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2118 sizeof(vsi_ctx->info), NULL);
2120 if (status != I40E_SUCCESS)
2121 goto aq_get_vsi_params_exit;
2123 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2124 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2125 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2126 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2128 aq_get_vsi_params_exit:
2133 * i40e_aq_update_vsi_params
2134 * @hw: pointer to the hw struct
2135 * @vsi_ctx: pointer to a vsi context struct
2136 * @cmd_details: pointer to command details structure or NULL
2138 * Update a VSI context.
2140 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2141 struct i40e_vsi_context *vsi_ctx,
2142 struct i40e_asq_cmd_details *cmd_details)
2144 struct i40e_aq_desc desc;
2145 struct i40e_aqc_add_get_update_vsi *cmd =
2146 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2147 enum i40e_status_code status;
2149 i40e_fill_default_direct_cmd_desc(&desc,
2150 i40e_aqc_opc_update_vsi_parameters);
2151 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2153 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2155 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2156 sizeof(vsi_ctx->info), cmd_details);
2162 * i40e_aq_get_switch_config
2163 * @hw: pointer to the hardware structure
2164 * @buf: pointer to the result buffer
2165 * @buf_size: length of input buffer
2166 * @start_seid: seid to start for the report, 0 == beginning
2167 * @cmd_details: pointer to command details structure or NULL
2169 * Fill the buf with switch configuration returned from AdminQ command
2171 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2172 struct i40e_aqc_get_switch_config_resp *buf,
2173 u16 buf_size, u16 *start_seid,
2174 struct i40e_asq_cmd_details *cmd_details)
2176 struct i40e_aq_desc desc;
2177 struct i40e_aqc_switch_seid *scfg =
2178 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2179 enum i40e_status_code status;
2181 i40e_fill_default_direct_cmd_desc(&desc,
2182 i40e_aqc_opc_get_switch_config);
2183 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2184 if (buf_size > I40E_AQ_LARGE_BUF)
2185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2186 scfg->seid = CPU_TO_LE16(*start_seid);
2188 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2189 *start_seid = LE16_TO_CPU(scfg->seid);
2195 * i40e_aq_get_firmware_version
2196 * @hw: pointer to the hw struct
2197 * @fw_major_version: firmware major version
2198 * @fw_minor_version: firmware minor version
2199 * @fw_build: firmware build number
2200 * @api_major_version: major queue version
2201 * @api_minor_version: minor queue version
2202 * @cmd_details: pointer to command details structure or NULL
2204 * Get the firmware version from the admin queue commands
2206 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2207 u16 *fw_major_version, u16 *fw_minor_version,
2209 u16 *api_major_version, u16 *api_minor_version,
2210 struct i40e_asq_cmd_details *cmd_details)
2212 struct i40e_aq_desc desc;
2213 struct i40e_aqc_get_version *resp =
2214 (struct i40e_aqc_get_version *)&desc.params.raw;
2215 enum i40e_status_code status;
2217 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2221 if (status == I40E_SUCCESS) {
2222 if (fw_major_version != NULL)
2223 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2224 if (fw_minor_version != NULL)
2225 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2226 if (fw_build != NULL)
2227 *fw_build = LE32_TO_CPU(resp->fw_build);
2228 if (api_major_version != NULL)
2229 *api_major_version = LE16_TO_CPU(resp->api_major);
2230 if (api_minor_version != NULL)
2231 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2233 /* A workaround to fix the API version in SW */
2234 if (api_major_version && api_minor_version &&
2235 fw_major_version && fw_minor_version &&
2236 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2237 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2238 (*fw_major_version > 4)))
2239 *api_minor_version = 2;
2246 * i40e_aq_send_driver_version
2247 * @hw: pointer to the hw struct
2248 * @dv: driver's major, minor version
2249 * @cmd_details: pointer to command details structure or NULL
2251 * Send the driver version to the firmware
2253 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2254 struct i40e_driver_version *dv,
2255 struct i40e_asq_cmd_details *cmd_details)
2257 struct i40e_aq_desc desc;
2258 struct i40e_aqc_driver_version *cmd =
2259 (struct i40e_aqc_driver_version *)&desc.params.raw;
2260 enum i40e_status_code status;
2264 return I40E_ERR_PARAM;
2266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2268 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2269 cmd->driver_major_ver = dv->major_version;
2270 cmd->driver_minor_ver = dv->minor_version;
2271 cmd->driver_build_ver = dv->build_version;
2272 cmd->driver_subbuild_ver = dv->subbuild_version;
2275 while (len < sizeof(dv->driver_string) &&
2276 (dv->driver_string[len] < 0x80) &&
2277 dv->driver_string[len])
2279 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2286 * i40e_get_link_status - get status of the HW network link
2287 * @hw: pointer to the hw struct
2288 * @link_up: pointer to bool (true/false = linkup/linkdown)
2290 * Variable link_up true if link is up, false if link is down.
2291 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2293 * Side effect: LinkStatusEvent reporting becomes enabled
2295 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2297 enum i40e_status_code status = I40E_SUCCESS;
2299 if (hw->phy.get_link_info) {
2300 status = i40e_update_link_info(hw);
2302 if (status != I40E_SUCCESS)
2303 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2307 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2313 * i40e_updatelink_status - update status of the HW network link
2314 * @hw: pointer to the hw struct
2316 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2318 struct i40e_aq_get_phy_abilities_resp abilities;
2319 enum i40e_status_code status = I40E_SUCCESS;
2321 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2325 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2330 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2331 sizeof(hw->phy.link_info.module_type));
2337 * i40e_get_link_speed
2338 * @hw: pointer to the hw struct
2340 * Returns the link speed of the adapter.
2342 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2344 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2345 enum i40e_status_code status = I40E_SUCCESS;
2347 if (hw->phy.get_link_info) {
2348 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2350 if (status != I40E_SUCCESS)
2351 goto i40e_link_speed_exit;
2354 speed = hw->phy.link_info.link_speed;
2356 i40e_link_speed_exit:
2361 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2362 * @hw: pointer to the hw struct
2363 * @uplink_seid: the MAC or other gizmo SEID
2364 * @downlink_seid: the VSI SEID
2365 * @enabled_tc: bitmap of TCs to be enabled
2366 * @default_port: true for default port VSI, false for control port
2367 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2368 * @veb_seid: pointer to where to put the resulting VEB SEID
2369 * @cmd_details: pointer to command details structure or NULL
2371 * This asks the FW to add a VEB between the uplink and downlink
2372 * elements. If the uplink SEID is 0, this will be a floating VEB.
2374 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2375 u16 downlink_seid, u8 enabled_tc,
2376 bool default_port, bool enable_l2_filtering,
2378 struct i40e_asq_cmd_details *cmd_details)
2380 struct i40e_aq_desc desc;
2381 struct i40e_aqc_add_veb *cmd =
2382 (struct i40e_aqc_add_veb *)&desc.params.raw;
2383 struct i40e_aqc_add_veb_completion *resp =
2384 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2385 enum i40e_status_code status;
2388 /* SEIDs need to either both be set or both be 0 for floating VEB */
2389 if (!!uplink_seid != !!downlink_seid)
2390 return I40E_ERR_PARAM;
2392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2394 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2395 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2396 cmd->enable_tcs = enabled_tc;
2398 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2400 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2402 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2404 if (enable_l2_filtering)
2405 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2407 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2411 if (!status && veb_seid)
2412 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2418 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2419 * @hw: pointer to the hw struct
2420 * @veb_seid: the SEID of the VEB to query
2421 * @switch_id: the uplink switch id
2422 * @floating: set to true if the VEB is floating
2423 * @statistic_index: index of the stats counter block for this VEB
2424 * @vebs_used: number of VEB's used by function
2425 * @vebs_free: total VEB's not reserved by any function
2426 * @cmd_details: pointer to command details structure or NULL
2428 * This retrieves the parameters for a particular VEB, specified by
2429 * uplink_seid, and returns them to the caller.
2431 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2432 u16 veb_seid, u16 *switch_id,
2433 bool *floating, u16 *statistic_index,
2434 u16 *vebs_used, u16 *vebs_free,
2435 struct i40e_asq_cmd_details *cmd_details)
2437 struct i40e_aq_desc desc;
2438 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2439 (struct i40e_aqc_get_veb_parameters_completion *)
2441 enum i40e_status_code status;
2444 return I40E_ERR_PARAM;
2446 i40e_fill_default_direct_cmd_desc(&desc,
2447 i40e_aqc_opc_get_veb_parameters);
2448 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2450 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2455 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2456 if (statistic_index)
2457 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2459 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2461 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2463 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2464 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2475 * i40e_aq_add_macvlan
2476 * @hw: pointer to the hw struct
2477 * @seid: VSI for the mac address
2478 * @mv_list: list of macvlans to be added
2479 * @count: length of the list
2480 * @cmd_details: pointer to command details structure or NULL
2482 * Add MAC/VLAN addresses to the HW filtering
2484 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2485 struct i40e_aqc_add_macvlan_element_data *mv_list,
2486 u16 count, struct i40e_asq_cmd_details *cmd_details)
2488 struct i40e_aq_desc desc;
2489 struct i40e_aqc_macvlan *cmd =
2490 (struct i40e_aqc_macvlan *)&desc.params.raw;
2491 enum i40e_status_code status;
2494 if (count == 0 || !mv_list || !hw)
2495 return I40E_ERR_PARAM;
2497 buf_size = count * sizeof(*mv_list);
2499 /* prep the rest of the request */
2500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2501 cmd->num_addresses = CPU_TO_LE16(count);
2502 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2506 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2507 if (buf_size > I40E_AQ_LARGE_BUF)
2508 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2510 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2517 * i40e_aq_remove_macvlan
2518 * @hw: pointer to the hw struct
2519 * @seid: VSI for the mac address
2520 * @mv_list: list of macvlans to be removed
2521 * @count: length of the list
2522 * @cmd_details: pointer to command details structure or NULL
2524 * Remove MAC/VLAN addresses from the HW filtering
2526 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2527 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2528 u16 count, struct i40e_asq_cmd_details *cmd_details)
2530 struct i40e_aq_desc desc;
2531 struct i40e_aqc_macvlan *cmd =
2532 (struct i40e_aqc_macvlan *)&desc.params.raw;
2533 enum i40e_status_code status;
2536 if (count == 0 || !mv_list || !hw)
2537 return I40E_ERR_PARAM;
2539 buf_size = count * sizeof(*mv_list);
2541 /* prep the rest of the request */
2542 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2543 cmd->num_addresses = CPU_TO_LE16(count);
2544 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2548 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2549 if (buf_size > I40E_AQ_LARGE_BUF)
2550 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2552 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2559 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2560 * @hw: pointer to the hw struct
2561 * @seid: VSI for the vlan filters
2562 * @v_list: list of vlan filters to be added
2563 * @count: length of the list
2564 * @cmd_details: pointer to command details structure or NULL
2566 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2567 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2568 u8 count, struct i40e_asq_cmd_details *cmd_details)
2570 struct i40e_aq_desc desc;
2571 struct i40e_aqc_macvlan *cmd =
2572 (struct i40e_aqc_macvlan *)&desc.params.raw;
2573 enum i40e_status_code status;
2576 if (count == 0 || !v_list || !hw)
2577 return I40E_ERR_PARAM;
2579 buf_size = count * sizeof(*v_list);
2581 /* prep the rest of the request */
2582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2583 cmd->num_addresses = CPU_TO_LE16(count);
2584 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2588 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2589 if (buf_size > I40E_AQ_LARGE_BUF)
2590 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2592 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2599 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2600 * @hw: pointer to the hw struct
2601 * @seid: VSI for the vlan filters
2602 * @v_list: list of macvlans to be removed
2603 * @count: length of the list
2604 * @cmd_details: pointer to command details structure or NULL
2606 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2607 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2608 u8 count, struct i40e_asq_cmd_details *cmd_details)
2610 struct i40e_aq_desc desc;
2611 struct i40e_aqc_macvlan *cmd =
2612 (struct i40e_aqc_macvlan *)&desc.params.raw;
2613 enum i40e_status_code status;
2616 if (count == 0 || !v_list || !hw)
2617 return I40E_ERR_PARAM;
2619 buf_size = count * sizeof(*v_list);
2621 /* prep the rest of the request */
2622 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2623 cmd->num_addresses = CPU_TO_LE16(count);
2624 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2628 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2629 if (buf_size > I40E_AQ_LARGE_BUF)
2630 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2632 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2639 * i40e_aq_send_msg_to_vf
2640 * @hw: pointer to the hardware structure
2641 * @vfid: vf id to send msg
2642 * @v_opcode: opcodes for VF-PF communication
2643 * @v_retval: return error code
2644 * @msg: pointer to the msg buffer
2645 * @msglen: msg length
2646 * @cmd_details: pointer to command details
2650 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2651 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2652 struct i40e_asq_cmd_details *cmd_details)
2654 struct i40e_aq_desc desc;
2655 struct i40e_aqc_pf_vf_message *cmd =
2656 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2657 enum i40e_status_code status;
2659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2660 cmd->id = CPU_TO_LE32(vfid);
2661 desc.cookie_high = CPU_TO_LE32(v_opcode);
2662 desc.cookie_low = CPU_TO_LE32(v_retval);
2663 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2665 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2667 if (msglen > I40E_AQ_LARGE_BUF)
2668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2669 desc.datalen = CPU_TO_LE16(msglen);
2671 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2677 * i40e_aq_debug_read_register
2678 * @hw: pointer to the hw struct
2679 * @reg_addr: register address
2680 * @reg_val: register value
2681 * @cmd_details: pointer to command details structure or NULL
2683 * Read the register using the admin queue commands
2685 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2686 u32 reg_addr, u64 *reg_val,
2687 struct i40e_asq_cmd_details *cmd_details)
2689 struct i40e_aq_desc desc;
2690 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2691 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2692 enum i40e_status_code status;
2694 if (reg_val == NULL)
2695 return I40E_ERR_PARAM;
2697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2699 cmd_resp->address = CPU_TO_LE32(reg_addr);
2701 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2703 if (status == I40E_SUCCESS) {
2704 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2705 (u64)LE32_TO_CPU(cmd_resp->value_low);
2712 * i40e_aq_debug_write_register
2713 * @hw: pointer to the hw struct
2714 * @reg_addr: register address
2715 * @reg_val: register value
2716 * @cmd_details: pointer to command details structure or NULL
2718 * Write to a register using the admin queue commands
2720 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2721 u32 reg_addr, u64 reg_val,
2722 struct i40e_asq_cmd_details *cmd_details)
2724 struct i40e_aq_desc desc;
2725 struct i40e_aqc_debug_reg_read_write *cmd =
2726 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2727 enum i40e_status_code status;
2729 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2731 cmd->address = CPU_TO_LE32(reg_addr);
2732 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2733 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2741 * i40e_aq_get_hmc_resource_profile
2742 * @hw: pointer to the hw struct
2743 * @profile: type of profile the HMC is to be set as
2744 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2745 * @cmd_details: pointer to command details structure or NULL
2747 * query the HMC profile of the device.
2749 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2750 enum i40e_aq_hmc_profile *profile,
2751 u8 *pe_vf_enabled_count,
2752 struct i40e_asq_cmd_details *cmd_details)
2754 struct i40e_aq_desc desc;
2755 struct i40e_aq_get_set_hmc_resource_profile *resp =
2756 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2757 enum i40e_status_code status;
2759 i40e_fill_default_direct_cmd_desc(&desc,
2760 i40e_aqc_opc_query_hmc_resource_profile);
2761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2763 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2764 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2765 *pe_vf_enabled_count = resp->pe_vf_enabled &
2766 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2772 * i40e_aq_set_hmc_resource_profile
2773 * @hw: pointer to the hw struct
2774 * @profile: type of profile the HMC is to be set as
2775 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2776 * @cmd_details: pointer to command details structure or NULL
2778 * set the HMC profile of the device.
2780 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2781 enum i40e_aq_hmc_profile profile,
2782 u8 pe_vf_enabled_count,
2783 struct i40e_asq_cmd_details *cmd_details)
2785 struct i40e_aq_desc desc;
2786 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2787 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2788 enum i40e_status_code status;
2790 i40e_fill_default_direct_cmd_desc(&desc,
2791 i40e_aqc_opc_set_hmc_resource_profile);
2793 cmd->pm_profile = (u8)profile;
2794 cmd->pe_vf_enabled = pe_vf_enabled_count;
2796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2802 * i40e_aq_request_resource
2803 * @hw: pointer to the hw struct
2804 * @resource: resource id
2805 * @access: access type
2806 * @sdp_number: resource number
2807 * @timeout: the maximum time in ms that the driver may hold the resource
2808 * @cmd_details: pointer to command details structure or NULL
2810 * requests common resource using the admin queue commands
2812 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2813 enum i40e_aq_resources_ids resource,
2814 enum i40e_aq_resource_access_type access,
2815 u8 sdp_number, u64 *timeout,
2816 struct i40e_asq_cmd_details *cmd_details)
2818 struct i40e_aq_desc desc;
2819 struct i40e_aqc_request_resource *cmd_resp =
2820 (struct i40e_aqc_request_resource *)&desc.params.raw;
2821 enum i40e_status_code status;
2823 DEBUGFUNC("i40e_aq_request_resource");
2825 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2827 cmd_resp->resource_id = CPU_TO_LE16(resource);
2828 cmd_resp->access_type = CPU_TO_LE16(access);
2829 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2831 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2832 /* The completion specifies the maximum time in ms that the driver
2833 * may hold the resource in the Timeout field.
2834 * If the resource is held by someone else, the command completes with
2835 * busy return value and the timeout field indicates the maximum time
2836 * the current owner of the resource has to free it.
2838 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2839 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2845 * i40e_aq_release_resource
2846 * @hw: pointer to the hw struct
2847 * @resource: resource id
2848 * @sdp_number: resource number
2849 * @cmd_details: pointer to command details structure or NULL
2851 * release common resource using the admin queue commands
2853 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2854 enum i40e_aq_resources_ids resource,
2856 struct i40e_asq_cmd_details *cmd_details)
2858 struct i40e_aq_desc desc;
2859 struct i40e_aqc_request_resource *cmd =
2860 (struct i40e_aqc_request_resource *)&desc.params.raw;
2861 enum i40e_status_code status;
2863 DEBUGFUNC("i40e_aq_release_resource");
2865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2867 cmd->resource_id = CPU_TO_LE16(resource);
2868 cmd->resource_number = CPU_TO_LE32(sdp_number);
2870 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2877 * @hw: pointer to the hw struct
2878 * @module_pointer: module pointer location in words from the NVM beginning
2879 * @offset: byte offset from the module beginning
2880 * @length: length of the section to be read (in bytes from the offset)
2881 * @data: command buffer (size [bytes] = length)
2882 * @last_command: tells if this is the last command in a series
2883 * @cmd_details: pointer to command details structure or NULL
2885 * Read the NVM using the admin queue commands
2887 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2888 u32 offset, u16 length, void *data,
2890 struct i40e_asq_cmd_details *cmd_details)
2892 struct i40e_aq_desc desc;
2893 struct i40e_aqc_nvm_update *cmd =
2894 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2895 enum i40e_status_code status;
2897 DEBUGFUNC("i40e_aq_read_nvm");
2899 /* In offset the highest byte must be zeroed. */
2900 if (offset & 0xFF000000) {
2901 status = I40E_ERR_PARAM;
2902 goto i40e_aq_read_nvm_exit;
2905 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2907 /* If this is the last command in a series, set the proper flag. */
2909 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2910 cmd->module_pointer = module_pointer;
2911 cmd->offset = CPU_TO_LE32(offset);
2912 cmd->length = CPU_TO_LE16(length);
2914 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2915 if (length > I40E_AQ_LARGE_BUF)
2916 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2918 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2920 i40e_aq_read_nvm_exit:
2925 * i40e_aq_read_nvm_config - read an nvm config block
2926 * @hw: pointer to the hw struct
2927 * @cmd_flags: NVM access admin command bits
2928 * @field_id: field or feature id
2929 * @data: buffer for result
2930 * @buf_size: buffer size
2931 * @element_count: pointer to count of elements read by FW
2932 * @cmd_details: pointer to command details structure or NULL
2934 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2935 u8 cmd_flags, u32 field_id, void *data,
2936 u16 buf_size, u16 *element_count,
2937 struct i40e_asq_cmd_details *cmd_details)
2939 struct i40e_aq_desc desc;
2940 struct i40e_aqc_nvm_config_read *cmd =
2941 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2942 enum i40e_status_code status;
2944 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2945 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2946 if (buf_size > I40E_AQ_LARGE_BUF)
2947 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2949 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2950 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2951 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2952 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2954 cmd->element_id_msw = 0;
2956 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2958 if (!status && element_count)
2959 *element_count = LE16_TO_CPU(cmd->element_count);
2965 * i40e_aq_write_nvm_config - write an nvm config block
2966 * @hw: pointer to the hw struct
2967 * @cmd_flags: NVM access admin command bits
2968 * @data: buffer for result
2969 * @buf_size: buffer size
2970 * @element_count: count of elements to be written
2971 * @cmd_details: pointer to command details structure or NULL
2973 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2974 u8 cmd_flags, void *data, u16 buf_size,
2976 struct i40e_asq_cmd_details *cmd_details)
2978 struct i40e_aq_desc desc;
2979 struct i40e_aqc_nvm_config_write *cmd =
2980 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2981 enum i40e_status_code status;
2983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2984 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2985 if (buf_size > I40E_AQ_LARGE_BUF)
2986 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2988 cmd->element_count = CPU_TO_LE16(element_count);
2989 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2990 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2997 * @hw: pointer to the hw struct
2998 * @module_pointer: module pointer location in words from the NVM beginning
2999 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3000 * @length: length of the section to be erased (expressed in 4 KB)
3001 * @last_command: tells if this is the last command in a series
3002 * @cmd_details: pointer to command details structure or NULL
3004 * Erase the NVM sector using the admin queue commands
3006 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3007 u32 offset, u16 length, bool last_command,
3008 struct i40e_asq_cmd_details *cmd_details)
3010 struct i40e_aq_desc desc;
3011 struct i40e_aqc_nvm_update *cmd =
3012 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3013 enum i40e_status_code status;
3015 DEBUGFUNC("i40e_aq_erase_nvm");
3017 /* In offset the highest byte must be zeroed. */
3018 if (offset & 0xFF000000) {
3019 status = I40E_ERR_PARAM;
3020 goto i40e_aq_erase_nvm_exit;
3023 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3025 /* If this is the last command in a series, set the proper flag. */
3027 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3028 cmd->module_pointer = module_pointer;
3029 cmd->offset = CPU_TO_LE32(offset);
3030 cmd->length = CPU_TO_LE16(length);
3032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3034 i40e_aq_erase_nvm_exit:
3038 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3039 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3040 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3041 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3042 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3043 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3044 #define I40E_DEV_FUNC_CAP_VF 0x13
3045 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3046 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3047 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3048 #define I40E_DEV_FUNC_CAP_VSI 0x17
3049 #define I40E_DEV_FUNC_CAP_DCB 0x18
3050 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3051 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3052 #define I40E_DEV_FUNC_CAP_RSS 0x40
3053 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3054 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3055 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3056 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3057 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3058 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3059 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
3060 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3061 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3062 #define I40E_DEV_FUNC_CAP_LED 0x61
3063 #define I40E_DEV_FUNC_CAP_SDP 0x62
3064 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3067 * i40e_parse_discover_capabilities
3068 * @hw: pointer to the hw struct
3069 * @buff: pointer to a buffer containing device/function capability records
3070 * @cap_count: number of capability records in the list
3071 * @list_type_opc: type of capabilities list to parse
3073 * Parse the device/function capabilities list.
3075 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3077 enum i40e_admin_queue_opc list_type_opc)
3079 struct i40e_aqc_list_capabilities_element_resp *cap;
3080 u32 valid_functions, num_functions;
3081 u32 number, logical_id, phys_id;
3082 struct i40e_hw_capabilities *p;
3086 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3088 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3089 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3090 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3091 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3095 for (i = 0; i < cap_count; i++, cap++) {
3096 id = LE16_TO_CPU(cap->id);
3097 number = LE32_TO_CPU(cap->number);
3098 logical_id = LE32_TO_CPU(cap->logical_id);
3099 phys_id = LE32_TO_CPU(cap->phys_id);
3102 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3103 p->switch_mode = number;
3105 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3106 p->management_mode = number;
3108 case I40E_DEV_FUNC_CAP_NPAR:
3109 p->npar_enable = number;
3111 case I40E_DEV_FUNC_CAP_OS2BMC:
3114 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3115 p->valid_functions = number;
3117 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3119 p->sr_iov_1_1 = true;
3121 case I40E_DEV_FUNC_CAP_VF:
3122 p->num_vfs = number;
3123 p->vf_base_id = logical_id;
3125 case I40E_DEV_FUNC_CAP_VMDQ:
3129 case I40E_DEV_FUNC_CAP_802_1_QBG:
3131 p->evb_802_1_qbg = true;
3133 case I40E_DEV_FUNC_CAP_802_1_QBH:
3135 p->evb_802_1_qbh = true;
3137 case I40E_DEV_FUNC_CAP_VSI:
3138 p->num_vsis = number;
3140 case I40E_DEV_FUNC_CAP_DCB:
3143 p->enabled_tcmap = logical_id;
3147 case I40E_DEV_FUNC_CAP_FCOE:
3151 case I40E_DEV_FUNC_CAP_ISCSI:
3155 case I40E_DEV_FUNC_CAP_RSS:
3157 p->rss_table_size = number;
3158 p->rss_table_entry_width = logical_id;
3160 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3161 p->num_rx_qp = number;
3162 p->base_queue = phys_id;
3164 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3165 p->num_tx_qp = number;
3166 p->base_queue = phys_id;
3168 case I40E_DEV_FUNC_CAP_MSIX:
3169 p->num_msix_vectors = number;
3171 case I40E_DEV_FUNC_CAP_MSIX_VF:
3172 p->num_msix_vectors_vf = number;
3174 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
3176 p->mfp_mode_1 = true;
3178 case I40E_DEV_FUNC_CAP_CEM:
3182 case I40E_DEV_FUNC_CAP_IWARP:
3186 case I40E_DEV_FUNC_CAP_LED:
3187 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3188 p->led[phys_id] = true;
3190 case I40E_DEV_FUNC_CAP_SDP:
3191 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3192 p->sdp[phys_id] = true;
3194 case I40E_DEV_FUNC_CAP_MDIO:
3196 p->mdio_port_num = phys_id;
3197 p->mdio_port_mode = logical_id;
3200 case I40E_DEV_FUNC_CAP_IEEE_1588:
3202 p->ieee_1588 = true;
3204 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3206 p->fd_filters_guaranteed = number;
3207 p->fd_filters_best_effort = logical_id;
3214 #ifdef I40E_FCOE_ENA
3215 /* Software override ensuring FCoE is disabled if npar or mfp
3216 * mode because it is not supported in these modes.
3218 if (p->npar_enable || p->mfp_mode_1)
3221 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3225 /* count the enabled ports (aka the "not disabled" ports) */
3227 for (i = 0; i < 4; i++) {
3228 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3231 /* use AQ read to get the physical register offset instead
3232 * of the port relative offset
3234 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3235 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3239 valid_functions = p->valid_functions;
3241 while (valid_functions) {
3242 if (valid_functions & 1)
3244 valid_functions >>= 1;
3247 /* partition id is 1-based, and functions are evenly spread
3248 * across the ports as partitions
3250 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3251 hw->num_partitions = num_functions / hw->num_ports;
3253 /* additional HW specific goodies that might
3254 * someday be HW version specific
3256 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3260 * i40e_aq_discover_capabilities
3261 * @hw: pointer to the hw struct
3262 * @buff: a virtual buffer to hold the capabilities
3263 * @buff_size: Size of the virtual buffer
3264 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3265 * @list_type_opc: capabilities type to discover - pass in the command opcode
3266 * @cmd_details: pointer to command details structure or NULL
3268 * Get the device capabilities descriptions from the firmware
3270 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3271 void *buff, u16 buff_size, u16 *data_size,
3272 enum i40e_admin_queue_opc list_type_opc,
3273 struct i40e_asq_cmd_details *cmd_details)
3275 struct i40e_aqc_list_capabilites *cmd;
3276 struct i40e_aq_desc desc;
3277 enum i40e_status_code status = I40E_SUCCESS;
3279 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3281 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3282 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3283 status = I40E_ERR_PARAM;
3287 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3289 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3290 if (buff_size > I40E_AQ_LARGE_BUF)
3291 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3293 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3294 *data_size = LE16_TO_CPU(desc.datalen);
3299 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3307 * i40e_aq_update_nvm
3308 * @hw: pointer to the hw struct
3309 * @module_pointer: module pointer location in words from the NVM beginning
3310 * @offset: byte offset from the module beginning
3311 * @length: length of the section to be written (in bytes from the offset)
3312 * @data: command buffer (size [bytes] = length)
3313 * @last_command: tells if this is the last command in a series
3314 * @cmd_details: pointer to command details structure or NULL
3316 * Update the NVM using the admin queue commands
3318 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3319 u32 offset, u16 length, void *data,
3321 struct i40e_asq_cmd_details *cmd_details)
3323 struct i40e_aq_desc desc;
3324 struct i40e_aqc_nvm_update *cmd =
3325 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3326 enum i40e_status_code status;
3328 DEBUGFUNC("i40e_aq_update_nvm");
3330 /* In offset the highest byte must be zeroed. */
3331 if (offset & 0xFF000000) {
3332 status = I40E_ERR_PARAM;
3333 goto i40e_aq_update_nvm_exit;
3336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3338 /* If this is the last command in a series, set the proper flag. */
3340 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3341 cmd->module_pointer = module_pointer;
3342 cmd->offset = CPU_TO_LE32(offset);
3343 cmd->length = CPU_TO_LE16(length);
3345 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3346 if (length > I40E_AQ_LARGE_BUF)
3347 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3349 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3351 i40e_aq_update_nvm_exit:
3356 * i40e_aq_get_lldp_mib
3357 * @hw: pointer to the hw struct
3358 * @bridge_type: type of bridge requested
3359 * @mib_type: Local, Remote or both Local and Remote MIBs
3360 * @buff: pointer to a user supplied buffer to store the MIB block
3361 * @buff_size: size of the buffer (in bytes)
3362 * @local_len : length of the returned Local LLDP MIB
3363 * @remote_len: length of the returned Remote LLDP MIB
3364 * @cmd_details: pointer to command details structure or NULL
3366 * Requests the complete LLDP MIB (entire packet).
3368 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3369 u8 mib_type, void *buff, u16 buff_size,
3370 u16 *local_len, u16 *remote_len,
3371 struct i40e_asq_cmd_details *cmd_details)
3373 struct i40e_aq_desc desc;
3374 struct i40e_aqc_lldp_get_mib *cmd =
3375 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3376 struct i40e_aqc_lldp_get_mib *resp =
3377 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3378 enum i40e_status_code status;
3380 if (buff_size == 0 || !buff)
3381 return I40E_ERR_PARAM;
3383 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3384 /* Indirect Command */
3385 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3387 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3388 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3389 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3391 desc.datalen = CPU_TO_LE16(buff_size);
3393 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3394 if (buff_size > I40E_AQ_LARGE_BUF)
3395 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3397 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3399 if (local_len != NULL)
3400 *local_len = LE16_TO_CPU(resp->local_len);
3401 if (remote_len != NULL)
3402 *remote_len = LE16_TO_CPU(resp->remote_len);
3409 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3410 * @hw: pointer to the hw struct
3411 * @mib_type: Local, Remote or both Local and Remote MIBs
3412 * @buff: pointer to a user supplied buffer to store the MIB block
3413 * @buff_size: size of the buffer (in bytes)
3414 * @cmd_details: pointer to command details structure or NULL
3418 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3419 u8 mib_type, void *buff, u16 buff_size,
3420 struct i40e_asq_cmd_details *cmd_details)
3422 struct i40e_aq_desc desc;
3423 struct i40e_aqc_lldp_set_local_mib *cmd =
3424 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3425 enum i40e_status_code status;
3427 if (buff_size == 0 || !buff)
3428 return I40E_ERR_PARAM;
3430 i40e_fill_default_direct_cmd_desc(&desc,
3431 i40e_aqc_opc_lldp_set_local_mib);
3432 /* Indirect Command */
3433 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3434 if (buff_size > I40E_AQ_LARGE_BUF)
3435 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3436 desc.datalen = CPU_TO_LE16(buff_size);
3438 cmd->type = mib_type;
3439 cmd->length = CPU_TO_LE16(buff_size);
3440 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3441 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3443 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3448 * i40e_aq_cfg_lldp_mib_change_event
3449 * @hw: pointer to the hw struct
3450 * @enable_update: Enable or Disable event posting
3451 * @cmd_details: pointer to command details structure or NULL
3453 * Enable or Disable posting of an event on ARQ when LLDP MIB
3454 * associated with the interface changes
3456 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3458 struct i40e_asq_cmd_details *cmd_details)
3460 struct i40e_aq_desc desc;
3461 struct i40e_aqc_lldp_update_mib *cmd =
3462 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3463 enum i40e_status_code status;
3465 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3468 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3476 * i40e_aq_add_lldp_tlv
3477 * @hw: pointer to the hw struct
3478 * @bridge_type: type of bridge
3479 * @buff: buffer with TLV to add
3480 * @buff_size: length of the buffer
3481 * @tlv_len: length of the TLV to be added
3482 * @mib_len: length of the LLDP MIB returned in response
3483 * @cmd_details: pointer to command details structure or NULL
3485 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3486 * it is responsibility of the caller to make sure that the TLV is not
3487 * already present in the LLDPDU.
3488 * In return firmware will write the complete LLDP MIB with the newly
3489 * added TLV in the response buffer.
3491 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3492 void *buff, u16 buff_size, u16 tlv_len,
3494 struct i40e_asq_cmd_details *cmd_details)
3496 struct i40e_aq_desc desc;
3497 struct i40e_aqc_lldp_add_tlv *cmd =
3498 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3499 enum i40e_status_code status;
3501 if (buff_size == 0 || !buff || tlv_len == 0)
3502 return I40E_ERR_PARAM;
3504 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3506 /* Indirect Command */
3507 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3508 if (buff_size > I40E_AQ_LARGE_BUF)
3509 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3510 desc.datalen = CPU_TO_LE16(buff_size);
3512 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3513 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3514 cmd->len = CPU_TO_LE16(tlv_len);
3516 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3518 if (mib_len != NULL)
3519 *mib_len = LE16_TO_CPU(desc.datalen);
3526 * i40e_aq_update_lldp_tlv
3527 * @hw: pointer to the hw struct
3528 * @bridge_type: type of bridge
3529 * @buff: buffer with TLV to update
3530 * @buff_size: size of the buffer holding original and updated TLVs
3531 * @old_len: Length of the Original TLV
3532 * @new_len: Length of the Updated TLV
3533 * @offset: offset of the updated TLV in the buff
3534 * @mib_len: length of the returned LLDP MIB
3535 * @cmd_details: pointer to command details structure or NULL
3537 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3538 * Firmware will place the complete LLDP MIB in response buffer with the
3541 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3542 u8 bridge_type, void *buff, u16 buff_size,
3543 u16 old_len, u16 new_len, u16 offset,
3545 struct i40e_asq_cmd_details *cmd_details)
3547 struct i40e_aq_desc desc;
3548 struct i40e_aqc_lldp_update_tlv *cmd =
3549 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3550 enum i40e_status_code status;
3552 if (buff_size == 0 || !buff || offset == 0 ||
3553 old_len == 0 || new_len == 0)
3554 return I40E_ERR_PARAM;
3556 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3558 /* Indirect Command */
3559 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3560 if (buff_size > I40E_AQ_LARGE_BUF)
3561 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3562 desc.datalen = CPU_TO_LE16(buff_size);
3564 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3565 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3566 cmd->old_len = CPU_TO_LE16(old_len);
3567 cmd->new_offset = CPU_TO_LE16(offset);
3568 cmd->new_len = CPU_TO_LE16(new_len);
3570 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3572 if (mib_len != NULL)
3573 *mib_len = LE16_TO_CPU(desc.datalen);
3580 * i40e_aq_delete_lldp_tlv
3581 * @hw: pointer to the hw struct
3582 * @bridge_type: type of bridge
3583 * @buff: pointer to a user supplied buffer that has the TLV
3584 * @buff_size: length of the buffer
3585 * @tlv_len: length of the TLV to be deleted
3586 * @mib_len: length of the returned LLDP MIB
3587 * @cmd_details: pointer to command details structure or NULL
3589 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3590 * The firmware places the entire LLDP MIB in the response buffer.
3592 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3593 u8 bridge_type, void *buff, u16 buff_size,
3594 u16 tlv_len, u16 *mib_len,
3595 struct i40e_asq_cmd_details *cmd_details)
3597 struct i40e_aq_desc desc;
3598 struct i40e_aqc_lldp_add_tlv *cmd =
3599 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3600 enum i40e_status_code status;
3602 if (buff_size == 0 || !buff)
3603 return I40E_ERR_PARAM;
3605 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3607 /* Indirect Command */
3608 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3609 if (buff_size > I40E_AQ_LARGE_BUF)
3610 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3611 desc.datalen = CPU_TO_LE16(buff_size);
3612 cmd->len = CPU_TO_LE16(tlv_len);
3613 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3614 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3616 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3618 if (mib_len != NULL)
3619 *mib_len = LE16_TO_CPU(desc.datalen);
3627 * @hw: pointer to the hw struct
3628 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3629 * @cmd_details: pointer to command details structure or NULL
3631 * Stop or Shutdown the embedded LLDP Agent
3633 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3634 struct i40e_asq_cmd_details *cmd_details)
3636 struct i40e_aq_desc desc;
3637 struct i40e_aqc_lldp_stop *cmd =
3638 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3639 enum i40e_status_code status;
3641 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3644 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3652 * i40e_aq_start_lldp
3653 * @hw: pointer to the hw struct
3654 * @cmd_details: pointer to command details structure or NULL
3656 * Start the embedded LLDP Agent on all ports.
3658 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3659 struct i40e_asq_cmd_details *cmd_details)
3661 struct i40e_aq_desc desc;
3662 struct i40e_aqc_lldp_start *cmd =
3663 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3664 enum i40e_status_code status;
3666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3668 cmd->command = I40E_AQ_LLDP_AGENT_START;
3670 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3676 * i40e_aq_get_cee_dcb_config
3677 * @hw: pointer to the hw struct
3678 * @buff: response buffer that stores CEE operational configuration
3679 * @buff_size: size of the buffer passed
3680 * @cmd_details: pointer to command details structure or NULL
3682 * Get CEE DCBX mode operational configuration from firmware
3684 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3685 void *buff, u16 buff_size,
3686 struct i40e_asq_cmd_details *cmd_details)
3688 struct i40e_aq_desc desc;
3689 enum i40e_status_code status;
3691 if (buff_size == 0 || !buff)
3692 return I40E_ERR_PARAM;
3694 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3696 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3697 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3704 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3705 * @hw: pointer to the hw struct
3706 * @start_agent: True if DCBx Agent needs to be Started
3707 * False if DCBx Agent needs to be Stopped
3708 * @cmd_details: pointer to command details structure or NULL
3710 * Start/Stop the embedded dcbx Agent
3712 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3714 struct i40e_asq_cmd_details *cmd_details)
3716 struct i40e_aq_desc desc;
3717 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3718 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3720 enum i40e_status_code status;
3722 i40e_fill_default_direct_cmd_desc(&desc,
3723 i40e_aqc_opc_lldp_stop_start_spec_agent);
3726 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3728 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3734 * i40e_aq_add_udp_tunnel
3735 * @hw: pointer to the hw struct
3736 * @udp_port: the UDP port to add
3737 * @header_len: length of the tunneling header length in DWords
3738 * @protocol_index: protocol index type
3739 * @filter_index: pointer to filter index
3740 * @cmd_details: pointer to command details structure or NULL
3742 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3743 u16 udp_port, u8 protocol_index,
3745 struct i40e_asq_cmd_details *cmd_details)
3747 struct i40e_aq_desc desc;
3748 struct i40e_aqc_add_udp_tunnel *cmd =
3749 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3750 struct i40e_aqc_del_udp_tunnel_completion *resp =
3751 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3752 enum i40e_status_code status;
3754 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3756 cmd->udp_port = CPU_TO_LE16(udp_port);
3757 cmd->protocol_type = protocol_index;
3759 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3761 if (!status && filter_index)
3762 *filter_index = resp->index;
3768 * i40e_aq_del_udp_tunnel
3769 * @hw: pointer to the hw struct
3770 * @index: filter index
3771 * @cmd_details: pointer to command details structure or NULL
3773 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3774 struct i40e_asq_cmd_details *cmd_details)
3776 struct i40e_aq_desc desc;
3777 struct i40e_aqc_remove_udp_tunnel *cmd =
3778 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3779 enum i40e_status_code status;
3781 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3785 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3791 * i40e_aq_get_switch_resource_alloc (0x0204)
3792 * @hw: pointer to the hw struct
3793 * @num_entries: pointer to u8 to store the number of resource entries returned
3794 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3795 * to store the resource information for all resource types. Each
3796 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3797 * @count: size, in bytes, of the buffer provided
3798 * @cmd_details: pointer to command details structure or NULL
3800 * Query the resources allocated to a function.
3802 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3804 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3806 struct i40e_asq_cmd_details *cmd_details)
3808 struct i40e_aq_desc desc;
3809 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3810 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3811 enum i40e_status_code status;
3812 u16 length = count * sizeof(*buf);
3814 i40e_fill_default_direct_cmd_desc(&desc,
3815 i40e_aqc_opc_get_switch_resource_alloc);
3817 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3818 if (length > I40E_AQ_LARGE_BUF)
3819 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3821 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3823 if (!status && num_entries)
3824 *num_entries = cmd_resp->num_entries;
3830 * i40e_aq_delete_element - Delete switch element
3831 * @hw: pointer to the hw struct
3832 * @seid: the SEID to delete from the switch
3833 * @cmd_details: pointer to command details structure or NULL
3835 * This deletes a switch element from the switch.
3837 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3838 struct i40e_asq_cmd_details *cmd_details)
3840 struct i40e_aq_desc desc;
3841 struct i40e_aqc_switch_seid *cmd =
3842 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3843 enum i40e_status_code status;
3846 return I40E_ERR_PARAM;
3848 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3850 cmd->seid = CPU_TO_LE16(seid);
3852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3858 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3859 * @hw: pointer to the hw struct
3860 * @flags: component flags
3861 * @mac_seid: uplink seid (MAC SEID)
3862 * @vsi_seid: connected vsi seid
3863 * @ret_seid: seid of create pv component
3865 * This instantiates an i40e port virtualizer with specified flags.
3866 * Depending on specified flags the port virtualizer can act as a
3867 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3869 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3870 u16 mac_seid, u16 vsi_seid,
3873 struct i40e_aq_desc desc;
3874 struct i40e_aqc_add_update_pv *cmd =
3875 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3876 struct i40e_aqc_add_update_pv_completion *resp =
3877 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3878 enum i40e_status_code status;
3881 return I40E_ERR_PARAM;
3883 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3884 cmd->command_flags = CPU_TO_LE16(flags);
3885 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3886 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3888 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3889 if (!status && ret_seid)
3890 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3896 * i40e_aq_add_tag - Add an S/E-tag
3897 * @hw: pointer to the hw struct
3898 * @direct_to_queue: should s-tag direct flow to a specific queue
3899 * @vsi_seid: VSI SEID to use this tag
3900 * @tag: value of the tag
3901 * @queue_num: queue number, only valid is direct_to_queue is true
3902 * @tags_used: return value, number of tags in use by this PF
3903 * @tags_free: return value, number of unallocated tags
3904 * @cmd_details: pointer to command details structure or NULL
3906 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3907 * the number of tags allocated by the PF, and the number of unallocated
3910 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3911 u16 vsi_seid, u16 tag, u16 queue_num,
3912 u16 *tags_used, u16 *tags_free,
3913 struct i40e_asq_cmd_details *cmd_details)
3915 struct i40e_aq_desc desc;
3916 struct i40e_aqc_add_tag *cmd =
3917 (struct i40e_aqc_add_tag *)&desc.params.raw;
3918 struct i40e_aqc_add_remove_tag_completion *resp =
3919 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3920 enum i40e_status_code status;
3923 return I40E_ERR_PARAM;
3925 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3927 cmd->seid = CPU_TO_LE16(vsi_seid);
3928 cmd->tag = CPU_TO_LE16(tag);
3929 if (direct_to_queue) {
3930 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3931 cmd->queue_number = CPU_TO_LE16(queue_num);
3934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3937 if (tags_used != NULL)
3938 *tags_used = LE16_TO_CPU(resp->tags_used);
3939 if (tags_free != NULL)
3940 *tags_free = LE16_TO_CPU(resp->tags_free);
3947 * i40e_aq_remove_tag - Remove an S- or E-tag
3948 * @hw: pointer to the hw struct
3949 * @vsi_seid: VSI SEID this tag is associated with
3950 * @tag: value of the S-tag to delete
3951 * @tags_used: return value, number of tags in use by this PF
3952 * @tags_free: return value, number of unallocated tags
3953 * @cmd_details: pointer to command details structure or NULL
3955 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3956 * the number of tags allocated by the PF, and the number of unallocated
3959 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3960 u16 tag, u16 *tags_used, u16 *tags_free,
3961 struct i40e_asq_cmd_details *cmd_details)
3963 struct i40e_aq_desc desc;
3964 struct i40e_aqc_remove_tag *cmd =
3965 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3966 struct i40e_aqc_add_remove_tag_completion *resp =
3967 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3968 enum i40e_status_code status;
3971 return I40E_ERR_PARAM;
3973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3975 cmd->seid = CPU_TO_LE16(vsi_seid);
3976 cmd->tag = CPU_TO_LE16(tag);
3978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3981 if (tags_used != NULL)
3982 *tags_used = LE16_TO_CPU(resp->tags_used);
3983 if (tags_free != NULL)
3984 *tags_free = LE16_TO_CPU(resp->tags_free);
3991 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3992 * @hw: pointer to the hw struct
3993 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3994 * @etag: value of E-tag to add
3995 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3996 * @buf: address of indirect buffer
3997 * @tags_used: return value, number of E-tags in use by this port
3998 * @tags_free: return value, number of unallocated M-tags
3999 * @cmd_details: pointer to command details structure or NULL
4001 * This associates a multicast E-tag to a port virtualizer. It will return
4002 * the number of tags allocated by the PF, and the number of unallocated
4005 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4006 * num_tags_in_buf long.
4008 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4009 u16 etag, u8 num_tags_in_buf, void *buf,
4010 u16 *tags_used, u16 *tags_free,
4011 struct i40e_asq_cmd_details *cmd_details)
4013 struct i40e_aq_desc desc;
4014 struct i40e_aqc_add_remove_mcast_etag *cmd =
4015 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4016 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4017 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4018 enum i40e_status_code status;
4019 u16 length = sizeof(u16) * num_tags_in_buf;
4021 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4022 return I40E_ERR_PARAM;
4024 i40e_fill_default_direct_cmd_desc(&desc,
4025 i40e_aqc_opc_add_multicast_etag);
4027 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4028 cmd->etag = CPU_TO_LE16(etag);
4029 cmd->num_unicast_etags = num_tags_in_buf;
4031 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4032 if (length > I40E_AQ_LARGE_BUF)
4033 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4035 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4038 if (tags_used != NULL)
4039 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4040 if (tags_free != NULL)
4041 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4048 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4049 * @hw: pointer to the hw struct
4050 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4051 * @etag: value of the E-tag to remove
4052 * @tags_used: return value, number of tags in use by this port
4053 * @tags_free: return value, number of unallocated tags
4054 * @cmd_details: pointer to command details structure or NULL
4056 * This deletes an E-tag from the port virtualizer. It will return
4057 * the number of tags allocated by the port, and the number of unallocated
4060 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4061 u16 etag, u16 *tags_used, u16 *tags_free,
4062 struct i40e_asq_cmd_details *cmd_details)
4064 struct i40e_aq_desc desc;
4065 struct i40e_aqc_add_remove_mcast_etag *cmd =
4066 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4067 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4068 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4069 enum i40e_status_code status;
4073 return I40E_ERR_PARAM;
4075 i40e_fill_default_direct_cmd_desc(&desc,
4076 i40e_aqc_opc_remove_multicast_etag);
4078 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4079 cmd->etag = CPU_TO_LE16(etag);
4081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4084 if (tags_used != NULL)
4085 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4086 if (tags_free != NULL)
4087 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4094 * i40e_aq_update_tag - Update an S/E-tag
4095 * @hw: pointer to the hw struct
4096 * @vsi_seid: VSI SEID using this S-tag
4097 * @old_tag: old tag value
4098 * @new_tag: new tag value
4099 * @tags_used: return value, number of tags in use by this PF
4100 * @tags_free: return value, number of unallocated tags
4101 * @cmd_details: pointer to command details structure or NULL
4103 * This updates the value of the tag currently attached to this VSI
4104 * in the switch complex. It will return the number of tags allocated
4105 * by the PF, and the number of unallocated tags available.
4107 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4108 u16 old_tag, u16 new_tag, u16 *tags_used,
4110 struct i40e_asq_cmd_details *cmd_details)
4112 struct i40e_aq_desc desc;
4113 struct i40e_aqc_update_tag *cmd =
4114 (struct i40e_aqc_update_tag *)&desc.params.raw;
4115 struct i40e_aqc_update_tag_completion *resp =
4116 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4117 enum i40e_status_code status;
4120 return I40E_ERR_PARAM;
4122 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4124 cmd->seid = CPU_TO_LE16(vsi_seid);
4125 cmd->old_tag = CPU_TO_LE16(old_tag);
4126 cmd->new_tag = CPU_TO_LE16(new_tag);
4128 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4131 if (tags_used != NULL)
4132 *tags_used = LE16_TO_CPU(resp->tags_used);
4133 if (tags_free != NULL)
4134 *tags_free = LE16_TO_CPU(resp->tags_free);
4141 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4142 * @hw: pointer to the hw struct
4143 * @tcmap: TC map for request/release any ignore PFC condition
4144 * @request: request or release ignore PFC condition
4145 * @tcmap_ret: return TCs for which PFC is currently ignored
4146 * @cmd_details: pointer to command details structure or NULL
4148 * This sends out request/release to ignore PFC condition for a TC.
4149 * It will return the TCs for which PFC is currently ignored.
4151 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4152 bool request, u8 *tcmap_ret,
4153 struct i40e_asq_cmd_details *cmd_details)
4155 struct i40e_aq_desc desc;
4156 struct i40e_aqc_pfc_ignore *cmd_resp =
4157 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4158 enum i40e_status_code status;
4160 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4163 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4165 cmd_resp->tc_bitmap = tcmap;
4167 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4170 if (tcmap_ret != NULL)
4171 *tcmap_ret = cmd_resp->tc_bitmap;
4178 * i40e_aq_dcb_updated - DCB Updated Command
4179 * @hw: pointer to the hw struct
4180 * @cmd_details: pointer to command details structure or NULL
4182 * When LLDP is handled in PF this command is used by the PF
4183 * to notify EMP that a DCB setting is modified.
4184 * When LLDP is handled in EMP this command is used by the PF
4185 * to notify EMP whenever one of the following parameters get
4187 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4188 * - PCIRTT in PRTDCB_GENC.PCIRTT
4189 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4190 * EMP will return when the shared RPB settings have been
4191 * recomputed and modified. The retval field in the descriptor
4192 * will be set to 0 when RPB is modified.
4194 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4195 struct i40e_asq_cmd_details *cmd_details)
4197 struct i40e_aq_desc desc;
4198 enum i40e_status_code status;
4200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4202 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4208 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4209 * @hw: pointer to the hw struct
4210 * @seid: defines the SEID of the switch for which the stats are requested
4211 * @vlan_id: the VLAN ID for which the statistics are requested
4212 * @stat_index: index of the statistics counters block assigned to this VLAN
4213 * @cmd_details: pointer to command details structure or NULL
4215 * XL710 supports 128 smonVlanStats counters.This command is used to
4216 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4219 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4220 u16 vlan_id, u16 *stat_index,
4221 struct i40e_asq_cmd_details *cmd_details)
4223 struct i40e_aq_desc desc;
4224 struct i40e_aqc_add_remove_statistics *cmd_resp =
4225 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4226 enum i40e_status_code status;
4228 if ((seid == 0) || (stat_index == NULL))
4229 return I40E_ERR_PARAM;
4231 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4233 cmd_resp->seid = CPU_TO_LE16(seid);
4234 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4238 if (!status && stat_index)
4239 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4245 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4246 * @hw: pointer to the hw struct
4247 * @seid: defines the SEID of the switch for which the stats are requested
4248 * @vlan_id: the VLAN ID for which the statistics are requested
4249 * @stat_index: index of the statistics counters block assigned to this VLAN
4250 * @cmd_details: pointer to command details structure or NULL
4252 * XL710 supports 128 smonVlanStats counters.This command is used to
4253 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4256 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4257 u16 vlan_id, u16 stat_index,
4258 struct i40e_asq_cmd_details *cmd_details)
4260 struct i40e_aq_desc desc;
4261 struct i40e_aqc_add_remove_statistics *cmd =
4262 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4263 enum i40e_status_code status;
4266 return I40E_ERR_PARAM;
4268 i40e_fill_default_direct_cmd_desc(&desc,
4269 i40e_aqc_opc_remove_statistics);
4271 cmd->seid = CPU_TO_LE16(seid);
4272 cmd->vlan = CPU_TO_LE16(vlan_id);
4273 cmd->stat_index = CPU_TO_LE16(stat_index);
4275 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4281 * i40e_aq_set_port_parameters - set physical port parameters.
4282 * @hw: pointer to the hw struct
4283 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4284 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4285 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4286 * @double_vlan: if set double VLAN is enabled
4287 * @cmd_details: pointer to command details structure or NULL
4289 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4290 u16 bad_frame_vsi, bool save_bad_pac,
4291 bool pad_short_pac, bool double_vlan,
4292 struct i40e_asq_cmd_details *cmd_details)
4294 struct i40e_aqc_set_port_parameters *cmd;
4295 enum i40e_status_code status;
4296 struct i40e_aq_desc desc;
4297 u16 command_flags = 0;
4299 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4301 i40e_fill_default_direct_cmd_desc(&desc,
4302 i40e_aqc_opc_set_port_parameters);
4304 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4306 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4308 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4310 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4311 cmd->command_flags = CPU_TO_LE16(command_flags);
4313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4319 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4320 * @hw: pointer to the hw struct
4321 * @seid: seid for the physical port/switching component/vsi
4322 * @buff: Indirect buffer to hold data parameters and response
4323 * @buff_size: Indirect buffer size
4324 * @opcode: Tx scheduler AQ command opcode
4325 * @cmd_details: pointer to command details structure or NULL
4327 * Generic command handler for Tx scheduler AQ commands
4329 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4330 void *buff, u16 buff_size,
4331 enum i40e_admin_queue_opc opcode,
4332 struct i40e_asq_cmd_details *cmd_details)
4334 struct i40e_aq_desc desc;
4335 struct i40e_aqc_tx_sched_ind *cmd =
4336 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4337 enum i40e_status_code status;
4338 bool cmd_param_flag = false;
4341 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4342 case i40e_aqc_opc_configure_vsi_tc_bw:
4343 case i40e_aqc_opc_enable_switching_comp_ets:
4344 case i40e_aqc_opc_modify_switching_comp_ets:
4345 case i40e_aqc_opc_disable_switching_comp_ets:
4346 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4347 case i40e_aqc_opc_configure_switching_comp_bw_config:
4348 cmd_param_flag = true;
4350 case i40e_aqc_opc_query_vsi_bw_config:
4351 case i40e_aqc_opc_query_vsi_ets_sla_config:
4352 case i40e_aqc_opc_query_switching_comp_ets_config:
4353 case i40e_aqc_opc_query_port_ets_config:
4354 case i40e_aqc_opc_query_switching_comp_bw_config:
4355 cmd_param_flag = false;
4358 return I40E_ERR_PARAM;
4361 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4363 /* Indirect command */
4364 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4366 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4367 if (buff_size > I40E_AQ_LARGE_BUF)
4368 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4370 desc.datalen = CPU_TO_LE16(buff_size);
4372 cmd->vsi_seid = CPU_TO_LE16(seid);
4374 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4380 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4381 * @hw: pointer to the hw struct
4383 * @credit: BW limit credits (0 = disabled)
4384 * @max_credit: Max BW limit credits
4385 * @cmd_details: pointer to command details structure or NULL
4387 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4388 u16 seid, u16 credit, u8 max_credit,
4389 struct i40e_asq_cmd_details *cmd_details)
4391 struct i40e_aq_desc desc;
4392 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4393 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4394 enum i40e_status_code status;
4396 i40e_fill_default_direct_cmd_desc(&desc,
4397 i40e_aqc_opc_configure_vsi_bw_limit);
4399 cmd->vsi_seid = CPU_TO_LE16(seid);
4400 cmd->credit = CPU_TO_LE16(credit);
4401 cmd->max_credit = max_credit;
4403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4409 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4410 * @hw: pointer to the hw struct
4411 * @seid: switching component seid
4412 * @credit: BW limit credits (0 = disabled)
4413 * @max_bw: Max BW limit credits
4414 * @cmd_details: pointer to command details structure or NULL
4416 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4417 u16 seid, u16 credit, u8 max_bw,
4418 struct i40e_asq_cmd_details *cmd_details)
4420 struct i40e_aq_desc desc;
4421 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4422 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4423 enum i40e_status_code status;
4425 i40e_fill_default_direct_cmd_desc(&desc,
4426 i40e_aqc_opc_configure_switching_comp_bw_limit);
4428 cmd->seid = CPU_TO_LE16(seid);
4429 cmd->credit = CPU_TO_LE16(credit);
4430 cmd->max_bw = max_bw;
4432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4438 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4439 * @hw: pointer to the hw struct
4441 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4442 * @cmd_details: pointer to command details structure or NULL
4444 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4446 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4447 struct i40e_asq_cmd_details *cmd_details)
4449 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4450 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4455 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4456 * @hw: pointer to the hw struct
4458 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4459 * @cmd_details: pointer to command details structure or NULL
4461 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4463 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4464 struct i40e_asq_cmd_details *cmd_details)
4466 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4467 i40e_aqc_opc_configure_vsi_tc_bw,
4472 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4473 * @hw: pointer to the hw struct
4474 * @seid: seid of the switching component connected to Physical Port
4475 * @ets_data: Buffer holding ETS parameters
4476 * @cmd_details: pointer to command details structure or NULL
4478 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4480 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4481 enum i40e_admin_queue_opc opcode,
4482 struct i40e_asq_cmd_details *cmd_details)
4484 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4485 sizeof(*ets_data), opcode, cmd_details);
4489 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4490 * @hw: pointer to the hw struct
4491 * @seid: seid of the switching component
4492 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4493 * @cmd_details: pointer to command details structure or NULL
4495 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4497 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4498 struct i40e_asq_cmd_details *cmd_details)
4500 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4501 i40e_aqc_opc_configure_switching_comp_bw_config,
4506 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4507 * @hw: pointer to the hw struct
4508 * @seid: seid of the switching component
4509 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4510 * @cmd_details: pointer to command details structure or NULL
4512 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4513 struct i40e_hw *hw, u16 seid,
4514 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4515 struct i40e_asq_cmd_details *cmd_details)
4517 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4518 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4523 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4524 * @hw: pointer to the hw struct
4525 * @seid: seid of the VSI
4526 * @bw_data: Buffer to hold VSI BW configuration
4527 * @cmd_details: pointer to command details structure or NULL
4529 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4531 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4532 struct i40e_asq_cmd_details *cmd_details)
4534 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4535 i40e_aqc_opc_query_vsi_bw_config,
4540 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4541 * @hw: pointer to the hw struct
4542 * @seid: seid of the VSI
4543 * @bw_data: Buffer to hold VSI BW configuration per TC
4544 * @cmd_details: pointer to command details structure or NULL
4546 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4548 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4549 struct i40e_asq_cmd_details *cmd_details)
4551 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4552 i40e_aqc_opc_query_vsi_ets_sla_config,
4557 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4558 * @hw: pointer to the hw struct
4559 * @seid: seid of the switching component
4560 * @bw_data: Buffer to hold switching component's per TC BW config
4561 * @cmd_details: pointer to command details structure or NULL
4563 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4565 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4566 struct i40e_asq_cmd_details *cmd_details)
4568 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4569 i40e_aqc_opc_query_switching_comp_ets_config,
4574 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4575 * @hw: pointer to the hw struct
4576 * @seid: seid of the VSI or switching component connected to Physical Port
4577 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4578 * @cmd_details: pointer to command details structure or NULL
4580 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4582 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4583 struct i40e_asq_cmd_details *cmd_details)
4585 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4586 i40e_aqc_opc_query_port_ets_config,
4591 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4592 * @hw: pointer to the hw struct
4593 * @seid: seid of the switching component
4594 * @bw_data: Buffer to hold switching component's BW configuration
4595 * @cmd_details: pointer to command details structure or NULL
4597 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4599 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4600 struct i40e_asq_cmd_details *cmd_details)
4602 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4603 i40e_aqc_opc_query_switching_comp_bw_config,
4608 * i40e_validate_filter_settings
4609 * @hw: pointer to the hardware structure
4610 * @settings: Filter control settings
4612 * Check and validate the filter control settings passed.
4613 * The function checks for the valid filter/context sizes being
4614 * passed for FCoE and PE.
4616 * Returns I40E_SUCCESS if the values passed are valid and within
4617 * range else returns an error.
4619 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4620 struct i40e_filter_control_settings *settings)
4622 u32 fcoe_cntx_size, fcoe_filt_size;
4623 u32 pe_cntx_size, pe_filt_size;
4628 /* Validate FCoE settings passed */
4629 switch (settings->fcoe_filt_num) {
4630 case I40E_HASH_FILTER_SIZE_1K:
4631 case I40E_HASH_FILTER_SIZE_2K:
4632 case I40E_HASH_FILTER_SIZE_4K:
4633 case I40E_HASH_FILTER_SIZE_8K:
4634 case I40E_HASH_FILTER_SIZE_16K:
4635 case I40E_HASH_FILTER_SIZE_32K:
4636 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4637 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4640 return I40E_ERR_PARAM;
4643 switch (settings->fcoe_cntx_num) {
4644 case I40E_DMA_CNTX_SIZE_512:
4645 case I40E_DMA_CNTX_SIZE_1K:
4646 case I40E_DMA_CNTX_SIZE_2K:
4647 case I40E_DMA_CNTX_SIZE_4K:
4648 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4649 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4652 return I40E_ERR_PARAM;
4655 /* Validate PE settings passed */
4656 switch (settings->pe_filt_num) {
4657 case I40E_HASH_FILTER_SIZE_1K:
4658 case I40E_HASH_FILTER_SIZE_2K:
4659 case I40E_HASH_FILTER_SIZE_4K:
4660 case I40E_HASH_FILTER_SIZE_8K:
4661 case I40E_HASH_FILTER_SIZE_16K:
4662 case I40E_HASH_FILTER_SIZE_32K:
4663 case I40E_HASH_FILTER_SIZE_64K:
4664 case I40E_HASH_FILTER_SIZE_128K:
4665 case I40E_HASH_FILTER_SIZE_256K:
4666 case I40E_HASH_FILTER_SIZE_512K:
4667 case I40E_HASH_FILTER_SIZE_1M:
4668 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4669 pe_filt_size <<= (u32)settings->pe_filt_num;
4672 return I40E_ERR_PARAM;
4675 switch (settings->pe_cntx_num) {
4676 case I40E_DMA_CNTX_SIZE_512:
4677 case I40E_DMA_CNTX_SIZE_1K:
4678 case I40E_DMA_CNTX_SIZE_2K:
4679 case I40E_DMA_CNTX_SIZE_4K:
4680 case I40E_DMA_CNTX_SIZE_8K:
4681 case I40E_DMA_CNTX_SIZE_16K:
4682 case I40E_DMA_CNTX_SIZE_32K:
4683 case I40E_DMA_CNTX_SIZE_64K:
4684 case I40E_DMA_CNTX_SIZE_128K:
4685 case I40E_DMA_CNTX_SIZE_256K:
4686 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4687 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4690 return I40E_ERR_PARAM;
4693 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4694 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4695 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4696 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4697 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4698 return I40E_ERR_INVALID_SIZE;
4700 return I40E_SUCCESS;
4704 * i40e_set_filter_control
4705 * @hw: pointer to the hardware structure
4706 * @settings: Filter control settings
4708 * Set the Queue Filters for PE/FCoE and enable filters required
4709 * for a single PF. It is expected that these settings are programmed
4710 * at the driver initialization time.
4712 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4713 struct i40e_filter_control_settings *settings)
4715 enum i40e_status_code ret = I40E_SUCCESS;
4716 u32 hash_lut_size = 0;
4720 return I40E_ERR_PARAM;
4722 /* Validate the input settings */
4723 ret = i40e_validate_filter_settings(hw, settings);
4727 /* Read the PF Queue Filter control register */
4728 val = rd32(hw, I40E_PFQF_CTL_0);
4730 /* Program required PE hash buckets for the PF */
4731 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4732 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4733 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4734 /* Program required PE contexts for the PF */
4735 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4736 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4737 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4739 /* Program required FCoE hash buckets for the PF */
4740 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4741 val |= ((u32)settings->fcoe_filt_num <<
4742 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4743 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4744 /* Program required FCoE DDP contexts for the PF */
4745 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4746 val |= ((u32)settings->fcoe_cntx_num <<
4747 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4748 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4750 /* Program Hash LUT size for the PF */
4751 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4752 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4754 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4755 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4757 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4758 if (settings->enable_fdir)
4759 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4760 if (settings->enable_ethtype)
4761 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4762 if (settings->enable_macvlan)
4763 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4765 wr32(hw, I40E_PFQF_CTL_0, val);
4767 return I40E_SUCCESS;
4771 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4772 * @hw: pointer to the hw struct
4773 * @mac_addr: MAC address to use in the filter
4774 * @ethtype: Ethertype to use in the filter
4775 * @flags: Flags that needs to be applied to the filter
4776 * @vsi_seid: seid of the control VSI
4777 * @queue: VSI queue number to send the packet to
4778 * @is_add: Add control packet filter if True else remove
4779 * @stats: Structure to hold information on control filter counts
4780 * @cmd_details: pointer to command details structure or NULL
4782 * This command will Add or Remove control packet filter for a control VSI.
4783 * In return it will update the total number of perfect filter count in
4786 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4787 u8 *mac_addr, u16 ethtype, u16 flags,
4788 u16 vsi_seid, u16 queue, bool is_add,
4789 struct i40e_control_filter_stats *stats,
4790 struct i40e_asq_cmd_details *cmd_details)
4792 struct i40e_aq_desc desc;
4793 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4794 (struct i40e_aqc_add_remove_control_packet_filter *)
4796 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4797 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4799 enum i40e_status_code status;
4802 return I40E_ERR_PARAM;
4805 i40e_fill_default_direct_cmd_desc(&desc,
4806 i40e_aqc_opc_add_control_packet_filter);
4807 cmd->queue = CPU_TO_LE16(queue);
4809 i40e_fill_default_direct_cmd_desc(&desc,
4810 i40e_aqc_opc_remove_control_packet_filter);
4814 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4815 I40E_NONDMA_TO_NONDMA);
4817 cmd->etype = CPU_TO_LE16(ethtype);
4818 cmd->flags = CPU_TO_LE16(flags);
4819 cmd->seid = CPU_TO_LE16(vsi_seid);
4821 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4823 if (!status && stats) {
4824 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4825 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4826 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4827 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4834 * i40e_aq_add_cloud_filters
4835 * @hw: pointer to the hardware structure
4836 * @seid: VSI seid to add cloud filters from
4837 * @filters: Buffer which contains the filters to be added
4838 * @filter_count: number of filters contained in the buffer
4840 * Set the cloud filters for a given VSI. The contents of the
4841 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4842 * in by the caller of the function.
4845 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4847 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4850 struct i40e_aq_desc desc;
4851 struct i40e_aqc_add_remove_cloud_filters *cmd =
4852 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4854 enum i40e_status_code status;
4856 i40e_fill_default_direct_cmd_desc(&desc,
4857 i40e_aqc_opc_add_cloud_filters);
4859 buff_len = filter_count * sizeof(*filters);
4860 desc.datalen = CPU_TO_LE16(buff_len);
4861 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4862 cmd->num_filters = filter_count;
4863 cmd->seid = CPU_TO_LE16(seid);
4865 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4871 * i40e_aq_remove_cloud_filters
4872 * @hw: pointer to the hardware structure
4873 * @seid: VSI seid to remove cloud filters from
4874 * @filters: Buffer which contains the filters to be removed
4875 * @filter_count: number of filters contained in the buffer
4877 * Remove the cloud filters for a given VSI. The contents of the
4878 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4879 * in by the caller of the function.
4882 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4884 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4887 struct i40e_aq_desc desc;
4888 struct i40e_aqc_add_remove_cloud_filters *cmd =
4889 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4890 enum i40e_status_code status;
4893 i40e_fill_default_direct_cmd_desc(&desc,
4894 i40e_aqc_opc_remove_cloud_filters);
4896 buff_len = filter_count * sizeof(*filters);
4897 desc.datalen = CPU_TO_LE16(buff_len);
4898 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4899 cmd->num_filters = filter_count;
4900 cmd->seid = CPU_TO_LE16(seid);
4902 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4908 * i40e_aq_alternate_write
4909 * @hw: pointer to the hardware structure
4910 * @reg_addr0: address of first dword to be read
4911 * @reg_val0: value to be written under 'reg_addr0'
4912 * @reg_addr1: address of second dword to be read
4913 * @reg_val1: value to be written under 'reg_addr1'
4915 * Write one or two dwords to alternate structure. Fields are indicated
4916 * by 'reg_addr0' and 'reg_addr1' register numbers.
4919 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4920 u32 reg_addr0, u32 reg_val0,
4921 u32 reg_addr1, u32 reg_val1)
4923 struct i40e_aq_desc desc;
4924 struct i40e_aqc_alternate_write *cmd_resp =
4925 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4926 enum i40e_status_code status;
4928 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4929 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4930 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4931 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4932 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4934 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4940 * i40e_aq_alternate_write_indirect
4941 * @hw: pointer to the hardware structure
4942 * @addr: address of a first register to be modified
4943 * @dw_count: number of alternate structure fields to write
4944 * @buffer: pointer to the command buffer
4946 * Write 'dw_count' dwords from 'buffer' to alternate structure
4947 * starting at 'addr'.
4950 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4951 u32 addr, u32 dw_count, void *buffer)
4953 struct i40e_aq_desc desc;
4954 struct i40e_aqc_alternate_ind_write *cmd_resp =
4955 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4956 enum i40e_status_code status;
4959 return I40E_ERR_PARAM;
4961 /* Indirect command */
4962 i40e_fill_default_direct_cmd_desc(&desc,
4963 i40e_aqc_opc_alternate_write_indirect);
4965 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4966 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4967 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4970 cmd_resp->address = CPU_TO_LE32(addr);
4971 cmd_resp->length = CPU_TO_LE32(dw_count);
4972 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4973 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4975 status = i40e_asq_send_command(hw, &desc, buffer,
4976 I40E_LO_DWORD(4*dw_count), NULL);
4982 * i40e_aq_alternate_read
4983 * @hw: pointer to the hardware structure
4984 * @reg_addr0: address of first dword to be read
4985 * @reg_val0: pointer for data read from 'reg_addr0'
4986 * @reg_addr1: address of second dword to be read
4987 * @reg_val1: pointer for data read from 'reg_addr1'
4989 * Read one or two dwords from alternate structure. Fields are indicated
4990 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4991 * is not passed then only register at 'reg_addr0' is read.
4994 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4995 u32 reg_addr0, u32 *reg_val0,
4996 u32 reg_addr1, u32 *reg_val1)
4998 struct i40e_aq_desc desc;
4999 struct i40e_aqc_alternate_write *cmd_resp =
5000 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5001 enum i40e_status_code status;
5003 if (reg_val0 == NULL)
5004 return I40E_ERR_PARAM;
5006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5007 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5008 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5010 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5012 if (status == I40E_SUCCESS) {
5013 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5015 if (reg_val1 != NULL)
5016 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5023 * i40e_aq_alternate_read_indirect
5024 * @hw: pointer to the hardware structure
5025 * @addr: address of the alternate structure field
5026 * @dw_count: number of alternate structure fields to read
5027 * @buffer: pointer to the command buffer
5029 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5030 * place them in 'buffer'. The buffer should be allocated by caller.
5033 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5034 u32 addr, u32 dw_count, void *buffer)
5036 struct i40e_aq_desc desc;
5037 struct i40e_aqc_alternate_ind_write *cmd_resp =
5038 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5039 enum i40e_status_code status;
5042 return I40E_ERR_PARAM;
5044 /* Indirect command */
5045 i40e_fill_default_direct_cmd_desc(&desc,
5046 i40e_aqc_opc_alternate_read_indirect);
5048 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5049 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5050 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5051 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5053 cmd_resp->address = CPU_TO_LE32(addr);
5054 cmd_resp->length = CPU_TO_LE32(dw_count);
5055 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
5056 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5058 status = i40e_asq_send_command(hw, &desc, buffer,
5059 I40E_LO_DWORD(4*dw_count), NULL);
5065 * i40e_aq_alternate_clear
5066 * @hw: pointer to the HW structure.
5068 * Clear the alternate structures of the port from which the function
5072 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5074 struct i40e_aq_desc desc;
5075 enum i40e_status_code status;
5077 i40e_fill_default_direct_cmd_desc(&desc,
5078 i40e_aqc_opc_alternate_clear_port);
5080 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5086 * i40e_aq_alternate_write_done
5087 * @hw: pointer to the HW structure.
5088 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5089 * @reset_needed: indicates the SW should trigger GLOBAL reset
5091 * Indicates to the FW that alternate structures have been changed.
5094 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5095 u8 bios_mode, bool *reset_needed)
5097 struct i40e_aq_desc desc;
5098 struct i40e_aqc_alternate_write_done *cmd =
5099 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5100 enum i40e_status_code status;
5102 if (reset_needed == NULL)
5103 return I40E_ERR_PARAM;
5105 i40e_fill_default_direct_cmd_desc(&desc,
5106 i40e_aqc_opc_alternate_write_done);
5108 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5110 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5111 if (!status && reset_needed)
5112 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5113 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5119 * i40e_aq_set_oem_mode
5120 * @hw: pointer to the HW structure.
5121 * @oem_mode: the OEM mode to be used
5123 * Sets the device to a specific operating mode. Currently the only supported
5124 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5127 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5130 struct i40e_aq_desc desc;
5131 struct i40e_aqc_alternate_write_done *cmd =
5132 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5133 enum i40e_status_code status;
5135 i40e_fill_default_direct_cmd_desc(&desc,
5136 i40e_aqc_opc_alternate_set_mode);
5138 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5140 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5146 * i40e_aq_resume_port_tx
5147 * @hw: pointer to the hardware structure
5148 * @cmd_details: pointer to command details structure or NULL
5150 * Resume port's Tx traffic
5152 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5153 struct i40e_asq_cmd_details *cmd_details)
5155 struct i40e_aq_desc desc;
5156 enum i40e_status_code status;
5158 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5166 * i40e_set_pci_config_data - store PCI bus info
5167 * @hw: pointer to hardware structure
5168 * @link_status: the link status word from PCI config space
5170 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5172 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5174 hw->bus.type = i40e_bus_type_pci_express;
5176 switch (link_status & I40E_PCI_LINK_WIDTH) {
5177 case I40E_PCI_LINK_WIDTH_1:
5178 hw->bus.width = i40e_bus_width_pcie_x1;
5180 case I40E_PCI_LINK_WIDTH_2:
5181 hw->bus.width = i40e_bus_width_pcie_x2;
5183 case I40E_PCI_LINK_WIDTH_4:
5184 hw->bus.width = i40e_bus_width_pcie_x4;
5186 case I40E_PCI_LINK_WIDTH_8:
5187 hw->bus.width = i40e_bus_width_pcie_x8;
5190 hw->bus.width = i40e_bus_width_unknown;
5194 switch (link_status & I40E_PCI_LINK_SPEED) {
5195 case I40E_PCI_LINK_SPEED_2500:
5196 hw->bus.speed = i40e_bus_speed_2500;
5198 case I40E_PCI_LINK_SPEED_5000:
5199 hw->bus.speed = i40e_bus_speed_5000;
5201 case I40E_PCI_LINK_SPEED_8000:
5202 hw->bus.speed = i40e_bus_speed_8000;
5205 hw->bus.speed = i40e_bus_speed_unknown;
5211 * i40e_read_bw_from_alt_ram
5212 * @hw: pointer to the hardware structure
5213 * @max_bw: pointer for max_bw read
5214 * @min_bw: pointer for min_bw read
5215 * @min_valid: pointer for bool that is true if min_bw is a valid value
5216 * @max_valid: pointer for bool that is true if max_bw is a valid value
5218 * Read bw from the alternate ram for the given pf
5220 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5221 u32 *max_bw, u32 *min_bw,
5222 bool *min_valid, bool *max_valid)
5224 enum i40e_status_code status;
5225 u32 max_bw_addr, min_bw_addr;
5227 /* Calculate the address of the min/max bw registers */
5228 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5229 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5230 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5231 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5232 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5233 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5235 /* Read the bandwidths from alt ram */
5236 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5237 min_bw_addr, min_bw);
5239 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5244 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5253 * i40e_aq_configure_partition_bw
5254 * @hw: pointer to the hardware structure
5255 * @bw_data: Buffer holding valid pfs and bw limits
5256 * @cmd_details: pointer to command details
5258 * Configure partitions guaranteed/max bw
5260 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5261 struct i40e_aqc_configure_partition_bw_data *bw_data,
5262 struct i40e_asq_cmd_details *cmd_details)
5264 enum i40e_status_code status;
5265 struct i40e_aq_desc desc;
5266 u16 bwd_size = sizeof(*bw_data);
5268 i40e_fill_default_direct_cmd_desc(&desc,
5269 i40e_aqc_opc_configure_partition_bw);
5271 /* Indirect command */
5272 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5273 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5275 if (bwd_size > I40E_AQ_LARGE_BUF)
5276 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5278 desc.datalen = CPU_TO_LE16(bwd_size);
5280 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5284 #endif /* PF_DRIVER */
5288 * i40e_aq_send_msg_to_pf
5289 * @hw: pointer to the hardware structure
5290 * @v_opcode: opcodes for VF-PF communication
5291 * @v_retval: return error code
5292 * @msg: pointer to the msg buffer
5293 * @msglen: msg length
5294 * @cmd_details: pointer to command details
5296 * Send message to PF driver using admin queue. By default, this message
5297 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5298 * completion before returning.
5300 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5301 enum i40e_virtchnl_ops v_opcode,
5302 enum i40e_status_code v_retval,
5303 u8 *msg, u16 msglen,
5304 struct i40e_asq_cmd_details *cmd_details)
5306 struct i40e_aq_desc desc;
5307 struct i40e_asq_cmd_details details;
5308 enum i40e_status_code status;
5310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5311 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5312 desc.cookie_high = CPU_TO_LE32(v_opcode);
5313 desc.cookie_low = CPU_TO_LE32(v_retval);
5315 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5316 | I40E_AQ_FLAG_RD));
5317 if (msglen > I40E_AQ_LARGE_BUF)
5318 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5319 desc.datalen = CPU_TO_LE16(msglen);
5322 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5323 details.async = true;
5324 cmd_details = &details;
5326 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5327 msglen, cmd_details);
5332 * i40e_vf_parse_hw_config
5333 * @hw: pointer to the hardware structure
5334 * @msg: pointer to the virtual channel VF resource structure
5336 * Given a VF resource message from the PF, populate the hw struct
5337 * with appropriate information.
5339 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5340 struct i40e_virtchnl_vf_resource *msg)
5342 struct i40e_virtchnl_vsi_resource *vsi_res;
5345 vsi_res = &msg->vsi_res[0];
5347 hw->dev_caps.num_vsis = msg->num_vsis;
5348 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5349 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5350 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5351 hw->dev_caps.dcb = msg->vf_offload_flags &
5352 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5353 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5354 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5355 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5356 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5357 for (i = 0; i < msg->num_vsis; i++) {
5358 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5359 i40e_memcpy(hw->mac.perm_addr,
5360 vsi_res->default_mac_addr,
5361 I40E_ETH_LENGTH_OF_ADDRESS,
5362 I40E_NONDMA_TO_NONDMA);
5363 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5364 I40E_ETH_LENGTH_OF_ADDRESS,
5365 I40E_NONDMA_TO_NONDMA);
5373 * @hw: pointer to the hardware structure
5375 * Send a VF_RESET message to the PF. Does not wait for response from PF
5376 * as none will be forthcoming. Immediately after calling this function,
5377 * the admin queue should be shut down and (optionally) reinitialized.
5379 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5381 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5382 I40E_SUCCESS, NULL, 0, NULL);
5384 #endif /* VF_DRIVER */