1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 hw->mac.type = I40E_MAC_X722;
88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
89 case I40E_DEV_ID_X722_VF:
90 #ifdef X722_A0_SUPPORT
91 case I40E_DEV_ID_X722_A0_VF:
93 hw->mac.type = I40E_MAC_X722_VF;
95 #endif /* INTEGRATED_VF || VF_DRIVER */
96 #endif /* X722_SUPPORT */
97 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
99 case I40E_DEV_ID_VF_HV:
100 hw->mac.type = I40E_MAC_VF;
104 hw->mac.type = I40E_MAC_GENERIC;
108 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
111 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
112 hw->mac.type, status);
116 #ifndef I40E_NDIS_SUPPORT
118 * i40e_aq_str - convert AQ err code to a string
119 * @hw: pointer to the HW structure
120 * @aq_err: the AQ error code to convert
122 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
127 case I40E_AQ_RC_EPERM:
128 return "I40E_AQ_RC_EPERM";
129 case I40E_AQ_RC_ENOENT:
130 return "I40E_AQ_RC_ENOENT";
131 case I40E_AQ_RC_ESRCH:
132 return "I40E_AQ_RC_ESRCH";
133 case I40E_AQ_RC_EINTR:
134 return "I40E_AQ_RC_EINTR";
136 return "I40E_AQ_RC_EIO";
137 case I40E_AQ_RC_ENXIO:
138 return "I40E_AQ_RC_ENXIO";
139 case I40E_AQ_RC_E2BIG:
140 return "I40E_AQ_RC_E2BIG";
141 case I40E_AQ_RC_EAGAIN:
142 return "I40E_AQ_RC_EAGAIN";
143 case I40E_AQ_RC_ENOMEM:
144 return "I40E_AQ_RC_ENOMEM";
145 case I40E_AQ_RC_EACCES:
146 return "I40E_AQ_RC_EACCES";
147 case I40E_AQ_RC_EFAULT:
148 return "I40E_AQ_RC_EFAULT";
149 case I40E_AQ_RC_EBUSY:
150 return "I40E_AQ_RC_EBUSY";
151 case I40E_AQ_RC_EEXIST:
152 return "I40E_AQ_RC_EEXIST";
153 case I40E_AQ_RC_EINVAL:
154 return "I40E_AQ_RC_EINVAL";
155 case I40E_AQ_RC_ENOTTY:
156 return "I40E_AQ_RC_ENOTTY";
157 case I40E_AQ_RC_ENOSPC:
158 return "I40E_AQ_RC_ENOSPC";
159 case I40E_AQ_RC_ENOSYS:
160 return "I40E_AQ_RC_ENOSYS";
161 case I40E_AQ_RC_ERANGE:
162 return "I40E_AQ_RC_ERANGE";
163 case I40E_AQ_RC_EFLUSHED:
164 return "I40E_AQ_RC_EFLUSHED";
165 case I40E_AQ_RC_BAD_ADDR:
166 return "I40E_AQ_RC_BAD_ADDR";
167 case I40E_AQ_RC_EMODE:
168 return "I40E_AQ_RC_EMODE";
169 case I40E_AQ_RC_EFBIG:
170 return "I40E_AQ_RC_EFBIG";
173 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
178 * i40e_stat_str - convert status err code to a string
179 * @hw: pointer to the HW structure
180 * @stat_err: the status error code to convert
182 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
188 return "I40E_ERR_NVM";
189 case I40E_ERR_NVM_CHECKSUM:
190 return "I40E_ERR_NVM_CHECKSUM";
192 return "I40E_ERR_PHY";
193 case I40E_ERR_CONFIG:
194 return "I40E_ERR_CONFIG";
196 return "I40E_ERR_PARAM";
197 case I40E_ERR_MAC_TYPE:
198 return "I40E_ERR_MAC_TYPE";
199 case I40E_ERR_UNKNOWN_PHY:
200 return "I40E_ERR_UNKNOWN_PHY";
201 case I40E_ERR_LINK_SETUP:
202 return "I40E_ERR_LINK_SETUP";
203 case I40E_ERR_ADAPTER_STOPPED:
204 return "I40E_ERR_ADAPTER_STOPPED";
205 case I40E_ERR_INVALID_MAC_ADDR:
206 return "I40E_ERR_INVALID_MAC_ADDR";
207 case I40E_ERR_DEVICE_NOT_SUPPORTED:
208 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
209 case I40E_ERR_MASTER_REQUESTS_PENDING:
210 return "I40E_ERR_MASTER_REQUESTS_PENDING";
211 case I40E_ERR_INVALID_LINK_SETTINGS:
212 return "I40E_ERR_INVALID_LINK_SETTINGS";
213 case I40E_ERR_AUTONEG_NOT_COMPLETE:
214 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
215 case I40E_ERR_RESET_FAILED:
216 return "I40E_ERR_RESET_FAILED";
217 case I40E_ERR_SWFW_SYNC:
218 return "I40E_ERR_SWFW_SYNC";
219 case I40E_ERR_NO_AVAILABLE_VSI:
220 return "I40E_ERR_NO_AVAILABLE_VSI";
221 case I40E_ERR_NO_MEMORY:
222 return "I40E_ERR_NO_MEMORY";
223 case I40E_ERR_BAD_PTR:
224 return "I40E_ERR_BAD_PTR";
225 case I40E_ERR_RING_FULL:
226 return "I40E_ERR_RING_FULL";
227 case I40E_ERR_INVALID_PD_ID:
228 return "I40E_ERR_INVALID_PD_ID";
229 case I40E_ERR_INVALID_QP_ID:
230 return "I40E_ERR_INVALID_QP_ID";
231 case I40E_ERR_INVALID_CQ_ID:
232 return "I40E_ERR_INVALID_CQ_ID";
233 case I40E_ERR_INVALID_CEQ_ID:
234 return "I40E_ERR_INVALID_CEQ_ID";
235 case I40E_ERR_INVALID_AEQ_ID:
236 return "I40E_ERR_INVALID_AEQ_ID";
237 case I40E_ERR_INVALID_SIZE:
238 return "I40E_ERR_INVALID_SIZE";
239 case I40E_ERR_INVALID_ARP_INDEX:
240 return "I40E_ERR_INVALID_ARP_INDEX";
241 case I40E_ERR_INVALID_FPM_FUNC_ID:
242 return "I40E_ERR_INVALID_FPM_FUNC_ID";
243 case I40E_ERR_QP_INVALID_MSG_SIZE:
244 return "I40E_ERR_QP_INVALID_MSG_SIZE";
245 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
246 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
247 case I40E_ERR_INVALID_FRAG_COUNT:
248 return "I40E_ERR_INVALID_FRAG_COUNT";
249 case I40E_ERR_QUEUE_EMPTY:
250 return "I40E_ERR_QUEUE_EMPTY";
251 case I40E_ERR_INVALID_ALIGNMENT:
252 return "I40E_ERR_INVALID_ALIGNMENT";
253 case I40E_ERR_FLUSHED_QUEUE:
254 return "I40E_ERR_FLUSHED_QUEUE";
255 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
256 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
257 case I40E_ERR_INVALID_IMM_DATA_SIZE:
258 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
259 case I40E_ERR_TIMEOUT:
260 return "I40E_ERR_TIMEOUT";
261 case I40E_ERR_OPCODE_MISMATCH:
262 return "I40E_ERR_OPCODE_MISMATCH";
263 case I40E_ERR_CQP_COMPL_ERROR:
264 return "I40E_ERR_CQP_COMPL_ERROR";
265 case I40E_ERR_INVALID_VF_ID:
266 return "I40E_ERR_INVALID_VF_ID";
267 case I40E_ERR_INVALID_HMCFN_ID:
268 return "I40E_ERR_INVALID_HMCFN_ID";
269 case I40E_ERR_BACKING_PAGE_ERROR:
270 return "I40E_ERR_BACKING_PAGE_ERROR";
271 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
272 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
273 case I40E_ERR_INVALID_PBLE_INDEX:
274 return "I40E_ERR_INVALID_PBLE_INDEX";
275 case I40E_ERR_INVALID_SD_INDEX:
276 return "I40E_ERR_INVALID_SD_INDEX";
277 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
278 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
279 case I40E_ERR_INVALID_SD_TYPE:
280 return "I40E_ERR_INVALID_SD_TYPE";
281 case I40E_ERR_MEMCPY_FAILED:
282 return "I40E_ERR_MEMCPY_FAILED";
283 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
284 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
285 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
286 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
287 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
288 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
289 case I40E_ERR_SRQ_ENABLED:
290 return "I40E_ERR_SRQ_ENABLED";
291 case I40E_ERR_ADMIN_QUEUE_ERROR:
292 return "I40E_ERR_ADMIN_QUEUE_ERROR";
293 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
294 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
295 case I40E_ERR_BUF_TOO_SHORT:
296 return "I40E_ERR_BUF_TOO_SHORT";
297 case I40E_ERR_ADMIN_QUEUE_FULL:
298 return "I40E_ERR_ADMIN_QUEUE_FULL";
299 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
300 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
301 case I40E_ERR_BAD_IWARP_CQE:
302 return "I40E_ERR_BAD_IWARP_CQE";
303 case I40E_ERR_NVM_BLANK_MODE:
304 return "I40E_ERR_NVM_BLANK_MODE";
305 case I40E_ERR_NOT_IMPLEMENTED:
306 return "I40E_ERR_NOT_IMPLEMENTED";
307 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
308 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
309 case I40E_ERR_DIAG_TEST_FAILED:
310 return "I40E_ERR_DIAG_TEST_FAILED";
311 case I40E_ERR_NOT_READY:
312 return "I40E_ERR_NOT_READY";
313 case I40E_NOT_SUPPORTED:
314 return "I40E_NOT_SUPPORTED";
315 case I40E_ERR_FIRMWARE_API_VERSION:
316 return "I40E_ERR_FIRMWARE_API_VERSION";
319 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
323 #endif /* I40E_NDIS_SUPPORT */
326 * @hw: debug mask related to admin queue
328 * @desc: pointer to admin queue descriptor
329 * @buffer: pointer to command buffer
330 * @buf_len: max length of buffer
332 * Dumps debug log about adminq command with descriptor contents.
334 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
335 void *buffer, u16 buf_len)
337 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
338 u16 len = LE16_TO_CPU(aq_desc->datalen);
339 u8 *buf = (u8 *)buffer;
342 if ((!(mask & hw->debug_mask)) || (desc == NULL))
346 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
347 LE16_TO_CPU(aq_desc->opcode),
348 LE16_TO_CPU(aq_desc->flags),
349 LE16_TO_CPU(aq_desc->datalen),
350 LE16_TO_CPU(aq_desc->retval));
351 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
352 LE32_TO_CPU(aq_desc->cookie_high),
353 LE32_TO_CPU(aq_desc->cookie_low));
354 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
355 LE32_TO_CPU(aq_desc->params.internal.param0),
356 LE32_TO_CPU(aq_desc->params.internal.param1));
357 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
358 LE32_TO_CPU(aq_desc->params.external.addr_high),
359 LE32_TO_CPU(aq_desc->params.external.addr_low));
361 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
362 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
365 /* write the full 16-byte chunks */
366 for (i = 0; i < (len - 16); i += 16)
368 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
369 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
370 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
371 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
372 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
373 /* the most we could have left is 16 bytes, pad with zeros */
379 memset(d_buf, 0, sizeof(d_buf));
380 for (j = 0; i < len; j++, i++)
383 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
384 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
385 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
386 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
387 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
393 * i40e_check_asq_alive
394 * @hw: pointer to the hw struct
396 * Returns true if Queue is enabled else false.
398 bool i40e_check_asq_alive(struct i40e_hw *hw)
404 return !!(rd32(hw, hw->aq.asq.len) &
405 I40E_PF_ATQLEN_ATQENABLE_MASK);
407 return !!(rd32(hw, hw->aq.asq.len) &
408 I40E_PF_ATQLEN_ATQENABLE_MASK);
409 #endif /* INTEGRATED_VF */
410 #endif /* PF_DRIVER */
414 return !!(rd32(hw, hw->aq.asq.len) &
415 I40E_VF_ATQLEN1_ATQENABLE_MASK);
417 return !!(rd32(hw, hw->aq.asq.len) &
418 I40E_VF_ATQLEN1_ATQENABLE_MASK);
419 #endif /* INTEGRATED_VF */
420 #endif /* VF_DRIVER */
425 * i40e_aq_queue_shutdown
426 * @hw: pointer to the hw struct
427 * @unloading: is the driver unloading itself
429 * Tell the Firmware that we're shutting down the AdminQ and whether
430 * or not the driver is unloading as well.
432 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
435 struct i40e_aq_desc desc;
436 struct i40e_aqc_queue_shutdown *cmd =
437 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
438 enum i40e_status_code status;
440 i40e_fill_default_direct_cmd_desc(&desc,
441 i40e_aqc_opc_queue_shutdown);
444 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
445 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
452 * i40e_aq_get_set_rss_lut
453 * @hw: pointer to the hardware structure
454 * @vsi_id: vsi fw index
455 * @pf_lut: for PF table set true, for VSI table set false
456 * @lut: pointer to the lut buffer provided by the caller
457 * @lut_size: size of the lut buffer
458 * @set: set true to set the table, false to get the table
460 * Internal function to get or set RSS look up table
462 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
463 u16 vsi_id, bool pf_lut,
464 u8 *lut, u16 lut_size,
467 enum i40e_status_code status;
468 struct i40e_aq_desc desc;
469 struct i40e_aqc_get_set_rss_lut *cmd_resp =
470 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_set_rss_lut);
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_get_rss_lut);
479 /* Indirect command */
480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
484 CPU_TO_LE16((u16)((vsi_id <<
485 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
486 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
487 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
490 cmd_resp->flags |= CPU_TO_LE16((u16)
491 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
492 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
495 cmd_resp->flags |= CPU_TO_LE16((u16)
496 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
497 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
500 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
506 * i40e_aq_get_rss_lut
507 * @hw: pointer to the hardware structure
508 * @vsi_id: vsi fw index
509 * @pf_lut: for PF table set true, for VSI table set false
510 * @lut: pointer to the lut buffer provided by the caller
511 * @lut_size: size of the lut buffer
513 * get the RSS lookup table, PF or VSI type
515 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
516 bool pf_lut, u8 *lut, u16 lut_size)
518 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
523 * i40e_aq_set_rss_lut
524 * @hw: pointer to the hardware structure
525 * @vsi_id: vsi fw index
526 * @pf_lut: for PF table set true, for VSI table set false
527 * @lut: pointer to the lut buffer provided by the caller
528 * @lut_size: size of the lut buffer
530 * set the RSS lookup table, PF or VSI type
532 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
533 bool pf_lut, u8 *lut, u16 lut_size)
535 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
539 * i40e_aq_get_set_rss_key
540 * @hw: pointer to the hw struct
541 * @vsi_id: vsi fw index
542 * @key: pointer to key info struct
543 * @set: set true to set the key, false to get the key
545 * get the RSS key per VSI
547 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
549 struct i40e_aqc_get_set_rss_key_data *key,
552 enum i40e_status_code status;
553 struct i40e_aq_desc desc;
554 struct i40e_aqc_get_set_rss_key *cmd_resp =
555 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
556 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
559 i40e_fill_default_direct_cmd_desc(&desc,
560 i40e_aqc_opc_set_rss_key);
562 i40e_fill_default_direct_cmd_desc(&desc,
563 i40e_aqc_opc_get_rss_key);
565 /* Indirect command */
566 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
570 CPU_TO_LE16((u16)((vsi_id <<
571 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
572 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
573 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
575 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
581 * i40e_aq_get_rss_key
582 * @hw: pointer to the hw struct
583 * @vsi_id: vsi fw index
584 * @key: pointer to key info struct
587 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
589 struct i40e_aqc_get_set_rss_key_data *key)
591 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
595 * i40e_aq_set_rss_key
596 * @hw: pointer to the hw struct
597 * @vsi_id: vsi fw index
598 * @key: pointer to key info struct
600 * set the RSS key per VSI
602 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
604 struct i40e_aqc_get_set_rss_key_data *key)
606 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
608 #endif /* X722_SUPPORT */
610 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
611 * hardware to a bit-field that can be used by SW to more easily determine the
614 * Macros are used to shorten the table lines and make this table human
617 * We store the PTYPE in the top byte of the bit field - this is just so that
618 * we can check that the table doesn't have a row missing, as the index into
619 * the table should be the PTYPE.
623 * IF NOT i40e_ptype_lookup[ptype].known
626 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
627 * Use the rest of the fields to look at the tunnels, inner protocols, etc
629 * Use the enum i40e_rx_l2_ptype to decode the packet type
633 /* macro to make the table lines short */
634 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
637 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
638 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
639 I40E_RX_PTYPE_##OUTER_FRAG, \
640 I40E_RX_PTYPE_TUNNEL_##T, \
641 I40E_RX_PTYPE_TUNNEL_END_##TE, \
642 I40E_RX_PTYPE_##TEF, \
643 I40E_RX_PTYPE_INNER_PROT_##I, \
644 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
646 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
647 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
649 /* shorter macros makes the table fit but are terse */
650 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
651 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
652 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
654 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
655 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
656 /* L2 Packet types */
657 I40E_PTT_UNUSED_ENTRY(0),
658 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
659 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
660 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT_UNUSED_ENTRY(4),
662 I40E_PTT_UNUSED_ENTRY(5),
663 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
664 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT_UNUSED_ENTRY(8),
666 I40E_PTT_UNUSED_ENTRY(9),
667 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
668 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
669 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
680 /* Non Tunneled IPv4 */
681 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
682 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(25),
685 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
686 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
687 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
690 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
691 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
692 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
693 I40E_PTT_UNUSED_ENTRY(32),
694 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
695 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
696 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
699 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
700 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
701 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
702 I40E_PTT_UNUSED_ENTRY(39),
703 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
704 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
705 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
707 /* IPv4 --> GRE/NAT */
708 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
710 /* IPv4 --> GRE/NAT --> IPv4 */
711 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
712 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
713 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
714 I40E_PTT_UNUSED_ENTRY(47),
715 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
716 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
717 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
719 /* IPv4 --> GRE/NAT --> IPv6 */
720 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
721 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
722 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
723 I40E_PTT_UNUSED_ENTRY(54),
724 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
725 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
726 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
728 /* IPv4 --> GRE/NAT --> MAC */
729 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
731 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
732 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
733 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
734 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(62),
736 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
737 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
738 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
740 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
741 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
742 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
743 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
744 I40E_PTT_UNUSED_ENTRY(69),
745 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
746 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
747 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
749 /* IPv4 --> GRE/NAT --> MAC/VLAN */
750 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
752 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
753 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
754 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
755 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(77),
757 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
758 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
759 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
761 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
762 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
763 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
764 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(84),
766 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
767 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
768 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
770 /* Non Tunneled IPv6 */
771 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
772 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(91),
775 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
776 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
777 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
780 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
781 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
782 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
783 I40E_PTT_UNUSED_ENTRY(98),
784 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
785 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
786 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
789 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
790 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
791 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
792 I40E_PTT_UNUSED_ENTRY(105),
793 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
794 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
795 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
797 /* IPv6 --> GRE/NAT */
798 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
800 /* IPv6 --> GRE/NAT -> IPv4 */
801 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
802 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
803 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
804 I40E_PTT_UNUSED_ENTRY(113),
805 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
806 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
807 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
809 /* IPv6 --> GRE/NAT -> IPv6 */
810 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
811 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
812 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
813 I40E_PTT_UNUSED_ENTRY(120),
814 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
815 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
816 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
818 /* IPv6 --> GRE/NAT -> MAC */
819 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
821 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
822 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
823 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
824 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
825 I40E_PTT_UNUSED_ENTRY(128),
826 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
827 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
828 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
830 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
831 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
832 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
833 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
834 I40E_PTT_UNUSED_ENTRY(135),
835 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
836 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
837 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
839 /* IPv6 --> GRE/NAT -> MAC/VLAN */
840 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
842 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
843 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
844 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
845 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
846 I40E_PTT_UNUSED_ENTRY(143),
847 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
848 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
849 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
851 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
852 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
853 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
854 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
855 I40E_PTT_UNUSED_ENTRY(150),
856 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
857 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
858 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
861 I40E_PTT_UNUSED_ENTRY(154),
862 I40E_PTT_UNUSED_ENTRY(155),
863 I40E_PTT_UNUSED_ENTRY(156),
864 I40E_PTT_UNUSED_ENTRY(157),
865 I40E_PTT_UNUSED_ENTRY(158),
866 I40E_PTT_UNUSED_ENTRY(159),
868 I40E_PTT_UNUSED_ENTRY(160),
869 I40E_PTT_UNUSED_ENTRY(161),
870 I40E_PTT_UNUSED_ENTRY(162),
871 I40E_PTT_UNUSED_ENTRY(163),
872 I40E_PTT_UNUSED_ENTRY(164),
873 I40E_PTT_UNUSED_ENTRY(165),
874 I40E_PTT_UNUSED_ENTRY(166),
875 I40E_PTT_UNUSED_ENTRY(167),
876 I40E_PTT_UNUSED_ENTRY(168),
877 I40E_PTT_UNUSED_ENTRY(169),
879 I40E_PTT_UNUSED_ENTRY(170),
880 I40E_PTT_UNUSED_ENTRY(171),
881 I40E_PTT_UNUSED_ENTRY(172),
882 I40E_PTT_UNUSED_ENTRY(173),
883 I40E_PTT_UNUSED_ENTRY(174),
884 I40E_PTT_UNUSED_ENTRY(175),
885 I40E_PTT_UNUSED_ENTRY(176),
886 I40E_PTT_UNUSED_ENTRY(177),
887 I40E_PTT_UNUSED_ENTRY(178),
888 I40E_PTT_UNUSED_ENTRY(179),
890 I40E_PTT_UNUSED_ENTRY(180),
891 I40E_PTT_UNUSED_ENTRY(181),
892 I40E_PTT_UNUSED_ENTRY(182),
893 I40E_PTT_UNUSED_ENTRY(183),
894 I40E_PTT_UNUSED_ENTRY(184),
895 I40E_PTT_UNUSED_ENTRY(185),
896 I40E_PTT_UNUSED_ENTRY(186),
897 I40E_PTT_UNUSED_ENTRY(187),
898 I40E_PTT_UNUSED_ENTRY(188),
899 I40E_PTT_UNUSED_ENTRY(189),
901 I40E_PTT_UNUSED_ENTRY(190),
902 I40E_PTT_UNUSED_ENTRY(191),
903 I40E_PTT_UNUSED_ENTRY(192),
904 I40E_PTT_UNUSED_ENTRY(193),
905 I40E_PTT_UNUSED_ENTRY(194),
906 I40E_PTT_UNUSED_ENTRY(195),
907 I40E_PTT_UNUSED_ENTRY(196),
908 I40E_PTT_UNUSED_ENTRY(197),
909 I40E_PTT_UNUSED_ENTRY(198),
910 I40E_PTT_UNUSED_ENTRY(199),
912 I40E_PTT_UNUSED_ENTRY(200),
913 I40E_PTT_UNUSED_ENTRY(201),
914 I40E_PTT_UNUSED_ENTRY(202),
915 I40E_PTT_UNUSED_ENTRY(203),
916 I40E_PTT_UNUSED_ENTRY(204),
917 I40E_PTT_UNUSED_ENTRY(205),
918 I40E_PTT_UNUSED_ENTRY(206),
919 I40E_PTT_UNUSED_ENTRY(207),
920 I40E_PTT_UNUSED_ENTRY(208),
921 I40E_PTT_UNUSED_ENTRY(209),
923 I40E_PTT_UNUSED_ENTRY(210),
924 I40E_PTT_UNUSED_ENTRY(211),
925 I40E_PTT_UNUSED_ENTRY(212),
926 I40E_PTT_UNUSED_ENTRY(213),
927 I40E_PTT_UNUSED_ENTRY(214),
928 I40E_PTT_UNUSED_ENTRY(215),
929 I40E_PTT_UNUSED_ENTRY(216),
930 I40E_PTT_UNUSED_ENTRY(217),
931 I40E_PTT_UNUSED_ENTRY(218),
932 I40E_PTT_UNUSED_ENTRY(219),
934 I40E_PTT_UNUSED_ENTRY(220),
935 I40E_PTT_UNUSED_ENTRY(221),
936 I40E_PTT_UNUSED_ENTRY(222),
937 I40E_PTT_UNUSED_ENTRY(223),
938 I40E_PTT_UNUSED_ENTRY(224),
939 I40E_PTT_UNUSED_ENTRY(225),
940 I40E_PTT_UNUSED_ENTRY(226),
941 I40E_PTT_UNUSED_ENTRY(227),
942 I40E_PTT_UNUSED_ENTRY(228),
943 I40E_PTT_UNUSED_ENTRY(229),
945 I40E_PTT_UNUSED_ENTRY(230),
946 I40E_PTT_UNUSED_ENTRY(231),
947 I40E_PTT_UNUSED_ENTRY(232),
948 I40E_PTT_UNUSED_ENTRY(233),
949 I40E_PTT_UNUSED_ENTRY(234),
950 I40E_PTT_UNUSED_ENTRY(235),
951 I40E_PTT_UNUSED_ENTRY(236),
952 I40E_PTT_UNUSED_ENTRY(237),
953 I40E_PTT_UNUSED_ENTRY(238),
954 I40E_PTT_UNUSED_ENTRY(239),
956 I40E_PTT_UNUSED_ENTRY(240),
957 I40E_PTT_UNUSED_ENTRY(241),
958 I40E_PTT_UNUSED_ENTRY(242),
959 I40E_PTT_UNUSED_ENTRY(243),
960 I40E_PTT_UNUSED_ENTRY(244),
961 I40E_PTT_UNUSED_ENTRY(245),
962 I40E_PTT_UNUSED_ENTRY(246),
963 I40E_PTT_UNUSED_ENTRY(247),
964 I40E_PTT_UNUSED_ENTRY(248),
965 I40E_PTT_UNUSED_ENTRY(249),
967 I40E_PTT_UNUSED_ENTRY(250),
968 I40E_PTT_UNUSED_ENTRY(251),
969 I40E_PTT_UNUSED_ENTRY(252),
970 I40E_PTT_UNUSED_ENTRY(253),
971 I40E_PTT_UNUSED_ENTRY(254),
972 I40E_PTT_UNUSED_ENTRY(255)
977 * i40e_validate_mac_addr - Validate unicast MAC address
978 * @mac_addr: pointer to MAC address
980 * Tests a MAC address to ensure it is a valid Individual Address
982 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
984 enum i40e_status_code status = I40E_SUCCESS;
986 DEBUGFUNC("i40e_validate_mac_addr");
988 /* Broadcast addresses ARE multicast addresses
989 * Make sure it is not a multicast address
990 * Reject the zero address
992 if (I40E_IS_MULTICAST(mac_addr) ||
993 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
994 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
995 status = I40E_ERR_INVALID_MAC_ADDR;
1002 * i40e_init_shared_code - Initialize the shared code
1003 * @hw: pointer to hardware structure
1005 * This assigns the MAC type and PHY code and inits the NVM.
1006 * Does not touch the hardware. This function must be called prior to any
1007 * other function in the shared code. The i40e_hw structure should be
1008 * memset to 0 prior to calling this function. The following fields in
1009 * hw structure should be filled in prior to calling this function:
1010 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1011 * subsystem_vendor_id, and revision_id
1013 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 enum i40e_status_code status = I40E_SUCCESS;
1016 u32 port, ari, func_rid;
1018 DEBUGFUNC("i40e_init_shared_code");
1020 i40e_set_mac_type(hw);
1022 switch (hw->mac.type) {
1023 case I40E_MAC_XL710:
1029 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1032 hw->phy.get_link_info = true;
1034 /* Determine port number and PF number*/
1035 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1036 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1037 hw->port = (u8)port;
1038 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1039 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1040 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042 hw->pf_id = (u8)(func_rid & 0xff);
1044 hw->pf_id = (u8)(func_rid & 0x7);
1047 if (hw->mac.type == I40E_MAC_X722)
1048 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1051 status = i40e_init_nvm(hw);
1056 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1057 * @hw: pointer to the hw struct
1058 * @flags: a return indicator of what addresses were added to the addr store
1059 * @addrs: the requestor's mac addr store
1060 * @cmd_details: pointer to command details structure or NULL
1062 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1064 struct i40e_aqc_mac_address_read_data *addrs,
1065 struct i40e_asq_cmd_details *cmd_details)
1067 struct i40e_aq_desc desc;
1068 struct i40e_aqc_mac_address_read *cmd_data =
1069 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1070 enum i40e_status_code status;
1072 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1073 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1075 status = i40e_asq_send_command(hw, &desc, addrs,
1076 sizeof(*addrs), cmd_details);
1077 *flags = LE16_TO_CPU(cmd_data->command_flags);
1083 * i40e_aq_mac_address_write - Change the MAC addresses
1084 * @hw: pointer to the hw struct
1085 * @flags: indicates which MAC to be written
1086 * @mac_addr: address to write
1087 * @cmd_details: pointer to command details structure or NULL
1089 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1090 u16 flags, u8 *mac_addr,
1091 struct i40e_asq_cmd_details *cmd_details)
1093 struct i40e_aq_desc desc;
1094 struct i40e_aqc_mac_address_write *cmd_data =
1095 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1096 enum i40e_status_code status;
1098 i40e_fill_default_direct_cmd_desc(&desc,
1099 i40e_aqc_opc_mac_address_write);
1100 cmd_data->command_flags = CPU_TO_LE16(flags);
1101 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1102 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1103 ((u32)mac_addr[3] << 16) |
1104 ((u32)mac_addr[4] << 8) |
1107 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1113 * i40e_get_mac_addr - get MAC address
1114 * @hw: pointer to the HW structure
1115 * @mac_addr: pointer to MAC address
1117 * Reads the adapter's MAC address from register
1119 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1121 struct i40e_aqc_mac_address_read_data addrs;
1122 enum i40e_status_code status;
1125 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1127 if (flags & I40E_AQC_LAN_ADDR_VALID)
1128 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1129 I40E_NONDMA_TO_NONDMA);
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1153 I40E_NONDMA_TO_NONDMA);
1155 status = I40E_ERR_INVALID_MAC_ADDR;
1161 * i40e_pre_tx_queue_cfg - pre tx queue configure
1162 * @hw: pointer to the HW structure
1163 * @queue: target pf queue index
1164 * @enable: state change request
1166 * Handles hw requirement to indicate intention to enable
1167 * or disable target queue.
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1171 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1175 if (abs_queue_idx >= 128) {
1176 reg_block = abs_queue_idx / 128;
1177 abs_queue_idx %= 128;
1180 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1185 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1187 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1189 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1193 * i40e_get_san_mac_addr - get SAN MAC address
1194 * @hw: pointer to the HW structure
1195 * @mac_addr: pointer to SAN MAC address
1197 * Reads the adapter's SAN MAC address from NVM
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1202 struct i40e_aqc_mac_address_read_data addrs;
1203 enum i40e_status_code status;
1206 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1210 if (flags & I40E_AQC_SAN_ADDR_VALID)
1211 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1212 I40E_NONDMA_TO_NONDMA);
1214 status = I40E_ERR_INVALID_MAC_ADDR;
1220 * i40e_read_pba_string - Reads part number string from EEPROM
1221 * @hw: pointer to hardware structure
1222 * @pba_num: stores the part number string from the EEPROM
1223 * @pba_num_size: part number string buffer length
1225 * Reads the part number string from the EEPROM.
1227 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1230 enum i40e_status_code status = I40E_SUCCESS;
1236 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1237 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1238 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1242 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1243 if (status != I40E_SUCCESS) {
1244 DEBUGOUT("Failed to read PBA Block pointer.\n");
1248 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1249 if (status != I40E_SUCCESS) {
1250 DEBUGOUT("Failed to read PBA Block size.\n");
1254 /* Subtract one to get PBA word count (PBA Size word is included in
1258 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1259 DEBUGOUT("Buffer to small for PBA data.\n");
1260 return I40E_ERR_PARAM;
1263 for (i = 0; i < pba_size; i++) {
1264 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1265 if (status != I40E_SUCCESS) {
1266 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1270 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1271 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1273 pba_num[(pba_size * 2)] = '\0';
1279 * i40e_get_media_type - Gets media type
1280 * @hw: pointer to the hardware structure
1282 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1284 enum i40e_media_type media;
1286 switch (hw->phy.link_info.phy_type) {
1287 case I40E_PHY_TYPE_10GBASE_SR:
1288 case I40E_PHY_TYPE_10GBASE_LR:
1289 case I40E_PHY_TYPE_1000BASE_SX:
1290 case I40E_PHY_TYPE_1000BASE_LX:
1291 case I40E_PHY_TYPE_40GBASE_SR4:
1292 case I40E_PHY_TYPE_40GBASE_LR4:
1293 case I40E_PHY_TYPE_25GBASE_LR:
1294 case I40E_PHY_TYPE_25GBASE_SR:
1295 media = I40E_MEDIA_TYPE_FIBER;
1297 case I40E_PHY_TYPE_100BASE_TX:
1298 case I40E_PHY_TYPE_1000BASE_T:
1299 case I40E_PHY_TYPE_10GBASE_T:
1300 media = I40E_MEDIA_TYPE_BASET;
1302 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1303 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1304 case I40E_PHY_TYPE_10GBASE_CR1:
1305 case I40E_PHY_TYPE_40GBASE_CR4:
1306 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1307 case I40E_PHY_TYPE_40GBASE_AOC:
1308 case I40E_PHY_TYPE_10GBASE_AOC:
1309 case I40E_PHY_TYPE_25GBASE_CR:
1310 media = I40E_MEDIA_TYPE_DA;
1312 case I40E_PHY_TYPE_1000BASE_KX:
1313 case I40E_PHY_TYPE_10GBASE_KX4:
1314 case I40E_PHY_TYPE_10GBASE_KR:
1315 case I40E_PHY_TYPE_40GBASE_KR4:
1316 case I40E_PHY_TYPE_20GBASE_KR2:
1317 case I40E_PHY_TYPE_25GBASE_KR:
1318 media = I40E_MEDIA_TYPE_BACKPLANE;
1320 case I40E_PHY_TYPE_SGMII:
1321 case I40E_PHY_TYPE_XAUI:
1322 case I40E_PHY_TYPE_XFI:
1323 case I40E_PHY_TYPE_XLAUI:
1324 case I40E_PHY_TYPE_XLPPI:
1326 media = I40E_MEDIA_TYPE_UNKNOWN;
1333 #define I40E_PF_RESET_WAIT_COUNT 200
1335 * i40e_pf_reset - Reset the PF
1336 * @hw: pointer to the hardware structure
1338 * Assuming someone else has triggered a global reset,
1339 * assure the global reset is complete and then reset the PF
1341 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1348 /* Poll for Global Reset steady state in case of recent GRST.
1349 * The grst delay value is in 100ms units, and we'll wait a
1350 * couple counts longer to be sure we don't just miss the end.
1352 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1353 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1354 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1356 grst_del = grst_del * 20;
1358 for (cnt = 0; cnt < grst_del; cnt++) {
1359 reg = rd32(hw, I40E_GLGEN_RSTAT);
1360 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1362 i40e_msec_delay(100);
1364 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1365 DEBUGOUT("Global reset polling failed to complete.\n");
1366 return I40E_ERR_RESET_FAILED;
1369 /* Now Wait for the FW to be ready */
1370 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1371 reg = rd32(hw, I40E_GLNVM_ULD);
1372 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1374 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1375 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1376 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1379 i40e_msec_delay(10);
1381 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1383 DEBUGOUT("wait for FW Reset complete timedout\n");
1384 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1385 return I40E_ERR_RESET_FAILED;
1388 /* If there was a Global Reset in progress when we got here,
1389 * we don't need to do the PF Reset
1392 reg = rd32(hw, I40E_PFGEN_CTRL);
1393 wr32(hw, I40E_PFGEN_CTRL,
1394 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396 reg = rd32(hw, I40E_PFGEN_CTRL);
1397 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1401 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1402 DEBUGOUT("PF reset polling failed to complete.\n");
1403 return I40E_ERR_RESET_FAILED;
1407 i40e_clear_pxe_mode(hw);
1410 return I40E_SUCCESS;
1414 * i40e_clear_hw - clear out any left over hw state
1415 * @hw: pointer to the hw struct
1417 * Clear queues and interrupts, typically called at init time,
1418 * but after the capabilities have been found so we know how many
1419 * queues and msix vectors have been allocated.
1421 void i40e_clear_hw(struct i40e_hw *hw)
1423 u32 num_queues, base_queue;
1431 /* get number of interrupts, queues, and vfs */
1432 val = rd32(hw, I40E_GLPCI_CNF2);
1433 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1434 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1435 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1436 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1438 val = rd32(hw, I40E_PFLAN_QALLOC);
1439 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1440 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1441 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1442 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1443 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1444 num_queues = (j - base_queue) + 1;
1448 val = rd32(hw, I40E_PF_VT_PFALLOC);
1449 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1450 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1451 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1452 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1453 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1454 num_vfs = (j - i) + 1;
1458 /* stop all the interrupts */
1459 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1460 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1461 for (i = 0; i < num_pf_int - 2; i++)
1462 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1464 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1465 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1466 wr32(hw, I40E_PFINT_LNKLST0, val);
1467 for (i = 0; i < num_pf_int - 2; i++)
1468 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1469 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1470 for (i = 0; i < num_vfs; i++)
1471 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1472 for (i = 0; i < num_vf_int - 2; i++)
1473 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1475 /* warn the HW of the coming Tx disables */
1476 for (i = 0; i < num_queues; i++) {
1477 u32 abs_queue_idx = base_queue + i;
1480 if (abs_queue_idx >= 128) {
1481 reg_block = abs_queue_idx / 128;
1482 abs_queue_idx %= 128;
1485 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1486 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1487 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1488 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1490 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1492 i40e_usec_delay(400);
1494 /* stop all the queues */
1495 for (i = 0; i < num_queues; i++) {
1496 wr32(hw, I40E_QINT_TQCTL(i), 0);
1497 wr32(hw, I40E_QTX_ENA(i), 0);
1498 wr32(hw, I40E_QINT_RQCTL(i), 0);
1499 wr32(hw, I40E_QRX_ENA(i), 0);
1502 /* short wait for all queue disables to settle */
1503 i40e_usec_delay(50);
1507 * i40e_clear_pxe_mode - clear pxe operations mode
1508 * @hw: pointer to the hw struct
1510 * Make sure all PXE mode settings are cleared, including things
1511 * like descriptor fetch/write-back mode.
1513 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1515 if (i40e_check_asq_alive(hw))
1516 i40e_aq_clear_pxe_mode(hw, NULL);
1520 * i40e_led_is_mine - helper to find matching led
1521 * @hw: pointer to the hw struct
1522 * @idx: index into GPIO registers
1524 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1526 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1531 if (!hw->func_caps.led[idx])
1534 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1535 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1536 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1538 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1539 * if it is not our port then ignore
1541 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1548 #define I40E_COMBINED_ACTIVITY 0xA
1549 #define I40E_FILTER_ACTIVITY 0xE
1550 #define I40E_LINK_ACTIVITY 0xC
1551 #define I40E_MAC_ACTIVITY 0xD
1552 #define I40E_LED0 22
1555 * i40e_led_get - return current on/off mode
1556 * @hw: pointer to the hw struct
1558 * The value returned is the 'mode' field as defined in the
1559 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1560 * values are variations of possible behaviors relating to
1561 * blink, link, and wire.
1563 u32 i40e_led_get(struct i40e_hw *hw)
1565 u32 current_mode = 0;
1569 /* as per the documentation GPIO 22-29 are the LED
1570 * GPIO pins named LED0..LED7
1572 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1573 u32 gpio_val = i40e_led_is_mine(hw, i);
1578 /* ignore gpio LED src mode entries related to the activity
1581 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1582 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1583 switch (current_mode) {
1584 case I40E_COMBINED_ACTIVITY:
1585 case I40E_FILTER_ACTIVITY:
1586 case I40E_MAC_ACTIVITY:
1592 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1593 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1601 * i40e_led_set - set new on/off mode
1602 * @hw: pointer to the hw struct
1603 * @mode: 0=off, 0xf=on (else see manual for mode details)
1604 * @blink: true if the LED should blink when on, false if steady
1606 * if this function is used to turn on the blink it should
1607 * be used to disable the blink when restoring the original state.
1609 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1611 u32 current_mode = 0;
1614 if (mode & 0xfffffff0)
1615 DEBUGOUT1("invalid mode passed in %X\n", mode);
1617 /* as per the documentation GPIO 22-29 are the LED
1618 * GPIO pins named LED0..LED7
1620 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1621 u32 gpio_val = i40e_led_is_mine(hw, i);
1626 /* ignore gpio LED src mode entries related to the activity
1629 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1630 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1631 switch (current_mode) {
1632 case I40E_COMBINED_ACTIVITY:
1633 case I40E_FILTER_ACTIVITY:
1634 case I40E_MAC_ACTIVITY:
1640 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1641 /* this & is a bit of paranoia, but serves as a range check */
1642 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1643 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1645 if (mode == I40E_LINK_ACTIVITY)
1649 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1653 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1658 /* Admin command wrappers */
1661 * i40e_aq_get_phy_capabilities
1662 * @hw: pointer to the hw struct
1663 * @abilities: structure for PHY capabilities to be filled
1664 * @qualified_modules: report Qualified Modules
1665 * @report_init: report init capabilities (active are default)
1666 * @cmd_details: pointer to command details structure or NULL
1668 * Returns the various PHY abilities supported on the Port.
1670 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1671 bool qualified_modules, bool report_init,
1672 struct i40e_aq_get_phy_abilities_resp *abilities,
1673 struct i40e_asq_cmd_details *cmd_details)
1675 struct i40e_aq_desc desc;
1676 enum i40e_status_code status;
1677 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1680 return I40E_ERR_PARAM;
1682 i40e_fill_default_direct_cmd_desc(&desc,
1683 i40e_aqc_opc_get_phy_abilities);
1685 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1686 if (abilities_size > I40E_AQ_LARGE_BUF)
1687 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1689 if (qualified_modules)
1690 desc.params.external.param0 |=
1691 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1694 desc.params.external.param0 |=
1695 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1697 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1700 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1701 status = I40E_ERR_UNKNOWN_PHY;
1704 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1705 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1712 * i40e_aq_set_phy_config
1713 * @hw: pointer to the hw struct
1714 * @config: structure with PHY configuration to be set
1715 * @cmd_details: pointer to command details structure or NULL
1717 * Set the various PHY configuration parameters
1718 * supported on the Port.One or more of the Set PHY config parameters may be
1719 * ignored in an MFP mode as the PF may not have the privilege to set some
1720 * of the PHY Config parameters. This status will be indicated by the
1723 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1724 struct i40e_aq_set_phy_config *config,
1725 struct i40e_asq_cmd_details *cmd_details)
1727 struct i40e_aq_desc desc;
1728 struct i40e_aq_set_phy_config *cmd =
1729 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1730 enum i40e_status_code status;
1733 return I40E_ERR_PARAM;
1735 i40e_fill_default_direct_cmd_desc(&desc,
1736 i40e_aqc_opc_set_phy_config);
1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747 * @hw: pointer to the hw struct
1749 * Set the requested flow control mode using set_phy_config.
1751 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1752 bool atomic_restart)
1754 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1755 struct i40e_aq_get_phy_abilities_resp abilities;
1756 struct i40e_aq_set_phy_config config;
1757 enum i40e_status_code status;
1758 u8 pause_mask = 0x0;
1764 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1765 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1767 case I40E_FC_RX_PAUSE:
1768 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1770 case I40E_FC_TX_PAUSE:
1771 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1777 /* Get the current phy config */
1778 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1781 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1785 memset(&config, 0, sizeof(config));
1786 /* clear the old pause settings */
1787 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1788 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1789 /* set the new abilities */
1790 config.abilities |= pause_mask;
1791 /* If the abilities have changed, then set the new config */
1792 if (config.abilities != abilities.abilities) {
1793 /* Auto restart link so settings take effect */
1795 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1796 /* Copy over all the old settings */
1797 config.phy_type = abilities.phy_type;
1798 config.phy_type_ext = abilities.phy_type_ext;
1799 config.link_speed = abilities.link_speed;
1800 config.eee_capability = abilities.eee_capability;
1801 config.eeer = abilities.eeer_val;
1802 config.low_power_ctrl = abilities.d3_lpan;
1803 status = i40e_aq_set_phy_config(hw, &config, NULL);
1806 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1808 /* Update the link info */
1809 status = i40e_update_link_info(hw);
1811 /* Wait a little bit (on 40G cards it sometimes takes a really
1812 * long time for link to come back from the atomic reset)
1815 i40e_msec_delay(1000);
1816 status = i40e_update_link_info(hw);
1819 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1825 * i40e_aq_set_mac_config
1826 * @hw: pointer to the hw struct
1827 * @max_frame_size: Maximum Frame Size to be supported by the port
1828 * @crc_en: Tell HW to append a CRC to outgoing frames
1829 * @pacing: Pacing configurations
1830 * @cmd_details: pointer to command details structure or NULL
1832 * Configure MAC settings for frame size, jumbo frame support and the
1833 * addition of a CRC by the hardware.
1835 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1837 bool crc_en, u16 pacing,
1838 struct i40e_asq_cmd_details *cmd_details)
1840 struct i40e_aq_desc desc;
1841 struct i40e_aq_set_mac_config *cmd =
1842 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1843 enum i40e_status_code status;
1845 if (max_frame_size == 0)
1846 return I40E_ERR_PARAM;
1848 i40e_fill_default_direct_cmd_desc(&desc,
1849 i40e_aqc_opc_set_mac_config);
1851 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1852 cmd->params = ((u8)pacing & 0x0F) << 3;
1854 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1862 * i40e_aq_clear_pxe_mode
1863 * @hw: pointer to the hw struct
1864 * @cmd_details: pointer to command details structure or NULL
1866 * Tell the firmware that the driver is taking over from PXE
1868 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1869 struct i40e_asq_cmd_details *cmd_details)
1871 enum i40e_status_code status;
1872 struct i40e_aq_desc desc;
1873 struct i40e_aqc_clear_pxe *cmd =
1874 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1876 i40e_fill_default_direct_cmd_desc(&desc,
1877 i40e_aqc_opc_clear_pxe_mode);
1881 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1883 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1889 * i40e_aq_set_link_restart_an
1890 * @hw: pointer to the hw struct
1891 * @enable_link: if true: enable link, if false: disable link
1892 * @cmd_details: pointer to command details structure or NULL
1894 * Sets up the link and restarts the Auto-Negotiation over the link.
1896 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1897 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1899 struct i40e_aq_desc desc;
1900 struct i40e_aqc_set_link_restart_an *cmd =
1901 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1902 enum i40e_status_code status;
1904 i40e_fill_default_direct_cmd_desc(&desc,
1905 i40e_aqc_opc_set_link_restart_an);
1907 cmd->command = I40E_AQ_PHY_RESTART_AN;
1909 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1911 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1919 * i40e_aq_get_link_info
1920 * @hw: pointer to the hw struct
1921 * @enable_lse: enable/disable LinkStatusEvent reporting
1922 * @link: pointer to link status structure - optional
1923 * @cmd_details: pointer to command details structure or NULL
1925 * Returns the link status of the adapter.
1927 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1928 bool enable_lse, struct i40e_link_status *link,
1929 struct i40e_asq_cmd_details *cmd_details)
1931 struct i40e_aq_desc desc;
1932 struct i40e_aqc_get_link_status *resp =
1933 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1934 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1935 enum i40e_status_code status;
1936 bool tx_pause, rx_pause;
1939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1942 command_flags = I40E_AQ_LSE_ENABLE;
1944 command_flags = I40E_AQ_LSE_DISABLE;
1945 resp->command_flags = CPU_TO_LE16(command_flags);
1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1949 if (status != I40E_SUCCESS)
1950 goto aq_get_link_info_exit;
1952 /* save off old link status information */
1953 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1954 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1956 /* update link status */
1957 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1958 hw->phy.media_type = i40e_get_media_type(hw);
1959 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1960 hw_link_info->link_info = resp->link_info;
1961 hw_link_info->an_info = resp->an_info;
1962 hw_link_info->ext_info = resp->ext_info;
1963 hw_link_info->loopback = resp->loopback;
1964 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1965 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1967 /* update fc info */
1968 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1969 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1970 if (tx_pause & rx_pause)
1971 hw->fc.current_mode = I40E_FC_FULL;
1973 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1975 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1977 hw->fc.current_mode = I40E_FC_NONE;
1979 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1980 hw_link_info->crc_enable = true;
1982 hw_link_info->crc_enable = false;
1984 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1985 hw_link_info->lse_enable = true;
1987 hw_link_info->lse_enable = false;
1989 if ((hw->mac.type == I40E_MAC_XL710) &&
1990 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1991 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1992 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1994 /* save link status information */
1996 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1997 I40E_NONDMA_TO_NONDMA);
1999 /* flag cleared so helper functions don't call AQ again */
2000 hw->phy.get_link_info = false;
2002 aq_get_link_info_exit:
2007 * i40e_aq_set_phy_int_mask
2008 * @hw: pointer to the hw struct
2009 * @mask: interrupt mask to be set
2010 * @cmd_details: pointer to command details structure or NULL
2012 * Set link interrupt mask.
2014 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2016 struct i40e_asq_cmd_details *cmd_details)
2018 struct i40e_aq_desc desc;
2019 struct i40e_aqc_set_phy_int_mask *cmd =
2020 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2021 enum i40e_status_code status;
2023 i40e_fill_default_direct_cmd_desc(&desc,
2024 i40e_aqc_opc_set_phy_int_mask);
2026 cmd->event_mask = CPU_TO_LE16(mask);
2028 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2034 * i40e_aq_get_local_advt_reg
2035 * @hw: pointer to the hw struct
2036 * @advt_reg: local AN advertisement register value
2037 * @cmd_details: pointer to command details structure or NULL
2039 * Get the Local AN advertisement register value.
2041 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2043 struct i40e_asq_cmd_details *cmd_details)
2045 struct i40e_aq_desc desc;
2046 struct i40e_aqc_an_advt_reg *resp =
2047 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2048 enum i40e_status_code status;
2050 i40e_fill_default_direct_cmd_desc(&desc,
2051 i40e_aqc_opc_get_local_advt_reg);
2053 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2055 if (status != I40E_SUCCESS)
2056 goto aq_get_local_advt_reg_exit;
2058 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2059 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2061 aq_get_local_advt_reg_exit:
2066 * i40e_aq_set_local_advt_reg
2067 * @hw: pointer to the hw struct
2068 * @advt_reg: local AN advertisement register value
2069 * @cmd_details: pointer to command details structure or NULL
2071 * Get the Local AN advertisement register value.
2073 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2075 struct i40e_asq_cmd_details *cmd_details)
2077 struct i40e_aq_desc desc;
2078 struct i40e_aqc_an_advt_reg *cmd =
2079 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2080 enum i40e_status_code status;
2082 i40e_fill_default_direct_cmd_desc(&desc,
2083 i40e_aqc_opc_get_local_advt_reg);
2085 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2086 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2094 * i40e_aq_get_partner_advt
2095 * @hw: pointer to the hw struct
2096 * @advt_reg: AN partner advertisement register value
2097 * @cmd_details: pointer to command details structure or NULL
2099 * Get the link partner AN advertisement register value.
2101 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2103 struct i40e_asq_cmd_details *cmd_details)
2105 struct i40e_aq_desc desc;
2106 struct i40e_aqc_an_advt_reg *resp =
2107 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2108 enum i40e_status_code status;
2110 i40e_fill_default_direct_cmd_desc(&desc,
2111 i40e_aqc_opc_get_partner_advt);
2113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2115 if (status != I40E_SUCCESS)
2116 goto aq_get_partner_advt_exit;
2118 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2119 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2121 aq_get_partner_advt_exit:
2126 * i40e_aq_set_lb_modes
2127 * @hw: pointer to the hw struct
2128 * @lb_modes: loopback mode to be set
2129 * @cmd_details: pointer to command details structure or NULL
2131 * Sets loopback modes.
2133 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2135 struct i40e_asq_cmd_details *cmd_details)
2137 struct i40e_aq_desc desc;
2138 struct i40e_aqc_set_lb_mode *cmd =
2139 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2140 enum i40e_status_code status;
2142 i40e_fill_default_direct_cmd_desc(&desc,
2143 i40e_aqc_opc_set_lb_modes);
2145 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2147 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2153 * i40e_aq_set_phy_debug
2154 * @hw: pointer to the hw struct
2155 * @cmd_flags: debug command flags
2156 * @cmd_details: pointer to command details structure or NULL
2158 * Reset the external PHY.
2160 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2161 struct i40e_asq_cmd_details *cmd_details)
2163 struct i40e_aq_desc desc;
2164 struct i40e_aqc_set_phy_debug *cmd =
2165 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2166 enum i40e_status_code status;
2168 i40e_fill_default_direct_cmd_desc(&desc,
2169 i40e_aqc_opc_set_phy_debug);
2171 cmd->command_flags = cmd_flags;
2173 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2180 * @hw: pointer to the hw struct
2181 * @vsi_ctx: pointer to a vsi context struct
2182 * @cmd_details: pointer to command details structure or NULL
2184 * Add a VSI context to the hardware.
2186 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2187 struct i40e_vsi_context *vsi_ctx,
2188 struct i40e_asq_cmd_details *cmd_details)
2190 struct i40e_aq_desc desc;
2191 struct i40e_aqc_add_get_update_vsi *cmd =
2192 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2193 struct i40e_aqc_add_get_update_vsi_completion *resp =
2194 (struct i40e_aqc_add_get_update_vsi_completion *)
2196 enum i40e_status_code status;
2198 i40e_fill_default_direct_cmd_desc(&desc,
2199 i40e_aqc_opc_add_vsi);
2201 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2202 cmd->connection_type = vsi_ctx->connection_type;
2203 cmd->vf_id = vsi_ctx->vf_num;
2204 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2206 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2208 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2209 sizeof(vsi_ctx->info), cmd_details);
2211 if (status != I40E_SUCCESS)
2212 goto aq_add_vsi_exit;
2214 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2215 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2216 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2217 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2224 * i40e_aq_set_default_vsi
2225 * @hw: pointer to the hw struct
2227 * @cmd_details: pointer to command details structure or NULL
2229 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2231 struct i40e_asq_cmd_details *cmd_details)
2233 struct i40e_aq_desc desc;
2234 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2235 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2237 enum i40e_status_code status;
2239 i40e_fill_default_direct_cmd_desc(&desc,
2240 i40e_aqc_opc_set_vsi_promiscuous_modes);
2242 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2243 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2244 cmd->seid = CPU_TO_LE16(seid);
2246 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2252 * i40e_aq_clear_default_vsi
2253 * @hw: pointer to the hw struct
2255 * @cmd_details: pointer to command details structure or NULL
2257 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2259 struct i40e_asq_cmd_details *cmd_details)
2261 struct i40e_aq_desc desc;
2262 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2263 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2265 enum i40e_status_code status;
2267 i40e_fill_default_direct_cmd_desc(&desc,
2268 i40e_aqc_opc_set_vsi_promiscuous_modes);
2270 cmd->promiscuous_flags = CPU_TO_LE16(0);
2271 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2272 cmd->seid = CPU_TO_LE16(seid);
2274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2280 * i40e_aq_set_vsi_unicast_promiscuous
2281 * @hw: pointer to the hw struct
2283 * @set: set unicast promiscuous enable/disable
2284 * @cmd_details: pointer to command details structure or NULL
2285 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2287 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2289 struct i40e_asq_cmd_details *cmd_details,
2290 bool rx_only_promisc)
2292 struct i40e_aq_desc desc;
2293 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2294 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2295 enum i40e_status_code status;
2298 i40e_fill_default_direct_cmd_desc(&desc,
2299 i40e_aqc_opc_set_vsi_promiscuous_modes);
2302 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2303 if (rx_only_promisc &&
2304 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2305 (hw->aq.api_maj_ver > 1)))
2306 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2309 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2311 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2312 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2313 (hw->aq.api_maj_ver > 1))
2314 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2316 cmd->seid = CPU_TO_LE16(seid);
2317 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2323 * i40e_aq_set_vsi_multicast_promiscuous
2324 * @hw: pointer to the hw struct
2326 * @set: set multicast promiscuous enable/disable
2327 * @cmd_details: pointer to command details structure or NULL
2329 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2330 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2332 struct i40e_aq_desc desc;
2333 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2334 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2335 enum i40e_status_code status;
2338 i40e_fill_default_direct_cmd_desc(&desc,
2339 i40e_aqc_opc_set_vsi_promiscuous_modes);
2342 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2344 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2346 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2348 cmd->seid = CPU_TO_LE16(seid);
2349 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2355 * i40e_aq_set_vsi_mc_promisc_on_vlan
2356 * @hw: pointer to the hw struct
2358 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2359 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2360 * @cmd_details: pointer to command details structure or NULL
2362 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2363 u16 seid, bool enable, u16 vid,
2364 struct i40e_asq_cmd_details *cmd_details)
2366 struct i40e_aq_desc desc;
2367 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2368 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2369 enum i40e_status_code status;
2372 i40e_fill_default_direct_cmd_desc(&desc,
2373 i40e_aqc_opc_set_vsi_promiscuous_modes);
2376 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2378 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2379 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2380 cmd->seid = CPU_TO_LE16(seid);
2381 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2383 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2389 * i40e_aq_set_vsi_uc_promisc_on_vlan
2390 * @hw: pointer to the hw struct
2392 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2393 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2394 * @cmd_details: pointer to command details structure or NULL
2396 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2397 u16 seid, bool enable, u16 vid,
2398 struct i40e_asq_cmd_details *cmd_details)
2400 struct i40e_aq_desc desc;
2401 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2402 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2403 enum i40e_status_code status;
2406 i40e_fill_default_direct_cmd_desc(&desc,
2407 i40e_aqc_opc_set_vsi_promiscuous_modes);
2410 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2412 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2413 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2414 cmd->seid = CPU_TO_LE16(seid);
2415 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2417 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2423 * i40e_aq_set_vsi_broadcast
2424 * @hw: pointer to the hw struct
2426 * @set_filter: true to set filter, false to clear filter
2427 * @cmd_details: pointer to command details structure or NULL
2429 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2431 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2432 u16 seid, bool set_filter,
2433 struct i40e_asq_cmd_details *cmd_details)
2435 struct i40e_aq_desc desc;
2436 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2437 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2438 enum i40e_status_code status;
2440 i40e_fill_default_direct_cmd_desc(&desc,
2441 i40e_aqc_opc_set_vsi_promiscuous_modes);
2444 cmd->promiscuous_flags
2445 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2447 cmd->promiscuous_flags
2448 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2450 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2451 cmd->seid = CPU_TO_LE16(seid);
2452 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2458 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2459 * @hw: pointer to the hw struct
2461 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2462 * @cmd_details: pointer to command details structure or NULL
2464 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2465 u16 seid, bool enable,
2466 struct i40e_asq_cmd_details *cmd_details)
2468 struct i40e_aq_desc desc;
2469 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2470 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2471 enum i40e_status_code status;
2474 i40e_fill_default_direct_cmd_desc(&desc,
2475 i40e_aqc_opc_set_vsi_promiscuous_modes);
2477 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2479 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2480 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2481 cmd->seid = CPU_TO_LE16(seid);
2483 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2489 * i40e_get_vsi_params - get VSI configuration info
2490 * @hw: pointer to the hw struct
2491 * @vsi_ctx: pointer to a vsi context struct
2492 * @cmd_details: pointer to command details structure or NULL
2494 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2495 struct i40e_vsi_context *vsi_ctx,
2496 struct i40e_asq_cmd_details *cmd_details)
2498 struct i40e_aq_desc desc;
2499 struct i40e_aqc_add_get_update_vsi *cmd =
2500 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2501 struct i40e_aqc_add_get_update_vsi_completion *resp =
2502 (struct i40e_aqc_add_get_update_vsi_completion *)
2504 enum i40e_status_code status;
2506 UNREFERENCED_1PARAMETER(cmd_details);
2507 i40e_fill_default_direct_cmd_desc(&desc,
2508 i40e_aqc_opc_get_vsi_parameters);
2510 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2512 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2514 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2515 sizeof(vsi_ctx->info), NULL);
2517 if (status != I40E_SUCCESS)
2518 goto aq_get_vsi_params_exit;
2520 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2521 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2522 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2523 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2525 aq_get_vsi_params_exit:
2530 * i40e_aq_update_vsi_params
2531 * @hw: pointer to the hw struct
2532 * @vsi_ctx: pointer to a vsi context struct
2533 * @cmd_details: pointer to command details structure or NULL
2535 * Update a VSI context.
2537 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2538 struct i40e_vsi_context *vsi_ctx,
2539 struct i40e_asq_cmd_details *cmd_details)
2541 struct i40e_aq_desc desc;
2542 struct i40e_aqc_add_get_update_vsi *cmd =
2543 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2544 struct i40e_aqc_add_get_update_vsi_completion *resp =
2545 (struct i40e_aqc_add_get_update_vsi_completion *)
2547 enum i40e_status_code status;
2549 i40e_fill_default_direct_cmd_desc(&desc,
2550 i40e_aqc_opc_update_vsi_parameters);
2551 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2553 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2555 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2556 sizeof(vsi_ctx->info), cmd_details);
2558 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2559 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2565 * i40e_aq_get_switch_config
2566 * @hw: pointer to the hardware structure
2567 * @buf: pointer to the result buffer
2568 * @buf_size: length of input buffer
2569 * @start_seid: seid to start for the report, 0 == beginning
2570 * @cmd_details: pointer to command details structure or NULL
2572 * Fill the buf with switch configuration returned from AdminQ command
2574 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2575 struct i40e_aqc_get_switch_config_resp *buf,
2576 u16 buf_size, u16 *start_seid,
2577 struct i40e_asq_cmd_details *cmd_details)
2579 struct i40e_aq_desc desc;
2580 struct i40e_aqc_switch_seid *scfg =
2581 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2582 enum i40e_status_code status;
2584 i40e_fill_default_direct_cmd_desc(&desc,
2585 i40e_aqc_opc_get_switch_config);
2586 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2587 if (buf_size > I40E_AQ_LARGE_BUF)
2588 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2589 scfg->seid = CPU_TO_LE16(*start_seid);
2591 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2592 *start_seid = LE16_TO_CPU(scfg->seid);
2598 * i40e_aq_set_switch_config
2599 * @hw: pointer to the hardware structure
2600 * @flags: bit flag values to set
2601 * @valid_flags: which bit flags to set
2602 * @cmd_details: pointer to command details structure or NULL
2604 * Set switch configuration bits
2606 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2607 u16 flags, u16 valid_flags,
2608 struct i40e_asq_cmd_details *cmd_details)
2610 struct i40e_aq_desc desc;
2611 struct i40e_aqc_set_switch_config *scfg =
2612 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2613 enum i40e_status_code status;
2615 i40e_fill_default_direct_cmd_desc(&desc,
2616 i40e_aqc_opc_set_switch_config);
2617 scfg->flags = CPU_TO_LE16(flags);
2618 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2620 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2626 * i40e_aq_get_firmware_version
2627 * @hw: pointer to the hw struct
2628 * @fw_major_version: firmware major version
2629 * @fw_minor_version: firmware minor version
2630 * @fw_build: firmware build number
2631 * @api_major_version: major queue version
2632 * @api_minor_version: minor queue version
2633 * @cmd_details: pointer to command details structure or NULL
2635 * Get the firmware version from the admin queue commands
2637 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2638 u16 *fw_major_version, u16 *fw_minor_version,
2640 u16 *api_major_version, u16 *api_minor_version,
2641 struct i40e_asq_cmd_details *cmd_details)
2643 struct i40e_aq_desc desc;
2644 struct i40e_aqc_get_version *resp =
2645 (struct i40e_aqc_get_version *)&desc.params.raw;
2646 enum i40e_status_code status;
2648 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2652 if (status == I40E_SUCCESS) {
2653 if (fw_major_version != NULL)
2654 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2655 if (fw_minor_version != NULL)
2656 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2657 if (fw_build != NULL)
2658 *fw_build = LE32_TO_CPU(resp->fw_build);
2659 if (api_major_version != NULL)
2660 *api_major_version = LE16_TO_CPU(resp->api_major);
2661 if (api_minor_version != NULL)
2662 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2664 /* A workaround to fix the API version in SW */
2665 if (api_major_version && api_minor_version &&
2666 fw_major_version && fw_minor_version &&
2667 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2668 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2669 (*fw_major_version > 4)))
2670 *api_minor_version = 2;
2677 * i40e_aq_send_driver_version
2678 * @hw: pointer to the hw struct
2679 * @dv: driver's major, minor version
2680 * @cmd_details: pointer to command details structure or NULL
2682 * Send the driver version to the firmware
2684 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2685 struct i40e_driver_version *dv,
2686 struct i40e_asq_cmd_details *cmd_details)
2688 struct i40e_aq_desc desc;
2689 struct i40e_aqc_driver_version *cmd =
2690 (struct i40e_aqc_driver_version *)&desc.params.raw;
2691 enum i40e_status_code status;
2695 return I40E_ERR_PARAM;
2697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2699 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2700 cmd->driver_major_ver = dv->major_version;
2701 cmd->driver_minor_ver = dv->minor_version;
2702 cmd->driver_build_ver = dv->build_version;
2703 cmd->driver_subbuild_ver = dv->subbuild_version;
2706 while (len < sizeof(dv->driver_string) &&
2707 (dv->driver_string[len] < 0x80) &&
2708 dv->driver_string[len])
2710 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2717 * i40e_get_link_status - get status of the HW network link
2718 * @hw: pointer to the hw struct
2719 * @link_up: pointer to bool (true/false = linkup/linkdown)
2721 * Variable link_up true if link is up, false if link is down.
2722 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2724 * Side effect: LinkStatusEvent reporting becomes enabled
2726 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2728 enum i40e_status_code status = I40E_SUCCESS;
2730 if (hw->phy.get_link_info) {
2731 status = i40e_update_link_info(hw);
2733 if (status != I40E_SUCCESS)
2734 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2738 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2744 * i40e_updatelink_status - update status of the HW network link
2745 * @hw: pointer to the hw struct
2747 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2749 struct i40e_aq_get_phy_abilities_resp abilities;
2750 enum i40e_status_code status = I40E_SUCCESS;
2752 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2756 /* extra checking needed to ensure link info to user is timely */
2757 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2758 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2759 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2760 status = i40e_aq_get_phy_capabilities(hw, false, false,
2765 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2766 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2773 * i40e_get_link_speed
2774 * @hw: pointer to the hw struct
2776 * Returns the link speed of the adapter.
2778 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2780 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2781 enum i40e_status_code status = I40E_SUCCESS;
2783 if (hw->phy.get_link_info) {
2784 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2786 if (status != I40E_SUCCESS)
2787 goto i40e_link_speed_exit;
2790 speed = hw->phy.link_info.link_speed;
2792 i40e_link_speed_exit:
2797 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2798 * @hw: pointer to the hw struct
2799 * @uplink_seid: the MAC or other gizmo SEID
2800 * @downlink_seid: the VSI SEID
2801 * @enabled_tc: bitmap of TCs to be enabled
2802 * @default_port: true for default port VSI, false for control port
2803 * @veb_seid: pointer to where to put the resulting VEB SEID
2804 * @enable_stats: true to turn on VEB stats
2805 * @cmd_details: pointer to command details structure or NULL
2807 * This asks the FW to add a VEB between the uplink and downlink
2808 * elements. If the uplink SEID is 0, this will be a floating VEB.
2810 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2811 u16 downlink_seid, u8 enabled_tc,
2812 bool default_port, u16 *veb_seid,
2814 struct i40e_asq_cmd_details *cmd_details)
2816 struct i40e_aq_desc desc;
2817 struct i40e_aqc_add_veb *cmd =
2818 (struct i40e_aqc_add_veb *)&desc.params.raw;
2819 struct i40e_aqc_add_veb_completion *resp =
2820 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2821 enum i40e_status_code status;
2824 /* SEIDs need to either both be set or both be 0 for floating VEB */
2825 if (!!uplink_seid != !!downlink_seid)
2826 return I40E_ERR_PARAM;
2828 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2830 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2831 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2832 cmd->enable_tcs = enabled_tc;
2834 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2836 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2838 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2840 /* reverse logic here: set the bitflag to disable the stats */
2842 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2844 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2846 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2848 if (!status && veb_seid)
2849 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2855 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2856 * @hw: pointer to the hw struct
2857 * @veb_seid: the SEID of the VEB to query
2858 * @switch_id: the uplink switch id
2859 * @floating: set to true if the VEB is floating
2860 * @statistic_index: index of the stats counter block for this VEB
2861 * @vebs_used: number of VEB's used by function
2862 * @vebs_free: total VEB's not reserved by any function
2863 * @cmd_details: pointer to command details structure or NULL
2865 * This retrieves the parameters for a particular VEB, specified by
2866 * uplink_seid, and returns them to the caller.
2868 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2869 u16 veb_seid, u16 *switch_id,
2870 bool *floating, u16 *statistic_index,
2871 u16 *vebs_used, u16 *vebs_free,
2872 struct i40e_asq_cmd_details *cmd_details)
2874 struct i40e_aq_desc desc;
2875 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2876 (struct i40e_aqc_get_veb_parameters_completion *)
2878 enum i40e_status_code status;
2881 return I40E_ERR_PARAM;
2883 i40e_fill_default_direct_cmd_desc(&desc,
2884 i40e_aqc_opc_get_veb_parameters);
2885 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2887 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2892 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2893 if (statistic_index)
2894 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2896 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2898 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2900 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2902 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2913 * i40e_aq_add_macvlan
2914 * @hw: pointer to the hw struct
2915 * @seid: VSI for the mac address
2916 * @mv_list: list of macvlans to be added
2917 * @count: length of the list
2918 * @cmd_details: pointer to command details structure or NULL
2920 * Add MAC/VLAN addresses to the HW filtering
2922 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2923 struct i40e_aqc_add_macvlan_element_data *mv_list,
2924 u16 count, struct i40e_asq_cmd_details *cmd_details)
2926 struct i40e_aq_desc desc;
2927 struct i40e_aqc_macvlan *cmd =
2928 (struct i40e_aqc_macvlan *)&desc.params.raw;
2929 enum i40e_status_code status;
2933 if (count == 0 || !mv_list || !hw)
2934 return I40E_ERR_PARAM;
2936 buf_size = count * sizeof(*mv_list);
2938 /* prep the rest of the request */
2939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2940 cmd->num_addresses = CPU_TO_LE16(count);
2941 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2945 for (i = 0; i < count; i++)
2946 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2948 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2950 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2951 if (buf_size > I40E_AQ_LARGE_BUF)
2952 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2954 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2961 * i40e_aq_remove_macvlan
2962 * @hw: pointer to the hw struct
2963 * @seid: VSI for the mac address
2964 * @mv_list: list of macvlans to be removed
2965 * @count: length of the list
2966 * @cmd_details: pointer to command details structure or NULL
2968 * Remove MAC/VLAN addresses from the HW filtering
2970 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2971 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2972 u16 count, struct i40e_asq_cmd_details *cmd_details)
2974 struct i40e_aq_desc desc;
2975 struct i40e_aqc_macvlan *cmd =
2976 (struct i40e_aqc_macvlan *)&desc.params.raw;
2977 enum i40e_status_code status;
2980 if (count == 0 || !mv_list || !hw)
2981 return I40E_ERR_PARAM;
2983 buf_size = count * sizeof(*mv_list);
2985 /* prep the rest of the request */
2986 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2987 cmd->num_addresses = CPU_TO_LE16(count);
2988 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2992 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2993 if (buf_size > I40E_AQ_LARGE_BUF)
2994 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2996 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3003 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3004 * @hw: pointer to the hw struct
3005 * @opcode: AQ opcode for add or delete mirror rule
3006 * @sw_seid: Switch SEID (to which rule refers)
3007 * @rule_type: Rule Type (ingress/egress/VLAN)
3008 * @id: Destination VSI SEID or Rule ID
3009 * @count: length of the list
3010 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3011 * @cmd_details: pointer to command details structure or NULL
3012 * @rule_id: Rule ID returned from FW
3013 * @rule_used: Number of rules used in internal switch
3014 * @rule_free: Number of rules free in internal switch
3016 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3017 * VEBs/VEPA elements only
3019 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3020 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3021 u16 count, __le16 *mr_list,
3022 struct i40e_asq_cmd_details *cmd_details,
3023 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3025 struct i40e_aq_desc desc;
3026 struct i40e_aqc_add_delete_mirror_rule *cmd =
3027 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3028 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3029 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3030 enum i40e_status_code status;
3033 buf_size = count * sizeof(*mr_list);
3035 /* prep the rest of the request */
3036 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3037 cmd->seid = CPU_TO_LE16(sw_seid);
3038 cmd->rule_type = CPU_TO_LE16(rule_type &
3039 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3040 cmd->num_entries = CPU_TO_LE16(count);
3041 /* Dest VSI for add, rule_id for delete */
3042 cmd->destination = CPU_TO_LE16(id);
3044 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3046 if (buf_size > I40E_AQ_LARGE_BUF)
3047 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3050 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3052 if (status == I40E_SUCCESS ||
3053 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3055 *rule_id = LE16_TO_CPU(resp->rule_id);
3057 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3059 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3065 * i40e_aq_add_mirrorrule - add a mirror rule
3066 * @hw: pointer to the hw struct
3067 * @sw_seid: Switch SEID (to which rule refers)
3068 * @rule_type: Rule Type (ingress/egress/VLAN)
3069 * @dest_vsi: SEID of VSI to which packets will be mirrored
3070 * @count: length of the list
3071 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3072 * @cmd_details: pointer to command details structure or NULL
3073 * @rule_id: Rule ID returned from FW
3074 * @rule_used: Number of rules used in internal switch
3075 * @rule_free: Number of rules free in internal switch
3077 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3079 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3080 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3081 struct i40e_asq_cmd_details *cmd_details,
3082 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3084 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3085 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3086 if (count == 0 || !mr_list)
3087 return I40E_ERR_PARAM;
3090 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3091 rule_type, dest_vsi, count, mr_list,
3092 cmd_details, rule_id, rules_used, rules_free);
3096 * i40e_aq_delete_mirrorrule - delete a mirror rule
3097 * @hw: pointer to the hw struct
3098 * @sw_seid: Switch SEID (to which rule refers)
3099 * @rule_type: Rule Type (ingress/egress/VLAN)
3100 * @count: length of the list
3101 * @rule_id: Rule ID that is returned in the receive desc as part of
3103 * @mr_list: list of mirrored VLAN IDs to be removed
3104 * @cmd_details: pointer to command details structure or NULL
3105 * @rule_used: Number of rules used in internal switch
3106 * @rule_free: Number of rules free in internal switch
3108 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3110 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3111 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3112 struct i40e_asq_cmd_details *cmd_details,
3113 u16 *rules_used, u16 *rules_free)
3115 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3116 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3117 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3118 * mirroring. For other rule_type, count and rule_type should
3121 if (count == 0 || !mr_list)
3122 return I40E_ERR_PARAM;
3125 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3126 rule_type, rule_id, count, mr_list,
3127 cmd_details, NULL, rules_used, rules_free);
3131 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3132 * @hw: pointer to the hw struct
3133 * @seid: VSI for the vlan filters
3134 * @v_list: list of vlan filters to be added
3135 * @count: length of the list
3136 * @cmd_details: pointer to command details structure or NULL
3138 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3139 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3140 u8 count, struct i40e_asq_cmd_details *cmd_details)
3142 struct i40e_aq_desc desc;
3143 struct i40e_aqc_macvlan *cmd =
3144 (struct i40e_aqc_macvlan *)&desc.params.raw;
3145 enum i40e_status_code status;
3148 if (count == 0 || !v_list || !hw)
3149 return I40E_ERR_PARAM;
3151 buf_size = count * sizeof(*v_list);
3153 /* prep the rest of the request */
3154 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3155 cmd->num_addresses = CPU_TO_LE16(count);
3156 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3160 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3161 if (buf_size > I40E_AQ_LARGE_BUF)
3162 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3164 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3171 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3172 * @hw: pointer to the hw struct
3173 * @seid: VSI for the vlan filters
3174 * @v_list: list of macvlans to be removed
3175 * @count: length of the list
3176 * @cmd_details: pointer to command details structure or NULL
3178 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3179 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3180 u8 count, struct i40e_asq_cmd_details *cmd_details)
3182 struct i40e_aq_desc desc;
3183 struct i40e_aqc_macvlan *cmd =
3184 (struct i40e_aqc_macvlan *)&desc.params.raw;
3185 enum i40e_status_code status;
3188 if (count == 0 || !v_list || !hw)
3189 return I40E_ERR_PARAM;
3191 buf_size = count * sizeof(*v_list);
3193 /* prep the rest of the request */
3194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3195 cmd->num_addresses = CPU_TO_LE16(count);
3196 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3200 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3201 if (buf_size > I40E_AQ_LARGE_BUF)
3202 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3204 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3211 * i40e_aq_send_msg_to_vf
3212 * @hw: pointer to the hardware structure
3213 * @vfid: vf id to send msg
3214 * @v_opcode: opcodes for VF-PF communication
3215 * @v_retval: return error code
3216 * @msg: pointer to the msg buffer
3217 * @msglen: msg length
3218 * @cmd_details: pointer to command details
3222 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3223 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3224 struct i40e_asq_cmd_details *cmd_details)
3226 struct i40e_aq_desc desc;
3227 struct i40e_aqc_pf_vf_message *cmd =
3228 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3229 enum i40e_status_code status;
3231 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3232 cmd->id = CPU_TO_LE32(vfid);
3233 desc.cookie_high = CPU_TO_LE32(v_opcode);
3234 desc.cookie_low = CPU_TO_LE32(v_retval);
3235 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3237 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3239 if (msglen > I40E_AQ_LARGE_BUF)
3240 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3241 desc.datalen = CPU_TO_LE16(msglen);
3243 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3249 * i40e_aq_debug_read_register
3250 * @hw: pointer to the hw struct
3251 * @reg_addr: register address
3252 * @reg_val: register value
3253 * @cmd_details: pointer to command details structure or NULL
3255 * Read the register using the admin queue commands
3257 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3258 u32 reg_addr, u64 *reg_val,
3259 struct i40e_asq_cmd_details *cmd_details)
3261 struct i40e_aq_desc desc;
3262 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3263 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3264 enum i40e_status_code status;
3266 if (reg_val == NULL)
3267 return I40E_ERR_PARAM;
3269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3271 cmd_resp->address = CPU_TO_LE32(reg_addr);
3273 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3275 if (status == I40E_SUCCESS) {
3276 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3277 (u64)LE32_TO_CPU(cmd_resp->value_low);
3284 * i40e_aq_debug_write_register
3285 * @hw: pointer to the hw struct
3286 * @reg_addr: register address
3287 * @reg_val: register value
3288 * @cmd_details: pointer to command details structure or NULL
3290 * Write to a register using the admin queue commands
3292 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3293 u32 reg_addr, u64 reg_val,
3294 struct i40e_asq_cmd_details *cmd_details)
3296 struct i40e_aq_desc desc;
3297 struct i40e_aqc_debug_reg_read_write *cmd =
3298 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3299 enum i40e_status_code status;
3301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3303 cmd->address = CPU_TO_LE32(reg_addr);
3304 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3305 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3307 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3313 * i40e_aq_request_resource
3314 * @hw: pointer to the hw struct
3315 * @resource: resource id
3316 * @access: access type
3317 * @sdp_number: resource number
3318 * @timeout: the maximum time in ms that the driver may hold the resource
3319 * @cmd_details: pointer to command details structure or NULL
3321 * requests common resource using the admin queue commands
3323 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3324 enum i40e_aq_resources_ids resource,
3325 enum i40e_aq_resource_access_type access,
3326 u8 sdp_number, u64 *timeout,
3327 struct i40e_asq_cmd_details *cmd_details)
3329 struct i40e_aq_desc desc;
3330 struct i40e_aqc_request_resource *cmd_resp =
3331 (struct i40e_aqc_request_resource *)&desc.params.raw;
3332 enum i40e_status_code status;
3334 DEBUGFUNC("i40e_aq_request_resource");
3336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3338 cmd_resp->resource_id = CPU_TO_LE16(resource);
3339 cmd_resp->access_type = CPU_TO_LE16(access);
3340 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3342 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3343 /* The completion specifies the maximum time in ms that the driver
3344 * may hold the resource in the Timeout field.
3345 * If the resource is held by someone else, the command completes with
3346 * busy return value and the timeout field indicates the maximum time
3347 * the current owner of the resource has to free it.
3349 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3350 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3356 * i40e_aq_release_resource
3357 * @hw: pointer to the hw struct
3358 * @resource: resource id
3359 * @sdp_number: resource number
3360 * @cmd_details: pointer to command details structure or NULL
3362 * release common resource using the admin queue commands
3364 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3365 enum i40e_aq_resources_ids resource,
3367 struct i40e_asq_cmd_details *cmd_details)
3369 struct i40e_aq_desc desc;
3370 struct i40e_aqc_request_resource *cmd =
3371 (struct i40e_aqc_request_resource *)&desc.params.raw;
3372 enum i40e_status_code status;
3374 DEBUGFUNC("i40e_aq_release_resource");
3376 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3378 cmd->resource_id = CPU_TO_LE16(resource);
3379 cmd->resource_number = CPU_TO_LE32(sdp_number);
3381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3388 * @hw: pointer to the hw struct
3389 * @module_pointer: module pointer location in words from the NVM beginning
3390 * @offset: byte offset from the module beginning
3391 * @length: length of the section to be read (in bytes from the offset)
3392 * @data: command buffer (size [bytes] = length)
3393 * @last_command: tells if this is the last command in a series
3394 * @cmd_details: pointer to command details structure or NULL
3396 * Read the NVM using the admin queue commands
3398 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3399 u32 offset, u16 length, void *data,
3401 struct i40e_asq_cmd_details *cmd_details)
3403 struct i40e_aq_desc desc;
3404 struct i40e_aqc_nvm_update *cmd =
3405 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3406 enum i40e_status_code status;
3408 DEBUGFUNC("i40e_aq_read_nvm");
3410 /* In offset the highest byte must be zeroed. */
3411 if (offset & 0xFF000000) {
3412 status = I40E_ERR_PARAM;
3413 goto i40e_aq_read_nvm_exit;
3416 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3418 /* If this is the last command in a series, set the proper flag. */
3420 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3421 cmd->module_pointer = module_pointer;
3422 cmd->offset = CPU_TO_LE32(offset);
3423 cmd->length = CPU_TO_LE16(length);
3425 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3426 if (length > I40E_AQ_LARGE_BUF)
3427 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3429 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3431 i40e_aq_read_nvm_exit:
3436 * i40e_aq_read_nvm_config - read an nvm config block
3437 * @hw: pointer to the hw struct
3438 * @cmd_flags: NVM access admin command bits
3439 * @field_id: field or feature id
3440 * @data: buffer for result
3441 * @buf_size: buffer size
3442 * @element_count: pointer to count of elements read by FW
3443 * @cmd_details: pointer to command details structure or NULL
3445 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3446 u8 cmd_flags, u32 field_id, void *data,
3447 u16 buf_size, u16 *element_count,
3448 struct i40e_asq_cmd_details *cmd_details)
3450 struct i40e_aq_desc desc;
3451 struct i40e_aqc_nvm_config_read *cmd =
3452 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3453 enum i40e_status_code status;
3455 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3456 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3457 if (buf_size > I40E_AQ_LARGE_BUF)
3458 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3460 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3461 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3462 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3463 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3465 cmd->element_id_msw = 0;
3467 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3469 if (!status && element_count)
3470 *element_count = LE16_TO_CPU(cmd->element_count);
3476 * i40e_aq_write_nvm_config - write an nvm config block
3477 * @hw: pointer to the hw struct
3478 * @cmd_flags: NVM access admin command bits
3479 * @data: buffer for result
3480 * @buf_size: buffer size
3481 * @element_count: count of elements to be written
3482 * @cmd_details: pointer to command details structure or NULL
3484 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3485 u8 cmd_flags, void *data, u16 buf_size,
3487 struct i40e_asq_cmd_details *cmd_details)
3489 struct i40e_aq_desc desc;
3490 struct i40e_aqc_nvm_config_write *cmd =
3491 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3492 enum i40e_status_code status;
3494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3495 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3496 if (buf_size > I40E_AQ_LARGE_BUF)
3497 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3499 cmd->element_count = CPU_TO_LE16(element_count);
3500 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3501 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3507 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3508 * @hw: pointer to the hw struct
3509 * @cmd_details: pointer to command details structure or NULL
3511 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3512 void *buff, u16 buff_size,
3513 struct i40e_asq_cmd_details *cmd_details)
3515 struct i40e_aq_desc desc;
3516 enum i40e_status_code status;
3518 UNREFERENCED_2PARAMETER(buff, buff_size);
3520 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3521 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3522 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3523 status = I40E_ERR_NOT_IMPLEMENTED;
3530 * @hw: pointer to the hw struct
3531 * @module_pointer: module pointer location in words from the NVM beginning
3532 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3533 * @length: length of the section to be erased (expressed in 4 KB)
3534 * @last_command: tells if this is the last command in a series
3535 * @cmd_details: pointer to command details structure or NULL
3537 * Erase the NVM sector using the admin queue commands
3539 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3540 u32 offset, u16 length, bool last_command,
3541 struct i40e_asq_cmd_details *cmd_details)
3543 struct i40e_aq_desc desc;
3544 struct i40e_aqc_nvm_update *cmd =
3545 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3546 enum i40e_status_code status;
3548 DEBUGFUNC("i40e_aq_erase_nvm");
3550 /* In offset the highest byte must be zeroed. */
3551 if (offset & 0xFF000000) {
3552 status = I40E_ERR_PARAM;
3553 goto i40e_aq_erase_nvm_exit;
3556 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3558 /* If this is the last command in a series, set the proper flag. */
3560 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3561 cmd->module_pointer = module_pointer;
3562 cmd->offset = CPU_TO_LE32(offset);
3563 cmd->length = CPU_TO_LE16(length);
3565 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3567 i40e_aq_erase_nvm_exit:
3572 * i40e_parse_discover_capabilities
3573 * @hw: pointer to the hw struct
3574 * @buff: pointer to a buffer containing device/function capability records
3575 * @cap_count: number of capability records in the list
3576 * @list_type_opc: type of capabilities list to parse
3578 * Parse the device/function capabilities list.
3580 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3582 enum i40e_admin_queue_opc list_type_opc)
3584 struct i40e_aqc_list_capabilities_element_resp *cap;
3585 u32 valid_functions, num_functions;
3586 u32 number, logical_id, phys_id;
3587 struct i40e_hw_capabilities *p;
3592 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3594 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3595 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3596 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3597 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3601 for (i = 0; i < cap_count; i++, cap++) {
3602 id = LE16_TO_CPU(cap->id);
3603 number = LE32_TO_CPU(cap->number);
3604 logical_id = LE32_TO_CPU(cap->logical_id);
3605 phys_id = LE32_TO_CPU(cap->phys_id);
3606 major_rev = cap->major_rev;
3609 case I40E_AQ_CAP_ID_SWITCH_MODE:
3610 p->switch_mode = number;
3611 i40e_debug(hw, I40E_DEBUG_INIT,
3612 "HW Capability: Switch mode = %d\n",
3615 case I40E_AQ_CAP_ID_MNG_MODE:
3616 p->management_mode = number;
3617 if (major_rev > 1) {
3618 p->mng_protocols_over_mctp = logical_id;
3619 i40e_debug(hw, I40E_DEBUG_INIT,
3620 "HW Capability: Protocols over MCTP = %d\n",
3621 p->mng_protocols_over_mctp);
3623 p->mng_protocols_over_mctp = 0;
3625 i40e_debug(hw, I40E_DEBUG_INIT,
3626 "HW Capability: Management Mode = %d\n",
3627 p->management_mode);
3629 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3630 p->npar_enable = number;
3631 i40e_debug(hw, I40E_DEBUG_INIT,
3632 "HW Capability: NPAR enable = %d\n",
3635 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3637 i40e_debug(hw, I40E_DEBUG_INIT,
3638 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3640 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3641 p->valid_functions = number;
3642 i40e_debug(hw, I40E_DEBUG_INIT,
3643 "HW Capability: Valid Functions = %d\n",
3644 p->valid_functions);
3646 case I40E_AQ_CAP_ID_SRIOV:
3648 p->sr_iov_1_1 = true;
3649 i40e_debug(hw, I40E_DEBUG_INIT,
3650 "HW Capability: SR-IOV = %d\n",
3653 case I40E_AQ_CAP_ID_VF:
3654 p->num_vfs = number;
3655 p->vf_base_id = logical_id;
3656 i40e_debug(hw, I40E_DEBUG_INIT,
3657 "HW Capability: VF count = %d\n",
3659 i40e_debug(hw, I40E_DEBUG_INIT,
3660 "HW Capability: VF base_id = %d\n",
3663 case I40E_AQ_CAP_ID_VMDQ:
3666 i40e_debug(hw, I40E_DEBUG_INIT,
3667 "HW Capability: VMDQ = %d\n", p->vmdq);
3669 case I40E_AQ_CAP_ID_8021QBG:
3671 p->evb_802_1_qbg = true;
3672 i40e_debug(hw, I40E_DEBUG_INIT,
3673 "HW Capability: 802.1Qbg = %d\n", number);
3675 case I40E_AQ_CAP_ID_8021QBR:
3677 p->evb_802_1_qbh = true;
3678 i40e_debug(hw, I40E_DEBUG_INIT,
3679 "HW Capability: 802.1Qbh = %d\n", number);
3681 case I40E_AQ_CAP_ID_VSI:
3682 p->num_vsis = number;
3683 i40e_debug(hw, I40E_DEBUG_INIT,
3684 "HW Capability: VSI count = %d\n",
3687 case I40E_AQ_CAP_ID_DCB:
3690 p->enabled_tcmap = logical_id;
3693 i40e_debug(hw, I40E_DEBUG_INIT,
3694 "HW Capability: DCB = %d\n", p->dcb);
3695 i40e_debug(hw, I40E_DEBUG_INIT,
3696 "HW Capability: TC Mapping = %d\n",
3698 i40e_debug(hw, I40E_DEBUG_INIT,
3699 "HW Capability: TC Max = %d\n", p->maxtc);
3701 case I40E_AQ_CAP_ID_FCOE:
3704 i40e_debug(hw, I40E_DEBUG_INIT,
3705 "HW Capability: FCOE = %d\n", p->fcoe);
3707 case I40E_AQ_CAP_ID_ISCSI:
3710 i40e_debug(hw, I40E_DEBUG_INIT,
3711 "HW Capability: iSCSI = %d\n", p->iscsi);
3713 case I40E_AQ_CAP_ID_RSS:
3715 p->rss_table_size = number;
3716 p->rss_table_entry_width = logical_id;
3717 i40e_debug(hw, I40E_DEBUG_INIT,
3718 "HW Capability: RSS = %d\n", p->rss);
3719 i40e_debug(hw, I40E_DEBUG_INIT,
3720 "HW Capability: RSS table size = %d\n",
3722 i40e_debug(hw, I40E_DEBUG_INIT,
3723 "HW Capability: RSS table width = %d\n",
3724 p->rss_table_entry_width);
3726 case I40E_AQ_CAP_ID_RXQ:
3727 p->num_rx_qp = number;
3728 p->base_queue = phys_id;
3729 i40e_debug(hw, I40E_DEBUG_INIT,
3730 "HW Capability: Rx QP = %d\n", number);
3731 i40e_debug(hw, I40E_DEBUG_INIT,
3732 "HW Capability: base_queue = %d\n",
3735 case I40E_AQ_CAP_ID_TXQ:
3736 p->num_tx_qp = number;
3737 p->base_queue = phys_id;
3738 i40e_debug(hw, I40E_DEBUG_INIT,
3739 "HW Capability: Tx QP = %d\n", number);
3740 i40e_debug(hw, I40E_DEBUG_INIT,
3741 "HW Capability: base_queue = %d\n",
3744 case I40E_AQ_CAP_ID_MSIX:
3745 p->num_msix_vectors = number;
3746 i40e_debug(hw, I40E_DEBUG_INIT,
3747 "HW Capability: MSIX vector count = %d\n",
3748 p->num_msix_vectors);
3750 case I40E_AQ_CAP_ID_VF_MSIX:
3751 p->num_msix_vectors_vf = number;
3752 i40e_debug(hw, I40E_DEBUG_INIT,
3753 "HW Capability: MSIX VF vector count = %d\n",
3754 p->num_msix_vectors_vf);
3756 case I40E_AQ_CAP_ID_FLEX10:
3757 if (major_rev == 1) {
3759 p->flex10_enable = true;
3760 p->flex10_capable = true;
3763 /* Capability revision >= 2 */
3765 p->flex10_enable = true;
3767 p->flex10_capable = true;
3769 p->flex10_mode = logical_id;
3770 p->flex10_status = phys_id;
3771 i40e_debug(hw, I40E_DEBUG_INIT,
3772 "HW Capability: Flex10 mode = %d\n",
3774 i40e_debug(hw, I40E_DEBUG_INIT,
3775 "HW Capability: Flex10 status = %d\n",
3778 case I40E_AQ_CAP_ID_CEM:
3781 i40e_debug(hw, I40E_DEBUG_INIT,
3782 "HW Capability: CEM = %d\n", p->mgmt_cem);
3784 case I40E_AQ_CAP_ID_IWARP:
3787 i40e_debug(hw, I40E_DEBUG_INIT,
3788 "HW Capability: iWARP = %d\n", p->iwarp);
3790 case I40E_AQ_CAP_ID_LED:
3791 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3792 p->led[phys_id] = true;
3793 i40e_debug(hw, I40E_DEBUG_INIT,
3794 "HW Capability: LED - PIN %d\n", phys_id);
3796 case I40E_AQ_CAP_ID_SDP:
3797 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3798 p->sdp[phys_id] = true;
3799 i40e_debug(hw, I40E_DEBUG_INIT,
3800 "HW Capability: SDP - PIN %d\n", phys_id);
3802 case I40E_AQ_CAP_ID_MDIO:
3804 p->mdio_port_num = phys_id;
3805 p->mdio_port_mode = logical_id;
3807 i40e_debug(hw, I40E_DEBUG_INIT,
3808 "HW Capability: MDIO port number = %d\n",
3810 i40e_debug(hw, I40E_DEBUG_INIT,
3811 "HW Capability: MDIO port mode = %d\n",
3814 case I40E_AQ_CAP_ID_1588:
3816 p->ieee_1588 = true;
3817 i40e_debug(hw, I40E_DEBUG_INIT,
3818 "HW Capability: IEEE 1588 = %d\n",
3821 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3823 p->fd_filters_guaranteed = number;
3824 p->fd_filters_best_effort = logical_id;
3825 i40e_debug(hw, I40E_DEBUG_INIT,
3826 "HW Capability: Flow Director = 1\n");
3827 i40e_debug(hw, I40E_DEBUG_INIT,
3828 "HW Capability: Guaranteed FD filters = %d\n",
3829 p->fd_filters_guaranteed);
3831 case I40E_AQ_CAP_ID_WSR_PROT:
3832 p->wr_csr_prot = (u64)number;
3833 p->wr_csr_prot |= (u64)logical_id << 32;
3834 i40e_debug(hw, I40E_DEBUG_INIT,
3835 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3836 (p->wr_csr_prot & 0xffff));
3838 case I40E_AQ_CAP_ID_NVM_MGMT:
3839 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3840 p->sec_rev_disabled = true;
3841 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3842 p->update_disabled = true;
3845 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3846 hw->num_wol_proxy_filters = (u16)number;
3847 hw->wol_proxy_vsi_seid = (u16)logical_id;
3848 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3849 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3850 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3852 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3853 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3854 i40e_debug(hw, I40E_DEBUG_INIT,
3855 "HW Capability: WOL proxy filters = %d\n",
3856 hw->num_wol_proxy_filters);
3865 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3867 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3870 /* count the enabled ports (aka the "not disabled" ports) */
3872 for (i = 0; i < 4; i++) {
3873 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3876 /* use AQ read to get the physical register offset instead
3877 * of the port relative offset
3879 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3880 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3884 valid_functions = p->valid_functions;
3886 while (valid_functions) {
3887 if (valid_functions & 1)
3889 valid_functions >>= 1;
3892 /* partition id is 1-based, and functions are evenly spread
3893 * across the ports as partitions
3895 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3896 hw->num_partitions = num_functions / hw->num_ports;
3898 /* additional HW specific goodies that might
3899 * someday be HW version specific
3901 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3905 * i40e_aq_discover_capabilities
3906 * @hw: pointer to the hw struct
3907 * @buff: a virtual buffer to hold the capabilities
3908 * @buff_size: Size of the virtual buffer
3909 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3910 * @list_type_opc: capabilities type to discover - pass in the command opcode
3911 * @cmd_details: pointer to command details structure or NULL
3913 * Get the device capabilities descriptions from the firmware
3915 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3916 void *buff, u16 buff_size, u16 *data_size,
3917 enum i40e_admin_queue_opc list_type_opc,
3918 struct i40e_asq_cmd_details *cmd_details)
3920 struct i40e_aqc_list_capabilites *cmd;
3921 struct i40e_aq_desc desc;
3922 enum i40e_status_code status = I40E_SUCCESS;
3924 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3926 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3927 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3928 status = I40E_ERR_PARAM;
3932 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3934 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3935 if (buff_size > I40E_AQ_LARGE_BUF)
3936 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3938 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3939 *data_size = LE16_TO_CPU(desc.datalen);
3944 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3952 * i40e_aq_update_nvm
3953 * @hw: pointer to the hw struct
3954 * @module_pointer: module pointer location in words from the NVM beginning
3955 * @offset: byte offset from the module beginning
3956 * @length: length of the section to be written (in bytes from the offset)
3957 * @data: command buffer (size [bytes] = length)
3958 * @last_command: tells if this is the last command in a series
3959 * @cmd_details: pointer to command details structure or NULL
3961 * Update the NVM using the admin queue commands
3963 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3964 u32 offset, u16 length, void *data,
3966 struct i40e_asq_cmd_details *cmd_details)
3968 struct i40e_aq_desc desc;
3969 struct i40e_aqc_nvm_update *cmd =
3970 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3971 enum i40e_status_code status;
3973 DEBUGFUNC("i40e_aq_update_nvm");
3975 /* In offset the highest byte must be zeroed. */
3976 if (offset & 0xFF000000) {
3977 status = I40E_ERR_PARAM;
3978 goto i40e_aq_update_nvm_exit;
3981 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3983 /* If this is the last command in a series, set the proper flag. */
3985 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3986 cmd->module_pointer = module_pointer;
3987 cmd->offset = CPU_TO_LE32(offset);
3988 cmd->length = CPU_TO_LE16(length);
3990 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3991 if (length > I40E_AQ_LARGE_BUF)
3992 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3994 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3996 i40e_aq_update_nvm_exit:
4001 * i40e_aq_get_lldp_mib
4002 * @hw: pointer to the hw struct
4003 * @bridge_type: type of bridge requested
4004 * @mib_type: Local, Remote or both Local and Remote MIBs
4005 * @buff: pointer to a user supplied buffer to store the MIB block
4006 * @buff_size: size of the buffer (in bytes)
4007 * @local_len : length of the returned Local LLDP MIB
4008 * @remote_len: length of the returned Remote LLDP MIB
4009 * @cmd_details: pointer to command details structure or NULL
4011 * Requests the complete LLDP MIB (entire packet).
4013 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4014 u8 mib_type, void *buff, u16 buff_size,
4015 u16 *local_len, u16 *remote_len,
4016 struct i40e_asq_cmd_details *cmd_details)
4018 struct i40e_aq_desc desc;
4019 struct i40e_aqc_lldp_get_mib *cmd =
4020 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4021 struct i40e_aqc_lldp_get_mib *resp =
4022 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4023 enum i40e_status_code status;
4025 if (buff_size == 0 || !buff)
4026 return I40E_ERR_PARAM;
4028 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4029 /* Indirect Command */
4030 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4032 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4033 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4034 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4036 desc.datalen = CPU_TO_LE16(buff_size);
4038 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4039 if (buff_size > I40E_AQ_LARGE_BUF)
4040 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4042 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4044 if (local_len != NULL)
4045 *local_len = LE16_TO_CPU(resp->local_len);
4046 if (remote_len != NULL)
4047 *remote_len = LE16_TO_CPU(resp->remote_len);
4054 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4055 * @hw: pointer to the hw struct
4056 * @mib_type: Local, Remote or both Local and Remote MIBs
4057 * @buff: pointer to a user supplied buffer to store the MIB block
4058 * @buff_size: size of the buffer (in bytes)
4059 * @cmd_details: pointer to command details structure or NULL
4063 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4064 u8 mib_type, void *buff, u16 buff_size,
4065 struct i40e_asq_cmd_details *cmd_details)
4067 struct i40e_aq_desc desc;
4068 struct i40e_aqc_lldp_set_local_mib *cmd =
4069 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4070 enum i40e_status_code status;
4072 if (buff_size == 0 || !buff)
4073 return I40E_ERR_PARAM;
4075 i40e_fill_default_direct_cmd_desc(&desc,
4076 i40e_aqc_opc_lldp_set_local_mib);
4077 /* Indirect Command */
4078 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4079 if (buff_size > I40E_AQ_LARGE_BUF)
4080 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4081 desc.datalen = CPU_TO_LE16(buff_size);
4083 cmd->type = mib_type;
4084 cmd->length = CPU_TO_LE16(buff_size);
4085 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4086 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4088 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4093 * i40e_aq_cfg_lldp_mib_change_event
4094 * @hw: pointer to the hw struct
4095 * @enable_update: Enable or Disable event posting
4096 * @cmd_details: pointer to command details structure or NULL
4098 * Enable or Disable posting of an event on ARQ when LLDP MIB
4099 * associated with the interface changes
4101 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4103 struct i40e_asq_cmd_details *cmd_details)
4105 struct i40e_aq_desc desc;
4106 struct i40e_aqc_lldp_update_mib *cmd =
4107 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4108 enum i40e_status_code status;
4110 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4113 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4115 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4121 * i40e_aq_add_lldp_tlv
4122 * @hw: pointer to the hw struct
4123 * @bridge_type: type of bridge
4124 * @buff: buffer with TLV to add
4125 * @buff_size: length of the buffer
4126 * @tlv_len: length of the TLV to be added
4127 * @mib_len: length of the LLDP MIB returned in response
4128 * @cmd_details: pointer to command details structure or NULL
4130 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4131 * it is responsibility of the caller to make sure that the TLV is not
4132 * already present in the LLDPDU.
4133 * In return firmware will write the complete LLDP MIB with the newly
4134 * added TLV in the response buffer.
4136 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4137 void *buff, u16 buff_size, u16 tlv_len,
4139 struct i40e_asq_cmd_details *cmd_details)
4141 struct i40e_aq_desc desc;
4142 struct i40e_aqc_lldp_add_tlv *cmd =
4143 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4144 enum i40e_status_code status;
4146 if (buff_size == 0 || !buff || tlv_len == 0)
4147 return I40E_ERR_PARAM;
4149 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4151 /* Indirect Command */
4152 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4153 if (buff_size > I40E_AQ_LARGE_BUF)
4154 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4155 desc.datalen = CPU_TO_LE16(buff_size);
4157 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4158 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4159 cmd->len = CPU_TO_LE16(tlv_len);
4161 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4163 if (mib_len != NULL)
4164 *mib_len = LE16_TO_CPU(desc.datalen);
4171 * i40e_aq_update_lldp_tlv
4172 * @hw: pointer to the hw struct
4173 * @bridge_type: type of bridge
4174 * @buff: buffer with TLV to update
4175 * @buff_size: size of the buffer holding original and updated TLVs
4176 * @old_len: Length of the Original TLV
4177 * @new_len: Length of the Updated TLV
4178 * @offset: offset of the updated TLV in the buff
4179 * @mib_len: length of the returned LLDP MIB
4180 * @cmd_details: pointer to command details structure or NULL
4182 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4183 * Firmware will place the complete LLDP MIB in response buffer with the
4186 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4187 u8 bridge_type, void *buff, u16 buff_size,
4188 u16 old_len, u16 new_len, u16 offset,
4190 struct i40e_asq_cmd_details *cmd_details)
4192 struct i40e_aq_desc desc;
4193 struct i40e_aqc_lldp_update_tlv *cmd =
4194 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4195 enum i40e_status_code status;
4197 if (buff_size == 0 || !buff || offset == 0 ||
4198 old_len == 0 || new_len == 0)
4199 return I40E_ERR_PARAM;
4201 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4203 /* Indirect Command */
4204 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4205 if (buff_size > I40E_AQ_LARGE_BUF)
4206 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4207 desc.datalen = CPU_TO_LE16(buff_size);
4209 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4210 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4211 cmd->old_len = CPU_TO_LE16(old_len);
4212 cmd->new_offset = CPU_TO_LE16(offset);
4213 cmd->new_len = CPU_TO_LE16(new_len);
4215 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4217 if (mib_len != NULL)
4218 *mib_len = LE16_TO_CPU(desc.datalen);
4225 * i40e_aq_delete_lldp_tlv
4226 * @hw: pointer to the hw struct
4227 * @bridge_type: type of bridge
4228 * @buff: pointer to a user supplied buffer that has the TLV
4229 * @buff_size: length of the buffer
4230 * @tlv_len: length of the TLV to be deleted
4231 * @mib_len: length of the returned LLDP MIB
4232 * @cmd_details: pointer to command details structure or NULL
4234 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4235 * The firmware places the entire LLDP MIB in the response buffer.
4237 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4238 u8 bridge_type, void *buff, u16 buff_size,
4239 u16 tlv_len, u16 *mib_len,
4240 struct i40e_asq_cmd_details *cmd_details)
4242 struct i40e_aq_desc desc;
4243 struct i40e_aqc_lldp_add_tlv *cmd =
4244 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4245 enum i40e_status_code status;
4247 if (buff_size == 0 || !buff)
4248 return I40E_ERR_PARAM;
4250 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4252 /* Indirect Command */
4253 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4254 if (buff_size > I40E_AQ_LARGE_BUF)
4255 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4256 desc.datalen = CPU_TO_LE16(buff_size);
4257 cmd->len = CPU_TO_LE16(tlv_len);
4258 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4259 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4261 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4263 if (mib_len != NULL)
4264 *mib_len = LE16_TO_CPU(desc.datalen);
4272 * @hw: pointer to the hw struct
4273 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4274 * @cmd_details: pointer to command details structure or NULL
4276 * Stop or Shutdown the embedded LLDP Agent
4278 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4279 struct i40e_asq_cmd_details *cmd_details)
4281 struct i40e_aq_desc desc;
4282 struct i40e_aqc_lldp_stop *cmd =
4283 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4284 enum i40e_status_code status;
4286 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4289 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4291 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4297 * i40e_aq_start_lldp
4298 * @hw: pointer to the hw struct
4299 * @cmd_details: pointer to command details structure or NULL
4301 * Start the embedded LLDP Agent on all ports.
4303 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4304 struct i40e_asq_cmd_details *cmd_details)
4306 struct i40e_aq_desc desc;
4307 struct i40e_aqc_lldp_start *cmd =
4308 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4309 enum i40e_status_code status;
4311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4313 cmd->command = I40E_AQ_LLDP_AGENT_START;
4315 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4321 * i40e_aq_get_cee_dcb_config
4322 * @hw: pointer to the hw struct
4323 * @buff: response buffer that stores CEE operational configuration
4324 * @buff_size: size of the buffer passed
4325 * @cmd_details: pointer to command details structure or NULL
4327 * Get CEE DCBX mode operational configuration from firmware
4329 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4330 void *buff, u16 buff_size,
4331 struct i40e_asq_cmd_details *cmd_details)
4333 struct i40e_aq_desc desc;
4334 enum i40e_status_code status;
4336 if (buff_size == 0 || !buff)
4337 return I40E_ERR_PARAM;
4339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4341 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4342 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4349 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4350 * @hw: pointer to the hw struct
4351 * @start_agent: True if DCBx Agent needs to be Started
4352 * False if DCBx Agent needs to be Stopped
4353 * @cmd_details: pointer to command details structure or NULL
4355 * Start/Stop the embedded dcbx Agent
4357 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4359 struct i40e_asq_cmd_details *cmd_details)
4361 struct i40e_aq_desc desc;
4362 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4363 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4365 enum i40e_status_code status;
4367 i40e_fill_default_direct_cmd_desc(&desc,
4368 i40e_aqc_opc_lldp_stop_start_spec_agent);
4371 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4373 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4379 * i40e_aq_add_udp_tunnel
4380 * @hw: pointer to the hw struct
4381 * @udp_port: the UDP port to add
4382 * @header_len: length of the tunneling header length in DWords
4383 * @protocol_index: protocol index type
4384 * @filter_index: pointer to filter index
4385 * @cmd_details: pointer to command details structure or NULL
4387 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4388 u16 udp_port, u8 protocol_index,
4390 struct i40e_asq_cmd_details *cmd_details)
4392 struct i40e_aq_desc desc;
4393 struct i40e_aqc_add_udp_tunnel *cmd =
4394 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4395 struct i40e_aqc_del_udp_tunnel_completion *resp =
4396 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4397 enum i40e_status_code status;
4399 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4401 cmd->udp_port = CPU_TO_LE16(udp_port);
4402 cmd->protocol_type = protocol_index;
4404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4406 if (!status && filter_index)
4407 *filter_index = resp->index;
4413 * i40e_aq_del_udp_tunnel
4414 * @hw: pointer to the hw struct
4415 * @index: filter index
4416 * @cmd_details: pointer to command details structure or NULL
4418 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4419 struct i40e_asq_cmd_details *cmd_details)
4421 struct i40e_aq_desc desc;
4422 struct i40e_aqc_remove_udp_tunnel *cmd =
4423 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4424 enum i40e_status_code status;
4426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4430 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4436 * i40e_aq_get_switch_resource_alloc (0x0204)
4437 * @hw: pointer to the hw struct
4438 * @num_entries: pointer to u8 to store the number of resource entries returned
4439 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4440 * to store the resource information for all resource types. Each
4441 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4442 * @count: size, in bytes, of the buffer provided
4443 * @cmd_details: pointer to command details structure or NULL
4445 * Query the resources allocated to a function.
4447 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4449 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4451 struct i40e_asq_cmd_details *cmd_details)
4453 struct i40e_aq_desc desc;
4454 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4455 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4456 enum i40e_status_code status;
4457 u16 length = count * sizeof(*buf);
4459 i40e_fill_default_direct_cmd_desc(&desc,
4460 i40e_aqc_opc_get_switch_resource_alloc);
4462 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4463 if (length > I40E_AQ_LARGE_BUF)
4464 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4466 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4468 if (!status && num_entries)
4469 *num_entries = cmd_resp->num_entries;
4475 * i40e_aq_delete_element - Delete switch element
4476 * @hw: pointer to the hw struct
4477 * @seid: the SEID to delete from the switch
4478 * @cmd_details: pointer to command details structure or NULL
4480 * This deletes a switch element from the switch.
4482 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4483 struct i40e_asq_cmd_details *cmd_details)
4485 struct i40e_aq_desc desc;
4486 struct i40e_aqc_switch_seid *cmd =
4487 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4488 enum i40e_status_code status;
4491 return I40E_ERR_PARAM;
4493 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4495 cmd->seid = CPU_TO_LE16(seid);
4497 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4503 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4504 * @hw: pointer to the hw struct
4505 * @flags: component flags
4506 * @mac_seid: uplink seid (MAC SEID)
4507 * @vsi_seid: connected vsi seid
4508 * @ret_seid: seid of create pv component
4510 * This instantiates an i40e port virtualizer with specified flags.
4511 * Depending on specified flags the port virtualizer can act as a
4512 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4514 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4515 u16 mac_seid, u16 vsi_seid,
4518 struct i40e_aq_desc desc;
4519 struct i40e_aqc_add_update_pv *cmd =
4520 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4521 struct i40e_aqc_add_update_pv_completion *resp =
4522 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4523 enum i40e_status_code status;
4526 return I40E_ERR_PARAM;
4528 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4529 cmd->command_flags = CPU_TO_LE16(flags);
4530 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4531 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4533 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4534 if (!status && ret_seid)
4535 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4541 * i40e_aq_add_tag - Add an S/E-tag
4542 * @hw: pointer to the hw struct
4543 * @direct_to_queue: should s-tag direct flow to a specific queue
4544 * @vsi_seid: VSI SEID to use this tag
4545 * @tag: value of the tag
4546 * @queue_num: queue number, only valid is direct_to_queue is true
4547 * @tags_used: return value, number of tags in use by this PF
4548 * @tags_free: return value, number of unallocated tags
4549 * @cmd_details: pointer to command details structure or NULL
4551 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4552 * the number of tags allocated by the PF, and the number of unallocated
4555 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4556 u16 vsi_seid, u16 tag, u16 queue_num,
4557 u16 *tags_used, u16 *tags_free,
4558 struct i40e_asq_cmd_details *cmd_details)
4560 struct i40e_aq_desc desc;
4561 struct i40e_aqc_add_tag *cmd =
4562 (struct i40e_aqc_add_tag *)&desc.params.raw;
4563 struct i40e_aqc_add_remove_tag_completion *resp =
4564 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4565 enum i40e_status_code status;
4568 return I40E_ERR_PARAM;
4570 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4572 cmd->seid = CPU_TO_LE16(vsi_seid);
4573 cmd->tag = CPU_TO_LE16(tag);
4574 if (direct_to_queue) {
4575 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4576 cmd->queue_number = CPU_TO_LE16(queue_num);
4579 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4582 if (tags_used != NULL)
4583 *tags_used = LE16_TO_CPU(resp->tags_used);
4584 if (tags_free != NULL)
4585 *tags_free = LE16_TO_CPU(resp->tags_free);
4592 * i40e_aq_remove_tag - Remove an S- or E-tag
4593 * @hw: pointer to the hw struct
4594 * @vsi_seid: VSI SEID this tag is associated with
4595 * @tag: value of the S-tag to delete
4596 * @tags_used: return value, number of tags in use by this PF
4597 * @tags_free: return value, number of unallocated tags
4598 * @cmd_details: pointer to command details structure or NULL
4600 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4601 * the number of tags allocated by the PF, and the number of unallocated
4604 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4605 u16 tag, u16 *tags_used, u16 *tags_free,
4606 struct i40e_asq_cmd_details *cmd_details)
4608 struct i40e_aq_desc desc;
4609 struct i40e_aqc_remove_tag *cmd =
4610 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4611 struct i40e_aqc_add_remove_tag_completion *resp =
4612 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4613 enum i40e_status_code status;
4616 return I40E_ERR_PARAM;
4618 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4620 cmd->seid = CPU_TO_LE16(vsi_seid);
4621 cmd->tag = CPU_TO_LE16(tag);
4623 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4626 if (tags_used != NULL)
4627 *tags_used = LE16_TO_CPU(resp->tags_used);
4628 if (tags_free != NULL)
4629 *tags_free = LE16_TO_CPU(resp->tags_free);
4636 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4637 * @hw: pointer to the hw struct
4638 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4639 * @etag: value of E-tag to add
4640 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4641 * @buf: address of indirect buffer
4642 * @tags_used: return value, number of E-tags in use by this port
4643 * @tags_free: return value, number of unallocated M-tags
4644 * @cmd_details: pointer to command details structure or NULL
4646 * This associates a multicast E-tag to a port virtualizer. It will return
4647 * the number of tags allocated by the PF, and the number of unallocated
4650 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4651 * num_tags_in_buf long.
4653 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4654 u16 etag, u8 num_tags_in_buf, void *buf,
4655 u16 *tags_used, u16 *tags_free,
4656 struct i40e_asq_cmd_details *cmd_details)
4658 struct i40e_aq_desc desc;
4659 struct i40e_aqc_add_remove_mcast_etag *cmd =
4660 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4661 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4662 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4663 enum i40e_status_code status;
4664 u16 length = sizeof(u16) * num_tags_in_buf;
4666 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4667 return I40E_ERR_PARAM;
4669 i40e_fill_default_direct_cmd_desc(&desc,
4670 i40e_aqc_opc_add_multicast_etag);
4672 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4673 cmd->etag = CPU_TO_LE16(etag);
4674 cmd->num_unicast_etags = num_tags_in_buf;
4676 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4677 if (length > I40E_AQ_LARGE_BUF)
4678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4680 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4683 if (tags_used != NULL)
4684 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4685 if (tags_free != NULL)
4686 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4693 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4694 * @hw: pointer to the hw struct
4695 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4696 * @etag: value of the E-tag to remove
4697 * @tags_used: return value, number of tags in use by this port
4698 * @tags_free: return value, number of unallocated tags
4699 * @cmd_details: pointer to command details structure or NULL
4701 * This deletes an E-tag from the port virtualizer. It will return
4702 * the number of tags allocated by the port, and the number of unallocated
4705 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4706 u16 etag, u16 *tags_used, u16 *tags_free,
4707 struct i40e_asq_cmd_details *cmd_details)
4709 struct i40e_aq_desc desc;
4710 struct i40e_aqc_add_remove_mcast_etag *cmd =
4711 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4712 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4713 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4714 enum i40e_status_code status;
4718 return I40E_ERR_PARAM;
4720 i40e_fill_default_direct_cmd_desc(&desc,
4721 i40e_aqc_opc_remove_multicast_etag);
4723 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4724 cmd->etag = CPU_TO_LE16(etag);
4726 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4729 if (tags_used != NULL)
4730 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4731 if (tags_free != NULL)
4732 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4739 * i40e_aq_update_tag - Update an S/E-tag
4740 * @hw: pointer to the hw struct
4741 * @vsi_seid: VSI SEID using this S-tag
4742 * @old_tag: old tag value
4743 * @new_tag: new tag value
4744 * @tags_used: return value, number of tags in use by this PF
4745 * @tags_free: return value, number of unallocated tags
4746 * @cmd_details: pointer to command details structure or NULL
4748 * This updates the value of the tag currently attached to this VSI
4749 * in the switch complex. It will return the number of tags allocated
4750 * by the PF, and the number of unallocated tags available.
4752 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4753 u16 old_tag, u16 new_tag, u16 *tags_used,
4755 struct i40e_asq_cmd_details *cmd_details)
4757 struct i40e_aq_desc desc;
4758 struct i40e_aqc_update_tag *cmd =
4759 (struct i40e_aqc_update_tag *)&desc.params.raw;
4760 struct i40e_aqc_update_tag_completion *resp =
4761 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4762 enum i40e_status_code status;
4765 return I40E_ERR_PARAM;
4767 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4769 cmd->seid = CPU_TO_LE16(vsi_seid);
4770 cmd->old_tag = CPU_TO_LE16(old_tag);
4771 cmd->new_tag = CPU_TO_LE16(new_tag);
4773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4776 if (tags_used != NULL)
4777 *tags_used = LE16_TO_CPU(resp->tags_used);
4778 if (tags_free != NULL)
4779 *tags_free = LE16_TO_CPU(resp->tags_free);
4786 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4787 * @hw: pointer to the hw struct
4788 * @tcmap: TC map for request/release any ignore PFC condition
4789 * @request: request or release ignore PFC condition
4790 * @tcmap_ret: return TCs for which PFC is currently ignored
4791 * @cmd_details: pointer to command details structure or NULL
4793 * This sends out request/release to ignore PFC condition for a TC.
4794 * It will return the TCs for which PFC is currently ignored.
4796 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4797 bool request, u8 *tcmap_ret,
4798 struct i40e_asq_cmd_details *cmd_details)
4800 struct i40e_aq_desc desc;
4801 struct i40e_aqc_pfc_ignore *cmd_resp =
4802 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4803 enum i40e_status_code status;
4805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4808 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4810 cmd_resp->tc_bitmap = tcmap;
4812 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4815 if (tcmap_ret != NULL)
4816 *tcmap_ret = cmd_resp->tc_bitmap;
4823 * i40e_aq_dcb_updated - DCB Updated Command
4824 * @hw: pointer to the hw struct
4825 * @cmd_details: pointer to command details structure or NULL
4827 * When LLDP is handled in PF this command is used by the PF
4828 * to notify EMP that a DCB setting is modified.
4829 * When LLDP is handled in EMP this command is used by the PF
4830 * to notify EMP whenever one of the following parameters get
4832 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4833 * - PCIRTT in PRTDCB_GENC.PCIRTT
4834 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4835 * EMP will return when the shared RPB settings have been
4836 * recomputed and modified. The retval field in the descriptor
4837 * will be set to 0 when RPB is modified.
4839 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4840 struct i40e_asq_cmd_details *cmd_details)
4842 struct i40e_aq_desc desc;
4843 enum i40e_status_code status;
4845 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4847 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4853 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4854 * @hw: pointer to the hw struct
4855 * @seid: defines the SEID of the switch for which the stats are requested
4856 * @vlan_id: the VLAN ID for which the statistics are requested
4857 * @stat_index: index of the statistics counters block assigned to this VLAN
4858 * @cmd_details: pointer to command details structure or NULL
4860 * XL710 supports 128 smonVlanStats counters.This command is used to
4861 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4864 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4865 u16 vlan_id, u16 *stat_index,
4866 struct i40e_asq_cmd_details *cmd_details)
4868 struct i40e_aq_desc desc;
4869 struct i40e_aqc_add_remove_statistics *cmd_resp =
4870 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4871 enum i40e_status_code status;
4873 if ((seid == 0) || (stat_index == NULL))
4874 return I40E_ERR_PARAM;
4876 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4878 cmd_resp->seid = CPU_TO_LE16(seid);
4879 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4881 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4883 if (!status && stat_index)
4884 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4890 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4891 * @hw: pointer to the hw struct
4892 * @seid: defines the SEID of the switch for which the stats are requested
4893 * @vlan_id: the VLAN ID for which the statistics are requested
4894 * @stat_index: index of the statistics counters block assigned to this VLAN
4895 * @cmd_details: pointer to command details structure or NULL
4897 * XL710 supports 128 smonVlanStats counters.This command is used to
4898 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4901 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4902 u16 vlan_id, u16 stat_index,
4903 struct i40e_asq_cmd_details *cmd_details)
4905 struct i40e_aq_desc desc;
4906 struct i40e_aqc_add_remove_statistics *cmd =
4907 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4908 enum i40e_status_code status;
4911 return I40E_ERR_PARAM;
4913 i40e_fill_default_direct_cmd_desc(&desc,
4914 i40e_aqc_opc_remove_statistics);
4916 cmd->seid = CPU_TO_LE16(seid);
4917 cmd->vlan = CPU_TO_LE16(vlan_id);
4918 cmd->stat_index = CPU_TO_LE16(stat_index);
4920 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4926 * i40e_aq_set_port_parameters - set physical port parameters.
4927 * @hw: pointer to the hw struct
4928 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4929 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4930 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4931 * @double_vlan: if set double VLAN is enabled
4932 * @cmd_details: pointer to command details structure or NULL
4934 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4935 u16 bad_frame_vsi, bool save_bad_pac,
4936 bool pad_short_pac, bool double_vlan,
4937 struct i40e_asq_cmd_details *cmd_details)
4939 struct i40e_aqc_set_port_parameters *cmd;
4940 enum i40e_status_code status;
4941 struct i40e_aq_desc desc;
4942 u16 command_flags = 0;
4944 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4946 i40e_fill_default_direct_cmd_desc(&desc,
4947 i40e_aqc_opc_set_port_parameters);
4949 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4951 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4953 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4955 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4956 cmd->command_flags = CPU_TO_LE16(command_flags);
4958 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4964 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4965 * @hw: pointer to the hw struct
4966 * @seid: seid for the physical port/switching component/vsi
4967 * @buff: Indirect buffer to hold data parameters and response
4968 * @buff_size: Indirect buffer size
4969 * @opcode: Tx scheduler AQ command opcode
4970 * @cmd_details: pointer to command details structure or NULL
4972 * Generic command handler for Tx scheduler AQ commands
4974 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4975 void *buff, u16 buff_size,
4976 enum i40e_admin_queue_opc opcode,
4977 struct i40e_asq_cmd_details *cmd_details)
4979 struct i40e_aq_desc desc;
4980 struct i40e_aqc_tx_sched_ind *cmd =
4981 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4982 enum i40e_status_code status;
4983 bool cmd_param_flag = false;
4986 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4987 case i40e_aqc_opc_configure_vsi_tc_bw:
4988 case i40e_aqc_opc_enable_switching_comp_ets:
4989 case i40e_aqc_opc_modify_switching_comp_ets:
4990 case i40e_aqc_opc_disable_switching_comp_ets:
4991 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4992 case i40e_aqc_opc_configure_switching_comp_bw_config:
4993 cmd_param_flag = true;
4995 case i40e_aqc_opc_query_vsi_bw_config:
4996 case i40e_aqc_opc_query_vsi_ets_sla_config:
4997 case i40e_aqc_opc_query_switching_comp_ets_config:
4998 case i40e_aqc_opc_query_port_ets_config:
4999 case i40e_aqc_opc_query_switching_comp_bw_config:
5000 cmd_param_flag = false;
5003 return I40E_ERR_PARAM;
5006 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5008 /* Indirect command */
5009 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5011 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5012 if (buff_size > I40E_AQ_LARGE_BUF)
5013 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5015 desc.datalen = CPU_TO_LE16(buff_size);
5017 cmd->vsi_seid = CPU_TO_LE16(seid);
5019 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5025 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5026 * @hw: pointer to the hw struct
5028 * @credit: BW limit credits (0 = disabled)
5029 * @max_credit: Max BW limit credits
5030 * @cmd_details: pointer to command details structure or NULL
5032 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5033 u16 seid, u16 credit, u8 max_credit,
5034 struct i40e_asq_cmd_details *cmd_details)
5036 struct i40e_aq_desc desc;
5037 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5038 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5039 enum i40e_status_code status;
5041 i40e_fill_default_direct_cmd_desc(&desc,
5042 i40e_aqc_opc_configure_vsi_bw_limit);
5044 cmd->vsi_seid = CPU_TO_LE16(seid);
5045 cmd->credit = CPU_TO_LE16(credit);
5046 cmd->max_credit = max_credit;
5048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5054 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5055 * @hw: pointer to the hw struct
5056 * @seid: switching component seid
5057 * @credit: BW limit credits (0 = disabled)
5058 * @max_bw: Max BW limit credits
5059 * @cmd_details: pointer to command details structure or NULL
5061 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5062 u16 seid, u16 credit, u8 max_bw,
5063 struct i40e_asq_cmd_details *cmd_details)
5065 struct i40e_aq_desc desc;
5066 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5067 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5068 enum i40e_status_code status;
5070 i40e_fill_default_direct_cmd_desc(&desc,
5071 i40e_aqc_opc_configure_switching_comp_bw_limit);
5073 cmd->seid = CPU_TO_LE16(seid);
5074 cmd->credit = CPU_TO_LE16(credit);
5075 cmd->max_bw = max_bw;
5077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5083 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5084 * @hw: pointer to the hw struct
5086 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5087 * @cmd_details: pointer to command details structure or NULL
5089 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5091 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5092 struct i40e_asq_cmd_details *cmd_details)
5094 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5095 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5100 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5101 * @hw: pointer to the hw struct
5103 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5104 * @cmd_details: pointer to command details structure or NULL
5106 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5108 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5109 struct i40e_asq_cmd_details *cmd_details)
5111 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5112 i40e_aqc_opc_configure_vsi_tc_bw,
5117 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5118 * @hw: pointer to the hw struct
5119 * @seid: seid of the switching component connected to Physical Port
5120 * @ets_data: Buffer holding ETS parameters
5121 * @cmd_details: pointer to command details structure or NULL
5123 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5125 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5126 enum i40e_admin_queue_opc opcode,
5127 struct i40e_asq_cmd_details *cmd_details)
5129 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5130 sizeof(*ets_data), opcode, cmd_details);
5134 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5135 * @hw: pointer to the hw struct
5136 * @seid: seid of the switching component
5137 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5138 * @cmd_details: pointer to command details structure or NULL
5140 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5142 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5143 struct i40e_asq_cmd_details *cmd_details)
5145 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5146 i40e_aqc_opc_configure_switching_comp_bw_config,
5151 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5152 * @hw: pointer to the hw struct
5153 * @seid: seid of the switching component
5154 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5155 * @cmd_details: pointer to command details structure or NULL
5157 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5158 struct i40e_hw *hw, u16 seid,
5159 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5160 struct i40e_asq_cmd_details *cmd_details)
5162 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5163 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5168 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5169 * @hw: pointer to the hw struct
5170 * @seid: seid of the VSI
5171 * @bw_data: Buffer to hold VSI BW configuration
5172 * @cmd_details: pointer to command details structure or NULL
5174 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5176 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5177 struct i40e_asq_cmd_details *cmd_details)
5179 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5180 i40e_aqc_opc_query_vsi_bw_config,
5185 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5186 * @hw: pointer to the hw struct
5187 * @seid: seid of the VSI
5188 * @bw_data: Buffer to hold VSI BW configuration per TC
5189 * @cmd_details: pointer to command details structure or NULL
5191 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5193 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5194 struct i40e_asq_cmd_details *cmd_details)
5196 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5197 i40e_aqc_opc_query_vsi_ets_sla_config,
5202 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5203 * @hw: pointer to the hw struct
5204 * @seid: seid of the switching component
5205 * @bw_data: Buffer to hold switching component's per TC BW config
5206 * @cmd_details: pointer to command details structure or NULL
5208 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5210 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5211 struct i40e_asq_cmd_details *cmd_details)
5213 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5214 i40e_aqc_opc_query_switching_comp_ets_config,
5219 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5220 * @hw: pointer to the hw struct
5221 * @seid: seid of the VSI or switching component connected to Physical Port
5222 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5223 * @cmd_details: pointer to command details structure or NULL
5225 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5227 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5228 struct i40e_asq_cmd_details *cmd_details)
5230 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5231 i40e_aqc_opc_query_port_ets_config,
5236 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5237 * @hw: pointer to the hw struct
5238 * @seid: seid of the switching component
5239 * @bw_data: Buffer to hold switching component's BW configuration
5240 * @cmd_details: pointer to command details structure or NULL
5242 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5244 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5245 struct i40e_asq_cmd_details *cmd_details)
5247 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5248 i40e_aqc_opc_query_switching_comp_bw_config,
5253 * i40e_validate_filter_settings
5254 * @hw: pointer to the hardware structure
5255 * @settings: Filter control settings
5257 * Check and validate the filter control settings passed.
5258 * The function checks for the valid filter/context sizes being
5259 * passed for FCoE and PE.
5261 * Returns I40E_SUCCESS if the values passed are valid and within
5262 * range else returns an error.
5264 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5265 struct i40e_filter_control_settings *settings)
5267 u32 fcoe_cntx_size, fcoe_filt_size;
5268 u32 pe_cntx_size, pe_filt_size;
5273 /* Validate FCoE settings passed */
5274 switch (settings->fcoe_filt_num) {
5275 case I40E_HASH_FILTER_SIZE_1K:
5276 case I40E_HASH_FILTER_SIZE_2K:
5277 case I40E_HASH_FILTER_SIZE_4K:
5278 case I40E_HASH_FILTER_SIZE_8K:
5279 case I40E_HASH_FILTER_SIZE_16K:
5280 case I40E_HASH_FILTER_SIZE_32K:
5281 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5282 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5285 return I40E_ERR_PARAM;
5288 switch (settings->fcoe_cntx_num) {
5289 case I40E_DMA_CNTX_SIZE_512:
5290 case I40E_DMA_CNTX_SIZE_1K:
5291 case I40E_DMA_CNTX_SIZE_2K:
5292 case I40E_DMA_CNTX_SIZE_4K:
5293 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5294 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5297 return I40E_ERR_PARAM;
5300 /* Validate PE settings passed */
5301 switch (settings->pe_filt_num) {
5302 case I40E_HASH_FILTER_SIZE_1K:
5303 case I40E_HASH_FILTER_SIZE_2K:
5304 case I40E_HASH_FILTER_SIZE_4K:
5305 case I40E_HASH_FILTER_SIZE_8K:
5306 case I40E_HASH_FILTER_SIZE_16K:
5307 case I40E_HASH_FILTER_SIZE_32K:
5308 case I40E_HASH_FILTER_SIZE_64K:
5309 case I40E_HASH_FILTER_SIZE_128K:
5310 case I40E_HASH_FILTER_SIZE_256K:
5311 case I40E_HASH_FILTER_SIZE_512K:
5312 case I40E_HASH_FILTER_SIZE_1M:
5313 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5314 pe_filt_size <<= (u32)settings->pe_filt_num;
5317 return I40E_ERR_PARAM;
5320 switch (settings->pe_cntx_num) {
5321 case I40E_DMA_CNTX_SIZE_512:
5322 case I40E_DMA_CNTX_SIZE_1K:
5323 case I40E_DMA_CNTX_SIZE_2K:
5324 case I40E_DMA_CNTX_SIZE_4K:
5325 case I40E_DMA_CNTX_SIZE_8K:
5326 case I40E_DMA_CNTX_SIZE_16K:
5327 case I40E_DMA_CNTX_SIZE_32K:
5328 case I40E_DMA_CNTX_SIZE_64K:
5329 case I40E_DMA_CNTX_SIZE_128K:
5330 case I40E_DMA_CNTX_SIZE_256K:
5331 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5332 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5335 return I40E_ERR_PARAM;
5338 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5339 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5340 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5341 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5342 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5343 return I40E_ERR_INVALID_SIZE;
5345 return I40E_SUCCESS;
5349 * i40e_set_filter_control
5350 * @hw: pointer to the hardware structure
5351 * @settings: Filter control settings
5353 * Set the Queue Filters for PE/FCoE and enable filters required
5354 * for a single PF. It is expected that these settings are programmed
5355 * at the driver initialization time.
5357 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5358 struct i40e_filter_control_settings *settings)
5360 enum i40e_status_code ret = I40E_SUCCESS;
5361 u32 hash_lut_size = 0;
5365 return I40E_ERR_PARAM;
5367 /* Validate the input settings */
5368 ret = i40e_validate_filter_settings(hw, settings);
5372 /* Read the PF Queue Filter control register */
5373 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5375 /* Program required PE hash buckets for the PF */
5376 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5377 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5378 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5379 /* Program required PE contexts for the PF */
5380 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5381 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5382 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5384 /* Program required FCoE hash buckets for the PF */
5385 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5386 val |= ((u32)settings->fcoe_filt_num <<
5387 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5388 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5389 /* Program required FCoE DDP contexts for the PF */
5390 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5391 val |= ((u32)settings->fcoe_cntx_num <<
5392 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5393 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5395 /* Program Hash LUT size for the PF */
5396 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5397 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5399 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5400 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5402 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5403 if (settings->enable_fdir)
5404 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5405 if (settings->enable_ethtype)
5406 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5407 if (settings->enable_macvlan)
5408 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5410 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5412 return I40E_SUCCESS;
5416 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5417 * @hw: pointer to the hw struct
5418 * @mac_addr: MAC address to use in the filter
5419 * @ethtype: Ethertype to use in the filter
5420 * @flags: Flags that needs to be applied to the filter
5421 * @vsi_seid: seid of the control VSI
5422 * @queue: VSI queue number to send the packet to
5423 * @is_add: Add control packet filter if True else remove
5424 * @stats: Structure to hold information on control filter counts
5425 * @cmd_details: pointer to command details structure or NULL
5427 * This command will Add or Remove control packet filter for a control VSI.
5428 * In return it will update the total number of perfect filter count in
5431 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5432 u8 *mac_addr, u16 ethtype, u16 flags,
5433 u16 vsi_seid, u16 queue, bool is_add,
5434 struct i40e_control_filter_stats *stats,
5435 struct i40e_asq_cmd_details *cmd_details)
5437 struct i40e_aq_desc desc;
5438 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5439 (struct i40e_aqc_add_remove_control_packet_filter *)
5441 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5442 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5444 enum i40e_status_code status;
5447 return I40E_ERR_PARAM;
5450 i40e_fill_default_direct_cmd_desc(&desc,
5451 i40e_aqc_opc_add_control_packet_filter);
5452 cmd->queue = CPU_TO_LE16(queue);
5454 i40e_fill_default_direct_cmd_desc(&desc,
5455 i40e_aqc_opc_remove_control_packet_filter);
5459 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5460 I40E_NONDMA_TO_NONDMA);
5462 cmd->etype = CPU_TO_LE16(ethtype);
5463 cmd->flags = CPU_TO_LE16(flags);
5464 cmd->seid = CPU_TO_LE16(vsi_seid);
5466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5468 if (!status && stats) {
5469 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5470 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5471 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5472 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5479 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5480 * @hw: pointer to the hw struct
5481 * @seid: VSI seid to add ethertype filter from
5483 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5484 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5487 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5488 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5489 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5490 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5491 enum i40e_status_code status;
5493 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5494 seid, 0, true, NULL,
5497 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5501 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5502 * @filters: list of cloud filters
5503 * @filter_count: length of list
5505 * There's an issue in the device where the Geneve VNI layout needs
5506 * to be shifted 1 byte over from the VxLAN VNI
5508 STATIC void i40e_fix_up_geneve_vni(
5509 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5512 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5515 for (i = 0; i < filter_count; i++) {
5519 tnl_type = (LE16_TO_CPU(f[i].flags) &
5520 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5521 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5522 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5523 ti = LE32_TO_CPU(f[i].tenant_id);
5524 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5530 * i40e_aq_add_cloud_filters
5531 * @hw: pointer to the hardware structure
5532 * @seid: VSI seid to add cloud filters from
5533 * @filters: Buffer which contains the filters to be added
5534 * @filter_count: number of filters contained in the buffer
5536 * Set the cloud filters for a given VSI. The contents of the
5537 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5538 * in by the caller of the function.
5541 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5543 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5546 struct i40e_aq_desc desc;
5547 struct i40e_aqc_add_remove_cloud_filters *cmd =
5548 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5549 enum i40e_status_code status;
5552 i40e_fill_default_direct_cmd_desc(&desc,
5553 i40e_aqc_opc_add_cloud_filters);
5555 buff_len = filter_count * sizeof(*filters);
5556 desc.datalen = CPU_TO_LE16(buff_len);
5557 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5558 cmd->num_filters = filter_count;
5559 cmd->seid = CPU_TO_LE16(seid);
5561 i40e_fix_up_geneve_vni(filters, filter_count);
5563 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5569 * i40e_aq_remove_cloud_filters
5570 * @hw: pointer to the hardware structure
5571 * @seid: VSI seid to remove cloud filters from
5572 * @filters: Buffer which contains the filters to be removed
5573 * @filter_count: number of filters contained in the buffer
5575 * Remove the cloud filters for a given VSI. The contents of the
5576 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5577 * in by the caller of the function.
5580 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5582 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5585 struct i40e_aq_desc desc;
5586 struct i40e_aqc_add_remove_cloud_filters *cmd =
5587 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5588 enum i40e_status_code status;
5591 i40e_fill_default_direct_cmd_desc(&desc,
5592 i40e_aqc_opc_remove_cloud_filters);
5594 buff_len = filter_count * sizeof(*filters);
5595 desc.datalen = CPU_TO_LE16(buff_len);
5596 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5597 cmd->num_filters = filter_count;
5598 cmd->seid = CPU_TO_LE16(seid);
5600 i40e_fix_up_geneve_vni(filters, filter_count);
5602 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5608 * i40e_aq_alternate_write
5609 * @hw: pointer to the hardware structure
5610 * @reg_addr0: address of first dword to be read
5611 * @reg_val0: value to be written under 'reg_addr0'
5612 * @reg_addr1: address of second dword to be read
5613 * @reg_val1: value to be written under 'reg_addr1'
5615 * Write one or two dwords to alternate structure. Fields are indicated
5616 * by 'reg_addr0' and 'reg_addr1' register numbers.
5619 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5620 u32 reg_addr0, u32 reg_val0,
5621 u32 reg_addr1, u32 reg_val1)
5623 struct i40e_aq_desc desc;
5624 struct i40e_aqc_alternate_write *cmd_resp =
5625 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5626 enum i40e_status_code status;
5628 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5629 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5630 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5631 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5632 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5634 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5640 * i40e_aq_alternate_write_indirect
5641 * @hw: pointer to the hardware structure
5642 * @addr: address of a first register to be modified
5643 * @dw_count: number of alternate structure fields to write
5644 * @buffer: pointer to the command buffer
5646 * Write 'dw_count' dwords from 'buffer' to alternate structure
5647 * starting at 'addr'.
5650 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5651 u32 addr, u32 dw_count, void *buffer)
5653 struct i40e_aq_desc desc;
5654 struct i40e_aqc_alternate_ind_write *cmd_resp =
5655 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5656 enum i40e_status_code status;
5659 return I40E_ERR_PARAM;
5661 /* Indirect command */
5662 i40e_fill_default_direct_cmd_desc(&desc,
5663 i40e_aqc_opc_alternate_write_indirect);
5665 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5666 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5667 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5670 cmd_resp->address = CPU_TO_LE32(addr);
5671 cmd_resp->length = CPU_TO_LE32(dw_count);
5673 status = i40e_asq_send_command(hw, &desc, buffer,
5674 I40E_LO_DWORD(4*dw_count), NULL);
5680 * i40e_aq_alternate_read
5681 * @hw: pointer to the hardware structure
5682 * @reg_addr0: address of first dword to be read
5683 * @reg_val0: pointer for data read from 'reg_addr0'
5684 * @reg_addr1: address of second dword to be read
5685 * @reg_val1: pointer for data read from 'reg_addr1'
5687 * Read one or two dwords from alternate structure. Fields are indicated
5688 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5689 * is not passed then only register at 'reg_addr0' is read.
5692 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5693 u32 reg_addr0, u32 *reg_val0,
5694 u32 reg_addr1, u32 *reg_val1)
5696 struct i40e_aq_desc desc;
5697 struct i40e_aqc_alternate_write *cmd_resp =
5698 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5699 enum i40e_status_code status;
5701 if (reg_val0 == NULL)
5702 return I40E_ERR_PARAM;
5704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5705 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5706 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5708 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5710 if (status == I40E_SUCCESS) {
5711 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5713 if (reg_val1 != NULL)
5714 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5721 * i40e_aq_alternate_read_indirect
5722 * @hw: pointer to the hardware structure
5723 * @addr: address of the alternate structure field
5724 * @dw_count: number of alternate structure fields to read
5725 * @buffer: pointer to the command buffer
5727 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5728 * place them in 'buffer'. The buffer should be allocated by caller.
5731 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5732 u32 addr, u32 dw_count, void *buffer)
5734 struct i40e_aq_desc desc;
5735 struct i40e_aqc_alternate_ind_write *cmd_resp =
5736 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5737 enum i40e_status_code status;
5740 return I40E_ERR_PARAM;
5742 /* Indirect command */
5743 i40e_fill_default_direct_cmd_desc(&desc,
5744 i40e_aqc_opc_alternate_read_indirect);
5746 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5747 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5748 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5749 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5751 cmd_resp->address = CPU_TO_LE32(addr);
5752 cmd_resp->length = CPU_TO_LE32(dw_count);
5754 status = i40e_asq_send_command(hw, &desc, buffer,
5755 I40E_LO_DWORD(4*dw_count), NULL);
5761 * i40e_aq_alternate_clear
5762 * @hw: pointer to the HW structure.
5764 * Clear the alternate structures of the port from which the function
5768 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5770 struct i40e_aq_desc desc;
5771 enum i40e_status_code status;
5773 i40e_fill_default_direct_cmd_desc(&desc,
5774 i40e_aqc_opc_alternate_clear_port);
5776 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5782 * i40e_aq_alternate_write_done
5783 * @hw: pointer to the HW structure.
5784 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5785 * @reset_needed: indicates the SW should trigger GLOBAL reset
5787 * Indicates to the FW that alternate structures have been changed.
5790 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5791 u8 bios_mode, bool *reset_needed)
5793 struct i40e_aq_desc desc;
5794 struct i40e_aqc_alternate_write_done *cmd =
5795 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5796 enum i40e_status_code status;
5798 if (reset_needed == NULL)
5799 return I40E_ERR_PARAM;
5801 i40e_fill_default_direct_cmd_desc(&desc,
5802 i40e_aqc_opc_alternate_write_done);
5804 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5806 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5807 if (!status && reset_needed)
5808 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5809 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5815 * i40e_aq_set_oem_mode
5816 * @hw: pointer to the HW structure.
5817 * @oem_mode: the OEM mode to be used
5819 * Sets the device to a specific operating mode. Currently the only supported
5820 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5823 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5826 struct i40e_aq_desc desc;
5827 struct i40e_aqc_alternate_write_done *cmd =
5828 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5829 enum i40e_status_code status;
5831 i40e_fill_default_direct_cmd_desc(&desc,
5832 i40e_aqc_opc_alternate_set_mode);
5834 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5836 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5842 * i40e_aq_resume_port_tx
5843 * @hw: pointer to the hardware structure
5844 * @cmd_details: pointer to command details structure or NULL
5846 * Resume port's Tx traffic
5848 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5849 struct i40e_asq_cmd_details *cmd_details)
5851 struct i40e_aq_desc desc;
5852 enum i40e_status_code status;
5854 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5862 * i40e_set_pci_config_data - store PCI bus info
5863 * @hw: pointer to hardware structure
5864 * @link_status: the link status word from PCI config space
5866 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5868 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5870 hw->bus.type = i40e_bus_type_pci_express;
5872 switch (link_status & I40E_PCI_LINK_WIDTH) {
5873 case I40E_PCI_LINK_WIDTH_1:
5874 hw->bus.width = i40e_bus_width_pcie_x1;
5876 case I40E_PCI_LINK_WIDTH_2:
5877 hw->bus.width = i40e_bus_width_pcie_x2;
5879 case I40E_PCI_LINK_WIDTH_4:
5880 hw->bus.width = i40e_bus_width_pcie_x4;
5882 case I40E_PCI_LINK_WIDTH_8:
5883 hw->bus.width = i40e_bus_width_pcie_x8;
5886 hw->bus.width = i40e_bus_width_unknown;
5890 switch (link_status & I40E_PCI_LINK_SPEED) {
5891 case I40E_PCI_LINK_SPEED_2500:
5892 hw->bus.speed = i40e_bus_speed_2500;
5894 case I40E_PCI_LINK_SPEED_5000:
5895 hw->bus.speed = i40e_bus_speed_5000;
5897 case I40E_PCI_LINK_SPEED_8000:
5898 hw->bus.speed = i40e_bus_speed_8000;
5901 hw->bus.speed = i40e_bus_speed_unknown;
5907 * i40e_aq_debug_dump
5908 * @hw: pointer to the hardware structure
5909 * @cluster_id: specific cluster to dump
5910 * @table_id: table id within cluster
5911 * @start_index: index of line in the block to read
5912 * @buff_size: dump buffer size
5913 * @buff: dump buffer
5914 * @ret_buff_size: actual buffer size returned
5915 * @ret_next_table: next block to read
5916 * @ret_next_index: next index to read
5918 * Dump internal FW/HW data for debug purposes.
5921 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5922 u8 table_id, u32 start_index, u16 buff_size,
5923 void *buff, u16 *ret_buff_size,
5924 u8 *ret_next_table, u32 *ret_next_index,
5925 struct i40e_asq_cmd_details *cmd_details)
5927 struct i40e_aq_desc desc;
5928 struct i40e_aqc_debug_dump_internals *cmd =
5929 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5930 struct i40e_aqc_debug_dump_internals *resp =
5931 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5932 enum i40e_status_code status;
5934 if (buff_size == 0 || !buff)
5935 return I40E_ERR_PARAM;
5937 i40e_fill_default_direct_cmd_desc(&desc,
5938 i40e_aqc_opc_debug_dump_internals);
5939 /* Indirect Command */
5940 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5941 if (buff_size > I40E_AQ_LARGE_BUF)
5942 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5944 cmd->cluster_id = cluster_id;
5945 cmd->table_id = table_id;
5946 cmd->idx = CPU_TO_LE32(start_index);
5948 desc.datalen = CPU_TO_LE16(buff_size);
5950 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5952 if (ret_buff_size != NULL)
5953 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5954 if (ret_next_table != NULL)
5955 *ret_next_table = resp->table_id;
5956 if (ret_next_index != NULL)
5957 *ret_next_index = LE32_TO_CPU(resp->idx);
5964 * i40e_read_bw_from_alt_ram
5965 * @hw: pointer to the hardware structure
5966 * @max_bw: pointer for max_bw read
5967 * @min_bw: pointer for min_bw read
5968 * @min_valid: pointer for bool that is true if min_bw is a valid value
5969 * @max_valid: pointer for bool that is true if max_bw is a valid value
5971 * Read bw from the alternate ram for the given pf
5973 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5974 u32 *max_bw, u32 *min_bw,
5975 bool *min_valid, bool *max_valid)
5977 enum i40e_status_code status;
5978 u32 max_bw_addr, min_bw_addr;
5980 /* Calculate the address of the min/max bw registers */
5981 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5982 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5983 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5984 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5985 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5986 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5988 /* Read the bandwidths from alt ram */
5989 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5990 min_bw_addr, min_bw);
5992 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5997 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6006 * i40e_aq_configure_partition_bw
6007 * @hw: pointer to the hardware structure
6008 * @bw_data: Buffer holding valid pfs and bw limits
6009 * @cmd_details: pointer to command details
6011 * Configure partitions guaranteed/max bw
6013 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6014 struct i40e_aqc_configure_partition_bw_data *bw_data,
6015 struct i40e_asq_cmd_details *cmd_details)
6017 enum i40e_status_code status;
6018 struct i40e_aq_desc desc;
6019 u16 bwd_size = sizeof(*bw_data);
6021 i40e_fill_default_direct_cmd_desc(&desc,
6022 i40e_aqc_opc_configure_partition_bw);
6024 /* Indirect command */
6025 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6026 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6028 desc.datalen = CPU_TO_LE16(bwd_size);
6030 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6036 * i40e_read_phy_register_clause22
6037 * @hw: pointer to the HW structure
6038 * @reg: register address in the page
6039 * @phy_adr: PHY address on MDIO interface
6040 * @value: PHY register value
6042 * Reads specified PHY register value
6044 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6045 u16 reg, u8 phy_addr, u16 *value)
6047 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6048 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6052 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6053 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6054 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6055 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6056 (I40E_GLGEN_MSCA_MDICMD_MASK);
6057 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6059 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6060 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6061 status = I40E_SUCCESS;
6064 i40e_usec_delay(10);
6069 i40e_debug(hw, I40E_DEBUG_PHY,
6070 "PHY: Can't write command to external PHY.\n");
6072 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6073 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6074 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6081 * i40e_write_phy_register_clause22
6082 * @hw: pointer to the HW structure
6083 * @reg: register address in the page
6084 * @phy_adr: PHY address on MDIO interface
6085 * @value: PHY register value
6087 * Writes specified PHY register value
6089 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6090 u16 reg, u8 phy_addr, u16 value)
6092 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6093 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6097 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6098 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6100 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6101 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6102 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6103 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6104 (I40E_GLGEN_MSCA_MDICMD_MASK);
6106 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6108 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6109 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6110 status = I40E_SUCCESS;
6113 i40e_usec_delay(10);
6121 * i40e_read_phy_register_clause45
6122 * @hw: pointer to the HW structure
6123 * @page: registers page number
6124 * @reg: register address in the page
6125 * @phy_adr: PHY address on MDIO interface
6126 * @value: PHY register value
6128 * Reads specified PHY register value
6130 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6131 u8 page, u16 reg, u8 phy_addr, u16 *value)
6133 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6136 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6138 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6139 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6140 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6141 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6142 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6143 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6144 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6145 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6147 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6148 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6149 status = I40E_SUCCESS;
6152 i40e_usec_delay(10);
6157 i40e_debug(hw, I40E_DEBUG_PHY,
6158 "PHY: Can't write command to external PHY.\n");
6162 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6163 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6164 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6165 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6166 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6167 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6168 status = I40E_ERR_TIMEOUT;
6170 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6172 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6173 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6174 status = I40E_SUCCESS;
6177 i40e_usec_delay(10);
6182 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6183 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6184 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6186 i40e_debug(hw, I40E_DEBUG_PHY,
6187 "PHY: Can't read register value from external PHY.\n");
6195 * i40e_write_phy_register_clause45
6196 * @hw: pointer to the HW structure
6197 * @page: registers page number
6198 * @reg: register address in the page
6199 * @phy_adr: PHY address on MDIO interface
6200 * @value: PHY register value
6202 * Writes value to specified PHY register
6204 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6205 u8 page, u16 reg, u8 phy_addr, u16 value)
6207 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6210 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6212 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6213 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6214 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6215 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6216 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6217 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6218 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6219 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6221 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6222 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6223 status = I40E_SUCCESS;
6226 i40e_usec_delay(10);
6230 i40e_debug(hw, I40E_DEBUG_PHY,
6231 "PHY: Can't write command to external PHY.\n");
6235 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6236 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6238 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6239 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6240 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6241 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6242 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6243 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6244 status = I40E_ERR_TIMEOUT;
6246 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6248 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6249 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6250 status = I40E_SUCCESS;
6253 i40e_usec_delay(10);
6262 * i40e_write_phy_register
6263 * @hw: pointer to the HW structure
6264 * @page: registers page number
6265 * @reg: register address in the page
6266 * @phy_adr: PHY address on MDIO interface
6267 * @value: PHY register value
6269 * Writes value to specified PHY register
6271 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6272 u8 page, u16 reg, u8 phy_addr, u16 value)
6274 enum i40e_status_code status;
6276 switch (hw->device_id) {
6277 case I40E_DEV_ID_1G_BASE_T_X722:
6278 status = i40e_write_phy_register_clause22(hw,
6279 reg, phy_addr, value);
6281 case I40E_DEV_ID_10G_BASE_T:
6282 case I40E_DEV_ID_10G_BASE_T4:
6283 case I40E_DEV_ID_10G_BASE_T_X722:
6284 case I40E_DEV_ID_25G_B:
6285 case I40E_DEV_ID_25G_SFP28:
6286 status = i40e_write_phy_register_clause45(hw,
6287 page, reg, phy_addr, value);
6290 status = I40E_ERR_UNKNOWN_PHY;
6298 * i40e_read_phy_register
6299 * @hw: pointer to the HW structure
6300 * @page: registers page number
6301 * @reg: register address in the page
6302 * @phy_adr: PHY address on MDIO interface
6303 * @value: PHY register value
6305 * Reads specified PHY register value
6307 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6308 u8 page, u16 reg, u8 phy_addr, u16 *value)
6310 enum i40e_status_code status;
6312 switch (hw->device_id) {
6313 case I40E_DEV_ID_1G_BASE_T_X722:
6314 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6317 case I40E_DEV_ID_10G_BASE_T:
6318 case I40E_DEV_ID_10G_BASE_T4:
6319 case I40E_DEV_ID_10G_BASE_T_X722:
6320 case I40E_DEV_ID_25G_B:
6321 case I40E_DEV_ID_25G_SFP28:
6322 status = i40e_read_phy_register_clause45(hw, page, reg,
6326 status = I40E_ERR_UNKNOWN_PHY;
6334 * i40e_get_phy_address
6335 * @hw: pointer to the HW structure
6336 * @dev_num: PHY port num that address we want
6337 * @phy_addr: Returned PHY address
6339 * Gets PHY address for current port
6341 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6343 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6344 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6346 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6350 * i40e_blink_phy_led
6351 * @hw: pointer to the HW structure
6352 * @time: time how long led will blinks in secs
6353 * @interval: gap between LED on and off in msecs
6355 * Blinks PHY link LED
6357 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6358 u32 time, u32 interval)
6360 enum i40e_status_code status = I40E_SUCCESS;
6365 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6369 i = rd32(hw, I40E_PFGEN_PORTNUM);
6370 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6371 phy_addr = i40e_get_phy_address(hw, port_num);
6373 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6375 status = i40e_read_phy_register_clause45(hw,
6376 I40E_PHY_COM_REG_PAGE,
6380 goto phy_blinking_end;
6382 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6384 status = i40e_write_phy_register_clause45(hw,
6385 I40E_PHY_COM_REG_PAGE,
6389 goto phy_blinking_end;
6394 if (time > 0 && interval > 0) {
6395 for (i = 0; i < time * 1000; i += interval) {
6396 status = i40e_read_phy_register_clause45(hw,
6397 I40E_PHY_COM_REG_PAGE,
6398 led_addr, phy_addr, &led_reg);
6400 goto restore_config;
6401 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6404 led_reg = I40E_PHY_LED_MANUAL_ON;
6405 status = i40e_write_phy_register_clause45(hw,
6406 I40E_PHY_COM_REG_PAGE,
6407 led_addr, phy_addr, led_reg);
6409 goto restore_config;
6410 i40e_msec_delay(interval);
6415 status = i40e_write_phy_register_clause45(hw,
6416 I40E_PHY_COM_REG_PAGE,
6417 led_addr, phy_addr, led_ctl);
6424 * i40e_led_get_phy - return current on/off mode
6425 * @hw: pointer to the hw struct
6426 * @led_addr: address of led register to use
6427 * @val: original value of register to use
6430 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6433 enum i40e_status_code status = I40E_SUCCESS;
6441 temp_addr = I40E_PHY_LED_PROV_REG_1;
6442 i = rd32(hw, I40E_PFGEN_PORTNUM);
6443 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6444 phy_addr = i40e_get_phy_address(hw, port_num);
6446 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6448 status = i40e_read_phy_register_clause45(hw,
6449 I40E_PHY_COM_REG_PAGE,
6450 temp_addr, phy_addr,
6455 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6456 *led_addr = temp_addr;
6465 * @hw: pointer to the HW structure
6466 * @on: true or false
6467 * @mode: original val plus bit for set or ignore
6468 * Set led's on or off when controlled by the PHY
6471 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6472 u16 led_addr, u32 mode)
6474 enum i40e_status_code status = I40E_SUCCESS;
6481 i = rd32(hw, I40E_PFGEN_PORTNUM);
6482 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6483 phy_addr = i40e_get_phy_address(hw, port_num);
6484 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6485 led_addr, phy_addr, &led_reg);
6489 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6491 status = i40e_write_phy_register_clause45(hw,
6492 I40E_PHY_COM_REG_PAGE,
6498 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6499 led_addr, phy_addr, &led_reg);
6501 goto restore_config;
6503 led_reg = I40E_PHY_LED_MANUAL_ON;
6506 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6507 led_addr, phy_addr, led_reg);
6509 goto restore_config;
6510 if (mode & I40E_PHY_LED_MODE_ORIG) {
6511 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6512 status = i40e_write_phy_register_clause45(hw,
6513 I40E_PHY_COM_REG_PAGE,
6514 led_addr, phy_addr, led_ctl);
6518 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6519 led_addr, phy_addr, led_ctl);
6522 #endif /* PF_DRIVER */
6525 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6526 * @hw: pointer to the hw struct
6527 * @reg_addr: register address
6528 * @reg_val: ptr to register value
6529 * @cmd_details: pointer to command details structure or NULL
6531 * Use the firmware to read the Rx control register,
6532 * especially useful if the Rx unit is under heavy pressure
6534 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6535 u32 reg_addr, u32 *reg_val,
6536 struct i40e_asq_cmd_details *cmd_details)
6538 struct i40e_aq_desc desc;
6539 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6540 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6541 enum i40e_status_code status;
6543 if (reg_val == NULL)
6544 return I40E_ERR_PARAM;
6546 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6548 cmd_resp->address = CPU_TO_LE32(reg_addr);
6550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6552 if (status == I40E_SUCCESS)
6553 *reg_val = LE32_TO_CPU(cmd_resp->value);
6559 * i40e_read_rx_ctl - read from an Rx control register
6560 * @hw: pointer to the hw struct
6561 * @reg_addr: register address
6563 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6565 enum i40e_status_code status = I40E_SUCCESS;
6570 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6571 if (!use_register) {
6573 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6574 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6581 /* if the AQ access failed, try the old-fashioned way */
6582 if (status || use_register)
6583 val = rd32(hw, reg_addr);
6589 * i40e_aq_rx_ctl_write_register
6590 * @hw: pointer to the hw struct
6591 * @reg_addr: register address
6592 * @reg_val: register value
6593 * @cmd_details: pointer to command details structure or NULL
6595 * Use the firmware to write to an Rx control register,
6596 * especially useful if the Rx unit is under heavy pressure
6598 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6599 u32 reg_addr, u32 reg_val,
6600 struct i40e_asq_cmd_details *cmd_details)
6602 struct i40e_aq_desc desc;
6603 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6604 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6605 enum i40e_status_code status;
6607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6609 cmd->address = CPU_TO_LE32(reg_addr);
6610 cmd->value = CPU_TO_LE32(reg_val);
6612 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6618 * i40e_write_rx_ctl - write to an Rx control register
6619 * @hw: pointer to the hw struct
6620 * @reg_addr: register address
6621 * @reg_val: register value
6623 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6625 enum i40e_status_code status = I40E_SUCCESS;
6629 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6630 if (!use_register) {
6632 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6634 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6641 /* if the AQ access failed, try the old-fashioned way */
6642 if (status || use_register)
6643 wr32(hw, reg_addr, reg_val);
6648 * i40e_aq_send_msg_to_pf
6649 * @hw: pointer to the hardware structure
6650 * @v_opcode: opcodes for VF-PF communication
6651 * @v_retval: return error code
6652 * @msg: pointer to the msg buffer
6653 * @msglen: msg length
6654 * @cmd_details: pointer to command details
6656 * Send message to PF driver using admin queue. By default, this message
6657 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6658 * completion before returning.
6660 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6661 enum i40e_virtchnl_ops v_opcode,
6662 enum i40e_status_code v_retval,
6663 u8 *msg, u16 msglen,
6664 struct i40e_asq_cmd_details *cmd_details)
6666 struct i40e_aq_desc desc;
6667 struct i40e_asq_cmd_details details;
6668 enum i40e_status_code status;
6670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6671 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6672 desc.cookie_high = CPU_TO_LE32(v_opcode);
6673 desc.cookie_low = CPU_TO_LE32(v_retval);
6675 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6676 | I40E_AQ_FLAG_RD));
6677 if (msglen > I40E_AQ_LARGE_BUF)
6678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6679 desc.datalen = CPU_TO_LE16(msglen);
6682 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6683 details.async = true;
6684 cmd_details = &details;
6686 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6687 msglen, cmd_details);
6692 * i40e_vf_parse_hw_config
6693 * @hw: pointer to the hardware structure
6694 * @msg: pointer to the virtual channel VF resource structure
6696 * Given a VF resource message from the PF, populate the hw struct
6697 * with appropriate information.
6699 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6700 struct i40e_virtchnl_vf_resource *msg)
6702 struct i40e_virtchnl_vsi_resource *vsi_res;
6705 vsi_res = &msg->vsi_res[0];
6707 hw->dev_caps.num_vsis = msg->num_vsis;
6708 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6709 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6710 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6711 hw->dev_caps.dcb = msg->vf_offload_flags &
6712 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6713 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6714 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6715 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6716 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6717 for (i = 0; i < msg->num_vsis; i++) {
6718 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6719 i40e_memcpy(hw->mac.perm_addr,
6720 vsi_res->default_mac_addr,
6721 I40E_ETH_LENGTH_OF_ADDRESS,
6722 I40E_NONDMA_TO_NONDMA);
6723 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6724 I40E_ETH_LENGTH_OF_ADDRESS,
6725 I40E_NONDMA_TO_NONDMA);
6733 * @hw: pointer to the hardware structure
6735 * Send a VF_RESET message to the PF. Does not wait for response from PF
6736 * as none will be forthcoming. Immediately after calling this function,
6737 * the admin queue should be shut down and (optionally) reinitialized.
6739 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6741 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6742 I40E_SUCCESS, NULL, 0, NULL);
6744 #endif /* VF_DRIVER */
6748 * i40e_aq_set_arp_proxy_config
6749 * @hw: pointer to the HW structure
6750 * @proxy_config - pointer to proxy config command table struct
6751 * @cmd_details: pointer to command details
6753 * Set ARP offload parameters from pre-populated
6754 * i40e_aqc_arp_proxy_data struct
6756 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6757 struct i40e_aqc_arp_proxy_data *proxy_config,
6758 struct i40e_asq_cmd_details *cmd_details)
6760 struct i40e_aq_desc desc;
6761 enum i40e_status_code status;
6764 return I40E_ERR_PARAM;
6766 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6768 desc.params.external.addr_high =
6769 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6770 desc.params.external.addr_low =
6771 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6773 status = i40e_asq_send_command(hw, &desc, proxy_config,
6774 sizeof(struct i40e_aqc_arp_proxy_data),
6781 * i40e_aq_opc_set_ns_proxy_table_entry
6782 * @hw: pointer to the HW structure
6783 * @ns_proxy_table_entry: pointer to NS table entry command struct
6784 * @cmd_details: pointer to command details
6786 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6787 * from pre-populated i40e_aqc_ns_proxy_data struct
6789 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6790 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6791 struct i40e_asq_cmd_details *cmd_details)
6793 struct i40e_aq_desc desc;
6794 enum i40e_status_code status;
6796 if (!ns_proxy_table_entry)
6797 return I40E_ERR_PARAM;
6799 i40e_fill_default_direct_cmd_desc(&desc,
6800 i40e_aqc_opc_set_ns_proxy_table_entry);
6802 desc.params.external.addr_high =
6803 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6804 desc.params.external.addr_low =
6805 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6807 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6808 sizeof(struct i40e_aqc_ns_proxy_data),
6815 * i40e_aq_set_clear_wol_filter
6816 * @hw: pointer to the hw struct
6817 * @filter_index: index of filter to modify (0-7)
6818 * @filter: buffer containing filter to be set
6819 * @set_filter: true to set filter, false to clear filter
6820 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6821 * if false, pass through packets may cause wake-up
6822 * @filter_valid: true if filter action is valid
6823 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6824 * @cmd_details: pointer to command details structure or NULL
6826 * Set or clear WoL filter for port attached to the PF
6828 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6830 struct i40e_aqc_set_wol_filter_data *filter,
6831 bool set_filter, bool no_wol_tco,
6832 bool filter_valid, bool no_wol_tco_valid,
6833 struct i40e_asq_cmd_details *cmd_details)
6835 struct i40e_aq_desc desc;
6836 struct i40e_aqc_set_wol_filter *cmd =
6837 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6838 enum i40e_status_code status;
6840 u16 valid_flags = 0;
6843 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6845 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6846 return I40E_ERR_PARAM;
6847 cmd->filter_index = CPU_TO_LE16(filter_index);
6851 return I40E_ERR_PARAM;
6852 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6853 buff_len = sizeof(*filter);
6856 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6857 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6860 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6861 if (no_wol_tco_valid)
6862 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6863 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6865 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6866 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6868 status = i40e_asq_send_command(hw, &desc, filter,
6869 buff_len, cmd_details);
6875 * i40e_aq_get_wake_event_reason
6876 * @hw: pointer to the hw struct
6877 * @wake_reason: return value, index of matching filter
6878 * @cmd_details: pointer to command details structure or NULL
6880 * Get information for the reason of a Wake Up event
6882 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6884 struct i40e_asq_cmd_details *cmd_details)
6886 struct i40e_aq_desc desc;
6887 struct i40e_aqc_get_wake_reason_completion *resp =
6888 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6889 enum i40e_status_code status;
6891 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6895 if (status == I40E_SUCCESS)
6896 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6901 #endif /* X722_SUPPORT */