drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319 #ifdef I40E_ESS_SUPPORT
1320         /* It can take upto 15 secs for GRST steady state */
1321         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1322 #endif
1323         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1324                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1326                         break;
1327                 i40e_msec_delay(100);
1328         }
1329         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330                 DEBUGOUT("Global reset polling failed to complete.\n");
1331                 return I40E_ERR_RESET_FAILED;
1332         }
1333
1334         /* Now Wait for the FW to be ready */
1335         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336                 reg = rd32(hw, I40E_GLNVM_ULD);
1337                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1342                         break;
1343                 }
1344                 i40e_msec_delay(10);
1345         }
1346         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348                 DEBUGOUT("wait for FW Reset complete timedout\n");
1349                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350                 return I40E_ERR_RESET_FAILED;
1351         }
1352
1353         /* If there was a Global Reset in progress when we got here,
1354          * we don't need to do the PF Reset
1355          */
1356         if (!cnt) {
1357                 reg = rd32(hw, I40E_PFGEN_CTRL);
1358                 wr32(hw, I40E_PFGEN_CTRL,
1359                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361                         reg = rd32(hw, I40E_PFGEN_CTRL);
1362                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1363                                 break;
1364                         i40e_msec_delay(1);
1365                 }
1366                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367                         DEBUGOUT("PF reset polling failed to complete.\n");
1368                         return I40E_ERR_RESET_FAILED;
1369                 }
1370         }
1371
1372         i40e_clear_pxe_mode(hw);
1373
1374
1375         return I40E_SUCCESS;
1376 }
1377
1378 /**
1379  * i40e_clear_hw - clear out any left over hw state
1380  * @hw: pointer to the hw struct
1381  *
1382  * Clear queues and interrupts, typically called at init time,
1383  * but after the capabilities have been found so we know how many
1384  * queues and msix vectors have been allocated.
1385  **/
1386 void i40e_clear_hw(struct i40e_hw *hw)
1387 {
1388         u32 num_queues, base_queue;
1389         u32 num_pf_int;
1390         u32 num_vf_int;
1391         u32 num_vfs;
1392         u32 i, j;
1393         u32 val;
1394         u32 eol = 0x7ff;
1395
1396         /* get number of interrupts, queues, and vfs */
1397         val = rd32(hw, I40E_GLPCI_CNF2);
1398         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1402
1403         val = rd32(hw, I40E_PFLAN_QALLOC);
1404         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409                 num_queues = (j - base_queue) + 1;
1410         else
1411                 num_queues = 0;
1412
1413         val = rd32(hw, I40E_PF_VT_PFALLOC);
1414         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419                 num_vfs = (j - i) + 1;
1420         else
1421                 num_vfs = 0;
1422
1423         /* stop all the interrupts */
1424         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426         for (i = 0; i < num_pf_int - 2; i++)
1427                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1428
1429         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431         wr32(hw, I40E_PFINT_LNKLST0, val);
1432         for (i = 0; i < num_pf_int - 2; i++)
1433                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435         for (i = 0; i < num_vfs; i++)
1436                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437         for (i = 0; i < num_vf_int - 2; i++)
1438                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1439
1440         /* warn the HW of the coming Tx disables */
1441         for (i = 0; i < num_queues; i++) {
1442                 u32 abs_queue_idx = base_queue + i;
1443                 u32 reg_block = 0;
1444
1445                 if (abs_queue_idx >= 128) {
1446                         reg_block = abs_queue_idx / 128;
1447                         abs_queue_idx %= 128;
1448                 }
1449
1450                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1454
1455                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1456         }
1457         i40e_usec_delay(400);
1458
1459         /* stop all the queues */
1460         for (i = 0; i < num_queues; i++) {
1461                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462                 wr32(hw, I40E_QTX_ENA(i), 0);
1463                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464                 wr32(hw, I40E_QRX_ENA(i), 0);
1465         }
1466
1467         /* short wait for all queue disables to settle */
1468         i40e_usec_delay(50);
1469 }
1470
1471 /**
1472  * i40e_clear_pxe_mode - clear pxe operations mode
1473  * @hw: pointer to the hw struct
1474  *
1475  * Make sure all PXE mode settings are cleared, including things
1476  * like descriptor fetch/write-back mode.
1477  **/
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1479 {
1480         if (i40e_check_asq_alive(hw))
1481                 i40e_aq_clear_pxe_mode(hw, NULL);
1482 }
1483
1484 /**
1485  * i40e_led_is_mine - helper to find matching led
1486  * @hw: pointer to the hw struct
1487  * @idx: index into GPIO registers
1488  *
1489  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1490  */
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1492 {
1493         u32 gpio_val = 0;
1494         u32 port;
1495
1496         if (!hw->func_caps.led[idx])
1497                 return 0;
1498
1499         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1502
1503         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504          * if it is not our port then ignore
1505          */
1506         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1507             (port != hw->port))
1508                 return 0;
1509
1510         return gpio_val;
1511 }
1512
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1518
1519 /**
1520  * i40e_led_get - return current on/off mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * The value returned is the 'mode' field as defined in the
1524  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525  * values are variations of possible behaviors relating to
1526  * blink, link, and wire.
1527  **/
1528 u32 i40e_led_get(struct i40e_hw *hw)
1529 {
1530         u32 current_mode = 0;
1531         u32 mode = 0;
1532         int i;
1533
1534         /* as per the documentation GPIO 22-29 are the LED
1535          * GPIO pins named LED0..LED7
1536          */
1537         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538                 u32 gpio_val = i40e_led_is_mine(hw, i);
1539
1540                 if (!gpio_val)
1541                         continue;
1542
1543                 /* ignore gpio LED src mode entries related to the activity LEDs */
1544                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546                 switch (current_mode) {
1547                 case I40E_COMBINED_ACTIVITY:
1548                 case I40E_FILTER_ACTIVITY:
1549                 case I40E_MAC_ACTIVITY:
1550                         continue;
1551                 default:
1552                         break;
1553                 }
1554
1555                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1557                 break;
1558         }
1559
1560         return mode;
1561 }
1562
1563 /**
1564  * i40e_led_set - set new on/off mode
1565  * @hw: pointer to the hw struct
1566  * @mode: 0=off, 0xf=on (else see manual for mode details)
1567  * @blink: true if the LED should blink when on, false if steady
1568  *
1569  * if this function is used to turn on the blink it should
1570  * be used to disable the blink when restoring the original state.
1571  **/
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1573 {
1574         u32 current_mode = 0;
1575         int i;
1576
1577         if (mode & 0xfffffff0)
1578                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1579
1580         /* as per the documentation GPIO 22-29 are the LED
1581          * GPIO pins named LED0..LED7
1582          */
1583         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584                 u32 gpio_val = i40e_led_is_mine(hw, i);
1585
1586                 if (!gpio_val)
1587                         continue;
1588
1589                 /* ignore gpio LED src mode entries related to the activity LEDs */
1590                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592                 switch (current_mode) {
1593                 case I40E_COMBINED_ACTIVITY:
1594                 case I40E_FILTER_ACTIVITY:
1595                 case I40E_MAC_ACTIVITY:
1596                         continue;
1597                 default:
1598                         break;
1599                 }
1600
1601                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602                 /* this & is a bit of paranoia, but serves as a range check */
1603                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1605
1606                 if (mode == I40E_LINK_ACTIVITY)
1607                         blink = false;
1608
1609                 if (blink)
1610                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1611                 else
1612                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1613
1614                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1615                 break;
1616         }
1617 }
1618
1619 /* Admin command wrappers */
1620
1621 /**
1622  * i40e_aq_get_phy_capabilities
1623  * @hw: pointer to the hw struct
1624  * @abilities: structure for PHY capabilities to be filled
1625  * @qualified_modules: report Qualified Modules
1626  * @report_init: report init capabilities (active are default)
1627  * @cmd_details: pointer to command details structure or NULL
1628  *
1629  * Returns the various PHY abilities supported on the Port.
1630  **/
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632                         bool qualified_modules, bool report_init,
1633                         struct i40e_aq_get_phy_abilities_resp *abilities,
1634                         struct i40e_asq_cmd_details *cmd_details)
1635 {
1636         struct i40e_aq_desc desc;
1637         enum i40e_status_code status;
1638         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1639
1640         if (!abilities)
1641                 return I40E_ERR_PARAM;
1642
1643         i40e_fill_default_direct_cmd_desc(&desc,
1644                                           i40e_aqc_opc_get_phy_abilities);
1645
1646         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647         if (abilities_size > I40E_AQ_LARGE_BUF)
1648                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1649
1650         if (qualified_modules)
1651                 desc.params.external.param0 |=
1652                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1653
1654         if (report_init)
1655                 desc.params.external.param0 |=
1656                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1657
1658         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1659                                     cmd_details);
1660
1661         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662                 status = I40E_ERR_UNKNOWN_PHY;
1663
1664         if (report_init)
1665                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1666
1667         return status;
1668 }
1669
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683                                 struct i40e_aq_set_phy_config *config,
1684                                 struct i40e_asq_cmd_details *cmd_details)
1685 {
1686         struct i40e_aq_desc desc;
1687         struct i40e_aq_set_phy_config *cmd =
1688                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689         enum i40e_status_code status;
1690
1691         if (!config)
1692                 return I40E_ERR_PARAM;
1693
1694         i40e_fill_default_direct_cmd_desc(&desc,
1695                                           i40e_aqc_opc_set_phy_config);
1696
1697         *cmd = *config;
1698
1699         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700
1701         return status;
1702 }
1703
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  *
1708  * Set the requested flow control mode using set_phy_config.
1709  **/
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711                                   bool atomic_restart)
1712 {
1713         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714         struct i40e_aq_get_phy_abilities_resp abilities;
1715         struct i40e_aq_set_phy_config config;
1716         enum i40e_status_code status;
1717         u8 pause_mask = 0x0;
1718
1719         *aq_failures = 0x0;
1720
1721         switch (fc_mode) {
1722         case I40E_FC_FULL:
1723                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1725                 break;
1726         case I40E_FC_RX_PAUSE:
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1728                 break;
1729         case I40E_FC_TX_PAUSE:
1730                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1731                 break;
1732         default:
1733                 break;
1734         }
1735
1736         /* Get the current phy config */
1737         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1738                                               NULL);
1739         if (status) {
1740                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1741                 return status;
1742         }
1743
1744         memset(&config, 0, sizeof(config));
1745         /* clear the old pause settings */
1746         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748         /* set the new abilities */
1749         config.abilities |= pause_mask;
1750         /* If the abilities have changed, then set the new config */
1751         if (config.abilities != abilities.abilities) {
1752                 /* Auto restart link so settings take effect */
1753                 if (atomic_restart)
1754                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755                 /* Copy over all the old settings */
1756                 config.phy_type = abilities.phy_type;
1757                 config.link_speed = abilities.link_speed;
1758                 config.eee_capability = abilities.eee_capability;
1759                 config.eeer = abilities.eeer_val;
1760                 config.low_power_ctrl = abilities.d3_lpan;
1761                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1762
1763                 if (status)
1764                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1765         }
1766         /* Update the link info */
1767         status = i40e_update_link_info(hw);
1768         if (status) {
1769                 /* Wait a little bit (on 40G cards it sometimes takes a really
1770                  * long time for link to come back from the atomic reset)
1771                  * and try once more
1772                  */
1773                 i40e_msec_delay(1000);
1774                 status = i40e_update_link_info(hw);
1775         }
1776         if (status)
1777                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_aq_set_mac_config
1784  * @hw: pointer to the hw struct
1785  * @max_frame_size: Maximum Frame Size to be supported by the port
1786  * @crc_en: Tell HW to append a CRC to outgoing frames
1787  * @pacing: Pacing configurations
1788  * @cmd_details: pointer to command details structure or NULL
1789  *
1790  * Configure MAC settings for frame size, jumbo frame support and the
1791  * addition of a CRC by the hardware.
1792  **/
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1794                                 u16 max_frame_size,
1795                                 bool crc_en, u16 pacing,
1796                                 struct i40e_asq_cmd_details *cmd_details)
1797 {
1798         struct i40e_aq_desc desc;
1799         struct i40e_aq_set_mac_config *cmd =
1800                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801         enum i40e_status_code status;
1802
1803         if (max_frame_size == 0)
1804                 return I40E_ERR_PARAM;
1805
1806         i40e_fill_default_direct_cmd_desc(&desc,
1807                                           i40e_aqc_opc_set_mac_config);
1808
1809         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810         cmd->params = ((u8)pacing & 0x0F) << 3;
1811         if (crc_en)
1812                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         return status;
1817 }
1818
1819 /**
1820  * i40e_aq_clear_pxe_mode
1821  * @hw: pointer to the hw struct
1822  * @cmd_details: pointer to command details structure or NULL
1823  *
1824  * Tell the firmware that the driver is taking over from PXE
1825  **/
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827                         struct i40e_asq_cmd_details *cmd_details)
1828 {
1829         enum i40e_status_code status;
1830         struct i40e_aq_desc desc;
1831         struct i40e_aqc_clear_pxe *cmd =
1832                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1833
1834         i40e_fill_default_direct_cmd_desc(&desc,
1835                                           i40e_aqc_opc_clear_pxe_mode);
1836
1837         cmd->rx_cnt = 0x2;
1838
1839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1840
1841         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1842
1843         return status;
1844 }
1845
1846 /**
1847  * i40e_aq_set_link_restart_an
1848  * @hw: pointer to the hw struct
1849  * @enable_link: if true: enable link, if false: disable link
1850  * @cmd_details: pointer to command details structure or NULL
1851  *
1852  * Sets up the link and restarts the Auto-Negotiation over the link.
1853  **/
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1856 {
1857         struct i40e_aq_desc desc;
1858         struct i40e_aqc_set_link_restart_an *cmd =
1859                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860         enum i40e_status_code status;
1861
1862         i40e_fill_default_direct_cmd_desc(&desc,
1863                                           i40e_aqc_opc_set_link_restart_an);
1864
1865         cmd->command = I40E_AQ_PHY_RESTART_AN;
1866         if (enable_link)
1867                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1868         else
1869                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1870
1871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1872
1873         return status;
1874 }
1875
1876 /**
1877  * i40e_aq_get_link_info
1878  * @hw: pointer to the hw struct
1879  * @enable_lse: enable/disable LinkStatusEvent reporting
1880  * @link: pointer to link status structure - optional
1881  * @cmd_details: pointer to command details structure or NULL
1882  *
1883  * Returns the link status of the adapter.
1884  **/
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886                                 bool enable_lse, struct i40e_link_status *link,
1887                                 struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_get_link_status *resp =
1891                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893         enum i40e_status_code status;
1894         bool tx_pause, rx_pause;
1895         u16 command_flags;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1898
1899         if (enable_lse)
1900                 command_flags = I40E_AQ_LSE_ENABLE;
1901         else
1902                 command_flags = I40E_AQ_LSE_DISABLE;
1903         resp->command_flags = CPU_TO_LE16(command_flags);
1904
1905         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1906
1907         if (status != I40E_SUCCESS)
1908                 goto aq_get_link_info_exit;
1909
1910         /* save off old link status information */
1911         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1913
1914         /* update link status */
1915         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916         hw->phy.media_type = i40e_get_media_type(hw);
1917         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918         hw_link_info->link_info = resp->link_info;
1919         hw_link_info->an_info = resp->an_info;
1920         hw_link_info->ext_info = resp->ext_info;
1921         hw_link_info->loopback = resp->loopback;
1922         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1924
1925         /* update fc info */
1926         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928         if (tx_pause & rx_pause)
1929                 hw->fc.current_mode = I40E_FC_FULL;
1930         else if (tx_pause)
1931                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1932         else if (rx_pause)
1933                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1934         else
1935                 hw->fc.current_mode = I40E_FC_NONE;
1936
1937         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938                 hw_link_info->crc_enable = true;
1939         else
1940                 hw_link_info->crc_enable = false;
1941
1942         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943                 hw_link_info->lse_enable = true;
1944         else
1945                 hw_link_info->lse_enable = false;
1946
1947         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1950
1951         /* save link status information */
1952         if (link)
1953                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954                             I40E_NONDMA_TO_NONDMA);
1955
1956         /* flag cleared so helper functions don't call AQ again */
1957         hw->phy.get_link_info = false;
1958
1959 aq_get_link_info_exit:
1960         return status;
1961 }
1962
1963 /**
1964  * i40e_aq_set_phy_int_mask
1965  * @hw: pointer to the hw struct
1966  * @mask: interrupt mask to be set
1967  * @cmd_details: pointer to command details structure or NULL
1968  *
1969  * Set link interrupt mask.
1970  **/
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1972                                 u16 mask,
1973                                 struct i40e_asq_cmd_details *cmd_details)
1974 {
1975         struct i40e_aq_desc desc;
1976         struct i40e_aqc_set_phy_int_mask *cmd =
1977                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978         enum i40e_status_code status;
1979
1980         i40e_fill_default_direct_cmd_desc(&desc,
1981                                           i40e_aqc_opc_set_phy_int_mask);
1982
1983         cmd->event_mask = CPU_TO_LE16(mask);
1984
1985         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1986
1987         return status;
1988 }
1989
1990 /**
1991  * i40e_aq_get_local_advt_reg
1992  * @hw: pointer to the hw struct
1993  * @advt_reg: local AN advertisement register value
1994  * @cmd_details: pointer to command details structure or NULL
1995  *
1996  * Get the Local AN advertisement register value.
1997  **/
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1999                                 u64 *advt_reg,
2000                                 struct i40e_asq_cmd_details *cmd_details)
2001 {
2002         struct i40e_aq_desc desc;
2003         struct i40e_aqc_an_advt_reg *resp =
2004                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005         enum i40e_status_code status;
2006
2007         i40e_fill_default_direct_cmd_desc(&desc,
2008                                           i40e_aqc_opc_get_local_advt_reg);
2009
2010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2011
2012         if (status != I40E_SUCCESS)
2013                 goto aq_get_local_advt_reg_exit;
2014
2015         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2017
2018 aq_get_local_advt_reg_exit:
2019         return status;
2020 }
2021
2022 /**
2023  * i40e_aq_set_local_advt_reg
2024  * @hw: pointer to the hw struct
2025  * @advt_reg: local AN advertisement register value
2026  * @cmd_details: pointer to command details structure or NULL
2027  *
2028  * Get the Local AN advertisement register value.
2029  **/
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2031                                 u64 advt_reg,
2032                                 struct i40e_asq_cmd_details *cmd_details)
2033 {
2034         struct i40e_aq_desc desc;
2035         struct i40e_aqc_an_advt_reg *cmd =
2036                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037         enum i40e_status_code status;
2038
2039         i40e_fill_default_direct_cmd_desc(&desc,
2040                                           i40e_aqc_opc_get_local_advt_reg);
2041
2042         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         return status;
2048 }
2049
2050 /**
2051  * i40e_aq_get_partner_advt
2052  * @hw: pointer to the hw struct
2053  * @advt_reg: AN partner advertisement register value
2054  * @cmd_details: pointer to command details structure or NULL
2055  *
2056  * Get the link partner AN advertisement register value.
2057  **/
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2059                                 u64 *advt_reg,
2060                                 struct i40e_asq_cmd_details *cmd_details)
2061 {
2062         struct i40e_aq_desc desc;
2063         struct i40e_aqc_an_advt_reg *resp =
2064                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065         enum i40e_status_code status;
2066
2067         i40e_fill_default_direct_cmd_desc(&desc,
2068                                           i40e_aqc_opc_get_partner_advt);
2069
2070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071
2072         if (status != I40E_SUCCESS)
2073                 goto aq_get_partner_advt_exit;
2074
2075         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2077
2078 aq_get_partner_advt_exit:
2079         return status;
2080 }
2081
2082 /**
2083  * i40e_aq_set_lb_modes
2084  * @hw: pointer to the hw struct
2085  * @lb_modes: loopback mode to be set
2086  * @cmd_details: pointer to command details structure or NULL
2087  *
2088  * Sets loopback modes.
2089  **/
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2091                                 u16 lb_modes,
2092                                 struct i40e_asq_cmd_details *cmd_details)
2093 {
2094         struct i40e_aq_desc desc;
2095         struct i40e_aqc_set_lb_mode *cmd =
2096                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097         enum i40e_status_code status;
2098
2099         i40e_fill_default_direct_cmd_desc(&desc,
2100                                           i40e_aqc_opc_set_lb_modes);
2101
2102         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2103
2104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2105
2106         return status;
2107 }
2108
2109 /**
2110  * i40e_aq_set_phy_debug
2111  * @hw: pointer to the hw struct
2112  * @cmd_flags: debug command flags
2113  * @cmd_details: pointer to command details structure or NULL
2114  *
2115  * Reset the external PHY.
2116  **/
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118                                 struct i40e_asq_cmd_details *cmd_details)
2119 {
2120         struct i40e_aq_desc desc;
2121         struct i40e_aqc_set_phy_debug *cmd =
2122                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123         enum i40e_status_code status;
2124
2125         i40e_fill_default_direct_cmd_desc(&desc,
2126                                           i40e_aqc_opc_set_phy_debug);
2127
2128         cmd->command_flags = cmd_flags;
2129
2130         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2131
2132         return status;
2133 }
2134
2135 /**
2136  * i40e_aq_add_vsi
2137  * @hw: pointer to the hw struct
2138  * @vsi_ctx: pointer to a vsi context struct
2139  * @cmd_details: pointer to command details structure or NULL
2140  *
2141  * Add a VSI context to the hardware.
2142 **/
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144                                 struct i40e_vsi_context *vsi_ctx,
2145                                 struct i40e_asq_cmd_details *cmd_details)
2146 {
2147         struct i40e_aq_desc desc;
2148         struct i40e_aqc_add_get_update_vsi *cmd =
2149                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150         struct i40e_aqc_add_get_update_vsi_completion *resp =
2151                 (struct i40e_aqc_add_get_update_vsi_completion *)
2152                 &desc.params.raw;
2153         enum i40e_status_code status;
2154
2155         i40e_fill_default_direct_cmd_desc(&desc,
2156                                           i40e_aqc_opc_add_vsi);
2157
2158         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159         cmd->connection_type = vsi_ctx->connection_type;
2160         cmd->vf_id = vsi_ctx->vf_num;
2161         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2162
2163         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2164
2165         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166                                     sizeof(vsi_ctx->info), cmd_details);
2167
2168         if (status != I40E_SUCCESS)
2169                 goto aq_add_vsi_exit;
2170
2171         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2175
2176 aq_add_vsi_exit:
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_aq_set_default_vsi
2182  * @hw: pointer to the hw struct
2183  * @seid: vsi number
2184  * @cmd_details: pointer to command details structure or NULL
2185  **/
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2187                                 u16 seid,
2188                                 struct i40e_asq_cmd_details *cmd_details)
2189 {
2190         struct i40e_aq_desc desc;
2191         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2193                 &desc.params.raw;
2194         enum i40e_status_code status;
2195
2196         i40e_fill_default_direct_cmd_desc(&desc,
2197                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2198
2199         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201         cmd->seid = CPU_TO_LE16(seid);
2202
2203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205         return status;
2206 }
2207
2208 /**
2209  * i40e_aq_set_vsi_unicast_promiscuous
2210  * @hw: pointer to the hw struct
2211  * @seid: vsi number
2212  * @set: set unicast promiscuous enable/disable
2213  * @cmd_details: pointer to command details structure or NULL
2214  **/
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2216                                 u16 seid, bool set,
2217                                 struct i40e_asq_cmd_details *cmd_details)
2218 {
2219         struct i40e_aq_desc desc;
2220         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222         enum i40e_status_code status;
2223         u16 flags = 0;
2224
2225         i40e_fill_default_direct_cmd_desc(&desc,
2226                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2227
2228         if (set)
2229                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2230
2231         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2232
2233         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2234
2235         cmd->seid = CPU_TO_LE16(seid);
2236         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2237
2238         return status;
2239 }
2240
2241 /**
2242  * i40e_aq_set_vsi_multicast_promiscuous
2243  * @hw: pointer to the hw struct
2244  * @seid: vsi number
2245  * @set: set multicast promiscuous enable/disable
2246  * @cmd_details: pointer to command details structure or NULL
2247  **/
2248 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2249                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2250 {
2251         struct i40e_aq_desc desc;
2252         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2253                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2254         enum i40e_status_code status;
2255         u16 flags = 0;
2256
2257         i40e_fill_default_direct_cmd_desc(&desc,
2258                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2259
2260         if (set)
2261                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2262
2263         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2264
2265         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2266
2267         cmd->seid = CPU_TO_LE16(seid);
2268         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2269
2270         return status;
2271 }
2272
2273 /**
2274  * i40e_aq_set_vsi_mc_promisc_on_vlan
2275  * @hw: pointer to the hw struct
2276  * @seid: vsi number
2277  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2278  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2279  * @cmd_details: pointer to command details structure or NULL
2280  **/
2281 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2282                                 u16 seid, bool enable, u16 vid,
2283                                 struct i40e_asq_cmd_details *cmd_details)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288         enum i40e_status_code status;
2289         u16 flags = 0;
2290
2291         i40e_fill_default_direct_cmd_desc(&desc,
2292                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2293
2294         if (enable)
2295                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2296
2297         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2298         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2299         cmd->seid = CPU_TO_LE16(seid);
2300         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2301
2302         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2303
2304         return status;
2305 }
2306
2307 /**
2308  * i40e_aq_set_vsi_uc_promisc_on_vlan
2309  * @hw: pointer to the hw struct
2310  * @seid: vsi number
2311  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2312  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2313  * @cmd_details: pointer to command details structure or NULL
2314  **/
2315 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2316                                 u16 seid, bool enable, u16 vid,
2317                                 struct i40e_asq_cmd_details *cmd_details)
2318 {
2319         struct i40e_aq_desc desc;
2320         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2321                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2322         enum i40e_status_code status;
2323         u16 flags = 0;
2324
2325         i40e_fill_default_direct_cmd_desc(&desc,
2326                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2327
2328         if (enable)
2329                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2330
2331         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2332         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2333         cmd->seid = CPU_TO_LE16(seid);
2334         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2335
2336         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2337
2338         return status;
2339 }
2340
2341 /**
2342  * i40e_aq_set_vsi_broadcast
2343  * @hw: pointer to the hw struct
2344  * @seid: vsi number
2345  * @set_filter: true to set filter, false to clear filter
2346  * @cmd_details: pointer to command details structure or NULL
2347  *
2348  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2349  **/
2350 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2351                                 u16 seid, bool set_filter,
2352                                 struct i40e_asq_cmd_details *cmd_details)
2353 {
2354         struct i40e_aq_desc desc;
2355         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357         enum i40e_status_code status;
2358
2359         i40e_fill_default_direct_cmd_desc(&desc,
2360                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2361
2362         if (set_filter)
2363                 cmd->promiscuous_flags
2364                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2365         else
2366                 cmd->promiscuous_flags
2367                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2368
2369         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2370         cmd->seid = CPU_TO_LE16(seid);
2371         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2372
2373         return status;
2374 }
2375
2376 /**
2377  * i40e_get_vsi_params - get VSI configuration info
2378  * @hw: pointer to the hw struct
2379  * @vsi_ctx: pointer to a vsi context struct
2380  * @cmd_details: pointer to command details structure or NULL
2381  **/
2382 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2383                                 struct i40e_vsi_context *vsi_ctx,
2384                                 struct i40e_asq_cmd_details *cmd_details)
2385 {
2386         struct i40e_aq_desc desc;
2387         struct i40e_aqc_add_get_update_vsi *cmd =
2388                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2389         struct i40e_aqc_add_get_update_vsi_completion *resp =
2390                 (struct i40e_aqc_add_get_update_vsi_completion *)
2391                 &desc.params.raw;
2392         enum i40e_status_code status;
2393
2394         UNREFERENCED_1PARAMETER(cmd_details);
2395         i40e_fill_default_direct_cmd_desc(&desc,
2396                                           i40e_aqc_opc_get_vsi_parameters);
2397
2398         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2399
2400         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2401
2402         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2403                                     sizeof(vsi_ctx->info), NULL);
2404
2405         if (status != I40E_SUCCESS)
2406                 goto aq_get_vsi_params_exit;
2407
2408         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2409         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2410         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2411         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2412
2413 aq_get_vsi_params_exit:
2414         return status;
2415 }
2416
2417 /**
2418  * i40e_aq_update_vsi_params
2419  * @hw: pointer to the hw struct
2420  * @vsi_ctx: pointer to a vsi context struct
2421  * @cmd_details: pointer to command details structure or NULL
2422  *
2423  * Update a VSI context.
2424  **/
2425 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2426                                 struct i40e_vsi_context *vsi_ctx,
2427                                 struct i40e_asq_cmd_details *cmd_details)
2428 {
2429         struct i40e_aq_desc desc;
2430         struct i40e_aqc_add_get_update_vsi *cmd =
2431                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2432         enum i40e_status_code status;
2433
2434         i40e_fill_default_direct_cmd_desc(&desc,
2435                                           i40e_aqc_opc_update_vsi_parameters);
2436         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2437
2438         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2439
2440         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2441                                     sizeof(vsi_ctx->info), cmd_details);
2442
2443         return status;
2444 }
2445
2446 /**
2447  * i40e_aq_get_switch_config
2448  * @hw: pointer to the hardware structure
2449  * @buf: pointer to the result buffer
2450  * @buf_size: length of input buffer
2451  * @start_seid: seid to start for the report, 0 == beginning
2452  * @cmd_details: pointer to command details structure or NULL
2453  *
2454  * Fill the buf with switch configuration returned from AdminQ command
2455  **/
2456 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2457                                 struct i40e_aqc_get_switch_config_resp *buf,
2458                                 u16 buf_size, u16 *start_seid,
2459                                 struct i40e_asq_cmd_details *cmd_details)
2460 {
2461         struct i40e_aq_desc desc;
2462         struct i40e_aqc_switch_seid *scfg =
2463                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2464         enum i40e_status_code status;
2465
2466         i40e_fill_default_direct_cmd_desc(&desc,
2467                                           i40e_aqc_opc_get_switch_config);
2468         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2469         if (buf_size > I40E_AQ_LARGE_BUF)
2470                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2471         scfg->seid = CPU_TO_LE16(*start_seid);
2472
2473         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2474         *start_seid = LE16_TO_CPU(scfg->seid);
2475
2476         return status;
2477 }
2478
2479 /**
2480  * i40e_aq_get_firmware_version
2481  * @hw: pointer to the hw struct
2482  * @fw_major_version: firmware major version
2483  * @fw_minor_version: firmware minor version
2484  * @fw_build: firmware build number
2485  * @api_major_version: major queue version
2486  * @api_minor_version: minor queue version
2487  * @cmd_details: pointer to command details structure or NULL
2488  *
2489  * Get the firmware version from the admin queue commands
2490  **/
2491 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2492                                 u16 *fw_major_version, u16 *fw_minor_version,
2493                                 u32 *fw_build,
2494                                 u16 *api_major_version, u16 *api_minor_version,
2495                                 struct i40e_asq_cmd_details *cmd_details)
2496 {
2497         struct i40e_aq_desc desc;
2498         struct i40e_aqc_get_version *resp =
2499                 (struct i40e_aqc_get_version *)&desc.params.raw;
2500         enum i40e_status_code status;
2501
2502         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2503
2504         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2505
2506         if (status == I40E_SUCCESS) {
2507                 if (fw_major_version != NULL)
2508                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2509                 if (fw_minor_version != NULL)
2510                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2511                 if (fw_build != NULL)
2512                         *fw_build = LE32_TO_CPU(resp->fw_build);
2513                 if (api_major_version != NULL)
2514                         *api_major_version = LE16_TO_CPU(resp->api_major);
2515                 if (api_minor_version != NULL)
2516                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2517
2518                 /* A workaround to fix the API version in SW */
2519                 if (api_major_version && api_minor_version &&
2520                     fw_major_version && fw_minor_version &&
2521                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2522                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2523                      (*fw_major_version > 4)))
2524                         *api_minor_version = 2;
2525         }
2526
2527         return status;
2528 }
2529
2530 /**
2531  * i40e_aq_send_driver_version
2532  * @hw: pointer to the hw struct
2533  * @dv: driver's major, minor version
2534  * @cmd_details: pointer to command details structure or NULL
2535  *
2536  * Send the driver version to the firmware
2537  **/
2538 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2539                                 struct i40e_driver_version *dv,
2540                                 struct i40e_asq_cmd_details *cmd_details)
2541 {
2542         struct i40e_aq_desc desc;
2543         struct i40e_aqc_driver_version *cmd =
2544                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2545         enum i40e_status_code status;
2546         u16 len;
2547
2548         if (dv == NULL)
2549                 return I40E_ERR_PARAM;
2550
2551         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2552
2553         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2554         cmd->driver_major_ver = dv->major_version;
2555         cmd->driver_minor_ver = dv->minor_version;
2556         cmd->driver_build_ver = dv->build_version;
2557         cmd->driver_subbuild_ver = dv->subbuild_version;
2558
2559         len = 0;
2560         while (len < sizeof(dv->driver_string) &&
2561                (dv->driver_string[len] < 0x80) &&
2562                dv->driver_string[len])
2563                 len++;
2564         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2565                                        len, cmd_details);
2566
2567         return status;
2568 }
2569
2570 /**
2571  * i40e_get_link_status - get status of the HW network link
2572  * @hw: pointer to the hw struct
2573  * @link_up: pointer to bool (true/false = linkup/linkdown)
2574  *
2575  * Variable link_up true if link is up, false if link is down.
2576  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2577  *
2578  * Side effect: LinkStatusEvent reporting becomes enabled
2579  **/
2580 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2581 {
2582         enum i40e_status_code status = I40E_SUCCESS;
2583
2584         if (hw->phy.get_link_info) {
2585                 status = i40e_update_link_info(hw);
2586
2587                 if (status != I40E_SUCCESS)
2588                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2589                                    status);
2590         }
2591
2592         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2593
2594         return status;
2595 }
2596
2597 /**
2598  * i40e_updatelink_status - update status of the HW network link
2599  * @hw: pointer to the hw struct
2600  **/
2601 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2602 {
2603         struct i40e_aq_get_phy_abilities_resp abilities;
2604         enum i40e_status_code status = I40E_SUCCESS;
2605
2606         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2607         if (status)
2608                 return status;
2609
2610         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2611                                               NULL);
2612         if (status)
2613                 return status;
2614
2615         memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2616                 sizeof(hw->phy.link_info.module_type));
2617
2618         return status;
2619 }
2620
2621 /**
2622  * i40e_get_link_speed
2623  * @hw: pointer to the hw struct
2624  *
2625  * Returns the link speed of the adapter.
2626  **/
2627 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2628 {
2629         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2630         enum i40e_status_code status = I40E_SUCCESS;
2631
2632         if (hw->phy.get_link_info) {
2633                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2634
2635                 if (status != I40E_SUCCESS)
2636                         goto i40e_link_speed_exit;
2637         }
2638
2639         speed = hw->phy.link_info.link_speed;
2640
2641 i40e_link_speed_exit:
2642         return speed;
2643 }
2644
2645 /**
2646  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2647  * @hw: pointer to the hw struct
2648  * @uplink_seid: the MAC or other gizmo SEID
2649  * @downlink_seid: the VSI SEID
2650  * @enabled_tc: bitmap of TCs to be enabled
2651  * @default_port: true for default port VSI, false for control port
2652  * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2653  * @veb_seid: pointer to where to put the resulting VEB SEID
2654  * @cmd_details: pointer to command details structure or NULL
2655  *
2656  * This asks the FW to add a VEB between the uplink and downlink
2657  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2658  **/
2659 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2660                                 u16 downlink_seid, u8 enabled_tc,
2661                                 bool default_port, bool enable_l2_filtering,
2662                                 u16 *veb_seid,
2663                                 struct i40e_asq_cmd_details *cmd_details)
2664 {
2665         struct i40e_aq_desc desc;
2666         struct i40e_aqc_add_veb *cmd =
2667                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2668         struct i40e_aqc_add_veb_completion *resp =
2669                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2670         enum i40e_status_code status;
2671         u16 veb_flags = 0;
2672
2673         /* SEIDs need to either both be set or both be 0 for floating VEB */
2674         if (!!uplink_seid != !!downlink_seid)
2675                 return I40E_ERR_PARAM;
2676
2677         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2678
2679         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2680         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2681         cmd->enable_tcs = enabled_tc;
2682         if (!uplink_seid)
2683                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2684         if (default_port)
2685                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2686         else
2687                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2688
2689         if (enable_l2_filtering)
2690                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2691
2692         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2693
2694         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2695
2696         if (!status && veb_seid)
2697                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2698
2699         return status;
2700 }
2701
2702 /**
2703  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2704  * @hw: pointer to the hw struct
2705  * @veb_seid: the SEID of the VEB to query
2706  * @switch_id: the uplink switch id
2707  * @floating: set to true if the VEB is floating
2708  * @statistic_index: index of the stats counter block for this VEB
2709  * @vebs_used: number of VEB's used by function
2710  * @vebs_free: total VEB's not reserved by any function
2711  * @cmd_details: pointer to command details structure or NULL
2712  *
2713  * This retrieves the parameters for a particular VEB, specified by
2714  * uplink_seid, and returns them to the caller.
2715  **/
2716 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2717                                 u16 veb_seid, u16 *switch_id,
2718                                 bool *floating, u16 *statistic_index,
2719                                 u16 *vebs_used, u16 *vebs_free,
2720                                 struct i40e_asq_cmd_details *cmd_details)
2721 {
2722         struct i40e_aq_desc desc;
2723         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2724                 (struct i40e_aqc_get_veb_parameters_completion *)
2725                 &desc.params.raw;
2726         enum i40e_status_code status;
2727
2728         if (veb_seid == 0)
2729                 return I40E_ERR_PARAM;
2730
2731         i40e_fill_default_direct_cmd_desc(&desc,
2732                                           i40e_aqc_opc_get_veb_parameters);
2733         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2734
2735         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2736         if (status)
2737                 goto get_veb_exit;
2738
2739         if (switch_id)
2740                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2741         if (statistic_index)
2742                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2743         if (vebs_used)
2744                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2745         if (vebs_free)
2746                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2747         if (floating) {
2748                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2749                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2750                         *floating = true;
2751                 else
2752                         *floating = false;
2753         }
2754
2755 get_veb_exit:
2756         return status;
2757 }
2758
2759 /**
2760  * i40e_aq_add_macvlan
2761  * @hw: pointer to the hw struct
2762  * @seid: VSI for the mac address
2763  * @mv_list: list of macvlans to be added
2764  * @count: length of the list
2765  * @cmd_details: pointer to command details structure or NULL
2766  *
2767  * Add MAC/VLAN addresses to the HW filtering
2768  **/
2769 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2770                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2771                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2772 {
2773         struct i40e_aq_desc desc;
2774         struct i40e_aqc_macvlan *cmd =
2775                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2776         enum i40e_status_code status;
2777         u16 buf_size;
2778
2779         if (count == 0 || !mv_list || !hw)
2780                 return I40E_ERR_PARAM;
2781
2782         buf_size = count * sizeof(*mv_list);
2783
2784         /* prep the rest of the request */
2785         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2786         cmd->num_addresses = CPU_TO_LE16(count);
2787         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2788         cmd->seid[1] = 0;
2789         cmd->seid[2] = 0;
2790
2791         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2792         if (buf_size > I40E_AQ_LARGE_BUF)
2793                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2794
2795         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2796                                     cmd_details);
2797
2798         return status;
2799 }
2800
2801 /**
2802  * i40e_aq_remove_macvlan
2803  * @hw: pointer to the hw struct
2804  * @seid: VSI for the mac address
2805  * @mv_list: list of macvlans to be removed
2806  * @count: length of the list
2807  * @cmd_details: pointer to command details structure or NULL
2808  *
2809  * Remove MAC/VLAN addresses from the HW filtering
2810  **/
2811 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2812                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2813                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2814 {
2815         struct i40e_aq_desc desc;
2816         struct i40e_aqc_macvlan *cmd =
2817                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2818         enum i40e_status_code status;
2819         u16 buf_size;
2820
2821         if (count == 0 || !mv_list || !hw)
2822                 return I40E_ERR_PARAM;
2823
2824         buf_size = count * sizeof(*mv_list);
2825
2826         /* prep the rest of the request */
2827         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2828         cmd->num_addresses = CPU_TO_LE16(count);
2829         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2830         cmd->seid[1] = 0;
2831         cmd->seid[2] = 0;
2832
2833         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2834         if (buf_size > I40E_AQ_LARGE_BUF)
2835                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2836
2837         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2838                                        cmd_details);
2839
2840         return status;
2841 }
2842
2843 /**
2844  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2845  * @hw: pointer to the hw struct
2846  * @seid: VSI for the vlan filters
2847  * @v_list: list of vlan filters to be added
2848  * @count: length of the list
2849  * @cmd_details: pointer to command details structure or NULL
2850  **/
2851 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2852                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2853                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2854 {
2855         struct i40e_aq_desc desc;
2856         struct i40e_aqc_macvlan *cmd =
2857                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2858         enum i40e_status_code status;
2859         u16 buf_size;
2860
2861         if (count == 0 || !v_list || !hw)
2862                 return I40E_ERR_PARAM;
2863
2864         buf_size = count * sizeof(*v_list);
2865
2866         /* prep the rest of the request */
2867         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2868         cmd->num_addresses = CPU_TO_LE16(count);
2869         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2870         cmd->seid[1] = 0;
2871         cmd->seid[2] = 0;
2872
2873         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2874         if (buf_size > I40E_AQ_LARGE_BUF)
2875                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2876
2877         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2878                                        cmd_details);
2879
2880         return status;
2881 }
2882
2883 /**
2884  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2885  * @hw: pointer to the hw struct
2886  * @seid: VSI for the vlan filters
2887  * @v_list: list of macvlans to be removed
2888  * @count: length of the list
2889  * @cmd_details: pointer to command details structure or NULL
2890  **/
2891 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2892                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2893                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2894 {
2895         struct i40e_aq_desc desc;
2896         struct i40e_aqc_macvlan *cmd =
2897                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2898         enum i40e_status_code status;
2899         u16 buf_size;
2900
2901         if (count == 0 || !v_list || !hw)
2902                 return I40E_ERR_PARAM;
2903
2904         buf_size = count * sizeof(*v_list);
2905
2906         /* prep the rest of the request */
2907         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2908         cmd->num_addresses = CPU_TO_LE16(count);
2909         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2910         cmd->seid[1] = 0;
2911         cmd->seid[2] = 0;
2912
2913         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2914         if (buf_size > I40E_AQ_LARGE_BUF)
2915                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2916
2917         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2918                                        cmd_details);
2919
2920         return status;
2921 }
2922
2923 /**
2924  * i40e_aq_send_msg_to_vf
2925  * @hw: pointer to the hardware structure
2926  * @vfid: vf id to send msg
2927  * @v_opcode: opcodes for VF-PF communication
2928  * @v_retval: return error code
2929  * @msg: pointer to the msg buffer
2930  * @msglen: msg length
2931  * @cmd_details: pointer to command details
2932  *
2933  * send msg to vf
2934  **/
2935 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2936                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2937                                 struct i40e_asq_cmd_details *cmd_details)
2938 {
2939         struct i40e_aq_desc desc;
2940         struct i40e_aqc_pf_vf_message *cmd =
2941                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2942         enum i40e_status_code status;
2943
2944         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2945         cmd->id = CPU_TO_LE32(vfid);
2946         desc.cookie_high = CPU_TO_LE32(v_opcode);
2947         desc.cookie_low = CPU_TO_LE32(v_retval);
2948         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2949         if (msglen) {
2950                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2951                                                 I40E_AQ_FLAG_RD));
2952                 if (msglen > I40E_AQ_LARGE_BUF)
2953                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2954                 desc.datalen = CPU_TO_LE16(msglen);
2955         }
2956         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2957
2958         return status;
2959 }
2960
2961 /**
2962  * i40e_aq_debug_read_register
2963  * @hw: pointer to the hw struct
2964  * @reg_addr: register address
2965  * @reg_val: register value
2966  * @cmd_details: pointer to command details structure or NULL
2967  *
2968  * Read the register using the admin queue commands
2969  **/
2970 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2971                                 u32 reg_addr, u64 *reg_val,
2972                                 struct i40e_asq_cmd_details *cmd_details)
2973 {
2974         struct i40e_aq_desc desc;
2975         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2976                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2977         enum i40e_status_code status;
2978
2979         if (reg_val == NULL)
2980                 return I40E_ERR_PARAM;
2981
2982         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2983
2984         cmd_resp->address = CPU_TO_LE32(reg_addr);
2985
2986         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2987
2988         if (status == I40E_SUCCESS) {
2989                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2990                            (u64)LE32_TO_CPU(cmd_resp->value_low);
2991         }
2992
2993         return status;
2994 }
2995
2996 /**
2997  * i40e_aq_debug_write_register
2998  * @hw: pointer to the hw struct
2999  * @reg_addr: register address
3000  * @reg_val: register value
3001  * @cmd_details: pointer to command details structure or NULL
3002  *
3003  * Write to a register using the admin queue commands
3004  **/
3005 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3006                                 u32 reg_addr, u64 reg_val,
3007                                 struct i40e_asq_cmd_details *cmd_details)
3008 {
3009         struct i40e_aq_desc desc;
3010         struct i40e_aqc_debug_reg_read_write *cmd =
3011                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3012         enum i40e_status_code status;
3013
3014         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3015
3016         cmd->address = CPU_TO_LE32(reg_addr);
3017         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3018         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3019
3020         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3021
3022         return status;
3023 }
3024
3025 /**
3026  * i40e_aq_get_hmc_resource_profile
3027  * @hw: pointer to the hw struct
3028  * @profile: type of profile the HMC is to be set as
3029  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3030  * @cmd_details: pointer to command details structure or NULL
3031  *
3032  * query the HMC profile of the device.
3033  **/
3034 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3035                                 enum i40e_aq_hmc_profile *profile,
3036                                 u8 *pe_vf_enabled_count,
3037                                 struct i40e_asq_cmd_details *cmd_details)
3038 {
3039         struct i40e_aq_desc desc;
3040         struct i40e_aq_get_set_hmc_resource_profile *resp =
3041                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3042         enum i40e_status_code status;
3043
3044         i40e_fill_default_direct_cmd_desc(&desc,
3045                                 i40e_aqc_opc_query_hmc_resource_profile);
3046         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3047
3048         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3049                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3050         *pe_vf_enabled_count = resp->pe_vf_enabled &
3051                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3052
3053         return status;
3054 }
3055
3056 /**
3057  * i40e_aq_set_hmc_resource_profile
3058  * @hw: pointer to the hw struct
3059  * @profile: type of profile the HMC is to be set as
3060  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3061  * @cmd_details: pointer to command details structure or NULL
3062  *
3063  * set the HMC profile of the device.
3064  **/
3065 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3066                                 enum i40e_aq_hmc_profile profile,
3067                                 u8 pe_vf_enabled_count,
3068                                 struct i40e_asq_cmd_details *cmd_details)
3069 {
3070         struct i40e_aq_desc desc;
3071         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3072                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3073         enum i40e_status_code status;
3074
3075         i40e_fill_default_direct_cmd_desc(&desc,
3076                                         i40e_aqc_opc_set_hmc_resource_profile);
3077
3078         cmd->pm_profile = (u8)profile;
3079         cmd->pe_vf_enabled = pe_vf_enabled_count;
3080
3081         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3082
3083         return status;
3084 }
3085
3086 /**
3087  * i40e_aq_request_resource
3088  * @hw: pointer to the hw struct
3089  * @resource: resource id
3090  * @access: access type
3091  * @sdp_number: resource number
3092  * @timeout: the maximum time in ms that the driver may hold the resource
3093  * @cmd_details: pointer to command details structure or NULL
3094  *
3095  * requests common resource using the admin queue commands
3096  **/
3097 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3098                                 enum i40e_aq_resources_ids resource,
3099                                 enum i40e_aq_resource_access_type access,
3100                                 u8 sdp_number, u64 *timeout,
3101                                 struct i40e_asq_cmd_details *cmd_details)
3102 {
3103         struct i40e_aq_desc desc;
3104         struct i40e_aqc_request_resource *cmd_resp =
3105                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3106         enum i40e_status_code status;
3107
3108         DEBUGFUNC("i40e_aq_request_resource");
3109
3110         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3111
3112         cmd_resp->resource_id = CPU_TO_LE16(resource);
3113         cmd_resp->access_type = CPU_TO_LE16(access);
3114         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3115
3116         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3117         /* The completion specifies the maximum time in ms that the driver
3118          * may hold the resource in the Timeout field.
3119          * If the resource is held by someone else, the command completes with
3120          * busy return value and the timeout field indicates the maximum time
3121          * the current owner of the resource has to free it.
3122          */
3123         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3124                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3125
3126         return status;
3127 }
3128
3129 /**
3130  * i40e_aq_release_resource
3131  * @hw: pointer to the hw struct
3132  * @resource: resource id
3133  * @sdp_number: resource number
3134  * @cmd_details: pointer to command details structure or NULL
3135  *
3136  * release common resource using the admin queue commands
3137  **/
3138 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3139                                 enum i40e_aq_resources_ids resource,
3140                                 u8 sdp_number,
3141                                 struct i40e_asq_cmd_details *cmd_details)
3142 {
3143         struct i40e_aq_desc desc;
3144         struct i40e_aqc_request_resource *cmd =
3145                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3146         enum i40e_status_code status;
3147
3148         DEBUGFUNC("i40e_aq_release_resource");
3149
3150         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3151
3152         cmd->resource_id = CPU_TO_LE16(resource);
3153         cmd->resource_number = CPU_TO_LE32(sdp_number);
3154
3155         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3156
3157         return status;
3158 }
3159
3160 /**
3161  * i40e_aq_read_nvm
3162  * @hw: pointer to the hw struct
3163  * @module_pointer: module pointer location in words from the NVM beginning
3164  * @offset: byte offset from the module beginning
3165  * @length: length of the section to be read (in bytes from the offset)
3166  * @data: command buffer (size [bytes] = length)
3167  * @last_command: tells if this is the last command in a series
3168  * @cmd_details: pointer to command details structure or NULL
3169  *
3170  * Read the NVM using the admin queue commands
3171  **/
3172 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3173                                 u32 offset, u16 length, void *data,
3174                                 bool last_command,
3175                                 struct i40e_asq_cmd_details *cmd_details)
3176 {
3177         struct i40e_aq_desc desc;
3178         struct i40e_aqc_nvm_update *cmd =
3179                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3180         enum i40e_status_code status;
3181
3182         DEBUGFUNC("i40e_aq_read_nvm");
3183
3184         /* In offset the highest byte must be zeroed. */
3185         if (offset & 0xFF000000) {
3186                 status = I40E_ERR_PARAM;
3187                 goto i40e_aq_read_nvm_exit;
3188         }
3189
3190         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3191
3192         /* If this is the last command in a series, set the proper flag. */
3193         if (last_command)
3194                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3195         cmd->module_pointer = module_pointer;
3196         cmd->offset = CPU_TO_LE32(offset);
3197         cmd->length = CPU_TO_LE16(length);
3198
3199         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3200         if (length > I40E_AQ_LARGE_BUF)
3201                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3202
3203         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3204
3205 i40e_aq_read_nvm_exit:
3206         return status;
3207 }
3208
3209 /**
3210  * i40e_aq_read_nvm_config - read an nvm config block
3211  * @hw: pointer to the hw struct
3212  * @cmd_flags: NVM access admin command bits
3213  * @field_id: field or feature id
3214  * @data: buffer for result
3215  * @buf_size: buffer size
3216  * @element_count: pointer to count of elements read by FW
3217  * @cmd_details: pointer to command details structure or NULL
3218  **/
3219 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3220                                 u8 cmd_flags, u32 field_id, void *data,
3221                                 u16 buf_size, u16 *element_count,
3222                                 struct i40e_asq_cmd_details *cmd_details)
3223 {
3224         struct i40e_aq_desc desc;
3225         struct i40e_aqc_nvm_config_read *cmd =
3226                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3227         enum i40e_status_code status;
3228
3229         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3230         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3231         if (buf_size > I40E_AQ_LARGE_BUF)
3232                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3233
3234         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3235         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3236         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3237                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3238         else
3239                 cmd->element_id_msw = 0;
3240
3241         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3242
3243         if (!status && element_count)
3244                 *element_count = LE16_TO_CPU(cmd->element_count);
3245
3246         return status;
3247 }
3248
3249 /**
3250  * i40e_aq_write_nvm_config - write an nvm config block
3251  * @hw: pointer to the hw struct
3252  * @cmd_flags: NVM access admin command bits
3253  * @data: buffer for result
3254  * @buf_size: buffer size
3255  * @element_count: count of elements to be written
3256  * @cmd_details: pointer to command details structure or NULL
3257  **/
3258 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3259                                 u8 cmd_flags, void *data, u16 buf_size,
3260                                 u16 element_count,
3261                                 struct i40e_asq_cmd_details *cmd_details)
3262 {
3263         struct i40e_aq_desc desc;
3264         struct i40e_aqc_nvm_config_write *cmd =
3265                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3266         enum i40e_status_code status;
3267
3268         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3269         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3270         if (buf_size > I40E_AQ_LARGE_BUF)
3271                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3272
3273         cmd->element_count = CPU_TO_LE16(element_count);
3274         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3275         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3276
3277         return status;
3278 }
3279
3280 /**
3281  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3282  * @hw: pointer to the hw struct
3283  * @cmd_details: pointer to command details structure or NULL
3284  **/
3285 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3286                                 void *buff, u16 buff_size,
3287                                 struct i40e_asq_cmd_details *cmd_details)
3288 {
3289         struct i40e_aq_desc desc;
3290         enum i40e_status_code status;
3291
3292         UNREFERENCED_2PARAMETER(buff, buff_size);
3293
3294         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3295         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3296         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3297                 status = I40E_ERR_NOT_IMPLEMENTED;
3298
3299         return status;
3300 }
3301
3302 /**
3303  * i40e_aq_erase_nvm
3304  * @hw: pointer to the hw struct
3305  * @module_pointer: module pointer location in words from the NVM beginning
3306  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3307  * @length: length of the section to be erased (expressed in 4 KB)
3308  * @last_command: tells if this is the last command in a series
3309  * @cmd_details: pointer to command details structure or NULL
3310  *
3311  * Erase the NVM sector using the admin queue commands
3312  **/
3313 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3314                                 u32 offset, u16 length, bool last_command,
3315                                 struct i40e_asq_cmd_details *cmd_details)
3316 {
3317         struct i40e_aq_desc desc;
3318         struct i40e_aqc_nvm_update *cmd =
3319                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3320         enum i40e_status_code status;
3321
3322         DEBUGFUNC("i40e_aq_erase_nvm");
3323
3324         /* In offset the highest byte must be zeroed. */
3325         if (offset & 0xFF000000) {
3326                 status = I40E_ERR_PARAM;
3327                 goto i40e_aq_erase_nvm_exit;
3328         }
3329
3330         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3331
3332         /* If this is the last command in a series, set the proper flag. */
3333         if (last_command)
3334                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3335         cmd->module_pointer = module_pointer;
3336         cmd->offset = CPU_TO_LE32(offset);
3337         cmd->length = CPU_TO_LE16(length);
3338
3339         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3340
3341 i40e_aq_erase_nvm_exit:
3342         return status;
3343 }
3344
3345 /**
3346  * i40e_parse_discover_capabilities
3347  * @hw: pointer to the hw struct
3348  * @buff: pointer to a buffer containing device/function capability records
3349  * @cap_count: number of capability records in the list
3350  * @list_type_opc: type of capabilities list to parse
3351  *
3352  * Parse the device/function capabilities list.
3353  **/
3354 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3355                                      u32 cap_count,
3356                                      enum i40e_admin_queue_opc list_type_opc)
3357 {
3358         struct i40e_aqc_list_capabilities_element_resp *cap;
3359         u32 valid_functions, num_functions;
3360         u32 number, logical_id, phys_id;
3361         struct i40e_hw_capabilities *p;
3362         u8 major_rev;
3363         u32 i = 0;
3364         u16 id;
3365
3366         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3367
3368         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3369                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3370         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3371                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3372         else
3373                 return;
3374
3375         for (i = 0; i < cap_count; i++, cap++) {
3376                 id = LE16_TO_CPU(cap->id);
3377                 number = LE32_TO_CPU(cap->number);
3378                 logical_id = LE32_TO_CPU(cap->logical_id);
3379                 phys_id = LE32_TO_CPU(cap->phys_id);
3380                 major_rev = cap->major_rev;
3381
3382                 switch (id) {
3383                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3384                         p->switch_mode = number;
3385                         i40e_debug(hw, I40E_DEBUG_INIT,
3386                                    "HW Capability: Switch mode = %d\n",
3387                                    p->switch_mode);
3388                         break;
3389                 case I40E_AQ_CAP_ID_MNG_MODE:
3390                         p->management_mode = number;
3391                         i40e_debug(hw, I40E_DEBUG_INIT,
3392                                    "HW Capability: Management Mode = %d\n",
3393                                    p->management_mode);
3394                         break;
3395                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3396                         p->npar_enable = number;
3397                         i40e_debug(hw, I40E_DEBUG_INIT,
3398                                    "HW Capability: NPAR enable = %d\n",
3399                                    p->npar_enable);
3400                         break;
3401                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3402                         p->os2bmc = number;
3403                         i40e_debug(hw, I40E_DEBUG_INIT,
3404                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3405                         break;
3406                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3407                         p->valid_functions = number;
3408                         i40e_debug(hw, I40E_DEBUG_INIT,
3409                                    "HW Capability: Valid Functions = %d\n",
3410                                    p->valid_functions);
3411                         break;
3412                 case I40E_AQ_CAP_ID_SRIOV:
3413                         if (number == 1)
3414                                 p->sr_iov_1_1 = true;
3415                         i40e_debug(hw, I40E_DEBUG_INIT,
3416                                    "HW Capability: SR-IOV = %d\n",
3417                                    p->sr_iov_1_1);
3418                         break;
3419                 case I40E_AQ_CAP_ID_VF:
3420                         p->num_vfs = number;
3421                         p->vf_base_id = logical_id;
3422                         i40e_debug(hw, I40E_DEBUG_INIT,
3423                                    "HW Capability: VF count = %d\n",
3424                                    p->num_vfs);
3425                         i40e_debug(hw, I40E_DEBUG_INIT,
3426                                    "HW Capability: VF base_id = %d\n",
3427                                    p->vf_base_id);
3428                         break;
3429                 case I40E_AQ_CAP_ID_VMDQ:
3430                         if (number == 1)
3431                                 p->vmdq = true;
3432                         i40e_debug(hw, I40E_DEBUG_INIT,
3433                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3434                         break;
3435                 case I40E_AQ_CAP_ID_8021QBG:
3436                         if (number == 1)
3437                                 p->evb_802_1_qbg = true;
3438                         i40e_debug(hw, I40E_DEBUG_INIT,
3439                                    "HW Capability: 802.1Qbg = %d\n", number);
3440                         break;
3441                 case I40E_AQ_CAP_ID_8021QBR:
3442                         if (number == 1)
3443                                 p->evb_802_1_qbh = true;
3444                         i40e_debug(hw, I40E_DEBUG_INIT,
3445                                    "HW Capability: 802.1Qbh = %d\n", number);
3446                         break;
3447                 case I40E_AQ_CAP_ID_VSI:
3448                         p->num_vsis = number;
3449                         i40e_debug(hw, I40E_DEBUG_INIT,
3450                                    "HW Capability: VSI count = %d\n",
3451                                    p->num_vsis);
3452                         break;
3453                 case I40E_AQ_CAP_ID_DCB:
3454                         if (number == 1) {
3455                                 p->dcb = true;
3456                                 p->enabled_tcmap = logical_id;
3457                                 p->maxtc = phys_id;
3458                         }
3459                         i40e_debug(hw, I40E_DEBUG_INIT,
3460                                    "HW Capability: DCB = %d\n", p->dcb);
3461                         i40e_debug(hw, I40E_DEBUG_INIT,
3462                                    "HW Capability: TC Mapping = %d\n",
3463                                    logical_id);
3464                         i40e_debug(hw, I40E_DEBUG_INIT,
3465                                    "HW Capability: TC Max = %d\n", p->maxtc);
3466                         break;
3467                 case I40E_AQ_CAP_ID_FCOE:
3468                         if (number == 1)
3469                                 p->fcoe = true;
3470                         i40e_debug(hw, I40E_DEBUG_INIT,
3471                                    "HW Capability: FCOE = %d\n", p->fcoe);
3472                         break;
3473                 case I40E_AQ_CAP_ID_ISCSI:
3474                         if (number == 1)
3475                                 p->iscsi = true;
3476                         i40e_debug(hw, I40E_DEBUG_INIT,
3477                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3478                         break;
3479                 case I40E_AQ_CAP_ID_RSS:
3480                         p->rss = true;
3481                         p->rss_table_size = number;
3482                         p->rss_table_entry_width = logical_id;
3483                         i40e_debug(hw, I40E_DEBUG_INIT,
3484                                    "HW Capability: RSS = %d\n", p->rss);
3485                         i40e_debug(hw, I40E_DEBUG_INIT,
3486                                    "HW Capability: RSS table size = %d\n",
3487                                    p->rss_table_size);
3488                         i40e_debug(hw, I40E_DEBUG_INIT,
3489                                    "HW Capability: RSS table width = %d\n",
3490                                    p->rss_table_entry_width);
3491                         break;
3492                 case I40E_AQ_CAP_ID_RXQ:
3493                         p->num_rx_qp = number;
3494                         p->base_queue = phys_id;
3495                         i40e_debug(hw, I40E_DEBUG_INIT,
3496                                    "HW Capability: Rx QP = %d\n", number);
3497                         i40e_debug(hw, I40E_DEBUG_INIT,
3498                                    "HW Capability: base_queue = %d\n",
3499                                    p->base_queue);
3500                         break;
3501                 case I40E_AQ_CAP_ID_TXQ:
3502                         p->num_tx_qp = number;
3503                         p->base_queue = phys_id;
3504                         i40e_debug(hw, I40E_DEBUG_INIT,
3505                                    "HW Capability: Tx QP = %d\n", number);
3506                         i40e_debug(hw, I40E_DEBUG_INIT,
3507                                    "HW Capability: base_queue = %d\n",
3508                                    p->base_queue);
3509                         break;
3510                 case I40E_AQ_CAP_ID_MSIX:
3511                         p->num_msix_vectors = number;
3512                         i40e_debug(hw, I40E_DEBUG_INIT,
3513                                    "HW Capability: MSIX vector count = %d\n",
3514                                    p->num_msix_vectors_vf);
3515                         break;
3516                 case I40E_AQ_CAP_ID_VF_MSIX:
3517                         p->num_msix_vectors_vf = number;
3518                         i40e_debug(hw, I40E_DEBUG_INIT,
3519                                    "HW Capability: MSIX VF vector count = %d\n",
3520                                    p->num_msix_vectors_vf);
3521                         break;
3522                 case I40E_AQ_CAP_ID_FLEX10:
3523                         if (major_rev == 1) {
3524                                 if (number == 1) {
3525                                         p->flex10_enable = true;
3526                                         p->flex10_capable = true;
3527                                 }
3528                         } else {
3529                                 /* Capability revision >= 2 */
3530                                 if (number & 1)
3531                                         p->flex10_enable = true;
3532                                 if (number & 2)
3533                                         p->flex10_capable = true;
3534                         }
3535                         p->flex10_mode = logical_id;
3536                         p->flex10_status = phys_id;
3537                         i40e_debug(hw, I40E_DEBUG_INIT,
3538                                    "HW Capability: Flex10 mode = %d\n",
3539                                    p->flex10_mode);
3540                         i40e_debug(hw, I40E_DEBUG_INIT,
3541                                    "HW Capability: Flex10 status = %d\n",
3542                                    p->flex10_status);
3543                         break;
3544                 case I40E_AQ_CAP_ID_CEM:
3545                         if (number == 1)
3546                                 p->mgmt_cem = true;
3547                         i40e_debug(hw, I40E_DEBUG_INIT,
3548                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3549                         break;
3550                 case I40E_AQ_CAP_ID_IWARP:
3551                         if (number == 1)
3552                                 p->iwarp = true;
3553                         i40e_debug(hw, I40E_DEBUG_INIT,
3554                                    "HW Capability: iWARP = %d\n", p->iwarp);
3555                         break;
3556                 case I40E_AQ_CAP_ID_LED:
3557                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3558                                 p->led[phys_id] = true;
3559                         i40e_debug(hw, I40E_DEBUG_INIT,
3560                                    "HW Capability: LED - PIN %d\n", phys_id);
3561                         break;
3562                 case I40E_AQ_CAP_ID_SDP:
3563                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3564                                 p->sdp[phys_id] = true;
3565                         i40e_debug(hw, I40E_DEBUG_INIT,
3566                                    "HW Capability: SDP - PIN %d\n", phys_id);
3567                         break;
3568                 case I40E_AQ_CAP_ID_MDIO:
3569                         if (number == 1) {
3570                                 p->mdio_port_num = phys_id;
3571                                 p->mdio_port_mode = logical_id;
3572                         }
3573                         i40e_debug(hw, I40E_DEBUG_INIT,
3574                                    "HW Capability: MDIO port number = %d\n",
3575                                    p->mdio_port_num);
3576                         i40e_debug(hw, I40E_DEBUG_INIT,
3577                                    "HW Capability: MDIO port mode = %d\n",
3578                                    p->mdio_port_mode);
3579                         break;
3580                 case I40E_AQ_CAP_ID_1588:
3581                         if (number == 1)
3582                                 p->ieee_1588 = true;
3583                         i40e_debug(hw, I40E_DEBUG_INIT,
3584                                    "HW Capability: IEEE 1588 = %d\n",
3585                                    p->ieee_1588);
3586                         break;
3587                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3588                         p->fd = true;
3589                         p->fd_filters_guaranteed = number;
3590                         p->fd_filters_best_effort = logical_id;
3591                         i40e_debug(hw, I40E_DEBUG_INIT,
3592                                    "HW Capability: Flow Director = 1\n");
3593                         i40e_debug(hw, I40E_DEBUG_INIT,
3594                                    "HW Capability: Guaranteed FD filters = %d\n",
3595                                    p->fd_filters_guaranteed);
3596                         break;
3597                 case I40E_AQ_CAP_ID_WSR_PROT:
3598                         p->wr_csr_prot = (u64)number;
3599                         p->wr_csr_prot |= (u64)logical_id << 32;
3600                         i40e_debug(hw, I40E_DEBUG_INIT,
3601                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3602                                    (p->wr_csr_prot & 0xffff));
3603                         break;
3604 #ifdef X722_SUPPORT
3605                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3606                         hw->num_wol_proxy_filters = (u16)number;
3607                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3608                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3609                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3610                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3611                         else
3612                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3613                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3614                         p->proxy_support = p->proxy_support;
3615                         i40e_debug(hw, I40E_DEBUG_INIT,
3616                                    "HW Capability: WOL proxy filters = %d\n",
3617                                    hw->num_wol_proxy_filters);
3618                         break;
3619 #endif
3620                 default:
3621                         break;
3622                 }
3623         }
3624
3625         if (p->fcoe)
3626                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3627
3628 #ifdef I40E_FCOE_ENA
3629         /* Software override ensuring FCoE is disabled if npar or mfp
3630          * mode because it is not supported in these modes.
3631          */
3632         if (p->npar_enable || p->flex10_enable)
3633                 p->fcoe = false;
3634 #else
3635         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3636         p->fcoe = false;
3637 #endif
3638
3639         /* count the enabled ports (aka the "not disabled" ports) */
3640         hw->num_ports = 0;
3641         for (i = 0; i < 4; i++) {
3642                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3643                 u64 port_cfg = 0;
3644
3645                 /* use AQ read to get the physical register offset instead
3646                  * of the port relative offset
3647                  */
3648                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3649                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3650                         hw->num_ports++;
3651         }
3652
3653         valid_functions = p->valid_functions;
3654         num_functions = 0;
3655         while (valid_functions) {
3656                 if (valid_functions & 1)
3657                         num_functions++;
3658                 valid_functions >>= 1;
3659         }
3660
3661         /* partition id is 1-based, and functions are evenly spread
3662          * across the ports as partitions
3663          */
3664         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3665         hw->num_partitions = num_functions / hw->num_ports;
3666
3667         /* additional HW specific goodies that might
3668          * someday be HW version specific
3669          */
3670         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3671 }
3672
3673 /**
3674  * i40e_aq_discover_capabilities
3675  * @hw: pointer to the hw struct
3676  * @buff: a virtual buffer to hold the capabilities
3677  * @buff_size: Size of the virtual buffer
3678  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3679  * @list_type_opc: capabilities type to discover - pass in the command opcode
3680  * @cmd_details: pointer to command details structure or NULL
3681  *
3682  * Get the device capabilities descriptions from the firmware
3683  **/
3684 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3685                                 void *buff, u16 buff_size, u16 *data_size,
3686                                 enum i40e_admin_queue_opc list_type_opc,
3687                                 struct i40e_asq_cmd_details *cmd_details)
3688 {
3689         struct i40e_aqc_list_capabilites *cmd;
3690         struct i40e_aq_desc desc;
3691         enum i40e_status_code status = I40E_SUCCESS;
3692
3693         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3694
3695         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3696                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3697                 status = I40E_ERR_PARAM;
3698                 goto exit;
3699         }
3700
3701         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3702
3703         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3704         if (buff_size > I40E_AQ_LARGE_BUF)
3705                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3706
3707         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3708         *data_size = LE16_TO_CPU(desc.datalen);
3709
3710         if (status)
3711                 goto exit;
3712
3713         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3714                                          list_type_opc);
3715
3716 exit:
3717         return status;
3718 }
3719
3720 /**
3721  * i40e_aq_update_nvm
3722  * @hw: pointer to the hw struct
3723  * @module_pointer: module pointer location in words from the NVM beginning
3724  * @offset: byte offset from the module beginning
3725  * @length: length of the section to be written (in bytes from the offset)
3726  * @data: command buffer (size [bytes] = length)
3727  * @last_command: tells if this is the last command in a series
3728  * @cmd_details: pointer to command details structure or NULL
3729  *
3730  * Update the NVM using the admin queue commands
3731  **/
3732 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3733                                 u32 offset, u16 length, void *data,
3734                                 bool last_command,
3735                                 struct i40e_asq_cmd_details *cmd_details)
3736 {
3737         struct i40e_aq_desc desc;
3738         struct i40e_aqc_nvm_update *cmd =
3739                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3740         enum i40e_status_code status;
3741
3742         DEBUGFUNC("i40e_aq_update_nvm");
3743
3744         /* In offset the highest byte must be zeroed. */
3745         if (offset & 0xFF000000) {
3746                 status = I40E_ERR_PARAM;
3747                 goto i40e_aq_update_nvm_exit;
3748         }
3749
3750         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3751
3752         /* If this is the last command in a series, set the proper flag. */
3753         if (last_command)
3754                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3755         cmd->module_pointer = module_pointer;
3756         cmd->offset = CPU_TO_LE32(offset);
3757         cmd->length = CPU_TO_LE16(length);
3758
3759         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3760         if (length > I40E_AQ_LARGE_BUF)
3761                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3762
3763         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3764
3765 i40e_aq_update_nvm_exit:
3766         return status;
3767 }
3768
3769 /**
3770  * i40e_aq_get_lldp_mib
3771  * @hw: pointer to the hw struct
3772  * @bridge_type: type of bridge requested
3773  * @mib_type: Local, Remote or both Local and Remote MIBs
3774  * @buff: pointer to a user supplied buffer to store the MIB block
3775  * @buff_size: size of the buffer (in bytes)
3776  * @local_len : length of the returned Local LLDP MIB
3777  * @remote_len: length of the returned Remote LLDP MIB
3778  * @cmd_details: pointer to command details structure or NULL
3779  *
3780  * Requests the complete LLDP MIB (entire packet).
3781  **/
3782 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3783                                 u8 mib_type, void *buff, u16 buff_size,
3784                                 u16 *local_len, u16 *remote_len,
3785                                 struct i40e_asq_cmd_details *cmd_details)
3786 {
3787         struct i40e_aq_desc desc;
3788         struct i40e_aqc_lldp_get_mib *cmd =
3789                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3790         struct i40e_aqc_lldp_get_mib *resp =
3791                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3792         enum i40e_status_code status;
3793
3794         if (buff_size == 0 || !buff)
3795                 return I40E_ERR_PARAM;
3796
3797         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3798         /* Indirect Command */
3799         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3800
3801         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3802         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3803                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3804
3805         desc.datalen = CPU_TO_LE16(buff_size);
3806
3807         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3808         if (buff_size > I40E_AQ_LARGE_BUF)
3809                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3810
3811         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3812         if (!status) {
3813                 if (local_len != NULL)
3814                         *local_len = LE16_TO_CPU(resp->local_len);
3815                 if (remote_len != NULL)
3816                         *remote_len = LE16_TO_CPU(resp->remote_len);
3817         }
3818
3819         return status;
3820 }
3821
3822  /**
3823  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3824  * @hw: pointer to the hw struct
3825  * @mib_type: Local, Remote or both Local and Remote MIBs
3826  * @buff: pointer to a user supplied buffer to store the MIB block
3827  * @buff_size: size of the buffer (in bytes)
3828  * @cmd_details: pointer to command details structure or NULL
3829  *
3830  * Set the LLDP MIB.
3831  **/
3832 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3833                                 u8 mib_type, void *buff, u16 buff_size,
3834                                 struct i40e_asq_cmd_details *cmd_details)
3835 {
3836         struct i40e_aq_desc desc;
3837         struct i40e_aqc_lldp_set_local_mib *cmd =
3838                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3839         enum i40e_status_code status;
3840
3841         if (buff_size == 0 || !buff)
3842                 return I40E_ERR_PARAM;
3843
3844         i40e_fill_default_direct_cmd_desc(&desc,
3845                                 i40e_aqc_opc_lldp_set_local_mib);
3846         /* Indirect Command */
3847         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3848         if (buff_size > I40E_AQ_LARGE_BUF)
3849                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3850         desc.datalen = CPU_TO_LE16(buff_size);
3851
3852         cmd->type = mib_type;
3853         cmd->length = CPU_TO_LE16(buff_size);
3854         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3855         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3856
3857         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3858         return status;
3859 }
3860
3861 /**
3862  * i40e_aq_cfg_lldp_mib_change_event
3863  * @hw: pointer to the hw struct
3864  * @enable_update: Enable or Disable event posting
3865  * @cmd_details: pointer to command details structure or NULL
3866  *
3867  * Enable or Disable posting of an event on ARQ when LLDP MIB
3868  * associated with the interface changes
3869  **/
3870 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3871                                 bool enable_update,
3872                                 struct i40e_asq_cmd_details *cmd_details)
3873 {
3874         struct i40e_aq_desc desc;
3875         struct i40e_aqc_lldp_update_mib *cmd =
3876                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3877         enum i40e_status_code status;
3878
3879         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3880
3881         if (!enable_update)
3882                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3883
3884         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3885
3886         return status;
3887 }
3888
3889 /**
3890  * i40e_aq_add_lldp_tlv
3891  * @hw: pointer to the hw struct
3892  * @bridge_type: type of bridge
3893  * @buff: buffer with TLV to add
3894  * @buff_size: length of the buffer
3895  * @tlv_len: length of the TLV to be added
3896  * @mib_len: length of the LLDP MIB returned in response
3897  * @cmd_details: pointer to command details structure or NULL
3898  *
3899  * Add the specified TLV to LLDP Local MIB for the given bridge type,
3900  * it is responsibility of the caller to make sure that the TLV is not
3901  * already present in the LLDPDU.
3902  * In return firmware will write the complete LLDP MIB with the newly
3903  * added TLV in the response buffer.
3904  **/
3905 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3906                                 void *buff, u16 buff_size, u16 tlv_len,
3907                                 u16 *mib_len,
3908                                 struct i40e_asq_cmd_details *cmd_details)
3909 {
3910         struct i40e_aq_desc desc;
3911         struct i40e_aqc_lldp_add_tlv *cmd =
3912                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3913         enum i40e_status_code status;
3914
3915         if (buff_size == 0 || !buff || tlv_len == 0)
3916                 return I40E_ERR_PARAM;
3917
3918         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3919
3920         /* Indirect Command */
3921         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3922         if (buff_size > I40E_AQ_LARGE_BUF)
3923                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3924         desc.datalen = CPU_TO_LE16(buff_size);
3925
3926         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3927                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3928         cmd->len = CPU_TO_LE16(tlv_len);
3929
3930         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3931         if (!status) {
3932                 if (mib_len != NULL)
3933                         *mib_len = LE16_TO_CPU(desc.datalen);
3934         }
3935
3936         return status;
3937 }
3938
3939 /**
3940  * i40e_aq_update_lldp_tlv
3941  * @hw: pointer to the hw struct
3942  * @bridge_type: type of bridge
3943  * @buff: buffer with TLV to update
3944  * @buff_size: size of the buffer holding original and updated TLVs
3945  * @old_len: Length of the Original TLV
3946  * @new_len: Length of the Updated TLV
3947  * @offset: offset of the updated TLV in the buff
3948  * @mib_len: length of the returned LLDP MIB
3949  * @cmd_details: pointer to command details structure or NULL
3950  *
3951  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3952  * Firmware will place the complete LLDP MIB in response buffer with the
3953  * updated TLV.
3954  **/
3955 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3956                                 u8 bridge_type, void *buff, u16 buff_size,
3957                                 u16 old_len, u16 new_len, u16 offset,
3958                                 u16 *mib_len,
3959                                 struct i40e_asq_cmd_details *cmd_details)
3960 {
3961         struct i40e_aq_desc desc;
3962         struct i40e_aqc_lldp_update_tlv *cmd =
3963                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3964         enum i40e_status_code status;
3965
3966         if (buff_size == 0 || !buff || offset == 0 ||
3967             old_len == 0 || new_len == 0)
3968                 return I40E_ERR_PARAM;
3969
3970         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3971
3972         /* Indirect Command */
3973         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3974         if (buff_size > I40E_AQ_LARGE_BUF)
3975                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3976         desc.datalen = CPU_TO_LE16(buff_size);
3977
3978         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3979                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3980         cmd->old_len = CPU_TO_LE16(old_len);
3981         cmd->new_offset = CPU_TO_LE16(offset);
3982         cmd->new_len = CPU_TO_LE16(new_len);
3983
3984         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3985         if (!status) {
3986                 if (mib_len != NULL)
3987                         *mib_len = LE16_TO_CPU(desc.datalen);
3988         }
3989
3990         return status;
3991 }
3992
3993 /**
3994  * i40e_aq_delete_lldp_tlv
3995  * @hw: pointer to the hw struct
3996  * @bridge_type: type of bridge
3997  * @buff: pointer to a user supplied buffer that has the TLV
3998  * @buff_size: length of the buffer
3999  * @tlv_len: length of the TLV to be deleted
4000  * @mib_len: length of the returned LLDP MIB
4001  * @cmd_details: pointer to command details structure or NULL
4002  *
4003  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4004  * The firmware places the entire LLDP MIB in the response buffer.
4005  **/
4006 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4007                                 u8 bridge_type, void *buff, u16 buff_size,
4008                                 u16 tlv_len, u16 *mib_len,
4009                                 struct i40e_asq_cmd_details *cmd_details)
4010 {
4011         struct i40e_aq_desc desc;
4012         struct i40e_aqc_lldp_add_tlv *cmd =
4013                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4014         enum i40e_status_code status;
4015
4016         if (buff_size == 0 || !buff)
4017                 return I40E_ERR_PARAM;
4018
4019         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4020
4021         /* Indirect Command */
4022         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4023         if (buff_size > I40E_AQ_LARGE_BUF)
4024                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4025         desc.datalen = CPU_TO_LE16(buff_size);
4026         cmd->len = CPU_TO_LE16(tlv_len);
4027         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4028                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4029
4030         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4031         if (!status) {
4032                 if (mib_len != NULL)
4033                         *mib_len = LE16_TO_CPU(desc.datalen);
4034         }
4035
4036         return status;
4037 }
4038
4039 /**
4040  * i40e_aq_stop_lldp
4041  * @hw: pointer to the hw struct
4042  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4043  * @cmd_details: pointer to command details structure or NULL
4044  *
4045  * Stop or Shutdown the embedded LLDP Agent
4046  **/
4047 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4048                                 struct i40e_asq_cmd_details *cmd_details)
4049 {
4050         struct i40e_aq_desc desc;
4051         struct i40e_aqc_lldp_stop *cmd =
4052                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4053         enum i40e_status_code status;
4054
4055         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4056
4057         if (shutdown_agent)
4058                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4059
4060         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4061
4062         return status;
4063 }
4064
4065 /**
4066  * i40e_aq_start_lldp
4067  * @hw: pointer to the hw struct
4068  * @cmd_details: pointer to command details structure or NULL
4069  *
4070  * Start the embedded LLDP Agent on all ports.
4071  **/
4072 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4073                                 struct i40e_asq_cmd_details *cmd_details)
4074 {
4075         struct i40e_aq_desc desc;
4076         struct i40e_aqc_lldp_start *cmd =
4077                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4078         enum i40e_status_code status;
4079
4080         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4081
4082         cmd->command = I40E_AQ_LLDP_AGENT_START;
4083
4084         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4085
4086         return status;
4087 }
4088
4089 /**
4090  * i40e_aq_get_cee_dcb_config
4091  * @hw: pointer to the hw struct
4092  * @buff: response buffer that stores CEE operational configuration
4093  * @buff_size: size of the buffer passed
4094  * @cmd_details: pointer to command details structure or NULL
4095  *
4096  * Get CEE DCBX mode operational configuration from firmware
4097  **/
4098 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4099                                 void *buff, u16 buff_size,
4100                                 struct i40e_asq_cmd_details *cmd_details)
4101 {
4102         struct i40e_aq_desc desc;
4103         enum i40e_status_code status;
4104
4105         if (buff_size == 0 || !buff)
4106                 return I40E_ERR_PARAM;
4107
4108         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4109
4110         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4111         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4112                                        cmd_details);
4113
4114         return status;
4115 }
4116
4117 /**
4118  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4119  * @hw: pointer to the hw struct
4120  * @start_agent: True if DCBx Agent needs to be Started
4121  *                              False if DCBx Agent needs to be Stopped
4122  * @cmd_details: pointer to command details structure or NULL
4123  *
4124  * Start/Stop the embedded dcbx Agent
4125  **/
4126 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4127                                 bool start_agent,
4128                                 struct i40e_asq_cmd_details *cmd_details)
4129 {
4130         struct i40e_aq_desc desc;
4131         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4132                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4133                                 &desc.params.raw;
4134         enum i40e_status_code status;
4135
4136         i40e_fill_default_direct_cmd_desc(&desc,
4137                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4138
4139         if (start_agent)
4140                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4141
4142         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4143
4144         return status;
4145 }
4146
4147 /**
4148  * i40e_aq_add_udp_tunnel
4149  * @hw: pointer to the hw struct
4150  * @udp_port: the UDP port to add
4151  * @header_len: length of the tunneling header length in DWords
4152  * @protocol_index: protocol index type
4153  * @filter_index: pointer to filter index
4154  * @cmd_details: pointer to command details structure or NULL
4155  **/
4156 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4157                                 u16 udp_port, u8 protocol_index,
4158                                 u8 *filter_index,
4159                                 struct i40e_asq_cmd_details *cmd_details)
4160 {
4161         struct i40e_aq_desc desc;
4162         struct i40e_aqc_add_udp_tunnel *cmd =
4163                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4164         struct i40e_aqc_del_udp_tunnel_completion *resp =
4165                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4166         enum i40e_status_code status;
4167
4168         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4169
4170         cmd->udp_port = CPU_TO_LE16(udp_port);
4171         cmd->protocol_type = protocol_index;
4172
4173         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4174
4175         if (!status && filter_index)
4176                 *filter_index = resp->index;
4177
4178         return status;
4179 }
4180
4181 /**
4182  * i40e_aq_del_udp_tunnel
4183  * @hw: pointer to the hw struct
4184  * @index: filter index
4185  * @cmd_details: pointer to command details structure or NULL
4186  **/
4187 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4188                                 struct i40e_asq_cmd_details *cmd_details)
4189 {
4190         struct i40e_aq_desc desc;
4191         struct i40e_aqc_remove_udp_tunnel *cmd =
4192                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4193         enum i40e_status_code status;
4194
4195         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4196
4197         cmd->index = index;
4198
4199         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4200
4201         return status;
4202 }
4203
4204 /**
4205  * i40e_aq_get_switch_resource_alloc (0x0204)
4206  * @hw: pointer to the hw struct
4207  * @num_entries: pointer to u8 to store the number of resource entries returned
4208  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4209  *        to store the resource information for all resource types.  Each
4210  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4211  * @count: size, in bytes, of the buffer provided
4212  * @cmd_details: pointer to command details structure or NULL
4213  *
4214  * Query the resources allocated to a function.
4215  **/
4216 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4217                         u8 *num_entries,
4218                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4219                         u16 count,
4220                         struct i40e_asq_cmd_details *cmd_details)
4221 {
4222         struct i40e_aq_desc desc;
4223         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4224                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4225         enum i40e_status_code status;
4226         u16 length = count * sizeof(*buf);
4227
4228         i40e_fill_default_direct_cmd_desc(&desc,
4229                                         i40e_aqc_opc_get_switch_resource_alloc);
4230
4231         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4232         if (length > I40E_AQ_LARGE_BUF)
4233                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4234
4235         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4236
4237         if (!status && num_entries)
4238                 *num_entries = cmd_resp->num_entries;
4239
4240         return status;
4241 }
4242
4243 /**
4244  * i40e_aq_delete_element - Delete switch element
4245  * @hw: pointer to the hw struct
4246  * @seid: the SEID to delete from the switch
4247  * @cmd_details: pointer to command details structure or NULL
4248  *
4249  * This deletes a switch element from the switch.
4250  **/
4251 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4252                                 struct i40e_asq_cmd_details *cmd_details)
4253 {
4254         struct i40e_aq_desc desc;
4255         struct i40e_aqc_switch_seid *cmd =
4256                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4257         enum i40e_status_code status;
4258
4259         if (seid == 0)
4260                 return I40E_ERR_PARAM;
4261
4262         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4263
4264         cmd->seid = CPU_TO_LE16(seid);
4265
4266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4267
4268         return status;
4269 }
4270
4271 /**
4272  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4273  * @hw: pointer to the hw struct
4274  * @flags: component flags
4275  * @mac_seid: uplink seid (MAC SEID)
4276  * @vsi_seid: connected vsi seid
4277  * @ret_seid: seid of create pv component
4278  *
4279  * This instantiates an i40e port virtualizer with specified flags.
4280  * Depending on specified flags the port virtualizer can act as a
4281  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4282  */
4283 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4284                                        u16 mac_seid, u16 vsi_seid,
4285                                        u16 *ret_seid)
4286 {
4287         struct i40e_aq_desc desc;
4288         struct i40e_aqc_add_update_pv *cmd =
4289                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4290         struct i40e_aqc_add_update_pv_completion *resp =
4291                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4292         enum i40e_status_code status;
4293
4294         if (vsi_seid == 0)
4295                 return I40E_ERR_PARAM;
4296
4297         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4298         cmd->command_flags = CPU_TO_LE16(flags);
4299         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4300         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4301
4302         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4303         if (!status && ret_seid)
4304                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4305
4306         return status;
4307 }
4308
4309 /**
4310  * i40e_aq_add_tag - Add an S/E-tag
4311  * @hw: pointer to the hw struct
4312  * @direct_to_queue: should s-tag direct flow to a specific queue
4313  * @vsi_seid: VSI SEID to use this tag
4314  * @tag: value of the tag
4315  * @queue_num: queue number, only valid is direct_to_queue is true
4316  * @tags_used: return value, number of tags in use by this PF
4317  * @tags_free: return value, number of unallocated tags
4318  * @cmd_details: pointer to command details structure or NULL
4319  *
4320  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4321  * the number of tags allocated by the PF, and the number of unallocated
4322  * tags available.
4323  **/
4324 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4325                                 u16 vsi_seid, u16 tag, u16 queue_num,
4326                                 u16 *tags_used, u16 *tags_free,
4327                                 struct i40e_asq_cmd_details *cmd_details)
4328 {
4329         struct i40e_aq_desc desc;
4330         struct i40e_aqc_add_tag *cmd =
4331                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4332         struct i40e_aqc_add_remove_tag_completion *resp =
4333                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4334         enum i40e_status_code status;
4335
4336         if (vsi_seid == 0)
4337                 return I40E_ERR_PARAM;
4338
4339         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4340
4341         cmd->seid = CPU_TO_LE16(vsi_seid);
4342         cmd->tag = CPU_TO_LE16(tag);
4343         if (direct_to_queue) {
4344                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4345                 cmd->queue_number = CPU_TO_LE16(queue_num);
4346         }
4347
4348         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4349
4350         if (!status) {
4351                 if (tags_used != NULL)
4352                         *tags_used = LE16_TO_CPU(resp->tags_used);
4353                 if (tags_free != NULL)
4354                         *tags_free = LE16_TO_CPU(resp->tags_free);
4355         }
4356
4357         return status;
4358 }
4359
4360 /**
4361  * i40e_aq_remove_tag - Remove an S- or E-tag
4362  * @hw: pointer to the hw struct
4363  * @vsi_seid: VSI SEID this tag is associated with
4364  * @tag: value of the S-tag to delete
4365  * @tags_used: return value, number of tags in use by this PF
4366  * @tags_free: return value, number of unallocated tags
4367  * @cmd_details: pointer to command details structure or NULL
4368  *
4369  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4370  * the number of tags allocated by the PF, and the number of unallocated
4371  * tags available.
4372  **/
4373 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4374                                 u16 tag, u16 *tags_used, u16 *tags_free,
4375                                 struct i40e_asq_cmd_details *cmd_details)
4376 {
4377         struct i40e_aq_desc desc;
4378         struct i40e_aqc_remove_tag *cmd =
4379                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4380         struct i40e_aqc_add_remove_tag_completion *resp =
4381                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4382         enum i40e_status_code status;
4383
4384         if (vsi_seid == 0)
4385                 return I40E_ERR_PARAM;
4386
4387         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4388
4389         cmd->seid = CPU_TO_LE16(vsi_seid);
4390         cmd->tag = CPU_TO_LE16(tag);
4391
4392         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4393
4394         if (!status) {
4395                 if (tags_used != NULL)
4396                         *tags_used = LE16_TO_CPU(resp->tags_used);
4397                 if (tags_free != NULL)
4398                         *tags_free = LE16_TO_CPU(resp->tags_free);
4399         }
4400
4401         return status;
4402 }
4403
4404 /**
4405  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4406  * @hw: pointer to the hw struct
4407  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4408  * @etag: value of E-tag to add
4409  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4410  * @buf: address of indirect buffer
4411  * @tags_used: return value, number of E-tags in use by this port
4412  * @tags_free: return value, number of unallocated M-tags
4413  * @cmd_details: pointer to command details structure or NULL
4414  *
4415  * This associates a multicast E-tag to a port virtualizer.  It will return
4416  * the number of tags allocated by the PF, and the number of unallocated
4417  * tags available.
4418  *
4419  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4420  * num_tags_in_buf long.
4421  **/
4422 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4423                                 u16 etag, u8 num_tags_in_buf, void *buf,
4424                                 u16 *tags_used, u16 *tags_free,
4425                                 struct i40e_asq_cmd_details *cmd_details)
4426 {
4427         struct i40e_aq_desc desc;
4428         struct i40e_aqc_add_remove_mcast_etag *cmd =
4429                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4430         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4431            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4432         enum i40e_status_code status;
4433         u16 length = sizeof(u16) * num_tags_in_buf;
4434
4435         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4436                 return I40E_ERR_PARAM;
4437
4438         i40e_fill_default_direct_cmd_desc(&desc,
4439                                           i40e_aqc_opc_add_multicast_etag);
4440
4441         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4442         cmd->etag = CPU_TO_LE16(etag);
4443         cmd->num_unicast_etags = num_tags_in_buf;
4444
4445         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4446         if (length > I40E_AQ_LARGE_BUF)
4447                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4448
4449         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4450
4451         if (!status) {
4452                 if (tags_used != NULL)
4453                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4454                 if (tags_free != NULL)
4455                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4456         }
4457
4458         return status;
4459 }
4460
4461 /**
4462  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4463  * @hw: pointer to the hw struct
4464  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4465  * @etag: value of the E-tag to remove
4466  * @tags_used: return value, number of tags in use by this port
4467  * @tags_free: return value, number of unallocated tags
4468  * @cmd_details: pointer to command details structure or NULL
4469  *
4470  * This deletes an E-tag from the port virtualizer.  It will return
4471  * the number of tags allocated by the port, and the number of unallocated
4472  * tags available.
4473  **/
4474 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4475                                 u16 etag, u16 *tags_used, u16 *tags_free,
4476                                 struct i40e_asq_cmd_details *cmd_details)
4477 {
4478         struct i40e_aq_desc desc;
4479         struct i40e_aqc_add_remove_mcast_etag *cmd =
4480                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4481         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4482            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4483         enum i40e_status_code status;
4484
4485
4486         if (pv_seid == 0)
4487                 return I40E_ERR_PARAM;
4488
4489         i40e_fill_default_direct_cmd_desc(&desc,
4490                                           i40e_aqc_opc_remove_multicast_etag);
4491
4492         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4493         cmd->etag = CPU_TO_LE16(etag);
4494
4495         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4496
4497         if (!status) {
4498                 if (tags_used != NULL)
4499                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4500                 if (tags_free != NULL)
4501                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4502         }
4503
4504         return status;
4505 }
4506
4507 /**
4508  * i40e_aq_update_tag - Update an S/E-tag
4509  * @hw: pointer to the hw struct
4510  * @vsi_seid: VSI SEID using this S-tag
4511  * @old_tag: old tag value
4512  * @new_tag: new tag value
4513  * @tags_used: return value, number of tags in use by this PF
4514  * @tags_free: return value, number of unallocated tags
4515  * @cmd_details: pointer to command details structure or NULL
4516  *
4517  * This updates the value of the tag currently attached to this VSI
4518  * in the switch complex.  It will return the number of tags allocated
4519  * by the PF, and the number of unallocated tags available.
4520  **/
4521 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4522                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4523                                 u16 *tags_free,
4524                                 struct i40e_asq_cmd_details *cmd_details)
4525 {
4526         struct i40e_aq_desc desc;
4527         struct i40e_aqc_update_tag *cmd =
4528                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4529         struct i40e_aqc_update_tag_completion *resp =
4530                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4531         enum i40e_status_code status;
4532
4533         if (vsi_seid == 0)
4534                 return I40E_ERR_PARAM;
4535
4536         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4537
4538         cmd->seid = CPU_TO_LE16(vsi_seid);
4539         cmd->old_tag = CPU_TO_LE16(old_tag);
4540         cmd->new_tag = CPU_TO_LE16(new_tag);
4541
4542         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4543
4544         if (!status) {
4545                 if (tags_used != NULL)
4546                         *tags_used = LE16_TO_CPU(resp->tags_used);
4547                 if (tags_free != NULL)
4548                         *tags_free = LE16_TO_CPU(resp->tags_free);
4549         }
4550
4551         return status;
4552 }
4553
4554 /**
4555  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4556  * @hw: pointer to the hw struct
4557  * @tcmap: TC map for request/release any ignore PFC condition
4558  * @request: request or release ignore PFC condition
4559  * @tcmap_ret: return TCs for which PFC is currently ignored
4560  * @cmd_details: pointer to command details structure or NULL
4561  *
4562  * This sends out request/release to ignore PFC condition for a TC.
4563  * It will return the TCs for which PFC is currently ignored.
4564  **/
4565 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4566                                 bool request, u8 *tcmap_ret,
4567                                 struct i40e_asq_cmd_details *cmd_details)
4568 {
4569         struct i40e_aq_desc desc;
4570         struct i40e_aqc_pfc_ignore *cmd_resp =
4571                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4572         enum i40e_status_code status;
4573
4574         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4575
4576         if (request)
4577                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4578
4579         cmd_resp->tc_bitmap = tcmap;
4580
4581         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4582
4583         if (!status) {
4584                 if (tcmap_ret != NULL)
4585                         *tcmap_ret = cmd_resp->tc_bitmap;
4586         }
4587
4588         return status;
4589 }
4590
4591 /**
4592  * i40e_aq_dcb_updated - DCB Updated Command
4593  * @hw: pointer to the hw struct
4594  * @cmd_details: pointer to command details structure or NULL
4595  *
4596  * When LLDP is handled in PF this command is used by the PF
4597  * to notify EMP that a DCB setting is modified.
4598  * When LLDP is handled in EMP this command is used by the PF
4599  * to notify EMP whenever one of the following parameters get
4600  * modified:
4601  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4602  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4603  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4604  * EMP will return when the shared RPB settings have been
4605  * recomputed and modified. The retval field in the descriptor
4606  * will be set to 0 when RPB is modified.
4607  **/
4608 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4609                                 struct i40e_asq_cmd_details *cmd_details)
4610 {
4611         struct i40e_aq_desc desc;
4612         enum i40e_status_code status;
4613
4614         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4615
4616         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4617
4618         return status;
4619 }
4620
4621 /**
4622  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4623  * @hw: pointer to the hw struct
4624  * @seid: defines the SEID of the switch for which the stats are requested
4625  * @vlan_id: the VLAN ID for which the statistics are requested
4626  * @stat_index: index of the statistics counters block assigned to this VLAN
4627  * @cmd_details: pointer to command details structure or NULL
4628  *
4629  * XL710 supports 128 smonVlanStats counters.This command is used to
4630  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4631  * switch.
4632  **/
4633 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4634                                 u16 vlan_id, u16 *stat_index,
4635                                 struct i40e_asq_cmd_details *cmd_details)
4636 {
4637         struct i40e_aq_desc desc;
4638         struct i40e_aqc_add_remove_statistics *cmd_resp =
4639                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4640         enum i40e_status_code status;
4641
4642         if ((seid == 0) || (stat_index == NULL))
4643                 return I40E_ERR_PARAM;
4644
4645         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4646
4647         cmd_resp->seid = CPU_TO_LE16(seid);
4648         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4649
4650         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4651
4652         if (!status && stat_index)
4653                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4654
4655         return status;
4656 }
4657
4658 /**
4659  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4660  * @hw: pointer to the hw struct
4661  * @seid: defines the SEID of the switch for which the stats are requested
4662  * @vlan_id: the VLAN ID for which the statistics are requested
4663  * @stat_index: index of the statistics counters block assigned to this VLAN
4664  * @cmd_details: pointer to command details structure or NULL
4665  *
4666  * XL710 supports 128 smonVlanStats counters.This command is used to
4667  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4668  * switch.
4669  **/
4670 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4671                                 u16 vlan_id, u16 stat_index,
4672                                 struct i40e_asq_cmd_details *cmd_details)
4673 {
4674         struct i40e_aq_desc desc;
4675         struct i40e_aqc_add_remove_statistics *cmd =
4676                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4677         enum i40e_status_code status;
4678
4679         if (seid == 0)
4680                 return I40E_ERR_PARAM;
4681
4682         i40e_fill_default_direct_cmd_desc(&desc,
4683                                           i40e_aqc_opc_remove_statistics);
4684
4685         cmd->seid = CPU_TO_LE16(seid);
4686         cmd->vlan  = CPU_TO_LE16(vlan_id);
4687         cmd->stat_index = CPU_TO_LE16(stat_index);
4688
4689         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4690
4691         return status;
4692 }
4693
4694 /**
4695  * i40e_aq_set_port_parameters - set physical port parameters.
4696  * @hw: pointer to the hw struct
4697  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4698  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4699  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4700  * @double_vlan: if set double VLAN is enabled
4701  * @cmd_details: pointer to command details structure or NULL
4702  **/
4703 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4704                                 u16 bad_frame_vsi, bool save_bad_pac,
4705                                 bool pad_short_pac, bool double_vlan,
4706                                 struct i40e_asq_cmd_details *cmd_details)
4707 {
4708         struct i40e_aqc_set_port_parameters *cmd;
4709         enum i40e_status_code status;
4710         struct i40e_aq_desc desc;
4711         u16 command_flags = 0;
4712
4713         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4714
4715         i40e_fill_default_direct_cmd_desc(&desc,
4716                                           i40e_aqc_opc_set_port_parameters);
4717
4718         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4719         if (save_bad_pac)
4720                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4721         if (pad_short_pac)
4722                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4723         if (double_vlan)
4724                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4725         cmd->command_flags = CPU_TO_LE16(command_flags);
4726
4727         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4728
4729         return status;
4730 }
4731
4732 /**
4733  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4734  * @hw: pointer to the hw struct
4735  * @seid: seid for the physical port/switching component/vsi
4736  * @buff: Indirect buffer to hold data parameters and response
4737  * @buff_size: Indirect buffer size
4738  * @opcode: Tx scheduler AQ command opcode
4739  * @cmd_details: pointer to command details structure or NULL
4740  *
4741  * Generic command handler for Tx scheduler AQ commands
4742  **/
4743 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4744                                 void *buff, u16 buff_size,
4745                                  enum i40e_admin_queue_opc opcode,
4746                                 struct i40e_asq_cmd_details *cmd_details)
4747 {
4748         struct i40e_aq_desc desc;
4749         struct i40e_aqc_tx_sched_ind *cmd =
4750                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4751         enum i40e_status_code status;
4752         bool cmd_param_flag = false;
4753
4754         switch (opcode) {
4755         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4756         case i40e_aqc_opc_configure_vsi_tc_bw:
4757         case i40e_aqc_opc_enable_switching_comp_ets:
4758         case i40e_aqc_opc_modify_switching_comp_ets:
4759         case i40e_aqc_opc_disable_switching_comp_ets:
4760         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4761         case i40e_aqc_opc_configure_switching_comp_bw_config:
4762                 cmd_param_flag = true;
4763                 break;
4764         case i40e_aqc_opc_query_vsi_bw_config:
4765         case i40e_aqc_opc_query_vsi_ets_sla_config:
4766         case i40e_aqc_opc_query_switching_comp_ets_config:
4767         case i40e_aqc_opc_query_port_ets_config:
4768         case i40e_aqc_opc_query_switching_comp_bw_config:
4769                 cmd_param_flag = false;
4770                 break;
4771         default:
4772                 return I40E_ERR_PARAM;
4773         }
4774
4775         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4776
4777         /* Indirect command */
4778         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4779         if (cmd_param_flag)
4780                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4781         if (buff_size > I40E_AQ_LARGE_BUF)
4782                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4783
4784         desc.datalen = CPU_TO_LE16(buff_size);
4785
4786         cmd->vsi_seid = CPU_TO_LE16(seid);
4787
4788         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4789
4790         return status;
4791 }
4792
4793 /**
4794  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4795  * @hw: pointer to the hw struct
4796  * @seid: VSI seid
4797  * @credit: BW limit credits (0 = disabled)
4798  * @max_credit: Max BW limit credits
4799  * @cmd_details: pointer to command details structure or NULL
4800  **/
4801 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4802                                 u16 seid, u16 credit, u8 max_credit,
4803                                 struct i40e_asq_cmd_details *cmd_details)
4804 {
4805         struct i40e_aq_desc desc;
4806         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4807                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4808         enum i40e_status_code status;
4809
4810         i40e_fill_default_direct_cmd_desc(&desc,
4811                                           i40e_aqc_opc_configure_vsi_bw_limit);
4812
4813         cmd->vsi_seid = CPU_TO_LE16(seid);
4814         cmd->credit = CPU_TO_LE16(credit);
4815         cmd->max_credit = max_credit;
4816
4817         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4818
4819         return status;
4820 }
4821
4822 /**
4823  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4824  * @hw: pointer to the hw struct
4825  * @seid: switching component seid
4826  * @credit: BW limit credits (0 = disabled)
4827  * @max_bw: Max BW limit credits
4828  * @cmd_details: pointer to command details structure or NULL
4829  **/
4830 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4831                                 u16 seid, u16 credit, u8 max_bw,
4832                                 struct i40e_asq_cmd_details *cmd_details)
4833 {
4834         struct i40e_aq_desc desc;
4835         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4836           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4837         enum i40e_status_code status;
4838
4839         i40e_fill_default_direct_cmd_desc(&desc,
4840                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4841
4842         cmd->seid = CPU_TO_LE16(seid);
4843         cmd->credit = CPU_TO_LE16(credit);
4844         cmd->max_bw = max_bw;
4845
4846         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4847
4848         return status;
4849 }
4850
4851 /**
4852  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4853  * @hw: pointer to the hw struct
4854  * @seid: VSI seid
4855  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4856  * @cmd_details: pointer to command details structure or NULL
4857  **/
4858 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4859                         u16 seid,
4860                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4861                         struct i40e_asq_cmd_details *cmd_details)
4862 {
4863         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4864                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4865                                     cmd_details);
4866 }
4867
4868 /**
4869  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4870  * @hw: pointer to the hw struct
4871  * @seid: VSI seid
4872  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4873  * @cmd_details: pointer to command details structure or NULL
4874  **/
4875 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4876                         u16 seid,
4877                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4878                         struct i40e_asq_cmd_details *cmd_details)
4879 {
4880         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4881                                     i40e_aqc_opc_configure_vsi_tc_bw,
4882                                     cmd_details);
4883 }
4884
4885 /**
4886  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4887  * @hw: pointer to the hw struct
4888  * @seid: seid of the switching component connected to Physical Port
4889  * @ets_data: Buffer holding ETS parameters
4890  * @cmd_details: pointer to command details structure or NULL
4891  **/
4892 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4893                 u16 seid,
4894                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4895                 enum i40e_admin_queue_opc opcode,
4896                 struct i40e_asq_cmd_details *cmd_details)
4897 {
4898         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4899                                     sizeof(*ets_data), opcode, cmd_details);
4900 }
4901
4902 /**
4903  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4904  * @hw: pointer to the hw struct
4905  * @seid: seid of the switching component
4906  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4907  * @cmd_details: pointer to command details structure or NULL
4908  **/
4909 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4910         u16 seid,
4911         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4912         struct i40e_asq_cmd_details *cmd_details)
4913 {
4914         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4915                             i40e_aqc_opc_configure_switching_comp_bw_config,
4916                             cmd_details);
4917 }
4918
4919 /**
4920  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4921  * @hw: pointer to the hw struct
4922  * @seid: seid of the switching component
4923  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4924  * @cmd_details: pointer to command details structure or NULL
4925  **/
4926 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4927         struct i40e_hw *hw, u16 seid,
4928         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4929         struct i40e_asq_cmd_details *cmd_details)
4930 {
4931         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4932                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4933                             cmd_details);
4934 }
4935
4936 /**
4937  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4938  * @hw: pointer to the hw struct
4939  * @seid: seid of the VSI
4940  * @bw_data: Buffer to hold VSI BW configuration
4941  * @cmd_details: pointer to command details structure or NULL
4942  **/
4943 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4944                         u16 seid,
4945                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4946                         struct i40e_asq_cmd_details *cmd_details)
4947 {
4948         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4949                                     i40e_aqc_opc_query_vsi_bw_config,
4950                                     cmd_details);
4951 }
4952
4953 /**
4954  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4955  * @hw: pointer to the hw struct
4956  * @seid: seid of the VSI
4957  * @bw_data: Buffer to hold VSI BW configuration per TC
4958  * @cmd_details: pointer to command details structure or NULL
4959  **/
4960 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4961                         u16 seid,
4962                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4963                         struct i40e_asq_cmd_details *cmd_details)
4964 {
4965         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4966                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4967                                     cmd_details);
4968 }
4969
4970 /**
4971  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4972  * @hw: pointer to the hw struct
4973  * @seid: seid of the switching component
4974  * @bw_data: Buffer to hold switching component's per TC BW config
4975  * @cmd_details: pointer to command details structure or NULL
4976  **/
4977 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4978                 u16 seid,
4979                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4980                 struct i40e_asq_cmd_details *cmd_details)
4981 {
4982         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4983                                    i40e_aqc_opc_query_switching_comp_ets_config,
4984                                    cmd_details);
4985 }
4986
4987 /**
4988  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4989  * @hw: pointer to the hw struct
4990  * @seid: seid of the VSI or switching component connected to Physical Port
4991  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4992  * @cmd_details: pointer to command details structure or NULL
4993  **/
4994 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4995                         u16 seid,
4996                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4997                         struct i40e_asq_cmd_details *cmd_details)
4998 {
4999         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5000                                     i40e_aqc_opc_query_port_ets_config,
5001                                     cmd_details);
5002 }
5003
5004 /**
5005  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5006  * @hw: pointer to the hw struct
5007  * @seid: seid of the switching component
5008  * @bw_data: Buffer to hold switching component's BW configuration
5009  * @cmd_details: pointer to command details structure or NULL
5010  **/
5011 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5012                 u16 seid,
5013                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5014                 struct i40e_asq_cmd_details *cmd_details)
5015 {
5016         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5017                                     i40e_aqc_opc_query_switching_comp_bw_config,
5018                                     cmd_details);
5019 }
5020
5021 /**
5022  * i40e_validate_filter_settings
5023  * @hw: pointer to the hardware structure
5024  * @settings: Filter control settings
5025  *
5026  * Check and validate the filter control settings passed.
5027  * The function checks for the valid filter/context sizes being
5028  * passed for FCoE and PE.
5029  *
5030  * Returns I40E_SUCCESS if the values passed are valid and within
5031  * range else returns an error.
5032  **/
5033 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5034                                 struct i40e_filter_control_settings *settings)
5035 {
5036         u32 fcoe_cntx_size, fcoe_filt_size;
5037         u32 pe_cntx_size, pe_filt_size;
5038         u32 fcoe_fmax;
5039
5040         u32 val;
5041
5042         /* Validate FCoE settings passed */
5043         switch (settings->fcoe_filt_num) {
5044         case I40E_HASH_FILTER_SIZE_1K:
5045         case I40E_HASH_FILTER_SIZE_2K:
5046         case I40E_HASH_FILTER_SIZE_4K:
5047         case I40E_HASH_FILTER_SIZE_8K:
5048         case I40E_HASH_FILTER_SIZE_16K:
5049         case I40E_HASH_FILTER_SIZE_32K:
5050                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5051                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5052                 break;
5053         default:
5054                 return I40E_ERR_PARAM;
5055         }
5056
5057         switch (settings->fcoe_cntx_num) {
5058         case I40E_DMA_CNTX_SIZE_512:
5059         case I40E_DMA_CNTX_SIZE_1K:
5060         case I40E_DMA_CNTX_SIZE_2K:
5061         case I40E_DMA_CNTX_SIZE_4K:
5062                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5063                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5064                 break;
5065         default:
5066                 return I40E_ERR_PARAM;
5067         }
5068
5069         /* Validate PE settings passed */
5070         switch (settings->pe_filt_num) {
5071         case I40E_HASH_FILTER_SIZE_1K:
5072         case I40E_HASH_FILTER_SIZE_2K:
5073         case I40E_HASH_FILTER_SIZE_4K:
5074         case I40E_HASH_FILTER_SIZE_8K:
5075         case I40E_HASH_FILTER_SIZE_16K:
5076         case I40E_HASH_FILTER_SIZE_32K:
5077         case I40E_HASH_FILTER_SIZE_64K:
5078         case I40E_HASH_FILTER_SIZE_128K:
5079         case I40E_HASH_FILTER_SIZE_256K:
5080         case I40E_HASH_FILTER_SIZE_512K:
5081         case I40E_HASH_FILTER_SIZE_1M:
5082                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5083                 pe_filt_size <<= (u32)settings->pe_filt_num;
5084                 break;
5085         default:
5086                 return I40E_ERR_PARAM;
5087         }
5088
5089         switch (settings->pe_cntx_num) {
5090         case I40E_DMA_CNTX_SIZE_512:
5091         case I40E_DMA_CNTX_SIZE_1K:
5092         case I40E_DMA_CNTX_SIZE_2K:
5093         case I40E_DMA_CNTX_SIZE_4K:
5094         case I40E_DMA_CNTX_SIZE_8K:
5095         case I40E_DMA_CNTX_SIZE_16K:
5096         case I40E_DMA_CNTX_SIZE_32K:
5097         case I40E_DMA_CNTX_SIZE_64K:
5098         case I40E_DMA_CNTX_SIZE_128K:
5099         case I40E_DMA_CNTX_SIZE_256K:
5100                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5101                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5102                 break;
5103         default:
5104                 return I40E_ERR_PARAM;
5105         }
5106
5107         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5108         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5109         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5110                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5111         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5112                 return I40E_ERR_INVALID_SIZE;
5113
5114         return I40E_SUCCESS;
5115 }
5116
5117 /**
5118  * i40e_set_filter_control
5119  * @hw: pointer to the hardware structure
5120  * @settings: Filter control settings
5121  *
5122  * Set the Queue Filters for PE/FCoE and enable filters required
5123  * for a single PF. It is expected that these settings are programmed
5124  * at the driver initialization time.
5125  **/
5126 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5127                                 struct i40e_filter_control_settings *settings)
5128 {
5129         enum i40e_status_code ret = I40E_SUCCESS;
5130         u32 hash_lut_size = 0;
5131         u32 val;
5132
5133         if (!settings)
5134                 return I40E_ERR_PARAM;
5135
5136         /* Validate the input settings */
5137         ret = i40e_validate_filter_settings(hw, settings);
5138         if (ret)
5139                 return ret;
5140
5141         /* Read the PF Queue Filter control register */
5142         val = rd32(hw, I40E_PFQF_CTL_0);
5143
5144         /* Program required PE hash buckets for the PF */
5145         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5146         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5147                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5148         /* Program required PE contexts for the PF */
5149         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5150         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5151                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5152
5153         /* Program required FCoE hash buckets for the PF */
5154         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5155         val |= ((u32)settings->fcoe_filt_num <<
5156                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5157                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5158         /* Program required FCoE DDP contexts for the PF */
5159         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5160         val |= ((u32)settings->fcoe_cntx_num <<
5161                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5162                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5163
5164         /* Program Hash LUT size for the PF */
5165         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5166         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5167                 hash_lut_size = 1;
5168         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5169                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5170
5171         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5172         if (settings->enable_fdir)
5173                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5174         if (settings->enable_ethtype)
5175                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5176         if (settings->enable_macvlan)
5177                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5178
5179         wr32(hw, I40E_PFQF_CTL_0, val);
5180
5181         return I40E_SUCCESS;
5182 }
5183
5184 /**
5185  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5186  * @hw: pointer to the hw struct
5187  * @mac_addr: MAC address to use in the filter
5188  * @ethtype: Ethertype to use in the filter
5189  * @flags: Flags that needs to be applied to the filter
5190  * @vsi_seid: seid of the control VSI
5191  * @queue: VSI queue number to send the packet to
5192  * @is_add: Add control packet filter if True else remove
5193  * @stats: Structure to hold information on control filter counts
5194  * @cmd_details: pointer to command details structure or NULL
5195  *
5196  * This command will Add or Remove control packet filter for a control VSI.
5197  * In return it will update the total number of perfect filter count in
5198  * the stats member.
5199  **/
5200 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5201                                 u8 *mac_addr, u16 ethtype, u16 flags,
5202                                 u16 vsi_seid, u16 queue, bool is_add,
5203                                 struct i40e_control_filter_stats *stats,
5204                                 struct i40e_asq_cmd_details *cmd_details)
5205 {
5206         struct i40e_aq_desc desc;
5207         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5208                 (struct i40e_aqc_add_remove_control_packet_filter *)
5209                 &desc.params.raw;
5210         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5211                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5212                 &desc.params.raw;
5213         enum i40e_status_code status;
5214
5215         if (vsi_seid == 0)
5216                 return I40E_ERR_PARAM;
5217
5218         if (is_add) {
5219                 i40e_fill_default_direct_cmd_desc(&desc,
5220                                 i40e_aqc_opc_add_control_packet_filter);
5221                 cmd->queue = CPU_TO_LE16(queue);
5222         } else {
5223                 i40e_fill_default_direct_cmd_desc(&desc,
5224                                 i40e_aqc_opc_remove_control_packet_filter);
5225         }
5226
5227         if (mac_addr)
5228                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5229                             I40E_NONDMA_TO_NONDMA);
5230
5231         cmd->etype = CPU_TO_LE16(ethtype);
5232         cmd->flags = CPU_TO_LE16(flags);
5233         cmd->seid = CPU_TO_LE16(vsi_seid);
5234
5235         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5236
5237         if (!status && stats) {
5238                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5239                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5240                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5241                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5242         }
5243
5244         return status;
5245 }
5246
5247 /**
5248  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5249  * @hw: pointer to the hw struct
5250  * @seid: VSI seid to add ethertype filter from
5251  **/
5252 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5253 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5254                                                     u16 seid)
5255 {
5256         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5257                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5258                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5259         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5260         enum i40e_status_code status;
5261
5262         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5263                                                        seid, 0, true, NULL,
5264                                                        NULL);
5265         if (status)
5266                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5267 }
5268
5269 /**
5270  * i40e_aq_add_cloud_filters
5271  * @hw: pointer to the hardware structure
5272  * @seid: VSI seid to add cloud filters from
5273  * @filters: Buffer which contains the filters to be added
5274  * @filter_count: number of filters contained in the buffer
5275  *
5276  * Set the cloud filters for a given VSI.  The contents of the
5277  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5278  * in by the caller of the function.
5279  *
5280  **/
5281 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5282         u16 seid,
5283         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5284         u8 filter_count)
5285 {
5286         struct i40e_aq_desc desc;
5287         struct i40e_aqc_add_remove_cloud_filters *cmd =
5288         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5289         u16 buff_len;
5290         enum i40e_status_code status;
5291
5292         i40e_fill_default_direct_cmd_desc(&desc,
5293                                           i40e_aqc_opc_add_cloud_filters);
5294
5295         buff_len = filter_count * sizeof(*filters);
5296         desc.datalen = CPU_TO_LE16(buff_len);
5297         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5298         cmd->num_filters = filter_count;
5299         cmd->seid = CPU_TO_LE16(seid);
5300
5301         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5302
5303         return status;
5304 }
5305
5306 /**
5307  * i40e_aq_remove_cloud_filters
5308  * @hw: pointer to the hardware structure
5309  * @seid: VSI seid to remove cloud filters from
5310  * @filters: Buffer which contains the filters to be removed
5311  * @filter_count: number of filters contained in the buffer
5312  *
5313  * Remove the cloud filters for a given VSI.  The contents of the
5314  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5315  * in by the caller of the function.
5316  *
5317  **/
5318 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5319                 u16 seid,
5320                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5321                 u8 filter_count)
5322 {
5323         struct i40e_aq_desc desc;
5324         struct i40e_aqc_add_remove_cloud_filters *cmd =
5325         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5326         enum i40e_status_code status;
5327         u16 buff_len;
5328
5329         i40e_fill_default_direct_cmd_desc(&desc,
5330                                           i40e_aqc_opc_remove_cloud_filters);
5331
5332         buff_len = filter_count * sizeof(*filters);
5333         desc.datalen = CPU_TO_LE16(buff_len);
5334         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5335         cmd->num_filters = filter_count;
5336         cmd->seid = CPU_TO_LE16(seid);
5337
5338         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5339
5340         return status;
5341 }
5342
5343 /**
5344  * i40e_aq_alternate_write
5345  * @hw: pointer to the hardware structure
5346  * @reg_addr0: address of first dword to be read
5347  * @reg_val0: value to be written under 'reg_addr0'
5348  * @reg_addr1: address of second dword to be read
5349  * @reg_val1: value to be written under 'reg_addr1'
5350  *
5351  * Write one or two dwords to alternate structure. Fields are indicated
5352  * by 'reg_addr0' and 'reg_addr1' register numbers.
5353  *
5354  **/
5355 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5356                                 u32 reg_addr0, u32 reg_val0,
5357                                 u32 reg_addr1, u32 reg_val1)
5358 {
5359         struct i40e_aq_desc desc;
5360         struct i40e_aqc_alternate_write *cmd_resp =
5361                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5362         enum i40e_status_code status;
5363
5364         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5365         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5366         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5367         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5368         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5369
5370         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5371
5372         return status;
5373 }
5374
5375 /**
5376  * i40e_aq_alternate_write_indirect
5377  * @hw: pointer to the hardware structure
5378  * @addr: address of a first register to be modified
5379  * @dw_count: number of alternate structure fields to write
5380  * @buffer: pointer to the command buffer
5381  *
5382  * Write 'dw_count' dwords from 'buffer' to alternate structure
5383  * starting at 'addr'.
5384  *
5385  **/
5386 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5387                                 u32 addr, u32 dw_count, void *buffer)
5388 {
5389         struct i40e_aq_desc desc;
5390         struct i40e_aqc_alternate_ind_write *cmd_resp =
5391                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5392         enum i40e_status_code status;
5393
5394         if (buffer == NULL)
5395                 return I40E_ERR_PARAM;
5396
5397         /* Indirect command */
5398         i40e_fill_default_direct_cmd_desc(&desc,
5399                                          i40e_aqc_opc_alternate_write_indirect);
5400
5401         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5402         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5403         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5404                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5405
5406         cmd_resp->address = CPU_TO_LE32(addr);
5407         cmd_resp->length = CPU_TO_LE32(dw_count);
5408
5409         status = i40e_asq_send_command(hw, &desc, buffer,
5410                                        I40E_LO_DWORD(4*dw_count), NULL);
5411
5412         return status;
5413 }
5414
5415 /**
5416  * i40e_aq_alternate_read
5417  * @hw: pointer to the hardware structure
5418  * @reg_addr0: address of first dword to be read
5419  * @reg_val0: pointer for data read from 'reg_addr0'
5420  * @reg_addr1: address of second dword to be read
5421  * @reg_val1: pointer for data read from 'reg_addr1'
5422  *
5423  * Read one or two dwords from alternate structure. Fields are indicated
5424  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5425  * is not passed then only register at 'reg_addr0' is read.
5426  *
5427  **/
5428 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5429                                 u32 reg_addr0, u32 *reg_val0,
5430                                 u32 reg_addr1, u32 *reg_val1)
5431 {
5432         struct i40e_aq_desc desc;
5433         struct i40e_aqc_alternate_write *cmd_resp =
5434                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5435         enum i40e_status_code status;
5436
5437         if (reg_val0 == NULL)
5438                 return I40E_ERR_PARAM;
5439
5440         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5441         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5442         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5443
5444         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5445
5446         if (status == I40E_SUCCESS) {
5447                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5448
5449                 if (reg_val1 != NULL)
5450                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5451         }
5452
5453         return status;
5454 }
5455
5456 /**
5457  * i40e_aq_alternate_read_indirect
5458  * @hw: pointer to the hardware structure
5459  * @addr: address of the alternate structure field
5460  * @dw_count: number of alternate structure fields to read
5461  * @buffer: pointer to the command buffer
5462  *
5463  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5464  * place them in 'buffer'. The buffer should be allocated by caller.
5465  *
5466  **/
5467 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5468                                 u32 addr, u32 dw_count, void *buffer)
5469 {
5470         struct i40e_aq_desc desc;
5471         struct i40e_aqc_alternate_ind_write *cmd_resp =
5472                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5473         enum i40e_status_code status;
5474
5475         if (buffer == NULL)
5476                 return I40E_ERR_PARAM;
5477
5478         /* Indirect command */
5479         i40e_fill_default_direct_cmd_desc(&desc,
5480                 i40e_aqc_opc_alternate_read_indirect);
5481
5482         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5483         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5484         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5485                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5486
5487         cmd_resp->address = CPU_TO_LE32(addr);
5488         cmd_resp->length = CPU_TO_LE32(dw_count);
5489
5490         status = i40e_asq_send_command(hw, &desc, buffer,
5491                                        I40E_LO_DWORD(4*dw_count), NULL);
5492
5493         return status;
5494 }
5495
5496 /**
5497  *  i40e_aq_alternate_clear
5498  *  @hw: pointer to the HW structure.
5499  *
5500  *  Clear the alternate structures of the port from which the function
5501  *  is called.
5502  *
5503  **/
5504 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5505 {
5506         struct i40e_aq_desc desc;
5507         enum i40e_status_code status;
5508
5509         i40e_fill_default_direct_cmd_desc(&desc,
5510                                           i40e_aqc_opc_alternate_clear_port);
5511
5512         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5513
5514         return status;
5515 }
5516
5517 /**
5518  *  i40e_aq_alternate_write_done
5519  *  @hw: pointer to the HW structure.
5520  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5521  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5522  *
5523  *  Indicates to the FW that alternate structures have been changed.
5524  *
5525  **/
5526 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5527                 u8 bios_mode, bool *reset_needed)
5528 {
5529         struct i40e_aq_desc desc;
5530         struct i40e_aqc_alternate_write_done *cmd =
5531                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5532         enum i40e_status_code status;
5533
5534         if (reset_needed == NULL)
5535                 return I40E_ERR_PARAM;
5536
5537         i40e_fill_default_direct_cmd_desc(&desc,
5538                                           i40e_aqc_opc_alternate_write_done);
5539
5540         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5541
5542         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5543         if (!status && reset_needed)
5544                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5545                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5546
5547         return status;
5548 }
5549
5550 /**
5551  *  i40e_aq_set_oem_mode
5552  *  @hw: pointer to the HW structure.
5553  *  @oem_mode: the OEM mode to be used
5554  *
5555  *  Sets the device to a specific operating mode. Currently the only supported
5556  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5557  *
5558  **/
5559 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5560                 u8 oem_mode)
5561 {
5562         struct i40e_aq_desc desc;
5563         struct i40e_aqc_alternate_write_done *cmd =
5564                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5565         enum i40e_status_code status;
5566
5567         i40e_fill_default_direct_cmd_desc(&desc,
5568                                           i40e_aqc_opc_alternate_set_mode);
5569
5570         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5571
5572         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5573
5574         return status;
5575 }
5576
5577 /**
5578  * i40e_aq_resume_port_tx
5579  * @hw: pointer to the hardware structure
5580  * @cmd_details: pointer to command details structure or NULL
5581  *
5582  * Resume port's Tx traffic
5583  **/
5584 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5585                                 struct i40e_asq_cmd_details *cmd_details)
5586 {
5587         struct i40e_aq_desc desc;
5588         enum i40e_status_code status;
5589
5590         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5591
5592         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5593
5594         return status;
5595 }
5596
5597 /**
5598  * i40e_set_pci_config_data - store PCI bus info
5599  * @hw: pointer to hardware structure
5600  * @link_status: the link status word from PCI config space
5601  *
5602  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5603  **/
5604 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5605 {
5606         hw->bus.type = i40e_bus_type_pci_express;
5607
5608         switch (link_status & I40E_PCI_LINK_WIDTH) {
5609         case I40E_PCI_LINK_WIDTH_1:
5610                 hw->bus.width = i40e_bus_width_pcie_x1;
5611                 break;
5612         case I40E_PCI_LINK_WIDTH_2:
5613                 hw->bus.width = i40e_bus_width_pcie_x2;
5614                 break;
5615         case I40E_PCI_LINK_WIDTH_4:
5616                 hw->bus.width = i40e_bus_width_pcie_x4;
5617                 break;
5618         case I40E_PCI_LINK_WIDTH_8:
5619                 hw->bus.width = i40e_bus_width_pcie_x8;
5620                 break;
5621         default:
5622                 hw->bus.width = i40e_bus_width_unknown;
5623                 break;
5624         }
5625
5626         switch (link_status & I40E_PCI_LINK_SPEED) {
5627         case I40E_PCI_LINK_SPEED_2500:
5628                 hw->bus.speed = i40e_bus_speed_2500;
5629                 break;
5630         case I40E_PCI_LINK_SPEED_5000:
5631                 hw->bus.speed = i40e_bus_speed_5000;
5632                 break;
5633         case I40E_PCI_LINK_SPEED_8000:
5634                 hw->bus.speed = i40e_bus_speed_8000;
5635                 break;
5636         default:
5637                 hw->bus.speed = i40e_bus_speed_unknown;
5638                 break;
5639         }
5640 }
5641
5642 /**
5643  * i40e_aq_debug_dump
5644  * @hw: pointer to the hardware structure
5645  * @cluster_id: specific cluster to dump
5646  * @table_id: table id within cluster
5647  * @start_index: index of line in the block to read
5648  * @buff_size: dump buffer size
5649  * @buff: dump buffer
5650  * @ret_buff_size: actual buffer size returned
5651  * @ret_next_table: next block to read
5652  * @ret_next_index: next index to read
5653  *
5654  * Dump internal FW/HW data for debug purposes.
5655  *
5656  **/
5657 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5658                                 u8 table_id, u32 start_index, u16 buff_size,
5659                                 void *buff, u16 *ret_buff_size,
5660                                 u8 *ret_next_table, u32 *ret_next_index,
5661                                 struct i40e_asq_cmd_details *cmd_details)
5662 {
5663         struct i40e_aq_desc desc;
5664         struct i40e_aqc_debug_dump_internals *cmd =
5665                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5666         struct i40e_aqc_debug_dump_internals *resp =
5667                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5668         enum i40e_status_code status;
5669
5670         if (buff_size == 0 || !buff)
5671                 return I40E_ERR_PARAM;
5672
5673         i40e_fill_default_direct_cmd_desc(&desc,
5674                                           i40e_aqc_opc_debug_dump_internals);
5675         /* Indirect Command */
5676         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5677         if (buff_size > I40E_AQ_LARGE_BUF)
5678                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5679
5680         cmd->cluster_id = cluster_id;
5681         cmd->table_id = table_id;
5682         cmd->idx = CPU_TO_LE32(start_index);
5683
5684         desc.datalen = CPU_TO_LE16(buff_size);
5685
5686         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5687         if (!status) {
5688                 if (ret_buff_size != NULL)
5689                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5690                 if (ret_next_table != NULL)
5691                         *ret_next_table = resp->table_id;
5692                 if (ret_next_index != NULL)
5693                         *ret_next_index = LE32_TO_CPU(resp->idx);
5694         }
5695
5696         return status;
5697 }
5698
5699 /**
5700  * i40e_read_bw_from_alt_ram
5701  * @hw: pointer to the hardware structure
5702  * @max_bw: pointer for max_bw read
5703  * @min_bw: pointer for min_bw read
5704  * @min_valid: pointer for bool that is true if min_bw is a valid value
5705  * @max_valid: pointer for bool that is true if max_bw is a valid value
5706  *
5707  * Read bw from the alternate ram for the given pf
5708  **/
5709 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5710                                         u32 *max_bw, u32 *min_bw,
5711                                         bool *min_valid, bool *max_valid)
5712 {
5713         enum i40e_status_code status;
5714         u32 max_bw_addr, min_bw_addr;
5715
5716         /* Calculate the address of the min/max bw registers */
5717         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5718                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5719                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5720         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5721                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5722                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5723
5724         /* Read the bandwidths from alt ram */
5725         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5726                                         min_bw_addr, min_bw);
5727
5728         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5729                 *min_valid = true;
5730         else
5731                 *min_valid = false;
5732
5733         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5734                 *max_valid = true;
5735         else
5736                 *max_valid = false;
5737
5738         return status;
5739 }
5740
5741 /**
5742  * i40e_aq_configure_partition_bw
5743  * @hw: pointer to the hardware structure
5744  * @bw_data: Buffer holding valid pfs and bw limits
5745  * @cmd_details: pointer to command details
5746  *
5747  * Configure partitions guaranteed/max bw
5748  **/
5749 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5750                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5751                         struct i40e_asq_cmd_details *cmd_details)
5752 {
5753         enum i40e_status_code status;
5754         struct i40e_aq_desc desc;
5755         u16 bwd_size = sizeof(*bw_data);
5756
5757         i40e_fill_default_direct_cmd_desc(&desc,
5758                                 i40e_aqc_opc_configure_partition_bw);
5759
5760         /* Indirect command */
5761         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5762         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5763
5764         if (bwd_size > I40E_AQ_LARGE_BUF)
5765                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5766
5767         desc.datalen = CPU_TO_LE16(bwd_size);
5768
5769         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5770
5771         return status;
5772 }
5773 #endif /* PF_DRIVER */
5774 #ifdef VF_DRIVER
5775
5776 /**
5777  * i40e_aq_send_msg_to_pf
5778  * @hw: pointer to the hardware structure
5779  * @v_opcode: opcodes for VF-PF communication
5780  * @v_retval: return error code
5781  * @msg: pointer to the msg buffer
5782  * @msglen: msg length
5783  * @cmd_details: pointer to command details
5784  *
5785  * Send message to PF driver using admin queue. By default, this message
5786  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5787  * completion before returning.
5788  **/
5789 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5790                                 enum i40e_virtchnl_ops v_opcode,
5791                                 enum i40e_status_code v_retval,
5792                                 u8 *msg, u16 msglen,
5793                                 struct i40e_asq_cmd_details *cmd_details)
5794 {
5795         struct i40e_aq_desc desc;
5796         struct i40e_asq_cmd_details details;
5797         enum i40e_status_code status;
5798
5799         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5800         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5801         desc.cookie_high = CPU_TO_LE32(v_opcode);
5802         desc.cookie_low = CPU_TO_LE32(v_retval);
5803         if (msglen) {
5804                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5805                                                 | I40E_AQ_FLAG_RD));
5806                 if (msglen > I40E_AQ_LARGE_BUF)
5807                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5808                 desc.datalen = CPU_TO_LE16(msglen);
5809         }
5810         if (!cmd_details) {
5811                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5812                 details.async = true;
5813                 cmd_details = &details;
5814         }
5815         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5816                                        msglen, cmd_details);
5817         return status;
5818 }
5819
5820 /**
5821  * i40e_vf_parse_hw_config
5822  * @hw: pointer to the hardware structure
5823  * @msg: pointer to the virtual channel VF resource structure
5824  *
5825  * Given a VF resource message from the PF, populate the hw struct
5826  * with appropriate information.
5827  **/
5828 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5829                              struct i40e_virtchnl_vf_resource *msg)
5830 {
5831         struct i40e_virtchnl_vsi_resource *vsi_res;
5832         int i;
5833
5834         vsi_res = &msg->vsi_res[0];
5835
5836         hw->dev_caps.num_vsis = msg->num_vsis;
5837         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5838         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5839         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5840         hw->dev_caps.dcb = msg->vf_offload_flags &
5841                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
5842         hw->dev_caps.fcoe = (msg->vf_offload_flags &
5843                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5844         hw->dev_caps.iwarp = (msg->vf_offload_flags &
5845                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5846         for (i = 0; i < msg->num_vsis; i++) {
5847                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5848                         i40e_memcpy(hw->mac.perm_addr,
5849                                     vsi_res->default_mac_addr,
5850                                     I40E_ETH_LENGTH_OF_ADDRESS,
5851                                     I40E_NONDMA_TO_NONDMA);
5852                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5853                                     I40E_ETH_LENGTH_OF_ADDRESS,
5854                                     I40E_NONDMA_TO_NONDMA);
5855                 }
5856                 vsi_res++;
5857         }
5858 }
5859
5860 /**
5861  * i40e_vf_reset
5862  * @hw: pointer to the hardware structure
5863  *
5864  * Send a VF_RESET message to the PF. Does not wait for response from PF
5865  * as none will be forthcoming. Immediately after calling this function,
5866  * the admin queue should be shut down and (optionally) reinitialized.
5867  **/
5868 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5869 {
5870         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5871                                       I40E_SUCCESS, NULL, 0, NULL);
5872 }
5873 #endif /* VF_DRIVER */
5874 #ifdef X722_SUPPORT
5875
5876 /**
5877  * i40e_aq_set_arp_proxy_config
5878  * @hw: pointer to the HW structure
5879  * @proxy_config - pointer to proxy config command table struct
5880  * @cmd_details: pointer to command details
5881  *
5882  * Set ARP offload parameters from pre-populated
5883  * i40e_aqc_arp_proxy_data struct
5884  **/
5885 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
5886                                 struct i40e_aqc_arp_proxy_data *proxy_config,
5887                                 struct i40e_asq_cmd_details *cmd_details)
5888 {
5889         struct i40e_aq_desc desc;
5890         enum i40e_status_code status;
5891
5892         if (!proxy_config)
5893                 return I40E_ERR_PARAM;
5894
5895         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
5896
5897         desc.params.external.addr_high =
5898                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
5899         desc.params.external.addr_low =
5900                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
5901
5902         status = i40e_asq_send_command(hw, &desc, proxy_config,
5903                                        sizeof(struct i40e_aqc_arp_proxy_data),
5904                                        cmd_details);
5905
5906         return status;
5907 }
5908
5909 /**
5910  * i40e_aq_opc_set_ns_proxy_table_entry
5911  * @hw: pointer to the HW structure
5912  * @ns_proxy_table_entry: pointer to NS table entry command struct
5913  * @cmd_details: pointer to command details
5914  *
5915  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
5916  * from pre-populated i40e_aqc_ns_proxy_data struct
5917  **/
5918 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
5919                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
5920                         struct i40e_asq_cmd_details *cmd_details)
5921 {
5922         struct i40e_aq_desc desc;
5923         enum i40e_status_code status;
5924
5925         if (!ns_proxy_table_entry)
5926                 return I40E_ERR_PARAM;
5927
5928         i40e_fill_default_direct_cmd_desc(&desc,
5929                                 i40e_aqc_opc_set_ns_proxy_table_entry);
5930
5931         desc.params.external.addr_high =
5932                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
5933         desc.params.external.addr_low =
5934                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
5935
5936         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
5937                                        sizeof(struct i40e_aqc_ns_proxy_data),
5938                                        cmd_details);
5939
5940         return status;
5941 }
5942
5943 /**
5944  * i40e_aq_set_clear_wol_filter
5945  * @hw: pointer to the hw struct
5946  * @filter_index: index of filter to modify (0-7)
5947  * @filter: buffer containing filter to be set
5948  * @set_filter: true to set filter, false to clear filter
5949  * @no_wol_tco: if true, pass through packets cannot cause wake-up
5950  *              if false, pass through packets may cause wake-up
5951  * @filter_valid: true if filter action is valid
5952  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
5953  * @cmd_details: pointer to command details structure or NULL
5954  *
5955  * Set or clear WoL filter for port attached to the PF
5956  **/
5957 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
5958                                 u8 filter_index,
5959                                 struct i40e_aqc_set_wol_filter_data *filter,
5960                                 bool set_filter, bool no_wol_tco,
5961                                 bool filter_valid, bool no_wol_tco_valid,
5962                                 struct i40e_asq_cmd_details *cmd_details)
5963 {
5964         struct i40e_aq_desc desc;
5965         struct i40e_aqc_set_wol_filter *cmd =
5966                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
5967         enum i40e_status_code status;
5968         u16 cmd_flags = 0;
5969         u16 valid_flags = 0;
5970         u16 buff_len = 0;
5971
5972         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
5973
5974         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
5975                 return  I40E_ERR_PARAM;
5976         cmd->filter_index = CPU_TO_LE16(filter_index);
5977
5978         if (set_filter) {
5979                 if (!filter)
5980                         return  I40E_ERR_PARAM;
5981                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
5982                 buff_len = sizeof(*filter);
5983         }
5984         if (no_wol_tco)
5985                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
5986         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
5987
5988         if (filter_valid)
5989                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
5990         if (no_wol_tco_valid)
5991                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
5992         cmd->valid_flags = CPU_TO_LE16(valid_flags);
5993
5994         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
5995         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
5996
5997         status = i40e_asq_send_command(hw, &desc, filter,
5998                                        buff_len, cmd_details);
5999
6000         return status;
6001 }
6002
6003 /**
6004  * i40e_aq_get_wake_event_reason
6005  * @hw: pointer to the hw struct
6006  * @wake_reason: return value, index of matching filter
6007  * @cmd_details: pointer to command details structure or NULL
6008  *
6009  * Get information for the reason of a Wake Up event
6010  **/
6011 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6012                                 u16 *wake_reason,
6013                                 struct i40e_asq_cmd_details *cmd_details)
6014 {
6015         struct i40e_aq_desc desc;
6016         struct i40e_aqc_get_wake_reason_completion *resp =
6017                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6018         enum i40e_status_code status;
6019
6020         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6021
6022         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6023
6024         if (status == I40E_SUCCESS)
6025                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6026
6027         return status;
6028 }
6029
6030 #endif /* X722_SUPPORT */