drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_A:
  62                 case I40E_DEV_ID_KX_B:
  63                 case I40E_DEV_ID_KX_C:
  64                 case I40E_DEV_ID_QSFP_A:
  65                 case I40E_DEV_ID_QSFP_B:
  66                 case I40E_DEV_ID_QSFP_C:
  67                 case I40E_DEV_ID_10G_BASE_T:
  68                 case I40E_DEV_ID_10G_BASE_T4:
  69                 case I40E_DEV_ID_20G_KR2:
  70                 case I40E_DEV_ID_20G_KR2_A:
  71                         hw->mac.type = I40E_MAC_XL710;
  72                         break;
  73                 case I40E_DEV_ID_VF:
  74                 case I40E_DEV_ID_VF_HV:
  75                         hw->mac.type = I40E_MAC_VF;
  76                         break;
  77                 default:
  78                         hw->mac.type = I40E_MAC_GENERIC;
  79                         break;
  80                 }
  81         } else {
  82                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  83         }
  84
  85         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  86                   hw->mac.type, status);
  87         return status;
  88 }
  89
  90 #ifndef I40E_NDIS_SUPPORT
  91 /**
  92  * i40e_aq_str - convert AQ err code to a string
  93  * @hw: pointer to the HW structure
  94  * @aq_err: the AQ error code to convert
  95  **/
  96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  97 {
  98         switch (aq_err) {
  99         case I40E_AQ_RC_OK:
 100                 return "OK";
 101         case I40E_AQ_RC_EPERM:
 102                 return "I40E_AQ_RC_EPERM";
 103         case I40E_AQ_RC_ENOENT:
 104                 return "I40E_AQ_RC_ENOENT";
 105         case I40E_AQ_RC_ESRCH:
 106                 return "I40E_AQ_RC_ESRCH";
 107         case I40E_AQ_RC_EINTR:
 108                 return "I40E_AQ_RC_EINTR";
 109         case I40E_AQ_RC_EIO:
 110                 return "I40E_AQ_RC_EIO";
 111         case I40E_AQ_RC_ENXIO:
 112                 return "I40E_AQ_RC_ENXIO";
 113         case I40E_AQ_RC_E2BIG:
 114                 return "I40E_AQ_RC_E2BIG";
 115         case I40E_AQ_RC_EAGAIN:
 116                 return "I40E_AQ_RC_EAGAIN";
 117         case I40E_AQ_RC_ENOMEM:
 118                 return "I40E_AQ_RC_ENOMEM";
 119         case I40E_AQ_RC_EACCES:
 120                 return "I40E_AQ_RC_EACCES";
 121         case I40E_AQ_RC_EFAULT:
 122                 return "I40E_AQ_RC_EFAULT";
 123         case I40E_AQ_RC_EBUSY:
 124                 return "I40E_AQ_RC_EBUSY";
 125         case I40E_AQ_RC_EEXIST:
 126                 return "I40E_AQ_RC_EEXIST";
 127         case I40E_AQ_RC_EINVAL:
 128                 return "I40E_AQ_RC_EINVAL";
 129         case I40E_AQ_RC_ENOTTY:
 130                 return "I40E_AQ_RC_ENOTTY";
 131         case I40E_AQ_RC_ENOSPC:
 132                 return "I40E_AQ_RC_ENOSPC";
 133         case I40E_AQ_RC_ENOSYS:
 134                 return "I40E_AQ_RC_ENOSYS";
 135         case I40E_AQ_RC_ERANGE:
 136                 return "I40E_AQ_RC_ERANGE";
 137         case I40E_AQ_RC_EFLUSHED:
 138                 return "I40E_AQ_RC_EFLUSHED";
 139         case I40E_AQ_RC_BAD_ADDR:
 140                 return "I40E_AQ_RC_BAD_ADDR";
 141         case I40E_AQ_RC_EMODE:
 142                 return "I40E_AQ_RC_EMODE";
 143         case I40E_AQ_RC_EFBIG:
 144                 return "I40E_AQ_RC_EFBIG";
 145         }
 146
 147         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 148         return hw->err_str;
 149 }
 150
 151 /**
 152  * i40e_stat_str - convert status err code to a string
 153  * @hw: pointer to the HW structure
 154  * @stat_err: the status error code to convert
 155  **/
 156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 157 {
 158         switch (stat_err) {
 159         case I40E_SUCCESS:
 160                 return "OK";
 161         case I40E_ERR_NVM:
 162                 return "I40E_ERR_NVM";
 163         case I40E_ERR_NVM_CHECKSUM:
 164                 return "I40E_ERR_NVM_CHECKSUM";
 165         case I40E_ERR_PHY:
 166                 return "I40E_ERR_PHY";
 167         case I40E_ERR_CONFIG:
 168                 return "I40E_ERR_CONFIG";
 169         case I40E_ERR_PARAM:
 170                 return "I40E_ERR_PARAM";
 171         case I40E_ERR_MAC_TYPE:
 172                 return "I40E_ERR_MAC_TYPE";
 173         case I40E_ERR_UNKNOWN_PHY:
 174                 return "I40E_ERR_UNKNOWN_PHY";
 175         case I40E_ERR_LINK_SETUP:
 176                 return "I40E_ERR_LINK_SETUP";
 177         case I40E_ERR_ADAPTER_STOPPED:
 178                 return "I40E_ERR_ADAPTER_STOPPED";
 179         case I40E_ERR_INVALID_MAC_ADDR:
 180                 return "I40E_ERR_INVALID_MAC_ADDR";
 181         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 182                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 183         case I40E_ERR_MASTER_REQUESTS_PENDING:
 184                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 185         case I40E_ERR_INVALID_LINK_SETTINGS:
 186                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 187         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 188                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 189         case I40E_ERR_RESET_FAILED:
 190                 return "I40E_ERR_RESET_FAILED";
 191         case I40E_ERR_SWFW_SYNC:
 192                 return "I40E_ERR_SWFW_SYNC";
 193         case I40E_ERR_NO_AVAILABLE_VSI:
 194                 return "I40E_ERR_NO_AVAILABLE_VSI";
 195         case I40E_ERR_NO_MEMORY:
 196                 return "I40E_ERR_NO_MEMORY";
 197         case I40E_ERR_BAD_PTR:
 198                 return "I40E_ERR_BAD_PTR";
 199         case I40E_ERR_RING_FULL:
 200                 return "I40E_ERR_RING_FULL";
 201         case I40E_ERR_INVALID_PD_ID:
 202                 return "I40E_ERR_INVALID_PD_ID";
 203         case I40E_ERR_INVALID_QP_ID:
 204                 return "I40E_ERR_INVALID_QP_ID";
 205         case I40E_ERR_INVALID_CQ_ID:
 206                 return "I40E_ERR_INVALID_CQ_ID";
 207         case I40E_ERR_INVALID_CEQ_ID:
 208                 return "I40E_ERR_INVALID_CEQ_ID";
 209         case I40E_ERR_INVALID_AEQ_ID:
 210                 return "I40E_ERR_INVALID_AEQ_ID";
 211         case I40E_ERR_INVALID_SIZE:
 212                 return "I40E_ERR_INVALID_SIZE";
 213         case I40E_ERR_INVALID_ARP_INDEX:
 214                 return "I40E_ERR_INVALID_ARP_INDEX";
 215         case I40E_ERR_INVALID_FPM_FUNC_ID:
 216                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 217         case I40E_ERR_QP_INVALID_MSG_SIZE:
 218                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 219         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 220                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 221         case I40E_ERR_INVALID_FRAG_COUNT:
 222                 return "I40E_ERR_INVALID_FRAG_COUNT";
 223         case I40E_ERR_QUEUE_EMPTY:
 224                 return "I40E_ERR_QUEUE_EMPTY";
 225         case I40E_ERR_INVALID_ALIGNMENT:
 226                 return "I40E_ERR_INVALID_ALIGNMENT";
 227         case I40E_ERR_FLUSHED_QUEUE:
 228                 return "I40E_ERR_FLUSHED_QUEUE";
 229         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 230                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 231         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 232                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 233         case I40E_ERR_TIMEOUT:
 234                 return "I40E_ERR_TIMEOUT";
 235         case I40E_ERR_OPCODE_MISMATCH:
 236                 return "I40E_ERR_OPCODE_MISMATCH";
 237         case I40E_ERR_CQP_COMPL_ERROR:
 238                 return "I40E_ERR_CQP_COMPL_ERROR";
 239         case I40E_ERR_INVALID_VF_ID:
 240                 return "I40E_ERR_INVALID_VF_ID";
 241         case I40E_ERR_INVALID_HMCFN_ID:
 242                 return "I40E_ERR_INVALID_HMCFN_ID";
 243         case I40E_ERR_BACKING_PAGE_ERROR:
 244                 return "I40E_ERR_BACKING_PAGE_ERROR";
 245         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 246                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 247         case I40E_ERR_INVALID_PBLE_INDEX:
 248                 return "I40E_ERR_INVALID_PBLE_INDEX";
 249         case I40E_ERR_INVALID_SD_INDEX:
 250                 return "I40E_ERR_INVALID_SD_INDEX";
 251         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 252                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 253         case I40E_ERR_INVALID_SD_TYPE:
 254                 return "I40E_ERR_INVALID_SD_TYPE";
 255         case I40E_ERR_MEMCPY_FAILED:
 256                 return "I40E_ERR_MEMCPY_FAILED";
 257         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 258                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 259         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 260                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 261         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 262                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 263         case I40E_ERR_SRQ_ENABLED:
 264                 return "I40E_ERR_SRQ_ENABLED";
 265         case I40E_ERR_ADMIN_QUEUE_ERROR:
 266                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 267         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 268                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 269         case I40E_ERR_BUF_TOO_SHORT:
 270                 return "I40E_ERR_BUF_TOO_SHORT";
 271         case I40E_ERR_ADMIN_QUEUE_FULL:
 272                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 273         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 274                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 275         case I40E_ERR_BAD_IWARP_CQE:
 276                 return "I40E_ERR_BAD_IWARP_CQE";
 277         case I40E_ERR_NVM_BLANK_MODE:
 278                 return "I40E_ERR_NVM_BLANK_MODE";
 279         case I40E_ERR_NOT_IMPLEMENTED:
 280                 return "I40E_ERR_NOT_IMPLEMENTED";
 281         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 282                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 283         case I40E_ERR_DIAG_TEST_FAILED:
 284                 return "I40E_ERR_DIAG_TEST_FAILED";
 285         case I40E_ERR_NOT_READY:
 286                 return "I40E_ERR_NOT_READY";
 287         case I40E_NOT_SUPPORTED:
 288                 return "I40E_NOT_SUPPORTED";
 289         case I40E_ERR_FIRMWARE_API_VERSION:
 290                 return "I40E_ERR_FIRMWARE_API_VERSION";
 291         }
 292
 293         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 294         return hw->err_str;
 295 }
 296
 297 #endif /* I40E_NDIS_SUPPORT */
 298 /**
 299  * i40e_debug_aq
 300  * @hw: debug mask related to admin queue
 301  * @mask: debug mask
 302  * @desc: pointer to admin queue descriptor
 303  * @buffer: pointer to command buffer
 304  * @buf_len: max length of buffer
 305  *
 306  * Dumps debug log about adminq command with descriptor contents.
 307  **/
 308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 309                    void *buffer, u16 buf_len)
 310 {
 311         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 312         u16 len = LE16_TO_CPU(aq_desc->datalen);
 313         u8 *buf = (u8 *)buffer;
 314         u16 i = 0;
 315
 316         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 317                 return;
 318
 319         i40e_debug(hw, mask,
 320                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 321                    LE16_TO_CPU(aq_desc->opcode),
 322                    LE16_TO_CPU(aq_desc->flags),
 323                    LE16_TO_CPU(aq_desc->datalen),
 324                    LE16_TO_CPU(aq_desc->retval));
 325         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 326                    LE32_TO_CPU(aq_desc->cookie_high),
 327                    LE32_TO_CPU(aq_desc->cookie_low));
 328         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 329                    LE32_TO_CPU(aq_desc->params.internal.param0),
 330                    LE32_TO_CPU(aq_desc->params.internal.param1));
 331         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 333                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 334
 335         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 336                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 337                 if (buf_len < len)
 338                         len = buf_len;
 339                 /* write the full 16-byte chunks */
 340                 for (i = 0; i < (len - 16); i += 16)
 341                         i40e_debug(hw, mask,
 342                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 343                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 344                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 345                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 346                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 347                 /* the most we could have left is 16 bytes, pad with zeros */
 348                 if (i < len) {
 349                         char d_buf[16];
 350                         int j;
 351
 352                         memset(d_buf, 0, sizeof(d_buf));
 353                         for (j = 0; i < len; j++, i++)
 354                                 d_buf[j] = buf[i];
 355                         i40e_debug(hw, mask,
 356                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 357                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 358                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 359                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 360                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 361                 }
 362         }
 363 }
 364
 365 /**
 366  * i40e_check_asq_alive
 367  * @hw: pointer to the hw struct
 368  *
 369  * Returns true if Queue is enabled else false.
 370  **/
 371 bool i40e_check_asq_alive(struct i40e_hw *hw)
 372 {
 373         if (hw->aq.asq.len)
 374 #ifdef PF_DRIVER
 375 #ifdef INTEGRATED_VF
 376                 if (!i40e_is_vf(hw))
 377                         return !!(rd32(hw, hw->aq.asq.len) &
 378                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 379 #else
 380                 return !!(rd32(hw, hw->aq.asq.len) &
 381                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 382 #endif /* INTEGRATED_VF */
 383 #endif /* PF_DRIVER */
 384 #ifdef VF_DRIVER
 385 #ifdef INTEGRATED_VF
 386                 if (i40e_is_vf(hw))
 387                         return !!(rd32(hw, hw->aq.asq.len) &
 388                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 389 #else
 390                 return !!(rd32(hw, hw->aq.asq.len) &
 391                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 392 #endif /* INTEGRATED_VF */
 393 #endif /* VF_DRIVER */
 394         return false;
 395 }
 396
 397 /**
 398  * i40e_aq_queue_shutdown
 399  * @hw: pointer to the hw struct
 400  * @unloading: is the driver unloading itself
 401  *
 402  * Tell the Firmware that we're shutting down the AdminQ and whether
 403  * or not the driver is unloading as well.
 404  **/
 405 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 406                                              bool unloading)
 407 {
 408         struct i40e_aq_desc desc;
 409         struct i40e_aqc_queue_shutdown *cmd =
 410                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 411         enum i40e_status_code status;
 412
 413         i40e_fill_default_direct_cmd_desc(&desc,
 414                                           i40e_aqc_opc_queue_shutdown);
 415
 416         if (unloading)
 417                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 418         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 419
 420         return status;
 421 }
 422
 423 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 424  * hardware to a bit-field that can be used by SW to more easily determine the
 425  * packet type.
 426  *
 427  * Macros are used to shorten the table lines and make this table human
 428  * readable.
 429  *
 430  * We store the PTYPE in the top byte of the bit field - this is just so that
 431  * we can check that the table doesn't have a row missing, as the index into
 432  * the table should be the PTYPE.
 433  *
 434  * Typical work flow:
 435  *
 436  * IF NOT i40e_ptype_lookup[ptype].known
 437  * THEN
 438  *      Packet is unknown
 439  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 440  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 441  * ELSE
 442  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 443  * ENDIF
 444  */
 445
 446 /* macro to make the table lines short */
 447 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 448         {       PTYPE, \
 449                 1, \
 450                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 451                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 452                 I40E_RX_PTYPE_##OUTER_FRAG, \
 453                 I40E_RX_PTYPE_TUNNEL_##T, \
 454                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 455                 I40E_RX_PTYPE_##TEF, \
 456                 I40E_RX_PTYPE_INNER_PROT_##I, \
 457                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 458
 459 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 460                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 461
 462 /* shorter macros makes the table fit but are terse */
 463 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 464 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 465 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 466
 467 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 468 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 469         /* L2 Packet types */
 470         I40E_PTT_UNUSED_ENTRY(0),
 471         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 472         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 473         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 474         I40E_PTT_UNUSED_ENTRY(4),
 475         I40E_PTT_UNUSED_ENTRY(5),
 476         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 477         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 478         I40E_PTT_UNUSED_ENTRY(8),
 479         I40E_PTT_UNUSED_ENTRY(9),
 480         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 481         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 482         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 483         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 484         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 485         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 486         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 487         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 488         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 489         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 490         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 491         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 492
 493         /* Non Tunneled IPv4 */
 494         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 495         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 496         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 497         I40E_PTT_UNUSED_ENTRY(25),
 498         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 499         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 500         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 501
 502         /* IPv4 --> IPv4 */
 503         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 504         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 505         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 506         I40E_PTT_UNUSED_ENTRY(32),
 507         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 508         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 509         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 510
 511         /* IPv4 --> IPv6 */
 512         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 513         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 514         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 515         I40E_PTT_UNUSED_ENTRY(39),
 516         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 517         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 518         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 519
 520         /* IPv4 --> GRE/NAT */
 521         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 522
 523         /* IPv4 --> GRE/NAT --> IPv4 */
 524         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 525         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 526         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 527         I40E_PTT_UNUSED_ENTRY(47),
 528         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 529         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 530         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 531
 532         /* IPv4 --> GRE/NAT --> IPv6 */
 533         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 534         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 535         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 536         I40E_PTT_UNUSED_ENTRY(54),
 537         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 538         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 539         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 540
 541         /* IPv4 --> GRE/NAT --> MAC */
 542         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 543
 544         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 545         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 546         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 547         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 548         I40E_PTT_UNUSED_ENTRY(62),
 549         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 550         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 551         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 552
 553         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 554         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 555         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 556         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 557         I40E_PTT_UNUSED_ENTRY(69),
 558         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 559         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 560         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 561
 562         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 563         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 564
 565         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 566         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 567         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 568         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 569         I40E_PTT_UNUSED_ENTRY(77),
 570         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 571         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 572         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 573
 574         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 575         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 576         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 577         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 578         I40E_PTT_UNUSED_ENTRY(84),
 579         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 580         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 581         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 582
 583         /* Non Tunneled IPv6 */
 584         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 585         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 586         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 587         I40E_PTT_UNUSED_ENTRY(91),
 588         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 589         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 590         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 591
 592         /* IPv6 --> IPv4 */
 593         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 594         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 595         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 596         I40E_PTT_UNUSED_ENTRY(98),
 597         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 598         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 599         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 600
 601         /* IPv6 --> IPv6 */
 602         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 603         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 604         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 605         I40E_PTT_UNUSED_ENTRY(105),
 606         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 607         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 608         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 609
 610         /* IPv6 --> GRE/NAT */
 611         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 612
 613         /* IPv6 --> GRE/NAT -> IPv4 */
 614         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 615         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 616         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 617         I40E_PTT_UNUSED_ENTRY(113),
 618         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 619         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 620         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 621
 622         /* IPv6 --> GRE/NAT -> IPv6 */
 623         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 624         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 625         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 626         I40E_PTT_UNUSED_ENTRY(120),
 627         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 628         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 629         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 630
 631         /* IPv6 --> GRE/NAT -> MAC */
 632         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 633
 634         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 635         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 636         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 637         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 638         I40E_PTT_UNUSED_ENTRY(128),
 639         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 640         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 641         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 642
 643         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 644         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 645         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 646         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 647         I40E_PTT_UNUSED_ENTRY(135),
 648         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 649         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 650         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 651
 652         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 653         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 654
 655         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 656         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 657         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 658         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 659         I40E_PTT_UNUSED_ENTRY(143),
 660         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 661         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 662         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 663
 664         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 665         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 666         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 667         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 668         I40E_PTT_UNUSED_ENTRY(150),
 669         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 670         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 671         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 672
 673         /* unused entries */
 674         I40E_PTT_UNUSED_ENTRY(154),
 675         I40E_PTT_UNUSED_ENTRY(155),
 676         I40E_PTT_UNUSED_ENTRY(156),
 677         I40E_PTT_UNUSED_ENTRY(157),
 678         I40E_PTT_UNUSED_ENTRY(158),
 679         I40E_PTT_UNUSED_ENTRY(159),
 680
 681         I40E_PTT_UNUSED_ENTRY(160),
 682         I40E_PTT_UNUSED_ENTRY(161),
 683         I40E_PTT_UNUSED_ENTRY(162),
 684         I40E_PTT_UNUSED_ENTRY(163),
 685         I40E_PTT_UNUSED_ENTRY(164),
 686         I40E_PTT_UNUSED_ENTRY(165),
 687         I40E_PTT_UNUSED_ENTRY(166),
 688         I40E_PTT_UNUSED_ENTRY(167),
 689         I40E_PTT_UNUSED_ENTRY(168),
 690         I40E_PTT_UNUSED_ENTRY(169),
 691
 692         I40E_PTT_UNUSED_ENTRY(170),
 693         I40E_PTT_UNUSED_ENTRY(171),
 694         I40E_PTT_UNUSED_ENTRY(172),
 695         I40E_PTT_UNUSED_ENTRY(173),
 696         I40E_PTT_UNUSED_ENTRY(174),
 697         I40E_PTT_UNUSED_ENTRY(175),
 698         I40E_PTT_UNUSED_ENTRY(176),
 699         I40E_PTT_UNUSED_ENTRY(177),
 700         I40E_PTT_UNUSED_ENTRY(178),
 701         I40E_PTT_UNUSED_ENTRY(179),
 702
 703         I40E_PTT_UNUSED_ENTRY(180),
 704         I40E_PTT_UNUSED_ENTRY(181),
 705         I40E_PTT_UNUSED_ENTRY(182),
 706         I40E_PTT_UNUSED_ENTRY(183),
 707         I40E_PTT_UNUSED_ENTRY(184),
 708         I40E_PTT_UNUSED_ENTRY(185),
 709         I40E_PTT_UNUSED_ENTRY(186),
 710         I40E_PTT_UNUSED_ENTRY(187),
 711         I40E_PTT_UNUSED_ENTRY(188),
 712         I40E_PTT_UNUSED_ENTRY(189),
 713
 714         I40E_PTT_UNUSED_ENTRY(190),
 715         I40E_PTT_UNUSED_ENTRY(191),
 716         I40E_PTT_UNUSED_ENTRY(192),
 717         I40E_PTT_UNUSED_ENTRY(193),
 718         I40E_PTT_UNUSED_ENTRY(194),
 719         I40E_PTT_UNUSED_ENTRY(195),
 720         I40E_PTT_UNUSED_ENTRY(196),
 721         I40E_PTT_UNUSED_ENTRY(197),
 722         I40E_PTT_UNUSED_ENTRY(198),
 723         I40E_PTT_UNUSED_ENTRY(199),
 724
 725         I40E_PTT_UNUSED_ENTRY(200),
 726         I40E_PTT_UNUSED_ENTRY(201),
 727         I40E_PTT_UNUSED_ENTRY(202),
 728         I40E_PTT_UNUSED_ENTRY(203),
 729         I40E_PTT_UNUSED_ENTRY(204),
 730         I40E_PTT_UNUSED_ENTRY(205),
 731         I40E_PTT_UNUSED_ENTRY(206),
 732         I40E_PTT_UNUSED_ENTRY(207),
 733         I40E_PTT_UNUSED_ENTRY(208),
 734         I40E_PTT_UNUSED_ENTRY(209),
 735
 736         I40E_PTT_UNUSED_ENTRY(210),
 737         I40E_PTT_UNUSED_ENTRY(211),
 738         I40E_PTT_UNUSED_ENTRY(212),
 739         I40E_PTT_UNUSED_ENTRY(213),
 740         I40E_PTT_UNUSED_ENTRY(214),
 741         I40E_PTT_UNUSED_ENTRY(215),
 742         I40E_PTT_UNUSED_ENTRY(216),
 743         I40E_PTT_UNUSED_ENTRY(217),
 744         I40E_PTT_UNUSED_ENTRY(218),
 745         I40E_PTT_UNUSED_ENTRY(219),
 746
 747         I40E_PTT_UNUSED_ENTRY(220),
 748         I40E_PTT_UNUSED_ENTRY(221),
 749         I40E_PTT_UNUSED_ENTRY(222),
 750         I40E_PTT_UNUSED_ENTRY(223),
 751         I40E_PTT_UNUSED_ENTRY(224),
 752         I40E_PTT_UNUSED_ENTRY(225),
 753         I40E_PTT_UNUSED_ENTRY(226),
 754         I40E_PTT_UNUSED_ENTRY(227),
 755         I40E_PTT_UNUSED_ENTRY(228),
 756         I40E_PTT_UNUSED_ENTRY(229),
 757
 758         I40E_PTT_UNUSED_ENTRY(230),
 759         I40E_PTT_UNUSED_ENTRY(231),
 760         I40E_PTT_UNUSED_ENTRY(232),
 761         I40E_PTT_UNUSED_ENTRY(233),
 762         I40E_PTT_UNUSED_ENTRY(234),
 763         I40E_PTT_UNUSED_ENTRY(235),
 764         I40E_PTT_UNUSED_ENTRY(236),
 765         I40E_PTT_UNUSED_ENTRY(237),
 766         I40E_PTT_UNUSED_ENTRY(238),
 767         I40E_PTT_UNUSED_ENTRY(239),
 768
 769         I40E_PTT_UNUSED_ENTRY(240),
 770         I40E_PTT_UNUSED_ENTRY(241),
 771         I40E_PTT_UNUSED_ENTRY(242),
 772         I40E_PTT_UNUSED_ENTRY(243),
 773         I40E_PTT_UNUSED_ENTRY(244),
 774         I40E_PTT_UNUSED_ENTRY(245),
 775         I40E_PTT_UNUSED_ENTRY(246),
 776         I40E_PTT_UNUSED_ENTRY(247),
 777         I40E_PTT_UNUSED_ENTRY(248),
 778         I40E_PTT_UNUSED_ENTRY(249),
 779
 780         I40E_PTT_UNUSED_ENTRY(250),
 781         I40E_PTT_UNUSED_ENTRY(251),
 782         I40E_PTT_UNUSED_ENTRY(252),
 783         I40E_PTT_UNUSED_ENTRY(253),
 784         I40E_PTT_UNUSED_ENTRY(254),
 785         I40E_PTT_UNUSED_ENTRY(255)
 786 };
 787
 788
 789 /**
 790  * i40e_validate_mac_addr - Validate unicast MAC address
 791  * @mac_addr: pointer to MAC address
 792  *
 793  * Tests a MAC address to ensure it is a valid Individual Address
 794  **/
 795 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 796 {
 797         enum i40e_status_code status = I40E_SUCCESS;
 798
 799         DEBUGFUNC("i40e_validate_mac_addr");
 800
 801         /* Broadcast addresses ARE multicast addresses
 802          * Make sure it is not a multicast address
 803          * Reject the zero address
 804          */
 805         if (I40E_IS_MULTICAST(mac_addr) ||
 806             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 807               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 808                 status = I40E_ERR_INVALID_MAC_ADDR;
 809
 810         return status;
 811 }
 812 #ifdef PF_DRIVER
 813
 814 /**
 815  * i40e_init_shared_code - Initialize the shared code
 816  * @hw: pointer to hardware structure
 817  *
 818  * This assigns the MAC type and PHY code and inits the NVM.
 819  * Does not touch the hardware. This function must be called prior to any
 820  * other function in the shared code. The i40e_hw structure should be
 821  * memset to 0 prior to calling this function.  The following fields in
 822  * hw structure should be filled in prior to calling this function:
 823  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 824  * subsystem_vendor_id, and revision_id
 825  **/
 826 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 827 {
 828         enum i40e_status_code status = I40E_SUCCESS;
 829         u32 port, ari, func_rid;
 830
 831         DEBUGFUNC("i40e_init_shared_code");
 832
 833         i40e_set_mac_type(hw);
 834
 835         switch (hw->mac.type) {
 836         case I40E_MAC_XL710:
 837                 break;
 838         default:
 839                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 840         }
 841
 842         hw->phy.get_link_info = true;
 843
 844         /* Determine port number and PF number*/
 845         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 846                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 847         hw->port = (u8)port;
 848         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 849                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 850         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 851         if (ari)
 852                 hw->pf_id = (u8)(func_rid & 0xff);
 853         else
 854                 hw->pf_id = (u8)(func_rid & 0x7);
 855
 856         status = i40e_init_nvm(hw);
 857         return status;
 858 }
 859
 860 /**
 861  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 862  * @hw: pointer to the hw struct
 863  * @flags: a return indicator of what addresses were added to the addr store
 864  * @addrs: the requestor's mac addr store
 865  * @cmd_details: pointer to command details structure or NULL
 866  **/
 867 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
 868                                    u16 *flags,
 869                                    struct i40e_aqc_mac_address_read_data *addrs,
 870                                    struct i40e_asq_cmd_details *cmd_details)
 871 {
 872         struct i40e_aq_desc desc;
 873         struct i40e_aqc_mac_address_read *cmd_data =
 874                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 875         enum i40e_status_code status;
 876
 877         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 878         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
 879
 880         status = i40e_asq_send_command(hw, &desc, addrs,
 881                                        sizeof(*addrs), cmd_details);
 882         *flags = LE16_TO_CPU(cmd_data->command_flags);
 883
 884         return status;
 885 }
 886
 887 /**
 888  * i40e_aq_mac_address_write - Change the MAC addresses
 889  * @hw: pointer to the hw struct
 890  * @flags: indicates which MAC to be written
 891  * @mac_addr: address to write
 892  * @cmd_details: pointer to command details structure or NULL
 893  **/
 894 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
 895                                     u16 flags, u8 *mac_addr,
 896                                     struct i40e_asq_cmd_details *cmd_details)
 897 {
 898         struct i40e_aq_desc desc;
 899         struct i40e_aqc_mac_address_write *cmd_data =
 900                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 901         enum i40e_status_code status;
 902
 903         i40e_fill_default_direct_cmd_desc(&desc,
 904                                           i40e_aqc_opc_mac_address_write);
 905         cmd_data->command_flags = CPU_TO_LE16(flags);
 906         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
 907         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
 908                                         ((u32)mac_addr[3] << 16) |
 909                                         ((u32)mac_addr[4] << 8) |
 910                                         mac_addr[5]);
 911
 912         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 913
 914         return status;
 915 }
 916
 917 /**
 918  * i40e_get_mac_addr - get MAC address
 919  * @hw: pointer to the HW structure
 920  * @mac_addr: pointer to MAC address
 921  *
 922  * Reads the adapter's MAC address from register
 923  **/
 924 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
 925 {
 926         struct i40e_aqc_mac_address_read_data addrs;
 927         enum i40e_status_code status;
 928         u16 flags = 0;
 929
 930         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
 931
 932         if (flags & I40E_AQC_LAN_ADDR_VALID)
 933                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
 934
 935         return status;
 936 }
 937
 938 /**
 939  * i40e_get_port_mac_addr - get Port MAC address
 940  * @hw: pointer to the HW structure
 941  * @mac_addr: pointer to Port MAC address
 942  *
 943  * Reads the adapter's Port MAC address
 944  **/
 945 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
 946 {
 947         struct i40e_aqc_mac_address_read_data addrs;
 948         enum i40e_status_code status;
 949         u16 flags = 0;
 950
 951         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
 952         if (status)
 953                 return status;
 954
 955         if (flags & I40E_AQC_PORT_ADDR_VALID)
 956                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
 957         else
 958                 status = I40E_ERR_INVALID_MAC_ADDR;
 959
 960         return status;
 961 }
 962
 963 /**
 964  * i40e_pre_tx_queue_cfg - pre tx queue configure
 965  * @hw: pointer to the HW structure
 966  * @queue: target pf queue index
 967  * @enable: state change request
 968  *
 969  * Handles hw requirement to indicate intention to enable
 970  * or disable target queue.
 971  **/
 972 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
 973 {
 974         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
 975         u32 reg_block = 0;
 976         u32 reg_val;
 977
 978         if (abs_queue_idx >= 128) {
 979                 reg_block = abs_queue_idx / 128;
 980                 abs_queue_idx %= 128;
 981         }
 982
 983         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
 984         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
 985         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
 986
 987         if (enable)
 988                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
 989         else
 990                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
 991
 992         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
 993 }
 994
 995 /**
 996  *  i40e_read_pba_string - Reads part number string from EEPROM
 997  *  @hw: pointer to hardware structure
 998  *  @pba_num: stores the part number string from the EEPROM
 999  *  @pba_num_size: part number string buffer length
1000  *
1001  *  Reads the part number string from the EEPROM.
1002  **/
1003 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1004                                             u32 pba_num_size)
1005 {
1006         enum i40e_status_code status = I40E_SUCCESS;
1007         u16 pba_word = 0;
1008         u16 pba_size = 0;
1009         u16 pba_ptr = 0;
1010         u16 i = 0;
1011
1012         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1013         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1014                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1015                 return status;
1016         }
1017
1018         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1019         if (status != I40E_SUCCESS) {
1020                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1021                 return status;
1022         }
1023
1024         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1025         if (status != I40E_SUCCESS) {
1026                 DEBUGOUT("Failed to read PBA Block size.\n");
1027                 return status;
1028         }
1029
1030         /* Subtract one to get PBA word count (PBA Size word is included in
1031          * total size)
1032          */
1033         pba_size--;
1034         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1035                 DEBUGOUT("Buffer to small for PBA data.\n");
1036                 return I40E_ERR_PARAM;
1037         }
1038
1039         for (i = 0; i < pba_size; i++) {
1040                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1041                 if (status != I40E_SUCCESS) {
1042                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1043                         return status;
1044                 }
1045
1046                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1047                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1048         }
1049         pba_num[(pba_size * 2)] = '\0';
1050
1051         return status;
1052 }
1053
1054 /**
1055  * i40e_get_media_type - Gets media type
1056  * @hw: pointer to the hardware structure
1057  **/
1058 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1059 {
1060         enum i40e_media_type media;
1061
1062         switch (hw->phy.link_info.phy_type) {
1063         case I40E_PHY_TYPE_10GBASE_SR:
1064         case I40E_PHY_TYPE_10GBASE_LR:
1065         case I40E_PHY_TYPE_1000BASE_SX:
1066         case I40E_PHY_TYPE_1000BASE_LX:
1067         case I40E_PHY_TYPE_40GBASE_SR4:
1068         case I40E_PHY_TYPE_40GBASE_LR4:
1069                 media = I40E_MEDIA_TYPE_FIBER;
1070                 break;
1071         case I40E_PHY_TYPE_100BASE_TX:
1072         case I40E_PHY_TYPE_1000BASE_T:
1073         case I40E_PHY_TYPE_10GBASE_T:
1074                 media = I40E_MEDIA_TYPE_BASET;
1075                 break;
1076         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1077         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1078         case I40E_PHY_TYPE_10GBASE_CR1:
1079         case I40E_PHY_TYPE_40GBASE_CR4:
1080         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1081         case I40E_PHY_TYPE_40GBASE_AOC:
1082         case I40E_PHY_TYPE_10GBASE_AOC:
1083                 media = I40E_MEDIA_TYPE_DA;
1084                 break;
1085         case I40E_PHY_TYPE_1000BASE_KX:
1086         case I40E_PHY_TYPE_10GBASE_KX4:
1087         case I40E_PHY_TYPE_10GBASE_KR:
1088         case I40E_PHY_TYPE_40GBASE_KR4:
1089         case I40E_PHY_TYPE_20GBASE_KR2:
1090                 media = I40E_MEDIA_TYPE_BACKPLANE;
1091                 break;
1092         case I40E_PHY_TYPE_SGMII:
1093         case I40E_PHY_TYPE_XAUI:
1094         case I40E_PHY_TYPE_XFI:
1095         case I40E_PHY_TYPE_XLAUI:
1096         case I40E_PHY_TYPE_XLPPI:
1097         default:
1098                 media = I40E_MEDIA_TYPE_UNKNOWN;
1099                 break;
1100         }
1101
1102         return media;
1103 }
1104
1105 #define I40E_PF_RESET_WAIT_COUNT        200
1106 /**
1107  * i40e_pf_reset - Reset the PF
1108  * @hw: pointer to the hardware structure
1109  *
1110  * Assuming someone else has triggered a global reset,
1111  * assure the global reset is complete and then reset the PF
1112  **/
1113 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1114 {
1115         u32 cnt = 0;
1116         u32 cnt1 = 0;
1117         u32 reg = 0;
1118         u32 grst_del;
1119
1120         /* Poll for Global Reset steady state in case of recent GRST.
1121          * The grst delay value is in 100ms units, and we'll wait a
1122          * couple counts longer to be sure we don't just miss the end.
1123          */
1124         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1125                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1126                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1127 #ifdef I40E_ESS_SUPPORT
1128         /* It can take upto 15 secs for GRST steady state */
1129         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1130 #endif
1131         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1132                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1133                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1134                         break;
1135                 i40e_msec_delay(100);
1136         }
1137         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1138                 DEBUGOUT("Global reset polling failed to complete.\n");
1139                 return I40E_ERR_RESET_FAILED;
1140         }
1141
1142         /* Now Wait for the FW to be ready */
1143         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1144                 reg = rd32(hw, I40E_GLNVM_ULD);
1145                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1146                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1147                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1148                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1149                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1150                         break;
1151                 }
1152                 i40e_msec_delay(10);
1153         }
1154         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1155                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1156                 DEBUGOUT("wait for FW Reset complete timedout\n");
1157                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1158                 return I40E_ERR_RESET_FAILED;
1159         }
1160
1161         /* If there was a Global Reset in progress when we got here,
1162          * we don't need to do the PF Reset
1163          */
1164         if (!cnt) {
1165                 reg = rd32(hw, I40E_PFGEN_CTRL);
1166                 wr32(hw, I40E_PFGEN_CTRL,
1167                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1168                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1169                         reg = rd32(hw, I40E_PFGEN_CTRL);
1170                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1171                                 break;
1172                         i40e_msec_delay(1);
1173                 }
1174                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1175                         DEBUGOUT("PF reset polling failed to complete.\n");
1176                         return I40E_ERR_RESET_FAILED;
1177                 }
1178         }
1179
1180         i40e_clear_pxe_mode(hw);
1181
1182
1183         return I40E_SUCCESS;
1184 }
1185
1186 /**
1187  * i40e_clear_hw - clear out any left over hw state
1188  * @hw: pointer to the hw struct
1189  *
1190  * Clear queues and interrupts, typically called at init time,
1191  * but after the capabilities have been found so we know how many
1192  * queues and msix vectors have been allocated.
1193  **/
1194 void i40e_clear_hw(struct i40e_hw *hw)
1195 {
1196         u32 num_queues, base_queue;
1197         u32 num_pf_int;
1198         u32 num_vf_int;
1199         u32 num_vfs;
1200         u32 i, j;
1201         u32 val;
1202         u32 eol = 0x7ff;
1203
1204         /* get number of interrupts, queues, and vfs */
1205         val = rd32(hw, I40E_GLPCI_CNF2);
1206         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1207                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1208         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1209                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1210
1211         val = rd32(hw, I40E_PFLAN_QALLOC);
1212         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1213                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1214         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1215                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1216         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1217                 num_queues = (j - base_queue) + 1;
1218         else
1219                 num_queues = 0;
1220
1221         val = rd32(hw, I40E_PF_VT_PFALLOC);
1222         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1223                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1224         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1225                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1226         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1227                 num_vfs = (j - i) + 1;
1228         else
1229                 num_vfs = 0;
1230
1231         /* stop all the interrupts */
1232         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1233         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1234         for (i = 0; i < num_pf_int - 2; i++)
1235                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1236
1237         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1238         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1239         wr32(hw, I40E_PFINT_LNKLST0, val);
1240         for (i = 0; i < num_pf_int - 2; i++)
1241                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1242         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1243         for (i = 0; i < num_vfs; i++)
1244                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1245         for (i = 0; i < num_vf_int - 2; i++)
1246                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1247
1248         /* warn the HW of the coming Tx disables */
1249         for (i = 0; i < num_queues; i++) {
1250                 u32 abs_queue_idx = base_queue + i;
1251                 u32 reg_block = 0;
1252
1253                 if (abs_queue_idx >= 128) {
1254                         reg_block = abs_queue_idx / 128;
1255                         abs_queue_idx %= 128;
1256                 }
1257
1258                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1259                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1260                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1261                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1262
1263                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1264         }
1265         i40e_usec_delay(400);
1266
1267         /* stop all the queues */
1268         for (i = 0; i < num_queues; i++) {
1269                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1270                 wr32(hw, I40E_QTX_ENA(i), 0);
1271                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1272                 wr32(hw, I40E_QRX_ENA(i), 0);
1273         }
1274
1275         /* short wait for all queue disables to settle */
1276         i40e_usec_delay(50);
1277 }
1278
1279 /**
1280  * i40e_clear_pxe_mode - clear pxe operations mode
1281  * @hw: pointer to the hw struct
1282  *
1283  * Make sure all PXE mode settings are cleared, including things
1284  * like descriptor fetch/write-back mode.
1285  **/
1286 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1287 {
1288         if (i40e_check_asq_alive(hw))
1289                 i40e_aq_clear_pxe_mode(hw, NULL);
1290 }
1291
1292 /**
1293  * i40e_led_is_mine - helper to find matching led
1294  * @hw: pointer to the hw struct
1295  * @idx: index into GPIO registers
1296  *
1297  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1298  */
1299 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1300 {
1301         u32 gpio_val = 0;
1302         u32 port;
1303
1304         if (!hw->func_caps.led[idx])
1305                 return 0;
1306
1307         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1308         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1309                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1310
1311         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1312          * if it is not our port then ignore
1313          */
1314         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1315             (port != hw->port))
1316                 return 0;
1317
1318         return gpio_val;
1319 }
1320
1321 #define I40E_COMBINED_ACTIVITY 0xA
1322 #define I40E_FILTER_ACTIVITY 0xE
1323 #define I40E_LINK_ACTIVITY 0xC
1324 #define I40E_MAC_ACTIVITY 0xD
1325 #define I40E_LED0 22
1326
1327 /**
1328  * i40e_led_get - return current on/off mode
1329  * @hw: pointer to the hw struct
1330  *
1331  * The value returned is the 'mode' field as defined in the
1332  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1333  * values are variations of possible behaviors relating to
1334  * blink, link, and wire.
1335  **/
1336 u32 i40e_led_get(struct i40e_hw *hw)
1337 {
1338         u32 current_mode = 0;
1339         u32 mode = 0;
1340         int i;
1341
1342         /* as per the documentation GPIO 22-29 are the LED
1343          * GPIO pins named LED0..LED7
1344          */
1345         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1346                 u32 gpio_val = i40e_led_is_mine(hw, i);
1347
1348                 if (!gpio_val)
1349                         continue;
1350
1351                 /* ignore gpio LED src mode entries related to the activity LEDs */
1352                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1353                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1354                 switch (current_mode) {
1355                 case I40E_COMBINED_ACTIVITY:
1356                 case I40E_FILTER_ACTIVITY:
1357                 case I40E_MAC_ACTIVITY:
1358                         continue;
1359                 default:
1360                         break;
1361                 }
1362
1363                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1364                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1365                 break;
1366         }
1367
1368         return mode;
1369 }
1370
1371 /**
1372  * i40e_led_set - set new on/off mode
1373  * @hw: pointer to the hw struct
1374  * @mode: 0=off, 0xf=on (else see manual for mode details)
1375  * @blink: true if the LED should blink when on, false if steady
1376  *
1377  * if this function is used to turn on the blink it should
1378  * be used to disable the blink when restoring the original state.
1379  **/
1380 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1381 {
1382         u32 current_mode = 0;
1383         int i;
1384
1385         if (mode & 0xfffffff0)
1386                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1387
1388         /* as per the documentation GPIO 22-29 are the LED
1389          * GPIO pins named LED0..LED7
1390          */
1391         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1392                 u32 gpio_val = i40e_led_is_mine(hw, i);
1393
1394                 if (!gpio_val)
1395                         continue;
1396
1397                 /* ignore gpio LED src mode entries related to the activity LEDs */
1398                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1399                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1400                 switch (current_mode) {
1401                 case I40E_COMBINED_ACTIVITY:
1402                 case I40E_FILTER_ACTIVITY:
1403                 case I40E_MAC_ACTIVITY:
1404                         continue;
1405                 default:
1406                         break;
1407                 }
1408
1409                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1410                 /* this & is a bit of paranoia, but serves as a range check */
1411                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1412                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1413
1414                 if (mode == I40E_LINK_ACTIVITY)
1415                         blink = false;
1416
1417                 if (blink)
1418                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1419                 else
1420                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1421
1422                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1423                 break;
1424         }
1425 }
1426
1427 /* Admin command wrappers */
1428
1429 /**
1430  * i40e_aq_get_phy_capabilities
1431  * @hw: pointer to the hw struct
1432  * @abilities: structure for PHY capabilities to be filled
1433  * @qualified_modules: report Qualified Modules
1434  * @report_init: report init capabilities (active are default)
1435  * @cmd_details: pointer to command details structure or NULL
1436  *
1437  * Returns the various PHY abilities supported on the Port.
1438  **/
1439 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1440                         bool qualified_modules, bool report_init,
1441                         struct i40e_aq_get_phy_abilities_resp *abilities,
1442                         struct i40e_asq_cmd_details *cmd_details)
1443 {
1444         struct i40e_aq_desc desc;
1445         enum i40e_status_code status;
1446         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1447
1448         if (!abilities)
1449                 return I40E_ERR_PARAM;
1450
1451         i40e_fill_default_direct_cmd_desc(&desc,
1452                                           i40e_aqc_opc_get_phy_abilities);
1453
1454         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1455         if (abilities_size > I40E_AQ_LARGE_BUF)
1456                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1457
1458         if (qualified_modules)
1459                 desc.params.external.param0 |=
1460                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1461
1462         if (report_init)
1463                 desc.params.external.param0 |=
1464                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1465
1466         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1467                                     cmd_details);
1468
1469         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1470                 status = I40E_ERR_UNKNOWN_PHY;
1471
1472         if (report_init)
1473                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1474
1475         return status;
1476 }
1477
1478 /**
1479  * i40e_aq_set_phy_config
1480  * @hw: pointer to the hw struct
1481  * @config: structure with PHY configuration to be set
1482  * @cmd_details: pointer to command details structure or NULL
1483  *
1484  * Set the various PHY configuration parameters
1485  * supported on the Port.One or more of the Set PHY config parameters may be
1486  * ignored in an MFP mode as the PF may not have the privilege to set some
1487  * of the PHY Config parameters. This status will be indicated by the
1488  * command response.
1489  **/
1490 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1491                                 struct i40e_aq_set_phy_config *config,
1492                                 struct i40e_asq_cmd_details *cmd_details)
1493 {
1494         struct i40e_aq_desc desc;
1495         struct i40e_aq_set_phy_config *cmd =
1496                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1497         enum i40e_status_code status;
1498
1499         if (!config)
1500                 return I40E_ERR_PARAM;
1501
1502         i40e_fill_default_direct_cmd_desc(&desc,
1503                                           i40e_aqc_opc_set_phy_config);
1504
1505         *cmd = *config;
1506
1507         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1508
1509         return status;
1510 }
1511
1512 /**
1513  * i40e_set_fc
1514  * @hw: pointer to the hw struct
1515  *
1516  * Set the requested flow control mode using set_phy_config.
1517  **/
1518 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1519                                   bool atomic_restart)
1520 {
1521         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1522         struct i40e_aq_get_phy_abilities_resp abilities;
1523         struct i40e_aq_set_phy_config config;
1524         enum i40e_status_code status;
1525         u8 pause_mask = 0x0;
1526
1527         *aq_failures = 0x0;
1528
1529         switch (fc_mode) {
1530         case I40E_FC_FULL:
1531                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1532                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1533                 break;
1534         case I40E_FC_RX_PAUSE:
1535                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1536                 break;
1537         case I40E_FC_TX_PAUSE:
1538                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1539                 break;
1540         default:
1541                 break;
1542         }
1543
1544         /* Get the current phy config */
1545         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1546                                               NULL);
1547         if (status) {
1548                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1549                 return status;
1550         }
1551
1552         memset(&config, 0, sizeof(config));
1553         /* clear the old pause settings */
1554         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1555                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1556         /* set the new abilities */
1557         config.abilities |= pause_mask;
1558         /* If the abilities have changed, then set the new config */
1559         if (config.abilities != abilities.abilities) {
1560                 /* Auto restart link so settings take effect */
1561                 if (atomic_restart)
1562                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1563                 /* Copy over all the old settings */
1564                 config.phy_type = abilities.phy_type;
1565                 config.link_speed = abilities.link_speed;
1566                 config.eee_capability = abilities.eee_capability;
1567                 config.eeer = abilities.eeer_val;
1568                 config.low_power_ctrl = abilities.d3_lpan;
1569                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1570
1571                 if (status)
1572                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1573         }
1574         /* Update the link info */
1575         status = i40e_update_link_info(hw);
1576         if (status) {
1577                 /* Wait a little bit (on 40G cards it sometimes takes a really
1578                  * long time for link to come back from the atomic reset)
1579                  * and try once more
1580                  */
1581                 i40e_msec_delay(1000);
1582                 status = i40e_update_link_info(hw);
1583         }
1584         if (status)
1585                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1586
1587         return status;
1588 }
1589
1590 /**
1591  * i40e_aq_set_mac_config
1592  * @hw: pointer to the hw struct
1593  * @max_frame_size: Maximum Frame Size to be supported by the port
1594  * @crc_en: Tell HW to append a CRC to outgoing frames
1595  * @pacing: Pacing configurations
1596  * @cmd_details: pointer to command details structure or NULL
1597  *
1598  * Configure MAC settings for frame size, jumbo frame support and the
1599  * addition of a CRC by the hardware.
1600  **/
1601 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1602                                 u16 max_frame_size,
1603                                 bool crc_en, u16 pacing,
1604                                 struct i40e_asq_cmd_details *cmd_details)
1605 {
1606         struct i40e_aq_desc desc;
1607         struct i40e_aq_set_mac_config *cmd =
1608                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1609         enum i40e_status_code status;
1610
1611         if (max_frame_size == 0)
1612                 return I40E_ERR_PARAM;
1613
1614         i40e_fill_default_direct_cmd_desc(&desc,
1615                                           i40e_aqc_opc_set_mac_config);
1616
1617         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1618         cmd->params = ((u8)pacing & 0x0F) << 3;
1619         if (crc_en)
1620                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1621
1622         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1623
1624         return status;
1625 }
1626
1627 /**
1628  * i40e_aq_clear_pxe_mode
1629  * @hw: pointer to the hw struct
1630  * @cmd_details: pointer to command details structure or NULL
1631  *
1632  * Tell the firmware that the driver is taking over from PXE
1633  **/
1634 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1635                         struct i40e_asq_cmd_details *cmd_details)
1636 {
1637         enum i40e_status_code status;
1638         struct i40e_aq_desc desc;
1639         struct i40e_aqc_clear_pxe *cmd =
1640                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1641
1642         i40e_fill_default_direct_cmd_desc(&desc,
1643                                           i40e_aqc_opc_clear_pxe_mode);
1644
1645         cmd->rx_cnt = 0x2;
1646
1647         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1648
1649         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1650
1651         return status;
1652 }
1653
1654 /**
1655  * i40e_aq_set_link_restart_an
1656  * @hw: pointer to the hw struct
1657  * @enable_link: if true: enable link, if false: disable link
1658  * @cmd_details: pointer to command details structure or NULL
1659  *
1660  * Sets up the link and restarts the Auto-Negotiation over the link.
1661  **/
1662 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1663                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1664 {
1665         struct i40e_aq_desc desc;
1666         struct i40e_aqc_set_link_restart_an *cmd =
1667                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1668         enum i40e_status_code status;
1669
1670         i40e_fill_default_direct_cmd_desc(&desc,
1671                                           i40e_aqc_opc_set_link_restart_an);
1672
1673         cmd->command = I40E_AQ_PHY_RESTART_AN;
1674         if (enable_link)
1675                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1676         else
1677                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1678
1679         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1680
1681         return status;
1682 }
1683
1684 /**
1685  * i40e_aq_get_link_info
1686  * @hw: pointer to the hw struct
1687  * @enable_lse: enable/disable LinkStatusEvent reporting
1688  * @link: pointer to link status structure - optional
1689  * @cmd_details: pointer to command details structure or NULL
1690  *
1691  * Returns the link status of the adapter.
1692  **/
1693 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1694                                 bool enable_lse, struct i40e_link_status *link,
1695                                 struct i40e_asq_cmd_details *cmd_details)
1696 {
1697         struct i40e_aq_desc desc;
1698         struct i40e_aqc_get_link_status *resp =
1699                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1700         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1701         enum i40e_status_code status;
1702         bool tx_pause, rx_pause;
1703         u16 command_flags;
1704
1705         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1706
1707         if (enable_lse)
1708                 command_flags = I40E_AQ_LSE_ENABLE;
1709         else
1710                 command_flags = I40E_AQ_LSE_DISABLE;
1711         resp->command_flags = CPU_TO_LE16(command_flags);
1712
1713         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1714
1715         if (status != I40E_SUCCESS)
1716                 goto aq_get_link_info_exit;
1717
1718         /* save off old link status information */
1719         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1720                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1721
1722         /* update link status */
1723         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1724         hw->phy.media_type = i40e_get_media_type(hw);
1725         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1726         hw_link_info->link_info = resp->link_info;
1727         hw_link_info->an_info = resp->an_info;
1728         hw_link_info->ext_info = resp->ext_info;
1729         hw_link_info->loopback = resp->loopback;
1730         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1731         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1732
1733         /* update fc info */
1734         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1735         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1736         if (tx_pause & rx_pause)
1737                 hw->fc.current_mode = I40E_FC_FULL;
1738         else if (tx_pause)
1739                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1740         else if (rx_pause)
1741                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1742         else
1743                 hw->fc.current_mode = I40E_FC_NONE;
1744
1745         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1746                 hw_link_info->crc_enable = true;
1747         else
1748                 hw_link_info->crc_enable = false;
1749
1750         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1751                 hw_link_info->lse_enable = true;
1752         else
1753                 hw_link_info->lse_enable = false;
1754
1755         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1756              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1757                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1758
1759         /* save link status information */
1760         if (link)
1761                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1762                             I40E_NONDMA_TO_NONDMA);
1763
1764         /* flag cleared so helper functions don't call AQ again */
1765         hw->phy.get_link_info = false;
1766
1767 aq_get_link_info_exit:
1768         return status;
1769 }
1770
1771 /**
1772  * i40e_aq_set_phy_int_mask
1773  * @hw: pointer to the hw struct
1774  * @mask: interrupt mask to be set
1775  * @cmd_details: pointer to command details structure or NULL
1776  *
1777  * Set link interrupt mask.
1778  **/
1779 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1780                                 u16 mask,
1781                                 struct i40e_asq_cmd_details *cmd_details)
1782 {
1783         struct i40e_aq_desc desc;
1784         struct i40e_aqc_set_phy_int_mask *cmd =
1785                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1786         enum i40e_status_code status;
1787
1788         i40e_fill_default_direct_cmd_desc(&desc,
1789                                           i40e_aqc_opc_set_phy_int_mask);
1790
1791         cmd->event_mask = CPU_TO_LE16(mask);
1792
1793         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1794
1795         return status;
1796 }
1797
1798 /**
1799  * i40e_aq_get_local_advt_reg
1800  * @hw: pointer to the hw struct
1801  * @advt_reg: local AN advertisement register value
1802  * @cmd_details: pointer to command details structure or NULL
1803  *
1804  * Get the Local AN advertisement register value.
1805  **/
1806 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1807                                 u64 *advt_reg,
1808                                 struct i40e_asq_cmd_details *cmd_details)
1809 {
1810         struct i40e_aq_desc desc;
1811         struct i40e_aqc_an_advt_reg *resp =
1812                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1813         enum i40e_status_code status;
1814
1815         i40e_fill_default_direct_cmd_desc(&desc,
1816                                           i40e_aqc_opc_get_local_advt_reg);
1817
1818         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1819
1820         if (status != I40E_SUCCESS)
1821                 goto aq_get_local_advt_reg_exit;
1822
1823         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1824         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1825
1826 aq_get_local_advt_reg_exit:
1827         return status;
1828 }
1829
1830 /**
1831  * i40e_aq_set_local_advt_reg
1832  * @hw: pointer to the hw struct
1833  * @advt_reg: local AN advertisement register value
1834  * @cmd_details: pointer to command details structure or NULL
1835  *
1836  * Get the Local AN advertisement register value.
1837  **/
1838 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1839                                 u64 advt_reg,
1840                                 struct i40e_asq_cmd_details *cmd_details)
1841 {
1842         struct i40e_aq_desc desc;
1843         struct i40e_aqc_an_advt_reg *cmd =
1844                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1845         enum i40e_status_code status;
1846
1847         i40e_fill_default_direct_cmd_desc(&desc,
1848                                           i40e_aqc_opc_get_local_advt_reg);
1849
1850         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1851         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1852
1853         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1854
1855         return status;
1856 }
1857
1858 /**
1859  * i40e_aq_get_partner_advt
1860  * @hw: pointer to the hw struct
1861  * @advt_reg: AN partner advertisement register value
1862  * @cmd_details: pointer to command details structure or NULL
1863  *
1864  * Get the link partner AN advertisement register value.
1865  **/
1866 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1867                                 u64 *advt_reg,
1868                                 struct i40e_asq_cmd_details *cmd_details)
1869 {
1870         struct i40e_aq_desc desc;
1871         struct i40e_aqc_an_advt_reg *resp =
1872                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1873         enum i40e_status_code status;
1874
1875         i40e_fill_default_direct_cmd_desc(&desc,
1876                                           i40e_aqc_opc_get_partner_advt);
1877
1878         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1879
1880         if (status != I40E_SUCCESS)
1881                 goto aq_get_partner_advt_exit;
1882
1883         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1884         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1885
1886 aq_get_partner_advt_exit:
1887         return status;
1888 }
1889
1890 /**
1891  * i40e_aq_set_lb_modes
1892  * @hw: pointer to the hw struct
1893  * @lb_modes: loopback mode to be set
1894  * @cmd_details: pointer to command details structure or NULL
1895  *
1896  * Sets loopback modes.
1897  **/
1898 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1899                                 u16 lb_modes,
1900                                 struct i40e_asq_cmd_details *cmd_details)
1901 {
1902         struct i40e_aq_desc desc;
1903         struct i40e_aqc_set_lb_mode *cmd =
1904                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1905         enum i40e_status_code status;
1906
1907         i40e_fill_default_direct_cmd_desc(&desc,
1908                                           i40e_aqc_opc_set_lb_modes);
1909
1910         cmd->lb_mode = CPU_TO_LE16(lb_modes);
1911
1912         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913
1914         return status;
1915 }
1916
1917 /**
1918  * i40e_aq_set_phy_debug
1919  * @hw: pointer to the hw struct
1920  * @cmd_flags: debug command flags
1921  * @cmd_details: pointer to command details structure or NULL
1922  *
1923  * Reset the external PHY.
1924  **/
1925 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1926                                 struct i40e_asq_cmd_details *cmd_details)
1927 {
1928         struct i40e_aq_desc desc;
1929         struct i40e_aqc_set_phy_debug *cmd =
1930                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1931         enum i40e_status_code status;
1932
1933         i40e_fill_default_direct_cmd_desc(&desc,
1934                                           i40e_aqc_opc_set_phy_debug);
1935
1936         cmd->command_flags = cmd_flags;
1937
1938         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1939
1940         return status;
1941 }
1942
1943 /**
1944  * i40e_aq_add_vsi
1945  * @hw: pointer to the hw struct
1946  * @vsi_ctx: pointer to a vsi context struct
1947  * @cmd_details: pointer to command details structure or NULL
1948  *
1949  * Add a VSI context to the hardware.
1950 **/
1951 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1952                                 struct i40e_vsi_context *vsi_ctx,
1953                                 struct i40e_asq_cmd_details *cmd_details)
1954 {
1955         struct i40e_aq_desc desc;
1956         struct i40e_aqc_add_get_update_vsi *cmd =
1957                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1958         struct i40e_aqc_add_get_update_vsi_completion *resp =
1959                 (struct i40e_aqc_add_get_update_vsi_completion *)
1960                 &desc.params.raw;
1961         enum i40e_status_code status;
1962
1963         i40e_fill_default_direct_cmd_desc(&desc,
1964                                           i40e_aqc_opc_add_vsi);
1965
1966         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1967         cmd->connection_type = vsi_ctx->connection_type;
1968         cmd->vf_id = vsi_ctx->vf_num;
1969         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1970
1971         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1972
1973         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1974                                     sizeof(vsi_ctx->info), cmd_details);
1975
1976         if (status != I40E_SUCCESS)
1977                 goto aq_add_vsi_exit;
1978
1979         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1980         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1981         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1982         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1983
1984 aq_add_vsi_exit:
1985         return status;
1986 }
1987
1988 /**
1989  * i40e_aq_set_default_vsi
1990  * @hw: pointer to the hw struct
1991  * @seid: vsi number
1992  * @cmd_details: pointer to command details structure or NULL
1993  **/
1994 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1995                                 u16 seid,
1996                                 struct i40e_asq_cmd_details *cmd_details)
1997 {
1998         struct i40e_aq_desc desc;
1999         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2000                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2001                 &desc.params.raw;
2002         enum i40e_status_code status;
2003
2004         i40e_fill_default_direct_cmd_desc(&desc,
2005                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2006
2007         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2008         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2009         cmd->seid = CPU_TO_LE16(seid);
2010
2011         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2012
2013         return status;
2014 }
2015
2016 /**
2017  * i40e_aq_set_vsi_unicast_promiscuous
2018  * @hw: pointer to the hw struct
2019  * @seid: vsi number
2020  * @set: set unicast promiscuous enable/disable
2021  * @cmd_details: pointer to command details structure or NULL
2022  **/
2023 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2024                                 u16 seid, bool set,
2025                                 struct i40e_asq_cmd_details *cmd_details)
2026 {
2027         struct i40e_aq_desc desc;
2028         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2029                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2030         enum i40e_status_code status;
2031         u16 flags = 0;
2032
2033         i40e_fill_default_direct_cmd_desc(&desc,
2034                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2035
2036         if (set)
2037                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2038
2039         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2040
2041         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2042
2043         cmd->seid = CPU_TO_LE16(seid);
2044         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2045
2046         return status;
2047 }
2048
2049 /**
2050  * i40e_aq_set_vsi_multicast_promiscuous
2051  * @hw: pointer to the hw struct
2052  * @seid: vsi number
2053  * @set: set multicast promiscuous enable/disable
2054  * @cmd_details: pointer to command details structure or NULL
2055  **/
2056 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2057                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2058 {
2059         struct i40e_aq_desc desc;
2060         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2061                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2062         enum i40e_status_code status;
2063         u16 flags = 0;
2064
2065         i40e_fill_default_direct_cmd_desc(&desc,
2066                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2067
2068         if (set)
2069                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2070
2071         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2072
2073         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2074
2075         cmd->seid = CPU_TO_LE16(seid);
2076         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2077
2078         return status;
2079 }
2080
2081 /**
2082  * i40e_aq_set_vsi_mc_promisc_on_vlan
2083  * @hw: pointer to the hw struct
2084  * @seid: vsi number
2085  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2086  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2087  * @cmd_details: pointer to command details structure or NULL
2088  **/
2089 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2090                                 u16 seid, bool enable, u16 vid,
2091                                 struct i40e_asq_cmd_details *cmd_details)
2092 {
2093         struct i40e_aq_desc desc;
2094         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2095                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2096         enum i40e_status_code status;
2097         u16 flags = 0;
2098
2099         i40e_fill_default_direct_cmd_desc(&desc,
2100                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2101
2102         if (enable)
2103                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2104
2105         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2106         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2107         cmd->seid = CPU_TO_LE16(seid);
2108         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2109
2110         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2111
2112         return status;
2113 }
2114
2115 /**
2116  * i40e_aq_set_vsi_uc_promisc_on_vlan
2117  * @hw: pointer to the hw struct
2118  * @seid: vsi number
2119  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2120  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2121  * @cmd_details: pointer to command details structure or NULL
2122  **/
2123 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2124                                 u16 seid, bool enable, u16 vid,
2125                                 struct i40e_asq_cmd_details *cmd_details)
2126 {
2127         struct i40e_aq_desc desc;
2128         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2129                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2130         enum i40e_status_code status;
2131         u16 flags = 0;
2132
2133         i40e_fill_default_direct_cmd_desc(&desc,
2134                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2135
2136         if (enable)
2137                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2138
2139         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2140         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2141         cmd->seid = CPU_TO_LE16(seid);
2142         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2143
2144         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2145
2146         return status;
2147 }
2148
2149 /**
2150  * i40e_aq_set_vsi_broadcast
2151  * @hw: pointer to the hw struct
2152  * @seid: vsi number
2153  * @set_filter: true to set filter, false to clear filter
2154  * @cmd_details: pointer to command details structure or NULL
2155  *
2156  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2157  **/
2158 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2159                                 u16 seid, bool set_filter,
2160                                 struct i40e_asq_cmd_details *cmd_details)
2161 {
2162         struct i40e_aq_desc desc;
2163         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2164                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2165         enum i40e_status_code status;
2166
2167         i40e_fill_default_direct_cmd_desc(&desc,
2168                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2169
2170         if (set_filter)
2171                 cmd->promiscuous_flags
2172                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2173         else
2174                 cmd->promiscuous_flags
2175                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2176
2177         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2178         cmd->seid = CPU_TO_LE16(seid);
2179         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2180
2181         return status;
2182 }
2183
2184 /**
2185  * i40e_get_vsi_params - get VSI configuration info
2186  * @hw: pointer to the hw struct
2187  * @vsi_ctx: pointer to a vsi context struct
2188  * @cmd_details: pointer to command details structure or NULL
2189  **/
2190 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2191                                 struct i40e_vsi_context *vsi_ctx,
2192                                 struct i40e_asq_cmd_details *cmd_details)
2193 {
2194         struct i40e_aq_desc desc;
2195         struct i40e_aqc_add_get_update_vsi *cmd =
2196                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2197         struct i40e_aqc_add_get_update_vsi_completion *resp =
2198                 (struct i40e_aqc_add_get_update_vsi_completion *)
2199                 &desc.params.raw;
2200         enum i40e_status_code status;
2201
2202         UNREFERENCED_1PARAMETER(cmd_details);
2203         i40e_fill_default_direct_cmd_desc(&desc,
2204                                           i40e_aqc_opc_get_vsi_parameters);
2205
2206         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2207
2208         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2209
2210         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2211                                     sizeof(vsi_ctx->info), NULL);
2212
2213         if (status != I40E_SUCCESS)
2214                 goto aq_get_vsi_params_exit;
2215
2216         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2217         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2218         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2219         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2220
2221 aq_get_vsi_params_exit:
2222         return status;
2223 }
2224
2225 /**
2226  * i40e_aq_update_vsi_params
2227  * @hw: pointer to the hw struct
2228  * @vsi_ctx: pointer to a vsi context struct
2229  * @cmd_details: pointer to command details structure or NULL
2230  *
2231  * Update a VSI context.
2232  **/
2233 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2234                                 struct i40e_vsi_context *vsi_ctx,
2235                                 struct i40e_asq_cmd_details *cmd_details)
2236 {
2237         struct i40e_aq_desc desc;
2238         struct i40e_aqc_add_get_update_vsi *cmd =
2239                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2240         enum i40e_status_code status;
2241
2242         i40e_fill_default_direct_cmd_desc(&desc,
2243                                           i40e_aqc_opc_update_vsi_parameters);
2244         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2245
2246         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2247
2248         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2249                                     sizeof(vsi_ctx->info), cmd_details);
2250
2251         return status;
2252 }
2253
2254 /**
2255  * i40e_aq_get_switch_config
2256  * @hw: pointer to the hardware structure
2257  * @buf: pointer to the result buffer
2258  * @buf_size: length of input buffer
2259  * @start_seid: seid to start for the report, 0 == beginning
2260  * @cmd_details: pointer to command details structure or NULL
2261  *
2262  * Fill the buf with switch configuration returned from AdminQ command
2263  **/
2264 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2265                                 struct i40e_aqc_get_switch_config_resp *buf,
2266                                 u16 buf_size, u16 *start_seid,
2267                                 struct i40e_asq_cmd_details *cmd_details)
2268 {
2269         struct i40e_aq_desc desc;
2270         struct i40e_aqc_switch_seid *scfg =
2271                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2272         enum i40e_status_code status;
2273
2274         i40e_fill_default_direct_cmd_desc(&desc,
2275                                           i40e_aqc_opc_get_switch_config);
2276         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2277         if (buf_size > I40E_AQ_LARGE_BUF)
2278                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2279         scfg->seid = CPU_TO_LE16(*start_seid);
2280
2281         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2282         *start_seid = LE16_TO_CPU(scfg->seid);
2283
2284         return status;
2285 }
2286
2287 /**
2288  * i40e_aq_get_firmware_version
2289  * @hw: pointer to the hw struct
2290  * @fw_major_version: firmware major version
2291  * @fw_minor_version: firmware minor version
2292  * @fw_build: firmware build number
2293  * @api_major_version: major queue version
2294  * @api_minor_version: minor queue version
2295  * @cmd_details: pointer to command details structure or NULL
2296  *
2297  * Get the firmware version from the admin queue commands
2298  **/
2299 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2300                                 u16 *fw_major_version, u16 *fw_minor_version,
2301                                 u32 *fw_build,
2302                                 u16 *api_major_version, u16 *api_minor_version,
2303                                 struct i40e_asq_cmd_details *cmd_details)
2304 {
2305         struct i40e_aq_desc desc;
2306         struct i40e_aqc_get_version *resp =
2307                 (struct i40e_aqc_get_version *)&desc.params.raw;
2308         enum i40e_status_code status;
2309
2310         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2311
2312         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2313
2314         if (status == I40E_SUCCESS) {
2315                 if (fw_major_version != NULL)
2316                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2317                 if (fw_minor_version != NULL)
2318                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2319                 if (fw_build != NULL)
2320                         *fw_build = LE32_TO_CPU(resp->fw_build);
2321                 if (api_major_version != NULL)
2322                         *api_major_version = LE16_TO_CPU(resp->api_major);
2323                 if (api_minor_version != NULL)
2324                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2325
2326                 /* A workaround to fix the API version in SW */
2327                 if (api_major_version && api_minor_version &&
2328                     fw_major_version && fw_minor_version &&
2329                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2330                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2331                      (*fw_major_version > 4)))
2332                         *api_minor_version = 2;
2333         }
2334
2335         return status;
2336 }
2337
2338 /**
2339  * i40e_aq_send_driver_version
2340  * @hw: pointer to the hw struct
2341  * @dv: driver's major, minor version
2342  * @cmd_details: pointer to command details structure or NULL
2343  *
2344  * Send the driver version to the firmware
2345  **/
2346 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2347                                 struct i40e_driver_version *dv,
2348                                 struct i40e_asq_cmd_details *cmd_details)
2349 {
2350         struct i40e_aq_desc desc;
2351         struct i40e_aqc_driver_version *cmd =
2352                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2353         enum i40e_status_code status;
2354         u16 len;
2355
2356         if (dv == NULL)
2357                 return I40E_ERR_PARAM;
2358
2359         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2360
2361         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2362         cmd->driver_major_ver = dv->major_version;
2363         cmd->driver_minor_ver = dv->minor_version;
2364         cmd->driver_build_ver = dv->build_version;
2365         cmd->driver_subbuild_ver = dv->subbuild_version;
2366
2367         len = 0;
2368         while (len < sizeof(dv->driver_string) &&
2369                (dv->driver_string[len] < 0x80) &&
2370                dv->driver_string[len])
2371                 len++;
2372         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2373                                        len, cmd_details);
2374
2375         return status;
2376 }
2377
2378 /**
2379  * i40e_get_link_status - get status of the HW network link
2380  * @hw: pointer to the hw struct
2381  * @link_up: pointer to bool (true/false = linkup/linkdown)
2382  *
2383  * Variable link_up true if link is up, false if link is down.
2384  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2385  *
2386  * Side effect: LinkStatusEvent reporting becomes enabled
2387  **/
2388 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2389 {
2390         enum i40e_status_code status = I40E_SUCCESS;
2391
2392         if (hw->phy.get_link_info) {
2393                 status = i40e_update_link_info(hw);
2394
2395                 if (status != I40E_SUCCESS)
2396                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2397                                    status);
2398         }
2399
2400         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2401
2402         return status;
2403 }
2404
2405 /**
2406  * i40e_updatelink_status - update status of the HW network link
2407  * @hw: pointer to the hw struct
2408  **/
2409 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2410 {
2411         struct i40e_aq_get_phy_abilities_resp abilities;
2412         enum i40e_status_code status = I40E_SUCCESS;
2413
2414         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2415         if (status)
2416                 return status;
2417
2418         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2419                                               NULL);
2420         if (status)
2421                 return status;
2422
2423         memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2424                 sizeof(hw->phy.link_info.module_type));
2425
2426         return status;
2427 }
2428
2429 /**
2430  * i40e_get_link_speed
2431  * @hw: pointer to the hw struct
2432  *
2433  * Returns the link speed of the adapter.
2434  **/
2435 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2436 {
2437         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2438         enum i40e_status_code status = I40E_SUCCESS;
2439
2440         if (hw->phy.get_link_info) {
2441                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2442
2443                 if (status != I40E_SUCCESS)
2444                         goto i40e_link_speed_exit;
2445         }
2446
2447         speed = hw->phy.link_info.link_speed;
2448
2449 i40e_link_speed_exit:
2450         return speed;
2451 }
2452
2453 /**
2454  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2455  * @hw: pointer to the hw struct
2456  * @uplink_seid: the MAC or other gizmo SEID
2457  * @downlink_seid: the VSI SEID
2458  * @enabled_tc: bitmap of TCs to be enabled
2459  * @default_port: true for default port VSI, false for control port
2460  * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2461  * @veb_seid: pointer to where to put the resulting VEB SEID
2462  * @cmd_details: pointer to command details structure or NULL
2463  *
2464  * This asks the FW to add a VEB between the uplink and downlink
2465  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2466  **/
2467 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2468                                 u16 downlink_seid, u8 enabled_tc,
2469                                 bool default_port, bool enable_l2_filtering,
2470                                 u16 *veb_seid,
2471                                 struct i40e_asq_cmd_details *cmd_details)
2472 {
2473         struct i40e_aq_desc desc;
2474         struct i40e_aqc_add_veb *cmd =
2475                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2476         struct i40e_aqc_add_veb_completion *resp =
2477                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2478         enum i40e_status_code status;
2479         u16 veb_flags = 0;
2480
2481         /* SEIDs need to either both be set or both be 0 for floating VEB */
2482         if (!!uplink_seid != !!downlink_seid)
2483                 return I40E_ERR_PARAM;
2484
2485         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2486
2487         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2488         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2489         cmd->enable_tcs = enabled_tc;
2490         if (!uplink_seid)
2491                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2492         if (default_port)
2493                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2494         else
2495                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2496
2497         if (enable_l2_filtering)
2498                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2499
2500         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2501
2502         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2503
2504         if (!status && veb_seid)
2505                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2506
2507         return status;
2508 }
2509
2510 /**
2511  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2512  * @hw: pointer to the hw struct
2513  * @veb_seid: the SEID of the VEB to query
2514  * @switch_id: the uplink switch id
2515  * @floating: set to true if the VEB is floating
2516  * @statistic_index: index of the stats counter block for this VEB
2517  * @vebs_used: number of VEB's used by function
2518  * @vebs_free: total VEB's not reserved by any function
2519  * @cmd_details: pointer to command details structure or NULL
2520  *
2521  * This retrieves the parameters for a particular VEB, specified by
2522  * uplink_seid, and returns them to the caller.
2523  **/
2524 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2525                                 u16 veb_seid, u16 *switch_id,
2526                                 bool *floating, u16 *statistic_index,
2527                                 u16 *vebs_used, u16 *vebs_free,
2528                                 struct i40e_asq_cmd_details *cmd_details)
2529 {
2530         struct i40e_aq_desc desc;
2531         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2532                 (struct i40e_aqc_get_veb_parameters_completion *)
2533                 &desc.params.raw;
2534         enum i40e_status_code status;
2535
2536         if (veb_seid == 0)
2537                 return I40E_ERR_PARAM;
2538
2539         i40e_fill_default_direct_cmd_desc(&desc,
2540                                           i40e_aqc_opc_get_veb_parameters);
2541         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2542
2543         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2544         if (status)
2545                 goto get_veb_exit;
2546
2547         if (switch_id)
2548                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2549         if (statistic_index)
2550                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2551         if (vebs_used)
2552                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2553         if (vebs_free)
2554                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2555         if (floating) {
2556                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2557                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2558                         *floating = true;
2559                 else
2560                         *floating = false;
2561         }
2562
2563 get_veb_exit:
2564         return status;
2565 }
2566
2567 /**
2568  * i40e_aq_add_macvlan
2569  * @hw: pointer to the hw struct
2570  * @seid: VSI for the mac address
2571  * @mv_list: list of macvlans to be added
2572  * @count: length of the list
2573  * @cmd_details: pointer to command details structure or NULL
2574  *
2575  * Add MAC/VLAN addresses to the HW filtering
2576  **/
2577 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2578                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2579                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2580 {
2581         struct i40e_aq_desc desc;
2582         struct i40e_aqc_macvlan *cmd =
2583                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2584         enum i40e_status_code status;
2585         u16 buf_size;
2586
2587         if (count == 0 || !mv_list || !hw)
2588                 return I40E_ERR_PARAM;
2589
2590         buf_size = count * sizeof(*mv_list);
2591
2592         /* prep the rest of the request */
2593         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2594         cmd->num_addresses = CPU_TO_LE16(count);
2595         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2596         cmd->seid[1] = 0;
2597         cmd->seid[2] = 0;
2598
2599         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2600         if (buf_size > I40E_AQ_LARGE_BUF)
2601                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2602
2603         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2604                                     cmd_details);
2605
2606         return status;
2607 }
2608
2609 /**
2610  * i40e_aq_remove_macvlan
2611  * @hw: pointer to the hw struct
2612  * @seid: VSI for the mac address
2613  * @mv_list: list of macvlans to be removed
2614  * @count: length of the list
2615  * @cmd_details: pointer to command details structure or NULL
2616  *
2617  * Remove MAC/VLAN addresses from the HW filtering
2618  **/
2619 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2620                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2621                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2622 {
2623         struct i40e_aq_desc desc;
2624         struct i40e_aqc_macvlan *cmd =
2625                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2626         enum i40e_status_code status;
2627         u16 buf_size;
2628
2629         if (count == 0 || !mv_list || !hw)
2630                 return I40E_ERR_PARAM;
2631
2632         buf_size = count * sizeof(*mv_list);
2633
2634         /* prep the rest of the request */
2635         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2636         cmd->num_addresses = CPU_TO_LE16(count);
2637         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2638         cmd->seid[1] = 0;
2639         cmd->seid[2] = 0;
2640
2641         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2642         if (buf_size > I40E_AQ_LARGE_BUF)
2643                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2644
2645         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2646                                        cmd_details);
2647
2648         return status;
2649 }
2650
2651 /**
2652  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2653  * @hw: pointer to the hw struct
2654  * @seid: VSI for the vlan filters
2655  * @v_list: list of vlan filters to be added
2656  * @count: length of the list
2657  * @cmd_details: pointer to command details structure or NULL
2658  **/
2659 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2660                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2661                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2662 {
2663         struct i40e_aq_desc desc;
2664         struct i40e_aqc_macvlan *cmd =
2665                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2666         enum i40e_status_code status;
2667         u16 buf_size;
2668
2669         if (count == 0 || !v_list || !hw)
2670                 return I40E_ERR_PARAM;
2671
2672         buf_size = count * sizeof(*v_list);
2673
2674         /* prep the rest of the request */
2675         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2676         cmd->num_addresses = CPU_TO_LE16(count);
2677         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2678         cmd->seid[1] = 0;
2679         cmd->seid[2] = 0;
2680
2681         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2682         if (buf_size > I40E_AQ_LARGE_BUF)
2683                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2684
2685         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2686                                        cmd_details);
2687
2688         return status;
2689 }
2690
2691 /**
2692  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2693  * @hw: pointer to the hw struct
2694  * @seid: VSI for the vlan filters
2695  * @v_list: list of macvlans to be removed
2696  * @count: length of the list
2697  * @cmd_details: pointer to command details structure or NULL
2698  **/
2699 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2700                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2701                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2702 {
2703         struct i40e_aq_desc desc;
2704         struct i40e_aqc_macvlan *cmd =
2705                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2706         enum i40e_status_code status;
2707         u16 buf_size;
2708
2709         if (count == 0 || !v_list || !hw)
2710                 return I40E_ERR_PARAM;
2711
2712         buf_size = count * sizeof(*v_list);
2713
2714         /* prep the rest of the request */
2715         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2716         cmd->num_addresses = CPU_TO_LE16(count);
2717         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2718         cmd->seid[1] = 0;
2719         cmd->seid[2] = 0;
2720
2721         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2722         if (buf_size > I40E_AQ_LARGE_BUF)
2723                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2724
2725         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2726                                        cmd_details);
2727
2728         return status;
2729 }
2730
2731 /**
2732  * i40e_aq_send_msg_to_vf
2733  * @hw: pointer to the hardware structure
2734  * @vfid: vf id to send msg
2735  * @v_opcode: opcodes for VF-PF communication
2736  * @v_retval: return error code
2737  * @msg: pointer to the msg buffer
2738  * @msglen: msg length
2739  * @cmd_details: pointer to command details
2740  *
2741  * send msg to vf
2742  **/
2743 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2744                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2745                                 struct i40e_asq_cmd_details *cmd_details)
2746 {
2747         struct i40e_aq_desc desc;
2748         struct i40e_aqc_pf_vf_message *cmd =
2749                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2750         enum i40e_status_code status;
2751
2752         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2753         cmd->id = CPU_TO_LE32(vfid);
2754         desc.cookie_high = CPU_TO_LE32(v_opcode);
2755         desc.cookie_low = CPU_TO_LE32(v_retval);
2756         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2757         if (msglen) {
2758                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2759                                                 I40E_AQ_FLAG_RD));
2760                 if (msglen > I40E_AQ_LARGE_BUF)
2761                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2762                 desc.datalen = CPU_TO_LE16(msglen);
2763         }
2764         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2765
2766         return status;
2767 }
2768
2769 /**
2770  * i40e_aq_debug_read_register
2771  * @hw: pointer to the hw struct
2772  * @reg_addr: register address
2773  * @reg_val: register value
2774  * @cmd_details: pointer to command details structure or NULL
2775  *
2776  * Read the register using the admin queue commands
2777  **/
2778 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2779                                 u32 reg_addr, u64 *reg_val,
2780                                 struct i40e_asq_cmd_details *cmd_details)
2781 {
2782         struct i40e_aq_desc desc;
2783         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2784                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2785         enum i40e_status_code status;
2786
2787         if (reg_val == NULL)
2788                 return I40E_ERR_PARAM;
2789
2790         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2791
2792         cmd_resp->address = CPU_TO_LE32(reg_addr);
2793
2794         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2795
2796         if (status == I40E_SUCCESS) {
2797                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2798                            (u64)LE32_TO_CPU(cmd_resp->value_low);
2799         }
2800
2801         return status;
2802 }
2803
2804 /**
2805  * i40e_aq_debug_write_register
2806  * @hw: pointer to the hw struct
2807  * @reg_addr: register address
2808  * @reg_val: register value
2809  * @cmd_details: pointer to command details structure or NULL
2810  *
2811  * Write to a register using the admin queue commands
2812  **/
2813 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2814                                 u32 reg_addr, u64 reg_val,
2815                                 struct i40e_asq_cmd_details *cmd_details)
2816 {
2817         struct i40e_aq_desc desc;
2818         struct i40e_aqc_debug_reg_read_write *cmd =
2819                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2820         enum i40e_status_code status;
2821
2822         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2823
2824         cmd->address = CPU_TO_LE32(reg_addr);
2825         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2826         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2827
2828         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2829
2830         return status;
2831 }
2832
2833 /**
2834  * i40e_aq_get_hmc_resource_profile
2835  * @hw: pointer to the hw struct
2836  * @profile: type of profile the HMC is to be set as
2837  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2838  * @cmd_details: pointer to command details structure or NULL
2839  *
2840  * query the HMC profile of the device.
2841  **/
2842 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2843                                 enum i40e_aq_hmc_profile *profile,
2844                                 u8 *pe_vf_enabled_count,
2845                                 struct i40e_asq_cmd_details *cmd_details)
2846 {
2847         struct i40e_aq_desc desc;
2848         struct i40e_aq_get_set_hmc_resource_profile *resp =
2849                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2850         enum i40e_status_code status;
2851
2852         i40e_fill_default_direct_cmd_desc(&desc,
2853                                 i40e_aqc_opc_query_hmc_resource_profile);
2854         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2855
2856         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2857                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2858         *pe_vf_enabled_count = resp->pe_vf_enabled &
2859                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2860
2861         return status;
2862 }
2863
2864 /**
2865  * i40e_aq_set_hmc_resource_profile
2866  * @hw: pointer to the hw struct
2867  * @profile: type of profile the HMC is to be set as
2868  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2869  * @cmd_details: pointer to command details structure or NULL
2870  *
2871  * set the HMC profile of the device.
2872  **/
2873 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2874                                 enum i40e_aq_hmc_profile profile,
2875                                 u8 pe_vf_enabled_count,
2876                                 struct i40e_asq_cmd_details *cmd_details)
2877 {
2878         struct i40e_aq_desc desc;
2879         struct i40e_aq_get_set_hmc_resource_profile *cmd =
2880                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2881         enum i40e_status_code status;
2882
2883         i40e_fill_default_direct_cmd_desc(&desc,
2884                                         i40e_aqc_opc_set_hmc_resource_profile);
2885
2886         cmd->pm_profile = (u8)profile;
2887         cmd->pe_vf_enabled = pe_vf_enabled_count;
2888
2889         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2890
2891         return status;
2892 }
2893
2894 /**
2895  * i40e_aq_request_resource
2896  * @hw: pointer to the hw struct
2897  * @resource: resource id
2898  * @access: access type
2899  * @sdp_number: resource number
2900  * @timeout: the maximum time in ms that the driver may hold the resource
2901  * @cmd_details: pointer to command details structure or NULL
2902  *
2903  * requests common resource using the admin queue commands
2904  **/
2905 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2906                                 enum i40e_aq_resources_ids resource,
2907                                 enum i40e_aq_resource_access_type access,
2908                                 u8 sdp_number, u64 *timeout,
2909                                 struct i40e_asq_cmd_details *cmd_details)
2910 {
2911         struct i40e_aq_desc desc;
2912         struct i40e_aqc_request_resource *cmd_resp =
2913                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2914         enum i40e_status_code status;
2915
2916         DEBUGFUNC("i40e_aq_request_resource");
2917
2918         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2919
2920         cmd_resp->resource_id = CPU_TO_LE16(resource);
2921         cmd_resp->access_type = CPU_TO_LE16(access);
2922         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2923
2924         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2925         /* The completion specifies the maximum time in ms that the driver
2926          * may hold the resource in the Timeout field.
2927          * If the resource is held by someone else, the command completes with
2928          * busy return value and the timeout field indicates the maximum time
2929          * the current owner of the resource has to free it.
2930          */
2931         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2932                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2933
2934         return status;
2935 }
2936
2937 /**
2938  * i40e_aq_release_resource
2939  * @hw: pointer to the hw struct
2940  * @resource: resource id
2941  * @sdp_number: resource number
2942  * @cmd_details: pointer to command details structure or NULL
2943  *
2944  * release common resource using the admin queue commands
2945  **/
2946 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2947                                 enum i40e_aq_resources_ids resource,
2948                                 u8 sdp_number,
2949                                 struct i40e_asq_cmd_details *cmd_details)
2950 {
2951         struct i40e_aq_desc desc;
2952         struct i40e_aqc_request_resource *cmd =
2953                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2954         enum i40e_status_code status;
2955
2956         DEBUGFUNC("i40e_aq_release_resource");
2957
2958         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2959
2960         cmd->resource_id = CPU_TO_LE16(resource);
2961         cmd->resource_number = CPU_TO_LE32(sdp_number);
2962
2963         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2964
2965         return status;
2966 }
2967
2968 /**
2969  * i40e_aq_read_nvm
2970  * @hw: pointer to the hw struct
2971  * @module_pointer: module pointer location in words from the NVM beginning
2972  * @offset: byte offset from the module beginning
2973  * @length: length of the section to be read (in bytes from the offset)
2974  * @data: command buffer (size [bytes] = length)
2975  * @last_command: tells if this is the last command in a series
2976  * @cmd_details: pointer to command details structure or NULL
2977  *
2978  * Read the NVM using the admin queue commands
2979  **/
2980 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2981                                 u32 offset, u16 length, void *data,
2982                                 bool last_command,
2983                                 struct i40e_asq_cmd_details *cmd_details)
2984 {
2985         struct i40e_aq_desc desc;
2986         struct i40e_aqc_nvm_update *cmd =
2987                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2988         enum i40e_status_code status;
2989
2990         DEBUGFUNC("i40e_aq_read_nvm");
2991
2992         /* In offset the highest byte must be zeroed. */
2993         if (offset & 0xFF000000) {
2994                 status = I40E_ERR_PARAM;
2995                 goto i40e_aq_read_nvm_exit;
2996         }
2997
2998         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2999
3000         /* If this is the last command in a series, set the proper flag. */
3001         if (last_command)
3002                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3003         cmd->module_pointer = module_pointer;
3004         cmd->offset = CPU_TO_LE32(offset);
3005         cmd->length = CPU_TO_LE16(length);
3006
3007         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3008         if (length > I40E_AQ_LARGE_BUF)
3009                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3010
3011         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3012
3013 i40e_aq_read_nvm_exit:
3014         return status;
3015 }
3016
3017 /**
3018  * i40e_aq_read_nvm_config - read an nvm config block
3019  * @hw: pointer to the hw struct
3020  * @cmd_flags: NVM access admin command bits
3021  * @field_id: field or feature id
3022  * @data: buffer for result
3023  * @buf_size: buffer size
3024  * @element_count: pointer to count of elements read by FW
3025  * @cmd_details: pointer to command details structure or NULL
3026  **/
3027 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3028                                 u8 cmd_flags, u32 field_id, void *data,
3029                                 u16 buf_size, u16 *element_count,
3030                                 struct i40e_asq_cmd_details *cmd_details)
3031 {
3032         struct i40e_aq_desc desc;
3033         struct i40e_aqc_nvm_config_read *cmd =
3034                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3035         enum i40e_status_code status;
3036
3037         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3038         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3039         if (buf_size > I40E_AQ_LARGE_BUF)
3040                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3041
3042         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3043         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3044         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3045                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3046         else
3047                 cmd->element_id_msw = 0;
3048
3049         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3050
3051         if (!status && element_count)
3052                 *element_count = LE16_TO_CPU(cmd->element_count);
3053
3054         return status;
3055 }
3056
3057 /**
3058  * i40e_aq_write_nvm_config - write an nvm config block
3059  * @hw: pointer to the hw struct
3060  * @cmd_flags: NVM access admin command bits
3061  * @data: buffer for result
3062  * @buf_size: buffer size
3063  * @element_count: count of elements to be written
3064  * @cmd_details: pointer to command details structure or NULL
3065  **/
3066 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3067                                 u8 cmd_flags, void *data, u16 buf_size,
3068                                 u16 element_count,
3069                                 struct i40e_asq_cmd_details *cmd_details)
3070 {
3071         struct i40e_aq_desc desc;
3072         struct i40e_aqc_nvm_config_write *cmd =
3073                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3074         enum i40e_status_code status;
3075
3076         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3077         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3078         if (buf_size > I40E_AQ_LARGE_BUF)
3079                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3080
3081         cmd->element_count = CPU_TO_LE16(element_count);
3082         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3083         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3084
3085         return status;
3086 }
3087
3088 /**
3089  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3090  * @hw: pointer to the hw struct
3091  * @cmd_details: pointer to command details structure or NULL
3092  **/
3093 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3094                                 void *buff, u16 buff_size,
3095                                 struct i40e_asq_cmd_details *cmd_details)
3096 {
3097         struct i40e_aq_desc desc;
3098         enum i40e_status_code status;
3099
3100         UNREFERENCED_2PARAMETER(buff, buff_size);
3101
3102         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3103         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3104         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3105                 status = I40E_ERR_NOT_IMPLEMENTED;
3106
3107         return status;
3108 }
3109
3110 /**
3111  * i40e_aq_erase_nvm
3112  * @hw: pointer to the hw struct
3113  * @module_pointer: module pointer location in words from the NVM beginning
3114  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3115  * @length: length of the section to be erased (expressed in 4 KB)
3116  * @last_command: tells if this is the last command in a series
3117  * @cmd_details: pointer to command details structure or NULL
3118  *
3119  * Erase the NVM sector using the admin queue commands
3120  **/
3121 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3122                                 u32 offset, u16 length, bool last_command,
3123                                 struct i40e_asq_cmd_details *cmd_details)
3124 {
3125         struct i40e_aq_desc desc;
3126         struct i40e_aqc_nvm_update *cmd =
3127                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3128         enum i40e_status_code status;
3129
3130         DEBUGFUNC("i40e_aq_erase_nvm");
3131
3132         /* In offset the highest byte must be zeroed. */
3133         if (offset & 0xFF000000) {
3134                 status = I40E_ERR_PARAM;
3135                 goto i40e_aq_erase_nvm_exit;
3136         }
3137
3138         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3139
3140         /* If this is the last command in a series, set the proper flag. */
3141         if (last_command)
3142                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3143         cmd->module_pointer = module_pointer;
3144         cmd->offset = CPU_TO_LE32(offset);
3145         cmd->length = CPU_TO_LE16(length);
3146
3147         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3148
3149 i40e_aq_erase_nvm_exit:
3150         return status;
3151 }
3152
3153 #define I40E_DEV_FUNC_CAP_SWITCH_MODE   0x01
3154 #define I40E_DEV_FUNC_CAP_MGMT_MODE     0x02
3155 #define I40E_DEV_FUNC_CAP_NPAR          0x03
3156 #define I40E_DEV_FUNC_CAP_OS2BMC        0x04
3157 #define I40E_DEV_FUNC_CAP_VALID_FUNC    0x05
3158 #define I40E_DEV_FUNC_CAP_SRIOV_1_1     0x12
3159 #define I40E_DEV_FUNC_CAP_VF            0x13
3160 #define I40E_DEV_FUNC_CAP_VMDQ          0x14
3161 #define I40E_DEV_FUNC_CAP_802_1_QBG     0x15
3162 #define I40E_DEV_FUNC_CAP_802_1_QBH     0x16
3163 #define I40E_DEV_FUNC_CAP_VSI           0x17
3164 #define I40E_DEV_FUNC_CAP_DCB           0x18
3165 #define I40E_DEV_FUNC_CAP_FCOE          0x21
3166 #define I40E_DEV_FUNC_CAP_ISCSI         0x22
3167 #define I40E_DEV_FUNC_CAP_RSS           0x40
3168 #define I40E_DEV_FUNC_CAP_RX_QUEUES     0x41
3169 #define I40E_DEV_FUNC_CAP_TX_QUEUES     0x42
3170 #define I40E_DEV_FUNC_CAP_MSIX          0x43
3171 #define I40E_DEV_FUNC_CAP_MSIX_VF       0x44
3172 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3173 #define I40E_DEV_FUNC_CAP_IEEE_1588     0x46
3174 #define I40E_DEV_FUNC_CAP_FLEX10        0xF1
3175 #define I40E_DEV_FUNC_CAP_CEM           0xF2
3176 #define I40E_DEV_FUNC_CAP_IWARP         0x51
3177 #define I40E_DEV_FUNC_CAP_LED           0x61
3178 #define I40E_DEV_FUNC_CAP_SDP           0x62
3179 #define I40E_DEV_FUNC_CAP_MDIO          0x63
3180
3181 /**
3182  * i40e_parse_discover_capabilities
3183  * @hw: pointer to the hw struct
3184  * @buff: pointer to a buffer containing device/function capability records
3185  * @cap_count: number of capability records in the list
3186  * @list_type_opc: type of capabilities list to parse
3187  *
3188  * Parse the device/function capabilities list.
3189  **/
3190 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3191                                      u32 cap_count,
3192                                      enum i40e_admin_queue_opc list_type_opc)
3193 {
3194         struct i40e_aqc_list_capabilities_element_resp *cap;
3195         u32 valid_functions, num_functions;
3196         u32 number, logical_id, phys_id;
3197         struct i40e_hw_capabilities *p;
3198         u8 major_rev;
3199         u32 i = 0;
3200         u16 id;
3201
3202         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3203
3204         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3205                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3206         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3207                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3208         else
3209                 return;
3210
3211         for (i = 0; i < cap_count; i++, cap++) {
3212                 id = LE16_TO_CPU(cap->id);
3213                 number = LE32_TO_CPU(cap->number);
3214                 logical_id = LE32_TO_CPU(cap->logical_id);
3215                 phys_id = LE32_TO_CPU(cap->phys_id);
3216                 major_rev = cap->major_rev;
3217
3218                 switch (id) {
3219                 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3220                         p->switch_mode = number;
3221                         break;
3222                 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3223                         p->management_mode = number;
3224                         break;
3225                 case I40E_DEV_FUNC_CAP_NPAR:
3226                         p->npar_enable = number;
3227                         break;
3228                 case I40E_DEV_FUNC_CAP_OS2BMC:
3229                         p->os2bmc = number;
3230                         break;
3231                 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3232                         p->valid_functions = number;
3233                         break;
3234                 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3235                         if (number == 1)
3236                                 p->sr_iov_1_1 = true;
3237                         break;
3238                 case I40E_DEV_FUNC_CAP_VF:
3239                         p->num_vfs = number;
3240                         p->vf_base_id = logical_id;
3241                         break;
3242                 case I40E_DEV_FUNC_CAP_VMDQ:
3243                         if (number == 1)
3244                                 p->vmdq = true;
3245                         break;
3246                 case I40E_DEV_FUNC_CAP_802_1_QBG:
3247                         if (number == 1)
3248                                 p->evb_802_1_qbg = true;
3249                         break;
3250                 case I40E_DEV_FUNC_CAP_802_1_QBH:
3251                         if (number == 1)
3252                                 p->evb_802_1_qbh = true;
3253                         break;
3254                 case I40E_DEV_FUNC_CAP_VSI:
3255                         p->num_vsis = number;
3256                         break;
3257                 case I40E_DEV_FUNC_CAP_DCB:
3258                         if (number == 1) {
3259                                 p->dcb = true;
3260                                 p->enabled_tcmap = logical_id;
3261                                 p->maxtc = phys_id;
3262                         }
3263                         break;
3264                 case I40E_DEV_FUNC_CAP_FCOE:
3265                         if (number == 1)
3266                                 p->fcoe = true;
3267                         break;
3268                 case I40E_DEV_FUNC_CAP_ISCSI:
3269                         if (number == 1)
3270                                 p->iscsi = true;
3271                         break;
3272                 case I40E_DEV_FUNC_CAP_RSS:
3273                         p->rss = true;
3274                         p->rss_table_size = number;
3275                         p->rss_table_entry_width = logical_id;
3276                         break;
3277                 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3278                         p->num_rx_qp = number;
3279                         p->base_queue = phys_id;
3280                         break;
3281                 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3282                         p->num_tx_qp = number;
3283                         p->base_queue = phys_id;
3284                         break;
3285                 case I40E_DEV_FUNC_CAP_MSIX:
3286                         p->num_msix_vectors = number;
3287                         break;
3288                 case I40E_DEV_FUNC_CAP_MSIX_VF:
3289                         p->num_msix_vectors_vf = number;
3290                         break;
3291                 case I40E_DEV_FUNC_CAP_FLEX10:
3292                         if (major_rev == 1) {
3293                                 if (number == 1) {
3294                                         p->flex10_enable = true;
3295                                         p->flex10_capable = true;
3296                                 }
3297                         } else {
3298                                 /* Capability revision >= 2 */
3299                                 if (number & 1)
3300                                         p->flex10_enable = true;
3301                                 if (number & 2)
3302                                         p->flex10_capable = true;
3303                         }
3304                         p->flex10_mode = logical_id;
3305                         p->flex10_status = phys_id;
3306                         break;
3307                 case I40E_DEV_FUNC_CAP_CEM:
3308                         if (number == 1)
3309                                 p->mgmt_cem = true;
3310                         break;
3311                 case I40E_DEV_FUNC_CAP_IWARP:
3312                         if (number == 1)
3313                                 p->iwarp = true;
3314                         break;
3315                 case I40E_DEV_FUNC_CAP_LED:
3316                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3317                                 p->led[phys_id] = true;
3318                         break;
3319                 case I40E_DEV_FUNC_CAP_SDP:
3320                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3321                                 p->sdp[phys_id] = true;
3322                         break;
3323                 case I40E_DEV_FUNC_CAP_MDIO:
3324                         if (number == 1) {
3325                                 p->mdio_port_num = phys_id;
3326                                 p->mdio_port_mode = logical_id;
3327                         }
3328                         break;
3329                 case I40E_DEV_FUNC_CAP_IEEE_1588:
3330                         if (number == 1)
3331                                 p->ieee_1588 = true;
3332                         break;
3333                 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3334                         p->fd = true;
3335                         p->fd_filters_guaranteed = number;
3336                         p->fd_filters_best_effort = logical_id;
3337                         break;
3338                 default:
3339                         break;
3340                 }
3341         }
3342
3343 #ifdef I40E_FCOE_ENA
3344         /* Software override ensuring FCoE is disabled if npar or mfp
3345          * mode because it is not supported in these modes.
3346          */
3347         if (p->npar_enable || p->flex10_enable)
3348                 p->fcoe = false;
3349 #else
3350         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3351         p->fcoe = false;
3352 #endif
3353
3354         /* count the enabled ports (aka the "not disabled" ports) */
3355         hw->num_ports = 0;
3356         for (i = 0; i < 4; i++) {
3357                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3358                 u64 port_cfg = 0;
3359
3360                 /* use AQ read to get the physical register offset instead
3361                  * of the port relative offset
3362                  */
3363                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3364                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3365                         hw->num_ports++;
3366         }
3367
3368         valid_functions = p->valid_functions;
3369         num_functions = 0;
3370         while (valid_functions) {
3371                 if (valid_functions & 1)
3372                         num_functions++;
3373                 valid_functions >>= 1;
3374         }
3375
3376         /* partition id is 1-based, and functions are evenly spread
3377          * across the ports as partitions
3378          */
3379         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3380         hw->num_partitions = num_functions / hw->num_ports;
3381
3382         /* additional HW specific goodies that might
3383          * someday be HW version specific
3384          */
3385         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3386 }
3387
3388 /**
3389  * i40e_aq_discover_capabilities
3390  * @hw: pointer to the hw struct
3391  * @buff: a virtual buffer to hold the capabilities
3392  * @buff_size: Size of the virtual buffer
3393  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3394  * @list_type_opc: capabilities type to discover - pass in the command opcode
3395  * @cmd_details: pointer to command details structure or NULL
3396  *
3397  * Get the device capabilities descriptions from the firmware
3398  **/
3399 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3400                                 void *buff, u16 buff_size, u16 *data_size,
3401                                 enum i40e_admin_queue_opc list_type_opc,
3402                                 struct i40e_asq_cmd_details *cmd_details)
3403 {
3404         struct i40e_aqc_list_capabilites *cmd;
3405         struct i40e_aq_desc desc;
3406         enum i40e_status_code status = I40E_SUCCESS;
3407
3408         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3409
3410         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3411                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3412                 status = I40E_ERR_PARAM;
3413                 goto exit;
3414         }
3415
3416         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3417
3418         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3419         if (buff_size > I40E_AQ_LARGE_BUF)
3420                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3421
3422         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3423         *data_size = LE16_TO_CPU(desc.datalen);
3424
3425         if (status)
3426                 goto exit;
3427
3428         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3429                                          list_type_opc);
3430
3431 exit:
3432         return status;
3433 }
3434
3435 /**
3436  * i40e_aq_update_nvm
3437  * @hw: pointer to the hw struct
3438  * @module_pointer: module pointer location in words from the NVM beginning
3439  * @offset: byte offset from the module beginning
3440  * @length: length of the section to be written (in bytes from the offset)
3441  * @data: command buffer (size [bytes] = length)
3442  * @last_command: tells if this is the last command in a series
3443  * @cmd_details: pointer to command details structure or NULL
3444  *
3445  * Update the NVM using the admin queue commands
3446  **/
3447 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3448                                 u32 offset, u16 length, void *data,
3449                                 bool last_command,
3450                                 struct i40e_asq_cmd_details *cmd_details)
3451 {
3452         struct i40e_aq_desc desc;
3453         struct i40e_aqc_nvm_update *cmd =
3454                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3455         enum i40e_status_code status;
3456
3457         DEBUGFUNC("i40e_aq_update_nvm");
3458
3459         /* In offset the highest byte must be zeroed. */
3460         if (offset & 0xFF000000) {
3461                 status = I40E_ERR_PARAM;
3462                 goto i40e_aq_update_nvm_exit;
3463         }
3464
3465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3466
3467         /* If this is the last command in a series, set the proper flag. */
3468         if (last_command)
3469                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3470         cmd->module_pointer = module_pointer;
3471         cmd->offset = CPU_TO_LE32(offset);
3472         cmd->length = CPU_TO_LE16(length);
3473
3474         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3475         if (length > I40E_AQ_LARGE_BUF)
3476                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3477
3478         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3479
3480 i40e_aq_update_nvm_exit:
3481         return status;
3482 }
3483
3484 /**
3485  * i40e_aq_get_lldp_mib
3486  * @hw: pointer to the hw struct
3487  * @bridge_type: type of bridge requested
3488  * @mib_type: Local, Remote or both Local and Remote MIBs
3489  * @buff: pointer to a user supplied buffer to store the MIB block
3490  * @buff_size: size of the buffer (in bytes)
3491  * @local_len : length of the returned Local LLDP MIB
3492  * @remote_len: length of the returned Remote LLDP MIB
3493  * @cmd_details: pointer to command details structure or NULL
3494  *
3495  * Requests the complete LLDP MIB (entire packet).
3496  **/
3497 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3498                                 u8 mib_type, void *buff, u16 buff_size,
3499                                 u16 *local_len, u16 *remote_len,
3500                                 struct i40e_asq_cmd_details *cmd_details)
3501 {
3502         struct i40e_aq_desc desc;
3503         struct i40e_aqc_lldp_get_mib *cmd =
3504                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3505         struct i40e_aqc_lldp_get_mib *resp =
3506                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3507         enum i40e_status_code status;
3508
3509         if (buff_size == 0 || !buff)
3510                 return I40E_ERR_PARAM;
3511
3512         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3513         /* Indirect Command */
3514         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3515
3516         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3517         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3518                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3519
3520         desc.datalen = CPU_TO_LE16(buff_size);
3521
3522         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3523         if (buff_size > I40E_AQ_LARGE_BUF)
3524                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3525
3526         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3527         if (!status) {
3528                 if (local_len != NULL)
3529                         *local_len = LE16_TO_CPU(resp->local_len);
3530                 if (remote_len != NULL)
3531                         *remote_len = LE16_TO_CPU(resp->remote_len);
3532         }
3533
3534         return status;
3535 }
3536
3537  /**
3538  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3539  * @hw: pointer to the hw struct
3540  * @mib_type: Local, Remote or both Local and Remote MIBs
3541  * @buff: pointer to a user supplied buffer to store the MIB block
3542  * @buff_size: size of the buffer (in bytes)
3543  * @cmd_details: pointer to command details structure or NULL
3544  *
3545  * Set the LLDP MIB.
3546  **/
3547 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3548                                 u8 mib_type, void *buff, u16 buff_size,
3549                                 struct i40e_asq_cmd_details *cmd_details)
3550 {
3551         struct i40e_aq_desc desc;
3552         struct i40e_aqc_lldp_set_local_mib *cmd =
3553                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3554         enum i40e_status_code status;
3555
3556         if (buff_size == 0 || !buff)
3557                 return I40E_ERR_PARAM;
3558
3559         i40e_fill_default_direct_cmd_desc(&desc,
3560                                 i40e_aqc_opc_lldp_set_local_mib);
3561         /* Indirect Command */
3562         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3563         if (buff_size > I40E_AQ_LARGE_BUF)
3564                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3565         desc.datalen = CPU_TO_LE16(buff_size);
3566
3567         cmd->type = mib_type;
3568         cmd->length = CPU_TO_LE16(buff_size);
3569         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3570         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3571
3572         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3573         return status;
3574 }
3575
3576 /**
3577  * i40e_aq_cfg_lldp_mib_change_event
3578  * @hw: pointer to the hw struct
3579  * @enable_update: Enable or Disable event posting
3580  * @cmd_details: pointer to command details structure or NULL
3581  *
3582  * Enable or Disable posting of an event on ARQ when LLDP MIB
3583  * associated with the interface changes
3584  **/
3585 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3586                                 bool enable_update,
3587                                 struct i40e_asq_cmd_details *cmd_details)
3588 {
3589         struct i40e_aq_desc desc;
3590         struct i40e_aqc_lldp_update_mib *cmd =
3591                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3592         enum i40e_status_code status;
3593
3594         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3595
3596         if (!enable_update)
3597                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3598
3599         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3600
3601         return status;
3602 }
3603
3604 /**
3605  * i40e_aq_add_lldp_tlv
3606  * @hw: pointer to the hw struct
3607  * @bridge_type: type of bridge
3608  * @buff: buffer with TLV to add
3609  * @buff_size: length of the buffer
3610  * @tlv_len: length of the TLV to be added
3611  * @mib_len: length of the LLDP MIB returned in response
3612  * @cmd_details: pointer to command details structure or NULL
3613  *
3614  * Add the specified TLV to LLDP Local MIB for the given bridge type,
3615  * it is responsibility of the caller to make sure that the TLV is not
3616  * already present in the LLDPDU.
3617  * In return firmware will write the complete LLDP MIB with the newly
3618  * added TLV in the response buffer.
3619  **/
3620 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3621                                 void *buff, u16 buff_size, u16 tlv_len,
3622                                 u16 *mib_len,
3623                                 struct i40e_asq_cmd_details *cmd_details)
3624 {
3625         struct i40e_aq_desc desc;
3626         struct i40e_aqc_lldp_add_tlv *cmd =
3627                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3628         enum i40e_status_code status;
3629
3630         if (buff_size == 0 || !buff || tlv_len == 0)
3631                 return I40E_ERR_PARAM;
3632
3633         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3634
3635         /* Indirect Command */
3636         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3637         if (buff_size > I40E_AQ_LARGE_BUF)
3638                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3639         desc.datalen = CPU_TO_LE16(buff_size);
3640
3641         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3642                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3643         cmd->len = CPU_TO_LE16(tlv_len);
3644
3645         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3646         if (!status) {
3647                 if (mib_len != NULL)
3648                         *mib_len = LE16_TO_CPU(desc.datalen);
3649         }
3650
3651         return status;
3652 }
3653
3654 /**
3655  * i40e_aq_update_lldp_tlv
3656  * @hw: pointer to the hw struct
3657  * @bridge_type: type of bridge
3658  * @buff: buffer with TLV to update
3659  * @buff_size: size of the buffer holding original and updated TLVs
3660  * @old_len: Length of the Original TLV
3661  * @new_len: Length of the Updated TLV
3662  * @offset: offset of the updated TLV in the buff
3663  * @mib_len: length of the returned LLDP MIB
3664  * @cmd_details: pointer to command details structure or NULL
3665  *
3666  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3667  * Firmware will place the complete LLDP MIB in response buffer with the
3668  * updated TLV.
3669  **/
3670 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3671                                 u8 bridge_type, void *buff, u16 buff_size,
3672                                 u16 old_len, u16 new_len, u16 offset,
3673                                 u16 *mib_len,
3674                                 struct i40e_asq_cmd_details *cmd_details)
3675 {
3676         struct i40e_aq_desc desc;
3677         struct i40e_aqc_lldp_update_tlv *cmd =
3678                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3679         enum i40e_status_code status;
3680
3681         if (buff_size == 0 || !buff || offset == 0 ||
3682             old_len == 0 || new_len == 0)
3683                 return I40E_ERR_PARAM;
3684
3685         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3686
3687         /* Indirect Command */
3688         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3689         if (buff_size > I40E_AQ_LARGE_BUF)
3690                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3691         desc.datalen = CPU_TO_LE16(buff_size);
3692
3693         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3694                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3695         cmd->old_len = CPU_TO_LE16(old_len);
3696         cmd->new_offset = CPU_TO_LE16(offset);
3697         cmd->new_len = CPU_TO_LE16(new_len);
3698
3699         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3700         if (!status) {
3701                 if (mib_len != NULL)
3702                         *mib_len = LE16_TO_CPU(desc.datalen);
3703         }
3704
3705         return status;
3706 }
3707
3708 /**
3709  * i40e_aq_delete_lldp_tlv
3710  * @hw: pointer to the hw struct
3711  * @bridge_type: type of bridge
3712  * @buff: pointer to a user supplied buffer that has the TLV
3713  * @buff_size: length of the buffer
3714  * @tlv_len: length of the TLV to be deleted
3715  * @mib_len: length of the returned LLDP MIB
3716  * @cmd_details: pointer to command details structure or NULL
3717  *
3718  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3719  * The firmware places the entire LLDP MIB in the response buffer.
3720  **/
3721 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3722                                 u8 bridge_type, void *buff, u16 buff_size,
3723                                 u16 tlv_len, u16 *mib_len,
3724                                 struct i40e_asq_cmd_details *cmd_details)
3725 {
3726         struct i40e_aq_desc desc;
3727         struct i40e_aqc_lldp_add_tlv *cmd =
3728                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3729         enum i40e_status_code status;
3730
3731         if (buff_size == 0 || !buff)
3732                 return I40E_ERR_PARAM;
3733
3734         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3735
3736         /* Indirect Command */
3737         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3738         if (buff_size > I40E_AQ_LARGE_BUF)
3739                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3740         desc.datalen = CPU_TO_LE16(buff_size);
3741         cmd->len = CPU_TO_LE16(tlv_len);
3742         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3743                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3744
3745         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3746         if (!status) {
3747                 if (mib_len != NULL)
3748                         *mib_len = LE16_TO_CPU(desc.datalen);
3749         }
3750
3751         return status;
3752 }
3753
3754 /**
3755  * i40e_aq_stop_lldp
3756  * @hw: pointer to the hw struct
3757  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3758  * @cmd_details: pointer to command details structure or NULL
3759  *
3760  * Stop or Shutdown the embedded LLDP Agent
3761  **/
3762 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3763                                 struct i40e_asq_cmd_details *cmd_details)
3764 {
3765         struct i40e_aq_desc desc;
3766         struct i40e_aqc_lldp_stop *cmd =
3767                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3768         enum i40e_status_code status;
3769
3770         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3771
3772         if (shutdown_agent)
3773                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3774
3775         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3776
3777         return status;
3778 }
3779
3780 /**
3781  * i40e_aq_start_lldp
3782  * @hw: pointer to the hw struct
3783  * @cmd_details: pointer to command details structure or NULL
3784  *
3785  * Start the embedded LLDP Agent on all ports.
3786  **/
3787 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3788                                 struct i40e_asq_cmd_details *cmd_details)
3789 {
3790         struct i40e_aq_desc desc;
3791         struct i40e_aqc_lldp_start *cmd =
3792                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3793         enum i40e_status_code status;
3794
3795         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3796
3797         cmd->command = I40E_AQ_LLDP_AGENT_START;
3798
3799         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3800
3801         return status;
3802 }
3803
3804 /**
3805  * i40e_aq_get_cee_dcb_config
3806  * @hw: pointer to the hw struct
3807  * @buff: response buffer that stores CEE operational configuration
3808  * @buff_size: size of the buffer passed
3809  * @cmd_details: pointer to command details structure or NULL
3810  *
3811  * Get CEE DCBX mode operational configuration from firmware
3812  **/
3813 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3814                                 void *buff, u16 buff_size,
3815                                 struct i40e_asq_cmd_details *cmd_details)
3816 {
3817         struct i40e_aq_desc desc;
3818         enum i40e_status_code status;
3819
3820         if (buff_size == 0 || !buff)
3821                 return I40E_ERR_PARAM;
3822
3823         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3824
3825         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3826         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3827                                        cmd_details);
3828
3829         return status;
3830 }
3831
3832 /**
3833  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3834  * @hw: pointer to the hw struct
3835  * @start_agent: True if DCBx Agent needs to be Started
3836  *                              False if DCBx Agent needs to be Stopped
3837  * @cmd_details: pointer to command details structure or NULL
3838  *
3839  * Start/Stop the embedded dcbx Agent
3840  **/
3841 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3842                                 bool start_agent,
3843                                 struct i40e_asq_cmd_details *cmd_details)
3844 {
3845         struct i40e_aq_desc desc;
3846         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3847                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3848                                 &desc.params.raw;
3849         enum i40e_status_code status;
3850
3851         i40e_fill_default_direct_cmd_desc(&desc,
3852                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
3853
3854         if (start_agent)
3855                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3856
3857         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3858
3859         return status;
3860 }
3861
3862 /**
3863  * i40e_aq_add_udp_tunnel
3864  * @hw: pointer to the hw struct
3865  * @udp_port: the UDP port to add
3866  * @header_len: length of the tunneling header length in DWords
3867  * @protocol_index: protocol index type
3868  * @filter_index: pointer to filter index
3869  * @cmd_details: pointer to command details structure or NULL
3870  **/
3871 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3872                                 u16 udp_port, u8 protocol_index,
3873                                 u8 *filter_index,
3874                                 struct i40e_asq_cmd_details *cmd_details)
3875 {
3876         struct i40e_aq_desc desc;
3877         struct i40e_aqc_add_udp_tunnel *cmd =
3878                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3879         struct i40e_aqc_del_udp_tunnel_completion *resp =
3880                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3881         enum i40e_status_code status;
3882
3883         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3884
3885         cmd->udp_port = CPU_TO_LE16(udp_port);
3886         cmd->protocol_type = protocol_index;
3887
3888         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3889
3890         if (!status && filter_index)
3891                 *filter_index = resp->index;
3892
3893         return status;
3894 }
3895
3896 /**
3897  * i40e_aq_del_udp_tunnel
3898  * @hw: pointer to the hw struct
3899  * @index: filter index
3900  * @cmd_details: pointer to command details structure or NULL
3901  **/
3902 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3903                                 struct i40e_asq_cmd_details *cmd_details)
3904 {
3905         struct i40e_aq_desc desc;
3906         struct i40e_aqc_remove_udp_tunnel *cmd =
3907                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3908         enum i40e_status_code status;
3909
3910         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3911
3912         cmd->index = index;
3913
3914         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3915
3916         return status;
3917 }
3918
3919 /**
3920  * i40e_aq_get_switch_resource_alloc (0x0204)
3921  * @hw: pointer to the hw struct
3922  * @num_entries: pointer to u8 to store the number of resource entries returned
3923  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
3924  *        to store the resource information for all resource types.  Each
3925  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
3926  * @count: size, in bytes, of the buffer provided
3927  * @cmd_details: pointer to command details structure or NULL
3928  *
3929  * Query the resources allocated to a function.
3930  **/
3931 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3932                         u8 *num_entries,
3933                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3934                         u16 count,
3935                         struct i40e_asq_cmd_details *cmd_details)
3936 {
3937         struct i40e_aq_desc desc;
3938         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3939                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3940         enum i40e_status_code status;
3941         u16 length = count * sizeof(*buf);
3942
3943         i40e_fill_default_direct_cmd_desc(&desc,
3944                                         i40e_aqc_opc_get_switch_resource_alloc);
3945
3946         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3947         if (length > I40E_AQ_LARGE_BUF)
3948                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3949
3950         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3951
3952         if (!status && num_entries)
3953                 *num_entries = cmd_resp->num_entries;
3954
3955         return status;
3956 }
3957
3958 /**
3959  * i40e_aq_delete_element - Delete switch element
3960  * @hw: pointer to the hw struct
3961  * @seid: the SEID to delete from the switch
3962  * @cmd_details: pointer to command details structure or NULL
3963  *
3964  * This deletes a switch element from the switch.
3965  **/
3966 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3967                                 struct i40e_asq_cmd_details *cmd_details)
3968 {
3969         struct i40e_aq_desc desc;
3970         struct i40e_aqc_switch_seid *cmd =
3971                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3972         enum i40e_status_code status;
3973
3974         if (seid == 0)
3975                 return I40E_ERR_PARAM;
3976
3977         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3978
3979         cmd->seid = CPU_TO_LE16(seid);
3980
3981         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3982
3983         return status;
3984 }
3985
3986 /**
3987  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3988  * @hw: pointer to the hw struct
3989  * @flags: component flags
3990  * @mac_seid: uplink seid (MAC SEID)
3991  * @vsi_seid: connected vsi seid
3992  * @ret_seid: seid of create pv component
3993  *
3994  * This instantiates an i40e port virtualizer with specified flags.
3995  * Depending on specified flags the port virtualizer can act as a
3996  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3997  */
3998 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3999                                        u16 mac_seid, u16 vsi_seid,
4000                                        u16 *ret_seid)
4001 {
4002         struct i40e_aq_desc desc;
4003         struct i40e_aqc_add_update_pv *cmd =
4004                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4005         struct i40e_aqc_add_update_pv_completion *resp =
4006                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4007         enum i40e_status_code status;
4008
4009         if (vsi_seid == 0)
4010                 return I40E_ERR_PARAM;
4011
4012         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4013         cmd->command_flags = CPU_TO_LE16(flags);
4014         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4015         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4016
4017         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4018         if (!status && ret_seid)
4019                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4020
4021         return status;
4022 }
4023
4024 /**
4025  * i40e_aq_add_tag - Add an S/E-tag
4026  * @hw: pointer to the hw struct
4027  * @direct_to_queue: should s-tag direct flow to a specific queue
4028  * @vsi_seid: VSI SEID to use this tag
4029  * @tag: value of the tag
4030  * @queue_num: queue number, only valid is direct_to_queue is true
4031  * @tags_used: return value, number of tags in use by this PF
4032  * @tags_free: return value, number of unallocated tags
4033  * @cmd_details: pointer to command details structure or NULL
4034  *
4035  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4036  * the number of tags allocated by the PF, and the number of unallocated
4037  * tags available.
4038  **/
4039 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4040                                 u16 vsi_seid, u16 tag, u16 queue_num,
4041                                 u16 *tags_used, u16 *tags_free,
4042                                 struct i40e_asq_cmd_details *cmd_details)
4043 {
4044         struct i40e_aq_desc desc;
4045         struct i40e_aqc_add_tag *cmd =
4046                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4047         struct i40e_aqc_add_remove_tag_completion *resp =
4048                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4049         enum i40e_status_code status;
4050
4051         if (vsi_seid == 0)
4052                 return I40E_ERR_PARAM;
4053
4054         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4055
4056         cmd->seid = CPU_TO_LE16(vsi_seid);
4057         cmd->tag = CPU_TO_LE16(tag);
4058         if (direct_to_queue) {
4059                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4060                 cmd->queue_number = CPU_TO_LE16(queue_num);
4061         }
4062
4063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4064
4065         if (!status) {
4066                 if (tags_used != NULL)
4067                         *tags_used = LE16_TO_CPU(resp->tags_used);
4068                 if (tags_free != NULL)
4069                         *tags_free = LE16_TO_CPU(resp->tags_free);
4070         }
4071
4072         return status;
4073 }
4074
4075 /**
4076  * i40e_aq_remove_tag - Remove an S- or E-tag
4077  * @hw: pointer to the hw struct
4078  * @vsi_seid: VSI SEID this tag is associated with
4079  * @tag: value of the S-tag to delete
4080  * @tags_used: return value, number of tags in use by this PF
4081  * @tags_free: return value, number of unallocated tags
4082  * @cmd_details: pointer to command details structure or NULL
4083  *
4084  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4085  * the number of tags allocated by the PF, and the number of unallocated
4086  * tags available.
4087  **/
4088 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4089                                 u16 tag, u16 *tags_used, u16 *tags_free,
4090                                 struct i40e_asq_cmd_details *cmd_details)
4091 {
4092         struct i40e_aq_desc desc;
4093         struct i40e_aqc_remove_tag *cmd =
4094                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4095         struct i40e_aqc_add_remove_tag_completion *resp =
4096                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4097         enum i40e_status_code status;
4098
4099         if (vsi_seid == 0)
4100                 return I40E_ERR_PARAM;
4101
4102         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4103
4104         cmd->seid = CPU_TO_LE16(vsi_seid);
4105         cmd->tag = CPU_TO_LE16(tag);
4106
4107         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4108
4109         if (!status) {
4110                 if (tags_used != NULL)
4111                         *tags_used = LE16_TO_CPU(resp->tags_used);
4112                 if (tags_free != NULL)
4113                         *tags_free = LE16_TO_CPU(resp->tags_free);
4114         }
4115
4116         return status;
4117 }
4118
4119 /**
4120  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4121  * @hw: pointer to the hw struct
4122  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4123  * @etag: value of E-tag to add
4124  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4125  * @buf: address of indirect buffer
4126  * @tags_used: return value, number of E-tags in use by this port
4127  * @tags_free: return value, number of unallocated M-tags
4128  * @cmd_details: pointer to command details structure or NULL
4129  *
4130  * This associates a multicast E-tag to a port virtualizer.  It will return
4131  * the number of tags allocated by the PF, and the number of unallocated
4132  * tags available.
4133  *
4134  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4135  * num_tags_in_buf long.
4136  **/
4137 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4138                                 u16 etag, u8 num_tags_in_buf, void *buf,
4139                                 u16 *tags_used, u16 *tags_free,
4140                                 struct i40e_asq_cmd_details *cmd_details)
4141 {
4142         struct i40e_aq_desc desc;
4143         struct i40e_aqc_add_remove_mcast_etag *cmd =
4144                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4145         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4146            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4147         enum i40e_status_code status;
4148         u16 length = sizeof(u16) * num_tags_in_buf;
4149
4150         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4151                 return I40E_ERR_PARAM;
4152
4153         i40e_fill_default_direct_cmd_desc(&desc,
4154                                           i40e_aqc_opc_add_multicast_etag);
4155
4156         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4157         cmd->etag = CPU_TO_LE16(etag);
4158         cmd->num_unicast_etags = num_tags_in_buf;
4159
4160         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4161         if (length > I40E_AQ_LARGE_BUF)
4162                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4163
4164         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4165
4166         if (!status) {
4167                 if (tags_used != NULL)
4168                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4169                 if (tags_free != NULL)
4170                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4171         }
4172
4173         return status;
4174 }
4175
4176 /**
4177  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4178  * @hw: pointer to the hw struct
4179  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4180  * @etag: value of the E-tag to remove
4181  * @tags_used: return value, number of tags in use by this port
4182  * @tags_free: return value, number of unallocated tags
4183  * @cmd_details: pointer to command details structure or NULL
4184  *
4185  * This deletes an E-tag from the port virtualizer.  It will return
4186  * the number of tags allocated by the port, and the number of unallocated
4187  * tags available.
4188  **/
4189 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4190                                 u16 etag, u16 *tags_used, u16 *tags_free,
4191                                 struct i40e_asq_cmd_details *cmd_details)
4192 {
4193         struct i40e_aq_desc desc;
4194         struct i40e_aqc_add_remove_mcast_etag *cmd =
4195                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4196         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4197            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4198         enum i40e_status_code status;
4199
4200
4201         if (pv_seid == 0)
4202                 return I40E_ERR_PARAM;
4203
4204         i40e_fill_default_direct_cmd_desc(&desc,
4205                                           i40e_aqc_opc_remove_multicast_etag);
4206
4207         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4208         cmd->etag = CPU_TO_LE16(etag);
4209
4210         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4211
4212         if (!status) {
4213                 if (tags_used != NULL)
4214                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4215                 if (tags_free != NULL)
4216                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4217         }
4218
4219         return status;
4220 }
4221
4222 /**
4223  * i40e_aq_update_tag - Update an S/E-tag
4224  * @hw: pointer to the hw struct
4225  * @vsi_seid: VSI SEID using this S-tag
4226  * @old_tag: old tag value
4227  * @new_tag: new tag value
4228  * @tags_used: return value, number of tags in use by this PF
4229  * @tags_free: return value, number of unallocated tags
4230  * @cmd_details: pointer to command details structure or NULL
4231  *
4232  * This updates the value of the tag currently attached to this VSI
4233  * in the switch complex.  It will return the number of tags allocated
4234  * by the PF, and the number of unallocated tags available.
4235  **/
4236 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4237                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4238                                 u16 *tags_free,
4239                                 struct i40e_asq_cmd_details *cmd_details)
4240 {
4241         struct i40e_aq_desc desc;
4242         struct i40e_aqc_update_tag *cmd =
4243                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4244         struct i40e_aqc_update_tag_completion *resp =
4245                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4246         enum i40e_status_code status;
4247
4248         if (vsi_seid == 0)
4249                 return I40E_ERR_PARAM;
4250
4251         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4252
4253         cmd->seid = CPU_TO_LE16(vsi_seid);
4254         cmd->old_tag = CPU_TO_LE16(old_tag);
4255         cmd->new_tag = CPU_TO_LE16(new_tag);
4256
4257         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4258
4259         if (!status) {
4260                 if (tags_used != NULL)
4261                         *tags_used = LE16_TO_CPU(resp->tags_used);
4262                 if (tags_free != NULL)
4263                         *tags_free = LE16_TO_CPU(resp->tags_free);
4264         }
4265
4266         return status;
4267 }
4268
4269 /**
4270  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4271  * @hw: pointer to the hw struct
4272  * @tcmap: TC map for request/release any ignore PFC condition
4273  * @request: request or release ignore PFC condition
4274  * @tcmap_ret: return TCs for which PFC is currently ignored
4275  * @cmd_details: pointer to command details structure or NULL
4276  *
4277  * This sends out request/release to ignore PFC condition for a TC.
4278  * It will return the TCs for which PFC is currently ignored.
4279  **/
4280 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4281                                 bool request, u8 *tcmap_ret,
4282                                 struct i40e_asq_cmd_details *cmd_details)
4283 {
4284         struct i40e_aq_desc desc;
4285         struct i40e_aqc_pfc_ignore *cmd_resp =
4286                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4287         enum i40e_status_code status;
4288
4289         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4290
4291         if (request)
4292                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4293
4294         cmd_resp->tc_bitmap = tcmap;
4295
4296         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4297
4298         if (!status) {
4299                 if (tcmap_ret != NULL)
4300                         *tcmap_ret = cmd_resp->tc_bitmap;
4301         }
4302
4303         return status;
4304 }
4305
4306 /**
4307  * i40e_aq_dcb_updated - DCB Updated Command
4308  * @hw: pointer to the hw struct
4309  * @cmd_details: pointer to command details structure or NULL
4310  *
4311  * When LLDP is handled in PF this command is used by the PF
4312  * to notify EMP that a DCB setting is modified.
4313  * When LLDP is handled in EMP this command is used by the PF
4314  * to notify EMP whenever one of the following parameters get
4315  * modified:
4316  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4317  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4318  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4319  * EMP will return when the shared RPB settings have been
4320  * recomputed and modified. The retval field in the descriptor
4321  * will be set to 0 when RPB is modified.
4322  **/
4323 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4324                                 struct i40e_asq_cmd_details *cmd_details)
4325 {
4326         struct i40e_aq_desc desc;
4327         enum i40e_status_code status;
4328
4329         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4330
4331         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4332
4333         return status;
4334 }
4335
4336 /**
4337  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4338  * @hw: pointer to the hw struct
4339  * @seid: defines the SEID of the switch for which the stats are requested
4340  * @vlan_id: the VLAN ID for which the statistics are requested
4341  * @stat_index: index of the statistics counters block assigned to this VLAN
4342  * @cmd_details: pointer to command details structure or NULL
4343  *
4344  * XL710 supports 128 smonVlanStats counters.This command is used to
4345  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4346  * switch.
4347  **/
4348 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4349                                 u16 vlan_id, u16 *stat_index,
4350                                 struct i40e_asq_cmd_details *cmd_details)
4351 {
4352         struct i40e_aq_desc desc;
4353         struct i40e_aqc_add_remove_statistics *cmd_resp =
4354                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4355         enum i40e_status_code status;
4356
4357         if ((seid == 0) || (stat_index == NULL))
4358                 return I40E_ERR_PARAM;
4359
4360         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4361
4362         cmd_resp->seid = CPU_TO_LE16(seid);
4363         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4364
4365         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4366
4367         if (!status && stat_index)
4368                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4369
4370         return status;
4371 }
4372
4373 /**
4374  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4375  * @hw: pointer to the hw struct
4376  * @seid: defines the SEID of the switch for which the stats are requested
4377  * @vlan_id: the VLAN ID for which the statistics are requested
4378  * @stat_index: index of the statistics counters block assigned to this VLAN
4379  * @cmd_details: pointer to command details structure or NULL
4380  *
4381  * XL710 supports 128 smonVlanStats counters.This command is used to
4382  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4383  * switch.
4384  **/
4385 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4386                                 u16 vlan_id, u16 stat_index,
4387                                 struct i40e_asq_cmd_details *cmd_details)
4388 {
4389         struct i40e_aq_desc desc;
4390         struct i40e_aqc_add_remove_statistics *cmd =
4391                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4392         enum i40e_status_code status;
4393
4394         if (seid == 0)
4395                 return I40E_ERR_PARAM;
4396
4397         i40e_fill_default_direct_cmd_desc(&desc,
4398                                           i40e_aqc_opc_remove_statistics);
4399
4400         cmd->seid = CPU_TO_LE16(seid);
4401         cmd->vlan  = CPU_TO_LE16(vlan_id);
4402         cmd->stat_index = CPU_TO_LE16(stat_index);
4403
4404         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4405
4406         return status;
4407 }
4408
4409 /**
4410  * i40e_aq_set_port_parameters - set physical port parameters.
4411  * @hw: pointer to the hw struct
4412  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4413  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4414  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4415  * @double_vlan: if set double VLAN is enabled
4416  * @cmd_details: pointer to command details structure or NULL
4417  **/
4418 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4419                                 u16 bad_frame_vsi, bool save_bad_pac,
4420                                 bool pad_short_pac, bool double_vlan,
4421                                 struct i40e_asq_cmd_details *cmd_details)
4422 {
4423         struct i40e_aqc_set_port_parameters *cmd;
4424         enum i40e_status_code status;
4425         struct i40e_aq_desc desc;
4426         u16 command_flags = 0;
4427
4428         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4429
4430         i40e_fill_default_direct_cmd_desc(&desc,
4431                                           i40e_aqc_opc_set_port_parameters);
4432
4433         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4434         if (save_bad_pac)
4435                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4436         if (pad_short_pac)
4437                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4438         if (double_vlan)
4439                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4440         cmd->command_flags = CPU_TO_LE16(command_flags);
4441
4442         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4443
4444         return status;
4445 }
4446
4447 /**
4448  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4449  * @hw: pointer to the hw struct
4450  * @seid: seid for the physical port/switching component/vsi
4451  * @buff: Indirect buffer to hold data parameters and response
4452  * @buff_size: Indirect buffer size
4453  * @opcode: Tx scheduler AQ command opcode
4454  * @cmd_details: pointer to command details structure or NULL
4455  *
4456  * Generic command handler for Tx scheduler AQ commands
4457  **/
4458 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4459                                 void *buff, u16 buff_size,
4460                                  enum i40e_admin_queue_opc opcode,
4461                                 struct i40e_asq_cmd_details *cmd_details)
4462 {
4463         struct i40e_aq_desc desc;
4464         struct i40e_aqc_tx_sched_ind *cmd =
4465                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4466         enum i40e_status_code status;
4467         bool cmd_param_flag = false;
4468
4469         switch (opcode) {
4470         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4471         case i40e_aqc_opc_configure_vsi_tc_bw:
4472         case i40e_aqc_opc_enable_switching_comp_ets:
4473         case i40e_aqc_opc_modify_switching_comp_ets:
4474         case i40e_aqc_opc_disable_switching_comp_ets:
4475         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4476         case i40e_aqc_opc_configure_switching_comp_bw_config:
4477                 cmd_param_flag = true;
4478                 break;
4479         case i40e_aqc_opc_query_vsi_bw_config:
4480         case i40e_aqc_opc_query_vsi_ets_sla_config:
4481         case i40e_aqc_opc_query_switching_comp_ets_config:
4482         case i40e_aqc_opc_query_port_ets_config:
4483         case i40e_aqc_opc_query_switching_comp_bw_config:
4484                 cmd_param_flag = false;
4485                 break;
4486         default:
4487                 return I40E_ERR_PARAM;
4488         }
4489
4490         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4491
4492         /* Indirect command */
4493         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4494         if (cmd_param_flag)
4495                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4496         if (buff_size > I40E_AQ_LARGE_BUF)
4497                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4498
4499         desc.datalen = CPU_TO_LE16(buff_size);
4500
4501         cmd->vsi_seid = CPU_TO_LE16(seid);
4502
4503         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4504
4505         return status;
4506 }
4507
4508 /**
4509  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4510  * @hw: pointer to the hw struct
4511  * @seid: VSI seid
4512  * @credit: BW limit credits (0 = disabled)
4513  * @max_credit: Max BW limit credits
4514  * @cmd_details: pointer to command details structure or NULL
4515  **/
4516 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4517                                 u16 seid, u16 credit, u8 max_credit,
4518                                 struct i40e_asq_cmd_details *cmd_details)
4519 {
4520         struct i40e_aq_desc desc;
4521         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4522                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4523         enum i40e_status_code status;
4524
4525         i40e_fill_default_direct_cmd_desc(&desc,
4526                                           i40e_aqc_opc_configure_vsi_bw_limit);
4527
4528         cmd->vsi_seid = CPU_TO_LE16(seid);
4529         cmd->credit = CPU_TO_LE16(credit);
4530         cmd->max_credit = max_credit;
4531
4532         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4533
4534         return status;
4535 }
4536
4537 /**
4538  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4539  * @hw: pointer to the hw struct
4540  * @seid: switching component seid
4541  * @credit: BW limit credits (0 = disabled)
4542  * @max_bw: Max BW limit credits
4543  * @cmd_details: pointer to command details structure or NULL
4544  **/
4545 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4546                                 u16 seid, u16 credit, u8 max_bw,
4547                                 struct i40e_asq_cmd_details *cmd_details)
4548 {
4549         struct i40e_aq_desc desc;
4550         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4551           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4552         enum i40e_status_code status;
4553
4554         i40e_fill_default_direct_cmd_desc(&desc,
4555                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4556
4557         cmd->seid = CPU_TO_LE16(seid);
4558         cmd->credit = CPU_TO_LE16(credit);
4559         cmd->max_bw = max_bw;
4560
4561         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4562
4563         return status;
4564 }
4565
4566 /**
4567  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4568  * @hw: pointer to the hw struct
4569  * @seid: VSI seid
4570  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4571  * @cmd_details: pointer to command details structure or NULL
4572  **/
4573 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4574                         u16 seid,
4575                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4576                         struct i40e_asq_cmd_details *cmd_details)
4577 {
4578         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4579                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4580                                     cmd_details);
4581 }
4582
4583 /**
4584  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4585  * @hw: pointer to the hw struct
4586  * @seid: VSI seid
4587  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4588  * @cmd_details: pointer to command details structure or NULL
4589  **/
4590 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4591                         u16 seid,
4592                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4593                         struct i40e_asq_cmd_details *cmd_details)
4594 {
4595         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4596                                     i40e_aqc_opc_configure_vsi_tc_bw,
4597                                     cmd_details);
4598 }
4599
4600 /**
4601  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4602  * @hw: pointer to the hw struct
4603  * @seid: seid of the switching component connected to Physical Port
4604  * @ets_data: Buffer holding ETS parameters
4605  * @cmd_details: pointer to command details structure or NULL
4606  **/
4607 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4608                 u16 seid,
4609                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4610                 enum i40e_admin_queue_opc opcode,
4611                 struct i40e_asq_cmd_details *cmd_details)
4612 {
4613         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4614                                     sizeof(*ets_data), opcode, cmd_details);
4615 }
4616
4617 /**
4618  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4619  * @hw: pointer to the hw struct
4620  * @seid: seid of the switching component
4621  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4622  * @cmd_details: pointer to command details structure or NULL
4623  **/
4624 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4625         u16 seid,
4626         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4627         struct i40e_asq_cmd_details *cmd_details)
4628 {
4629         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4630                             i40e_aqc_opc_configure_switching_comp_bw_config,
4631                             cmd_details);
4632 }
4633
4634 /**
4635  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4636  * @hw: pointer to the hw struct
4637  * @seid: seid of the switching component
4638  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4639  * @cmd_details: pointer to command details structure or NULL
4640  **/
4641 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4642         struct i40e_hw *hw, u16 seid,
4643         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4644         struct i40e_asq_cmd_details *cmd_details)
4645 {
4646         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4647                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4648                             cmd_details);
4649 }
4650
4651 /**
4652  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4653  * @hw: pointer to the hw struct
4654  * @seid: seid of the VSI
4655  * @bw_data: Buffer to hold VSI BW configuration
4656  * @cmd_details: pointer to command details structure or NULL
4657  **/
4658 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4659                         u16 seid,
4660                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4661                         struct i40e_asq_cmd_details *cmd_details)
4662 {
4663         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4664                                     i40e_aqc_opc_query_vsi_bw_config,
4665                                     cmd_details);
4666 }
4667
4668 /**
4669  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4670  * @hw: pointer to the hw struct
4671  * @seid: seid of the VSI
4672  * @bw_data: Buffer to hold VSI BW configuration per TC
4673  * @cmd_details: pointer to command details structure or NULL
4674  **/
4675 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4676                         u16 seid,
4677                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4678                         struct i40e_asq_cmd_details *cmd_details)
4679 {
4680         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4681                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4682                                     cmd_details);
4683 }
4684
4685 /**
4686  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4687  * @hw: pointer to the hw struct
4688  * @seid: seid of the switching component
4689  * @bw_data: Buffer to hold switching component's per TC BW config
4690  * @cmd_details: pointer to command details structure or NULL
4691  **/
4692 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4693                 u16 seid,
4694                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4695                 struct i40e_asq_cmd_details *cmd_details)
4696 {
4697         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4698                                    i40e_aqc_opc_query_switching_comp_ets_config,
4699                                    cmd_details);
4700 }
4701
4702 /**
4703  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4704  * @hw: pointer to the hw struct
4705  * @seid: seid of the VSI or switching component connected to Physical Port
4706  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4707  * @cmd_details: pointer to command details structure or NULL
4708  **/
4709 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4710                         u16 seid,
4711                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4712                         struct i40e_asq_cmd_details *cmd_details)
4713 {
4714         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4715                                     i40e_aqc_opc_query_port_ets_config,
4716                                     cmd_details);
4717 }
4718
4719 /**
4720  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4721  * @hw: pointer to the hw struct
4722  * @seid: seid of the switching component
4723  * @bw_data: Buffer to hold switching component's BW configuration
4724  * @cmd_details: pointer to command details structure or NULL
4725  **/
4726 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4727                 u16 seid,
4728                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4729                 struct i40e_asq_cmd_details *cmd_details)
4730 {
4731         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4732                                     i40e_aqc_opc_query_switching_comp_bw_config,
4733                                     cmd_details);
4734 }
4735
4736 /**
4737  * i40e_validate_filter_settings
4738  * @hw: pointer to the hardware structure
4739  * @settings: Filter control settings
4740  *
4741  * Check and validate the filter control settings passed.
4742  * The function checks for the valid filter/context sizes being
4743  * passed for FCoE and PE.
4744  *
4745  * Returns I40E_SUCCESS if the values passed are valid and within
4746  * range else returns an error.
4747  **/
4748 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4749                                 struct i40e_filter_control_settings *settings)
4750 {
4751         u32 fcoe_cntx_size, fcoe_filt_size;
4752         u32 pe_cntx_size, pe_filt_size;
4753         u32 fcoe_fmax;
4754
4755         u32 val;
4756
4757         /* Validate FCoE settings passed */
4758         switch (settings->fcoe_filt_num) {
4759         case I40E_HASH_FILTER_SIZE_1K:
4760         case I40E_HASH_FILTER_SIZE_2K:
4761         case I40E_HASH_FILTER_SIZE_4K:
4762         case I40E_HASH_FILTER_SIZE_8K:
4763         case I40E_HASH_FILTER_SIZE_16K:
4764         case I40E_HASH_FILTER_SIZE_32K:
4765                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4766                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4767                 break;
4768         default:
4769                 return I40E_ERR_PARAM;
4770         }
4771
4772         switch (settings->fcoe_cntx_num) {
4773         case I40E_DMA_CNTX_SIZE_512:
4774         case I40E_DMA_CNTX_SIZE_1K:
4775         case I40E_DMA_CNTX_SIZE_2K:
4776         case I40E_DMA_CNTX_SIZE_4K:
4777                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4778                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4779                 break;
4780         default:
4781                 return I40E_ERR_PARAM;
4782         }
4783
4784         /* Validate PE settings passed */
4785         switch (settings->pe_filt_num) {
4786         case I40E_HASH_FILTER_SIZE_1K:
4787         case I40E_HASH_FILTER_SIZE_2K:
4788         case I40E_HASH_FILTER_SIZE_4K:
4789         case I40E_HASH_FILTER_SIZE_8K:
4790         case I40E_HASH_FILTER_SIZE_16K:
4791         case I40E_HASH_FILTER_SIZE_32K:
4792         case I40E_HASH_FILTER_SIZE_64K:
4793         case I40E_HASH_FILTER_SIZE_128K:
4794         case I40E_HASH_FILTER_SIZE_256K:
4795         case I40E_HASH_FILTER_SIZE_512K:
4796         case I40E_HASH_FILTER_SIZE_1M:
4797                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4798                 pe_filt_size <<= (u32)settings->pe_filt_num;
4799                 break;
4800         default:
4801                 return I40E_ERR_PARAM;
4802         }
4803
4804         switch (settings->pe_cntx_num) {
4805         case I40E_DMA_CNTX_SIZE_512:
4806         case I40E_DMA_CNTX_SIZE_1K:
4807         case I40E_DMA_CNTX_SIZE_2K:
4808         case I40E_DMA_CNTX_SIZE_4K:
4809         case I40E_DMA_CNTX_SIZE_8K:
4810         case I40E_DMA_CNTX_SIZE_16K:
4811         case I40E_DMA_CNTX_SIZE_32K:
4812         case I40E_DMA_CNTX_SIZE_64K:
4813         case I40E_DMA_CNTX_SIZE_128K:
4814         case I40E_DMA_CNTX_SIZE_256K:
4815                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4816                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4817                 break;
4818         default:
4819                 return I40E_ERR_PARAM;
4820         }
4821
4822         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4823         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4824         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4825                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4826         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4827                 return I40E_ERR_INVALID_SIZE;
4828
4829         return I40E_SUCCESS;
4830 }
4831
4832 /**
4833  * i40e_set_filter_control
4834  * @hw: pointer to the hardware structure
4835  * @settings: Filter control settings
4836  *
4837  * Set the Queue Filters for PE/FCoE and enable filters required
4838  * for a single PF. It is expected that these settings are programmed
4839  * at the driver initialization time.
4840  **/
4841 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4842                                 struct i40e_filter_control_settings *settings)
4843 {
4844         enum i40e_status_code ret = I40E_SUCCESS;
4845         u32 hash_lut_size = 0;
4846         u32 val;
4847
4848         if (!settings)
4849                 return I40E_ERR_PARAM;
4850
4851         /* Validate the input settings */
4852         ret = i40e_validate_filter_settings(hw, settings);
4853         if (ret)
4854                 return ret;
4855
4856         /* Read the PF Queue Filter control register */
4857         val = rd32(hw, I40E_PFQF_CTL_0);
4858
4859         /* Program required PE hash buckets for the PF */
4860         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4861         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4862                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4863         /* Program required PE contexts for the PF */
4864         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4865         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4866                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4867
4868         /* Program required FCoE hash buckets for the PF */
4869         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4870         val |= ((u32)settings->fcoe_filt_num <<
4871                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4872                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4873         /* Program required FCoE DDP contexts for the PF */
4874         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4875         val |= ((u32)settings->fcoe_cntx_num <<
4876                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4877                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4878
4879         /* Program Hash LUT size for the PF */
4880         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4881         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4882                 hash_lut_size = 1;
4883         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4884                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4885
4886         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4887         if (settings->enable_fdir)
4888                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4889         if (settings->enable_ethtype)
4890                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4891         if (settings->enable_macvlan)
4892                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4893
4894         wr32(hw, I40E_PFQF_CTL_0, val);
4895
4896         return I40E_SUCCESS;
4897 }
4898
4899 /**
4900  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4901  * @hw: pointer to the hw struct
4902  * @mac_addr: MAC address to use in the filter
4903  * @ethtype: Ethertype to use in the filter
4904  * @flags: Flags that needs to be applied to the filter
4905  * @vsi_seid: seid of the control VSI
4906  * @queue: VSI queue number to send the packet to
4907  * @is_add: Add control packet filter if True else remove
4908  * @stats: Structure to hold information on control filter counts
4909  * @cmd_details: pointer to command details structure or NULL
4910  *
4911  * This command will Add or Remove control packet filter for a control VSI.
4912  * In return it will update the total number of perfect filter count in
4913  * the stats member.
4914  **/
4915 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4916                                 u8 *mac_addr, u16 ethtype, u16 flags,
4917                                 u16 vsi_seid, u16 queue, bool is_add,
4918                                 struct i40e_control_filter_stats *stats,
4919                                 struct i40e_asq_cmd_details *cmd_details)
4920 {
4921         struct i40e_aq_desc desc;
4922         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4923                 (struct i40e_aqc_add_remove_control_packet_filter *)
4924                 &desc.params.raw;
4925         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4926                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4927                 &desc.params.raw;
4928         enum i40e_status_code status;
4929
4930         if (vsi_seid == 0)
4931                 return I40E_ERR_PARAM;
4932
4933         if (is_add) {
4934                 i40e_fill_default_direct_cmd_desc(&desc,
4935                                 i40e_aqc_opc_add_control_packet_filter);
4936                 cmd->queue = CPU_TO_LE16(queue);
4937         } else {
4938                 i40e_fill_default_direct_cmd_desc(&desc,
4939                                 i40e_aqc_opc_remove_control_packet_filter);
4940         }
4941
4942         if (mac_addr)
4943                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4944                             I40E_NONDMA_TO_NONDMA);
4945
4946         cmd->etype = CPU_TO_LE16(ethtype);
4947         cmd->flags = CPU_TO_LE16(flags);
4948         cmd->seid = CPU_TO_LE16(vsi_seid);
4949
4950         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4951
4952         if (!status && stats) {
4953                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4954                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4955                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4956                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4957         }
4958
4959         return status;
4960 }
4961
4962 /**
4963  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4964  * @hw: pointer to the hw struct
4965  * @seid: VSI seid to add ethertype filter from
4966  **/
4967 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4968 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4969                                                     u16 seid)
4970 {
4971         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4972                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4973                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4974         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4975         enum i40e_status_code status;
4976
4977         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
4978                                                        seid, 0, true, NULL,
4979                                                        NULL);
4980         if (status)
4981                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4982 }
4983
4984 /**
4985  * i40e_aq_add_cloud_filters
4986  * @hw: pointer to the hardware structure
4987  * @seid: VSI seid to add cloud filters from
4988  * @filters: Buffer which contains the filters to be added
4989  * @filter_count: number of filters contained in the buffer
4990  *
4991  * Set the cloud filters for a given VSI.  The contents of the
4992  * i40e_aqc_add_remove_cloud_filters_element_data are filled
4993  * in by the caller of the function.
4994  *
4995  **/
4996 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4997         u16 seid,
4998         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4999         u8 filter_count)
5000 {
5001         struct i40e_aq_desc desc;
5002         struct i40e_aqc_add_remove_cloud_filters *cmd =
5003         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5004         u16 buff_len;
5005         enum i40e_status_code status;
5006
5007         i40e_fill_default_direct_cmd_desc(&desc,
5008                                           i40e_aqc_opc_add_cloud_filters);
5009
5010         buff_len = filter_count * sizeof(*filters);
5011         desc.datalen = CPU_TO_LE16(buff_len);
5012         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5013         cmd->num_filters = filter_count;
5014         cmd->seid = CPU_TO_LE16(seid);
5015
5016         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5017
5018         return status;
5019 }
5020
5021 /**
5022  * i40e_aq_remove_cloud_filters
5023  * @hw: pointer to the hardware structure
5024  * @seid: VSI seid to remove cloud filters from
5025  * @filters: Buffer which contains the filters to be removed
5026  * @filter_count: number of filters contained in the buffer
5027  *
5028  * Remove the cloud filters for a given VSI.  The contents of the
5029  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5030  * in by the caller of the function.
5031  *
5032  **/
5033 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5034                 u16 seid,
5035                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5036                 u8 filter_count)
5037 {
5038         struct i40e_aq_desc desc;
5039         struct i40e_aqc_add_remove_cloud_filters *cmd =
5040         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5041         enum i40e_status_code status;
5042         u16 buff_len;
5043
5044         i40e_fill_default_direct_cmd_desc(&desc,
5045                                           i40e_aqc_opc_remove_cloud_filters);
5046
5047         buff_len = filter_count * sizeof(*filters);
5048         desc.datalen = CPU_TO_LE16(buff_len);
5049         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5050         cmd->num_filters = filter_count;
5051         cmd->seid = CPU_TO_LE16(seid);
5052
5053         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5054
5055         return status;
5056 }
5057
5058 /**
5059  * i40e_aq_alternate_write
5060  * @hw: pointer to the hardware structure
5061  * @reg_addr0: address of first dword to be read
5062  * @reg_val0: value to be written under 'reg_addr0'
5063  * @reg_addr1: address of second dword to be read
5064  * @reg_val1: value to be written under 'reg_addr1'
5065  *
5066  * Write one or two dwords to alternate structure. Fields are indicated
5067  * by 'reg_addr0' and 'reg_addr1' register numbers.
5068  *
5069  **/
5070 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5071                                 u32 reg_addr0, u32 reg_val0,
5072                                 u32 reg_addr1, u32 reg_val1)
5073 {
5074         struct i40e_aq_desc desc;
5075         struct i40e_aqc_alternate_write *cmd_resp =
5076                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5077         enum i40e_status_code status;
5078
5079         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5080         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5081         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5082         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5083         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5084
5085         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5086
5087         return status;
5088 }
5089
5090 /**
5091  * i40e_aq_alternate_write_indirect
5092  * @hw: pointer to the hardware structure
5093  * @addr: address of a first register to be modified
5094  * @dw_count: number of alternate structure fields to write
5095  * @buffer: pointer to the command buffer
5096  *
5097  * Write 'dw_count' dwords from 'buffer' to alternate structure
5098  * starting at 'addr'.
5099  *
5100  **/
5101 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5102                                 u32 addr, u32 dw_count, void *buffer)
5103 {
5104         struct i40e_aq_desc desc;
5105         struct i40e_aqc_alternate_ind_write *cmd_resp =
5106                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5107         enum i40e_status_code status;
5108
5109         if (buffer == NULL)
5110                 return I40E_ERR_PARAM;
5111
5112         /* Indirect command */
5113         i40e_fill_default_direct_cmd_desc(&desc,
5114                                          i40e_aqc_opc_alternate_write_indirect);
5115
5116         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5117         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5118         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5119                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5120
5121         cmd_resp->address = CPU_TO_LE32(addr);
5122         cmd_resp->length = CPU_TO_LE32(dw_count);
5123
5124         status = i40e_asq_send_command(hw, &desc, buffer,
5125                                        I40E_LO_DWORD(4*dw_count), NULL);
5126
5127         return status;
5128 }
5129
5130 /**
5131  * i40e_aq_alternate_read
5132  * @hw: pointer to the hardware structure
5133  * @reg_addr0: address of first dword to be read
5134  * @reg_val0: pointer for data read from 'reg_addr0'
5135  * @reg_addr1: address of second dword to be read
5136  * @reg_val1: pointer for data read from 'reg_addr1'
5137  *
5138  * Read one or two dwords from alternate structure. Fields are indicated
5139  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5140  * is not passed then only register at 'reg_addr0' is read.
5141  *
5142  **/
5143 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5144                                 u32 reg_addr0, u32 *reg_val0,
5145                                 u32 reg_addr1, u32 *reg_val1)
5146 {
5147         struct i40e_aq_desc desc;
5148         struct i40e_aqc_alternate_write *cmd_resp =
5149                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5150         enum i40e_status_code status;
5151
5152         if (reg_val0 == NULL)
5153                 return I40E_ERR_PARAM;
5154
5155         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5156         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5157         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5158
5159         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5160
5161         if (status == I40E_SUCCESS) {
5162                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5163
5164                 if (reg_val1 != NULL)
5165                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5166         }
5167
5168         return status;
5169 }
5170
5171 /**
5172  * i40e_aq_alternate_read_indirect
5173  * @hw: pointer to the hardware structure
5174  * @addr: address of the alternate structure field
5175  * @dw_count: number of alternate structure fields to read
5176  * @buffer: pointer to the command buffer
5177  *
5178  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5179  * place them in 'buffer'. The buffer should be allocated by caller.
5180  *
5181  **/
5182 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5183                                 u32 addr, u32 dw_count, void *buffer)
5184 {
5185         struct i40e_aq_desc desc;
5186         struct i40e_aqc_alternate_ind_write *cmd_resp =
5187                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5188         enum i40e_status_code status;
5189
5190         if (buffer == NULL)
5191                 return I40E_ERR_PARAM;
5192
5193         /* Indirect command */
5194         i40e_fill_default_direct_cmd_desc(&desc,
5195                 i40e_aqc_opc_alternate_read_indirect);
5196
5197         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5198         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5199         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5200                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5201
5202         cmd_resp->address = CPU_TO_LE32(addr);
5203         cmd_resp->length = CPU_TO_LE32(dw_count);
5204
5205         status = i40e_asq_send_command(hw, &desc, buffer,
5206                                        I40E_LO_DWORD(4*dw_count), NULL);
5207
5208         return status;
5209 }
5210
5211 /**
5212  *  i40e_aq_alternate_clear
5213  *  @hw: pointer to the HW structure.
5214  *
5215  *  Clear the alternate structures of the port from which the function
5216  *  is called.
5217  *
5218  **/
5219 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5220 {
5221         struct i40e_aq_desc desc;
5222         enum i40e_status_code status;
5223
5224         i40e_fill_default_direct_cmd_desc(&desc,
5225                                           i40e_aqc_opc_alternate_clear_port);
5226
5227         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5228
5229         return status;
5230 }
5231
5232 /**
5233  *  i40e_aq_alternate_write_done
5234  *  @hw: pointer to the HW structure.
5235  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5236  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5237  *
5238  *  Indicates to the FW that alternate structures have been changed.
5239  *
5240  **/
5241 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5242                 u8 bios_mode, bool *reset_needed)
5243 {
5244         struct i40e_aq_desc desc;
5245         struct i40e_aqc_alternate_write_done *cmd =
5246                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5247         enum i40e_status_code status;
5248
5249         if (reset_needed == NULL)
5250                 return I40E_ERR_PARAM;
5251
5252         i40e_fill_default_direct_cmd_desc(&desc,
5253                                           i40e_aqc_opc_alternate_write_done);
5254
5255         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5256
5257         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5258         if (!status && reset_needed)
5259                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5260                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5261
5262         return status;
5263 }
5264
5265 /**
5266  *  i40e_aq_set_oem_mode
5267  *  @hw: pointer to the HW structure.
5268  *  @oem_mode: the OEM mode to be used
5269  *
5270  *  Sets the device to a specific operating mode. Currently the only supported
5271  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5272  *
5273  **/
5274 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5275                 u8 oem_mode)
5276 {
5277         struct i40e_aq_desc desc;
5278         struct i40e_aqc_alternate_write_done *cmd =
5279                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5280         enum i40e_status_code status;
5281
5282         i40e_fill_default_direct_cmd_desc(&desc,
5283                                           i40e_aqc_opc_alternate_set_mode);
5284
5285         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5286
5287         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5288
5289         return status;
5290 }
5291
5292 /**
5293  * i40e_aq_resume_port_tx
5294  * @hw: pointer to the hardware structure
5295  * @cmd_details: pointer to command details structure or NULL
5296  *
5297  * Resume port's Tx traffic
5298  **/
5299 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5300                                 struct i40e_asq_cmd_details *cmd_details)
5301 {
5302         struct i40e_aq_desc desc;
5303         enum i40e_status_code status;
5304
5305         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5306
5307         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5308
5309         return status;
5310 }
5311
5312 /**
5313  * i40e_set_pci_config_data - store PCI bus info
5314  * @hw: pointer to hardware structure
5315  * @link_status: the link status word from PCI config space
5316  *
5317  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5318  **/
5319 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5320 {
5321         hw->bus.type = i40e_bus_type_pci_express;
5322
5323         switch (link_status & I40E_PCI_LINK_WIDTH) {
5324         case I40E_PCI_LINK_WIDTH_1:
5325                 hw->bus.width = i40e_bus_width_pcie_x1;
5326                 break;
5327         case I40E_PCI_LINK_WIDTH_2:
5328                 hw->bus.width = i40e_bus_width_pcie_x2;
5329                 break;
5330         case I40E_PCI_LINK_WIDTH_4:
5331                 hw->bus.width = i40e_bus_width_pcie_x4;
5332                 break;
5333         case I40E_PCI_LINK_WIDTH_8:
5334                 hw->bus.width = i40e_bus_width_pcie_x8;
5335                 break;
5336         default:
5337                 hw->bus.width = i40e_bus_width_unknown;
5338                 break;
5339         }
5340
5341         switch (link_status & I40E_PCI_LINK_SPEED) {
5342         case I40E_PCI_LINK_SPEED_2500:
5343                 hw->bus.speed = i40e_bus_speed_2500;
5344                 break;
5345         case I40E_PCI_LINK_SPEED_5000:
5346                 hw->bus.speed = i40e_bus_speed_5000;
5347                 break;
5348         case I40E_PCI_LINK_SPEED_8000:
5349                 hw->bus.speed = i40e_bus_speed_8000;
5350                 break;
5351         default:
5352                 hw->bus.speed = i40e_bus_speed_unknown;
5353                 break;
5354         }
5355 }
5356
5357 /**
5358  * i40e_aq_debug_dump
5359  * @hw: pointer to the hardware structure
5360  * @cluster_id: specific cluster to dump
5361  * @table_id: table id within cluster
5362  * @start_index: index of line in the block to read
5363  * @buff_size: dump buffer size
5364  * @buff: dump buffer
5365  * @ret_buff_size: actual buffer size returned
5366  * @ret_next_table: next block to read
5367  * @ret_next_index: next index to read
5368  *
5369  * Dump internal FW/HW data for debug purposes.
5370  *
5371  **/
5372 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5373                                 u8 table_id, u32 start_index, u16 buff_size,
5374                                 void *buff, u16 *ret_buff_size,
5375                                 u8 *ret_next_table, u32 *ret_next_index,
5376                                 struct i40e_asq_cmd_details *cmd_details)
5377 {
5378         struct i40e_aq_desc desc;
5379         struct i40e_aqc_debug_dump_internals *cmd =
5380                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5381         struct i40e_aqc_debug_dump_internals *resp =
5382                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5383         enum i40e_status_code status;
5384
5385         if (buff_size == 0 || !buff)
5386                 return I40E_ERR_PARAM;
5387
5388         i40e_fill_default_direct_cmd_desc(&desc,
5389                                           i40e_aqc_opc_debug_dump_internals);
5390         /* Indirect Command */
5391         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5392         if (buff_size > I40E_AQ_LARGE_BUF)
5393                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5394
5395         cmd->cluster_id = cluster_id;
5396         cmd->table_id = table_id;
5397         cmd->idx = CPU_TO_LE32(start_index);
5398
5399         desc.datalen = CPU_TO_LE16(buff_size);
5400
5401         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5402         if (!status) {
5403                 if (ret_buff_size != NULL)
5404                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5405                 if (ret_next_table != NULL)
5406                         *ret_next_table = resp->table_id;
5407                 if (ret_next_index != NULL)
5408                         *ret_next_index = LE32_TO_CPU(resp->idx);
5409         }
5410
5411         return status;
5412 }
5413
5414 /**
5415  * i40e_read_bw_from_alt_ram
5416  * @hw: pointer to the hardware structure
5417  * @max_bw: pointer for max_bw read
5418  * @min_bw: pointer for min_bw read
5419  * @min_valid: pointer for bool that is true if min_bw is a valid value
5420  * @max_valid: pointer for bool that is true if max_bw is a valid value
5421  *
5422  * Read bw from the alternate ram for the given pf
5423  **/
5424 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5425                                         u32 *max_bw, u32 *min_bw,
5426                                         bool *min_valid, bool *max_valid)
5427 {
5428         enum i40e_status_code status;
5429         u32 max_bw_addr, min_bw_addr;
5430
5431         /* Calculate the address of the min/max bw registers */
5432         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5433                 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5434                 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5435         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5436                 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5437                 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5438
5439         /* Read the bandwidths from alt ram */
5440         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5441                                         min_bw_addr, min_bw);
5442
5443         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5444                 *min_valid = true;
5445         else
5446                 *min_valid = false;
5447
5448         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5449                 *max_valid = true;
5450         else
5451                 *max_valid = false;
5452
5453         return status;
5454 }
5455
5456 /**
5457  * i40e_aq_configure_partition_bw
5458  * @hw: pointer to the hardware structure
5459  * @bw_data: Buffer holding valid pfs and bw limits
5460  * @cmd_details: pointer to command details
5461  *
5462  * Configure partitions guaranteed/max bw
5463  **/
5464 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5465                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5466                         struct i40e_asq_cmd_details *cmd_details)
5467 {
5468         enum i40e_status_code status;
5469         struct i40e_aq_desc desc;
5470         u16 bwd_size = sizeof(*bw_data);
5471
5472         i40e_fill_default_direct_cmd_desc(&desc,
5473                                 i40e_aqc_opc_configure_partition_bw);
5474
5475         /* Indirect command */
5476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5478
5479         if (bwd_size > I40E_AQ_LARGE_BUF)
5480                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5481
5482         desc.datalen = CPU_TO_LE16(bwd_size);
5483
5484         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5485
5486         return status;
5487 }
5488 #endif /* PF_DRIVER */
5489 #ifdef VF_DRIVER
5490
5491 /**
5492  * i40e_aq_send_msg_to_pf
5493  * @hw: pointer to the hardware structure
5494  * @v_opcode: opcodes for VF-PF communication
5495  * @v_retval: return error code
5496  * @msg: pointer to the msg buffer
5497  * @msglen: msg length
5498  * @cmd_details: pointer to command details
5499  *
5500  * Send message to PF driver using admin queue. By default, this message
5501  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5502  * completion before returning.
5503  **/
5504 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5505                                 enum i40e_virtchnl_ops v_opcode,
5506                                 enum i40e_status_code v_retval,
5507                                 u8 *msg, u16 msglen,
5508                                 struct i40e_asq_cmd_details *cmd_details)
5509 {
5510         struct i40e_aq_desc desc;
5511         struct i40e_asq_cmd_details details;
5512         enum i40e_status_code status;
5513
5514         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5515         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5516         desc.cookie_high = CPU_TO_LE32(v_opcode);
5517         desc.cookie_low = CPU_TO_LE32(v_retval);
5518         if (msglen) {
5519                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5520                                                 | I40E_AQ_FLAG_RD));
5521                 if (msglen > I40E_AQ_LARGE_BUF)
5522                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5523                 desc.datalen = CPU_TO_LE16(msglen);
5524         }
5525         if (!cmd_details) {
5526                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5527                 details.async = true;
5528                 cmd_details = &details;
5529         }
5530         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5531                                        msglen, cmd_details);
5532         return status;
5533 }
5534
5535 /**
5536  * i40e_vf_parse_hw_config
5537  * @hw: pointer to the hardware structure
5538  * @msg: pointer to the virtual channel VF resource structure
5539  *
5540  * Given a VF resource message from the PF, populate the hw struct
5541  * with appropriate information.
5542  **/
5543 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5544                              struct i40e_virtchnl_vf_resource *msg)
5545 {
5546         struct i40e_virtchnl_vsi_resource *vsi_res;
5547         int i;
5548
5549         vsi_res = &msg->vsi_res[0];
5550
5551         hw->dev_caps.num_vsis = msg->num_vsis;
5552         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5553         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5554         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5555         hw->dev_caps.dcb = msg->vf_offload_flags &
5556                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
5557         hw->dev_caps.fcoe = (msg->vf_offload_flags &
5558                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5559         hw->dev_caps.iwarp = (msg->vf_offload_flags &
5560                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5561         for (i = 0; i < msg->num_vsis; i++) {
5562                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5563                         i40e_memcpy(hw->mac.perm_addr,
5564                                     vsi_res->default_mac_addr,
5565                                     I40E_ETH_LENGTH_OF_ADDRESS,
5566                                     I40E_NONDMA_TO_NONDMA);
5567                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5568                                     I40E_ETH_LENGTH_OF_ADDRESS,
5569                                     I40E_NONDMA_TO_NONDMA);
5570                 }
5571                 vsi_res++;
5572         }
5573 }
5574
5575 /**
5576  * i40e_vf_reset
5577  * @hw: pointer to the hardware structure
5578  *
5579  * Send a VF_RESET message to the PF. Does not wait for response from PF
5580  * as none will be forthcoming. Immediately after calling this function,
5581  * the admin queue should be shut down and (optionally) reinitialized.
5582  **/
5583 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5584 {
5585         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5586                                       I40E_SUCCESS, NULL, 0, NULL);
5587 }
5588 #endif /* VF_DRIVER */