1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* write whatever's left over without overrunning the buffer */
352 memset(d_buf, 0, sizeof(d_buf));
353 j += sprintf(d_buf, "\t0x%04X ", i);
355 j += sprintf(&d_buf[j], " %02X", buf[i++]);
356 i40e_debug(hw, mask, "%s\n", d_buf);
362 * i40e_check_asq_alive
363 * @hw: pointer to the hw struct
365 * Returns true if Queue is enabled else false.
367 bool i40e_check_asq_alive(struct i40e_hw *hw)
370 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
376 * i40e_aq_queue_shutdown
377 * @hw: pointer to the hw struct
378 * @unloading: is the driver unloading itself
380 * Tell the Firmware that we're shutting down the AdminQ and whether
381 * or not the driver is unloading as well.
383 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
386 struct i40e_aq_desc desc;
387 struct i40e_aqc_queue_shutdown *cmd =
388 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
389 enum i40e_status_code status;
391 i40e_fill_default_direct_cmd_desc(&desc,
392 i40e_aqc_opc_queue_shutdown);
395 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
396 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
401 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
402 * hardware to a bit-field that can be used by SW to more easily determine the
405 * Macros are used to shorten the table lines and make this table human
408 * We store the PTYPE in the top byte of the bit field - this is just so that
409 * we can check that the table doesn't have a row missing, as the index into
410 * the table should be the PTYPE.
414 * IF NOT i40e_ptype_lookup[ptype].known
417 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
418 * Use the rest of the fields to look at the tunnels, inner protocols, etc
420 * Use the enum i40e_rx_l2_ptype to decode the packet type
424 /* macro to make the table lines short */
425 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
428 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
429 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
430 I40E_RX_PTYPE_##OUTER_FRAG, \
431 I40E_RX_PTYPE_TUNNEL_##T, \
432 I40E_RX_PTYPE_TUNNEL_END_##TE, \
433 I40E_RX_PTYPE_##TEF, \
434 I40E_RX_PTYPE_INNER_PROT_##I, \
435 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
437 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
438 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
440 /* shorter macros makes the table fit but are terse */
441 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
442 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
443 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
445 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
446 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
447 /* L2 Packet types */
448 I40E_PTT_UNUSED_ENTRY(0),
449 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
450 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
451 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
452 I40E_PTT_UNUSED_ENTRY(4),
453 I40E_PTT_UNUSED_ENTRY(5),
454 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
455 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
456 I40E_PTT_UNUSED_ENTRY(8),
457 I40E_PTT_UNUSED_ENTRY(9),
458 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
459 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
460 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
461 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
462 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
463 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
464 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
465 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
466 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
467 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
468 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
469 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
471 /* Non Tunneled IPv4 */
472 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
473 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
474 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
475 I40E_PTT_UNUSED_ENTRY(25),
476 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
477 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
478 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
481 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
482 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
483 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
484 I40E_PTT_UNUSED_ENTRY(32),
485 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
486 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
487 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
490 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
491 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
492 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
493 I40E_PTT_UNUSED_ENTRY(39),
494 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
495 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
496 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
498 /* IPv4 --> GRE/NAT */
499 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
501 /* IPv4 --> GRE/NAT --> IPv4 */
502 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
503 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
504 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
505 I40E_PTT_UNUSED_ENTRY(47),
506 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
507 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
508 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
510 /* IPv4 --> GRE/NAT --> IPv6 */
511 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
512 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
513 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
514 I40E_PTT_UNUSED_ENTRY(54),
515 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
516 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
517 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
519 /* IPv4 --> GRE/NAT --> MAC */
520 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
522 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
523 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
524 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
525 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
526 I40E_PTT_UNUSED_ENTRY(62),
527 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
528 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
529 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
531 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
532 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
533 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
534 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
535 I40E_PTT_UNUSED_ENTRY(69),
536 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
537 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
538 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
540 /* IPv4 --> GRE/NAT --> MAC/VLAN */
541 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
543 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
544 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
545 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
546 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
547 I40E_PTT_UNUSED_ENTRY(77),
548 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
549 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
550 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
552 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
553 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
554 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
555 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
556 I40E_PTT_UNUSED_ENTRY(84),
557 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
558 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
559 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
561 /* Non Tunneled IPv6 */
562 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
563 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
564 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
565 I40E_PTT_UNUSED_ENTRY(91),
566 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
567 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
568 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
571 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
572 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
573 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
574 I40E_PTT_UNUSED_ENTRY(98),
575 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
576 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
577 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
580 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
581 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
582 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
583 I40E_PTT_UNUSED_ENTRY(105),
584 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
585 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
586 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
588 /* IPv6 --> GRE/NAT */
589 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
591 /* IPv6 --> GRE/NAT -> IPv4 */
592 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
593 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
594 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
595 I40E_PTT_UNUSED_ENTRY(113),
596 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
597 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
598 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
600 /* IPv6 --> GRE/NAT -> IPv6 */
601 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
602 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
603 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
604 I40E_PTT_UNUSED_ENTRY(120),
605 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
606 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
607 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
609 /* IPv6 --> GRE/NAT -> MAC */
610 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
612 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
613 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
614 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
615 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
616 I40E_PTT_UNUSED_ENTRY(128),
617 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
618 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
619 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
621 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
622 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
623 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
624 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
625 I40E_PTT_UNUSED_ENTRY(135),
626 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
627 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
628 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
630 /* IPv6 --> GRE/NAT -> MAC/VLAN */
631 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
633 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
634 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
635 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
636 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
637 I40E_PTT_UNUSED_ENTRY(143),
638 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
639 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
640 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
642 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
643 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
644 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
645 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
646 I40E_PTT_UNUSED_ENTRY(150),
647 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
648 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
649 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
652 I40E_PTT_UNUSED_ENTRY(154),
653 I40E_PTT_UNUSED_ENTRY(155),
654 I40E_PTT_UNUSED_ENTRY(156),
655 I40E_PTT_UNUSED_ENTRY(157),
656 I40E_PTT_UNUSED_ENTRY(158),
657 I40E_PTT_UNUSED_ENTRY(159),
659 I40E_PTT_UNUSED_ENTRY(160),
660 I40E_PTT_UNUSED_ENTRY(161),
661 I40E_PTT_UNUSED_ENTRY(162),
662 I40E_PTT_UNUSED_ENTRY(163),
663 I40E_PTT_UNUSED_ENTRY(164),
664 I40E_PTT_UNUSED_ENTRY(165),
665 I40E_PTT_UNUSED_ENTRY(166),
666 I40E_PTT_UNUSED_ENTRY(167),
667 I40E_PTT_UNUSED_ENTRY(168),
668 I40E_PTT_UNUSED_ENTRY(169),
670 I40E_PTT_UNUSED_ENTRY(170),
671 I40E_PTT_UNUSED_ENTRY(171),
672 I40E_PTT_UNUSED_ENTRY(172),
673 I40E_PTT_UNUSED_ENTRY(173),
674 I40E_PTT_UNUSED_ENTRY(174),
675 I40E_PTT_UNUSED_ENTRY(175),
676 I40E_PTT_UNUSED_ENTRY(176),
677 I40E_PTT_UNUSED_ENTRY(177),
678 I40E_PTT_UNUSED_ENTRY(178),
679 I40E_PTT_UNUSED_ENTRY(179),
681 I40E_PTT_UNUSED_ENTRY(180),
682 I40E_PTT_UNUSED_ENTRY(181),
683 I40E_PTT_UNUSED_ENTRY(182),
684 I40E_PTT_UNUSED_ENTRY(183),
685 I40E_PTT_UNUSED_ENTRY(184),
686 I40E_PTT_UNUSED_ENTRY(185),
687 I40E_PTT_UNUSED_ENTRY(186),
688 I40E_PTT_UNUSED_ENTRY(187),
689 I40E_PTT_UNUSED_ENTRY(188),
690 I40E_PTT_UNUSED_ENTRY(189),
692 I40E_PTT_UNUSED_ENTRY(190),
693 I40E_PTT_UNUSED_ENTRY(191),
694 I40E_PTT_UNUSED_ENTRY(192),
695 I40E_PTT_UNUSED_ENTRY(193),
696 I40E_PTT_UNUSED_ENTRY(194),
697 I40E_PTT_UNUSED_ENTRY(195),
698 I40E_PTT_UNUSED_ENTRY(196),
699 I40E_PTT_UNUSED_ENTRY(197),
700 I40E_PTT_UNUSED_ENTRY(198),
701 I40E_PTT_UNUSED_ENTRY(199),
703 I40E_PTT_UNUSED_ENTRY(200),
704 I40E_PTT_UNUSED_ENTRY(201),
705 I40E_PTT_UNUSED_ENTRY(202),
706 I40E_PTT_UNUSED_ENTRY(203),
707 I40E_PTT_UNUSED_ENTRY(204),
708 I40E_PTT_UNUSED_ENTRY(205),
709 I40E_PTT_UNUSED_ENTRY(206),
710 I40E_PTT_UNUSED_ENTRY(207),
711 I40E_PTT_UNUSED_ENTRY(208),
712 I40E_PTT_UNUSED_ENTRY(209),
714 I40E_PTT_UNUSED_ENTRY(210),
715 I40E_PTT_UNUSED_ENTRY(211),
716 I40E_PTT_UNUSED_ENTRY(212),
717 I40E_PTT_UNUSED_ENTRY(213),
718 I40E_PTT_UNUSED_ENTRY(214),
719 I40E_PTT_UNUSED_ENTRY(215),
720 I40E_PTT_UNUSED_ENTRY(216),
721 I40E_PTT_UNUSED_ENTRY(217),
722 I40E_PTT_UNUSED_ENTRY(218),
723 I40E_PTT_UNUSED_ENTRY(219),
725 I40E_PTT_UNUSED_ENTRY(220),
726 I40E_PTT_UNUSED_ENTRY(221),
727 I40E_PTT_UNUSED_ENTRY(222),
728 I40E_PTT_UNUSED_ENTRY(223),
729 I40E_PTT_UNUSED_ENTRY(224),
730 I40E_PTT_UNUSED_ENTRY(225),
731 I40E_PTT_UNUSED_ENTRY(226),
732 I40E_PTT_UNUSED_ENTRY(227),
733 I40E_PTT_UNUSED_ENTRY(228),
734 I40E_PTT_UNUSED_ENTRY(229),
736 I40E_PTT_UNUSED_ENTRY(230),
737 I40E_PTT_UNUSED_ENTRY(231),
738 I40E_PTT_UNUSED_ENTRY(232),
739 I40E_PTT_UNUSED_ENTRY(233),
740 I40E_PTT_UNUSED_ENTRY(234),
741 I40E_PTT_UNUSED_ENTRY(235),
742 I40E_PTT_UNUSED_ENTRY(236),
743 I40E_PTT_UNUSED_ENTRY(237),
744 I40E_PTT_UNUSED_ENTRY(238),
745 I40E_PTT_UNUSED_ENTRY(239),
747 I40E_PTT_UNUSED_ENTRY(240),
748 I40E_PTT_UNUSED_ENTRY(241),
749 I40E_PTT_UNUSED_ENTRY(242),
750 I40E_PTT_UNUSED_ENTRY(243),
751 I40E_PTT_UNUSED_ENTRY(244),
752 I40E_PTT_UNUSED_ENTRY(245),
753 I40E_PTT_UNUSED_ENTRY(246),
754 I40E_PTT_UNUSED_ENTRY(247),
755 I40E_PTT_UNUSED_ENTRY(248),
756 I40E_PTT_UNUSED_ENTRY(249),
758 I40E_PTT_UNUSED_ENTRY(250),
759 I40E_PTT_UNUSED_ENTRY(251),
760 I40E_PTT_UNUSED_ENTRY(252),
761 I40E_PTT_UNUSED_ENTRY(253),
762 I40E_PTT_UNUSED_ENTRY(254),
763 I40E_PTT_UNUSED_ENTRY(255)
768 * i40e_validate_mac_addr - Validate unicast MAC address
769 * @mac_addr: pointer to MAC address
771 * Tests a MAC address to ensure it is a valid Individual Address
773 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
775 enum i40e_status_code status = I40E_SUCCESS;
777 DEBUGFUNC("i40e_validate_mac_addr");
779 /* Broadcast addresses ARE multicast addresses
780 * Make sure it is not a multicast address
781 * Reject the zero address
783 if (I40E_IS_MULTICAST(mac_addr) ||
784 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
785 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
786 status = I40E_ERR_INVALID_MAC_ADDR;
793 * i40e_init_shared_code - Initialize the shared code
794 * @hw: pointer to hardware structure
796 * This assigns the MAC type and PHY code and inits the NVM.
797 * Does not touch the hardware. This function must be called prior to any
798 * other function in the shared code. The i40e_hw structure should be
799 * memset to 0 prior to calling this function. The following fields in
800 * hw structure should be filled in prior to calling this function:
801 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
802 * subsystem_vendor_id, and revision_id
804 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
806 enum i40e_status_code status = I40E_SUCCESS;
807 u32 port, ari, func_rid;
809 DEBUGFUNC("i40e_init_shared_code");
811 i40e_set_mac_type(hw);
813 switch (hw->mac.type) {
817 return I40E_ERR_DEVICE_NOT_SUPPORTED;
820 hw->phy.get_link_info = true;
822 /* Determine port number and PF number*/
823 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
824 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
826 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
827 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
828 func_rid = rd32(hw, I40E_PF_FUNC_RID);
830 hw->pf_id = (u8)(func_rid & 0xff);
832 hw->pf_id = (u8)(func_rid & 0x7);
834 status = i40e_init_nvm(hw);
839 * i40e_aq_mac_address_read - Retrieve the MAC addresses
840 * @hw: pointer to the hw struct
841 * @flags: a return indicator of what addresses were added to the addr store
842 * @addrs: the requestor's mac addr store
843 * @cmd_details: pointer to command details structure or NULL
845 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
847 struct i40e_aqc_mac_address_read_data *addrs,
848 struct i40e_asq_cmd_details *cmd_details)
850 struct i40e_aq_desc desc;
851 struct i40e_aqc_mac_address_read *cmd_data =
852 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
853 enum i40e_status_code status;
855 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
856 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
858 status = i40e_asq_send_command(hw, &desc, addrs,
859 sizeof(*addrs), cmd_details);
860 *flags = LE16_TO_CPU(cmd_data->command_flags);
866 * i40e_aq_mac_address_write - Change the MAC addresses
867 * @hw: pointer to the hw struct
868 * @flags: indicates which MAC to be written
869 * @mac_addr: address to write
870 * @cmd_details: pointer to command details structure or NULL
872 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
873 u16 flags, u8 *mac_addr,
874 struct i40e_asq_cmd_details *cmd_details)
876 struct i40e_aq_desc desc;
877 struct i40e_aqc_mac_address_write *cmd_data =
878 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
879 enum i40e_status_code status;
881 i40e_fill_default_direct_cmd_desc(&desc,
882 i40e_aqc_opc_mac_address_write);
883 cmd_data->command_flags = CPU_TO_LE16(flags);
884 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
885 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
886 ((u32)mac_addr[3] << 16) |
887 ((u32)mac_addr[4] << 8) |
890 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
896 * i40e_get_mac_addr - get MAC address
897 * @hw: pointer to the HW structure
898 * @mac_addr: pointer to MAC address
900 * Reads the adapter's MAC address from register
902 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
904 struct i40e_aqc_mac_address_read_data addrs;
905 enum i40e_status_code status;
908 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
910 if (flags & I40E_AQC_LAN_ADDR_VALID)
911 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
917 * i40e_get_port_mac_addr - get Port MAC address
918 * @hw: pointer to the HW structure
919 * @mac_addr: pointer to Port MAC address
921 * Reads the adapter's Port MAC address
923 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
925 struct i40e_aqc_mac_address_read_data addrs;
926 enum i40e_status_code status;
929 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
933 if (flags & I40E_AQC_PORT_ADDR_VALID)
934 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
936 status = I40E_ERR_INVALID_MAC_ADDR;
942 * i40e_pre_tx_queue_cfg - pre tx queue configure
943 * @hw: pointer to the HW structure
944 * @queue: target pf queue index
945 * @enable: state change request
947 * Handles hw requirement to indicate intention to enable
948 * or disable target queue.
950 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
952 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
956 if (abs_queue_idx >= 128) {
957 reg_block = abs_queue_idx / 128;
958 abs_queue_idx %= 128;
961 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
962 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
963 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
966 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
968 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
970 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
974 * i40e_read_pba_string - Reads part number string from EEPROM
975 * @hw: pointer to hardware structure
976 * @pba_num: stores the part number string from the EEPROM
977 * @pba_num_size: part number string buffer length
979 * Reads the part number string from the EEPROM.
981 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
984 enum i40e_status_code status = I40E_SUCCESS;
990 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
991 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
992 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
996 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
997 if (status != I40E_SUCCESS) {
998 DEBUGOUT("Failed to read PBA Block pointer.\n");
1002 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1003 if (status != I40E_SUCCESS) {
1004 DEBUGOUT("Failed to read PBA Block size.\n");
1008 /* Subtract one to get PBA word count (PBA Size word is included in
1012 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1013 DEBUGOUT("Buffer to small for PBA data.\n");
1014 return I40E_ERR_PARAM;
1017 for (i = 0; i < pba_size; i++) {
1018 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1019 if (status != I40E_SUCCESS) {
1020 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1024 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1025 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1027 pba_num[(pba_size * 2)] = '\0';
1033 * i40e_get_media_type - Gets media type
1034 * @hw: pointer to the hardware structure
1036 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1038 enum i40e_media_type media;
1040 switch (hw->phy.link_info.phy_type) {
1041 case I40E_PHY_TYPE_10GBASE_SR:
1042 case I40E_PHY_TYPE_10GBASE_LR:
1043 case I40E_PHY_TYPE_1000BASE_SX:
1044 case I40E_PHY_TYPE_1000BASE_LX:
1045 case I40E_PHY_TYPE_40GBASE_SR4:
1046 case I40E_PHY_TYPE_40GBASE_LR4:
1047 media = I40E_MEDIA_TYPE_FIBER;
1049 case I40E_PHY_TYPE_100BASE_TX:
1050 case I40E_PHY_TYPE_1000BASE_T:
1051 case I40E_PHY_TYPE_10GBASE_T:
1052 media = I40E_MEDIA_TYPE_BASET;
1054 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1055 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1056 case I40E_PHY_TYPE_10GBASE_CR1:
1057 case I40E_PHY_TYPE_40GBASE_CR4:
1058 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1059 case I40E_PHY_TYPE_40GBASE_AOC:
1060 case I40E_PHY_TYPE_10GBASE_AOC:
1061 media = I40E_MEDIA_TYPE_DA;
1063 case I40E_PHY_TYPE_1000BASE_KX:
1064 case I40E_PHY_TYPE_10GBASE_KX4:
1065 case I40E_PHY_TYPE_10GBASE_KR:
1066 case I40E_PHY_TYPE_40GBASE_KR4:
1067 case I40E_PHY_TYPE_20GBASE_KR2:
1068 media = I40E_MEDIA_TYPE_BACKPLANE;
1070 case I40E_PHY_TYPE_SGMII:
1071 case I40E_PHY_TYPE_XAUI:
1072 case I40E_PHY_TYPE_XFI:
1073 case I40E_PHY_TYPE_XLAUI:
1074 case I40E_PHY_TYPE_XLPPI:
1076 media = I40E_MEDIA_TYPE_UNKNOWN;
1083 #define I40E_PF_RESET_WAIT_COUNT 110
1085 * i40e_pf_reset - Reset the PF
1086 * @hw: pointer to the hardware structure
1088 * Assuming someone else has triggered a global reset,
1089 * assure the global reset is complete and then reset the PF
1091 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1098 /* Poll for Global Reset steady state in case of recent GRST.
1099 * The grst delay value is in 100ms units, and we'll wait a
1100 * couple counts longer to be sure we don't just miss the end.
1102 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1103 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1104 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1105 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1106 reg = rd32(hw, I40E_GLGEN_RSTAT);
1107 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1109 i40e_msec_delay(100);
1111 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1112 DEBUGOUT("Global reset polling failed to complete.\n");
1113 return I40E_ERR_RESET_FAILED;
1116 /* Now Wait for the FW to be ready */
1117 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1118 reg = rd32(hw, I40E_GLNVM_ULD);
1119 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1120 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1121 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1122 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1123 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1126 i40e_msec_delay(10);
1128 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1129 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1130 DEBUGOUT("wait for FW Reset complete timedout\n");
1131 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1132 return I40E_ERR_RESET_FAILED;
1135 /* If there was a Global Reset in progress when we got here,
1136 * we don't need to do the PF Reset
1139 reg = rd32(hw, I40E_PFGEN_CTRL);
1140 wr32(hw, I40E_PFGEN_CTRL,
1141 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1142 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1143 reg = rd32(hw, I40E_PFGEN_CTRL);
1144 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1148 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1149 DEBUGOUT("PF reset polling failed to complete.\n");
1150 return I40E_ERR_RESET_FAILED;
1154 i40e_clear_pxe_mode(hw);
1157 return I40E_SUCCESS;
1161 * i40e_clear_hw - clear out any left over hw state
1162 * @hw: pointer to the hw struct
1164 * Clear queues and interrupts, typically called at init time,
1165 * but after the capabilities have been found so we know how many
1166 * queues and msix vectors have been allocated.
1168 void i40e_clear_hw(struct i40e_hw *hw)
1170 u32 num_queues, base_queue;
1178 /* get number of interrupts, queues, and vfs */
1179 val = rd32(hw, I40E_GLPCI_CNF2);
1180 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1181 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1182 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1183 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1185 val = rd32(hw, I40E_PFLAN_QALLOC);
1186 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1187 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1188 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1189 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1190 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1191 num_queues = (j - base_queue) + 1;
1195 val = rd32(hw, I40E_PF_VT_PFALLOC);
1196 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1197 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1198 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1199 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1200 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1201 num_vfs = (j - i) + 1;
1205 /* stop all the interrupts */
1206 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1207 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1208 for (i = 0; i < num_pf_int - 2; i++)
1209 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1211 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1212 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1213 wr32(hw, I40E_PFINT_LNKLST0, val);
1214 for (i = 0; i < num_pf_int - 2; i++)
1215 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1216 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1217 for (i = 0; i < num_vfs; i++)
1218 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1219 for (i = 0; i < num_vf_int - 2; i++)
1220 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1222 /* warn the HW of the coming Tx disables */
1223 for (i = 0; i < num_queues; i++) {
1224 u32 abs_queue_idx = base_queue + i;
1227 if (abs_queue_idx >= 128) {
1228 reg_block = abs_queue_idx / 128;
1229 abs_queue_idx %= 128;
1232 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1233 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1234 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1235 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1237 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1239 i40e_usec_delay(400);
1241 /* stop all the queues */
1242 for (i = 0; i < num_queues; i++) {
1243 wr32(hw, I40E_QINT_TQCTL(i), 0);
1244 wr32(hw, I40E_QTX_ENA(i), 0);
1245 wr32(hw, I40E_QINT_RQCTL(i), 0);
1246 wr32(hw, I40E_QRX_ENA(i), 0);
1249 /* short wait for all queue disables to settle */
1250 i40e_usec_delay(50);
1254 * i40e_clear_pxe_mode - clear pxe operations mode
1255 * @hw: pointer to the hw struct
1257 * Make sure all PXE mode settings are cleared, including things
1258 * like descriptor fetch/write-back mode.
1260 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1262 if (i40e_check_asq_alive(hw))
1263 i40e_aq_clear_pxe_mode(hw, NULL);
1267 * i40e_led_is_mine - helper to find matching led
1268 * @hw: pointer to the hw struct
1269 * @idx: index into GPIO registers
1271 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1273 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1278 if (!hw->func_caps.led[idx])
1281 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1282 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1283 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1285 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1286 * if it is not our port then ignore
1288 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1295 #define I40E_COMBINED_ACTIVITY 0xA
1296 #define I40E_FILTER_ACTIVITY 0xE
1297 #define I40E_LINK_ACTIVITY 0xC
1298 #define I40E_MAC_ACTIVITY 0xD
1299 #define I40E_LED0 22
1302 * i40e_led_get - return current on/off mode
1303 * @hw: pointer to the hw struct
1305 * The value returned is the 'mode' field as defined in the
1306 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1307 * values are variations of possible behaviors relating to
1308 * blink, link, and wire.
1310 u32 i40e_led_get(struct i40e_hw *hw)
1312 u32 current_mode = 0;
1316 /* as per the documentation GPIO 22-29 are the LED
1317 * GPIO pins named LED0..LED7
1319 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1320 u32 gpio_val = i40e_led_is_mine(hw, i);
1325 /* ignore gpio LED src mode entries related to the activity LEDs */
1326 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1327 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1328 switch (current_mode) {
1329 case I40E_COMBINED_ACTIVITY:
1330 case I40E_FILTER_ACTIVITY:
1331 case I40E_MAC_ACTIVITY:
1337 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1338 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1346 * i40e_led_set - set new on/off mode
1347 * @hw: pointer to the hw struct
1348 * @mode: 0=off, 0xf=on (else see manual for mode details)
1349 * @blink: true if the LED should blink when on, false if steady
1351 * if this function is used to turn on the blink it should
1352 * be used to disable the blink when restoring the original state.
1354 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1356 u32 current_mode = 0;
1359 if (mode & 0xfffffff0)
1360 DEBUGOUT1("invalid mode passed in %X\n", mode);
1362 /* as per the documentation GPIO 22-29 are the LED
1363 * GPIO pins named LED0..LED7
1365 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1366 u32 gpio_val = i40e_led_is_mine(hw, i);
1371 /* ignore gpio LED src mode entries related to the activity LEDs */
1372 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1373 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1374 switch (current_mode) {
1375 case I40E_COMBINED_ACTIVITY:
1376 case I40E_FILTER_ACTIVITY:
1377 case I40E_MAC_ACTIVITY:
1383 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1384 /* this & is a bit of paranoia, but serves as a range check */
1385 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1386 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1388 if (mode == I40E_LINK_ACTIVITY)
1392 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1394 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1396 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1401 /* Admin command wrappers */
1404 * i40e_aq_get_phy_capabilities
1405 * @hw: pointer to the hw struct
1406 * @abilities: structure for PHY capabilities to be filled
1407 * @qualified_modules: report Qualified Modules
1408 * @report_init: report init capabilities (active are default)
1409 * @cmd_details: pointer to command details structure or NULL
1411 * Returns the various PHY abilities supported on the Port.
1413 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1414 bool qualified_modules, bool report_init,
1415 struct i40e_aq_get_phy_abilities_resp *abilities,
1416 struct i40e_asq_cmd_details *cmd_details)
1418 struct i40e_aq_desc desc;
1419 enum i40e_status_code status;
1420 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1423 return I40E_ERR_PARAM;
1425 i40e_fill_default_direct_cmd_desc(&desc,
1426 i40e_aqc_opc_get_phy_abilities);
1428 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1429 if (abilities_size > I40E_AQ_LARGE_BUF)
1430 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1432 if (qualified_modules)
1433 desc.params.external.param0 |=
1434 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1437 desc.params.external.param0 |=
1438 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1440 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1443 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1444 status = I40E_ERR_UNKNOWN_PHY;
1450 * i40e_aq_set_phy_config
1451 * @hw: pointer to the hw struct
1452 * @config: structure with PHY configuration to be set
1453 * @cmd_details: pointer to command details structure or NULL
1455 * Set the various PHY configuration parameters
1456 * supported on the Port.One or more of the Set PHY config parameters may be
1457 * ignored in an MFP mode as the PF may not have the privilege to set some
1458 * of the PHY Config parameters. This status will be indicated by the
1461 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1462 struct i40e_aq_set_phy_config *config,
1463 struct i40e_asq_cmd_details *cmd_details)
1465 struct i40e_aq_desc desc;
1466 struct i40e_aq_set_phy_config *cmd =
1467 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1468 enum i40e_status_code status;
1471 return I40E_ERR_PARAM;
1473 i40e_fill_default_direct_cmd_desc(&desc,
1474 i40e_aqc_opc_set_phy_config);
1478 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1485 * @hw: pointer to the hw struct
1487 * Set the requested flow control mode using set_phy_config.
1489 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1490 bool atomic_restart)
1492 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1493 struct i40e_aq_get_phy_abilities_resp abilities;
1494 struct i40e_aq_set_phy_config config;
1495 enum i40e_status_code status;
1496 u8 pause_mask = 0x0;
1502 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1503 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1505 case I40E_FC_RX_PAUSE:
1506 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1508 case I40E_FC_TX_PAUSE:
1509 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1515 /* Get the current phy config */
1516 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1519 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1523 memset(&config, 0, sizeof(config));
1524 /* clear the old pause settings */
1525 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1526 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1527 /* set the new abilities */
1528 config.abilities |= pause_mask;
1529 /* If the abilities have changed, then set the new config */
1530 if (config.abilities != abilities.abilities) {
1531 /* Auto restart link so settings take effect */
1533 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1534 /* Copy over all the old settings */
1535 config.phy_type = abilities.phy_type;
1536 config.link_speed = abilities.link_speed;
1537 config.eee_capability = abilities.eee_capability;
1538 config.eeer = abilities.eeer_val;
1539 config.low_power_ctrl = abilities.d3_lpan;
1540 status = i40e_aq_set_phy_config(hw, &config, NULL);
1543 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1545 /* Update the link info */
1546 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1548 /* Wait a little bit (on 40G cards it sometimes takes a really
1549 * long time for link to come back from the atomic reset)
1552 i40e_msec_delay(1000);
1553 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1556 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1562 * i40e_aq_set_mac_config
1563 * @hw: pointer to the hw struct
1564 * @max_frame_size: Maximum Frame Size to be supported by the port
1565 * @crc_en: Tell HW to append a CRC to outgoing frames
1566 * @pacing: Pacing configurations
1567 * @cmd_details: pointer to command details structure or NULL
1569 * Configure MAC settings for frame size, jumbo frame support and the
1570 * addition of a CRC by the hardware.
1572 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1574 bool crc_en, u16 pacing,
1575 struct i40e_asq_cmd_details *cmd_details)
1577 struct i40e_aq_desc desc;
1578 struct i40e_aq_set_mac_config *cmd =
1579 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1580 enum i40e_status_code status;
1582 if (max_frame_size == 0)
1583 return I40E_ERR_PARAM;
1585 i40e_fill_default_direct_cmd_desc(&desc,
1586 i40e_aqc_opc_set_mac_config);
1588 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1589 cmd->params = ((u8)pacing & 0x0F) << 3;
1591 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1593 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1599 * i40e_aq_clear_pxe_mode
1600 * @hw: pointer to the hw struct
1601 * @cmd_details: pointer to command details structure or NULL
1603 * Tell the firmware that the driver is taking over from PXE
1605 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1606 struct i40e_asq_cmd_details *cmd_details)
1608 enum i40e_status_code status;
1609 struct i40e_aq_desc desc;
1610 struct i40e_aqc_clear_pxe *cmd =
1611 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1613 i40e_fill_default_direct_cmd_desc(&desc,
1614 i40e_aqc_opc_clear_pxe_mode);
1618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1620 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1626 * i40e_aq_set_link_restart_an
1627 * @hw: pointer to the hw struct
1628 * @enable_link: if true: enable link, if false: disable link
1629 * @cmd_details: pointer to command details structure or NULL
1631 * Sets up the link and restarts the Auto-Negotiation over the link.
1633 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1634 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1636 struct i40e_aq_desc desc;
1637 struct i40e_aqc_set_link_restart_an *cmd =
1638 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1639 enum i40e_status_code status;
1641 i40e_fill_default_direct_cmd_desc(&desc,
1642 i40e_aqc_opc_set_link_restart_an);
1644 cmd->command = I40E_AQ_PHY_RESTART_AN;
1646 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1648 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1656 * i40e_aq_get_link_info
1657 * @hw: pointer to the hw struct
1658 * @enable_lse: enable/disable LinkStatusEvent reporting
1659 * @link: pointer to link status structure - optional
1660 * @cmd_details: pointer to command details structure or NULL
1662 * Returns the link status of the adapter.
1664 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1665 bool enable_lse, struct i40e_link_status *link,
1666 struct i40e_asq_cmd_details *cmd_details)
1668 struct i40e_aq_desc desc;
1669 struct i40e_aqc_get_link_status *resp =
1670 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1671 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1672 enum i40e_status_code status;
1673 bool tx_pause, rx_pause;
1676 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1679 command_flags = I40E_AQ_LSE_ENABLE;
1681 command_flags = I40E_AQ_LSE_DISABLE;
1682 resp->command_flags = CPU_TO_LE16(command_flags);
1684 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1686 if (status != I40E_SUCCESS)
1687 goto aq_get_link_info_exit;
1689 /* save off old link status information */
1690 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1691 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1693 /* update link status */
1694 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1695 hw->phy.media_type = i40e_get_media_type(hw);
1696 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1697 hw_link_info->link_info = resp->link_info;
1698 hw_link_info->an_info = resp->an_info;
1699 hw_link_info->ext_info = resp->ext_info;
1700 hw_link_info->loopback = resp->loopback;
1701 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1702 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1704 /* update fc info */
1705 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1706 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1707 if (tx_pause & rx_pause)
1708 hw->fc.current_mode = I40E_FC_FULL;
1710 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1712 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1714 hw->fc.current_mode = I40E_FC_NONE;
1716 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1717 hw_link_info->crc_enable = true;
1719 hw_link_info->crc_enable = false;
1721 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1722 hw_link_info->lse_enable = true;
1724 hw_link_info->lse_enable = false;
1726 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1727 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1728 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1730 /* save link status information */
1732 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1733 I40E_NONDMA_TO_NONDMA);
1735 /* flag cleared so helper functions don't call AQ again */
1736 hw->phy.get_link_info = false;
1738 aq_get_link_info_exit:
1744 * i40e_aq_set_phy_int_mask
1745 * @hw: pointer to the hw struct
1746 * @mask: interrupt mask to be set
1747 * @cmd_details: pointer to command details structure or NULL
1749 * Set link interrupt mask.
1751 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1753 struct i40e_asq_cmd_details *cmd_details)
1755 struct i40e_aq_desc desc;
1756 struct i40e_aqc_set_phy_int_mask *cmd =
1757 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1758 enum i40e_status_code status;
1760 i40e_fill_default_direct_cmd_desc(&desc,
1761 i40e_aqc_opc_set_phy_int_mask);
1763 cmd->event_mask = CPU_TO_LE16(mask);
1765 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1771 * i40e_aq_get_local_advt_reg
1772 * @hw: pointer to the hw struct
1773 * @advt_reg: local AN advertisement register value
1774 * @cmd_details: pointer to command details structure or NULL
1776 * Get the Local AN advertisement register value.
1778 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1780 struct i40e_asq_cmd_details *cmd_details)
1782 struct i40e_aq_desc desc;
1783 struct i40e_aqc_an_advt_reg *resp =
1784 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1785 enum i40e_status_code status;
1787 i40e_fill_default_direct_cmd_desc(&desc,
1788 i40e_aqc_opc_get_local_advt_reg);
1790 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1792 if (status != I40E_SUCCESS)
1793 goto aq_get_local_advt_reg_exit;
1795 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1796 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1798 aq_get_local_advt_reg_exit:
1803 * i40e_aq_set_local_advt_reg
1804 * @hw: pointer to the hw struct
1805 * @advt_reg: local AN advertisement register value
1806 * @cmd_details: pointer to command details structure or NULL
1808 * Get the Local AN advertisement register value.
1810 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1812 struct i40e_asq_cmd_details *cmd_details)
1814 struct i40e_aq_desc desc;
1815 struct i40e_aqc_an_advt_reg *cmd =
1816 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1817 enum i40e_status_code status;
1819 i40e_fill_default_direct_cmd_desc(&desc,
1820 i40e_aqc_opc_get_local_advt_reg);
1822 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1823 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1825 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1831 * i40e_aq_get_partner_advt
1832 * @hw: pointer to the hw struct
1833 * @advt_reg: AN partner advertisement register value
1834 * @cmd_details: pointer to command details structure or NULL
1836 * Get the link partner AN advertisement register value.
1838 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1840 struct i40e_asq_cmd_details *cmd_details)
1842 struct i40e_aq_desc desc;
1843 struct i40e_aqc_an_advt_reg *resp =
1844 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1845 enum i40e_status_code status;
1847 i40e_fill_default_direct_cmd_desc(&desc,
1848 i40e_aqc_opc_get_partner_advt);
1850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1852 if (status != I40E_SUCCESS)
1853 goto aq_get_partner_advt_exit;
1855 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1856 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1858 aq_get_partner_advt_exit:
1863 * i40e_aq_set_lb_modes
1864 * @hw: pointer to the hw struct
1865 * @lb_modes: loopback mode to be set
1866 * @cmd_details: pointer to command details structure or NULL
1868 * Sets loopback modes.
1870 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1872 struct i40e_asq_cmd_details *cmd_details)
1874 struct i40e_aq_desc desc;
1875 struct i40e_aqc_set_lb_mode *cmd =
1876 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1877 enum i40e_status_code status;
1879 i40e_fill_default_direct_cmd_desc(&desc,
1880 i40e_aqc_opc_set_lb_modes);
1882 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1890 * i40e_aq_set_phy_debug
1891 * @hw: pointer to the hw struct
1892 * @cmd_flags: debug command flags
1893 * @cmd_details: pointer to command details structure or NULL
1895 * Reset the external PHY.
1897 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1898 struct i40e_asq_cmd_details *cmd_details)
1900 struct i40e_aq_desc desc;
1901 struct i40e_aqc_set_phy_debug *cmd =
1902 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1903 enum i40e_status_code status;
1905 i40e_fill_default_direct_cmd_desc(&desc,
1906 i40e_aqc_opc_set_phy_debug);
1908 cmd->command_flags = cmd_flags;
1910 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1917 * @hw: pointer to the hw struct
1918 * @vsi_ctx: pointer to a vsi context struct
1919 * @cmd_details: pointer to command details structure or NULL
1921 * Add a VSI context to the hardware.
1923 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1924 struct i40e_vsi_context *vsi_ctx,
1925 struct i40e_asq_cmd_details *cmd_details)
1927 struct i40e_aq_desc desc;
1928 struct i40e_aqc_add_get_update_vsi *cmd =
1929 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1930 struct i40e_aqc_add_get_update_vsi_completion *resp =
1931 (struct i40e_aqc_add_get_update_vsi_completion *)
1933 enum i40e_status_code status;
1935 i40e_fill_default_direct_cmd_desc(&desc,
1936 i40e_aqc_opc_add_vsi);
1938 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1939 cmd->connection_type = vsi_ctx->connection_type;
1940 cmd->vf_id = vsi_ctx->vf_num;
1941 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1943 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1945 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1946 sizeof(vsi_ctx->info), cmd_details);
1948 if (status != I40E_SUCCESS)
1949 goto aq_add_vsi_exit;
1951 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1952 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1953 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1954 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1961 * i40e_aq_set_default_vsi
1962 * @hw: pointer to the hw struct
1964 * @cmd_details: pointer to command details structure or NULL
1966 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1968 struct i40e_asq_cmd_details *cmd_details)
1970 struct i40e_aq_desc desc;
1971 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1972 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1974 enum i40e_status_code status;
1976 i40e_fill_default_direct_cmd_desc(&desc,
1977 i40e_aqc_opc_set_vsi_promiscuous_modes);
1979 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1980 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1981 cmd->seid = CPU_TO_LE16(seid);
1983 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1989 * i40e_aq_set_vsi_unicast_promiscuous
1990 * @hw: pointer to the hw struct
1992 * @set: set unicast promiscuous enable/disable
1993 * @cmd_details: pointer to command details structure or NULL
1995 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1997 struct i40e_asq_cmd_details *cmd_details)
1999 struct i40e_aq_desc desc;
2000 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2001 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2002 enum i40e_status_code status;
2005 i40e_fill_default_direct_cmd_desc(&desc,
2006 i40e_aqc_opc_set_vsi_promiscuous_modes);
2009 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2011 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2013 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2015 cmd->seid = CPU_TO_LE16(seid);
2016 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2022 * i40e_aq_set_vsi_multicast_promiscuous
2023 * @hw: pointer to the hw struct
2025 * @set: set multicast promiscuous enable/disable
2026 * @cmd_details: pointer to command details structure or NULL
2028 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2029 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2031 struct i40e_aq_desc desc;
2032 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2033 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2034 enum i40e_status_code status;
2037 i40e_fill_default_direct_cmd_desc(&desc,
2038 i40e_aqc_opc_set_vsi_promiscuous_modes);
2041 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2043 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2045 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2047 cmd->seid = CPU_TO_LE16(seid);
2048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2054 * i40e_aq_set_vsi_broadcast
2055 * @hw: pointer to the hw struct
2057 * @set_filter: true to set filter, false to clear filter
2058 * @cmd_details: pointer to command details structure or NULL
2060 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2062 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2063 u16 seid, bool set_filter,
2064 struct i40e_asq_cmd_details *cmd_details)
2066 struct i40e_aq_desc desc;
2067 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2068 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2069 enum i40e_status_code status;
2071 i40e_fill_default_direct_cmd_desc(&desc,
2072 i40e_aqc_opc_set_vsi_promiscuous_modes);
2075 cmd->promiscuous_flags
2076 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2078 cmd->promiscuous_flags
2079 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2081 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2082 cmd->seid = CPU_TO_LE16(seid);
2083 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2089 * i40e_get_vsi_params - get VSI configuration info
2090 * @hw: pointer to the hw struct
2091 * @vsi_ctx: pointer to a vsi context struct
2092 * @cmd_details: pointer to command details structure or NULL
2094 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2095 struct i40e_vsi_context *vsi_ctx,
2096 struct i40e_asq_cmd_details *cmd_details)
2098 struct i40e_aq_desc desc;
2099 struct i40e_aqc_add_get_update_vsi *cmd =
2100 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2101 struct i40e_aqc_add_get_update_vsi_completion *resp =
2102 (struct i40e_aqc_add_get_update_vsi_completion *)
2104 enum i40e_status_code status;
2106 UNREFERENCED_1PARAMETER(cmd_details);
2107 i40e_fill_default_direct_cmd_desc(&desc,
2108 i40e_aqc_opc_get_vsi_parameters);
2110 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2114 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2115 sizeof(vsi_ctx->info), NULL);
2117 if (status != I40E_SUCCESS)
2118 goto aq_get_vsi_params_exit;
2120 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2121 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2122 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2123 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2125 aq_get_vsi_params_exit:
2130 * i40e_aq_update_vsi_params
2131 * @hw: pointer to the hw struct
2132 * @vsi_ctx: pointer to a vsi context struct
2133 * @cmd_details: pointer to command details structure or NULL
2135 * Update a VSI context.
2137 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2138 struct i40e_vsi_context *vsi_ctx,
2139 struct i40e_asq_cmd_details *cmd_details)
2141 struct i40e_aq_desc desc;
2142 struct i40e_aqc_add_get_update_vsi *cmd =
2143 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2144 enum i40e_status_code status;
2146 i40e_fill_default_direct_cmd_desc(&desc,
2147 i40e_aqc_opc_update_vsi_parameters);
2148 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2150 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2152 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2153 sizeof(vsi_ctx->info), cmd_details);
2159 * i40e_aq_get_switch_config
2160 * @hw: pointer to the hardware structure
2161 * @buf: pointer to the result buffer
2162 * @buf_size: length of input buffer
2163 * @start_seid: seid to start for the report, 0 == beginning
2164 * @cmd_details: pointer to command details structure or NULL
2166 * Fill the buf with switch configuration returned from AdminQ command
2168 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2169 struct i40e_aqc_get_switch_config_resp *buf,
2170 u16 buf_size, u16 *start_seid,
2171 struct i40e_asq_cmd_details *cmd_details)
2173 struct i40e_aq_desc desc;
2174 struct i40e_aqc_switch_seid *scfg =
2175 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2176 enum i40e_status_code status;
2178 i40e_fill_default_direct_cmd_desc(&desc,
2179 i40e_aqc_opc_get_switch_config);
2180 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2181 if (buf_size > I40E_AQ_LARGE_BUF)
2182 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2183 scfg->seid = CPU_TO_LE16(*start_seid);
2185 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2186 *start_seid = LE16_TO_CPU(scfg->seid);
2192 * i40e_aq_get_firmware_version
2193 * @hw: pointer to the hw struct
2194 * @fw_major_version: firmware major version
2195 * @fw_minor_version: firmware minor version
2196 * @fw_build: firmware build number
2197 * @api_major_version: major queue version
2198 * @api_minor_version: minor queue version
2199 * @cmd_details: pointer to command details structure or NULL
2201 * Get the firmware version from the admin queue commands
2203 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2204 u16 *fw_major_version, u16 *fw_minor_version,
2206 u16 *api_major_version, u16 *api_minor_version,
2207 struct i40e_asq_cmd_details *cmd_details)
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_get_version *resp =
2211 (struct i40e_aqc_get_version *)&desc.params.raw;
2212 enum i40e_status_code status;
2214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2216 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2218 if (status == I40E_SUCCESS) {
2219 if (fw_major_version != NULL)
2220 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2221 if (fw_minor_version != NULL)
2222 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2223 if (fw_build != NULL)
2224 *fw_build = LE32_TO_CPU(resp->fw_build);
2225 if (api_major_version != NULL)
2226 *api_major_version = LE16_TO_CPU(resp->api_major);
2227 if (api_minor_version != NULL)
2228 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2230 /* A workaround to fix the API version in SW */
2231 if (api_major_version && api_minor_version &&
2232 fw_major_version && fw_minor_version &&
2233 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2234 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2235 (*fw_major_version > 4)))
2236 *api_minor_version = 2;
2243 * i40e_aq_send_driver_version
2244 * @hw: pointer to the hw struct
2245 * @dv: driver's major, minor version
2246 * @cmd_details: pointer to command details structure or NULL
2248 * Send the driver version to the firmware
2250 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2251 struct i40e_driver_version *dv,
2252 struct i40e_asq_cmd_details *cmd_details)
2254 struct i40e_aq_desc desc;
2255 struct i40e_aqc_driver_version *cmd =
2256 (struct i40e_aqc_driver_version *)&desc.params.raw;
2257 enum i40e_status_code status;
2261 return I40E_ERR_PARAM;
2263 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2265 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2266 cmd->driver_major_ver = dv->major_version;
2267 cmd->driver_minor_ver = dv->minor_version;
2268 cmd->driver_build_ver = dv->build_version;
2269 cmd->driver_subbuild_ver = dv->subbuild_version;
2272 while (len < sizeof(dv->driver_string) &&
2273 (dv->driver_string[len] < 0x80) &&
2274 dv->driver_string[len])
2276 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2283 * i40e_get_link_status - get status of the HW network link
2284 * @hw: pointer to the hw struct
2286 * Returns true if link is up, false if link is down.
2288 * Side effect: LinkStatusEvent reporting becomes enabled
2290 bool i40e_get_link_status(struct i40e_hw *hw)
2292 enum i40e_status_code status = I40E_SUCCESS;
2293 bool link_status = false;
2295 if (hw->phy.get_link_info) {
2296 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2298 if (status != I40E_SUCCESS)
2299 goto i40e_get_link_status_exit;
2302 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2304 i40e_get_link_status_exit:
2309 * i40e_get_link_speed
2310 * @hw: pointer to the hw struct
2312 * Returns the link speed of the adapter.
2314 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2316 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2317 enum i40e_status_code status = I40E_SUCCESS;
2319 if (hw->phy.get_link_info) {
2320 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2322 if (status != I40E_SUCCESS)
2323 goto i40e_link_speed_exit;
2326 speed = hw->phy.link_info.link_speed;
2328 i40e_link_speed_exit:
2333 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2334 * @hw: pointer to the hw struct
2335 * @uplink_seid: the MAC or other gizmo SEID
2336 * @downlink_seid: the VSI SEID
2337 * @enabled_tc: bitmap of TCs to be enabled
2338 * @default_port: true for default port VSI, false for control port
2339 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2340 * @veb_seid: pointer to where to put the resulting VEB SEID
2341 * @cmd_details: pointer to command details structure or NULL
2343 * This asks the FW to add a VEB between the uplink and downlink
2344 * elements. If the uplink SEID is 0, this will be a floating VEB.
2346 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2347 u16 downlink_seid, u8 enabled_tc,
2348 bool default_port, bool enable_l2_filtering,
2350 struct i40e_asq_cmd_details *cmd_details)
2352 struct i40e_aq_desc desc;
2353 struct i40e_aqc_add_veb *cmd =
2354 (struct i40e_aqc_add_veb *)&desc.params.raw;
2355 struct i40e_aqc_add_veb_completion *resp =
2356 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2357 enum i40e_status_code status;
2360 /* SEIDs need to either both be set or both be 0 for floating VEB */
2361 if (!!uplink_seid != !!downlink_seid)
2362 return I40E_ERR_PARAM;
2364 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2366 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2367 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2368 cmd->enable_tcs = enabled_tc;
2370 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2372 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2374 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2376 if (enable_l2_filtering)
2377 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2379 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2383 if (!status && veb_seid)
2384 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2390 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2391 * @hw: pointer to the hw struct
2392 * @veb_seid: the SEID of the VEB to query
2393 * @switch_id: the uplink switch id
2394 * @floating: set to true if the VEB is floating
2395 * @statistic_index: index of the stats counter block for this VEB
2396 * @vebs_used: number of VEB's used by function
2397 * @vebs_free: total VEB's not reserved by any function
2398 * @cmd_details: pointer to command details structure or NULL
2400 * This retrieves the parameters for a particular VEB, specified by
2401 * uplink_seid, and returns them to the caller.
2403 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2404 u16 veb_seid, u16 *switch_id,
2405 bool *floating, u16 *statistic_index,
2406 u16 *vebs_used, u16 *vebs_free,
2407 struct i40e_asq_cmd_details *cmd_details)
2409 struct i40e_aq_desc desc;
2410 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2411 (struct i40e_aqc_get_veb_parameters_completion *)
2413 enum i40e_status_code status;
2416 return I40E_ERR_PARAM;
2418 i40e_fill_default_direct_cmd_desc(&desc,
2419 i40e_aqc_opc_get_veb_parameters);
2420 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2422 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2428 if (statistic_index)
2429 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2431 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2433 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2435 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2436 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2447 * i40e_aq_add_macvlan
2448 * @hw: pointer to the hw struct
2449 * @seid: VSI for the mac address
2450 * @mv_list: list of macvlans to be added
2451 * @count: length of the list
2452 * @cmd_details: pointer to command details structure or NULL
2454 * Add MAC/VLAN addresses to the HW filtering
2456 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2457 struct i40e_aqc_add_macvlan_element_data *mv_list,
2458 u16 count, struct i40e_asq_cmd_details *cmd_details)
2460 struct i40e_aq_desc desc;
2461 struct i40e_aqc_macvlan *cmd =
2462 (struct i40e_aqc_macvlan *)&desc.params.raw;
2463 enum i40e_status_code status;
2466 if (count == 0 || !mv_list || !hw)
2467 return I40E_ERR_PARAM;
2469 buf_size = count * sizeof(*mv_list);
2471 /* prep the rest of the request */
2472 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2473 cmd->num_addresses = CPU_TO_LE16(count);
2474 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2478 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2479 if (buf_size > I40E_AQ_LARGE_BUF)
2480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2482 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2489 * i40e_aq_remove_macvlan
2490 * @hw: pointer to the hw struct
2491 * @seid: VSI for the mac address
2492 * @mv_list: list of macvlans to be removed
2493 * @count: length of the list
2494 * @cmd_details: pointer to command details structure or NULL
2496 * Remove MAC/VLAN addresses from the HW filtering
2498 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2499 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2500 u16 count, struct i40e_asq_cmd_details *cmd_details)
2502 struct i40e_aq_desc desc;
2503 struct i40e_aqc_macvlan *cmd =
2504 (struct i40e_aqc_macvlan *)&desc.params.raw;
2505 enum i40e_status_code status;
2508 if (count == 0 || !mv_list || !hw)
2509 return I40E_ERR_PARAM;
2511 buf_size = count * sizeof(*mv_list);
2513 /* prep the rest of the request */
2514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2515 cmd->num_addresses = CPU_TO_LE16(count);
2516 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2520 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2521 if (buf_size > I40E_AQ_LARGE_BUF)
2522 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2524 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2531 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2532 * @hw: pointer to the hw struct
2533 * @seid: VSI for the vlan filters
2534 * @v_list: list of vlan filters to be added
2535 * @count: length of the list
2536 * @cmd_details: pointer to command details structure or NULL
2538 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2539 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2540 u8 count, struct i40e_asq_cmd_details *cmd_details)
2542 struct i40e_aq_desc desc;
2543 struct i40e_aqc_macvlan *cmd =
2544 (struct i40e_aqc_macvlan *)&desc.params.raw;
2545 enum i40e_status_code status;
2548 if (count == 0 || !v_list || !hw)
2549 return I40E_ERR_PARAM;
2551 buf_size = count * sizeof(*v_list);
2553 /* prep the rest of the request */
2554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2555 cmd->num_addresses = CPU_TO_LE16(count);
2556 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2560 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2561 if (buf_size > I40E_AQ_LARGE_BUF)
2562 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2564 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2571 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2572 * @hw: pointer to the hw struct
2573 * @seid: VSI for the vlan filters
2574 * @v_list: list of macvlans to be removed
2575 * @count: length of the list
2576 * @cmd_details: pointer to command details structure or NULL
2578 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2579 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2580 u8 count, struct i40e_asq_cmd_details *cmd_details)
2582 struct i40e_aq_desc desc;
2583 struct i40e_aqc_macvlan *cmd =
2584 (struct i40e_aqc_macvlan *)&desc.params.raw;
2585 enum i40e_status_code status;
2588 if (count == 0 || !v_list || !hw)
2589 return I40E_ERR_PARAM;
2591 buf_size = count * sizeof(*v_list);
2593 /* prep the rest of the request */
2594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2595 cmd->num_addresses = CPU_TO_LE16(count);
2596 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2600 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2601 if (buf_size > I40E_AQ_LARGE_BUF)
2602 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2604 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2611 * i40e_aq_send_msg_to_vf
2612 * @hw: pointer to the hardware structure
2613 * @vfid: vf id to send msg
2614 * @v_opcode: opcodes for VF-PF communication
2615 * @v_retval: return error code
2616 * @msg: pointer to the msg buffer
2617 * @msglen: msg length
2618 * @cmd_details: pointer to command details
2622 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2623 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2624 struct i40e_asq_cmd_details *cmd_details)
2626 struct i40e_aq_desc desc;
2627 struct i40e_aqc_pf_vf_message *cmd =
2628 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2629 enum i40e_status_code status;
2631 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2632 cmd->id = CPU_TO_LE32(vfid);
2633 desc.cookie_high = CPU_TO_LE32(v_opcode);
2634 desc.cookie_low = CPU_TO_LE32(v_retval);
2635 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2637 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2639 if (msglen > I40E_AQ_LARGE_BUF)
2640 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2641 desc.datalen = CPU_TO_LE16(msglen);
2643 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2649 * i40e_aq_debug_read_register
2650 * @hw: pointer to the hw struct
2651 * @reg_addr: register address
2652 * @reg_val: register value
2653 * @cmd_details: pointer to command details structure or NULL
2655 * Read the register using the admin queue commands
2657 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2658 u32 reg_addr, u64 *reg_val,
2659 struct i40e_asq_cmd_details *cmd_details)
2661 struct i40e_aq_desc desc;
2662 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2663 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2664 enum i40e_status_code status;
2666 if (reg_val == NULL)
2667 return I40E_ERR_PARAM;
2669 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2671 cmd_resp->address = CPU_TO_LE32(reg_addr);
2673 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2675 if (status == I40E_SUCCESS) {
2676 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2677 (u64)LE32_TO_CPU(cmd_resp->value_low);
2684 * i40e_aq_debug_write_register
2685 * @hw: pointer to the hw struct
2686 * @reg_addr: register address
2687 * @reg_val: register value
2688 * @cmd_details: pointer to command details structure or NULL
2690 * Write to a register using the admin queue commands
2692 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2693 u32 reg_addr, u64 reg_val,
2694 struct i40e_asq_cmd_details *cmd_details)
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_debug_reg_read_write *cmd =
2698 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2699 enum i40e_status_code status;
2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2703 cmd->address = CPU_TO_LE32(reg_addr);
2704 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2705 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2707 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2713 * i40e_aq_get_hmc_resource_profile
2714 * @hw: pointer to the hw struct
2715 * @profile: type of profile the HMC is to be set as
2716 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2717 * @cmd_details: pointer to command details structure or NULL
2719 * query the HMC profile of the device.
2721 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2722 enum i40e_aq_hmc_profile *profile,
2723 u8 *pe_vf_enabled_count,
2724 struct i40e_asq_cmd_details *cmd_details)
2726 struct i40e_aq_desc desc;
2727 struct i40e_aq_get_set_hmc_resource_profile *resp =
2728 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2729 enum i40e_status_code status;
2731 i40e_fill_default_direct_cmd_desc(&desc,
2732 i40e_aqc_opc_query_hmc_resource_profile);
2733 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2735 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2736 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2737 *pe_vf_enabled_count = resp->pe_vf_enabled &
2738 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2744 * i40e_aq_set_hmc_resource_profile
2745 * @hw: pointer to the hw struct
2746 * @profile: type of profile the HMC is to be set as
2747 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2748 * @cmd_details: pointer to command details structure or NULL
2750 * set the HMC profile of the device.
2752 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2753 enum i40e_aq_hmc_profile profile,
2754 u8 pe_vf_enabled_count,
2755 struct i40e_asq_cmd_details *cmd_details)
2757 struct i40e_aq_desc desc;
2758 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2759 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2760 enum i40e_status_code status;
2762 i40e_fill_default_direct_cmd_desc(&desc,
2763 i40e_aqc_opc_set_hmc_resource_profile);
2765 cmd->pm_profile = (u8)profile;
2766 cmd->pe_vf_enabled = pe_vf_enabled_count;
2768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2774 * i40e_aq_request_resource
2775 * @hw: pointer to the hw struct
2776 * @resource: resource id
2777 * @access: access type
2778 * @sdp_number: resource number
2779 * @timeout: the maximum time in ms that the driver may hold the resource
2780 * @cmd_details: pointer to command details structure or NULL
2782 * requests common resource using the admin queue commands
2784 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2785 enum i40e_aq_resources_ids resource,
2786 enum i40e_aq_resource_access_type access,
2787 u8 sdp_number, u64 *timeout,
2788 struct i40e_asq_cmd_details *cmd_details)
2790 struct i40e_aq_desc desc;
2791 struct i40e_aqc_request_resource *cmd_resp =
2792 (struct i40e_aqc_request_resource *)&desc.params.raw;
2793 enum i40e_status_code status;
2795 DEBUGFUNC("i40e_aq_request_resource");
2797 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2799 cmd_resp->resource_id = CPU_TO_LE16(resource);
2800 cmd_resp->access_type = CPU_TO_LE16(access);
2801 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2803 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2804 /* The completion specifies the maximum time in ms that the driver
2805 * may hold the resource in the Timeout field.
2806 * If the resource is held by someone else, the command completes with
2807 * busy return value and the timeout field indicates the maximum time
2808 * the current owner of the resource has to free it.
2810 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2811 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2817 * i40e_aq_release_resource
2818 * @hw: pointer to the hw struct
2819 * @resource: resource id
2820 * @sdp_number: resource number
2821 * @cmd_details: pointer to command details structure or NULL
2823 * release common resource using the admin queue commands
2825 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2826 enum i40e_aq_resources_ids resource,
2828 struct i40e_asq_cmd_details *cmd_details)
2830 struct i40e_aq_desc desc;
2831 struct i40e_aqc_request_resource *cmd =
2832 (struct i40e_aqc_request_resource *)&desc.params.raw;
2833 enum i40e_status_code status;
2835 DEBUGFUNC("i40e_aq_release_resource");
2837 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2839 cmd->resource_id = CPU_TO_LE16(resource);
2840 cmd->resource_number = CPU_TO_LE32(sdp_number);
2842 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2849 * @hw: pointer to the hw struct
2850 * @module_pointer: module pointer location in words from the NVM beginning
2851 * @offset: byte offset from the module beginning
2852 * @length: length of the section to be read (in bytes from the offset)
2853 * @data: command buffer (size [bytes] = length)
2854 * @last_command: tells if this is the last command in a series
2855 * @cmd_details: pointer to command details structure or NULL
2857 * Read the NVM using the admin queue commands
2859 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2860 u32 offset, u16 length, void *data,
2862 struct i40e_asq_cmd_details *cmd_details)
2864 struct i40e_aq_desc desc;
2865 struct i40e_aqc_nvm_update *cmd =
2866 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2867 enum i40e_status_code status;
2869 DEBUGFUNC("i40e_aq_read_nvm");
2871 /* In offset the highest byte must be zeroed. */
2872 if (offset & 0xFF000000) {
2873 status = I40E_ERR_PARAM;
2874 goto i40e_aq_read_nvm_exit;
2877 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2879 /* If this is the last command in a series, set the proper flag. */
2881 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2882 cmd->module_pointer = module_pointer;
2883 cmd->offset = CPU_TO_LE32(offset);
2884 cmd->length = CPU_TO_LE16(length);
2886 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2887 if (length > I40E_AQ_LARGE_BUF)
2888 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2890 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2892 i40e_aq_read_nvm_exit:
2897 * i40e_aq_read_nvm_config - read an nvm config block
2898 * @hw: pointer to the hw struct
2899 * @cmd_flags: NVM access admin command bits
2900 * @field_id: field or feature id
2901 * @data: buffer for result
2902 * @buf_size: buffer size
2903 * @element_count: pointer to count of elements read by FW
2904 * @cmd_details: pointer to command details structure or NULL
2906 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2907 u8 cmd_flags, u32 field_id, void *data,
2908 u16 buf_size, u16 *element_count,
2909 struct i40e_asq_cmd_details *cmd_details)
2911 struct i40e_aq_desc desc;
2912 struct i40e_aqc_nvm_config_read *cmd =
2913 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2914 enum i40e_status_code status;
2916 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2917 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2918 if (buf_size > I40E_AQ_LARGE_BUF)
2919 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2921 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2922 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2923 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2924 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2926 cmd->element_id_msw = 0;
2928 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2930 if (!status && element_count)
2931 *element_count = LE16_TO_CPU(cmd->element_count);
2937 * i40e_aq_write_nvm_config - write an nvm config block
2938 * @hw: pointer to the hw struct
2939 * @cmd_flags: NVM access admin command bits
2940 * @data: buffer for result
2941 * @buf_size: buffer size
2942 * @element_count: count of elements to be written
2943 * @cmd_details: pointer to command details structure or NULL
2945 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2946 u8 cmd_flags, void *data, u16 buf_size,
2948 struct i40e_asq_cmd_details *cmd_details)
2950 struct i40e_aq_desc desc;
2951 struct i40e_aqc_nvm_config_write *cmd =
2952 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2953 enum i40e_status_code status;
2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2956 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2957 if (buf_size > I40E_AQ_LARGE_BUF)
2958 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2960 cmd->element_count = CPU_TO_LE16(element_count);
2961 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2962 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2969 * @hw: pointer to the hw struct
2970 * @module_pointer: module pointer location in words from the NVM beginning
2971 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2972 * @length: length of the section to be erased (expressed in 4 KB)
2973 * @last_command: tells if this is the last command in a series
2974 * @cmd_details: pointer to command details structure or NULL
2976 * Erase the NVM sector using the admin queue commands
2978 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2979 u32 offset, u16 length, bool last_command,
2980 struct i40e_asq_cmd_details *cmd_details)
2982 struct i40e_aq_desc desc;
2983 struct i40e_aqc_nvm_update *cmd =
2984 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2985 enum i40e_status_code status;
2987 DEBUGFUNC("i40e_aq_erase_nvm");
2989 /* In offset the highest byte must be zeroed. */
2990 if (offset & 0xFF000000) {
2991 status = I40E_ERR_PARAM;
2992 goto i40e_aq_erase_nvm_exit;
2995 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2997 /* If this is the last command in a series, set the proper flag. */
2999 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3000 cmd->module_pointer = module_pointer;
3001 cmd->offset = CPU_TO_LE32(offset);
3002 cmd->length = CPU_TO_LE16(length);
3004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3006 i40e_aq_erase_nvm_exit:
3010 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3011 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3012 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3013 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3014 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3015 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3016 #define I40E_DEV_FUNC_CAP_VF 0x13
3017 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3018 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3019 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3020 #define I40E_DEV_FUNC_CAP_VSI 0x17
3021 #define I40E_DEV_FUNC_CAP_DCB 0x18
3022 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3023 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3024 #define I40E_DEV_FUNC_CAP_RSS 0x40
3025 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3026 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3027 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3028 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3029 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3030 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3031 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
3032 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3033 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3034 #define I40E_DEV_FUNC_CAP_LED 0x61
3035 #define I40E_DEV_FUNC_CAP_SDP 0x62
3036 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3039 * i40e_parse_discover_capabilities
3040 * @hw: pointer to the hw struct
3041 * @buff: pointer to a buffer containing device/function capability records
3042 * @cap_count: number of capability records in the list
3043 * @list_type_opc: type of capabilities list to parse
3045 * Parse the device/function capabilities list.
3047 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3049 enum i40e_admin_queue_opc list_type_opc)
3051 struct i40e_aqc_list_capabilities_element_resp *cap;
3052 u32 valid_functions, num_functions;
3053 u32 number, logical_id, phys_id;
3054 struct i40e_hw_capabilities *p;
3058 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3060 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3061 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3062 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3063 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3067 for (i = 0; i < cap_count; i++, cap++) {
3068 id = LE16_TO_CPU(cap->id);
3069 number = LE32_TO_CPU(cap->number);
3070 logical_id = LE32_TO_CPU(cap->logical_id);
3071 phys_id = LE32_TO_CPU(cap->phys_id);
3074 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3075 p->switch_mode = number;
3077 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3078 p->management_mode = number;
3080 case I40E_DEV_FUNC_CAP_NPAR:
3081 p->npar_enable = number;
3083 case I40E_DEV_FUNC_CAP_OS2BMC:
3086 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3087 p->valid_functions = number;
3089 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3091 p->sr_iov_1_1 = true;
3093 case I40E_DEV_FUNC_CAP_VF:
3094 p->num_vfs = number;
3095 p->vf_base_id = logical_id;
3097 case I40E_DEV_FUNC_CAP_VMDQ:
3101 case I40E_DEV_FUNC_CAP_802_1_QBG:
3103 p->evb_802_1_qbg = true;
3105 case I40E_DEV_FUNC_CAP_802_1_QBH:
3107 p->evb_802_1_qbh = true;
3109 case I40E_DEV_FUNC_CAP_VSI:
3110 p->num_vsis = number;
3112 case I40E_DEV_FUNC_CAP_DCB:
3115 p->enabled_tcmap = logical_id;
3119 case I40E_DEV_FUNC_CAP_FCOE:
3123 case I40E_DEV_FUNC_CAP_ISCSI:
3127 case I40E_DEV_FUNC_CAP_RSS:
3129 p->rss_table_size = number;
3130 p->rss_table_entry_width = logical_id;
3132 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3133 p->num_rx_qp = number;
3134 p->base_queue = phys_id;
3136 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3137 p->num_tx_qp = number;
3138 p->base_queue = phys_id;
3140 case I40E_DEV_FUNC_CAP_MSIX:
3141 p->num_msix_vectors = number;
3143 case I40E_DEV_FUNC_CAP_MSIX_VF:
3144 p->num_msix_vectors_vf = number;
3146 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
3148 p->mfp_mode_1 = true;
3150 case I40E_DEV_FUNC_CAP_CEM:
3154 case I40E_DEV_FUNC_CAP_IWARP:
3158 case I40E_DEV_FUNC_CAP_LED:
3159 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3160 p->led[phys_id] = true;
3162 case I40E_DEV_FUNC_CAP_SDP:
3163 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3164 p->sdp[phys_id] = true;
3166 case I40E_DEV_FUNC_CAP_MDIO:
3168 p->mdio_port_num = phys_id;
3169 p->mdio_port_mode = logical_id;
3172 case I40E_DEV_FUNC_CAP_IEEE_1588:
3174 p->ieee_1588 = true;
3176 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3178 p->fd_filters_guaranteed = number;
3179 p->fd_filters_best_effort = logical_id;
3186 #ifdef I40E_FCOE_ENA
3187 /* Software override ensuring FCoE is disabled if npar or mfp
3188 * mode because it is not supported in these modes.
3190 if (p->npar_enable || p->mfp_mode_1)
3193 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3197 /* count the enabled ports (aka the "not disabled" ports) */
3199 for (i = 0; i < 4; i++) {
3200 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3203 /* use AQ read to get the physical register offset instead
3204 * of the port relative offset
3206 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3207 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3211 valid_functions = p->valid_functions;
3213 while (valid_functions) {
3214 if (valid_functions & 1)
3216 valid_functions >>= 1;
3219 /* partition id is 1-based, and functions are evenly spread
3220 * across the ports as partitions
3222 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3223 hw->num_partitions = num_functions / hw->num_ports;
3225 /* additional HW specific goodies that might
3226 * someday be HW version specific
3228 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3232 * i40e_aq_discover_capabilities
3233 * @hw: pointer to the hw struct
3234 * @buff: a virtual buffer to hold the capabilities
3235 * @buff_size: Size of the virtual buffer
3236 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3237 * @list_type_opc: capabilities type to discover - pass in the command opcode
3238 * @cmd_details: pointer to command details structure or NULL
3240 * Get the device capabilities descriptions from the firmware
3242 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3243 void *buff, u16 buff_size, u16 *data_size,
3244 enum i40e_admin_queue_opc list_type_opc,
3245 struct i40e_asq_cmd_details *cmd_details)
3247 struct i40e_aqc_list_capabilites *cmd;
3248 struct i40e_aq_desc desc;
3249 enum i40e_status_code status = I40E_SUCCESS;
3251 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3253 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3254 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3255 status = I40E_ERR_PARAM;
3259 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3261 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3262 if (buff_size > I40E_AQ_LARGE_BUF)
3263 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3265 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3266 *data_size = LE16_TO_CPU(desc.datalen);
3271 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3279 * i40e_aq_update_nvm
3280 * @hw: pointer to the hw struct
3281 * @module_pointer: module pointer location in words from the NVM beginning
3282 * @offset: byte offset from the module beginning
3283 * @length: length of the section to be written (in bytes from the offset)
3284 * @data: command buffer (size [bytes] = length)
3285 * @last_command: tells if this is the last command in a series
3286 * @cmd_details: pointer to command details structure or NULL
3288 * Update the NVM using the admin queue commands
3290 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3291 u32 offset, u16 length, void *data,
3293 struct i40e_asq_cmd_details *cmd_details)
3295 struct i40e_aq_desc desc;
3296 struct i40e_aqc_nvm_update *cmd =
3297 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3298 enum i40e_status_code status;
3300 DEBUGFUNC("i40e_aq_update_nvm");
3302 /* In offset the highest byte must be zeroed. */
3303 if (offset & 0xFF000000) {
3304 status = I40E_ERR_PARAM;
3305 goto i40e_aq_update_nvm_exit;
3308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3310 /* If this is the last command in a series, set the proper flag. */
3312 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3313 cmd->module_pointer = module_pointer;
3314 cmd->offset = CPU_TO_LE32(offset);
3315 cmd->length = CPU_TO_LE16(length);
3317 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3318 if (length > I40E_AQ_LARGE_BUF)
3319 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3321 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3323 i40e_aq_update_nvm_exit:
3328 * i40e_aq_get_lldp_mib
3329 * @hw: pointer to the hw struct
3330 * @bridge_type: type of bridge requested
3331 * @mib_type: Local, Remote or both Local and Remote MIBs
3332 * @buff: pointer to a user supplied buffer to store the MIB block
3333 * @buff_size: size of the buffer (in bytes)
3334 * @local_len : length of the returned Local LLDP MIB
3335 * @remote_len: length of the returned Remote LLDP MIB
3336 * @cmd_details: pointer to command details structure or NULL
3338 * Requests the complete LLDP MIB (entire packet).
3340 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3341 u8 mib_type, void *buff, u16 buff_size,
3342 u16 *local_len, u16 *remote_len,
3343 struct i40e_asq_cmd_details *cmd_details)
3345 struct i40e_aq_desc desc;
3346 struct i40e_aqc_lldp_get_mib *cmd =
3347 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3348 struct i40e_aqc_lldp_get_mib *resp =
3349 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3350 enum i40e_status_code status;
3352 if (buff_size == 0 || !buff)
3353 return I40E_ERR_PARAM;
3355 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3356 /* Indirect Command */
3357 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3359 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3360 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3361 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3363 desc.datalen = CPU_TO_LE16(buff_size);
3365 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3366 if (buff_size > I40E_AQ_LARGE_BUF)
3367 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3369 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3371 if (local_len != NULL)
3372 *local_len = LE16_TO_CPU(resp->local_len);
3373 if (remote_len != NULL)
3374 *remote_len = LE16_TO_CPU(resp->remote_len);
3381 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3382 * @hw: pointer to the hw struct
3383 * @mib_type: Local, Remote or both Local and Remote MIBs
3384 * @buff: pointer to a user supplied buffer to store the MIB block
3385 * @buff_size: size of the buffer (in bytes)
3386 * @cmd_details: pointer to command details structure or NULL
3390 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3391 u8 mib_type, void *buff, u16 buff_size,
3392 struct i40e_asq_cmd_details *cmd_details)
3394 struct i40e_aq_desc desc;
3395 struct i40e_aqc_lldp_set_local_mib *cmd =
3396 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3397 enum i40e_status_code status;
3399 if (buff_size == 0 || !buff)
3400 return I40E_ERR_PARAM;
3402 i40e_fill_default_direct_cmd_desc(&desc,
3403 i40e_aqc_opc_lldp_set_local_mib);
3404 /* Indirect Command */
3405 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3406 if (buff_size > I40E_AQ_LARGE_BUF)
3407 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3408 desc.datalen = CPU_TO_LE16(buff_size);
3410 cmd->type = mib_type;
3411 cmd->length = CPU_TO_LE16(buff_size);
3412 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3413 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3415 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3420 * i40e_aq_cfg_lldp_mib_change_event
3421 * @hw: pointer to the hw struct
3422 * @enable_update: Enable or Disable event posting
3423 * @cmd_details: pointer to command details structure or NULL
3425 * Enable or Disable posting of an event on ARQ when LLDP MIB
3426 * associated with the interface changes
3428 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3430 struct i40e_asq_cmd_details *cmd_details)
3432 struct i40e_aq_desc desc;
3433 struct i40e_aqc_lldp_update_mib *cmd =
3434 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3435 enum i40e_status_code status;
3437 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3440 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3442 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3448 * i40e_aq_add_lldp_tlv
3449 * @hw: pointer to the hw struct
3450 * @bridge_type: type of bridge
3451 * @buff: buffer with TLV to add
3452 * @buff_size: length of the buffer
3453 * @tlv_len: length of the TLV to be added
3454 * @mib_len: length of the LLDP MIB returned in response
3455 * @cmd_details: pointer to command details structure or NULL
3457 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3458 * it is responsibility of the caller to make sure that the TLV is not
3459 * already present in the LLDPDU.
3460 * In return firmware will write the complete LLDP MIB with the newly
3461 * added TLV in the response buffer.
3463 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3464 void *buff, u16 buff_size, u16 tlv_len,
3466 struct i40e_asq_cmd_details *cmd_details)
3468 struct i40e_aq_desc desc;
3469 struct i40e_aqc_lldp_add_tlv *cmd =
3470 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3471 enum i40e_status_code status;
3473 if (buff_size == 0 || !buff || tlv_len == 0)
3474 return I40E_ERR_PARAM;
3476 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3478 /* Indirect Command */
3479 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3480 if (buff_size > I40E_AQ_LARGE_BUF)
3481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3482 desc.datalen = CPU_TO_LE16(buff_size);
3484 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3485 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3486 cmd->len = CPU_TO_LE16(tlv_len);
3488 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3490 if (mib_len != NULL)
3491 *mib_len = LE16_TO_CPU(desc.datalen);
3498 * i40e_aq_update_lldp_tlv
3499 * @hw: pointer to the hw struct
3500 * @bridge_type: type of bridge
3501 * @buff: buffer with TLV to update
3502 * @buff_size: size of the buffer holding original and updated TLVs
3503 * @old_len: Length of the Original TLV
3504 * @new_len: Length of the Updated TLV
3505 * @offset: offset of the updated TLV in the buff
3506 * @mib_len: length of the returned LLDP MIB
3507 * @cmd_details: pointer to command details structure or NULL
3509 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3510 * Firmware will place the complete LLDP MIB in response buffer with the
3513 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3514 u8 bridge_type, void *buff, u16 buff_size,
3515 u16 old_len, u16 new_len, u16 offset,
3517 struct i40e_asq_cmd_details *cmd_details)
3519 struct i40e_aq_desc desc;
3520 struct i40e_aqc_lldp_update_tlv *cmd =
3521 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3522 enum i40e_status_code status;
3524 if (buff_size == 0 || !buff || offset == 0 ||
3525 old_len == 0 || new_len == 0)
3526 return I40E_ERR_PARAM;
3528 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3530 /* Indirect Command */
3531 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3532 if (buff_size > I40E_AQ_LARGE_BUF)
3533 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3534 desc.datalen = CPU_TO_LE16(buff_size);
3536 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3537 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3538 cmd->old_len = CPU_TO_LE16(old_len);
3539 cmd->new_offset = CPU_TO_LE16(offset);
3540 cmd->new_len = CPU_TO_LE16(new_len);
3542 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3544 if (mib_len != NULL)
3545 *mib_len = LE16_TO_CPU(desc.datalen);
3552 * i40e_aq_delete_lldp_tlv
3553 * @hw: pointer to the hw struct
3554 * @bridge_type: type of bridge
3555 * @buff: pointer to a user supplied buffer that has the TLV
3556 * @buff_size: length of the buffer
3557 * @tlv_len: length of the TLV to be deleted
3558 * @mib_len: length of the returned LLDP MIB
3559 * @cmd_details: pointer to command details structure or NULL
3561 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3562 * The firmware places the entire LLDP MIB in the response buffer.
3564 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3565 u8 bridge_type, void *buff, u16 buff_size,
3566 u16 tlv_len, u16 *mib_len,
3567 struct i40e_asq_cmd_details *cmd_details)
3569 struct i40e_aq_desc desc;
3570 struct i40e_aqc_lldp_add_tlv *cmd =
3571 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3572 enum i40e_status_code status;
3574 if (buff_size == 0 || !buff)
3575 return I40E_ERR_PARAM;
3577 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3579 /* Indirect Command */
3580 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3581 if (buff_size > I40E_AQ_LARGE_BUF)
3582 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3583 desc.datalen = CPU_TO_LE16(buff_size);
3584 cmd->len = CPU_TO_LE16(tlv_len);
3585 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3586 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3588 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3590 if (mib_len != NULL)
3591 *mib_len = LE16_TO_CPU(desc.datalen);
3599 * @hw: pointer to the hw struct
3600 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3601 * @cmd_details: pointer to command details structure or NULL
3603 * Stop or Shutdown the embedded LLDP Agent
3605 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3606 struct i40e_asq_cmd_details *cmd_details)
3608 struct i40e_aq_desc desc;
3609 struct i40e_aqc_lldp_stop *cmd =
3610 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3611 enum i40e_status_code status;
3613 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3616 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3624 * i40e_aq_start_lldp
3625 * @hw: pointer to the hw struct
3626 * @cmd_details: pointer to command details structure or NULL
3628 * Start the embedded LLDP Agent on all ports.
3630 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3631 struct i40e_asq_cmd_details *cmd_details)
3633 struct i40e_aq_desc desc;
3634 struct i40e_aqc_lldp_start *cmd =
3635 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3636 enum i40e_status_code status;
3638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3640 cmd->command = I40E_AQ_LLDP_AGENT_START;
3642 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3648 * i40e_aq_get_cee_dcb_config
3649 * @hw: pointer to the hw struct
3650 * @buff: response buffer that stores CEE operational configuration
3651 * @buff_size: size of the buffer passed
3652 * @cmd_details: pointer to command details structure or NULL
3654 * Get CEE DCBX mode operational configuration from firmware
3656 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3657 void *buff, u16 buff_size,
3658 struct i40e_asq_cmd_details *cmd_details)
3660 struct i40e_aq_desc desc;
3661 enum i40e_status_code status;
3663 if (buff_size == 0 || !buff)
3664 return I40E_ERR_PARAM;
3666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3668 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3669 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3676 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3677 * @hw: pointer to the hw struct
3678 * @start_agent: True if DCBx Agent needs to be Started
3679 * False if DCBx Agent needs to be Stopped
3680 * @cmd_details: pointer to command details structure or NULL
3682 * Start/Stop the embedded dcbx Agent
3684 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3686 struct i40e_asq_cmd_details *cmd_details)
3688 struct i40e_aq_desc desc;
3689 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3690 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3692 enum i40e_status_code status;
3694 i40e_fill_default_direct_cmd_desc(&desc,
3695 i40e_aqc_opc_lldp_stop_start_spec_agent);
3698 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3700 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3706 * i40e_aq_add_udp_tunnel
3707 * @hw: pointer to the hw struct
3708 * @udp_port: the UDP port to add
3709 * @header_len: length of the tunneling header length in DWords
3710 * @protocol_index: protocol index type
3711 * @filter_index: pointer to filter index
3712 * @cmd_details: pointer to command details structure or NULL
3714 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3715 u16 udp_port, u8 protocol_index,
3717 struct i40e_asq_cmd_details *cmd_details)
3719 struct i40e_aq_desc desc;
3720 struct i40e_aqc_add_udp_tunnel *cmd =
3721 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3722 struct i40e_aqc_del_udp_tunnel_completion *resp =
3723 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3724 enum i40e_status_code status;
3726 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3728 cmd->udp_port = CPU_TO_LE16(udp_port);
3729 cmd->protocol_type = protocol_index;
3731 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3733 if (!status && filter_index)
3734 *filter_index = resp->index;
3740 * i40e_aq_del_udp_tunnel
3741 * @hw: pointer to the hw struct
3742 * @index: filter index
3743 * @cmd_details: pointer to command details structure or NULL
3745 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3746 struct i40e_asq_cmd_details *cmd_details)
3748 struct i40e_aq_desc desc;
3749 struct i40e_aqc_remove_udp_tunnel *cmd =
3750 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3751 enum i40e_status_code status;
3753 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3763 * i40e_aq_get_switch_resource_alloc (0x0204)
3764 * @hw: pointer to the hw struct
3765 * @num_entries: pointer to u8 to store the number of resource entries returned
3766 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3767 * to store the resource information for all resource types. Each
3768 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3769 * @count: size, in bytes, of the buffer provided
3770 * @cmd_details: pointer to command details structure or NULL
3772 * Query the resources allocated to a function.
3774 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3776 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3778 struct i40e_asq_cmd_details *cmd_details)
3780 struct i40e_aq_desc desc;
3781 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3782 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3783 enum i40e_status_code status;
3784 u16 length = count * sizeof(*buf);
3786 i40e_fill_default_direct_cmd_desc(&desc,
3787 i40e_aqc_opc_get_switch_resource_alloc);
3789 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3790 if (length > I40E_AQ_LARGE_BUF)
3791 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3793 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3795 if (!status && num_entries)
3796 *num_entries = cmd_resp->num_entries;
3802 * i40e_aq_delete_element - Delete switch element
3803 * @hw: pointer to the hw struct
3804 * @seid: the SEID to delete from the switch
3805 * @cmd_details: pointer to command details structure or NULL
3807 * This deletes a switch element from the switch.
3809 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3810 struct i40e_asq_cmd_details *cmd_details)
3812 struct i40e_aq_desc desc;
3813 struct i40e_aqc_switch_seid *cmd =
3814 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3815 enum i40e_status_code status;
3818 return I40E_ERR_PARAM;
3820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3822 cmd->seid = CPU_TO_LE16(seid);
3824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3830 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3831 * @hw: pointer to the hw struct
3832 * @flags: component flags
3833 * @mac_seid: uplink seid (MAC SEID)
3834 * @vsi_seid: connected vsi seid
3835 * @ret_seid: seid of create pv component
3837 * This instantiates an i40e port virtualizer with specified flags.
3838 * Depending on specified flags the port virtualizer can act as a
3839 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3841 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3842 u16 mac_seid, u16 vsi_seid,
3845 struct i40e_aq_desc desc;
3846 struct i40e_aqc_add_update_pv *cmd =
3847 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3848 struct i40e_aqc_add_update_pv_completion *resp =
3849 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3850 enum i40e_status_code status;
3853 return I40E_ERR_PARAM;
3855 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3856 cmd->command_flags = CPU_TO_LE16(flags);
3857 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3858 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3860 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3861 if (!status && ret_seid)
3862 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3868 * i40e_aq_add_tag - Add an S/E-tag
3869 * @hw: pointer to the hw struct
3870 * @direct_to_queue: should s-tag direct flow to a specific queue
3871 * @vsi_seid: VSI SEID to use this tag
3872 * @tag: value of the tag
3873 * @queue_num: queue number, only valid is direct_to_queue is true
3874 * @tags_used: return value, number of tags in use by this PF
3875 * @tags_free: return value, number of unallocated tags
3876 * @cmd_details: pointer to command details structure or NULL
3878 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3879 * the number of tags allocated by the PF, and the number of unallocated
3882 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3883 u16 vsi_seid, u16 tag, u16 queue_num,
3884 u16 *tags_used, u16 *tags_free,
3885 struct i40e_asq_cmd_details *cmd_details)
3887 struct i40e_aq_desc desc;
3888 struct i40e_aqc_add_tag *cmd =
3889 (struct i40e_aqc_add_tag *)&desc.params.raw;
3890 struct i40e_aqc_add_remove_tag_completion *resp =
3891 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3892 enum i40e_status_code status;
3895 return I40E_ERR_PARAM;
3897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3899 cmd->seid = CPU_TO_LE16(vsi_seid);
3900 cmd->tag = CPU_TO_LE16(tag);
3901 if (direct_to_queue) {
3902 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3903 cmd->queue_number = CPU_TO_LE16(queue_num);
3906 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3909 if (tags_used != NULL)
3910 *tags_used = LE16_TO_CPU(resp->tags_used);
3911 if (tags_free != NULL)
3912 *tags_free = LE16_TO_CPU(resp->tags_free);
3919 * i40e_aq_remove_tag - Remove an S- or E-tag
3920 * @hw: pointer to the hw struct
3921 * @vsi_seid: VSI SEID this tag is associated with
3922 * @tag: value of the S-tag to delete
3923 * @tags_used: return value, number of tags in use by this PF
3924 * @tags_free: return value, number of unallocated tags
3925 * @cmd_details: pointer to command details structure or NULL
3927 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3928 * the number of tags allocated by the PF, and the number of unallocated
3931 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3932 u16 tag, u16 *tags_used, u16 *tags_free,
3933 struct i40e_asq_cmd_details *cmd_details)
3935 struct i40e_aq_desc desc;
3936 struct i40e_aqc_remove_tag *cmd =
3937 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3938 struct i40e_aqc_add_remove_tag_completion *resp =
3939 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3940 enum i40e_status_code status;
3943 return I40E_ERR_PARAM;
3945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3947 cmd->seid = CPU_TO_LE16(vsi_seid);
3948 cmd->tag = CPU_TO_LE16(tag);
3950 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3953 if (tags_used != NULL)
3954 *tags_used = LE16_TO_CPU(resp->tags_used);
3955 if (tags_free != NULL)
3956 *tags_free = LE16_TO_CPU(resp->tags_free);
3963 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3964 * @hw: pointer to the hw struct
3965 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3966 * @etag: value of E-tag to add
3967 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3968 * @buf: address of indirect buffer
3969 * @tags_used: return value, number of E-tags in use by this port
3970 * @tags_free: return value, number of unallocated M-tags
3971 * @cmd_details: pointer to command details structure or NULL
3973 * This associates a multicast E-tag to a port virtualizer. It will return
3974 * the number of tags allocated by the PF, and the number of unallocated
3977 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3978 * num_tags_in_buf long.
3980 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3981 u16 etag, u8 num_tags_in_buf, void *buf,
3982 u16 *tags_used, u16 *tags_free,
3983 struct i40e_asq_cmd_details *cmd_details)
3985 struct i40e_aq_desc desc;
3986 struct i40e_aqc_add_remove_mcast_etag *cmd =
3987 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3988 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3989 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3990 enum i40e_status_code status;
3991 u16 length = sizeof(u16) * num_tags_in_buf;
3993 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3994 return I40E_ERR_PARAM;
3996 i40e_fill_default_direct_cmd_desc(&desc,
3997 i40e_aqc_opc_add_multicast_etag);
3999 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4000 cmd->etag = CPU_TO_LE16(etag);
4001 cmd->num_unicast_etags = num_tags_in_buf;
4003 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4004 if (length > I40E_AQ_LARGE_BUF)
4005 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4007 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4010 if (tags_used != NULL)
4011 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4012 if (tags_free != NULL)
4013 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4020 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4021 * @hw: pointer to the hw struct
4022 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4023 * @etag: value of the E-tag to remove
4024 * @tags_used: return value, number of tags in use by this port
4025 * @tags_free: return value, number of unallocated tags
4026 * @cmd_details: pointer to command details structure or NULL
4028 * This deletes an E-tag from the port virtualizer. It will return
4029 * the number of tags allocated by the port, and the number of unallocated
4032 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4033 u16 etag, u16 *tags_used, u16 *tags_free,
4034 struct i40e_asq_cmd_details *cmd_details)
4036 struct i40e_aq_desc desc;
4037 struct i40e_aqc_add_remove_mcast_etag *cmd =
4038 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4039 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4040 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4041 enum i40e_status_code status;
4045 return I40E_ERR_PARAM;
4047 i40e_fill_default_direct_cmd_desc(&desc,
4048 i40e_aqc_opc_remove_multicast_etag);
4050 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4051 cmd->etag = CPU_TO_LE16(etag);
4053 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4056 if (tags_used != NULL)
4057 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4058 if (tags_free != NULL)
4059 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4066 * i40e_aq_update_tag - Update an S/E-tag
4067 * @hw: pointer to the hw struct
4068 * @vsi_seid: VSI SEID using this S-tag
4069 * @old_tag: old tag value
4070 * @new_tag: new tag value
4071 * @tags_used: return value, number of tags in use by this PF
4072 * @tags_free: return value, number of unallocated tags
4073 * @cmd_details: pointer to command details structure or NULL
4075 * This updates the value of the tag currently attached to this VSI
4076 * in the switch complex. It will return the number of tags allocated
4077 * by the PF, and the number of unallocated tags available.
4079 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4080 u16 old_tag, u16 new_tag, u16 *tags_used,
4082 struct i40e_asq_cmd_details *cmd_details)
4084 struct i40e_aq_desc desc;
4085 struct i40e_aqc_update_tag *cmd =
4086 (struct i40e_aqc_update_tag *)&desc.params.raw;
4087 struct i40e_aqc_update_tag_completion *resp =
4088 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4089 enum i40e_status_code status;
4092 return I40E_ERR_PARAM;
4094 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4096 cmd->seid = CPU_TO_LE16(vsi_seid);
4097 cmd->old_tag = CPU_TO_LE16(old_tag);
4098 cmd->new_tag = CPU_TO_LE16(new_tag);
4100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4103 if (tags_used != NULL)
4104 *tags_used = LE16_TO_CPU(resp->tags_used);
4105 if (tags_free != NULL)
4106 *tags_free = LE16_TO_CPU(resp->tags_free);
4113 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4114 * @hw: pointer to the hw struct
4115 * @tcmap: TC map for request/release any ignore PFC condition
4116 * @request: request or release ignore PFC condition
4117 * @tcmap_ret: return TCs for which PFC is currently ignored
4118 * @cmd_details: pointer to command details structure or NULL
4120 * This sends out request/release to ignore PFC condition for a TC.
4121 * It will return the TCs for which PFC is currently ignored.
4123 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4124 bool request, u8 *tcmap_ret,
4125 struct i40e_asq_cmd_details *cmd_details)
4127 struct i40e_aq_desc desc;
4128 struct i40e_aqc_pfc_ignore *cmd_resp =
4129 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4130 enum i40e_status_code status;
4132 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4135 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4137 cmd_resp->tc_bitmap = tcmap;
4139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4142 if (tcmap_ret != NULL)
4143 *tcmap_ret = cmd_resp->tc_bitmap;
4150 * i40e_aq_dcb_updated - DCB Updated Command
4151 * @hw: pointer to the hw struct
4152 * @cmd_details: pointer to command details structure or NULL
4154 * When LLDP is handled in PF this command is used by the PF
4155 * to notify EMP that a DCB setting is modified.
4156 * When LLDP is handled in EMP this command is used by the PF
4157 * to notify EMP whenever one of the following parameters get
4159 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4160 * - PCIRTT in PRTDCB_GENC.PCIRTT
4161 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4162 * EMP will return when the shared RPB settings have been
4163 * recomputed and modified. The retval field in the descriptor
4164 * will be set to 0 when RPB is modified.
4166 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4167 struct i40e_asq_cmd_details *cmd_details)
4169 struct i40e_aq_desc desc;
4170 enum i40e_status_code status;
4172 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4174 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4180 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4181 * @hw: pointer to the hw struct
4182 * @seid: defines the SEID of the switch for which the stats are requested
4183 * @vlan_id: the VLAN ID for which the statistics are requested
4184 * @stat_index: index of the statistics counters block assigned to this VLAN
4185 * @cmd_details: pointer to command details structure or NULL
4187 * XL710 supports 128 smonVlanStats counters.This command is used to
4188 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4191 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4192 u16 vlan_id, u16 *stat_index,
4193 struct i40e_asq_cmd_details *cmd_details)
4195 struct i40e_aq_desc desc;
4196 struct i40e_aqc_add_remove_statistics *cmd_resp =
4197 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4198 enum i40e_status_code status;
4200 if ((seid == 0) || (stat_index == NULL))
4201 return I40E_ERR_PARAM;
4203 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4205 cmd_resp->seid = CPU_TO_LE16(seid);
4206 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4210 if (!status && stat_index)
4211 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4217 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4218 * @hw: pointer to the hw struct
4219 * @seid: defines the SEID of the switch for which the stats are requested
4220 * @vlan_id: the VLAN ID for which the statistics are requested
4221 * @stat_index: index of the statistics counters block assigned to this VLAN
4222 * @cmd_details: pointer to command details structure or NULL
4224 * XL710 supports 128 smonVlanStats counters.This command is used to
4225 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4228 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4229 u16 vlan_id, u16 stat_index,
4230 struct i40e_asq_cmd_details *cmd_details)
4232 struct i40e_aq_desc desc;
4233 struct i40e_aqc_add_remove_statistics *cmd =
4234 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4235 enum i40e_status_code status;
4238 return I40E_ERR_PARAM;
4240 i40e_fill_default_direct_cmd_desc(&desc,
4241 i40e_aqc_opc_remove_statistics);
4243 cmd->seid = CPU_TO_LE16(seid);
4244 cmd->vlan = CPU_TO_LE16(vlan_id);
4245 cmd->stat_index = CPU_TO_LE16(stat_index);
4247 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4253 * i40e_aq_set_port_parameters - set physical port parameters.
4254 * @hw: pointer to the hw struct
4255 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4256 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4257 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4258 * @double_vlan: if set double VLAN is enabled
4259 * @cmd_details: pointer to command details structure or NULL
4261 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4262 u16 bad_frame_vsi, bool save_bad_pac,
4263 bool pad_short_pac, bool double_vlan,
4264 struct i40e_asq_cmd_details *cmd_details)
4266 struct i40e_aqc_set_port_parameters *cmd;
4267 enum i40e_status_code status;
4268 struct i40e_aq_desc desc;
4269 u16 command_flags = 0;
4271 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4273 i40e_fill_default_direct_cmd_desc(&desc,
4274 i40e_aqc_opc_set_port_parameters);
4276 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4278 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4280 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4282 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4283 cmd->command_flags = CPU_TO_LE16(command_flags);
4285 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4291 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4292 * @hw: pointer to the hw struct
4293 * @seid: seid for the physical port/switching component/vsi
4294 * @buff: Indirect buffer to hold data parameters and response
4295 * @buff_size: Indirect buffer size
4296 * @opcode: Tx scheduler AQ command opcode
4297 * @cmd_details: pointer to command details structure or NULL
4299 * Generic command handler for Tx scheduler AQ commands
4301 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4302 void *buff, u16 buff_size,
4303 enum i40e_admin_queue_opc opcode,
4304 struct i40e_asq_cmd_details *cmd_details)
4306 struct i40e_aq_desc desc;
4307 struct i40e_aqc_tx_sched_ind *cmd =
4308 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4309 enum i40e_status_code status;
4310 bool cmd_param_flag = false;
4313 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4314 case i40e_aqc_opc_configure_vsi_tc_bw:
4315 case i40e_aqc_opc_enable_switching_comp_ets:
4316 case i40e_aqc_opc_modify_switching_comp_ets:
4317 case i40e_aqc_opc_disable_switching_comp_ets:
4318 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4319 case i40e_aqc_opc_configure_switching_comp_bw_config:
4320 cmd_param_flag = true;
4322 case i40e_aqc_opc_query_vsi_bw_config:
4323 case i40e_aqc_opc_query_vsi_ets_sla_config:
4324 case i40e_aqc_opc_query_switching_comp_ets_config:
4325 case i40e_aqc_opc_query_port_ets_config:
4326 case i40e_aqc_opc_query_switching_comp_bw_config:
4327 cmd_param_flag = false;
4330 return I40E_ERR_PARAM;
4333 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4335 /* Indirect command */
4336 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4338 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4339 if (buff_size > I40E_AQ_LARGE_BUF)
4340 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4342 desc.datalen = CPU_TO_LE16(buff_size);
4344 cmd->vsi_seid = CPU_TO_LE16(seid);
4346 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4352 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4353 * @hw: pointer to the hw struct
4355 * @credit: BW limit credits (0 = disabled)
4356 * @max_credit: Max BW limit credits
4357 * @cmd_details: pointer to command details structure or NULL
4359 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4360 u16 seid, u16 credit, u8 max_credit,
4361 struct i40e_asq_cmd_details *cmd_details)
4363 struct i40e_aq_desc desc;
4364 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4365 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4366 enum i40e_status_code status;
4368 i40e_fill_default_direct_cmd_desc(&desc,
4369 i40e_aqc_opc_configure_vsi_bw_limit);
4371 cmd->vsi_seid = CPU_TO_LE16(seid);
4372 cmd->credit = CPU_TO_LE16(credit);
4373 cmd->max_credit = max_credit;
4375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4381 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4382 * @hw: pointer to the hw struct
4383 * @seid: switching component seid
4384 * @credit: BW limit credits (0 = disabled)
4385 * @max_bw: Max BW limit credits
4386 * @cmd_details: pointer to command details structure or NULL
4388 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4389 u16 seid, u16 credit, u8 max_bw,
4390 struct i40e_asq_cmd_details *cmd_details)
4392 struct i40e_aq_desc desc;
4393 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4394 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4395 enum i40e_status_code status;
4397 i40e_fill_default_direct_cmd_desc(&desc,
4398 i40e_aqc_opc_configure_switching_comp_bw_limit);
4400 cmd->seid = CPU_TO_LE16(seid);
4401 cmd->credit = CPU_TO_LE16(credit);
4402 cmd->max_bw = max_bw;
4404 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4410 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4411 * @hw: pointer to the hw struct
4413 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4414 * @cmd_details: pointer to command details structure or NULL
4416 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4418 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4419 struct i40e_asq_cmd_details *cmd_details)
4421 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4422 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4427 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4428 * @hw: pointer to the hw struct
4430 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4431 * @cmd_details: pointer to command details structure or NULL
4433 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4435 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4436 struct i40e_asq_cmd_details *cmd_details)
4438 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4439 i40e_aqc_opc_configure_vsi_tc_bw,
4444 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4445 * @hw: pointer to the hw struct
4446 * @seid: seid of the switching component
4447 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4448 * @cmd_details: pointer to command details structure or NULL
4450 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4451 struct i40e_hw *hw, u16 seid,
4452 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4453 struct i40e_asq_cmd_details *cmd_details)
4455 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4456 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4461 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4462 * @hw: pointer to the hw struct
4463 * @seid: seid of the VSI
4464 * @bw_data: Buffer to hold VSI BW configuration
4465 * @cmd_details: pointer to command details structure or NULL
4467 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4469 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4470 struct i40e_asq_cmd_details *cmd_details)
4472 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4473 i40e_aqc_opc_query_vsi_bw_config,
4478 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4479 * @hw: pointer to the hw struct
4480 * @seid: seid of the VSI
4481 * @bw_data: Buffer to hold VSI BW configuration per TC
4482 * @cmd_details: pointer to command details structure or NULL
4484 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4486 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4487 struct i40e_asq_cmd_details *cmd_details)
4489 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4490 i40e_aqc_opc_query_vsi_ets_sla_config,
4495 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4496 * @hw: pointer to the hw struct
4497 * @seid: seid of the switching component
4498 * @bw_data: Buffer to hold switching component's per TC BW config
4499 * @cmd_details: pointer to command details structure or NULL
4501 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4503 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4504 struct i40e_asq_cmd_details *cmd_details)
4506 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4507 i40e_aqc_opc_query_switching_comp_ets_config,
4512 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4513 * @hw: pointer to the hw struct
4514 * @seid: seid of the VSI or switching component connected to Physical Port
4515 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4516 * @cmd_details: pointer to command details structure or NULL
4518 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4520 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4521 struct i40e_asq_cmd_details *cmd_details)
4523 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4524 i40e_aqc_opc_query_port_ets_config,
4529 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4530 * @hw: pointer to the hw struct
4531 * @seid: seid of the switching component
4532 * @bw_data: Buffer to hold switching component's BW configuration
4533 * @cmd_details: pointer to command details structure or NULL
4535 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4537 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4538 struct i40e_asq_cmd_details *cmd_details)
4540 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4541 i40e_aqc_opc_query_switching_comp_bw_config,
4546 * i40e_validate_filter_settings
4547 * @hw: pointer to the hardware structure
4548 * @settings: Filter control settings
4550 * Check and validate the filter control settings passed.
4551 * The function checks for the valid filter/context sizes being
4552 * passed for FCoE and PE.
4554 * Returns I40E_SUCCESS if the values passed are valid and within
4555 * range else returns an error.
4557 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4558 struct i40e_filter_control_settings *settings)
4560 u32 fcoe_cntx_size, fcoe_filt_size;
4561 u32 pe_cntx_size, pe_filt_size;
4566 /* Validate FCoE settings passed */
4567 switch (settings->fcoe_filt_num) {
4568 case I40E_HASH_FILTER_SIZE_1K:
4569 case I40E_HASH_FILTER_SIZE_2K:
4570 case I40E_HASH_FILTER_SIZE_4K:
4571 case I40E_HASH_FILTER_SIZE_8K:
4572 case I40E_HASH_FILTER_SIZE_16K:
4573 case I40E_HASH_FILTER_SIZE_32K:
4574 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4575 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4578 return I40E_ERR_PARAM;
4581 switch (settings->fcoe_cntx_num) {
4582 case I40E_DMA_CNTX_SIZE_512:
4583 case I40E_DMA_CNTX_SIZE_1K:
4584 case I40E_DMA_CNTX_SIZE_2K:
4585 case I40E_DMA_CNTX_SIZE_4K:
4586 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4587 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4590 return I40E_ERR_PARAM;
4593 /* Validate PE settings passed */
4594 switch (settings->pe_filt_num) {
4595 case I40E_HASH_FILTER_SIZE_1K:
4596 case I40E_HASH_FILTER_SIZE_2K:
4597 case I40E_HASH_FILTER_SIZE_4K:
4598 case I40E_HASH_FILTER_SIZE_8K:
4599 case I40E_HASH_FILTER_SIZE_16K:
4600 case I40E_HASH_FILTER_SIZE_32K:
4601 case I40E_HASH_FILTER_SIZE_64K:
4602 case I40E_HASH_FILTER_SIZE_128K:
4603 case I40E_HASH_FILTER_SIZE_256K:
4604 case I40E_HASH_FILTER_SIZE_512K:
4605 case I40E_HASH_FILTER_SIZE_1M:
4606 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4607 pe_filt_size <<= (u32)settings->pe_filt_num;
4610 return I40E_ERR_PARAM;
4613 switch (settings->pe_cntx_num) {
4614 case I40E_DMA_CNTX_SIZE_512:
4615 case I40E_DMA_CNTX_SIZE_1K:
4616 case I40E_DMA_CNTX_SIZE_2K:
4617 case I40E_DMA_CNTX_SIZE_4K:
4618 case I40E_DMA_CNTX_SIZE_8K:
4619 case I40E_DMA_CNTX_SIZE_16K:
4620 case I40E_DMA_CNTX_SIZE_32K:
4621 case I40E_DMA_CNTX_SIZE_64K:
4622 case I40E_DMA_CNTX_SIZE_128K:
4623 case I40E_DMA_CNTX_SIZE_256K:
4624 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4625 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4628 return I40E_ERR_PARAM;
4631 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4632 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4633 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4634 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4635 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4636 return I40E_ERR_INVALID_SIZE;
4638 return I40E_SUCCESS;
4642 * i40e_set_filter_control
4643 * @hw: pointer to the hardware structure
4644 * @settings: Filter control settings
4646 * Set the Queue Filters for PE/FCoE and enable filters required
4647 * for a single PF. It is expected that these settings are programmed
4648 * at the driver initialization time.
4650 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4651 struct i40e_filter_control_settings *settings)
4653 enum i40e_status_code ret = I40E_SUCCESS;
4654 u32 hash_lut_size = 0;
4658 return I40E_ERR_PARAM;
4660 /* Validate the input settings */
4661 ret = i40e_validate_filter_settings(hw, settings);
4665 /* Read the PF Queue Filter control register */
4666 val = rd32(hw, I40E_PFQF_CTL_0);
4668 /* Program required PE hash buckets for the PF */
4669 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4670 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4671 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4672 /* Program required PE contexts for the PF */
4673 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4674 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4675 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4677 /* Program required FCoE hash buckets for the PF */
4678 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4679 val |= ((u32)settings->fcoe_filt_num <<
4680 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4681 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4682 /* Program required FCoE DDP contexts for the PF */
4683 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4684 val |= ((u32)settings->fcoe_cntx_num <<
4685 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4686 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4688 /* Program Hash LUT size for the PF */
4689 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4690 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4692 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4693 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4695 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4696 if (settings->enable_fdir)
4697 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4698 if (settings->enable_ethtype)
4699 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4700 if (settings->enable_macvlan)
4701 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4703 wr32(hw, I40E_PFQF_CTL_0, val);
4705 return I40E_SUCCESS;
4709 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4710 * @hw: pointer to the hw struct
4711 * @mac_addr: MAC address to use in the filter
4712 * @ethtype: Ethertype to use in the filter
4713 * @flags: Flags that needs to be applied to the filter
4714 * @vsi_seid: seid of the control VSI
4715 * @queue: VSI queue number to send the packet to
4716 * @is_add: Add control packet filter if True else remove
4717 * @stats: Structure to hold information on control filter counts
4718 * @cmd_details: pointer to command details structure or NULL
4720 * This command will Add or Remove control packet filter for a control VSI.
4721 * In return it will update the total number of perfect filter count in
4724 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4725 u8 *mac_addr, u16 ethtype, u16 flags,
4726 u16 vsi_seid, u16 queue, bool is_add,
4727 struct i40e_control_filter_stats *stats,
4728 struct i40e_asq_cmd_details *cmd_details)
4730 struct i40e_aq_desc desc;
4731 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4732 (struct i40e_aqc_add_remove_control_packet_filter *)
4734 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4735 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4737 enum i40e_status_code status;
4740 return I40E_ERR_PARAM;
4743 i40e_fill_default_direct_cmd_desc(&desc,
4744 i40e_aqc_opc_add_control_packet_filter);
4745 cmd->queue = CPU_TO_LE16(queue);
4747 i40e_fill_default_direct_cmd_desc(&desc,
4748 i40e_aqc_opc_remove_control_packet_filter);
4752 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4753 I40E_NONDMA_TO_NONDMA);
4755 cmd->etype = CPU_TO_LE16(ethtype);
4756 cmd->flags = CPU_TO_LE16(flags);
4757 cmd->seid = CPU_TO_LE16(vsi_seid);
4759 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4761 if (!status && stats) {
4762 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4763 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4764 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4765 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4772 * i40e_aq_add_cloud_filters
4773 * @hw: pointer to the hardware structure
4774 * @seid: VSI seid to add cloud filters from
4775 * @filters: Buffer which contains the filters to be added
4776 * @filter_count: number of filters contained in the buffer
4778 * Set the cloud filters for a given VSI. The contents of the
4779 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4780 * in by the caller of the function.
4783 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4785 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4788 struct i40e_aq_desc desc;
4789 struct i40e_aqc_add_remove_cloud_filters *cmd =
4790 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4792 enum i40e_status_code status;
4794 i40e_fill_default_direct_cmd_desc(&desc,
4795 i40e_aqc_opc_add_cloud_filters);
4797 buff_len = filter_count * sizeof(*filters);
4798 desc.datalen = CPU_TO_LE16(buff_len);
4799 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4800 cmd->num_filters = filter_count;
4801 cmd->seid = CPU_TO_LE16(seid);
4803 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4809 * i40e_aq_remove_cloud_filters
4810 * @hw: pointer to the hardware structure
4811 * @seid: VSI seid to remove cloud filters from
4812 * @filters: Buffer which contains the filters to be removed
4813 * @filter_count: number of filters contained in the buffer
4815 * Remove the cloud filters for a given VSI. The contents of the
4816 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4817 * in by the caller of the function.
4820 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4822 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4825 struct i40e_aq_desc desc;
4826 struct i40e_aqc_add_remove_cloud_filters *cmd =
4827 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4828 enum i40e_status_code status;
4831 i40e_fill_default_direct_cmd_desc(&desc,
4832 i40e_aqc_opc_remove_cloud_filters);
4834 buff_len = filter_count * sizeof(*filters);
4835 desc.datalen = CPU_TO_LE16(buff_len);
4836 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4837 cmd->num_filters = filter_count;
4838 cmd->seid = CPU_TO_LE16(seid);
4840 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4846 * i40e_aq_alternate_write
4847 * @hw: pointer to the hardware structure
4848 * @reg_addr0: address of first dword to be read
4849 * @reg_val0: value to be written under 'reg_addr0'
4850 * @reg_addr1: address of second dword to be read
4851 * @reg_val1: value to be written under 'reg_addr1'
4853 * Write one or two dwords to alternate structure. Fields are indicated
4854 * by 'reg_addr0' and 'reg_addr1' register numbers.
4857 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4858 u32 reg_addr0, u32 reg_val0,
4859 u32 reg_addr1, u32 reg_val1)
4861 struct i40e_aq_desc desc;
4862 struct i40e_aqc_alternate_write *cmd_resp =
4863 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4864 enum i40e_status_code status;
4866 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4867 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4868 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4869 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4870 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4872 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4878 * i40e_aq_alternate_write_indirect
4879 * @hw: pointer to the hardware structure
4880 * @addr: address of a first register to be modified
4881 * @dw_count: number of alternate structure fields to write
4882 * @buffer: pointer to the command buffer
4884 * Write 'dw_count' dwords from 'buffer' to alternate structure
4885 * starting at 'addr'.
4888 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4889 u32 addr, u32 dw_count, void *buffer)
4891 struct i40e_aq_desc desc;
4892 struct i40e_aqc_alternate_ind_write *cmd_resp =
4893 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4894 enum i40e_status_code status;
4897 return I40E_ERR_PARAM;
4899 /* Indirect command */
4900 i40e_fill_default_direct_cmd_desc(&desc,
4901 i40e_aqc_opc_alternate_write_indirect);
4903 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4904 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4905 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4906 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4908 cmd_resp->address = CPU_TO_LE32(addr);
4909 cmd_resp->length = CPU_TO_LE32(dw_count);
4910 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4911 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4913 status = i40e_asq_send_command(hw, &desc, buffer,
4914 I40E_LO_DWORD(4*dw_count), NULL);
4920 * i40e_aq_alternate_read
4921 * @hw: pointer to the hardware structure
4922 * @reg_addr0: address of first dword to be read
4923 * @reg_val0: pointer for data read from 'reg_addr0'
4924 * @reg_addr1: address of second dword to be read
4925 * @reg_val1: pointer for data read from 'reg_addr1'
4927 * Read one or two dwords from alternate structure. Fields are indicated
4928 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4929 * is not passed then only register at 'reg_addr0' is read.
4932 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4933 u32 reg_addr0, u32 *reg_val0,
4934 u32 reg_addr1, u32 *reg_val1)
4936 struct i40e_aq_desc desc;
4937 struct i40e_aqc_alternate_write *cmd_resp =
4938 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4939 enum i40e_status_code status;
4941 if (reg_val0 == NULL)
4942 return I40E_ERR_PARAM;
4944 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4945 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4946 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4948 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4950 if (status == I40E_SUCCESS) {
4951 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4953 if (reg_val1 != NULL)
4954 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4961 * i40e_aq_alternate_read_indirect
4962 * @hw: pointer to the hardware structure
4963 * @addr: address of the alternate structure field
4964 * @dw_count: number of alternate structure fields to read
4965 * @buffer: pointer to the command buffer
4967 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4968 * place them in 'buffer'. The buffer should be allocated by caller.
4971 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4972 u32 addr, u32 dw_count, void *buffer)
4974 struct i40e_aq_desc desc;
4975 struct i40e_aqc_alternate_ind_write *cmd_resp =
4976 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4977 enum i40e_status_code status;
4980 return I40E_ERR_PARAM;
4982 /* Indirect command */
4983 i40e_fill_default_direct_cmd_desc(&desc,
4984 i40e_aqc_opc_alternate_read_indirect);
4986 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4987 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4988 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4989 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4991 cmd_resp->address = CPU_TO_LE32(addr);
4992 cmd_resp->length = CPU_TO_LE32(dw_count);
4993 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4994 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4996 status = i40e_asq_send_command(hw, &desc, buffer,
4997 I40E_LO_DWORD(4*dw_count), NULL);
5003 * i40e_aq_alternate_clear
5004 * @hw: pointer to the HW structure.
5006 * Clear the alternate structures of the port from which the function
5010 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5012 struct i40e_aq_desc desc;
5013 enum i40e_status_code status;
5015 i40e_fill_default_direct_cmd_desc(&desc,
5016 i40e_aqc_opc_alternate_clear_port);
5018 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5024 * i40e_aq_alternate_write_done
5025 * @hw: pointer to the HW structure.
5026 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5027 * @reset_needed: indicates the SW should trigger GLOBAL reset
5029 * Indicates to the FW that alternate structures have been changed.
5032 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5033 u8 bios_mode, bool *reset_needed)
5035 struct i40e_aq_desc desc;
5036 struct i40e_aqc_alternate_write_done *cmd =
5037 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5038 enum i40e_status_code status;
5040 if (reset_needed == NULL)
5041 return I40E_ERR_PARAM;
5043 i40e_fill_default_direct_cmd_desc(&desc,
5044 i40e_aqc_opc_alternate_write_done);
5046 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5048 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5049 if (!status && reset_needed)
5050 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5051 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5057 * i40e_aq_set_oem_mode
5058 * @hw: pointer to the HW structure.
5059 * @oem_mode: the OEM mode to be used
5061 * Sets the device to a specific operating mode. Currently the only supported
5062 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5065 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5068 struct i40e_aq_desc desc;
5069 struct i40e_aqc_alternate_write_done *cmd =
5070 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5071 enum i40e_status_code status;
5073 i40e_fill_default_direct_cmd_desc(&desc,
5074 i40e_aqc_opc_alternate_set_mode);
5076 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5078 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5084 * i40e_aq_resume_port_tx
5085 * @hw: pointer to the hardware structure
5086 * @cmd_details: pointer to command details structure or NULL
5088 * Resume port's Tx traffic
5090 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5091 struct i40e_asq_cmd_details *cmd_details)
5093 struct i40e_aq_desc desc;
5094 enum i40e_status_code status;
5096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5104 * i40e_set_pci_config_data - store PCI bus info
5105 * @hw: pointer to hardware structure
5106 * @link_status: the link status word from PCI config space
5108 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5110 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5112 hw->bus.type = i40e_bus_type_pci_express;
5114 switch (link_status & I40E_PCI_LINK_WIDTH) {
5115 case I40E_PCI_LINK_WIDTH_1:
5116 hw->bus.width = i40e_bus_width_pcie_x1;
5118 case I40E_PCI_LINK_WIDTH_2:
5119 hw->bus.width = i40e_bus_width_pcie_x2;
5121 case I40E_PCI_LINK_WIDTH_4:
5122 hw->bus.width = i40e_bus_width_pcie_x4;
5124 case I40E_PCI_LINK_WIDTH_8:
5125 hw->bus.width = i40e_bus_width_pcie_x8;
5128 hw->bus.width = i40e_bus_width_unknown;
5132 switch (link_status & I40E_PCI_LINK_SPEED) {
5133 case I40E_PCI_LINK_SPEED_2500:
5134 hw->bus.speed = i40e_bus_speed_2500;
5136 case I40E_PCI_LINK_SPEED_5000:
5137 hw->bus.speed = i40e_bus_speed_5000;
5139 case I40E_PCI_LINK_SPEED_8000:
5140 hw->bus.speed = i40e_bus_speed_8000;
5143 hw->bus.speed = i40e_bus_speed_unknown;
5149 * i40e_read_bw_from_alt_ram
5150 * @hw: pointer to the hardware structure
5151 * @max_bw: pointer for max_bw read
5152 * @min_bw: pointer for min_bw read
5153 * @min_valid: pointer for bool that is true if min_bw is a valid value
5154 * @max_valid: pointer for bool that is true if max_bw is a valid value
5156 * Read bw from the alternate ram for the given pf
5158 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5159 u32 *max_bw, u32 *min_bw,
5160 bool *min_valid, bool *max_valid)
5162 enum i40e_status_code status;
5163 u32 max_bw_addr, min_bw_addr;
5165 /* Calculate the address of the min/max bw registers */
5166 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5167 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5168 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5169 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5170 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5171 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5173 /* Read the bandwidths from alt ram */
5174 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5175 min_bw_addr, min_bw);
5177 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5182 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5191 * i40e_aq_configure_partition_bw
5192 * @hw: pointer to the hardware structure
5193 * @bw_data: Buffer holding valid pfs and bw limits
5194 * @cmd_details: pointer to command details
5196 * Configure partitions guaranteed/max bw
5198 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5199 struct i40e_aqc_configure_partition_bw_data *bw_data,
5200 struct i40e_asq_cmd_details *cmd_details)
5202 enum i40e_status_code status;
5203 struct i40e_aq_desc desc;
5204 u16 bwd_size = sizeof(*bw_data);
5206 i40e_fill_default_direct_cmd_desc(&desc,
5207 i40e_aqc_opc_configure_partition_bw);
5209 /* Indirect command */
5210 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5211 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5213 if (bwd_size > I40E_AQ_LARGE_BUF)
5214 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5216 desc.datalen = CPU_TO_LE16(bwd_size);
5218 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5222 #endif /* PF_DRIVER */
5226 * i40e_aq_send_msg_to_pf
5227 * @hw: pointer to the hardware structure
5228 * @v_opcode: opcodes for VF-PF communication
5229 * @v_retval: return error code
5230 * @msg: pointer to the msg buffer
5231 * @msglen: msg length
5232 * @cmd_details: pointer to command details
5234 * Send message to PF driver using admin queue. By default, this message
5235 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5236 * completion before returning.
5238 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5239 enum i40e_virtchnl_ops v_opcode,
5240 enum i40e_status_code v_retval,
5241 u8 *msg, u16 msglen,
5242 struct i40e_asq_cmd_details *cmd_details)
5244 struct i40e_aq_desc desc;
5245 struct i40e_asq_cmd_details details;
5246 enum i40e_status_code status;
5248 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5249 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5250 desc.cookie_high = CPU_TO_LE32(v_opcode);
5251 desc.cookie_low = CPU_TO_LE32(v_retval);
5253 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5254 | I40E_AQ_FLAG_RD));
5255 if (msglen > I40E_AQ_LARGE_BUF)
5256 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5257 desc.datalen = CPU_TO_LE16(msglen);
5260 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5261 details.async = true;
5262 cmd_details = &details;
5264 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5265 msglen, cmd_details);
5270 * i40e_vf_parse_hw_config
5271 * @hw: pointer to the hardware structure
5272 * @msg: pointer to the virtual channel VF resource structure
5274 * Given a VF resource message from the PF, populate the hw struct
5275 * with appropriate information.
5277 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5278 struct i40e_virtchnl_vf_resource *msg)
5280 struct i40e_virtchnl_vsi_resource *vsi_res;
5283 vsi_res = &msg->vsi_res[0];
5285 hw->dev_caps.num_vsis = msg->num_vsis;
5286 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5287 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5288 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5289 hw->dev_caps.dcb = msg->vf_offload_flags &
5290 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5291 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5292 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5293 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5294 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5295 for (i = 0; i < msg->num_vsis; i++) {
5296 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5297 i40e_memcpy(hw->mac.perm_addr,
5298 vsi_res->default_mac_addr,
5299 I40E_ETH_LENGTH_OF_ADDRESS,
5300 I40E_NONDMA_TO_NONDMA);
5301 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5302 I40E_ETH_LENGTH_OF_ADDRESS,
5303 I40E_NONDMA_TO_NONDMA);
5311 * @hw: pointer to the hardware structure
5313 * Send a VF_RESET message to the PF. Does not wait for response from PF
5314 * as none will be forthcoming. Immediately after calling this function,
5315 * the admin queue should be shut down and (optionally) reinitialized.
5317 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5319 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5320 I40E_SUCCESS, NULL, 0, NULL);
5322 #endif /* VF_DRIVER */