1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 case I40E_DEV_ID_QSFP_I_X722:
85 hw->mac.type = I40E_MAC_X722;
89 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
90 case I40E_DEV_ID_X722_VF:
91 case I40E_DEV_ID_X722_VF_HV:
92 #ifdef X722_A0_SUPPORT
93 case I40E_DEV_ID_X722_A0_VF:
95 hw->mac.type = I40E_MAC_X722_VF;
97 #endif /* INTEGRATED_VF || VF_DRIVER */
98 #endif /* X722_SUPPORT */
99 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
101 case I40E_DEV_ID_VF_HV:
102 hw->mac.type = I40E_MAC_VF;
106 hw->mac.type = I40E_MAC_GENERIC;
110 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
113 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
114 hw->mac.type, status);
118 #ifndef I40E_NDIS_SUPPORT
120 * i40e_aq_str - convert AQ err code to a string
121 * @hw: pointer to the HW structure
122 * @aq_err: the AQ error code to convert
124 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
129 case I40E_AQ_RC_EPERM:
130 return "I40E_AQ_RC_EPERM";
131 case I40E_AQ_RC_ENOENT:
132 return "I40E_AQ_RC_ENOENT";
133 case I40E_AQ_RC_ESRCH:
134 return "I40E_AQ_RC_ESRCH";
135 case I40E_AQ_RC_EINTR:
136 return "I40E_AQ_RC_EINTR";
138 return "I40E_AQ_RC_EIO";
139 case I40E_AQ_RC_ENXIO:
140 return "I40E_AQ_RC_ENXIO";
141 case I40E_AQ_RC_E2BIG:
142 return "I40E_AQ_RC_E2BIG";
143 case I40E_AQ_RC_EAGAIN:
144 return "I40E_AQ_RC_EAGAIN";
145 case I40E_AQ_RC_ENOMEM:
146 return "I40E_AQ_RC_ENOMEM";
147 case I40E_AQ_RC_EACCES:
148 return "I40E_AQ_RC_EACCES";
149 case I40E_AQ_RC_EFAULT:
150 return "I40E_AQ_RC_EFAULT";
151 case I40E_AQ_RC_EBUSY:
152 return "I40E_AQ_RC_EBUSY";
153 case I40E_AQ_RC_EEXIST:
154 return "I40E_AQ_RC_EEXIST";
155 case I40E_AQ_RC_EINVAL:
156 return "I40E_AQ_RC_EINVAL";
157 case I40E_AQ_RC_ENOTTY:
158 return "I40E_AQ_RC_ENOTTY";
159 case I40E_AQ_RC_ENOSPC:
160 return "I40E_AQ_RC_ENOSPC";
161 case I40E_AQ_RC_ENOSYS:
162 return "I40E_AQ_RC_ENOSYS";
163 case I40E_AQ_RC_ERANGE:
164 return "I40E_AQ_RC_ERANGE";
165 case I40E_AQ_RC_EFLUSHED:
166 return "I40E_AQ_RC_EFLUSHED";
167 case I40E_AQ_RC_BAD_ADDR:
168 return "I40E_AQ_RC_BAD_ADDR";
169 case I40E_AQ_RC_EMODE:
170 return "I40E_AQ_RC_EMODE";
171 case I40E_AQ_RC_EFBIG:
172 return "I40E_AQ_RC_EFBIG";
175 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
180 * i40e_stat_str - convert status err code to a string
181 * @hw: pointer to the HW structure
182 * @stat_err: the status error code to convert
184 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
190 return "I40E_ERR_NVM";
191 case I40E_ERR_NVM_CHECKSUM:
192 return "I40E_ERR_NVM_CHECKSUM";
194 return "I40E_ERR_PHY";
195 case I40E_ERR_CONFIG:
196 return "I40E_ERR_CONFIG";
198 return "I40E_ERR_PARAM";
199 case I40E_ERR_MAC_TYPE:
200 return "I40E_ERR_MAC_TYPE";
201 case I40E_ERR_UNKNOWN_PHY:
202 return "I40E_ERR_UNKNOWN_PHY";
203 case I40E_ERR_LINK_SETUP:
204 return "I40E_ERR_LINK_SETUP";
205 case I40E_ERR_ADAPTER_STOPPED:
206 return "I40E_ERR_ADAPTER_STOPPED";
207 case I40E_ERR_INVALID_MAC_ADDR:
208 return "I40E_ERR_INVALID_MAC_ADDR";
209 case I40E_ERR_DEVICE_NOT_SUPPORTED:
210 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
211 case I40E_ERR_MASTER_REQUESTS_PENDING:
212 return "I40E_ERR_MASTER_REQUESTS_PENDING";
213 case I40E_ERR_INVALID_LINK_SETTINGS:
214 return "I40E_ERR_INVALID_LINK_SETTINGS";
215 case I40E_ERR_AUTONEG_NOT_COMPLETE:
216 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
217 case I40E_ERR_RESET_FAILED:
218 return "I40E_ERR_RESET_FAILED";
219 case I40E_ERR_SWFW_SYNC:
220 return "I40E_ERR_SWFW_SYNC";
221 case I40E_ERR_NO_AVAILABLE_VSI:
222 return "I40E_ERR_NO_AVAILABLE_VSI";
223 case I40E_ERR_NO_MEMORY:
224 return "I40E_ERR_NO_MEMORY";
225 case I40E_ERR_BAD_PTR:
226 return "I40E_ERR_BAD_PTR";
227 case I40E_ERR_RING_FULL:
228 return "I40E_ERR_RING_FULL";
229 case I40E_ERR_INVALID_PD_ID:
230 return "I40E_ERR_INVALID_PD_ID";
231 case I40E_ERR_INVALID_QP_ID:
232 return "I40E_ERR_INVALID_QP_ID";
233 case I40E_ERR_INVALID_CQ_ID:
234 return "I40E_ERR_INVALID_CQ_ID";
235 case I40E_ERR_INVALID_CEQ_ID:
236 return "I40E_ERR_INVALID_CEQ_ID";
237 case I40E_ERR_INVALID_AEQ_ID:
238 return "I40E_ERR_INVALID_AEQ_ID";
239 case I40E_ERR_INVALID_SIZE:
240 return "I40E_ERR_INVALID_SIZE";
241 case I40E_ERR_INVALID_ARP_INDEX:
242 return "I40E_ERR_INVALID_ARP_INDEX";
243 case I40E_ERR_INVALID_FPM_FUNC_ID:
244 return "I40E_ERR_INVALID_FPM_FUNC_ID";
245 case I40E_ERR_QP_INVALID_MSG_SIZE:
246 return "I40E_ERR_QP_INVALID_MSG_SIZE";
247 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
248 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
249 case I40E_ERR_INVALID_FRAG_COUNT:
250 return "I40E_ERR_INVALID_FRAG_COUNT";
251 case I40E_ERR_QUEUE_EMPTY:
252 return "I40E_ERR_QUEUE_EMPTY";
253 case I40E_ERR_INVALID_ALIGNMENT:
254 return "I40E_ERR_INVALID_ALIGNMENT";
255 case I40E_ERR_FLUSHED_QUEUE:
256 return "I40E_ERR_FLUSHED_QUEUE";
257 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
258 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
259 case I40E_ERR_INVALID_IMM_DATA_SIZE:
260 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
261 case I40E_ERR_TIMEOUT:
262 return "I40E_ERR_TIMEOUT";
263 case I40E_ERR_OPCODE_MISMATCH:
264 return "I40E_ERR_OPCODE_MISMATCH";
265 case I40E_ERR_CQP_COMPL_ERROR:
266 return "I40E_ERR_CQP_COMPL_ERROR";
267 case I40E_ERR_INVALID_VF_ID:
268 return "I40E_ERR_INVALID_VF_ID";
269 case I40E_ERR_INVALID_HMCFN_ID:
270 return "I40E_ERR_INVALID_HMCFN_ID";
271 case I40E_ERR_BACKING_PAGE_ERROR:
272 return "I40E_ERR_BACKING_PAGE_ERROR";
273 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
274 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
275 case I40E_ERR_INVALID_PBLE_INDEX:
276 return "I40E_ERR_INVALID_PBLE_INDEX";
277 case I40E_ERR_INVALID_SD_INDEX:
278 return "I40E_ERR_INVALID_SD_INDEX";
279 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
280 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
281 case I40E_ERR_INVALID_SD_TYPE:
282 return "I40E_ERR_INVALID_SD_TYPE";
283 case I40E_ERR_MEMCPY_FAILED:
284 return "I40E_ERR_MEMCPY_FAILED";
285 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
286 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
287 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
288 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
289 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
290 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
291 case I40E_ERR_SRQ_ENABLED:
292 return "I40E_ERR_SRQ_ENABLED";
293 case I40E_ERR_ADMIN_QUEUE_ERROR:
294 return "I40E_ERR_ADMIN_QUEUE_ERROR";
295 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
296 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
297 case I40E_ERR_BUF_TOO_SHORT:
298 return "I40E_ERR_BUF_TOO_SHORT";
299 case I40E_ERR_ADMIN_QUEUE_FULL:
300 return "I40E_ERR_ADMIN_QUEUE_FULL";
301 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
302 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
303 case I40E_ERR_BAD_IWARP_CQE:
304 return "I40E_ERR_BAD_IWARP_CQE";
305 case I40E_ERR_NVM_BLANK_MODE:
306 return "I40E_ERR_NVM_BLANK_MODE";
307 case I40E_ERR_NOT_IMPLEMENTED:
308 return "I40E_ERR_NOT_IMPLEMENTED";
309 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
310 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
311 case I40E_ERR_DIAG_TEST_FAILED:
312 return "I40E_ERR_DIAG_TEST_FAILED";
313 case I40E_ERR_NOT_READY:
314 return "I40E_ERR_NOT_READY";
315 case I40E_NOT_SUPPORTED:
316 return "I40E_NOT_SUPPORTED";
317 case I40E_ERR_FIRMWARE_API_VERSION:
318 return "I40E_ERR_FIRMWARE_API_VERSION";
321 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
325 #endif /* I40E_NDIS_SUPPORT */
328 * @hw: debug mask related to admin queue
330 * @desc: pointer to admin queue descriptor
331 * @buffer: pointer to command buffer
332 * @buf_len: max length of buffer
334 * Dumps debug log about adminq command with descriptor contents.
336 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
337 void *buffer, u16 buf_len)
339 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
340 u16 len = LE16_TO_CPU(aq_desc->datalen);
341 u8 *buf = (u8 *)buffer;
344 if ((!(mask & hw->debug_mask)) || (desc == NULL))
348 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
349 LE16_TO_CPU(aq_desc->opcode),
350 LE16_TO_CPU(aq_desc->flags),
351 LE16_TO_CPU(aq_desc->datalen),
352 LE16_TO_CPU(aq_desc->retval));
353 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
354 LE32_TO_CPU(aq_desc->cookie_high),
355 LE32_TO_CPU(aq_desc->cookie_low));
356 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
357 LE32_TO_CPU(aq_desc->params.internal.param0),
358 LE32_TO_CPU(aq_desc->params.internal.param1));
359 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
360 LE32_TO_CPU(aq_desc->params.external.addr_high),
361 LE32_TO_CPU(aq_desc->params.external.addr_low));
363 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
364 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
367 /* write the full 16-byte chunks */
368 for (i = 0; i < (len - 16); i += 16)
370 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
371 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
372 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
373 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
374 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
375 /* the most we could have left is 16 bytes, pad with zeros */
381 memset(d_buf, 0, sizeof(d_buf));
382 for (j = 0; i < len; j++, i++)
385 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
386 i_sav, d_buf[0], d_buf[1],
388 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
389 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
390 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
396 * i40e_check_asq_alive
397 * @hw: pointer to the hw struct
399 * Returns true if Queue is enabled else false.
401 bool i40e_check_asq_alive(struct i40e_hw *hw)
407 return !!(rd32(hw, hw->aq.asq.len) &
408 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 return !!(rd32(hw, hw->aq.asq.len) &
411 I40E_PF_ATQLEN_ATQENABLE_MASK);
412 #endif /* INTEGRATED_VF */
413 #endif /* PF_DRIVER */
417 return !!(rd32(hw, hw->aq.asq.len) &
418 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 return !!(rd32(hw, hw->aq.asq.len) &
421 I40E_VF_ATQLEN1_ATQENABLE_MASK);
422 #endif /* INTEGRATED_VF */
423 #endif /* VF_DRIVER */
428 * i40e_aq_queue_shutdown
429 * @hw: pointer to the hw struct
430 * @unloading: is the driver unloading itself
432 * Tell the Firmware that we're shutting down the AdminQ and whether
433 * or not the driver is unloading as well.
435 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
438 struct i40e_aq_desc desc;
439 struct i40e_aqc_queue_shutdown *cmd =
440 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
441 enum i40e_status_code status;
443 i40e_fill_default_direct_cmd_desc(&desc,
444 i40e_aqc_opc_queue_shutdown);
447 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
448 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
455 * i40e_aq_get_set_rss_lut
456 * @hw: pointer to the hardware structure
457 * @vsi_id: vsi fw index
458 * @pf_lut: for PF table set true, for VSI table set false
459 * @lut: pointer to the lut buffer provided by the caller
460 * @lut_size: size of the lut buffer
461 * @set: set true to set the table, false to get the table
463 * Internal function to get or set RSS look up table
465 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
466 u16 vsi_id, bool pf_lut,
467 u8 *lut, u16 lut_size,
470 enum i40e_status_code status;
471 struct i40e_aq_desc desc;
472 struct i40e_aqc_get_set_rss_lut *cmd_resp =
473 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
476 i40e_fill_default_direct_cmd_desc(&desc,
477 i40e_aqc_opc_set_rss_lut);
479 i40e_fill_default_direct_cmd_desc(&desc,
480 i40e_aqc_opc_get_rss_lut);
482 /* Indirect command */
483 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
484 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
487 CPU_TO_LE16((u16)((vsi_id <<
488 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
489 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
490 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
493 cmd_resp->flags |= CPU_TO_LE16((u16)
494 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
495 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
496 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
498 cmd_resp->flags |= CPU_TO_LE16((u16)
499 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
500 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
501 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
503 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
509 * i40e_aq_get_rss_lut
510 * @hw: pointer to the hardware structure
511 * @vsi_id: vsi fw index
512 * @pf_lut: for PF table set true, for VSI table set false
513 * @lut: pointer to the lut buffer provided by the caller
514 * @lut_size: size of the lut buffer
516 * get the RSS lookup table, PF or VSI type
518 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
519 bool pf_lut, u8 *lut, u16 lut_size)
521 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
526 * i40e_aq_set_rss_lut
527 * @hw: pointer to the hardware structure
528 * @vsi_id: vsi fw index
529 * @pf_lut: for PF table set true, for VSI table set false
530 * @lut: pointer to the lut buffer provided by the caller
531 * @lut_size: size of the lut buffer
533 * set the RSS lookup table, PF or VSI type
535 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
536 bool pf_lut, u8 *lut, u16 lut_size)
538 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
542 * i40e_aq_get_set_rss_key
543 * @hw: pointer to the hw struct
544 * @vsi_id: vsi fw index
545 * @key: pointer to key info struct
546 * @set: set true to set the key, false to get the key
548 * get the RSS key per VSI
550 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
552 struct i40e_aqc_get_set_rss_key_data *key,
555 enum i40e_status_code status;
556 struct i40e_aq_desc desc;
557 struct i40e_aqc_get_set_rss_key *cmd_resp =
558 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
559 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
562 i40e_fill_default_direct_cmd_desc(&desc,
563 i40e_aqc_opc_set_rss_key);
565 i40e_fill_default_direct_cmd_desc(&desc,
566 i40e_aqc_opc_get_rss_key);
568 /* Indirect command */
569 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
570 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
573 CPU_TO_LE16((u16)((vsi_id <<
574 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
575 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
576 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
578 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
584 * i40e_aq_get_rss_key
585 * @hw: pointer to the hw struct
586 * @vsi_id: vsi fw index
587 * @key: pointer to key info struct
590 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
592 struct i40e_aqc_get_set_rss_key_data *key)
594 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
598 * i40e_aq_set_rss_key
599 * @hw: pointer to the hw struct
600 * @vsi_id: vsi fw index
601 * @key: pointer to key info struct
603 * set the RSS key per VSI
605 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
607 struct i40e_aqc_get_set_rss_key_data *key)
609 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
611 #endif /* X722_SUPPORT */
613 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
614 * hardware to a bit-field that can be used by SW to more easily determine the
617 * Macros are used to shorten the table lines and make this table human
620 * We store the PTYPE in the top byte of the bit field - this is just so that
621 * we can check that the table doesn't have a row missing, as the index into
622 * the table should be the PTYPE.
626 * IF NOT i40e_ptype_lookup[ptype].known
629 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
630 * Use the rest of the fields to look at the tunnels, inner protocols, etc
632 * Use the enum i40e_rx_l2_ptype to decode the packet type
636 /* macro to make the table lines short */
637 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
640 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
641 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
642 I40E_RX_PTYPE_##OUTER_FRAG, \
643 I40E_RX_PTYPE_TUNNEL_##T, \
644 I40E_RX_PTYPE_TUNNEL_END_##TE, \
645 I40E_RX_PTYPE_##TEF, \
646 I40E_RX_PTYPE_INNER_PROT_##I, \
647 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
649 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
650 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
652 /* shorter macros makes the table fit but are terse */
653 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
654 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
655 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
657 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
658 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
659 /* L2 Packet types */
660 I40E_PTT_UNUSED_ENTRY(0),
661 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
663 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
664 I40E_PTT_UNUSED_ENTRY(4),
665 I40E_PTT_UNUSED_ENTRY(5),
666 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
667 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
668 I40E_PTT_UNUSED_ENTRY(8),
669 I40E_PTT_UNUSED_ENTRY(9),
670 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
671 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
672 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
680 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
683 /* Non Tunneled IPv4 */
684 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
685 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
686 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(25),
688 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
689 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
690 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
693 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
694 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
695 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(32),
697 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
698 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
699 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
702 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
703 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
704 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(39),
706 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
707 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
708 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
710 /* IPv4 --> GRE/NAT */
711 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
713 /* IPv4 --> GRE/NAT --> IPv4 */
714 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
715 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
716 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(47),
718 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
719 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
720 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
722 /* IPv4 --> GRE/NAT --> IPv6 */
723 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
724 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
725 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(54),
727 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
728 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
729 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
731 /* IPv4 --> GRE/NAT --> MAC */
732 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
734 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
735 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
736 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
737 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(62),
739 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
740 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
741 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
743 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
744 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
745 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
746 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(69),
748 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
749 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
750 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
752 /* IPv4 --> GRE/NAT --> MAC/VLAN */
753 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
755 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
756 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
757 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
758 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
759 I40E_PTT_UNUSED_ENTRY(77),
760 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
761 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
762 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
764 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
765 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
766 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
767 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(84),
769 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
770 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
771 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
773 /* Non Tunneled IPv6 */
774 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
775 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
776 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
777 I40E_PTT_UNUSED_ENTRY(91),
778 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
779 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
780 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
783 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
784 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
785 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
786 I40E_PTT_UNUSED_ENTRY(98),
787 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
788 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
789 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
792 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
793 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
794 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
795 I40E_PTT_UNUSED_ENTRY(105),
796 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
797 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
798 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
800 /* IPv6 --> GRE/NAT */
801 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
803 /* IPv6 --> GRE/NAT -> IPv4 */
804 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
805 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
806 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
807 I40E_PTT_UNUSED_ENTRY(113),
808 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
809 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
810 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
812 /* IPv6 --> GRE/NAT -> IPv6 */
813 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
814 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
815 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
816 I40E_PTT_UNUSED_ENTRY(120),
817 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
818 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
819 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
821 /* IPv6 --> GRE/NAT -> MAC */
822 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
824 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
825 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
826 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
827 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(128),
829 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
830 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
831 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
833 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
834 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
835 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
836 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
837 I40E_PTT_UNUSED_ENTRY(135),
838 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
839 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
840 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
842 /* IPv6 --> GRE/NAT -> MAC/VLAN */
843 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
845 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
846 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
847 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
848 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
849 I40E_PTT_UNUSED_ENTRY(143),
850 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
851 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
852 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
854 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
855 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
856 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
857 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
858 I40E_PTT_UNUSED_ENTRY(150),
859 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
860 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
861 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
864 I40E_PTT_UNUSED_ENTRY(154),
865 I40E_PTT_UNUSED_ENTRY(155),
866 I40E_PTT_UNUSED_ENTRY(156),
867 I40E_PTT_UNUSED_ENTRY(157),
868 I40E_PTT_UNUSED_ENTRY(158),
869 I40E_PTT_UNUSED_ENTRY(159),
871 I40E_PTT_UNUSED_ENTRY(160),
872 I40E_PTT_UNUSED_ENTRY(161),
873 I40E_PTT_UNUSED_ENTRY(162),
874 I40E_PTT_UNUSED_ENTRY(163),
875 I40E_PTT_UNUSED_ENTRY(164),
876 I40E_PTT_UNUSED_ENTRY(165),
877 I40E_PTT_UNUSED_ENTRY(166),
878 I40E_PTT_UNUSED_ENTRY(167),
879 I40E_PTT_UNUSED_ENTRY(168),
880 I40E_PTT_UNUSED_ENTRY(169),
882 I40E_PTT_UNUSED_ENTRY(170),
883 I40E_PTT_UNUSED_ENTRY(171),
884 I40E_PTT_UNUSED_ENTRY(172),
885 I40E_PTT_UNUSED_ENTRY(173),
886 I40E_PTT_UNUSED_ENTRY(174),
887 I40E_PTT_UNUSED_ENTRY(175),
888 I40E_PTT_UNUSED_ENTRY(176),
889 I40E_PTT_UNUSED_ENTRY(177),
890 I40E_PTT_UNUSED_ENTRY(178),
891 I40E_PTT_UNUSED_ENTRY(179),
893 I40E_PTT_UNUSED_ENTRY(180),
894 I40E_PTT_UNUSED_ENTRY(181),
895 I40E_PTT_UNUSED_ENTRY(182),
896 I40E_PTT_UNUSED_ENTRY(183),
897 I40E_PTT_UNUSED_ENTRY(184),
898 I40E_PTT_UNUSED_ENTRY(185),
899 I40E_PTT_UNUSED_ENTRY(186),
900 I40E_PTT_UNUSED_ENTRY(187),
901 I40E_PTT_UNUSED_ENTRY(188),
902 I40E_PTT_UNUSED_ENTRY(189),
904 I40E_PTT_UNUSED_ENTRY(190),
905 I40E_PTT_UNUSED_ENTRY(191),
906 I40E_PTT_UNUSED_ENTRY(192),
907 I40E_PTT_UNUSED_ENTRY(193),
908 I40E_PTT_UNUSED_ENTRY(194),
909 I40E_PTT_UNUSED_ENTRY(195),
910 I40E_PTT_UNUSED_ENTRY(196),
911 I40E_PTT_UNUSED_ENTRY(197),
912 I40E_PTT_UNUSED_ENTRY(198),
913 I40E_PTT_UNUSED_ENTRY(199),
915 I40E_PTT_UNUSED_ENTRY(200),
916 I40E_PTT_UNUSED_ENTRY(201),
917 I40E_PTT_UNUSED_ENTRY(202),
918 I40E_PTT_UNUSED_ENTRY(203),
919 I40E_PTT_UNUSED_ENTRY(204),
920 I40E_PTT_UNUSED_ENTRY(205),
921 I40E_PTT_UNUSED_ENTRY(206),
922 I40E_PTT_UNUSED_ENTRY(207),
923 I40E_PTT_UNUSED_ENTRY(208),
924 I40E_PTT_UNUSED_ENTRY(209),
926 I40E_PTT_UNUSED_ENTRY(210),
927 I40E_PTT_UNUSED_ENTRY(211),
928 I40E_PTT_UNUSED_ENTRY(212),
929 I40E_PTT_UNUSED_ENTRY(213),
930 I40E_PTT_UNUSED_ENTRY(214),
931 I40E_PTT_UNUSED_ENTRY(215),
932 I40E_PTT_UNUSED_ENTRY(216),
933 I40E_PTT_UNUSED_ENTRY(217),
934 I40E_PTT_UNUSED_ENTRY(218),
935 I40E_PTT_UNUSED_ENTRY(219),
937 I40E_PTT_UNUSED_ENTRY(220),
938 I40E_PTT_UNUSED_ENTRY(221),
939 I40E_PTT_UNUSED_ENTRY(222),
940 I40E_PTT_UNUSED_ENTRY(223),
941 I40E_PTT_UNUSED_ENTRY(224),
942 I40E_PTT_UNUSED_ENTRY(225),
943 I40E_PTT_UNUSED_ENTRY(226),
944 I40E_PTT_UNUSED_ENTRY(227),
945 I40E_PTT_UNUSED_ENTRY(228),
946 I40E_PTT_UNUSED_ENTRY(229),
948 I40E_PTT_UNUSED_ENTRY(230),
949 I40E_PTT_UNUSED_ENTRY(231),
950 I40E_PTT_UNUSED_ENTRY(232),
951 I40E_PTT_UNUSED_ENTRY(233),
952 I40E_PTT_UNUSED_ENTRY(234),
953 I40E_PTT_UNUSED_ENTRY(235),
954 I40E_PTT_UNUSED_ENTRY(236),
955 I40E_PTT_UNUSED_ENTRY(237),
956 I40E_PTT_UNUSED_ENTRY(238),
957 I40E_PTT_UNUSED_ENTRY(239),
959 I40E_PTT_UNUSED_ENTRY(240),
960 I40E_PTT_UNUSED_ENTRY(241),
961 I40E_PTT_UNUSED_ENTRY(242),
962 I40E_PTT_UNUSED_ENTRY(243),
963 I40E_PTT_UNUSED_ENTRY(244),
964 I40E_PTT_UNUSED_ENTRY(245),
965 I40E_PTT_UNUSED_ENTRY(246),
966 I40E_PTT_UNUSED_ENTRY(247),
967 I40E_PTT_UNUSED_ENTRY(248),
968 I40E_PTT_UNUSED_ENTRY(249),
970 I40E_PTT_UNUSED_ENTRY(250),
971 I40E_PTT_UNUSED_ENTRY(251),
972 I40E_PTT_UNUSED_ENTRY(252),
973 I40E_PTT_UNUSED_ENTRY(253),
974 I40E_PTT_UNUSED_ENTRY(254),
975 I40E_PTT_UNUSED_ENTRY(255)
980 * i40e_validate_mac_addr - Validate unicast MAC address
981 * @mac_addr: pointer to MAC address
983 * Tests a MAC address to ensure it is a valid Individual Address
985 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
987 enum i40e_status_code status = I40E_SUCCESS;
989 DEBUGFUNC("i40e_validate_mac_addr");
991 /* Broadcast addresses ARE multicast addresses
992 * Make sure it is not a multicast address
993 * Reject the zero address
995 if (I40E_IS_MULTICAST(mac_addr) ||
996 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
997 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
998 status = I40E_ERR_INVALID_MAC_ADDR;
1005 * i40e_init_shared_code - Initialize the shared code
1006 * @hw: pointer to hardware structure
1008 * This assigns the MAC type and PHY code and inits the NVM.
1009 * Does not touch the hardware. This function must be called prior to any
1010 * other function in the shared code. The i40e_hw structure should be
1011 * memset to 0 prior to calling this function. The following fields in
1012 * hw structure should be filled in prior to calling this function:
1013 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1014 * subsystem_vendor_id, and revision_id
1016 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1018 enum i40e_status_code status = I40E_SUCCESS;
1019 u32 port, ari, func_rid;
1021 DEBUGFUNC("i40e_init_shared_code");
1023 i40e_set_mac_type(hw);
1025 switch (hw->mac.type) {
1026 case I40E_MAC_XL710:
1032 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1035 hw->phy.get_link_info = true;
1037 /* Determine port number and PF number*/
1038 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1039 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1040 hw->port = (u8)port;
1041 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1042 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1043 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1045 hw->pf_id = (u8)(func_rid & 0xff);
1047 hw->pf_id = (u8)(func_rid & 0x7);
1050 if (hw->mac.type == I40E_MAC_X722)
1051 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1054 status = i40e_init_nvm(hw);
1059 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1060 * @hw: pointer to the hw struct
1061 * @flags: a return indicator of what addresses were added to the addr store
1062 * @addrs: the requestor's mac addr store
1063 * @cmd_details: pointer to command details structure or NULL
1065 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1067 struct i40e_aqc_mac_address_read_data *addrs,
1068 struct i40e_asq_cmd_details *cmd_details)
1070 struct i40e_aq_desc desc;
1071 struct i40e_aqc_mac_address_read *cmd_data =
1072 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1073 enum i40e_status_code status;
1075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1076 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1078 status = i40e_asq_send_command(hw, &desc, addrs,
1079 sizeof(*addrs), cmd_details);
1080 *flags = LE16_TO_CPU(cmd_data->command_flags);
1086 * i40e_aq_mac_address_write - Change the MAC addresses
1087 * @hw: pointer to the hw struct
1088 * @flags: indicates which MAC to be written
1089 * @mac_addr: address to write
1090 * @cmd_details: pointer to command details structure or NULL
1092 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1093 u16 flags, u8 *mac_addr,
1094 struct i40e_asq_cmd_details *cmd_details)
1096 struct i40e_aq_desc desc;
1097 struct i40e_aqc_mac_address_write *cmd_data =
1098 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1099 enum i40e_status_code status;
1101 i40e_fill_default_direct_cmd_desc(&desc,
1102 i40e_aqc_opc_mac_address_write);
1103 cmd_data->command_flags = CPU_TO_LE16(flags);
1104 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1105 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1106 ((u32)mac_addr[3] << 16) |
1107 ((u32)mac_addr[4] << 8) |
1110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1116 * i40e_get_mac_addr - get MAC address
1117 * @hw: pointer to the HW structure
1118 * @mac_addr: pointer to MAC address
1120 * Reads the adapter's MAC address from register
1122 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1124 struct i40e_aqc_mac_address_read_data addrs;
1125 enum i40e_status_code status;
1128 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1130 if (flags & I40E_AQC_LAN_ADDR_VALID)
1131 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1137 * i40e_get_port_mac_addr - get Port MAC address
1138 * @hw: pointer to the HW structure
1139 * @mac_addr: pointer to Port MAC address
1141 * Reads the adapter's Port MAC address
1143 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1145 struct i40e_aqc_mac_address_read_data addrs;
1146 enum i40e_status_code status;
1149 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1153 if (flags & I40E_AQC_PORT_ADDR_VALID)
1154 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1156 status = I40E_ERR_INVALID_MAC_ADDR;
1162 * i40e_pre_tx_queue_cfg - pre tx queue configure
1163 * @hw: pointer to the HW structure
1164 * @queue: target pf queue index
1165 * @enable: state change request
1167 * Handles hw requirement to indicate intention to enable
1168 * or disable target queue.
1170 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1172 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1176 if (abs_queue_idx >= 128) {
1177 reg_block = abs_queue_idx / 128;
1178 abs_queue_idx %= 128;
1181 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1182 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1183 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1188 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1190 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1194 * i40e_read_pba_string - Reads part number string from EEPROM
1195 * @hw: pointer to hardware structure
1196 * @pba_num: stores the part number string from the EEPROM
1197 * @pba_num_size: part number string buffer length
1199 * Reads the part number string from the EEPROM.
1201 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1204 enum i40e_status_code status = I40E_SUCCESS;
1210 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1211 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1212 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1216 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1217 if (status != I40E_SUCCESS) {
1218 DEBUGOUT("Failed to read PBA Block pointer.\n");
1222 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1223 if (status != I40E_SUCCESS) {
1224 DEBUGOUT("Failed to read PBA Block size.\n");
1228 /* Subtract one to get PBA word count (PBA Size word is included in
1232 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1233 DEBUGOUT("Buffer to small for PBA data.\n");
1234 return I40E_ERR_PARAM;
1237 for (i = 0; i < pba_size; i++) {
1238 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1239 if (status != I40E_SUCCESS) {
1240 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1244 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1245 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1247 pba_num[(pba_size * 2)] = '\0';
1253 * i40e_get_media_type - Gets media type
1254 * @hw: pointer to the hardware structure
1256 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1258 enum i40e_media_type media;
1260 switch (hw->phy.link_info.phy_type) {
1261 case I40E_PHY_TYPE_10GBASE_SR:
1262 case I40E_PHY_TYPE_10GBASE_LR:
1263 case I40E_PHY_TYPE_1000BASE_SX:
1264 case I40E_PHY_TYPE_1000BASE_LX:
1265 case I40E_PHY_TYPE_40GBASE_SR4:
1266 case I40E_PHY_TYPE_40GBASE_LR4:
1267 media = I40E_MEDIA_TYPE_FIBER;
1269 case I40E_PHY_TYPE_100BASE_TX:
1270 case I40E_PHY_TYPE_1000BASE_T:
1271 case I40E_PHY_TYPE_10GBASE_T:
1272 media = I40E_MEDIA_TYPE_BASET;
1274 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1275 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1276 case I40E_PHY_TYPE_10GBASE_CR1:
1277 case I40E_PHY_TYPE_40GBASE_CR4:
1278 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1279 case I40E_PHY_TYPE_40GBASE_AOC:
1280 case I40E_PHY_TYPE_10GBASE_AOC:
1281 media = I40E_MEDIA_TYPE_DA;
1283 case I40E_PHY_TYPE_1000BASE_KX:
1284 case I40E_PHY_TYPE_10GBASE_KX4:
1285 case I40E_PHY_TYPE_10GBASE_KR:
1286 case I40E_PHY_TYPE_40GBASE_KR4:
1287 case I40E_PHY_TYPE_20GBASE_KR2:
1288 media = I40E_MEDIA_TYPE_BACKPLANE;
1290 case I40E_PHY_TYPE_SGMII:
1291 case I40E_PHY_TYPE_XAUI:
1292 case I40E_PHY_TYPE_XFI:
1293 case I40E_PHY_TYPE_XLAUI:
1294 case I40E_PHY_TYPE_XLPPI:
1296 media = I40E_MEDIA_TYPE_UNKNOWN;
1303 #define I40E_PF_RESET_WAIT_COUNT 200
1305 * i40e_pf_reset - Reset the PF
1306 * @hw: pointer to the hardware structure
1308 * Assuming someone else has triggered a global reset,
1309 * assure the global reset is complete and then reset the PF
1311 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1318 /* Poll for Global Reset steady state in case of recent GRST.
1319 * The grst delay value is in 100ms units, and we'll wait a
1320 * couple counts longer to be sure we don't just miss the end.
1322 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1323 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1324 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1326 grst_del = grst_del * 20;
1328 for (cnt = 0; cnt < grst_del; cnt++) {
1329 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1332 i40e_msec_delay(100);
1334 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1335 DEBUGOUT("Global reset polling failed to complete.\n");
1336 return I40E_ERR_RESET_FAILED;
1339 /* Now Wait for the FW to be ready */
1340 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1341 reg = rd32(hw, I40E_GLNVM_ULD);
1342 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1343 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1344 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1345 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1346 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1349 i40e_msec_delay(10);
1351 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1352 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1353 DEBUGOUT("wait for FW Reset complete timedout\n");
1354 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1355 return I40E_ERR_RESET_FAILED;
1358 /* If there was a Global Reset in progress when we got here,
1359 * we don't need to do the PF Reset
1362 reg = rd32(hw, I40E_PFGEN_CTRL);
1363 wr32(hw, I40E_PFGEN_CTRL,
1364 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1365 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1366 reg = rd32(hw, I40E_PFGEN_CTRL);
1367 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1371 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1372 DEBUGOUT("PF reset polling failed to complete.\n");
1373 return I40E_ERR_RESET_FAILED;
1377 i40e_clear_pxe_mode(hw);
1380 return I40E_SUCCESS;
1384 * i40e_clear_hw - clear out any left over hw state
1385 * @hw: pointer to the hw struct
1387 * Clear queues and interrupts, typically called at init time,
1388 * but after the capabilities have been found so we know how many
1389 * queues and msix vectors have been allocated.
1391 void i40e_clear_hw(struct i40e_hw *hw)
1393 u32 num_queues, base_queue;
1401 /* get number of interrupts, queues, and vfs */
1402 val = rd32(hw, I40E_GLPCI_CNF2);
1403 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1404 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1405 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1406 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1408 val = rd32(hw, I40E_PFLAN_QALLOC);
1409 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1410 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1411 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1412 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1413 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1414 num_queues = (j - base_queue) + 1;
1418 val = rd32(hw, I40E_PF_VT_PFALLOC);
1419 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1420 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1421 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1422 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1423 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1424 num_vfs = (j - i) + 1;
1428 /* stop all the interrupts */
1429 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1430 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1431 for (i = 0; i < num_pf_int - 2; i++)
1432 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1434 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1435 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1436 wr32(hw, I40E_PFINT_LNKLST0, val);
1437 for (i = 0; i < num_pf_int - 2; i++)
1438 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1439 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1440 for (i = 0; i < num_vfs; i++)
1441 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1442 for (i = 0; i < num_vf_int - 2; i++)
1443 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1445 /* warn the HW of the coming Tx disables */
1446 for (i = 0; i < num_queues; i++) {
1447 u32 abs_queue_idx = base_queue + i;
1450 if (abs_queue_idx >= 128) {
1451 reg_block = abs_queue_idx / 128;
1452 abs_queue_idx %= 128;
1455 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1456 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1457 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1458 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1460 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1462 i40e_usec_delay(400);
1464 /* stop all the queues */
1465 for (i = 0; i < num_queues; i++) {
1466 wr32(hw, I40E_QINT_TQCTL(i), 0);
1467 wr32(hw, I40E_QTX_ENA(i), 0);
1468 wr32(hw, I40E_QINT_RQCTL(i), 0);
1469 wr32(hw, I40E_QRX_ENA(i), 0);
1472 /* short wait for all queue disables to settle */
1473 i40e_usec_delay(50);
1477 * i40e_clear_pxe_mode - clear pxe operations mode
1478 * @hw: pointer to the hw struct
1480 * Make sure all PXE mode settings are cleared, including things
1481 * like descriptor fetch/write-back mode.
1483 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1485 if (i40e_check_asq_alive(hw))
1486 i40e_aq_clear_pxe_mode(hw, NULL);
1490 * i40e_led_is_mine - helper to find matching led
1491 * @hw: pointer to the hw struct
1492 * @idx: index into GPIO registers
1494 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1496 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1501 if (!hw->func_caps.led[idx])
1504 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1505 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1506 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1508 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1509 * if it is not our port then ignore
1511 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1518 #define I40E_COMBINED_ACTIVITY 0xA
1519 #define I40E_FILTER_ACTIVITY 0xE
1520 #define I40E_LINK_ACTIVITY 0xC
1521 #define I40E_MAC_ACTIVITY 0xD
1522 #define I40E_LED0 22
1525 * i40e_led_get - return current on/off mode
1526 * @hw: pointer to the hw struct
1528 * The value returned is the 'mode' field as defined in the
1529 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1530 * values are variations of possible behaviors relating to
1531 * blink, link, and wire.
1533 u32 i40e_led_get(struct i40e_hw *hw)
1535 u32 current_mode = 0;
1539 /* as per the documentation GPIO 22-29 are the LED
1540 * GPIO pins named LED0..LED7
1542 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1543 u32 gpio_val = i40e_led_is_mine(hw, i);
1548 /* ignore gpio LED src mode entries related to the activity
1551 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1552 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1553 switch (current_mode) {
1554 case I40E_COMBINED_ACTIVITY:
1555 case I40E_FILTER_ACTIVITY:
1556 case I40E_MAC_ACTIVITY:
1562 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1563 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1571 * i40e_led_set - set new on/off mode
1572 * @hw: pointer to the hw struct
1573 * @mode: 0=off, 0xf=on (else see manual for mode details)
1574 * @blink: true if the LED should blink when on, false if steady
1576 * if this function is used to turn on the blink it should
1577 * be used to disable the blink when restoring the original state.
1579 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1581 u32 current_mode = 0;
1584 if (mode & 0xfffffff0)
1585 DEBUGOUT1("invalid mode passed in %X\n", mode);
1587 /* as per the documentation GPIO 22-29 are the LED
1588 * GPIO pins named LED0..LED7
1590 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1591 u32 gpio_val = i40e_led_is_mine(hw, i);
1596 /* ignore gpio LED src mode entries related to the activity
1599 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1600 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1601 switch (current_mode) {
1602 case I40E_COMBINED_ACTIVITY:
1603 case I40E_FILTER_ACTIVITY:
1604 case I40E_MAC_ACTIVITY:
1610 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1611 /* this & is a bit of paranoia, but serves as a range check */
1612 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1613 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1615 if (mode == I40E_LINK_ACTIVITY)
1619 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1621 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1623 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1628 /* Admin command wrappers */
1631 * i40e_aq_get_phy_capabilities
1632 * @hw: pointer to the hw struct
1633 * @abilities: structure for PHY capabilities to be filled
1634 * @qualified_modules: report Qualified Modules
1635 * @report_init: report init capabilities (active are default)
1636 * @cmd_details: pointer to command details structure or NULL
1638 * Returns the various PHY abilities supported on the Port.
1640 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1641 bool qualified_modules, bool report_init,
1642 struct i40e_aq_get_phy_abilities_resp *abilities,
1643 struct i40e_asq_cmd_details *cmd_details)
1645 struct i40e_aq_desc desc;
1646 enum i40e_status_code status;
1647 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1650 return I40E_ERR_PARAM;
1652 i40e_fill_default_direct_cmd_desc(&desc,
1653 i40e_aqc_opc_get_phy_abilities);
1655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1656 if (abilities_size > I40E_AQ_LARGE_BUF)
1657 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1659 if (qualified_modules)
1660 desc.params.external.param0 |=
1661 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1664 desc.params.external.param0 |=
1665 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1667 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1670 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1671 status = I40E_ERR_UNKNOWN_PHY;
1674 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1680 * i40e_aq_set_phy_config
1681 * @hw: pointer to the hw struct
1682 * @config: structure with PHY configuration to be set
1683 * @cmd_details: pointer to command details structure or NULL
1685 * Set the various PHY configuration parameters
1686 * supported on the Port.One or more of the Set PHY config parameters may be
1687 * ignored in an MFP mode as the PF may not have the privilege to set some
1688 * of the PHY Config parameters. This status will be indicated by the
1691 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1692 struct i40e_aq_set_phy_config *config,
1693 struct i40e_asq_cmd_details *cmd_details)
1695 struct i40e_aq_desc desc;
1696 struct i40e_aq_set_phy_config *cmd =
1697 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1698 enum i40e_status_code status;
1701 return I40E_ERR_PARAM;
1703 i40e_fill_default_direct_cmd_desc(&desc,
1704 i40e_aqc_opc_set_phy_config);
1708 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1715 * @hw: pointer to the hw struct
1717 * Set the requested flow control mode using set_phy_config.
1719 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1720 bool atomic_restart)
1722 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1723 struct i40e_aq_get_phy_abilities_resp abilities;
1724 struct i40e_aq_set_phy_config config;
1725 enum i40e_status_code status;
1726 u8 pause_mask = 0x0;
1732 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1733 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1735 case I40E_FC_RX_PAUSE:
1736 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1738 case I40E_FC_TX_PAUSE:
1739 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1745 /* Get the current phy config */
1746 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1749 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1753 memset(&config, 0, sizeof(config));
1754 /* clear the old pause settings */
1755 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1756 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1757 /* set the new abilities */
1758 config.abilities |= pause_mask;
1759 /* If the abilities have changed, then set the new config */
1760 if (config.abilities != abilities.abilities) {
1761 /* Auto restart link so settings take effect */
1763 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1764 /* Copy over all the old settings */
1765 config.phy_type = abilities.phy_type;
1766 config.link_speed = abilities.link_speed;
1767 config.eee_capability = abilities.eee_capability;
1768 config.eeer = abilities.eeer_val;
1769 config.low_power_ctrl = abilities.d3_lpan;
1770 status = i40e_aq_set_phy_config(hw, &config, NULL);
1773 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1775 /* Update the link info */
1776 status = i40e_update_link_info(hw);
1778 /* Wait a little bit (on 40G cards it sometimes takes a really
1779 * long time for link to come back from the atomic reset)
1782 i40e_msec_delay(1000);
1783 status = i40e_update_link_info(hw);
1786 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1792 * i40e_aq_set_mac_config
1793 * @hw: pointer to the hw struct
1794 * @max_frame_size: Maximum Frame Size to be supported by the port
1795 * @crc_en: Tell HW to append a CRC to outgoing frames
1796 * @pacing: Pacing configurations
1797 * @cmd_details: pointer to command details structure or NULL
1799 * Configure MAC settings for frame size, jumbo frame support and the
1800 * addition of a CRC by the hardware.
1802 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1804 bool crc_en, u16 pacing,
1805 struct i40e_asq_cmd_details *cmd_details)
1807 struct i40e_aq_desc desc;
1808 struct i40e_aq_set_mac_config *cmd =
1809 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1810 enum i40e_status_code status;
1812 if (max_frame_size == 0)
1813 return I40E_ERR_PARAM;
1815 i40e_fill_default_direct_cmd_desc(&desc,
1816 i40e_aqc_opc_set_mac_config);
1818 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1819 cmd->params = ((u8)pacing & 0x0F) << 3;
1821 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1823 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1829 * i40e_aq_clear_pxe_mode
1830 * @hw: pointer to the hw struct
1831 * @cmd_details: pointer to command details structure or NULL
1833 * Tell the firmware that the driver is taking over from PXE
1835 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1836 struct i40e_asq_cmd_details *cmd_details)
1838 enum i40e_status_code status;
1839 struct i40e_aq_desc desc;
1840 struct i40e_aqc_clear_pxe *cmd =
1841 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1843 i40e_fill_default_direct_cmd_desc(&desc,
1844 i40e_aqc_opc_clear_pxe_mode);
1848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1850 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1856 * i40e_aq_set_link_restart_an
1857 * @hw: pointer to the hw struct
1858 * @enable_link: if true: enable link, if false: disable link
1859 * @cmd_details: pointer to command details structure or NULL
1861 * Sets up the link and restarts the Auto-Negotiation over the link.
1863 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1864 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1866 struct i40e_aq_desc desc;
1867 struct i40e_aqc_set_link_restart_an *cmd =
1868 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1869 enum i40e_status_code status;
1871 i40e_fill_default_direct_cmd_desc(&desc,
1872 i40e_aqc_opc_set_link_restart_an);
1874 cmd->command = I40E_AQ_PHY_RESTART_AN;
1876 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1878 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1880 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1886 * i40e_aq_get_link_info
1887 * @hw: pointer to the hw struct
1888 * @enable_lse: enable/disable LinkStatusEvent reporting
1889 * @link: pointer to link status structure - optional
1890 * @cmd_details: pointer to command details structure or NULL
1892 * Returns the link status of the adapter.
1894 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1895 bool enable_lse, struct i40e_link_status *link,
1896 struct i40e_asq_cmd_details *cmd_details)
1898 struct i40e_aq_desc desc;
1899 struct i40e_aqc_get_link_status *resp =
1900 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1901 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1902 enum i40e_status_code status;
1903 bool tx_pause, rx_pause;
1906 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1909 command_flags = I40E_AQ_LSE_ENABLE;
1911 command_flags = I40E_AQ_LSE_DISABLE;
1912 resp->command_flags = CPU_TO_LE16(command_flags);
1914 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1916 if (status != I40E_SUCCESS)
1917 goto aq_get_link_info_exit;
1919 /* save off old link status information */
1920 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1921 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1923 /* update link status */
1924 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1925 hw->phy.media_type = i40e_get_media_type(hw);
1926 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1927 hw_link_info->link_info = resp->link_info;
1928 hw_link_info->an_info = resp->an_info;
1929 hw_link_info->ext_info = resp->ext_info;
1930 hw_link_info->loopback = resp->loopback;
1931 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1932 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1934 /* update fc info */
1935 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1936 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1937 if (tx_pause & rx_pause)
1938 hw->fc.current_mode = I40E_FC_FULL;
1940 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1942 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1944 hw->fc.current_mode = I40E_FC_NONE;
1946 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1947 hw_link_info->crc_enable = true;
1949 hw_link_info->crc_enable = false;
1951 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1952 hw_link_info->lse_enable = true;
1954 hw_link_info->lse_enable = false;
1956 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1957 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1958 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1960 /* save link status information */
1962 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1963 I40E_NONDMA_TO_NONDMA);
1965 /* flag cleared so helper functions don't call AQ again */
1966 hw->phy.get_link_info = false;
1968 aq_get_link_info_exit:
1973 * i40e_aq_set_phy_int_mask
1974 * @hw: pointer to the hw struct
1975 * @mask: interrupt mask to be set
1976 * @cmd_details: pointer to command details structure or NULL
1978 * Set link interrupt mask.
1980 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1982 struct i40e_asq_cmd_details *cmd_details)
1984 struct i40e_aq_desc desc;
1985 struct i40e_aqc_set_phy_int_mask *cmd =
1986 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1987 enum i40e_status_code status;
1989 i40e_fill_default_direct_cmd_desc(&desc,
1990 i40e_aqc_opc_set_phy_int_mask);
1992 cmd->event_mask = CPU_TO_LE16(mask);
1994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2000 * i40e_aq_get_local_advt_reg
2001 * @hw: pointer to the hw struct
2002 * @advt_reg: local AN advertisement register value
2003 * @cmd_details: pointer to command details structure or NULL
2005 * Get the Local AN advertisement register value.
2007 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2009 struct i40e_asq_cmd_details *cmd_details)
2011 struct i40e_aq_desc desc;
2012 struct i40e_aqc_an_advt_reg *resp =
2013 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2014 enum i40e_status_code status;
2016 i40e_fill_default_direct_cmd_desc(&desc,
2017 i40e_aqc_opc_get_local_advt_reg);
2019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2021 if (status != I40E_SUCCESS)
2022 goto aq_get_local_advt_reg_exit;
2024 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2025 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2027 aq_get_local_advt_reg_exit:
2032 * i40e_aq_set_local_advt_reg
2033 * @hw: pointer to the hw struct
2034 * @advt_reg: local AN advertisement register value
2035 * @cmd_details: pointer to command details structure or NULL
2037 * Get the Local AN advertisement register value.
2039 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2041 struct i40e_asq_cmd_details *cmd_details)
2043 struct i40e_aq_desc desc;
2044 struct i40e_aqc_an_advt_reg *cmd =
2045 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2046 enum i40e_status_code status;
2048 i40e_fill_default_direct_cmd_desc(&desc,
2049 i40e_aqc_opc_get_local_advt_reg);
2051 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2052 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2054 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2060 * i40e_aq_get_partner_advt
2061 * @hw: pointer to the hw struct
2062 * @advt_reg: AN partner advertisement register value
2063 * @cmd_details: pointer to command details structure or NULL
2065 * Get the link partner AN advertisement register value.
2067 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2069 struct i40e_asq_cmd_details *cmd_details)
2071 struct i40e_aq_desc desc;
2072 struct i40e_aqc_an_advt_reg *resp =
2073 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2074 enum i40e_status_code status;
2076 i40e_fill_default_direct_cmd_desc(&desc,
2077 i40e_aqc_opc_get_partner_advt);
2079 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2081 if (status != I40E_SUCCESS)
2082 goto aq_get_partner_advt_exit;
2084 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2085 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2087 aq_get_partner_advt_exit:
2092 * i40e_aq_set_lb_modes
2093 * @hw: pointer to the hw struct
2094 * @lb_modes: loopback mode to be set
2095 * @cmd_details: pointer to command details structure or NULL
2097 * Sets loopback modes.
2099 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2101 struct i40e_asq_cmd_details *cmd_details)
2103 struct i40e_aq_desc desc;
2104 struct i40e_aqc_set_lb_mode *cmd =
2105 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2106 enum i40e_status_code status;
2108 i40e_fill_default_direct_cmd_desc(&desc,
2109 i40e_aqc_opc_set_lb_modes);
2111 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2119 * i40e_aq_set_phy_debug
2120 * @hw: pointer to the hw struct
2121 * @cmd_flags: debug command flags
2122 * @cmd_details: pointer to command details structure or NULL
2124 * Reset the external PHY.
2126 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2127 struct i40e_asq_cmd_details *cmd_details)
2129 struct i40e_aq_desc desc;
2130 struct i40e_aqc_set_phy_debug *cmd =
2131 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2132 enum i40e_status_code status;
2134 i40e_fill_default_direct_cmd_desc(&desc,
2135 i40e_aqc_opc_set_phy_debug);
2137 cmd->command_flags = cmd_flags;
2139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2146 * @hw: pointer to the hw struct
2147 * @vsi_ctx: pointer to a vsi context struct
2148 * @cmd_details: pointer to command details structure or NULL
2150 * Add a VSI context to the hardware.
2152 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2153 struct i40e_vsi_context *vsi_ctx,
2154 struct i40e_asq_cmd_details *cmd_details)
2156 struct i40e_aq_desc desc;
2157 struct i40e_aqc_add_get_update_vsi *cmd =
2158 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2159 struct i40e_aqc_add_get_update_vsi_completion *resp =
2160 (struct i40e_aqc_add_get_update_vsi_completion *)
2162 enum i40e_status_code status;
2164 i40e_fill_default_direct_cmd_desc(&desc,
2165 i40e_aqc_opc_add_vsi);
2167 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2168 cmd->connection_type = vsi_ctx->connection_type;
2169 cmd->vf_id = vsi_ctx->vf_num;
2170 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2172 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2174 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2175 sizeof(vsi_ctx->info), cmd_details);
2177 if (status != I40E_SUCCESS)
2178 goto aq_add_vsi_exit;
2180 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2181 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2182 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2183 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2190 * i40e_aq_set_default_vsi
2191 * @hw: pointer to the hw struct
2193 * @cmd_details: pointer to command details structure or NULL
2195 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2197 struct i40e_asq_cmd_details *cmd_details)
2199 struct i40e_aq_desc desc;
2200 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2201 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2203 enum i40e_status_code status;
2205 i40e_fill_default_direct_cmd_desc(&desc,
2206 i40e_aqc_opc_set_vsi_promiscuous_modes);
2208 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2209 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2210 cmd->seid = CPU_TO_LE16(seid);
2212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2218 * i40e_aq_set_vsi_unicast_promiscuous
2219 * @hw: pointer to the hw struct
2221 * @set: set unicast promiscuous enable/disable
2222 * @cmd_details: pointer to command details structure or NULL
2223 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2225 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2227 struct i40e_asq_cmd_details *cmd_details,
2228 bool rx_only_promisc)
2230 struct i40e_aq_desc desc;
2231 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2232 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2233 enum i40e_status_code status;
2236 i40e_fill_default_direct_cmd_desc(&desc,
2237 i40e_aqc_opc_set_vsi_promiscuous_modes);
2240 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2241 if (rx_only_promisc &&
2242 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2243 (hw->aq.api_maj_ver > 1)))
2244 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2247 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2249 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2250 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2251 (hw->aq.api_maj_ver > 1))
2252 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2254 cmd->seid = CPU_TO_LE16(seid);
2255 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2261 * i40e_aq_set_vsi_multicast_promiscuous
2262 * @hw: pointer to the hw struct
2264 * @set: set multicast promiscuous enable/disable
2265 * @cmd_details: pointer to command details structure or NULL
2267 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2268 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2270 struct i40e_aq_desc desc;
2271 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2272 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2273 enum i40e_status_code status;
2276 i40e_fill_default_direct_cmd_desc(&desc,
2277 i40e_aqc_opc_set_vsi_promiscuous_modes);
2280 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2282 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2284 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2286 cmd->seid = CPU_TO_LE16(seid);
2287 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2293 * i40e_aq_set_vsi_mc_promisc_on_vlan
2294 * @hw: pointer to the hw struct
2296 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2297 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2298 * @cmd_details: pointer to command details structure or NULL
2300 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2301 u16 seid, bool enable, u16 vid,
2302 struct i40e_asq_cmd_details *cmd_details)
2304 struct i40e_aq_desc desc;
2305 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2306 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2307 enum i40e_status_code status;
2310 i40e_fill_default_direct_cmd_desc(&desc,
2311 i40e_aqc_opc_set_vsi_promiscuous_modes);
2314 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2316 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2317 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2318 cmd->seid = CPU_TO_LE16(seid);
2319 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2321 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2327 * i40e_aq_set_vsi_uc_promisc_on_vlan
2328 * @hw: pointer to the hw struct
2330 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2331 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2332 * @cmd_details: pointer to command details structure or NULL
2334 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2335 u16 seid, bool enable, u16 vid,
2336 struct i40e_asq_cmd_details *cmd_details)
2338 struct i40e_aq_desc desc;
2339 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2340 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2341 enum i40e_status_code status;
2344 i40e_fill_default_direct_cmd_desc(&desc,
2345 i40e_aqc_opc_set_vsi_promiscuous_modes);
2348 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2350 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2351 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2352 cmd->seid = CPU_TO_LE16(seid);
2353 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2355 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2361 * i40e_aq_set_vsi_broadcast
2362 * @hw: pointer to the hw struct
2364 * @set_filter: true to set filter, false to clear filter
2365 * @cmd_details: pointer to command details structure or NULL
2367 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2369 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2370 u16 seid, bool set_filter,
2371 struct i40e_asq_cmd_details *cmd_details)
2373 struct i40e_aq_desc desc;
2374 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2375 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2376 enum i40e_status_code status;
2378 i40e_fill_default_direct_cmd_desc(&desc,
2379 i40e_aqc_opc_set_vsi_promiscuous_modes);
2382 cmd->promiscuous_flags
2383 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2385 cmd->promiscuous_flags
2386 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2388 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2389 cmd->seid = CPU_TO_LE16(seid);
2390 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2396 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2397 * @hw: pointer to the hw struct
2399 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2400 * @cmd_details: pointer to command details structure or NULL
2402 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2403 u16 seid, bool enable,
2404 struct i40e_asq_cmd_details *cmd_details)
2406 struct i40e_aq_desc desc;
2407 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2408 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2409 enum i40e_status_code status;
2412 i40e_fill_default_direct_cmd_desc(&desc,
2413 i40e_aqc_opc_set_vsi_promiscuous_modes);
2415 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2417 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2418 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2419 cmd->seid = CPU_TO_LE16(seid);
2421 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427 * i40e_get_vsi_params - get VSI configuration info
2428 * @hw: pointer to the hw struct
2429 * @vsi_ctx: pointer to a vsi context struct
2430 * @cmd_details: pointer to command details structure or NULL
2432 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2433 struct i40e_vsi_context *vsi_ctx,
2434 struct i40e_asq_cmd_details *cmd_details)
2436 struct i40e_aq_desc desc;
2437 struct i40e_aqc_add_get_update_vsi *cmd =
2438 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2439 struct i40e_aqc_add_get_update_vsi_completion *resp =
2440 (struct i40e_aqc_add_get_update_vsi_completion *)
2442 enum i40e_status_code status;
2444 UNREFERENCED_1PARAMETER(cmd_details);
2445 i40e_fill_default_direct_cmd_desc(&desc,
2446 i40e_aqc_opc_get_vsi_parameters);
2448 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2452 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2453 sizeof(vsi_ctx->info), NULL);
2455 if (status != I40E_SUCCESS)
2456 goto aq_get_vsi_params_exit;
2458 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2459 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2460 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2461 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2463 aq_get_vsi_params_exit:
2468 * i40e_aq_update_vsi_params
2469 * @hw: pointer to the hw struct
2470 * @vsi_ctx: pointer to a vsi context struct
2471 * @cmd_details: pointer to command details structure or NULL
2473 * Update a VSI context.
2475 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2476 struct i40e_vsi_context *vsi_ctx,
2477 struct i40e_asq_cmd_details *cmd_details)
2479 struct i40e_aq_desc desc;
2480 struct i40e_aqc_add_get_update_vsi *cmd =
2481 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2482 struct i40e_aqc_add_get_update_vsi_completion *resp =
2483 (struct i40e_aqc_add_get_update_vsi_completion *)
2485 enum i40e_status_code status;
2487 i40e_fill_default_direct_cmd_desc(&desc,
2488 i40e_aqc_opc_update_vsi_parameters);
2489 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2491 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2493 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2494 sizeof(vsi_ctx->info), cmd_details);
2496 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2497 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2503 * i40e_aq_get_switch_config
2504 * @hw: pointer to the hardware structure
2505 * @buf: pointer to the result buffer
2506 * @buf_size: length of input buffer
2507 * @start_seid: seid to start for the report, 0 == beginning
2508 * @cmd_details: pointer to command details structure or NULL
2510 * Fill the buf with switch configuration returned from AdminQ command
2512 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2513 struct i40e_aqc_get_switch_config_resp *buf,
2514 u16 buf_size, u16 *start_seid,
2515 struct i40e_asq_cmd_details *cmd_details)
2517 struct i40e_aq_desc desc;
2518 struct i40e_aqc_switch_seid *scfg =
2519 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2520 enum i40e_status_code status;
2522 i40e_fill_default_direct_cmd_desc(&desc,
2523 i40e_aqc_opc_get_switch_config);
2524 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2525 if (buf_size > I40E_AQ_LARGE_BUF)
2526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2527 scfg->seid = CPU_TO_LE16(*start_seid);
2529 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2530 *start_seid = LE16_TO_CPU(scfg->seid);
2536 * i40e_aq_set_switch_config
2537 * @hw: pointer to the hardware structure
2538 * @flags: bit flag values to set
2539 * @valid_flags: which bit flags to set
2540 * @cmd_details: pointer to command details structure or NULL
2542 * Set switch configuration bits
2544 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2545 u16 flags, u16 valid_flags,
2546 struct i40e_asq_cmd_details *cmd_details)
2548 struct i40e_aq_desc desc;
2549 struct i40e_aqc_set_switch_config *scfg =
2550 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2551 enum i40e_status_code status;
2553 i40e_fill_default_direct_cmd_desc(&desc,
2554 i40e_aqc_opc_set_switch_config);
2555 scfg->flags = CPU_TO_LE16(flags);
2556 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2564 * i40e_aq_get_firmware_version
2565 * @hw: pointer to the hw struct
2566 * @fw_major_version: firmware major version
2567 * @fw_minor_version: firmware minor version
2568 * @fw_build: firmware build number
2569 * @api_major_version: major queue version
2570 * @api_minor_version: minor queue version
2571 * @cmd_details: pointer to command details structure or NULL
2573 * Get the firmware version from the admin queue commands
2575 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2576 u16 *fw_major_version, u16 *fw_minor_version,
2578 u16 *api_major_version, u16 *api_minor_version,
2579 struct i40e_asq_cmd_details *cmd_details)
2581 struct i40e_aq_desc desc;
2582 struct i40e_aqc_get_version *resp =
2583 (struct i40e_aqc_get_version *)&desc.params.raw;
2584 enum i40e_status_code status;
2586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2590 if (status == I40E_SUCCESS) {
2591 if (fw_major_version != NULL)
2592 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2593 if (fw_minor_version != NULL)
2594 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2595 if (fw_build != NULL)
2596 *fw_build = LE32_TO_CPU(resp->fw_build);
2597 if (api_major_version != NULL)
2598 *api_major_version = LE16_TO_CPU(resp->api_major);
2599 if (api_minor_version != NULL)
2600 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2602 /* A workaround to fix the API version in SW */
2603 if (api_major_version && api_minor_version &&
2604 fw_major_version && fw_minor_version &&
2605 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2606 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2607 (*fw_major_version > 4)))
2608 *api_minor_version = 2;
2615 * i40e_aq_send_driver_version
2616 * @hw: pointer to the hw struct
2617 * @dv: driver's major, minor version
2618 * @cmd_details: pointer to command details structure or NULL
2620 * Send the driver version to the firmware
2622 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2623 struct i40e_driver_version *dv,
2624 struct i40e_asq_cmd_details *cmd_details)
2626 struct i40e_aq_desc desc;
2627 struct i40e_aqc_driver_version *cmd =
2628 (struct i40e_aqc_driver_version *)&desc.params.raw;
2629 enum i40e_status_code status;
2633 return I40E_ERR_PARAM;
2635 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2637 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2638 cmd->driver_major_ver = dv->major_version;
2639 cmd->driver_minor_ver = dv->minor_version;
2640 cmd->driver_build_ver = dv->build_version;
2641 cmd->driver_subbuild_ver = dv->subbuild_version;
2644 while (len < sizeof(dv->driver_string) &&
2645 (dv->driver_string[len] < 0x80) &&
2646 dv->driver_string[len])
2648 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2655 * i40e_get_link_status - get status of the HW network link
2656 * @hw: pointer to the hw struct
2657 * @link_up: pointer to bool (true/false = linkup/linkdown)
2659 * Variable link_up true if link is up, false if link is down.
2660 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2662 * Side effect: LinkStatusEvent reporting becomes enabled
2664 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2666 enum i40e_status_code status = I40E_SUCCESS;
2668 if (hw->phy.get_link_info) {
2669 status = i40e_update_link_info(hw);
2671 if (status != I40E_SUCCESS)
2672 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2676 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2682 * i40e_updatelink_status - update status of the HW network link
2683 * @hw: pointer to the hw struct
2685 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2687 struct i40e_aq_get_phy_abilities_resp abilities;
2688 enum i40e_status_code status = I40E_SUCCESS;
2690 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2694 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2695 status = i40e_aq_get_phy_capabilities(hw, false, false,
2700 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2701 sizeof(hw->phy.link_info.module_type));
2708 * i40e_get_link_speed
2709 * @hw: pointer to the hw struct
2711 * Returns the link speed of the adapter.
2713 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2715 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2716 enum i40e_status_code status = I40E_SUCCESS;
2718 if (hw->phy.get_link_info) {
2719 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2721 if (status != I40E_SUCCESS)
2722 goto i40e_link_speed_exit;
2725 speed = hw->phy.link_info.link_speed;
2727 i40e_link_speed_exit:
2732 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2733 * @hw: pointer to the hw struct
2734 * @uplink_seid: the MAC or other gizmo SEID
2735 * @downlink_seid: the VSI SEID
2736 * @enabled_tc: bitmap of TCs to be enabled
2737 * @default_port: true for default port VSI, false for control port
2738 * @veb_seid: pointer to where to put the resulting VEB SEID
2739 * @enable_stats: true to turn on VEB stats
2740 * @cmd_details: pointer to command details structure or NULL
2742 * This asks the FW to add a VEB between the uplink and downlink
2743 * elements. If the uplink SEID is 0, this will be a floating VEB.
2745 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2746 u16 downlink_seid, u8 enabled_tc,
2747 bool default_port, u16 *veb_seid,
2749 struct i40e_asq_cmd_details *cmd_details)
2751 struct i40e_aq_desc desc;
2752 struct i40e_aqc_add_veb *cmd =
2753 (struct i40e_aqc_add_veb *)&desc.params.raw;
2754 struct i40e_aqc_add_veb_completion *resp =
2755 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2756 enum i40e_status_code status;
2759 /* SEIDs need to either both be set or both be 0 for floating VEB */
2760 if (!!uplink_seid != !!downlink_seid)
2761 return I40E_ERR_PARAM;
2763 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2765 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2766 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2767 cmd->enable_tcs = enabled_tc;
2769 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2771 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2773 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2775 /* reverse logic here: set the bitflag to disable the stats */
2777 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2779 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2783 if (!status && veb_seid)
2784 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2790 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2791 * @hw: pointer to the hw struct
2792 * @veb_seid: the SEID of the VEB to query
2793 * @switch_id: the uplink switch id
2794 * @floating: set to true if the VEB is floating
2795 * @statistic_index: index of the stats counter block for this VEB
2796 * @vebs_used: number of VEB's used by function
2797 * @vebs_free: total VEB's not reserved by any function
2798 * @cmd_details: pointer to command details structure or NULL
2800 * This retrieves the parameters for a particular VEB, specified by
2801 * uplink_seid, and returns them to the caller.
2803 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2804 u16 veb_seid, u16 *switch_id,
2805 bool *floating, u16 *statistic_index,
2806 u16 *vebs_used, u16 *vebs_free,
2807 struct i40e_asq_cmd_details *cmd_details)
2809 struct i40e_aq_desc desc;
2810 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2811 (struct i40e_aqc_get_veb_parameters_completion *)
2813 enum i40e_status_code status;
2816 return I40E_ERR_PARAM;
2818 i40e_fill_default_direct_cmd_desc(&desc,
2819 i40e_aqc_opc_get_veb_parameters);
2820 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2827 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2828 if (statistic_index)
2829 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2831 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2833 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2835 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2837 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2848 * i40e_aq_add_macvlan
2849 * @hw: pointer to the hw struct
2850 * @seid: VSI for the mac address
2851 * @mv_list: list of macvlans to be added
2852 * @count: length of the list
2853 * @cmd_details: pointer to command details structure or NULL
2855 * Add MAC/VLAN addresses to the HW filtering
2857 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2858 struct i40e_aqc_add_macvlan_element_data *mv_list,
2859 u16 count, struct i40e_asq_cmd_details *cmd_details)
2861 struct i40e_aq_desc desc;
2862 struct i40e_aqc_macvlan *cmd =
2863 (struct i40e_aqc_macvlan *)&desc.params.raw;
2864 enum i40e_status_code status;
2868 if (count == 0 || !mv_list || !hw)
2869 return I40E_ERR_PARAM;
2871 buf_size = count * sizeof(*mv_list);
2873 /* prep the rest of the request */
2874 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2875 cmd->num_addresses = CPU_TO_LE16(count);
2876 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2880 for (i = 0; i < count; i++)
2881 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2883 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2885 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2886 if (buf_size > I40E_AQ_LARGE_BUF)
2887 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2889 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2896 * i40e_aq_remove_macvlan
2897 * @hw: pointer to the hw struct
2898 * @seid: VSI for the mac address
2899 * @mv_list: list of macvlans to be removed
2900 * @count: length of the list
2901 * @cmd_details: pointer to command details structure or NULL
2903 * Remove MAC/VLAN addresses from the HW filtering
2905 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2906 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2907 u16 count, struct i40e_asq_cmd_details *cmd_details)
2909 struct i40e_aq_desc desc;
2910 struct i40e_aqc_macvlan *cmd =
2911 (struct i40e_aqc_macvlan *)&desc.params.raw;
2912 enum i40e_status_code status;
2915 if (count == 0 || !mv_list || !hw)
2916 return I40E_ERR_PARAM;
2918 buf_size = count * sizeof(*mv_list);
2920 /* prep the rest of the request */
2921 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2922 cmd->num_addresses = CPU_TO_LE16(count);
2923 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2927 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2928 if (buf_size > I40E_AQ_LARGE_BUF)
2929 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2931 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2938 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2939 * @hw: pointer to the hw struct
2940 * @opcode: AQ opcode for add or delete mirror rule
2941 * @sw_seid: Switch SEID (to which rule refers)
2942 * @rule_type: Rule Type (ingress/egress/VLAN)
2943 * @id: Destination VSI SEID or Rule ID
2944 * @count: length of the list
2945 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2946 * @cmd_details: pointer to command details structure or NULL
2947 * @rule_id: Rule ID returned from FW
2948 * @rule_used: Number of rules used in internal switch
2949 * @rule_free: Number of rules free in internal switch
2951 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2952 * VEBs/VEPA elements only
2954 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2955 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2956 u16 count, __le16 *mr_list,
2957 struct i40e_asq_cmd_details *cmd_details,
2958 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2960 struct i40e_aq_desc desc;
2961 struct i40e_aqc_add_delete_mirror_rule *cmd =
2962 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2963 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2964 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2965 enum i40e_status_code status;
2968 buf_size = count * sizeof(*mr_list);
2970 /* prep the rest of the request */
2971 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2972 cmd->seid = CPU_TO_LE16(sw_seid);
2973 cmd->rule_type = CPU_TO_LE16(rule_type &
2974 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2975 cmd->num_entries = CPU_TO_LE16(count);
2976 /* Dest VSI for add, rule_id for delete */
2977 cmd->destination = CPU_TO_LE16(id);
2979 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2981 if (buf_size > I40E_AQ_LARGE_BUF)
2982 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2985 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2987 if (status == I40E_SUCCESS ||
2988 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2990 *rule_id = LE16_TO_CPU(resp->rule_id);
2992 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2994 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3000 * i40e_aq_add_mirrorrule - add a mirror rule
3001 * @hw: pointer to the hw struct
3002 * @sw_seid: Switch SEID (to which rule refers)
3003 * @rule_type: Rule Type (ingress/egress/VLAN)
3004 * @dest_vsi: SEID of VSI to which packets will be mirrored
3005 * @count: length of the list
3006 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3007 * @cmd_details: pointer to command details structure or NULL
3008 * @rule_id: Rule ID returned from FW
3009 * @rule_used: Number of rules used in internal switch
3010 * @rule_free: Number of rules free in internal switch
3012 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3014 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3015 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3016 struct i40e_asq_cmd_details *cmd_details,
3017 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3019 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3020 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3021 if (count == 0 || !mr_list)
3022 return I40E_ERR_PARAM;
3025 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3026 rule_type, dest_vsi, count, mr_list,
3027 cmd_details, rule_id, rules_used, rules_free);
3031 * i40e_aq_delete_mirrorrule - delete a mirror rule
3032 * @hw: pointer to the hw struct
3033 * @sw_seid: Switch SEID (to which rule refers)
3034 * @rule_type: Rule Type (ingress/egress/VLAN)
3035 * @count: length of the list
3036 * @rule_id: Rule ID that is returned in the receive desc as part of
3038 * @mr_list: list of mirrored VLAN IDs to be removed
3039 * @cmd_details: pointer to command details structure or NULL
3040 * @rule_used: Number of rules used in internal switch
3041 * @rule_free: Number of rules free in internal switch
3043 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3045 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3046 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3047 struct i40e_asq_cmd_details *cmd_details,
3048 u16 *rules_used, u16 *rules_free)
3050 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3051 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3052 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3053 * mirroring. For other rule_type, count and rule_type should
3056 if (count == 0 || !mr_list)
3057 return I40E_ERR_PARAM;
3060 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3061 rule_type, rule_id, count, mr_list,
3062 cmd_details, NULL, rules_used, rules_free);
3066 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3067 * @hw: pointer to the hw struct
3068 * @seid: VSI for the vlan filters
3069 * @v_list: list of vlan filters to be added
3070 * @count: length of the list
3071 * @cmd_details: pointer to command details structure or NULL
3073 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3074 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3075 u8 count, struct i40e_asq_cmd_details *cmd_details)
3077 struct i40e_aq_desc desc;
3078 struct i40e_aqc_macvlan *cmd =
3079 (struct i40e_aqc_macvlan *)&desc.params.raw;
3080 enum i40e_status_code status;
3083 if (count == 0 || !v_list || !hw)
3084 return I40E_ERR_PARAM;
3086 buf_size = count * sizeof(*v_list);
3088 /* prep the rest of the request */
3089 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3090 cmd->num_addresses = CPU_TO_LE16(count);
3091 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3095 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3096 if (buf_size > I40E_AQ_LARGE_BUF)
3097 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3099 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3106 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3107 * @hw: pointer to the hw struct
3108 * @seid: VSI for the vlan filters
3109 * @v_list: list of macvlans to be removed
3110 * @count: length of the list
3111 * @cmd_details: pointer to command details structure or NULL
3113 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3114 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3115 u8 count, struct i40e_asq_cmd_details *cmd_details)
3117 struct i40e_aq_desc desc;
3118 struct i40e_aqc_macvlan *cmd =
3119 (struct i40e_aqc_macvlan *)&desc.params.raw;
3120 enum i40e_status_code status;
3123 if (count == 0 || !v_list || !hw)
3124 return I40E_ERR_PARAM;
3126 buf_size = count * sizeof(*v_list);
3128 /* prep the rest of the request */
3129 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3130 cmd->num_addresses = CPU_TO_LE16(count);
3131 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3135 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3136 if (buf_size > I40E_AQ_LARGE_BUF)
3137 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3139 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3146 * i40e_aq_send_msg_to_vf
3147 * @hw: pointer to the hardware structure
3148 * @vfid: vf id to send msg
3149 * @v_opcode: opcodes for VF-PF communication
3150 * @v_retval: return error code
3151 * @msg: pointer to the msg buffer
3152 * @msglen: msg length
3153 * @cmd_details: pointer to command details
3157 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3158 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3159 struct i40e_asq_cmd_details *cmd_details)
3161 struct i40e_aq_desc desc;
3162 struct i40e_aqc_pf_vf_message *cmd =
3163 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3164 enum i40e_status_code status;
3166 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3167 cmd->id = CPU_TO_LE32(vfid);
3168 desc.cookie_high = CPU_TO_LE32(v_opcode);
3169 desc.cookie_low = CPU_TO_LE32(v_retval);
3170 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3172 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3174 if (msglen > I40E_AQ_LARGE_BUF)
3175 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3176 desc.datalen = CPU_TO_LE16(msglen);
3178 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3184 * i40e_aq_debug_read_register
3185 * @hw: pointer to the hw struct
3186 * @reg_addr: register address
3187 * @reg_val: register value
3188 * @cmd_details: pointer to command details structure or NULL
3190 * Read the register using the admin queue commands
3192 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3193 u32 reg_addr, u64 *reg_val,
3194 struct i40e_asq_cmd_details *cmd_details)
3196 struct i40e_aq_desc desc;
3197 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3198 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3199 enum i40e_status_code status;
3201 if (reg_val == NULL)
3202 return I40E_ERR_PARAM;
3204 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3206 cmd_resp->address = CPU_TO_LE32(reg_addr);
3208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3210 if (status == I40E_SUCCESS) {
3211 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3212 (u64)LE32_TO_CPU(cmd_resp->value_low);
3219 * i40e_aq_debug_write_register
3220 * @hw: pointer to the hw struct
3221 * @reg_addr: register address
3222 * @reg_val: register value
3223 * @cmd_details: pointer to command details structure or NULL
3225 * Write to a register using the admin queue commands
3227 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3228 u32 reg_addr, u64 reg_val,
3229 struct i40e_asq_cmd_details *cmd_details)
3231 struct i40e_aq_desc desc;
3232 struct i40e_aqc_debug_reg_read_write *cmd =
3233 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3234 enum i40e_status_code status;
3236 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3238 cmd->address = CPU_TO_LE32(reg_addr);
3239 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3240 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3242 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3248 * i40e_aq_request_resource
3249 * @hw: pointer to the hw struct
3250 * @resource: resource id
3251 * @access: access type
3252 * @sdp_number: resource number
3253 * @timeout: the maximum time in ms that the driver may hold the resource
3254 * @cmd_details: pointer to command details structure or NULL
3256 * requests common resource using the admin queue commands
3258 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3259 enum i40e_aq_resources_ids resource,
3260 enum i40e_aq_resource_access_type access,
3261 u8 sdp_number, u64 *timeout,
3262 struct i40e_asq_cmd_details *cmd_details)
3264 struct i40e_aq_desc desc;
3265 struct i40e_aqc_request_resource *cmd_resp =
3266 (struct i40e_aqc_request_resource *)&desc.params.raw;
3267 enum i40e_status_code status;
3269 DEBUGFUNC("i40e_aq_request_resource");
3271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3273 cmd_resp->resource_id = CPU_TO_LE16(resource);
3274 cmd_resp->access_type = CPU_TO_LE16(access);
3275 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3277 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3278 /* The completion specifies the maximum time in ms that the driver
3279 * may hold the resource in the Timeout field.
3280 * If the resource is held by someone else, the command completes with
3281 * busy return value and the timeout field indicates the maximum time
3282 * the current owner of the resource has to free it.
3284 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3285 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3291 * i40e_aq_release_resource
3292 * @hw: pointer to the hw struct
3293 * @resource: resource id
3294 * @sdp_number: resource number
3295 * @cmd_details: pointer to command details structure or NULL
3297 * release common resource using the admin queue commands
3299 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3300 enum i40e_aq_resources_ids resource,
3302 struct i40e_asq_cmd_details *cmd_details)
3304 struct i40e_aq_desc desc;
3305 struct i40e_aqc_request_resource *cmd =
3306 (struct i40e_aqc_request_resource *)&desc.params.raw;
3307 enum i40e_status_code status;
3309 DEBUGFUNC("i40e_aq_release_resource");
3311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3313 cmd->resource_id = CPU_TO_LE16(resource);
3314 cmd->resource_number = CPU_TO_LE32(sdp_number);
3316 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3323 * @hw: pointer to the hw struct
3324 * @module_pointer: module pointer location in words from the NVM beginning
3325 * @offset: byte offset from the module beginning
3326 * @length: length of the section to be read (in bytes from the offset)
3327 * @data: command buffer (size [bytes] = length)
3328 * @last_command: tells if this is the last command in a series
3329 * @cmd_details: pointer to command details structure or NULL
3331 * Read the NVM using the admin queue commands
3333 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3334 u32 offset, u16 length, void *data,
3336 struct i40e_asq_cmd_details *cmd_details)
3338 struct i40e_aq_desc desc;
3339 struct i40e_aqc_nvm_update *cmd =
3340 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3341 enum i40e_status_code status;
3343 DEBUGFUNC("i40e_aq_read_nvm");
3345 /* In offset the highest byte must be zeroed. */
3346 if (offset & 0xFF000000) {
3347 status = I40E_ERR_PARAM;
3348 goto i40e_aq_read_nvm_exit;
3351 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3353 /* If this is the last command in a series, set the proper flag. */
3355 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3356 cmd->module_pointer = module_pointer;
3357 cmd->offset = CPU_TO_LE32(offset);
3358 cmd->length = CPU_TO_LE16(length);
3360 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3361 if (length > I40E_AQ_LARGE_BUF)
3362 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3364 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3366 i40e_aq_read_nvm_exit:
3371 * i40e_aq_read_nvm_config - read an nvm config block
3372 * @hw: pointer to the hw struct
3373 * @cmd_flags: NVM access admin command bits
3374 * @field_id: field or feature id
3375 * @data: buffer for result
3376 * @buf_size: buffer size
3377 * @element_count: pointer to count of elements read by FW
3378 * @cmd_details: pointer to command details structure or NULL
3380 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3381 u8 cmd_flags, u32 field_id, void *data,
3382 u16 buf_size, u16 *element_count,
3383 struct i40e_asq_cmd_details *cmd_details)
3385 struct i40e_aq_desc desc;
3386 struct i40e_aqc_nvm_config_read *cmd =
3387 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3388 enum i40e_status_code status;
3390 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3391 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3392 if (buf_size > I40E_AQ_LARGE_BUF)
3393 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3395 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3396 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3397 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3398 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3400 cmd->element_id_msw = 0;
3402 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3404 if (!status && element_count)
3405 *element_count = LE16_TO_CPU(cmd->element_count);
3411 * i40e_aq_write_nvm_config - write an nvm config block
3412 * @hw: pointer to the hw struct
3413 * @cmd_flags: NVM access admin command bits
3414 * @data: buffer for result
3415 * @buf_size: buffer size
3416 * @element_count: count of elements to be written
3417 * @cmd_details: pointer to command details structure or NULL
3419 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3420 u8 cmd_flags, void *data, u16 buf_size,
3422 struct i40e_asq_cmd_details *cmd_details)
3424 struct i40e_aq_desc desc;
3425 struct i40e_aqc_nvm_config_write *cmd =
3426 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3427 enum i40e_status_code status;
3429 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3430 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3431 if (buf_size > I40E_AQ_LARGE_BUF)
3432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3434 cmd->element_count = CPU_TO_LE16(element_count);
3435 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3436 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3442 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3443 * @hw: pointer to the hw struct
3444 * @cmd_details: pointer to command details structure or NULL
3446 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3447 void *buff, u16 buff_size,
3448 struct i40e_asq_cmd_details *cmd_details)
3450 struct i40e_aq_desc desc;
3451 enum i40e_status_code status;
3453 UNREFERENCED_2PARAMETER(buff, buff_size);
3455 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3456 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3457 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3458 status = I40E_ERR_NOT_IMPLEMENTED;
3465 * @hw: pointer to the hw struct
3466 * @module_pointer: module pointer location in words from the NVM beginning
3467 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3468 * @length: length of the section to be erased (expressed in 4 KB)
3469 * @last_command: tells if this is the last command in a series
3470 * @cmd_details: pointer to command details structure or NULL
3472 * Erase the NVM sector using the admin queue commands
3474 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3475 u32 offset, u16 length, bool last_command,
3476 struct i40e_asq_cmd_details *cmd_details)
3478 struct i40e_aq_desc desc;
3479 struct i40e_aqc_nvm_update *cmd =
3480 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3481 enum i40e_status_code status;
3483 DEBUGFUNC("i40e_aq_erase_nvm");
3485 /* In offset the highest byte must be zeroed. */
3486 if (offset & 0xFF000000) {
3487 status = I40E_ERR_PARAM;
3488 goto i40e_aq_erase_nvm_exit;
3491 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3493 /* If this is the last command in a series, set the proper flag. */
3495 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3496 cmd->module_pointer = module_pointer;
3497 cmd->offset = CPU_TO_LE32(offset);
3498 cmd->length = CPU_TO_LE16(length);
3500 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3502 i40e_aq_erase_nvm_exit:
3507 * i40e_parse_discover_capabilities
3508 * @hw: pointer to the hw struct
3509 * @buff: pointer to a buffer containing device/function capability records
3510 * @cap_count: number of capability records in the list
3511 * @list_type_opc: type of capabilities list to parse
3513 * Parse the device/function capabilities list.
3515 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3517 enum i40e_admin_queue_opc list_type_opc)
3519 struct i40e_aqc_list_capabilities_element_resp *cap;
3520 u32 valid_functions, num_functions;
3521 u32 number, logical_id, phys_id;
3522 struct i40e_hw_capabilities *p;
3527 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3529 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3530 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3531 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3532 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3536 for (i = 0; i < cap_count; i++, cap++) {
3537 id = LE16_TO_CPU(cap->id);
3538 number = LE32_TO_CPU(cap->number);
3539 logical_id = LE32_TO_CPU(cap->logical_id);
3540 phys_id = LE32_TO_CPU(cap->phys_id);
3541 major_rev = cap->major_rev;
3544 case I40E_AQ_CAP_ID_SWITCH_MODE:
3545 p->switch_mode = number;
3546 i40e_debug(hw, I40E_DEBUG_INIT,
3547 "HW Capability: Switch mode = %d\n",
3550 case I40E_AQ_CAP_ID_MNG_MODE:
3551 p->management_mode = number;
3552 i40e_debug(hw, I40E_DEBUG_INIT,
3553 "HW Capability: Management Mode = %d\n",
3554 p->management_mode);
3556 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3557 p->npar_enable = number;
3558 i40e_debug(hw, I40E_DEBUG_INIT,
3559 "HW Capability: NPAR enable = %d\n",
3562 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3564 i40e_debug(hw, I40E_DEBUG_INIT,
3565 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3567 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3568 p->valid_functions = number;
3569 i40e_debug(hw, I40E_DEBUG_INIT,
3570 "HW Capability: Valid Functions = %d\n",
3571 p->valid_functions);
3573 case I40E_AQ_CAP_ID_SRIOV:
3575 p->sr_iov_1_1 = true;
3576 i40e_debug(hw, I40E_DEBUG_INIT,
3577 "HW Capability: SR-IOV = %d\n",
3580 case I40E_AQ_CAP_ID_VF:
3581 p->num_vfs = number;
3582 p->vf_base_id = logical_id;
3583 i40e_debug(hw, I40E_DEBUG_INIT,
3584 "HW Capability: VF count = %d\n",
3586 i40e_debug(hw, I40E_DEBUG_INIT,
3587 "HW Capability: VF base_id = %d\n",
3590 case I40E_AQ_CAP_ID_VMDQ:
3593 i40e_debug(hw, I40E_DEBUG_INIT,
3594 "HW Capability: VMDQ = %d\n", p->vmdq);
3596 case I40E_AQ_CAP_ID_8021QBG:
3598 p->evb_802_1_qbg = true;
3599 i40e_debug(hw, I40E_DEBUG_INIT,
3600 "HW Capability: 802.1Qbg = %d\n", number);
3602 case I40E_AQ_CAP_ID_8021QBR:
3604 p->evb_802_1_qbh = true;
3605 i40e_debug(hw, I40E_DEBUG_INIT,
3606 "HW Capability: 802.1Qbh = %d\n", number);
3608 case I40E_AQ_CAP_ID_VSI:
3609 p->num_vsis = number;
3610 i40e_debug(hw, I40E_DEBUG_INIT,
3611 "HW Capability: VSI count = %d\n",
3614 case I40E_AQ_CAP_ID_DCB:
3617 p->enabled_tcmap = logical_id;
3620 i40e_debug(hw, I40E_DEBUG_INIT,
3621 "HW Capability: DCB = %d\n", p->dcb);
3622 i40e_debug(hw, I40E_DEBUG_INIT,
3623 "HW Capability: TC Mapping = %d\n",
3625 i40e_debug(hw, I40E_DEBUG_INIT,
3626 "HW Capability: TC Max = %d\n", p->maxtc);
3628 case I40E_AQ_CAP_ID_FCOE:
3631 i40e_debug(hw, I40E_DEBUG_INIT,
3632 "HW Capability: FCOE = %d\n", p->fcoe);
3634 case I40E_AQ_CAP_ID_ISCSI:
3637 i40e_debug(hw, I40E_DEBUG_INIT,
3638 "HW Capability: iSCSI = %d\n", p->iscsi);
3640 case I40E_AQ_CAP_ID_RSS:
3642 p->rss_table_size = number;
3643 p->rss_table_entry_width = logical_id;
3644 i40e_debug(hw, I40E_DEBUG_INIT,
3645 "HW Capability: RSS = %d\n", p->rss);
3646 i40e_debug(hw, I40E_DEBUG_INIT,
3647 "HW Capability: RSS table size = %d\n",
3649 i40e_debug(hw, I40E_DEBUG_INIT,
3650 "HW Capability: RSS table width = %d\n",
3651 p->rss_table_entry_width);
3653 case I40E_AQ_CAP_ID_RXQ:
3654 p->num_rx_qp = number;
3655 p->base_queue = phys_id;
3656 i40e_debug(hw, I40E_DEBUG_INIT,
3657 "HW Capability: Rx QP = %d\n", number);
3658 i40e_debug(hw, I40E_DEBUG_INIT,
3659 "HW Capability: base_queue = %d\n",
3662 case I40E_AQ_CAP_ID_TXQ:
3663 p->num_tx_qp = number;
3664 p->base_queue = phys_id;
3665 i40e_debug(hw, I40E_DEBUG_INIT,
3666 "HW Capability: Tx QP = %d\n", number);
3667 i40e_debug(hw, I40E_DEBUG_INIT,
3668 "HW Capability: base_queue = %d\n",
3671 case I40E_AQ_CAP_ID_MSIX:
3672 p->num_msix_vectors = number;
3673 i40e_debug(hw, I40E_DEBUG_INIT,
3674 "HW Capability: MSIX vector count = %d\n",
3675 p->num_msix_vectors);
3677 case I40E_AQ_CAP_ID_VF_MSIX:
3678 p->num_msix_vectors_vf = number;
3679 i40e_debug(hw, I40E_DEBUG_INIT,
3680 "HW Capability: MSIX VF vector count = %d\n",
3681 p->num_msix_vectors_vf);
3683 case I40E_AQ_CAP_ID_FLEX10:
3684 if (major_rev == 1) {
3686 p->flex10_enable = true;
3687 p->flex10_capable = true;
3690 /* Capability revision >= 2 */
3692 p->flex10_enable = true;
3694 p->flex10_capable = true;
3696 p->flex10_mode = logical_id;
3697 p->flex10_status = phys_id;
3698 i40e_debug(hw, I40E_DEBUG_INIT,
3699 "HW Capability: Flex10 mode = %d\n",
3701 i40e_debug(hw, I40E_DEBUG_INIT,
3702 "HW Capability: Flex10 status = %d\n",
3705 case I40E_AQ_CAP_ID_CEM:
3708 i40e_debug(hw, I40E_DEBUG_INIT,
3709 "HW Capability: CEM = %d\n", p->mgmt_cem);
3711 case I40E_AQ_CAP_ID_IWARP:
3714 i40e_debug(hw, I40E_DEBUG_INIT,
3715 "HW Capability: iWARP = %d\n", p->iwarp);
3717 case I40E_AQ_CAP_ID_LED:
3718 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3719 p->led[phys_id] = true;
3720 i40e_debug(hw, I40E_DEBUG_INIT,
3721 "HW Capability: LED - PIN %d\n", phys_id);
3723 case I40E_AQ_CAP_ID_SDP:
3724 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3725 p->sdp[phys_id] = true;
3726 i40e_debug(hw, I40E_DEBUG_INIT,
3727 "HW Capability: SDP - PIN %d\n", phys_id);
3729 case I40E_AQ_CAP_ID_MDIO:
3731 p->mdio_port_num = phys_id;
3732 p->mdio_port_mode = logical_id;
3734 i40e_debug(hw, I40E_DEBUG_INIT,
3735 "HW Capability: MDIO port number = %d\n",
3737 i40e_debug(hw, I40E_DEBUG_INIT,
3738 "HW Capability: MDIO port mode = %d\n",
3741 case I40E_AQ_CAP_ID_1588:
3743 p->ieee_1588 = true;
3744 i40e_debug(hw, I40E_DEBUG_INIT,
3745 "HW Capability: IEEE 1588 = %d\n",
3748 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3750 p->fd_filters_guaranteed = number;
3751 p->fd_filters_best_effort = logical_id;
3752 i40e_debug(hw, I40E_DEBUG_INIT,
3753 "HW Capability: Flow Director = 1\n");
3754 i40e_debug(hw, I40E_DEBUG_INIT,
3755 "HW Capability: Guaranteed FD filters = %d\n",
3756 p->fd_filters_guaranteed);
3758 case I40E_AQ_CAP_ID_WSR_PROT:
3759 p->wr_csr_prot = (u64)number;
3760 p->wr_csr_prot |= (u64)logical_id << 32;
3761 i40e_debug(hw, I40E_DEBUG_INIT,
3762 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3763 (p->wr_csr_prot & 0xffff));
3766 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3767 hw->num_wol_proxy_filters = (u16)number;
3768 hw->wol_proxy_vsi_seid = (u16)logical_id;
3769 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3770 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3771 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3773 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3774 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3775 p->proxy_support = p->proxy_support;
3776 i40e_debug(hw, I40E_DEBUG_INIT,
3777 "HW Capability: WOL proxy filters = %d\n",
3778 hw->num_wol_proxy_filters);
3787 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3789 #ifdef I40E_FCOE_ENA
3790 /* Software override ensuring FCoE is disabled if npar or mfp
3791 * mode because it is not supported in these modes.
3793 if (p->npar_enable || p->flex10_enable)
3796 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3800 /* count the enabled ports (aka the "not disabled" ports) */
3802 for (i = 0; i < 4; i++) {
3803 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3806 /* use AQ read to get the physical register offset instead
3807 * of the port relative offset
3809 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3810 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3814 valid_functions = p->valid_functions;
3816 while (valid_functions) {
3817 if (valid_functions & 1)
3819 valid_functions >>= 1;
3822 /* partition id is 1-based, and functions are evenly spread
3823 * across the ports as partitions
3825 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3826 hw->num_partitions = num_functions / hw->num_ports;
3828 /* additional HW specific goodies that might
3829 * someday be HW version specific
3831 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3835 * i40e_aq_discover_capabilities
3836 * @hw: pointer to the hw struct
3837 * @buff: a virtual buffer to hold the capabilities
3838 * @buff_size: Size of the virtual buffer
3839 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3840 * @list_type_opc: capabilities type to discover - pass in the command opcode
3841 * @cmd_details: pointer to command details structure or NULL
3843 * Get the device capabilities descriptions from the firmware
3845 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3846 void *buff, u16 buff_size, u16 *data_size,
3847 enum i40e_admin_queue_opc list_type_opc,
3848 struct i40e_asq_cmd_details *cmd_details)
3850 struct i40e_aqc_list_capabilites *cmd;
3851 struct i40e_aq_desc desc;
3852 enum i40e_status_code status = I40E_SUCCESS;
3854 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3856 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3857 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3858 status = I40E_ERR_PARAM;
3862 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3864 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3865 if (buff_size > I40E_AQ_LARGE_BUF)
3866 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3868 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3869 *data_size = LE16_TO_CPU(desc.datalen);
3874 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3882 * i40e_aq_update_nvm
3883 * @hw: pointer to the hw struct
3884 * @module_pointer: module pointer location in words from the NVM beginning
3885 * @offset: byte offset from the module beginning
3886 * @length: length of the section to be written (in bytes from the offset)
3887 * @data: command buffer (size [bytes] = length)
3888 * @last_command: tells if this is the last command in a series
3889 * @cmd_details: pointer to command details structure or NULL
3891 * Update the NVM using the admin queue commands
3893 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3894 u32 offset, u16 length, void *data,
3896 struct i40e_asq_cmd_details *cmd_details)
3898 struct i40e_aq_desc desc;
3899 struct i40e_aqc_nvm_update *cmd =
3900 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3901 enum i40e_status_code status;
3903 DEBUGFUNC("i40e_aq_update_nvm");
3905 /* In offset the highest byte must be zeroed. */
3906 if (offset & 0xFF000000) {
3907 status = I40E_ERR_PARAM;
3908 goto i40e_aq_update_nvm_exit;
3911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3913 /* If this is the last command in a series, set the proper flag. */
3915 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3916 cmd->module_pointer = module_pointer;
3917 cmd->offset = CPU_TO_LE32(offset);
3918 cmd->length = CPU_TO_LE16(length);
3920 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3921 if (length > I40E_AQ_LARGE_BUF)
3922 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3924 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3926 i40e_aq_update_nvm_exit:
3931 * i40e_aq_get_lldp_mib
3932 * @hw: pointer to the hw struct
3933 * @bridge_type: type of bridge requested
3934 * @mib_type: Local, Remote or both Local and Remote MIBs
3935 * @buff: pointer to a user supplied buffer to store the MIB block
3936 * @buff_size: size of the buffer (in bytes)
3937 * @local_len : length of the returned Local LLDP MIB
3938 * @remote_len: length of the returned Remote LLDP MIB
3939 * @cmd_details: pointer to command details structure or NULL
3941 * Requests the complete LLDP MIB (entire packet).
3943 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3944 u8 mib_type, void *buff, u16 buff_size,
3945 u16 *local_len, u16 *remote_len,
3946 struct i40e_asq_cmd_details *cmd_details)
3948 struct i40e_aq_desc desc;
3949 struct i40e_aqc_lldp_get_mib *cmd =
3950 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3951 struct i40e_aqc_lldp_get_mib *resp =
3952 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3953 enum i40e_status_code status;
3955 if (buff_size == 0 || !buff)
3956 return I40E_ERR_PARAM;
3958 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3959 /* Indirect Command */
3960 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3962 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3963 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3964 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3966 desc.datalen = CPU_TO_LE16(buff_size);
3968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3969 if (buff_size > I40E_AQ_LARGE_BUF)
3970 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3972 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3974 if (local_len != NULL)
3975 *local_len = LE16_TO_CPU(resp->local_len);
3976 if (remote_len != NULL)
3977 *remote_len = LE16_TO_CPU(resp->remote_len);
3984 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3985 * @hw: pointer to the hw struct
3986 * @mib_type: Local, Remote or both Local and Remote MIBs
3987 * @buff: pointer to a user supplied buffer to store the MIB block
3988 * @buff_size: size of the buffer (in bytes)
3989 * @cmd_details: pointer to command details structure or NULL
3993 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3994 u8 mib_type, void *buff, u16 buff_size,
3995 struct i40e_asq_cmd_details *cmd_details)
3997 struct i40e_aq_desc desc;
3998 struct i40e_aqc_lldp_set_local_mib *cmd =
3999 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4000 enum i40e_status_code status;
4002 if (buff_size == 0 || !buff)
4003 return I40E_ERR_PARAM;
4005 i40e_fill_default_direct_cmd_desc(&desc,
4006 i40e_aqc_opc_lldp_set_local_mib);
4007 /* Indirect Command */
4008 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4009 if (buff_size > I40E_AQ_LARGE_BUF)
4010 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4011 desc.datalen = CPU_TO_LE16(buff_size);
4013 cmd->type = mib_type;
4014 cmd->length = CPU_TO_LE16(buff_size);
4015 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4016 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4018 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4023 * i40e_aq_cfg_lldp_mib_change_event
4024 * @hw: pointer to the hw struct
4025 * @enable_update: Enable or Disable event posting
4026 * @cmd_details: pointer to command details structure or NULL
4028 * Enable or Disable posting of an event on ARQ when LLDP MIB
4029 * associated with the interface changes
4031 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4033 struct i40e_asq_cmd_details *cmd_details)
4035 struct i40e_aq_desc desc;
4036 struct i40e_aqc_lldp_update_mib *cmd =
4037 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4038 enum i40e_status_code status;
4040 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4043 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4051 * i40e_aq_add_lldp_tlv
4052 * @hw: pointer to the hw struct
4053 * @bridge_type: type of bridge
4054 * @buff: buffer with TLV to add
4055 * @buff_size: length of the buffer
4056 * @tlv_len: length of the TLV to be added
4057 * @mib_len: length of the LLDP MIB returned in response
4058 * @cmd_details: pointer to command details structure or NULL
4060 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4061 * it is responsibility of the caller to make sure that the TLV is not
4062 * already present in the LLDPDU.
4063 * In return firmware will write the complete LLDP MIB with the newly
4064 * added TLV in the response buffer.
4066 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4067 void *buff, u16 buff_size, u16 tlv_len,
4069 struct i40e_asq_cmd_details *cmd_details)
4071 struct i40e_aq_desc desc;
4072 struct i40e_aqc_lldp_add_tlv *cmd =
4073 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4074 enum i40e_status_code status;
4076 if (buff_size == 0 || !buff || tlv_len == 0)
4077 return I40E_ERR_PARAM;
4079 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4081 /* Indirect Command */
4082 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4083 if (buff_size > I40E_AQ_LARGE_BUF)
4084 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4085 desc.datalen = CPU_TO_LE16(buff_size);
4087 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4088 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4089 cmd->len = CPU_TO_LE16(tlv_len);
4091 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4093 if (mib_len != NULL)
4094 *mib_len = LE16_TO_CPU(desc.datalen);
4101 * i40e_aq_update_lldp_tlv
4102 * @hw: pointer to the hw struct
4103 * @bridge_type: type of bridge
4104 * @buff: buffer with TLV to update
4105 * @buff_size: size of the buffer holding original and updated TLVs
4106 * @old_len: Length of the Original TLV
4107 * @new_len: Length of the Updated TLV
4108 * @offset: offset of the updated TLV in the buff
4109 * @mib_len: length of the returned LLDP MIB
4110 * @cmd_details: pointer to command details structure or NULL
4112 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4113 * Firmware will place the complete LLDP MIB in response buffer with the
4116 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4117 u8 bridge_type, void *buff, u16 buff_size,
4118 u16 old_len, u16 new_len, u16 offset,
4120 struct i40e_asq_cmd_details *cmd_details)
4122 struct i40e_aq_desc desc;
4123 struct i40e_aqc_lldp_update_tlv *cmd =
4124 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4125 enum i40e_status_code status;
4127 if (buff_size == 0 || !buff || offset == 0 ||
4128 old_len == 0 || new_len == 0)
4129 return I40E_ERR_PARAM;
4131 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4133 /* Indirect Command */
4134 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4135 if (buff_size > I40E_AQ_LARGE_BUF)
4136 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4137 desc.datalen = CPU_TO_LE16(buff_size);
4139 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4140 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4141 cmd->old_len = CPU_TO_LE16(old_len);
4142 cmd->new_offset = CPU_TO_LE16(offset);
4143 cmd->new_len = CPU_TO_LE16(new_len);
4145 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4147 if (mib_len != NULL)
4148 *mib_len = LE16_TO_CPU(desc.datalen);
4155 * i40e_aq_delete_lldp_tlv
4156 * @hw: pointer to the hw struct
4157 * @bridge_type: type of bridge
4158 * @buff: pointer to a user supplied buffer that has the TLV
4159 * @buff_size: length of the buffer
4160 * @tlv_len: length of the TLV to be deleted
4161 * @mib_len: length of the returned LLDP MIB
4162 * @cmd_details: pointer to command details structure or NULL
4164 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4165 * The firmware places the entire LLDP MIB in the response buffer.
4167 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4168 u8 bridge_type, void *buff, u16 buff_size,
4169 u16 tlv_len, u16 *mib_len,
4170 struct i40e_asq_cmd_details *cmd_details)
4172 struct i40e_aq_desc desc;
4173 struct i40e_aqc_lldp_add_tlv *cmd =
4174 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4175 enum i40e_status_code status;
4177 if (buff_size == 0 || !buff)
4178 return I40E_ERR_PARAM;
4180 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4182 /* Indirect Command */
4183 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4184 if (buff_size > I40E_AQ_LARGE_BUF)
4185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4186 desc.datalen = CPU_TO_LE16(buff_size);
4187 cmd->len = CPU_TO_LE16(tlv_len);
4188 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4189 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4191 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4193 if (mib_len != NULL)
4194 *mib_len = LE16_TO_CPU(desc.datalen);
4202 * @hw: pointer to the hw struct
4203 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4204 * @cmd_details: pointer to command details structure or NULL
4206 * Stop or Shutdown the embedded LLDP Agent
4208 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4209 struct i40e_asq_cmd_details *cmd_details)
4211 struct i40e_aq_desc desc;
4212 struct i40e_aqc_lldp_stop *cmd =
4213 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4214 enum i40e_status_code status;
4216 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4219 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4221 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4227 * i40e_aq_start_lldp
4228 * @hw: pointer to the hw struct
4229 * @cmd_details: pointer to command details structure or NULL
4231 * Start the embedded LLDP Agent on all ports.
4233 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4234 struct i40e_asq_cmd_details *cmd_details)
4236 struct i40e_aq_desc desc;
4237 struct i40e_aqc_lldp_start *cmd =
4238 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4239 enum i40e_status_code status;
4241 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4243 cmd->command = I40E_AQ_LLDP_AGENT_START;
4245 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4251 * i40e_aq_get_cee_dcb_config
4252 * @hw: pointer to the hw struct
4253 * @buff: response buffer that stores CEE operational configuration
4254 * @buff_size: size of the buffer passed
4255 * @cmd_details: pointer to command details structure or NULL
4257 * Get CEE DCBX mode operational configuration from firmware
4259 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4260 void *buff, u16 buff_size,
4261 struct i40e_asq_cmd_details *cmd_details)
4263 struct i40e_aq_desc desc;
4264 enum i40e_status_code status;
4266 if (buff_size == 0 || !buff)
4267 return I40E_ERR_PARAM;
4269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4271 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4272 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4279 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4280 * @hw: pointer to the hw struct
4281 * @start_agent: True if DCBx Agent needs to be Started
4282 * False if DCBx Agent needs to be Stopped
4283 * @cmd_details: pointer to command details structure or NULL
4285 * Start/Stop the embedded dcbx Agent
4287 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4289 struct i40e_asq_cmd_details *cmd_details)
4291 struct i40e_aq_desc desc;
4292 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4293 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4295 enum i40e_status_code status;
4297 i40e_fill_default_direct_cmd_desc(&desc,
4298 i40e_aqc_opc_lldp_stop_start_spec_agent);
4301 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4303 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4309 * i40e_aq_add_udp_tunnel
4310 * @hw: pointer to the hw struct
4311 * @udp_port: the UDP port to add
4312 * @header_len: length of the tunneling header length in DWords
4313 * @protocol_index: protocol index type
4314 * @filter_index: pointer to filter index
4315 * @cmd_details: pointer to command details structure or NULL
4317 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4318 u16 udp_port, u8 protocol_index,
4320 struct i40e_asq_cmd_details *cmd_details)
4322 struct i40e_aq_desc desc;
4323 struct i40e_aqc_add_udp_tunnel *cmd =
4324 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4325 struct i40e_aqc_del_udp_tunnel_completion *resp =
4326 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4327 enum i40e_status_code status;
4329 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4331 cmd->udp_port = CPU_TO_LE16(udp_port);
4332 cmd->protocol_type = protocol_index;
4334 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4336 if (!status && filter_index)
4337 *filter_index = resp->index;
4343 * i40e_aq_del_udp_tunnel
4344 * @hw: pointer to the hw struct
4345 * @index: filter index
4346 * @cmd_details: pointer to command details structure or NULL
4348 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4349 struct i40e_asq_cmd_details *cmd_details)
4351 struct i40e_aq_desc desc;
4352 struct i40e_aqc_remove_udp_tunnel *cmd =
4353 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4354 enum i40e_status_code status;
4356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4360 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4366 * i40e_aq_get_switch_resource_alloc (0x0204)
4367 * @hw: pointer to the hw struct
4368 * @num_entries: pointer to u8 to store the number of resource entries returned
4369 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4370 * to store the resource information for all resource types. Each
4371 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4372 * @count: size, in bytes, of the buffer provided
4373 * @cmd_details: pointer to command details structure or NULL
4375 * Query the resources allocated to a function.
4377 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4379 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4381 struct i40e_asq_cmd_details *cmd_details)
4383 struct i40e_aq_desc desc;
4384 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4385 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4386 enum i40e_status_code status;
4387 u16 length = count * sizeof(*buf);
4389 i40e_fill_default_direct_cmd_desc(&desc,
4390 i40e_aqc_opc_get_switch_resource_alloc);
4392 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4393 if (length > I40E_AQ_LARGE_BUF)
4394 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4396 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4398 if (!status && num_entries)
4399 *num_entries = cmd_resp->num_entries;
4405 * i40e_aq_delete_element - Delete switch element
4406 * @hw: pointer to the hw struct
4407 * @seid: the SEID to delete from the switch
4408 * @cmd_details: pointer to command details structure or NULL
4410 * This deletes a switch element from the switch.
4412 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4413 struct i40e_asq_cmd_details *cmd_details)
4415 struct i40e_aq_desc desc;
4416 struct i40e_aqc_switch_seid *cmd =
4417 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4418 enum i40e_status_code status;
4421 return I40E_ERR_PARAM;
4423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4425 cmd->seid = CPU_TO_LE16(seid);
4427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4433 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4434 * @hw: pointer to the hw struct
4435 * @flags: component flags
4436 * @mac_seid: uplink seid (MAC SEID)
4437 * @vsi_seid: connected vsi seid
4438 * @ret_seid: seid of create pv component
4440 * This instantiates an i40e port virtualizer with specified flags.
4441 * Depending on specified flags the port virtualizer can act as a
4442 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4444 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4445 u16 mac_seid, u16 vsi_seid,
4448 struct i40e_aq_desc desc;
4449 struct i40e_aqc_add_update_pv *cmd =
4450 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4451 struct i40e_aqc_add_update_pv_completion *resp =
4452 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4453 enum i40e_status_code status;
4456 return I40E_ERR_PARAM;
4458 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4459 cmd->command_flags = CPU_TO_LE16(flags);
4460 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4461 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4463 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4464 if (!status && ret_seid)
4465 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4471 * i40e_aq_add_tag - Add an S/E-tag
4472 * @hw: pointer to the hw struct
4473 * @direct_to_queue: should s-tag direct flow to a specific queue
4474 * @vsi_seid: VSI SEID to use this tag
4475 * @tag: value of the tag
4476 * @queue_num: queue number, only valid is direct_to_queue is true
4477 * @tags_used: return value, number of tags in use by this PF
4478 * @tags_free: return value, number of unallocated tags
4479 * @cmd_details: pointer to command details structure or NULL
4481 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4482 * the number of tags allocated by the PF, and the number of unallocated
4485 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4486 u16 vsi_seid, u16 tag, u16 queue_num,
4487 u16 *tags_used, u16 *tags_free,
4488 struct i40e_asq_cmd_details *cmd_details)
4490 struct i40e_aq_desc desc;
4491 struct i40e_aqc_add_tag *cmd =
4492 (struct i40e_aqc_add_tag *)&desc.params.raw;
4493 struct i40e_aqc_add_remove_tag_completion *resp =
4494 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4495 enum i40e_status_code status;
4498 return I40E_ERR_PARAM;
4500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4502 cmd->seid = CPU_TO_LE16(vsi_seid);
4503 cmd->tag = CPU_TO_LE16(tag);
4504 if (direct_to_queue) {
4505 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4506 cmd->queue_number = CPU_TO_LE16(queue_num);
4509 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4512 if (tags_used != NULL)
4513 *tags_used = LE16_TO_CPU(resp->tags_used);
4514 if (tags_free != NULL)
4515 *tags_free = LE16_TO_CPU(resp->tags_free);
4522 * i40e_aq_remove_tag - Remove an S- or E-tag
4523 * @hw: pointer to the hw struct
4524 * @vsi_seid: VSI SEID this tag is associated with
4525 * @tag: value of the S-tag to delete
4526 * @tags_used: return value, number of tags in use by this PF
4527 * @tags_free: return value, number of unallocated tags
4528 * @cmd_details: pointer to command details structure or NULL
4530 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4531 * the number of tags allocated by the PF, and the number of unallocated
4534 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4535 u16 tag, u16 *tags_used, u16 *tags_free,
4536 struct i40e_asq_cmd_details *cmd_details)
4538 struct i40e_aq_desc desc;
4539 struct i40e_aqc_remove_tag *cmd =
4540 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4541 struct i40e_aqc_add_remove_tag_completion *resp =
4542 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4543 enum i40e_status_code status;
4546 return I40E_ERR_PARAM;
4548 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4550 cmd->seid = CPU_TO_LE16(vsi_seid);
4551 cmd->tag = CPU_TO_LE16(tag);
4553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4556 if (tags_used != NULL)
4557 *tags_used = LE16_TO_CPU(resp->tags_used);
4558 if (tags_free != NULL)
4559 *tags_free = LE16_TO_CPU(resp->tags_free);
4566 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4567 * @hw: pointer to the hw struct
4568 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4569 * @etag: value of E-tag to add
4570 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4571 * @buf: address of indirect buffer
4572 * @tags_used: return value, number of E-tags in use by this port
4573 * @tags_free: return value, number of unallocated M-tags
4574 * @cmd_details: pointer to command details structure or NULL
4576 * This associates a multicast E-tag to a port virtualizer. It will return
4577 * the number of tags allocated by the PF, and the number of unallocated
4580 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4581 * num_tags_in_buf long.
4583 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4584 u16 etag, u8 num_tags_in_buf, void *buf,
4585 u16 *tags_used, u16 *tags_free,
4586 struct i40e_asq_cmd_details *cmd_details)
4588 struct i40e_aq_desc desc;
4589 struct i40e_aqc_add_remove_mcast_etag *cmd =
4590 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4591 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4592 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4593 enum i40e_status_code status;
4594 u16 length = sizeof(u16) * num_tags_in_buf;
4596 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4597 return I40E_ERR_PARAM;
4599 i40e_fill_default_direct_cmd_desc(&desc,
4600 i40e_aqc_opc_add_multicast_etag);
4602 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4603 cmd->etag = CPU_TO_LE16(etag);
4604 cmd->num_unicast_etags = num_tags_in_buf;
4606 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4607 if (length > I40E_AQ_LARGE_BUF)
4608 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4610 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4613 if (tags_used != NULL)
4614 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4615 if (tags_free != NULL)
4616 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4623 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4624 * @hw: pointer to the hw struct
4625 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4626 * @etag: value of the E-tag to remove
4627 * @tags_used: return value, number of tags in use by this port
4628 * @tags_free: return value, number of unallocated tags
4629 * @cmd_details: pointer to command details structure or NULL
4631 * This deletes an E-tag from the port virtualizer. It will return
4632 * the number of tags allocated by the port, and the number of unallocated
4635 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4636 u16 etag, u16 *tags_used, u16 *tags_free,
4637 struct i40e_asq_cmd_details *cmd_details)
4639 struct i40e_aq_desc desc;
4640 struct i40e_aqc_add_remove_mcast_etag *cmd =
4641 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4642 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4643 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4644 enum i40e_status_code status;
4648 return I40E_ERR_PARAM;
4650 i40e_fill_default_direct_cmd_desc(&desc,
4651 i40e_aqc_opc_remove_multicast_etag);
4653 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4654 cmd->etag = CPU_TO_LE16(etag);
4656 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4659 if (tags_used != NULL)
4660 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4661 if (tags_free != NULL)
4662 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4669 * i40e_aq_update_tag - Update an S/E-tag
4670 * @hw: pointer to the hw struct
4671 * @vsi_seid: VSI SEID using this S-tag
4672 * @old_tag: old tag value
4673 * @new_tag: new tag value
4674 * @tags_used: return value, number of tags in use by this PF
4675 * @tags_free: return value, number of unallocated tags
4676 * @cmd_details: pointer to command details structure or NULL
4678 * This updates the value of the tag currently attached to this VSI
4679 * in the switch complex. It will return the number of tags allocated
4680 * by the PF, and the number of unallocated tags available.
4682 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4683 u16 old_tag, u16 new_tag, u16 *tags_used,
4685 struct i40e_asq_cmd_details *cmd_details)
4687 struct i40e_aq_desc desc;
4688 struct i40e_aqc_update_tag *cmd =
4689 (struct i40e_aqc_update_tag *)&desc.params.raw;
4690 struct i40e_aqc_update_tag_completion *resp =
4691 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4692 enum i40e_status_code status;
4695 return I40E_ERR_PARAM;
4697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4699 cmd->seid = CPU_TO_LE16(vsi_seid);
4700 cmd->old_tag = CPU_TO_LE16(old_tag);
4701 cmd->new_tag = CPU_TO_LE16(new_tag);
4703 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4706 if (tags_used != NULL)
4707 *tags_used = LE16_TO_CPU(resp->tags_used);
4708 if (tags_free != NULL)
4709 *tags_free = LE16_TO_CPU(resp->tags_free);
4716 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4717 * @hw: pointer to the hw struct
4718 * @tcmap: TC map for request/release any ignore PFC condition
4719 * @request: request or release ignore PFC condition
4720 * @tcmap_ret: return TCs for which PFC is currently ignored
4721 * @cmd_details: pointer to command details structure or NULL
4723 * This sends out request/release to ignore PFC condition for a TC.
4724 * It will return the TCs for which PFC is currently ignored.
4726 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4727 bool request, u8 *tcmap_ret,
4728 struct i40e_asq_cmd_details *cmd_details)
4730 struct i40e_aq_desc desc;
4731 struct i40e_aqc_pfc_ignore *cmd_resp =
4732 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4733 enum i40e_status_code status;
4735 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4738 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4740 cmd_resp->tc_bitmap = tcmap;
4742 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4745 if (tcmap_ret != NULL)
4746 *tcmap_ret = cmd_resp->tc_bitmap;
4753 * i40e_aq_dcb_updated - DCB Updated Command
4754 * @hw: pointer to the hw struct
4755 * @cmd_details: pointer to command details structure or NULL
4757 * When LLDP is handled in PF this command is used by the PF
4758 * to notify EMP that a DCB setting is modified.
4759 * When LLDP is handled in EMP this command is used by the PF
4760 * to notify EMP whenever one of the following parameters get
4762 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4763 * - PCIRTT in PRTDCB_GENC.PCIRTT
4764 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4765 * EMP will return when the shared RPB settings have been
4766 * recomputed and modified. The retval field in the descriptor
4767 * will be set to 0 when RPB is modified.
4769 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4770 struct i40e_asq_cmd_details *cmd_details)
4772 struct i40e_aq_desc desc;
4773 enum i40e_status_code status;
4775 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4783 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4784 * @hw: pointer to the hw struct
4785 * @seid: defines the SEID of the switch for which the stats are requested
4786 * @vlan_id: the VLAN ID for which the statistics are requested
4787 * @stat_index: index of the statistics counters block assigned to this VLAN
4788 * @cmd_details: pointer to command details structure or NULL
4790 * XL710 supports 128 smonVlanStats counters.This command is used to
4791 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4794 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4795 u16 vlan_id, u16 *stat_index,
4796 struct i40e_asq_cmd_details *cmd_details)
4798 struct i40e_aq_desc desc;
4799 struct i40e_aqc_add_remove_statistics *cmd_resp =
4800 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4801 enum i40e_status_code status;
4803 if ((seid == 0) || (stat_index == NULL))
4804 return I40E_ERR_PARAM;
4806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4808 cmd_resp->seid = CPU_TO_LE16(seid);
4809 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4813 if (!status && stat_index)
4814 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4820 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4821 * @hw: pointer to the hw struct
4822 * @seid: defines the SEID of the switch for which the stats are requested
4823 * @vlan_id: the VLAN ID for which the statistics are requested
4824 * @stat_index: index of the statistics counters block assigned to this VLAN
4825 * @cmd_details: pointer to command details structure or NULL
4827 * XL710 supports 128 smonVlanStats counters.This command is used to
4828 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4831 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4832 u16 vlan_id, u16 stat_index,
4833 struct i40e_asq_cmd_details *cmd_details)
4835 struct i40e_aq_desc desc;
4836 struct i40e_aqc_add_remove_statistics *cmd =
4837 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4838 enum i40e_status_code status;
4841 return I40E_ERR_PARAM;
4843 i40e_fill_default_direct_cmd_desc(&desc,
4844 i40e_aqc_opc_remove_statistics);
4846 cmd->seid = CPU_TO_LE16(seid);
4847 cmd->vlan = CPU_TO_LE16(vlan_id);
4848 cmd->stat_index = CPU_TO_LE16(stat_index);
4850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4856 * i40e_aq_set_port_parameters - set physical port parameters.
4857 * @hw: pointer to the hw struct
4858 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4859 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4860 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4861 * @double_vlan: if set double VLAN is enabled
4862 * @cmd_details: pointer to command details structure or NULL
4864 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4865 u16 bad_frame_vsi, bool save_bad_pac,
4866 bool pad_short_pac, bool double_vlan,
4867 struct i40e_asq_cmd_details *cmd_details)
4869 struct i40e_aqc_set_port_parameters *cmd;
4870 enum i40e_status_code status;
4871 struct i40e_aq_desc desc;
4872 u16 command_flags = 0;
4874 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4876 i40e_fill_default_direct_cmd_desc(&desc,
4877 i40e_aqc_opc_set_port_parameters);
4879 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4881 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4883 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4885 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4886 cmd->command_flags = CPU_TO_LE16(command_flags);
4888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4894 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4895 * @hw: pointer to the hw struct
4896 * @seid: seid for the physical port/switching component/vsi
4897 * @buff: Indirect buffer to hold data parameters and response
4898 * @buff_size: Indirect buffer size
4899 * @opcode: Tx scheduler AQ command opcode
4900 * @cmd_details: pointer to command details structure or NULL
4902 * Generic command handler for Tx scheduler AQ commands
4904 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4905 void *buff, u16 buff_size,
4906 enum i40e_admin_queue_opc opcode,
4907 struct i40e_asq_cmd_details *cmd_details)
4909 struct i40e_aq_desc desc;
4910 struct i40e_aqc_tx_sched_ind *cmd =
4911 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4912 enum i40e_status_code status;
4913 bool cmd_param_flag = false;
4916 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4917 case i40e_aqc_opc_configure_vsi_tc_bw:
4918 case i40e_aqc_opc_enable_switching_comp_ets:
4919 case i40e_aqc_opc_modify_switching_comp_ets:
4920 case i40e_aqc_opc_disable_switching_comp_ets:
4921 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4922 case i40e_aqc_opc_configure_switching_comp_bw_config:
4923 cmd_param_flag = true;
4925 case i40e_aqc_opc_query_vsi_bw_config:
4926 case i40e_aqc_opc_query_vsi_ets_sla_config:
4927 case i40e_aqc_opc_query_switching_comp_ets_config:
4928 case i40e_aqc_opc_query_port_ets_config:
4929 case i40e_aqc_opc_query_switching_comp_bw_config:
4930 cmd_param_flag = false;
4933 return I40E_ERR_PARAM;
4936 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4938 /* Indirect command */
4939 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4941 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4942 if (buff_size > I40E_AQ_LARGE_BUF)
4943 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4945 desc.datalen = CPU_TO_LE16(buff_size);
4947 cmd->vsi_seid = CPU_TO_LE16(seid);
4949 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4955 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4956 * @hw: pointer to the hw struct
4958 * @credit: BW limit credits (0 = disabled)
4959 * @max_credit: Max BW limit credits
4960 * @cmd_details: pointer to command details structure or NULL
4962 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4963 u16 seid, u16 credit, u8 max_credit,
4964 struct i40e_asq_cmd_details *cmd_details)
4966 struct i40e_aq_desc desc;
4967 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4968 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4969 enum i40e_status_code status;
4971 i40e_fill_default_direct_cmd_desc(&desc,
4972 i40e_aqc_opc_configure_vsi_bw_limit);
4974 cmd->vsi_seid = CPU_TO_LE16(seid);
4975 cmd->credit = CPU_TO_LE16(credit);
4976 cmd->max_credit = max_credit;
4978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4984 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4985 * @hw: pointer to the hw struct
4986 * @seid: switching component seid
4987 * @credit: BW limit credits (0 = disabled)
4988 * @max_bw: Max BW limit credits
4989 * @cmd_details: pointer to command details structure or NULL
4991 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4992 u16 seid, u16 credit, u8 max_bw,
4993 struct i40e_asq_cmd_details *cmd_details)
4995 struct i40e_aq_desc desc;
4996 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4997 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4998 enum i40e_status_code status;
5000 i40e_fill_default_direct_cmd_desc(&desc,
5001 i40e_aqc_opc_configure_switching_comp_bw_limit);
5003 cmd->seid = CPU_TO_LE16(seid);
5004 cmd->credit = CPU_TO_LE16(credit);
5005 cmd->max_bw = max_bw;
5007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5013 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5014 * @hw: pointer to the hw struct
5016 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5017 * @cmd_details: pointer to command details structure or NULL
5019 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5021 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5022 struct i40e_asq_cmd_details *cmd_details)
5024 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5025 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5030 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5031 * @hw: pointer to the hw struct
5033 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5034 * @cmd_details: pointer to command details structure or NULL
5036 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5038 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5039 struct i40e_asq_cmd_details *cmd_details)
5041 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5042 i40e_aqc_opc_configure_vsi_tc_bw,
5047 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5048 * @hw: pointer to the hw struct
5049 * @seid: seid of the switching component connected to Physical Port
5050 * @ets_data: Buffer holding ETS parameters
5051 * @cmd_details: pointer to command details structure or NULL
5053 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5055 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5056 enum i40e_admin_queue_opc opcode,
5057 struct i40e_asq_cmd_details *cmd_details)
5059 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5060 sizeof(*ets_data), opcode, cmd_details);
5064 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5065 * @hw: pointer to the hw struct
5066 * @seid: seid of the switching component
5067 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5068 * @cmd_details: pointer to command details structure or NULL
5070 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5072 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5073 struct i40e_asq_cmd_details *cmd_details)
5075 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5076 i40e_aqc_opc_configure_switching_comp_bw_config,
5081 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5082 * @hw: pointer to the hw struct
5083 * @seid: seid of the switching component
5084 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5085 * @cmd_details: pointer to command details structure or NULL
5087 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5088 struct i40e_hw *hw, u16 seid,
5089 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5090 struct i40e_asq_cmd_details *cmd_details)
5092 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5093 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5098 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5099 * @hw: pointer to the hw struct
5100 * @seid: seid of the VSI
5101 * @bw_data: Buffer to hold VSI BW configuration
5102 * @cmd_details: pointer to command details structure or NULL
5104 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5106 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5107 struct i40e_asq_cmd_details *cmd_details)
5109 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5110 i40e_aqc_opc_query_vsi_bw_config,
5115 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5116 * @hw: pointer to the hw struct
5117 * @seid: seid of the VSI
5118 * @bw_data: Buffer to hold VSI BW configuration per TC
5119 * @cmd_details: pointer to command details structure or NULL
5121 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5123 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5124 struct i40e_asq_cmd_details *cmd_details)
5126 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5127 i40e_aqc_opc_query_vsi_ets_sla_config,
5132 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5133 * @hw: pointer to the hw struct
5134 * @seid: seid of the switching component
5135 * @bw_data: Buffer to hold switching component's per TC BW config
5136 * @cmd_details: pointer to command details structure or NULL
5138 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5140 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5141 struct i40e_asq_cmd_details *cmd_details)
5143 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5144 i40e_aqc_opc_query_switching_comp_ets_config,
5149 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5150 * @hw: pointer to the hw struct
5151 * @seid: seid of the VSI or switching component connected to Physical Port
5152 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5153 * @cmd_details: pointer to command details structure or NULL
5155 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5157 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5158 struct i40e_asq_cmd_details *cmd_details)
5160 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5161 i40e_aqc_opc_query_port_ets_config,
5166 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5167 * @hw: pointer to the hw struct
5168 * @seid: seid of the switching component
5169 * @bw_data: Buffer to hold switching component's BW configuration
5170 * @cmd_details: pointer to command details structure or NULL
5172 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5174 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5175 struct i40e_asq_cmd_details *cmd_details)
5177 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5178 i40e_aqc_opc_query_switching_comp_bw_config,
5183 * i40e_validate_filter_settings
5184 * @hw: pointer to the hardware structure
5185 * @settings: Filter control settings
5187 * Check and validate the filter control settings passed.
5188 * The function checks for the valid filter/context sizes being
5189 * passed for FCoE and PE.
5191 * Returns I40E_SUCCESS if the values passed are valid and within
5192 * range else returns an error.
5194 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5195 struct i40e_filter_control_settings *settings)
5197 u32 fcoe_cntx_size, fcoe_filt_size;
5198 u32 pe_cntx_size, pe_filt_size;
5203 /* Validate FCoE settings passed */
5204 switch (settings->fcoe_filt_num) {
5205 case I40E_HASH_FILTER_SIZE_1K:
5206 case I40E_HASH_FILTER_SIZE_2K:
5207 case I40E_HASH_FILTER_SIZE_4K:
5208 case I40E_HASH_FILTER_SIZE_8K:
5209 case I40E_HASH_FILTER_SIZE_16K:
5210 case I40E_HASH_FILTER_SIZE_32K:
5211 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5212 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5215 return I40E_ERR_PARAM;
5218 switch (settings->fcoe_cntx_num) {
5219 case I40E_DMA_CNTX_SIZE_512:
5220 case I40E_DMA_CNTX_SIZE_1K:
5221 case I40E_DMA_CNTX_SIZE_2K:
5222 case I40E_DMA_CNTX_SIZE_4K:
5223 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5224 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5227 return I40E_ERR_PARAM;
5230 /* Validate PE settings passed */
5231 switch (settings->pe_filt_num) {
5232 case I40E_HASH_FILTER_SIZE_1K:
5233 case I40E_HASH_FILTER_SIZE_2K:
5234 case I40E_HASH_FILTER_SIZE_4K:
5235 case I40E_HASH_FILTER_SIZE_8K:
5236 case I40E_HASH_FILTER_SIZE_16K:
5237 case I40E_HASH_FILTER_SIZE_32K:
5238 case I40E_HASH_FILTER_SIZE_64K:
5239 case I40E_HASH_FILTER_SIZE_128K:
5240 case I40E_HASH_FILTER_SIZE_256K:
5241 case I40E_HASH_FILTER_SIZE_512K:
5242 case I40E_HASH_FILTER_SIZE_1M:
5243 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5244 pe_filt_size <<= (u32)settings->pe_filt_num;
5247 return I40E_ERR_PARAM;
5250 switch (settings->pe_cntx_num) {
5251 case I40E_DMA_CNTX_SIZE_512:
5252 case I40E_DMA_CNTX_SIZE_1K:
5253 case I40E_DMA_CNTX_SIZE_2K:
5254 case I40E_DMA_CNTX_SIZE_4K:
5255 case I40E_DMA_CNTX_SIZE_8K:
5256 case I40E_DMA_CNTX_SIZE_16K:
5257 case I40E_DMA_CNTX_SIZE_32K:
5258 case I40E_DMA_CNTX_SIZE_64K:
5259 case I40E_DMA_CNTX_SIZE_128K:
5260 case I40E_DMA_CNTX_SIZE_256K:
5261 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5262 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5265 return I40E_ERR_PARAM;
5268 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5269 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5270 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5271 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5272 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5273 return I40E_ERR_INVALID_SIZE;
5275 return I40E_SUCCESS;
5279 * i40e_set_filter_control
5280 * @hw: pointer to the hardware structure
5281 * @settings: Filter control settings
5283 * Set the Queue Filters for PE/FCoE and enable filters required
5284 * for a single PF. It is expected that these settings are programmed
5285 * at the driver initialization time.
5287 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5288 struct i40e_filter_control_settings *settings)
5290 enum i40e_status_code ret = I40E_SUCCESS;
5291 u32 hash_lut_size = 0;
5295 return I40E_ERR_PARAM;
5297 /* Validate the input settings */
5298 ret = i40e_validate_filter_settings(hw, settings);
5302 /* Read the PF Queue Filter control register */
5303 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5305 /* Program required PE hash buckets for the PF */
5306 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5307 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5308 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5309 /* Program required PE contexts for the PF */
5310 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5311 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5312 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5314 /* Program required FCoE hash buckets for the PF */
5315 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5316 val |= ((u32)settings->fcoe_filt_num <<
5317 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5318 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5319 /* Program required FCoE DDP contexts for the PF */
5320 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5321 val |= ((u32)settings->fcoe_cntx_num <<
5322 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5323 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5325 /* Program Hash LUT size for the PF */
5326 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5327 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5329 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5330 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5332 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5333 if (settings->enable_fdir)
5334 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5335 if (settings->enable_ethtype)
5336 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5337 if (settings->enable_macvlan)
5338 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5340 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5342 return I40E_SUCCESS;
5346 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5347 * @hw: pointer to the hw struct
5348 * @mac_addr: MAC address to use in the filter
5349 * @ethtype: Ethertype to use in the filter
5350 * @flags: Flags that needs to be applied to the filter
5351 * @vsi_seid: seid of the control VSI
5352 * @queue: VSI queue number to send the packet to
5353 * @is_add: Add control packet filter if True else remove
5354 * @stats: Structure to hold information on control filter counts
5355 * @cmd_details: pointer to command details structure or NULL
5357 * This command will Add or Remove control packet filter for a control VSI.
5358 * In return it will update the total number of perfect filter count in
5361 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5362 u8 *mac_addr, u16 ethtype, u16 flags,
5363 u16 vsi_seid, u16 queue, bool is_add,
5364 struct i40e_control_filter_stats *stats,
5365 struct i40e_asq_cmd_details *cmd_details)
5367 struct i40e_aq_desc desc;
5368 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5369 (struct i40e_aqc_add_remove_control_packet_filter *)
5371 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5372 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5374 enum i40e_status_code status;
5377 return I40E_ERR_PARAM;
5380 i40e_fill_default_direct_cmd_desc(&desc,
5381 i40e_aqc_opc_add_control_packet_filter);
5382 cmd->queue = CPU_TO_LE16(queue);
5384 i40e_fill_default_direct_cmd_desc(&desc,
5385 i40e_aqc_opc_remove_control_packet_filter);
5389 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5390 I40E_NONDMA_TO_NONDMA);
5392 cmd->etype = CPU_TO_LE16(ethtype);
5393 cmd->flags = CPU_TO_LE16(flags);
5394 cmd->seid = CPU_TO_LE16(vsi_seid);
5396 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5398 if (!status && stats) {
5399 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5400 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5401 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5402 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5409 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5410 * @hw: pointer to the hw struct
5411 * @seid: VSI seid to add ethertype filter from
5413 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5414 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5417 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5418 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5419 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5420 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5421 enum i40e_status_code status;
5423 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5424 seid, 0, true, NULL,
5427 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5431 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5432 * @filters: list of cloud filters
5433 * @filter_count: length of list
5435 * There's an issue in the device where the Geneve VNI layout needs
5436 * to be shifted 1 byte over from the VxLAN VNI
5438 STATIC void i40e_fix_up_geneve_vni(
5439 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5442 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5445 for (i = 0; i < filter_count; i++) {
5449 tnl_type = (le16_to_cpu(f[i].flags) &
5450 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5451 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5452 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5453 ti = le32_to_cpu(f[i].tenant_id);
5454 f[i].tenant_id = cpu_to_le32(ti << 8);
5460 * i40e_aq_add_cloud_filters
5461 * @hw: pointer to the hardware structure
5462 * @seid: VSI seid to add cloud filters from
5463 * @filters: Buffer which contains the filters to be added
5464 * @filter_count: number of filters contained in the buffer
5466 * Set the cloud filters for a given VSI. The contents of the
5467 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5468 * in by the caller of the function.
5471 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5473 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5476 struct i40e_aq_desc desc;
5477 struct i40e_aqc_add_remove_cloud_filters *cmd =
5478 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5479 enum i40e_status_code status;
5482 i40e_fill_default_direct_cmd_desc(&desc,
5483 i40e_aqc_opc_add_cloud_filters);
5485 buff_len = filter_count * sizeof(*filters);
5486 desc.datalen = CPU_TO_LE16(buff_len);
5487 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5488 cmd->num_filters = filter_count;
5489 cmd->seid = CPU_TO_LE16(seid);
5491 i40e_fix_up_geneve_vni(filters, filter_count);
5493 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5499 * i40e_aq_remove_cloud_filters
5500 * @hw: pointer to the hardware structure
5501 * @seid: VSI seid to remove cloud filters from
5502 * @filters: Buffer which contains the filters to be removed
5503 * @filter_count: number of filters contained in the buffer
5505 * Remove the cloud filters for a given VSI. The contents of the
5506 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5507 * in by the caller of the function.
5510 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5512 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5515 struct i40e_aq_desc desc;
5516 struct i40e_aqc_add_remove_cloud_filters *cmd =
5517 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5518 enum i40e_status_code status;
5521 i40e_fill_default_direct_cmd_desc(&desc,
5522 i40e_aqc_opc_remove_cloud_filters);
5524 buff_len = filter_count * sizeof(*filters);
5525 desc.datalen = CPU_TO_LE16(buff_len);
5526 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5527 cmd->num_filters = filter_count;
5528 cmd->seid = CPU_TO_LE16(seid);
5530 i40e_fix_up_geneve_vni(filters, filter_count);
5532 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5538 * i40e_aq_alternate_write
5539 * @hw: pointer to the hardware structure
5540 * @reg_addr0: address of first dword to be read
5541 * @reg_val0: value to be written under 'reg_addr0'
5542 * @reg_addr1: address of second dword to be read
5543 * @reg_val1: value to be written under 'reg_addr1'
5545 * Write one or two dwords to alternate structure. Fields are indicated
5546 * by 'reg_addr0' and 'reg_addr1' register numbers.
5549 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5550 u32 reg_addr0, u32 reg_val0,
5551 u32 reg_addr1, u32 reg_val1)
5553 struct i40e_aq_desc desc;
5554 struct i40e_aqc_alternate_write *cmd_resp =
5555 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5556 enum i40e_status_code status;
5558 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5559 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5560 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5561 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5562 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5564 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5570 * i40e_aq_alternate_write_indirect
5571 * @hw: pointer to the hardware structure
5572 * @addr: address of a first register to be modified
5573 * @dw_count: number of alternate structure fields to write
5574 * @buffer: pointer to the command buffer
5576 * Write 'dw_count' dwords from 'buffer' to alternate structure
5577 * starting at 'addr'.
5580 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5581 u32 addr, u32 dw_count, void *buffer)
5583 struct i40e_aq_desc desc;
5584 struct i40e_aqc_alternate_ind_write *cmd_resp =
5585 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5586 enum i40e_status_code status;
5589 return I40E_ERR_PARAM;
5591 /* Indirect command */
5592 i40e_fill_default_direct_cmd_desc(&desc,
5593 i40e_aqc_opc_alternate_write_indirect);
5595 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5596 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5597 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5598 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5600 cmd_resp->address = CPU_TO_LE32(addr);
5601 cmd_resp->length = CPU_TO_LE32(dw_count);
5603 status = i40e_asq_send_command(hw, &desc, buffer,
5604 I40E_LO_DWORD(4*dw_count), NULL);
5610 * i40e_aq_alternate_read
5611 * @hw: pointer to the hardware structure
5612 * @reg_addr0: address of first dword to be read
5613 * @reg_val0: pointer for data read from 'reg_addr0'
5614 * @reg_addr1: address of second dword to be read
5615 * @reg_val1: pointer for data read from 'reg_addr1'
5617 * Read one or two dwords from alternate structure. Fields are indicated
5618 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5619 * is not passed then only register at 'reg_addr0' is read.
5622 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5623 u32 reg_addr0, u32 *reg_val0,
5624 u32 reg_addr1, u32 *reg_val1)
5626 struct i40e_aq_desc desc;
5627 struct i40e_aqc_alternate_write *cmd_resp =
5628 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5629 enum i40e_status_code status;
5631 if (reg_val0 == NULL)
5632 return I40E_ERR_PARAM;
5634 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5635 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5636 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5638 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5640 if (status == I40E_SUCCESS) {
5641 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5643 if (reg_val1 != NULL)
5644 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5651 * i40e_aq_alternate_read_indirect
5652 * @hw: pointer to the hardware structure
5653 * @addr: address of the alternate structure field
5654 * @dw_count: number of alternate structure fields to read
5655 * @buffer: pointer to the command buffer
5657 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5658 * place them in 'buffer'. The buffer should be allocated by caller.
5661 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5662 u32 addr, u32 dw_count, void *buffer)
5664 struct i40e_aq_desc desc;
5665 struct i40e_aqc_alternate_ind_write *cmd_resp =
5666 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5667 enum i40e_status_code status;
5670 return I40E_ERR_PARAM;
5672 /* Indirect command */
5673 i40e_fill_default_direct_cmd_desc(&desc,
5674 i40e_aqc_opc_alternate_read_indirect);
5676 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5677 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5678 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5679 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5681 cmd_resp->address = CPU_TO_LE32(addr);
5682 cmd_resp->length = CPU_TO_LE32(dw_count);
5684 status = i40e_asq_send_command(hw, &desc, buffer,
5685 I40E_LO_DWORD(4*dw_count), NULL);
5691 * i40e_aq_alternate_clear
5692 * @hw: pointer to the HW structure.
5694 * Clear the alternate structures of the port from which the function
5698 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5700 struct i40e_aq_desc desc;
5701 enum i40e_status_code status;
5703 i40e_fill_default_direct_cmd_desc(&desc,
5704 i40e_aqc_opc_alternate_clear_port);
5706 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5712 * i40e_aq_alternate_write_done
5713 * @hw: pointer to the HW structure.
5714 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5715 * @reset_needed: indicates the SW should trigger GLOBAL reset
5717 * Indicates to the FW that alternate structures have been changed.
5720 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5721 u8 bios_mode, bool *reset_needed)
5723 struct i40e_aq_desc desc;
5724 struct i40e_aqc_alternate_write_done *cmd =
5725 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5726 enum i40e_status_code status;
5728 if (reset_needed == NULL)
5729 return I40E_ERR_PARAM;
5731 i40e_fill_default_direct_cmd_desc(&desc,
5732 i40e_aqc_opc_alternate_write_done);
5734 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5736 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5737 if (!status && reset_needed)
5738 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5739 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5745 * i40e_aq_set_oem_mode
5746 * @hw: pointer to the HW structure.
5747 * @oem_mode: the OEM mode to be used
5749 * Sets the device to a specific operating mode. Currently the only supported
5750 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5753 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5756 struct i40e_aq_desc desc;
5757 struct i40e_aqc_alternate_write_done *cmd =
5758 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5759 enum i40e_status_code status;
5761 i40e_fill_default_direct_cmd_desc(&desc,
5762 i40e_aqc_opc_alternate_set_mode);
5764 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5766 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5772 * i40e_aq_resume_port_tx
5773 * @hw: pointer to the hardware structure
5774 * @cmd_details: pointer to command details structure or NULL
5776 * Resume port's Tx traffic
5778 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5779 struct i40e_asq_cmd_details *cmd_details)
5781 struct i40e_aq_desc desc;
5782 enum i40e_status_code status;
5784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5786 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5792 * i40e_set_pci_config_data - store PCI bus info
5793 * @hw: pointer to hardware structure
5794 * @link_status: the link status word from PCI config space
5796 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5798 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5800 hw->bus.type = i40e_bus_type_pci_express;
5802 switch (link_status & I40E_PCI_LINK_WIDTH) {
5803 case I40E_PCI_LINK_WIDTH_1:
5804 hw->bus.width = i40e_bus_width_pcie_x1;
5806 case I40E_PCI_LINK_WIDTH_2:
5807 hw->bus.width = i40e_bus_width_pcie_x2;
5809 case I40E_PCI_LINK_WIDTH_4:
5810 hw->bus.width = i40e_bus_width_pcie_x4;
5812 case I40E_PCI_LINK_WIDTH_8:
5813 hw->bus.width = i40e_bus_width_pcie_x8;
5816 hw->bus.width = i40e_bus_width_unknown;
5820 switch (link_status & I40E_PCI_LINK_SPEED) {
5821 case I40E_PCI_LINK_SPEED_2500:
5822 hw->bus.speed = i40e_bus_speed_2500;
5824 case I40E_PCI_LINK_SPEED_5000:
5825 hw->bus.speed = i40e_bus_speed_5000;
5827 case I40E_PCI_LINK_SPEED_8000:
5828 hw->bus.speed = i40e_bus_speed_8000;
5831 hw->bus.speed = i40e_bus_speed_unknown;
5837 * i40e_aq_debug_dump
5838 * @hw: pointer to the hardware structure
5839 * @cluster_id: specific cluster to dump
5840 * @table_id: table id within cluster
5841 * @start_index: index of line in the block to read
5842 * @buff_size: dump buffer size
5843 * @buff: dump buffer
5844 * @ret_buff_size: actual buffer size returned
5845 * @ret_next_table: next block to read
5846 * @ret_next_index: next index to read
5848 * Dump internal FW/HW data for debug purposes.
5851 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5852 u8 table_id, u32 start_index, u16 buff_size,
5853 void *buff, u16 *ret_buff_size,
5854 u8 *ret_next_table, u32 *ret_next_index,
5855 struct i40e_asq_cmd_details *cmd_details)
5857 struct i40e_aq_desc desc;
5858 struct i40e_aqc_debug_dump_internals *cmd =
5859 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5860 struct i40e_aqc_debug_dump_internals *resp =
5861 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5862 enum i40e_status_code status;
5864 if (buff_size == 0 || !buff)
5865 return I40E_ERR_PARAM;
5867 i40e_fill_default_direct_cmd_desc(&desc,
5868 i40e_aqc_opc_debug_dump_internals);
5869 /* Indirect Command */
5870 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5871 if (buff_size > I40E_AQ_LARGE_BUF)
5872 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5874 cmd->cluster_id = cluster_id;
5875 cmd->table_id = table_id;
5876 cmd->idx = CPU_TO_LE32(start_index);
5878 desc.datalen = CPU_TO_LE16(buff_size);
5880 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5882 if (ret_buff_size != NULL)
5883 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5884 if (ret_next_table != NULL)
5885 *ret_next_table = resp->table_id;
5886 if (ret_next_index != NULL)
5887 *ret_next_index = LE32_TO_CPU(resp->idx);
5894 * i40e_read_bw_from_alt_ram
5895 * @hw: pointer to the hardware structure
5896 * @max_bw: pointer for max_bw read
5897 * @min_bw: pointer for min_bw read
5898 * @min_valid: pointer for bool that is true if min_bw is a valid value
5899 * @max_valid: pointer for bool that is true if max_bw is a valid value
5901 * Read bw from the alternate ram for the given pf
5903 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5904 u32 *max_bw, u32 *min_bw,
5905 bool *min_valid, bool *max_valid)
5907 enum i40e_status_code status;
5908 u32 max_bw_addr, min_bw_addr;
5910 /* Calculate the address of the min/max bw registers */
5911 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5912 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5913 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5914 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5915 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5916 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5918 /* Read the bandwidths from alt ram */
5919 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5920 min_bw_addr, min_bw);
5922 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5927 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5936 * i40e_aq_configure_partition_bw
5937 * @hw: pointer to the hardware structure
5938 * @bw_data: Buffer holding valid pfs and bw limits
5939 * @cmd_details: pointer to command details
5941 * Configure partitions guaranteed/max bw
5943 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5944 struct i40e_aqc_configure_partition_bw_data *bw_data,
5945 struct i40e_asq_cmd_details *cmd_details)
5947 enum i40e_status_code status;
5948 struct i40e_aq_desc desc;
5949 u16 bwd_size = sizeof(*bw_data);
5951 i40e_fill_default_direct_cmd_desc(&desc,
5952 i40e_aqc_opc_configure_partition_bw);
5954 /* Indirect command */
5955 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5956 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5958 if (bwd_size > I40E_AQ_LARGE_BUF)
5959 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5961 desc.datalen = CPU_TO_LE16(bwd_size);
5963 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5969 * i40e_read_phy_register
5970 * @hw: pointer to the HW structure
5971 * @page: registers page number
5972 * @reg: register address in the page
5973 * @phy_adr: PHY address on MDIO interface
5974 * @value: PHY register value
5976 * Reads specified PHY register value
5978 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5979 u8 page, u16 reg, u8 phy_addr,
5982 enum i40e_status_code status = I40E_ERR_TIMEOUT;
5985 u8 port_num = (u8)hw->func_caps.mdio_port_num;
5987 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
5988 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5989 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5990 (I40E_MDIO_OPCODE_ADDRESS) |
5991 (I40E_MDIO_STCODE) |
5992 (I40E_GLGEN_MSCA_MDICMD_MASK) |
5993 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
5994 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
5996 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
5997 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
5998 status = I40E_SUCCESS;
6001 i40e_usec_delay(10);
6006 i40e_debug(hw, I40E_DEBUG_PHY,
6007 "PHY: Can't write command to external PHY.\n");
6011 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6012 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6013 (I40E_MDIO_OPCODE_READ) |
6014 (I40E_MDIO_STCODE) |
6015 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6016 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6017 status = I40E_ERR_TIMEOUT;
6019 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6021 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6022 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6023 status = I40E_SUCCESS;
6026 i40e_usec_delay(10);
6031 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6032 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6033 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6035 i40e_debug(hw, I40E_DEBUG_PHY,
6036 "PHY: Can't read register value from external PHY.\n");
6044 * i40e_write_phy_register
6045 * @hw: pointer to the HW structure
6046 * @page: registers page number
6047 * @reg: register address in the page
6048 * @phy_adr: PHY address on MDIO interface
6049 * @value: PHY register value
6051 * Writes value to specified PHY register
6053 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6054 u8 page, u16 reg, u8 phy_addr,
6057 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6060 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6062 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6063 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6064 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6065 (I40E_MDIO_OPCODE_ADDRESS) |
6066 (I40E_MDIO_STCODE) |
6067 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6068 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6069 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6071 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6072 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6073 status = I40E_SUCCESS;
6076 i40e_usec_delay(10);
6080 i40e_debug(hw, I40E_DEBUG_PHY,
6081 "PHY: Can't write command to external PHY.\n");
6085 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6086 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6088 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6089 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6090 (I40E_MDIO_OPCODE_WRITE) |
6091 (I40E_MDIO_STCODE) |
6092 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6093 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6094 status = I40E_ERR_TIMEOUT;
6096 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6098 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6099 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6100 status = I40E_SUCCESS;
6103 i40e_usec_delay(10);
6112 * i40e_get_phy_address
6113 * @hw: pointer to the HW structure
6114 * @dev_num: PHY port num that address we want
6115 * @phy_addr: Returned PHY address
6117 * Gets PHY address for current port
6119 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6121 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6122 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6124 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6128 * i40e_blink_phy_led
6129 * @hw: pointer to the HW structure
6130 * @time: time how long led will blinks in secs
6131 * @interval: gap between LED on and off in msecs
6133 * Blinks PHY link LED
6135 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6136 u32 time, u32 interval)
6138 enum i40e_status_code status = I40E_SUCCESS;
6143 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6147 i = rd32(hw, I40E_PFGEN_PORTNUM);
6148 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6149 phy_addr = i40e_get_phy_address(hw, port_num);
6151 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6153 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6154 led_addr, phy_addr, &led_reg);
6156 goto phy_blinking_end;
6158 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6160 status = i40e_write_phy_register(hw,
6161 I40E_PHY_COM_REG_PAGE,
6165 goto phy_blinking_end;
6170 if (time > 0 && interval > 0) {
6171 for (i = 0; i < time * 1000; i += interval) {
6172 status = i40e_read_phy_register(hw,
6173 I40E_PHY_COM_REG_PAGE,
6177 goto restore_config;
6178 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6181 led_reg = I40E_PHY_LED_MANUAL_ON;
6182 status = i40e_write_phy_register(hw,
6183 I40E_PHY_COM_REG_PAGE,
6187 goto restore_config;
6188 i40e_msec_delay(interval);
6193 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6201 * i40e_led_get_phy - return current on/off mode
6202 * @hw: pointer to the hw struct
6203 * @led_addr: address of led register to use
6204 * @val: original value of register to use
6207 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6210 enum i40e_status_code status = I40E_SUCCESS;
6218 temp_addr = I40E_PHY_LED_PROV_REG_1;
6219 i = rd32(hw, I40E_PFGEN_PORTNUM);
6220 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6221 phy_addr = i40e_get_phy_address(hw, port_num);
6223 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6225 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6226 temp_addr, phy_addr, ®_val);
6230 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6231 *led_addr = temp_addr;
6240 * @hw: pointer to the HW structure
6241 * @on: true or false
6242 * @mode: original val plus bit for set or ignore
6243 * Set led's on or off when controlled by the PHY
6246 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6247 u16 led_addr, u32 mode)
6249 enum i40e_status_code status = I40E_SUCCESS;
6256 i = rd32(hw, I40E_PFGEN_PORTNUM);
6257 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6258 phy_addr = i40e_get_phy_address(hw, port_num);
6260 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6261 phy_addr, &led_reg);
6265 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6267 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6268 led_addr, phy_addr, led_reg);
6272 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6273 led_addr, phy_addr, &led_reg);
6275 goto restore_config;
6277 led_reg = I40E_PHY_LED_MANUAL_ON;
6280 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6281 led_addr, phy_addr, led_reg);
6283 goto restore_config;
6284 if (mode & I40E_PHY_LED_MODE_ORIG) {
6285 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6286 status = i40e_write_phy_register(hw,
6287 I40E_PHY_COM_REG_PAGE,
6288 led_addr, phy_addr, led_ctl);
6292 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6296 #endif /* PF_DRIVER */
6299 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6300 * @hw: pointer to the hw struct
6301 * @reg_addr: register address
6302 * @reg_val: ptr to register value
6303 * @cmd_details: pointer to command details structure or NULL
6305 * Use the firmware to read the Rx control register,
6306 * especially useful if the Rx unit is under heavy pressure
6308 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6309 u32 reg_addr, u32 *reg_val,
6310 struct i40e_asq_cmd_details *cmd_details)
6312 struct i40e_aq_desc desc;
6313 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6314 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6315 enum i40e_status_code status;
6317 if (reg_val == NULL)
6318 return I40E_ERR_PARAM;
6320 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6322 cmd_resp->address = CPU_TO_LE32(reg_addr);
6324 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6326 if (status == I40E_SUCCESS)
6327 *reg_val = LE32_TO_CPU(cmd_resp->value);
6333 * i40e_read_rx_ctl - read from an Rx control register
6334 * @hw: pointer to the hw struct
6335 * @reg_addr: register address
6337 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6339 enum i40e_status_code status = I40E_SUCCESS;
6344 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6345 if (!use_register) {
6347 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6348 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6355 /* if the AQ access failed, try the old-fashioned way */
6356 if (status || use_register)
6357 val = rd32(hw, reg_addr);
6363 * i40e_aq_rx_ctl_write_register
6364 * @hw: pointer to the hw struct
6365 * @reg_addr: register address
6366 * @reg_val: register value
6367 * @cmd_details: pointer to command details structure or NULL
6369 * Use the firmware to write to an Rx control register,
6370 * especially useful if the Rx unit is under heavy pressure
6372 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6373 u32 reg_addr, u32 reg_val,
6374 struct i40e_asq_cmd_details *cmd_details)
6376 struct i40e_aq_desc desc;
6377 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6378 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6379 enum i40e_status_code status;
6381 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6383 cmd->address = CPU_TO_LE32(reg_addr);
6384 cmd->value = CPU_TO_LE32(reg_val);
6386 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6392 * i40e_write_rx_ctl - write to an Rx control register
6393 * @hw: pointer to the hw struct
6394 * @reg_addr: register address
6395 * @reg_val: register value
6397 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6399 enum i40e_status_code status = I40E_SUCCESS;
6403 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6404 if (!use_register) {
6406 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6408 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6415 /* if the AQ access failed, try the old-fashioned way */
6416 if (status || use_register)
6417 wr32(hw, reg_addr, reg_val);
6422 * i40e_aq_send_msg_to_pf
6423 * @hw: pointer to the hardware structure
6424 * @v_opcode: opcodes for VF-PF communication
6425 * @v_retval: return error code
6426 * @msg: pointer to the msg buffer
6427 * @msglen: msg length
6428 * @cmd_details: pointer to command details
6430 * Send message to PF driver using admin queue. By default, this message
6431 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6432 * completion before returning.
6434 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6435 enum i40e_virtchnl_ops v_opcode,
6436 enum i40e_status_code v_retval,
6437 u8 *msg, u16 msglen,
6438 struct i40e_asq_cmd_details *cmd_details)
6440 struct i40e_aq_desc desc;
6441 struct i40e_asq_cmd_details details;
6442 enum i40e_status_code status;
6444 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6446 desc.cookie_high = CPU_TO_LE32(v_opcode);
6447 desc.cookie_low = CPU_TO_LE32(v_retval);
6449 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6450 | I40E_AQ_FLAG_RD));
6451 if (msglen > I40E_AQ_LARGE_BUF)
6452 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6453 desc.datalen = CPU_TO_LE16(msglen);
6456 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6457 details.async = true;
6458 cmd_details = &details;
6460 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6461 msglen, cmd_details);
6466 * i40e_vf_parse_hw_config
6467 * @hw: pointer to the hardware structure
6468 * @msg: pointer to the virtual channel VF resource structure
6470 * Given a VF resource message from the PF, populate the hw struct
6471 * with appropriate information.
6473 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6474 struct i40e_virtchnl_vf_resource *msg)
6476 struct i40e_virtchnl_vsi_resource *vsi_res;
6479 vsi_res = &msg->vsi_res[0];
6481 hw->dev_caps.num_vsis = msg->num_vsis;
6482 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6483 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6484 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6485 hw->dev_caps.dcb = msg->vf_offload_flags &
6486 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6487 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6488 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6489 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6490 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6491 for (i = 0; i < msg->num_vsis; i++) {
6492 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6493 i40e_memcpy(hw->mac.perm_addr,
6494 vsi_res->default_mac_addr,
6495 I40E_ETH_LENGTH_OF_ADDRESS,
6496 I40E_NONDMA_TO_NONDMA);
6497 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6498 I40E_ETH_LENGTH_OF_ADDRESS,
6499 I40E_NONDMA_TO_NONDMA);
6507 * @hw: pointer to the hardware structure
6509 * Send a VF_RESET message to the PF. Does not wait for response from PF
6510 * as none will be forthcoming. Immediately after calling this function,
6511 * the admin queue should be shut down and (optionally) reinitialized.
6513 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6515 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6516 I40E_SUCCESS, NULL, 0, NULL);
6518 #endif /* VF_DRIVER */
6522 * i40e_aq_set_arp_proxy_config
6523 * @hw: pointer to the HW structure
6524 * @proxy_config - pointer to proxy config command table struct
6525 * @cmd_details: pointer to command details
6527 * Set ARP offload parameters from pre-populated
6528 * i40e_aqc_arp_proxy_data struct
6530 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6531 struct i40e_aqc_arp_proxy_data *proxy_config,
6532 struct i40e_asq_cmd_details *cmd_details)
6534 struct i40e_aq_desc desc;
6535 enum i40e_status_code status;
6538 return I40E_ERR_PARAM;
6540 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6542 desc.params.external.addr_high =
6543 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6544 desc.params.external.addr_low =
6545 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6547 status = i40e_asq_send_command(hw, &desc, proxy_config,
6548 sizeof(struct i40e_aqc_arp_proxy_data),
6555 * i40e_aq_opc_set_ns_proxy_table_entry
6556 * @hw: pointer to the HW structure
6557 * @ns_proxy_table_entry: pointer to NS table entry command struct
6558 * @cmd_details: pointer to command details
6560 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6561 * from pre-populated i40e_aqc_ns_proxy_data struct
6563 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6564 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6565 struct i40e_asq_cmd_details *cmd_details)
6567 struct i40e_aq_desc desc;
6568 enum i40e_status_code status;
6570 if (!ns_proxy_table_entry)
6571 return I40E_ERR_PARAM;
6573 i40e_fill_default_direct_cmd_desc(&desc,
6574 i40e_aqc_opc_set_ns_proxy_table_entry);
6576 desc.params.external.addr_high =
6577 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6578 desc.params.external.addr_low =
6579 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6581 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6582 sizeof(struct i40e_aqc_ns_proxy_data),
6589 * i40e_aq_set_clear_wol_filter
6590 * @hw: pointer to the hw struct
6591 * @filter_index: index of filter to modify (0-7)
6592 * @filter: buffer containing filter to be set
6593 * @set_filter: true to set filter, false to clear filter
6594 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6595 * if false, pass through packets may cause wake-up
6596 * @filter_valid: true if filter action is valid
6597 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6598 * @cmd_details: pointer to command details structure or NULL
6600 * Set or clear WoL filter for port attached to the PF
6602 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6604 struct i40e_aqc_set_wol_filter_data *filter,
6605 bool set_filter, bool no_wol_tco,
6606 bool filter_valid, bool no_wol_tco_valid,
6607 struct i40e_asq_cmd_details *cmd_details)
6609 struct i40e_aq_desc desc;
6610 struct i40e_aqc_set_wol_filter *cmd =
6611 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6612 enum i40e_status_code status;
6614 u16 valid_flags = 0;
6617 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6619 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6620 return I40E_ERR_PARAM;
6621 cmd->filter_index = CPU_TO_LE16(filter_index);
6625 return I40E_ERR_PARAM;
6626 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6627 buff_len = sizeof(*filter);
6630 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6631 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6634 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6635 if (no_wol_tco_valid)
6636 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6637 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6639 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6640 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6642 status = i40e_asq_send_command(hw, &desc, filter,
6643 buff_len, cmd_details);
6649 * i40e_aq_get_wake_event_reason
6650 * @hw: pointer to the hw struct
6651 * @wake_reason: return value, index of matching filter
6652 * @cmd_details: pointer to command details structure or NULL
6654 * Get information for the reason of a Wake Up event
6656 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6658 struct i40e_asq_cmd_details *cmd_details)
6660 struct i40e_aq_desc desc;
6661 struct i40e_aqc_get_wake_reason_completion *resp =
6662 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6663 enum i40e_status_code status;
6665 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6669 if (status == I40E_SUCCESS)
6670 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6675 #endif /* X722_SUPPORT */