1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
352 memset(d_buf, 0, sizeof(d_buf));
353 for (j = 0; i < len; j++, i++)
356 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
357 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
358 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
359 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
360 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 * i40e_check_asq_alive
367 * @hw: pointer to the hw struct
369 * Returns true if Queue is enabled else false.
371 bool i40e_check_asq_alive(struct i40e_hw *hw)
374 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
380 * i40e_aq_queue_shutdown
381 * @hw: pointer to the hw struct
382 * @unloading: is the driver unloading itself
384 * Tell the Firmware that we're shutting down the AdminQ and whether
385 * or not the driver is unloading as well.
387 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
390 struct i40e_aq_desc desc;
391 struct i40e_aqc_queue_shutdown *cmd =
392 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
393 enum i40e_status_code status;
395 i40e_fill_default_direct_cmd_desc(&desc,
396 i40e_aqc_opc_queue_shutdown);
399 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
400 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
405 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
406 * hardware to a bit-field that can be used by SW to more easily determine the
409 * Macros are used to shorten the table lines and make this table human
412 * We store the PTYPE in the top byte of the bit field - this is just so that
413 * we can check that the table doesn't have a row missing, as the index into
414 * the table should be the PTYPE.
418 * IF NOT i40e_ptype_lookup[ptype].known
421 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
422 * Use the rest of the fields to look at the tunnels, inner protocols, etc
424 * Use the enum i40e_rx_l2_ptype to decode the packet type
428 /* macro to make the table lines short */
429 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
432 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
433 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
434 I40E_RX_PTYPE_##OUTER_FRAG, \
435 I40E_RX_PTYPE_TUNNEL_##T, \
436 I40E_RX_PTYPE_TUNNEL_END_##TE, \
437 I40E_RX_PTYPE_##TEF, \
438 I40E_RX_PTYPE_INNER_PROT_##I, \
439 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
441 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
442 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
444 /* shorter macros makes the table fit but are terse */
445 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
446 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
447 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
449 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
450 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
451 /* L2 Packet types */
452 I40E_PTT_UNUSED_ENTRY(0),
453 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
454 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
455 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
456 I40E_PTT_UNUSED_ENTRY(4),
457 I40E_PTT_UNUSED_ENTRY(5),
458 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
459 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
460 I40E_PTT_UNUSED_ENTRY(8),
461 I40E_PTT_UNUSED_ENTRY(9),
462 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
463 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
464 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
465 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
466 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
467 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
468 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
469 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
470 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
471 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
472 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
473 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
475 /* Non Tunneled IPv4 */
476 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
477 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
478 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
479 I40E_PTT_UNUSED_ENTRY(25),
480 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
481 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
482 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
485 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
486 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
487 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
488 I40E_PTT_UNUSED_ENTRY(32),
489 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
490 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
491 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
494 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
495 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
496 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
497 I40E_PTT_UNUSED_ENTRY(39),
498 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
499 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
500 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
502 /* IPv4 --> GRE/NAT */
503 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
505 /* IPv4 --> GRE/NAT --> IPv4 */
506 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
507 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
508 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
509 I40E_PTT_UNUSED_ENTRY(47),
510 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
511 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
512 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
514 /* IPv4 --> GRE/NAT --> IPv6 */
515 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
516 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
517 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
518 I40E_PTT_UNUSED_ENTRY(54),
519 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
520 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
521 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
523 /* IPv4 --> GRE/NAT --> MAC */
524 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
526 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
527 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
528 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
529 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
530 I40E_PTT_UNUSED_ENTRY(62),
531 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
532 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
533 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
535 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
536 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
537 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
538 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
539 I40E_PTT_UNUSED_ENTRY(69),
540 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
541 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
542 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
544 /* IPv4 --> GRE/NAT --> MAC/VLAN */
545 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
547 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
548 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
549 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
550 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
551 I40E_PTT_UNUSED_ENTRY(77),
552 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
553 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
554 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
556 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
557 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
558 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
559 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
560 I40E_PTT_UNUSED_ENTRY(84),
561 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
562 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
563 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
565 /* Non Tunneled IPv6 */
566 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
567 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
568 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
569 I40E_PTT_UNUSED_ENTRY(91),
570 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
571 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
572 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
575 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
576 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
577 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
578 I40E_PTT_UNUSED_ENTRY(98),
579 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
580 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
581 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
584 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
585 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
586 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
587 I40E_PTT_UNUSED_ENTRY(105),
588 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
589 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
590 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
592 /* IPv6 --> GRE/NAT */
593 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
595 /* IPv6 --> GRE/NAT -> IPv4 */
596 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
597 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
598 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
599 I40E_PTT_UNUSED_ENTRY(113),
600 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
601 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
602 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
604 /* IPv6 --> GRE/NAT -> IPv6 */
605 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
606 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
607 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(120),
609 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
610 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
611 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
613 /* IPv6 --> GRE/NAT -> MAC */
614 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
616 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
617 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
618 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
619 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
620 I40E_PTT_UNUSED_ENTRY(128),
621 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
622 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
623 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
625 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
626 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
627 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
628 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
629 I40E_PTT_UNUSED_ENTRY(135),
630 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
631 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
632 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
634 /* IPv6 --> GRE/NAT -> MAC/VLAN */
635 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
637 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
638 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
639 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
640 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
641 I40E_PTT_UNUSED_ENTRY(143),
642 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
643 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
644 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
646 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
647 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
648 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
649 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
650 I40E_PTT_UNUSED_ENTRY(150),
651 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
652 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
653 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(154),
657 I40E_PTT_UNUSED_ENTRY(155),
658 I40E_PTT_UNUSED_ENTRY(156),
659 I40E_PTT_UNUSED_ENTRY(157),
660 I40E_PTT_UNUSED_ENTRY(158),
661 I40E_PTT_UNUSED_ENTRY(159),
663 I40E_PTT_UNUSED_ENTRY(160),
664 I40E_PTT_UNUSED_ENTRY(161),
665 I40E_PTT_UNUSED_ENTRY(162),
666 I40E_PTT_UNUSED_ENTRY(163),
667 I40E_PTT_UNUSED_ENTRY(164),
668 I40E_PTT_UNUSED_ENTRY(165),
669 I40E_PTT_UNUSED_ENTRY(166),
670 I40E_PTT_UNUSED_ENTRY(167),
671 I40E_PTT_UNUSED_ENTRY(168),
672 I40E_PTT_UNUSED_ENTRY(169),
674 I40E_PTT_UNUSED_ENTRY(170),
675 I40E_PTT_UNUSED_ENTRY(171),
676 I40E_PTT_UNUSED_ENTRY(172),
677 I40E_PTT_UNUSED_ENTRY(173),
678 I40E_PTT_UNUSED_ENTRY(174),
679 I40E_PTT_UNUSED_ENTRY(175),
680 I40E_PTT_UNUSED_ENTRY(176),
681 I40E_PTT_UNUSED_ENTRY(177),
682 I40E_PTT_UNUSED_ENTRY(178),
683 I40E_PTT_UNUSED_ENTRY(179),
685 I40E_PTT_UNUSED_ENTRY(180),
686 I40E_PTT_UNUSED_ENTRY(181),
687 I40E_PTT_UNUSED_ENTRY(182),
688 I40E_PTT_UNUSED_ENTRY(183),
689 I40E_PTT_UNUSED_ENTRY(184),
690 I40E_PTT_UNUSED_ENTRY(185),
691 I40E_PTT_UNUSED_ENTRY(186),
692 I40E_PTT_UNUSED_ENTRY(187),
693 I40E_PTT_UNUSED_ENTRY(188),
694 I40E_PTT_UNUSED_ENTRY(189),
696 I40E_PTT_UNUSED_ENTRY(190),
697 I40E_PTT_UNUSED_ENTRY(191),
698 I40E_PTT_UNUSED_ENTRY(192),
699 I40E_PTT_UNUSED_ENTRY(193),
700 I40E_PTT_UNUSED_ENTRY(194),
701 I40E_PTT_UNUSED_ENTRY(195),
702 I40E_PTT_UNUSED_ENTRY(196),
703 I40E_PTT_UNUSED_ENTRY(197),
704 I40E_PTT_UNUSED_ENTRY(198),
705 I40E_PTT_UNUSED_ENTRY(199),
707 I40E_PTT_UNUSED_ENTRY(200),
708 I40E_PTT_UNUSED_ENTRY(201),
709 I40E_PTT_UNUSED_ENTRY(202),
710 I40E_PTT_UNUSED_ENTRY(203),
711 I40E_PTT_UNUSED_ENTRY(204),
712 I40E_PTT_UNUSED_ENTRY(205),
713 I40E_PTT_UNUSED_ENTRY(206),
714 I40E_PTT_UNUSED_ENTRY(207),
715 I40E_PTT_UNUSED_ENTRY(208),
716 I40E_PTT_UNUSED_ENTRY(209),
718 I40E_PTT_UNUSED_ENTRY(210),
719 I40E_PTT_UNUSED_ENTRY(211),
720 I40E_PTT_UNUSED_ENTRY(212),
721 I40E_PTT_UNUSED_ENTRY(213),
722 I40E_PTT_UNUSED_ENTRY(214),
723 I40E_PTT_UNUSED_ENTRY(215),
724 I40E_PTT_UNUSED_ENTRY(216),
725 I40E_PTT_UNUSED_ENTRY(217),
726 I40E_PTT_UNUSED_ENTRY(218),
727 I40E_PTT_UNUSED_ENTRY(219),
729 I40E_PTT_UNUSED_ENTRY(220),
730 I40E_PTT_UNUSED_ENTRY(221),
731 I40E_PTT_UNUSED_ENTRY(222),
732 I40E_PTT_UNUSED_ENTRY(223),
733 I40E_PTT_UNUSED_ENTRY(224),
734 I40E_PTT_UNUSED_ENTRY(225),
735 I40E_PTT_UNUSED_ENTRY(226),
736 I40E_PTT_UNUSED_ENTRY(227),
737 I40E_PTT_UNUSED_ENTRY(228),
738 I40E_PTT_UNUSED_ENTRY(229),
740 I40E_PTT_UNUSED_ENTRY(230),
741 I40E_PTT_UNUSED_ENTRY(231),
742 I40E_PTT_UNUSED_ENTRY(232),
743 I40E_PTT_UNUSED_ENTRY(233),
744 I40E_PTT_UNUSED_ENTRY(234),
745 I40E_PTT_UNUSED_ENTRY(235),
746 I40E_PTT_UNUSED_ENTRY(236),
747 I40E_PTT_UNUSED_ENTRY(237),
748 I40E_PTT_UNUSED_ENTRY(238),
749 I40E_PTT_UNUSED_ENTRY(239),
751 I40E_PTT_UNUSED_ENTRY(240),
752 I40E_PTT_UNUSED_ENTRY(241),
753 I40E_PTT_UNUSED_ENTRY(242),
754 I40E_PTT_UNUSED_ENTRY(243),
755 I40E_PTT_UNUSED_ENTRY(244),
756 I40E_PTT_UNUSED_ENTRY(245),
757 I40E_PTT_UNUSED_ENTRY(246),
758 I40E_PTT_UNUSED_ENTRY(247),
759 I40E_PTT_UNUSED_ENTRY(248),
760 I40E_PTT_UNUSED_ENTRY(249),
762 I40E_PTT_UNUSED_ENTRY(250),
763 I40E_PTT_UNUSED_ENTRY(251),
764 I40E_PTT_UNUSED_ENTRY(252),
765 I40E_PTT_UNUSED_ENTRY(253),
766 I40E_PTT_UNUSED_ENTRY(254),
767 I40E_PTT_UNUSED_ENTRY(255)
772 * i40e_validate_mac_addr - Validate unicast MAC address
773 * @mac_addr: pointer to MAC address
775 * Tests a MAC address to ensure it is a valid Individual Address
777 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
779 enum i40e_status_code status = I40E_SUCCESS;
781 DEBUGFUNC("i40e_validate_mac_addr");
783 /* Broadcast addresses ARE multicast addresses
784 * Make sure it is not a multicast address
785 * Reject the zero address
787 if (I40E_IS_MULTICAST(mac_addr) ||
788 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
789 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
790 status = I40E_ERR_INVALID_MAC_ADDR;
797 * i40e_init_shared_code - Initialize the shared code
798 * @hw: pointer to hardware structure
800 * This assigns the MAC type and PHY code and inits the NVM.
801 * Does not touch the hardware. This function must be called prior to any
802 * other function in the shared code. The i40e_hw structure should be
803 * memset to 0 prior to calling this function. The following fields in
804 * hw structure should be filled in prior to calling this function:
805 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
806 * subsystem_vendor_id, and revision_id
808 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
810 enum i40e_status_code status = I40E_SUCCESS;
811 u32 port, ari, func_rid;
813 DEBUGFUNC("i40e_init_shared_code");
815 i40e_set_mac_type(hw);
817 switch (hw->mac.type) {
821 return I40E_ERR_DEVICE_NOT_SUPPORTED;
824 hw->phy.get_link_info = true;
826 /* Determine port number and PF number*/
827 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
828 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
830 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
831 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
832 func_rid = rd32(hw, I40E_PF_FUNC_RID);
834 hw->pf_id = (u8)(func_rid & 0xff);
836 hw->pf_id = (u8)(func_rid & 0x7);
838 status = i40e_init_nvm(hw);
843 * i40e_aq_mac_address_read - Retrieve the MAC addresses
844 * @hw: pointer to the hw struct
845 * @flags: a return indicator of what addresses were added to the addr store
846 * @addrs: the requestor's mac addr store
847 * @cmd_details: pointer to command details structure or NULL
849 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
851 struct i40e_aqc_mac_address_read_data *addrs,
852 struct i40e_asq_cmd_details *cmd_details)
854 struct i40e_aq_desc desc;
855 struct i40e_aqc_mac_address_read *cmd_data =
856 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
857 enum i40e_status_code status;
859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
860 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
862 status = i40e_asq_send_command(hw, &desc, addrs,
863 sizeof(*addrs), cmd_details);
864 *flags = LE16_TO_CPU(cmd_data->command_flags);
870 * i40e_aq_mac_address_write - Change the MAC addresses
871 * @hw: pointer to the hw struct
872 * @flags: indicates which MAC to be written
873 * @mac_addr: address to write
874 * @cmd_details: pointer to command details structure or NULL
876 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
877 u16 flags, u8 *mac_addr,
878 struct i40e_asq_cmd_details *cmd_details)
880 struct i40e_aq_desc desc;
881 struct i40e_aqc_mac_address_write *cmd_data =
882 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
883 enum i40e_status_code status;
885 i40e_fill_default_direct_cmd_desc(&desc,
886 i40e_aqc_opc_mac_address_write);
887 cmd_data->command_flags = CPU_TO_LE16(flags);
888 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
889 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
890 ((u32)mac_addr[3] << 16) |
891 ((u32)mac_addr[4] << 8) |
894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
900 * i40e_get_mac_addr - get MAC address
901 * @hw: pointer to the HW structure
902 * @mac_addr: pointer to MAC address
904 * Reads the adapter's MAC address from register
906 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
908 struct i40e_aqc_mac_address_read_data addrs;
909 enum i40e_status_code status;
912 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
914 if (flags & I40E_AQC_LAN_ADDR_VALID)
915 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
921 * i40e_get_port_mac_addr - get Port MAC address
922 * @hw: pointer to the HW structure
923 * @mac_addr: pointer to Port MAC address
925 * Reads the adapter's Port MAC address
927 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
929 struct i40e_aqc_mac_address_read_data addrs;
930 enum i40e_status_code status;
933 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
937 if (flags & I40E_AQC_PORT_ADDR_VALID)
938 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
940 status = I40E_ERR_INVALID_MAC_ADDR;
946 * i40e_pre_tx_queue_cfg - pre tx queue configure
947 * @hw: pointer to the HW structure
948 * @queue: target pf queue index
949 * @enable: state change request
951 * Handles hw requirement to indicate intention to enable
952 * or disable target queue.
954 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
956 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
960 if (abs_queue_idx >= 128) {
961 reg_block = abs_queue_idx / 128;
962 abs_queue_idx %= 128;
965 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
966 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
967 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
970 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
972 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
974 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
978 * i40e_read_pba_string - Reads part number string from EEPROM
979 * @hw: pointer to hardware structure
980 * @pba_num: stores the part number string from the EEPROM
981 * @pba_num_size: part number string buffer length
983 * Reads the part number string from the EEPROM.
985 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
988 enum i40e_status_code status = I40E_SUCCESS;
994 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
995 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
996 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1000 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1001 if (status != I40E_SUCCESS) {
1002 DEBUGOUT("Failed to read PBA Block pointer.\n");
1006 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1007 if (status != I40E_SUCCESS) {
1008 DEBUGOUT("Failed to read PBA Block size.\n");
1012 /* Subtract one to get PBA word count (PBA Size word is included in
1016 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1017 DEBUGOUT("Buffer to small for PBA data.\n");
1018 return I40E_ERR_PARAM;
1021 for (i = 0; i < pba_size; i++) {
1022 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1023 if (status != I40E_SUCCESS) {
1024 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1028 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1029 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1031 pba_num[(pba_size * 2)] = '\0';
1037 * i40e_get_media_type - Gets media type
1038 * @hw: pointer to the hardware structure
1040 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1042 enum i40e_media_type media;
1044 switch (hw->phy.link_info.phy_type) {
1045 case I40E_PHY_TYPE_10GBASE_SR:
1046 case I40E_PHY_TYPE_10GBASE_LR:
1047 case I40E_PHY_TYPE_1000BASE_SX:
1048 case I40E_PHY_TYPE_1000BASE_LX:
1049 case I40E_PHY_TYPE_40GBASE_SR4:
1050 case I40E_PHY_TYPE_40GBASE_LR4:
1051 media = I40E_MEDIA_TYPE_FIBER;
1053 case I40E_PHY_TYPE_100BASE_TX:
1054 case I40E_PHY_TYPE_1000BASE_T:
1055 case I40E_PHY_TYPE_10GBASE_T:
1056 media = I40E_MEDIA_TYPE_BASET;
1058 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1059 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1060 case I40E_PHY_TYPE_10GBASE_CR1:
1061 case I40E_PHY_TYPE_40GBASE_CR4:
1062 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1063 case I40E_PHY_TYPE_40GBASE_AOC:
1064 case I40E_PHY_TYPE_10GBASE_AOC:
1065 media = I40E_MEDIA_TYPE_DA;
1067 case I40E_PHY_TYPE_1000BASE_KX:
1068 case I40E_PHY_TYPE_10GBASE_KX4:
1069 case I40E_PHY_TYPE_10GBASE_KR:
1070 case I40E_PHY_TYPE_40GBASE_KR4:
1071 case I40E_PHY_TYPE_20GBASE_KR2:
1072 media = I40E_MEDIA_TYPE_BACKPLANE;
1074 case I40E_PHY_TYPE_SGMII:
1075 case I40E_PHY_TYPE_XAUI:
1076 case I40E_PHY_TYPE_XFI:
1077 case I40E_PHY_TYPE_XLAUI:
1078 case I40E_PHY_TYPE_XLPPI:
1080 media = I40E_MEDIA_TYPE_UNKNOWN;
1087 #define I40E_PF_RESET_WAIT_COUNT 110
1089 * i40e_pf_reset - Reset the PF
1090 * @hw: pointer to the hardware structure
1092 * Assuming someone else has triggered a global reset,
1093 * assure the global reset is complete and then reset the PF
1095 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1102 /* Poll for Global Reset steady state in case of recent GRST.
1103 * The grst delay value is in 100ms units, and we'll wait a
1104 * couple counts longer to be sure we don't just miss the end.
1106 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1107 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1108 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1109 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1110 reg = rd32(hw, I40E_GLGEN_RSTAT);
1111 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1113 i40e_msec_delay(100);
1115 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1116 DEBUGOUT("Global reset polling failed to complete.\n");
1117 return I40E_ERR_RESET_FAILED;
1120 /* Now Wait for the FW to be ready */
1121 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1122 reg = rd32(hw, I40E_GLNVM_ULD);
1123 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1124 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1125 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1126 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1127 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1130 i40e_msec_delay(10);
1132 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1133 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1134 DEBUGOUT("wait for FW Reset complete timedout\n");
1135 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1136 return I40E_ERR_RESET_FAILED;
1139 /* If there was a Global Reset in progress when we got here,
1140 * we don't need to do the PF Reset
1143 reg = rd32(hw, I40E_PFGEN_CTRL);
1144 wr32(hw, I40E_PFGEN_CTRL,
1145 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1146 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1147 reg = rd32(hw, I40E_PFGEN_CTRL);
1148 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1152 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1153 DEBUGOUT("PF reset polling failed to complete.\n");
1154 return I40E_ERR_RESET_FAILED;
1158 i40e_clear_pxe_mode(hw);
1161 return I40E_SUCCESS;
1165 * i40e_clear_hw - clear out any left over hw state
1166 * @hw: pointer to the hw struct
1168 * Clear queues and interrupts, typically called at init time,
1169 * but after the capabilities have been found so we know how many
1170 * queues and msix vectors have been allocated.
1172 void i40e_clear_hw(struct i40e_hw *hw)
1174 u32 num_queues, base_queue;
1182 /* get number of interrupts, queues, and vfs */
1183 val = rd32(hw, I40E_GLPCI_CNF2);
1184 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1185 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1186 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1187 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1189 val = rd32(hw, I40E_PFLAN_QALLOC);
1190 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1191 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1192 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1193 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1194 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1195 num_queues = (j - base_queue) + 1;
1199 val = rd32(hw, I40E_PF_VT_PFALLOC);
1200 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1201 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1202 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1203 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1204 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1205 num_vfs = (j - i) + 1;
1209 /* stop all the interrupts */
1210 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1211 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1212 for (i = 0; i < num_pf_int - 2; i++)
1213 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1215 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1216 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1217 wr32(hw, I40E_PFINT_LNKLST0, val);
1218 for (i = 0; i < num_pf_int - 2; i++)
1219 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1220 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1221 for (i = 0; i < num_vfs; i++)
1222 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1223 for (i = 0; i < num_vf_int - 2; i++)
1224 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1226 /* warn the HW of the coming Tx disables */
1227 for (i = 0; i < num_queues; i++) {
1228 u32 abs_queue_idx = base_queue + i;
1231 if (abs_queue_idx >= 128) {
1232 reg_block = abs_queue_idx / 128;
1233 abs_queue_idx %= 128;
1236 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1237 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1238 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1239 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1241 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1243 i40e_usec_delay(400);
1245 /* stop all the queues */
1246 for (i = 0; i < num_queues; i++) {
1247 wr32(hw, I40E_QINT_TQCTL(i), 0);
1248 wr32(hw, I40E_QTX_ENA(i), 0);
1249 wr32(hw, I40E_QINT_RQCTL(i), 0);
1250 wr32(hw, I40E_QRX_ENA(i), 0);
1253 /* short wait for all queue disables to settle */
1254 i40e_usec_delay(50);
1258 * i40e_clear_pxe_mode - clear pxe operations mode
1259 * @hw: pointer to the hw struct
1261 * Make sure all PXE mode settings are cleared, including things
1262 * like descriptor fetch/write-back mode.
1264 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1266 if (i40e_check_asq_alive(hw))
1267 i40e_aq_clear_pxe_mode(hw, NULL);
1271 * i40e_led_is_mine - helper to find matching led
1272 * @hw: pointer to the hw struct
1273 * @idx: index into GPIO registers
1275 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1277 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1282 if (!hw->func_caps.led[idx])
1285 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1286 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1287 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1289 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1290 * if it is not our port then ignore
1292 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1299 #define I40E_COMBINED_ACTIVITY 0xA
1300 #define I40E_FILTER_ACTIVITY 0xE
1301 #define I40E_LINK_ACTIVITY 0xC
1302 #define I40E_MAC_ACTIVITY 0xD
1303 #define I40E_LED0 22
1306 * i40e_led_get - return current on/off mode
1307 * @hw: pointer to the hw struct
1309 * The value returned is the 'mode' field as defined in the
1310 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1311 * values are variations of possible behaviors relating to
1312 * blink, link, and wire.
1314 u32 i40e_led_get(struct i40e_hw *hw)
1316 u32 current_mode = 0;
1320 /* as per the documentation GPIO 22-29 are the LED
1321 * GPIO pins named LED0..LED7
1323 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1324 u32 gpio_val = i40e_led_is_mine(hw, i);
1329 /* ignore gpio LED src mode entries related to the activity LEDs */
1330 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1331 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1332 switch (current_mode) {
1333 case I40E_COMBINED_ACTIVITY:
1334 case I40E_FILTER_ACTIVITY:
1335 case I40E_MAC_ACTIVITY:
1341 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1342 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1350 * i40e_led_set - set new on/off mode
1351 * @hw: pointer to the hw struct
1352 * @mode: 0=off, 0xf=on (else see manual for mode details)
1353 * @blink: true if the LED should blink when on, false if steady
1355 * if this function is used to turn on the blink it should
1356 * be used to disable the blink when restoring the original state.
1358 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1360 u32 current_mode = 0;
1363 if (mode & 0xfffffff0)
1364 DEBUGOUT1("invalid mode passed in %X\n", mode);
1366 /* as per the documentation GPIO 22-29 are the LED
1367 * GPIO pins named LED0..LED7
1369 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1370 u32 gpio_val = i40e_led_is_mine(hw, i);
1375 /* ignore gpio LED src mode entries related to the activity LEDs */
1376 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1377 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1378 switch (current_mode) {
1379 case I40E_COMBINED_ACTIVITY:
1380 case I40E_FILTER_ACTIVITY:
1381 case I40E_MAC_ACTIVITY:
1387 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1388 /* this & is a bit of paranoia, but serves as a range check */
1389 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1390 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1392 if (mode == I40E_LINK_ACTIVITY)
1396 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1398 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1400 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1405 /* Admin command wrappers */
1408 * i40e_aq_get_phy_capabilities
1409 * @hw: pointer to the hw struct
1410 * @abilities: structure for PHY capabilities to be filled
1411 * @qualified_modules: report Qualified Modules
1412 * @report_init: report init capabilities (active are default)
1413 * @cmd_details: pointer to command details structure or NULL
1415 * Returns the various PHY abilities supported on the Port.
1417 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1418 bool qualified_modules, bool report_init,
1419 struct i40e_aq_get_phy_abilities_resp *abilities,
1420 struct i40e_asq_cmd_details *cmd_details)
1422 struct i40e_aq_desc desc;
1423 enum i40e_status_code status;
1424 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1427 return I40E_ERR_PARAM;
1429 i40e_fill_default_direct_cmd_desc(&desc,
1430 i40e_aqc_opc_get_phy_abilities);
1432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1433 if (abilities_size > I40E_AQ_LARGE_BUF)
1434 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1436 if (qualified_modules)
1437 desc.params.external.param0 |=
1438 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1441 desc.params.external.param0 |=
1442 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1444 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1447 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1448 status = I40E_ERR_UNKNOWN_PHY;
1454 * i40e_aq_set_phy_config
1455 * @hw: pointer to the hw struct
1456 * @config: structure with PHY configuration to be set
1457 * @cmd_details: pointer to command details structure or NULL
1459 * Set the various PHY configuration parameters
1460 * supported on the Port.One or more of the Set PHY config parameters may be
1461 * ignored in an MFP mode as the PF may not have the privilege to set some
1462 * of the PHY Config parameters. This status will be indicated by the
1465 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1466 struct i40e_aq_set_phy_config *config,
1467 struct i40e_asq_cmd_details *cmd_details)
1469 struct i40e_aq_desc desc;
1470 struct i40e_aq_set_phy_config *cmd =
1471 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1472 enum i40e_status_code status;
1475 return I40E_ERR_PARAM;
1477 i40e_fill_default_direct_cmd_desc(&desc,
1478 i40e_aqc_opc_set_phy_config);
1482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1489 * @hw: pointer to the hw struct
1491 * Set the requested flow control mode using set_phy_config.
1493 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1494 bool atomic_restart)
1496 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1497 struct i40e_aq_get_phy_abilities_resp abilities;
1498 struct i40e_aq_set_phy_config config;
1499 enum i40e_status_code status;
1500 u8 pause_mask = 0x0;
1506 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1507 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1509 case I40E_FC_RX_PAUSE:
1510 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1512 case I40E_FC_TX_PAUSE:
1513 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1519 /* Get the current phy config */
1520 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1523 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1527 memset(&config, 0, sizeof(config));
1528 /* clear the old pause settings */
1529 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1530 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1531 /* set the new abilities */
1532 config.abilities |= pause_mask;
1533 /* If the abilities have changed, then set the new config */
1534 if (config.abilities != abilities.abilities) {
1535 /* Auto restart link so settings take effect */
1537 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1538 /* Copy over all the old settings */
1539 config.phy_type = abilities.phy_type;
1540 config.link_speed = abilities.link_speed;
1541 config.eee_capability = abilities.eee_capability;
1542 config.eeer = abilities.eeer_val;
1543 config.low_power_ctrl = abilities.d3_lpan;
1544 status = i40e_aq_set_phy_config(hw, &config, NULL);
1547 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1549 /* Update the link info */
1550 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1552 /* Wait a little bit (on 40G cards it sometimes takes a really
1553 * long time for link to come back from the atomic reset)
1556 i40e_msec_delay(1000);
1557 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1560 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1566 * i40e_aq_set_mac_config
1567 * @hw: pointer to the hw struct
1568 * @max_frame_size: Maximum Frame Size to be supported by the port
1569 * @crc_en: Tell HW to append a CRC to outgoing frames
1570 * @pacing: Pacing configurations
1571 * @cmd_details: pointer to command details structure or NULL
1573 * Configure MAC settings for frame size, jumbo frame support and the
1574 * addition of a CRC by the hardware.
1576 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1578 bool crc_en, u16 pacing,
1579 struct i40e_asq_cmd_details *cmd_details)
1581 struct i40e_aq_desc desc;
1582 struct i40e_aq_set_mac_config *cmd =
1583 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1584 enum i40e_status_code status;
1586 if (max_frame_size == 0)
1587 return I40E_ERR_PARAM;
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_set_mac_config);
1592 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1593 cmd->params = ((u8)pacing & 0x0F) << 3;
1595 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1597 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1603 * i40e_aq_clear_pxe_mode
1604 * @hw: pointer to the hw struct
1605 * @cmd_details: pointer to command details structure or NULL
1607 * Tell the firmware that the driver is taking over from PXE
1609 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1610 struct i40e_asq_cmd_details *cmd_details)
1612 enum i40e_status_code status;
1613 struct i40e_aq_desc desc;
1614 struct i40e_aqc_clear_pxe *cmd =
1615 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1617 i40e_fill_default_direct_cmd_desc(&desc,
1618 i40e_aqc_opc_clear_pxe_mode);
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1624 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1630 * i40e_aq_set_link_restart_an
1631 * @hw: pointer to the hw struct
1632 * @enable_link: if true: enable link, if false: disable link
1633 * @cmd_details: pointer to command details structure or NULL
1635 * Sets up the link and restarts the Auto-Negotiation over the link.
1637 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1638 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1640 struct i40e_aq_desc desc;
1641 struct i40e_aqc_set_link_restart_an *cmd =
1642 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1643 enum i40e_status_code status;
1645 i40e_fill_default_direct_cmd_desc(&desc,
1646 i40e_aqc_opc_set_link_restart_an);
1648 cmd->command = I40E_AQ_PHY_RESTART_AN;
1650 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1652 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1660 * i40e_aq_get_link_info
1661 * @hw: pointer to the hw struct
1662 * @enable_lse: enable/disable LinkStatusEvent reporting
1663 * @link: pointer to link status structure - optional
1664 * @cmd_details: pointer to command details structure or NULL
1666 * Returns the link status of the adapter.
1668 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1669 bool enable_lse, struct i40e_link_status *link,
1670 struct i40e_asq_cmd_details *cmd_details)
1672 struct i40e_aq_desc desc;
1673 struct i40e_aqc_get_link_status *resp =
1674 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1675 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1676 enum i40e_status_code status;
1677 bool tx_pause, rx_pause;
1680 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1683 command_flags = I40E_AQ_LSE_ENABLE;
1685 command_flags = I40E_AQ_LSE_DISABLE;
1686 resp->command_flags = CPU_TO_LE16(command_flags);
1688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1690 if (status != I40E_SUCCESS)
1691 goto aq_get_link_info_exit;
1693 /* save off old link status information */
1694 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1695 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1697 /* update link status */
1698 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1699 hw->phy.media_type = i40e_get_media_type(hw);
1700 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1701 hw_link_info->link_info = resp->link_info;
1702 hw_link_info->an_info = resp->an_info;
1703 hw_link_info->ext_info = resp->ext_info;
1704 hw_link_info->loopback = resp->loopback;
1705 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1706 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1708 /* update fc info */
1709 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1710 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1711 if (tx_pause & rx_pause)
1712 hw->fc.current_mode = I40E_FC_FULL;
1714 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1716 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1718 hw->fc.current_mode = I40E_FC_NONE;
1720 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1721 hw_link_info->crc_enable = true;
1723 hw_link_info->crc_enable = false;
1725 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1726 hw_link_info->lse_enable = true;
1728 hw_link_info->lse_enable = false;
1730 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1731 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1732 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1734 /* save link status information */
1736 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1737 I40E_NONDMA_TO_NONDMA);
1739 /* flag cleared so helper functions don't call AQ again */
1740 hw->phy.get_link_info = false;
1742 aq_get_link_info_exit:
1748 * i40e_aq_set_phy_int_mask
1749 * @hw: pointer to the hw struct
1750 * @mask: interrupt mask to be set
1751 * @cmd_details: pointer to command details structure or NULL
1753 * Set link interrupt mask.
1755 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1757 struct i40e_asq_cmd_details *cmd_details)
1759 struct i40e_aq_desc desc;
1760 struct i40e_aqc_set_phy_int_mask *cmd =
1761 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1762 enum i40e_status_code status;
1764 i40e_fill_default_direct_cmd_desc(&desc,
1765 i40e_aqc_opc_set_phy_int_mask);
1767 cmd->event_mask = CPU_TO_LE16(mask);
1769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1775 * i40e_aq_get_local_advt_reg
1776 * @hw: pointer to the hw struct
1777 * @advt_reg: local AN advertisement register value
1778 * @cmd_details: pointer to command details structure or NULL
1780 * Get the Local AN advertisement register value.
1782 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1784 struct i40e_asq_cmd_details *cmd_details)
1786 struct i40e_aq_desc desc;
1787 struct i40e_aqc_an_advt_reg *resp =
1788 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1789 enum i40e_status_code status;
1791 i40e_fill_default_direct_cmd_desc(&desc,
1792 i40e_aqc_opc_get_local_advt_reg);
1794 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1796 if (status != I40E_SUCCESS)
1797 goto aq_get_local_advt_reg_exit;
1799 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1800 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1802 aq_get_local_advt_reg_exit:
1807 * i40e_aq_set_local_advt_reg
1808 * @hw: pointer to the hw struct
1809 * @advt_reg: local AN advertisement register value
1810 * @cmd_details: pointer to command details structure or NULL
1812 * Get the Local AN advertisement register value.
1814 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1816 struct i40e_asq_cmd_details *cmd_details)
1818 struct i40e_aq_desc desc;
1819 struct i40e_aqc_an_advt_reg *cmd =
1820 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1821 enum i40e_status_code status;
1823 i40e_fill_default_direct_cmd_desc(&desc,
1824 i40e_aqc_opc_get_local_advt_reg);
1826 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1827 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1829 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1835 * i40e_aq_get_partner_advt
1836 * @hw: pointer to the hw struct
1837 * @advt_reg: AN partner advertisement register value
1838 * @cmd_details: pointer to command details structure or NULL
1840 * Get the link partner AN advertisement register value.
1842 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1844 struct i40e_asq_cmd_details *cmd_details)
1846 struct i40e_aq_desc desc;
1847 struct i40e_aqc_an_advt_reg *resp =
1848 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1849 enum i40e_status_code status;
1851 i40e_fill_default_direct_cmd_desc(&desc,
1852 i40e_aqc_opc_get_partner_advt);
1854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1856 if (status != I40E_SUCCESS)
1857 goto aq_get_partner_advt_exit;
1859 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1860 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1862 aq_get_partner_advt_exit:
1867 * i40e_aq_set_lb_modes
1868 * @hw: pointer to the hw struct
1869 * @lb_modes: loopback mode to be set
1870 * @cmd_details: pointer to command details structure or NULL
1872 * Sets loopback modes.
1874 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1876 struct i40e_asq_cmd_details *cmd_details)
1878 struct i40e_aq_desc desc;
1879 struct i40e_aqc_set_lb_mode *cmd =
1880 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1881 enum i40e_status_code status;
1883 i40e_fill_default_direct_cmd_desc(&desc,
1884 i40e_aqc_opc_set_lb_modes);
1886 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1894 * i40e_aq_set_phy_debug
1895 * @hw: pointer to the hw struct
1896 * @cmd_flags: debug command flags
1897 * @cmd_details: pointer to command details structure or NULL
1899 * Reset the external PHY.
1901 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1902 struct i40e_asq_cmd_details *cmd_details)
1904 struct i40e_aq_desc desc;
1905 struct i40e_aqc_set_phy_debug *cmd =
1906 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1907 enum i40e_status_code status;
1909 i40e_fill_default_direct_cmd_desc(&desc,
1910 i40e_aqc_opc_set_phy_debug);
1912 cmd->command_flags = cmd_flags;
1914 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1921 * @hw: pointer to the hw struct
1922 * @vsi_ctx: pointer to a vsi context struct
1923 * @cmd_details: pointer to command details structure or NULL
1925 * Add a VSI context to the hardware.
1927 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1928 struct i40e_vsi_context *vsi_ctx,
1929 struct i40e_asq_cmd_details *cmd_details)
1931 struct i40e_aq_desc desc;
1932 struct i40e_aqc_add_get_update_vsi *cmd =
1933 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1934 struct i40e_aqc_add_get_update_vsi_completion *resp =
1935 (struct i40e_aqc_add_get_update_vsi_completion *)
1937 enum i40e_status_code status;
1939 i40e_fill_default_direct_cmd_desc(&desc,
1940 i40e_aqc_opc_add_vsi);
1942 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1943 cmd->connection_type = vsi_ctx->connection_type;
1944 cmd->vf_id = vsi_ctx->vf_num;
1945 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1947 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1949 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1950 sizeof(vsi_ctx->info), cmd_details);
1952 if (status != I40E_SUCCESS)
1953 goto aq_add_vsi_exit;
1955 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1956 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1957 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1958 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1965 * i40e_aq_set_default_vsi
1966 * @hw: pointer to the hw struct
1968 * @cmd_details: pointer to command details structure or NULL
1970 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1972 struct i40e_asq_cmd_details *cmd_details)
1974 struct i40e_aq_desc desc;
1975 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1976 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1978 enum i40e_status_code status;
1980 i40e_fill_default_direct_cmd_desc(&desc,
1981 i40e_aqc_opc_set_vsi_promiscuous_modes);
1983 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1984 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1985 cmd->seid = CPU_TO_LE16(seid);
1987 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1993 * i40e_aq_set_vsi_unicast_promiscuous
1994 * @hw: pointer to the hw struct
1996 * @set: set unicast promiscuous enable/disable
1997 * @cmd_details: pointer to command details structure or NULL
1999 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2001 struct i40e_asq_cmd_details *cmd_details)
2003 struct i40e_aq_desc desc;
2004 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2005 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2006 enum i40e_status_code status;
2009 i40e_fill_default_direct_cmd_desc(&desc,
2010 i40e_aqc_opc_set_vsi_promiscuous_modes);
2013 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2015 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2017 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2019 cmd->seid = CPU_TO_LE16(seid);
2020 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2026 * i40e_aq_set_vsi_multicast_promiscuous
2027 * @hw: pointer to the hw struct
2029 * @set: set multicast promiscuous enable/disable
2030 * @cmd_details: pointer to command details structure or NULL
2032 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2033 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2035 struct i40e_aq_desc desc;
2036 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2037 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2038 enum i40e_status_code status;
2041 i40e_fill_default_direct_cmd_desc(&desc,
2042 i40e_aqc_opc_set_vsi_promiscuous_modes);
2045 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2047 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2049 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2051 cmd->seid = CPU_TO_LE16(seid);
2052 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2058 * i40e_aq_set_vsi_broadcast
2059 * @hw: pointer to the hw struct
2061 * @set_filter: true to set filter, false to clear filter
2062 * @cmd_details: pointer to command details structure or NULL
2064 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2066 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2067 u16 seid, bool set_filter,
2068 struct i40e_asq_cmd_details *cmd_details)
2070 struct i40e_aq_desc desc;
2071 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2072 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2073 enum i40e_status_code status;
2075 i40e_fill_default_direct_cmd_desc(&desc,
2076 i40e_aqc_opc_set_vsi_promiscuous_modes);
2079 cmd->promiscuous_flags
2080 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2082 cmd->promiscuous_flags
2083 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2085 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2086 cmd->seid = CPU_TO_LE16(seid);
2087 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2093 * i40e_get_vsi_params - get VSI configuration info
2094 * @hw: pointer to the hw struct
2095 * @vsi_ctx: pointer to a vsi context struct
2096 * @cmd_details: pointer to command details structure or NULL
2098 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2099 struct i40e_vsi_context *vsi_ctx,
2100 struct i40e_asq_cmd_details *cmd_details)
2102 struct i40e_aq_desc desc;
2103 struct i40e_aqc_add_get_update_vsi *cmd =
2104 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2105 struct i40e_aqc_add_get_update_vsi_completion *resp =
2106 (struct i40e_aqc_add_get_update_vsi_completion *)
2108 enum i40e_status_code status;
2110 UNREFERENCED_1PARAMETER(cmd_details);
2111 i40e_fill_default_direct_cmd_desc(&desc,
2112 i40e_aqc_opc_get_vsi_parameters);
2114 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2116 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2118 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2119 sizeof(vsi_ctx->info), NULL);
2121 if (status != I40E_SUCCESS)
2122 goto aq_get_vsi_params_exit;
2124 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2125 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2126 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2127 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2129 aq_get_vsi_params_exit:
2134 * i40e_aq_update_vsi_params
2135 * @hw: pointer to the hw struct
2136 * @vsi_ctx: pointer to a vsi context struct
2137 * @cmd_details: pointer to command details structure or NULL
2139 * Update a VSI context.
2141 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2142 struct i40e_vsi_context *vsi_ctx,
2143 struct i40e_asq_cmd_details *cmd_details)
2145 struct i40e_aq_desc desc;
2146 struct i40e_aqc_add_get_update_vsi *cmd =
2147 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2148 enum i40e_status_code status;
2150 i40e_fill_default_direct_cmd_desc(&desc,
2151 i40e_aqc_opc_update_vsi_parameters);
2152 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2154 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2156 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2157 sizeof(vsi_ctx->info), cmd_details);
2163 * i40e_aq_get_switch_config
2164 * @hw: pointer to the hardware structure
2165 * @buf: pointer to the result buffer
2166 * @buf_size: length of input buffer
2167 * @start_seid: seid to start for the report, 0 == beginning
2168 * @cmd_details: pointer to command details structure or NULL
2170 * Fill the buf with switch configuration returned from AdminQ command
2172 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2173 struct i40e_aqc_get_switch_config_resp *buf,
2174 u16 buf_size, u16 *start_seid,
2175 struct i40e_asq_cmd_details *cmd_details)
2177 struct i40e_aq_desc desc;
2178 struct i40e_aqc_switch_seid *scfg =
2179 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2180 enum i40e_status_code status;
2182 i40e_fill_default_direct_cmd_desc(&desc,
2183 i40e_aqc_opc_get_switch_config);
2184 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2185 if (buf_size > I40E_AQ_LARGE_BUF)
2186 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2187 scfg->seid = CPU_TO_LE16(*start_seid);
2189 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2190 *start_seid = LE16_TO_CPU(scfg->seid);
2196 * i40e_aq_get_firmware_version
2197 * @hw: pointer to the hw struct
2198 * @fw_major_version: firmware major version
2199 * @fw_minor_version: firmware minor version
2200 * @fw_build: firmware build number
2201 * @api_major_version: major queue version
2202 * @api_minor_version: minor queue version
2203 * @cmd_details: pointer to command details structure or NULL
2205 * Get the firmware version from the admin queue commands
2207 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2208 u16 *fw_major_version, u16 *fw_minor_version,
2210 u16 *api_major_version, u16 *api_minor_version,
2211 struct i40e_asq_cmd_details *cmd_details)
2213 struct i40e_aq_desc desc;
2214 struct i40e_aqc_get_version *resp =
2215 (struct i40e_aqc_get_version *)&desc.params.raw;
2216 enum i40e_status_code status;
2218 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2220 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2222 if (status == I40E_SUCCESS) {
2223 if (fw_major_version != NULL)
2224 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2225 if (fw_minor_version != NULL)
2226 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2227 if (fw_build != NULL)
2228 *fw_build = LE32_TO_CPU(resp->fw_build);
2229 if (api_major_version != NULL)
2230 *api_major_version = LE16_TO_CPU(resp->api_major);
2231 if (api_minor_version != NULL)
2232 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2234 /* A workaround to fix the API version in SW */
2235 if (api_major_version && api_minor_version &&
2236 fw_major_version && fw_minor_version &&
2237 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2238 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2239 (*fw_major_version > 4)))
2240 *api_minor_version = 2;
2247 * i40e_aq_send_driver_version
2248 * @hw: pointer to the hw struct
2249 * @dv: driver's major, minor version
2250 * @cmd_details: pointer to command details structure or NULL
2252 * Send the driver version to the firmware
2254 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2255 struct i40e_driver_version *dv,
2256 struct i40e_asq_cmd_details *cmd_details)
2258 struct i40e_aq_desc desc;
2259 struct i40e_aqc_driver_version *cmd =
2260 (struct i40e_aqc_driver_version *)&desc.params.raw;
2261 enum i40e_status_code status;
2265 return I40E_ERR_PARAM;
2267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2269 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2270 cmd->driver_major_ver = dv->major_version;
2271 cmd->driver_minor_ver = dv->minor_version;
2272 cmd->driver_build_ver = dv->build_version;
2273 cmd->driver_subbuild_ver = dv->subbuild_version;
2276 while (len < sizeof(dv->driver_string) &&
2277 (dv->driver_string[len] < 0x80) &&
2278 dv->driver_string[len])
2280 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2287 * i40e_get_link_status - get status of the HW network link
2288 * @hw: pointer to the hw struct
2290 * Returns true if link is up, false if link is down.
2292 * Side effect: LinkStatusEvent reporting becomes enabled
2294 bool i40e_get_link_status(struct i40e_hw *hw)
2296 enum i40e_status_code status = I40E_SUCCESS;
2297 bool link_status = false;
2299 if (hw->phy.get_link_info) {
2300 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2302 if (status != I40E_SUCCESS)
2303 goto i40e_get_link_status_exit;
2306 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2308 i40e_get_link_status_exit:
2313 * i40e_get_link_speed
2314 * @hw: pointer to the hw struct
2316 * Returns the link speed of the adapter.
2318 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2320 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2321 enum i40e_status_code status = I40E_SUCCESS;
2323 if (hw->phy.get_link_info) {
2324 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2326 if (status != I40E_SUCCESS)
2327 goto i40e_link_speed_exit;
2330 speed = hw->phy.link_info.link_speed;
2332 i40e_link_speed_exit:
2337 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2338 * @hw: pointer to the hw struct
2339 * @uplink_seid: the MAC or other gizmo SEID
2340 * @downlink_seid: the VSI SEID
2341 * @enabled_tc: bitmap of TCs to be enabled
2342 * @default_port: true for default port VSI, false for control port
2343 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2344 * @veb_seid: pointer to where to put the resulting VEB SEID
2345 * @cmd_details: pointer to command details structure or NULL
2347 * This asks the FW to add a VEB between the uplink and downlink
2348 * elements. If the uplink SEID is 0, this will be a floating VEB.
2350 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2351 u16 downlink_seid, u8 enabled_tc,
2352 bool default_port, bool enable_l2_filtering,
2354 struct i40e_asq_cmd_details *cmd_details)
2356 struct i40e_aq_desc desc;
2357 struct i40e_aqc_add_veb *cmd =
2358 (struct i40e_aqc_add_veb *)&desc.params.raw;
2359 struct i40e_aqc_add_veb_completion *resp =
2360 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2361 enum i40e_status_code status;
2364 /* SEIDs need to either both be set or both be 0 for floating VEB */
2365 if (!!uplink_seid != !!downlink_seid)
2366 return I40E_ERR_PARAM;
2368 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2370 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2371 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2372 cmd->enable_tcs = enabled_tc;
2374 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2376 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2378 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2380 if (enable_l2_filtering)
2381 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2383 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2387 if (!status && veb_seid)
2388 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2394 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2395 * @hw: pointer to the hw struct
2396 * @veb_seid: the SEID of the VEB to query
2397 * @switch_id: the uplink switch id
2398 * @floating: set to true if the VEB is floating
2399 * @statistic_index: index of the stats counter block for this VEB
2400 * @vebs_used: number of VEB's used by function
2401 * @vebs_free: total VEB's not reserved by any function
2402 * @cmd_details: pointer to command details structure or NULL
2404 * This retrieves the parameters for a particular VEB, specified by
2405 * uplink_seid, and returns them to the caller.
2407 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2408 u16 veb_seid, u16 *switch_id,
2409 bool *floating, u16 *statistic_index,
2410 u16 *vebs_used, u16 *vebs_free,
2411 struct i40e_asq_cmd_details *cmd_details)
2413 struct i40e_aq_desc desc;
2414 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2415 (struct i40e_aqc_get_veb_parameters_completion *)
2417 enum i40e_status_code status;
2420 return I40E_ERR_PARAM;
2422 i40e_fill_default_direct_cmd_desc(&desc,
2423 i40e_aqc_opc_get_veb_parameters);
2424 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2431 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2432 if (statistic_index)
2433 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2435 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2437 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2439 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2440 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2451 * i40e_aq_add_macvlan
2452 * @hw: pointer to the hw struct
2453 * @seid: VSI for the mac address
2454 * @mv_list: list of macvlans to be added
2455 * @count: length of the list
2456 * @cmd_details: pointer to command details structure or NULL
2458 * Add MAC/VLAN addresses to the HW filtering
2460 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2461 struct i40e_aqc_add_macvlan_element_data *mv_list,
2462 u16 count, struct i40e_asq_cmd_details *cmd_details)
2464 struct i40e_aq_desc desc;
2465 struct i40e_aqc_macvlan *cmd =
2466 (struct i40e_aqc_macvlan *)&desc.params.raw;
2467 enum i40e_status_code status;
2470 if (count == 0 || !mv_list || !hw)
2471 return I40E_ERR_PARAM;
2473 buf_size = count * sizeof(*mv_list);
2475 /* prep the rest of the request */
2476 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2477 cmd->num_addresses = CPU_TO_LE16(count);
2478 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2482 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2483 if (buf_size > I40E_AQ_LARGE_BUF)
2484 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2486 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2493 * i40e_aq_remove_macvlan
2494 * @hw: pointer to the hw struct
2495 * @seid: VSI for the mac address
2496 * @mv_list: list of macvlans to be removed
2497 * @count: length of the list
2498 * @cmd_details: pointer to command details structure or NULL
2500 * Remove MAC/VLAN addresses from the HW filtering
2502 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2503 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2504 u16 count, struct i40e_asq_cmd_details *cmd_details)
2506 struct i40e_aq_desc desc;
2507 struct i40e_aqc_macvlan *cmd =
2508 (struct i40e_aqc_macvlan *)&desc.params.raw;
2509 enum i40e_status_code status;
2512 if (count == 0 || !mv_list || !hw)
2513 return I40E_ERR_PARAM;
2515 buf_size = count * sizeof(*mv_list);
2517 /* prep the rest of the request */
2518 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2519 cmd->num_addresses = CPU_TO_LE16(count);
2520 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2524 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2525 if (buf_size > I40E_AQ_LARGE_BUF)
2526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2528 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2535 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2536 * @hw: pointer to the hw struct
2537 * @seid: VSI for the vlan filters
2538 * @v_list: list of vlan filters to be added
2539 * @count: length of the list
2540 * @cmd_details: pointer to command details structure or NULL
2542 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2543 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2544 u8 count, struct i40e_asq_cmd_details *cmd_details)
2546 struct i40e_aq_desc desc;
2547 struct i40e_aqc_macvlan *cmd =
2548 (struct i40e_aqc_macvlan *)&desc.params.raw;
2549 enum i40e_status_code status;
2552 if (count == 0 || !v_list || !hw)
2553 return I40E_ERR_PARAM;
2555 buf_size = count * sizeof(*v_list);
2557 /* prep the rest of the request */
2558 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2559 cmd->num_addresses = CPU_TO_LE16(count);
2560 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2564 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2565 if (buf_size > I40E_AQ_LARGE_BUF)
2566 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2568 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2575 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2576 * @hw: pointer to the hw struct
2577 * @seid: VSI for the vlan filters
2578 * @v_list: list of macvlans to be removed
2579 * @count: length of the list
2580 * @cmd_details: pointer to command details structure or NULL
2582 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2583 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2584 u8 count, struct i40e_asq_cmd_details *cmd_details)
2586 struct i40e_aq_desc desc;
2587 struct i40e_aqc_macvlan *cmd =
2588 (struct i40e_aqc_macvlan *)&desc.params.raw;
2589 enum i40e_status_code status;
2592 if (count == 0 || !v_list || !hw)
2593 return I40E_ERR_PARAM;
2595 buf_size = count * sizeof(*v_list);
2597 /* prep the rest of the request */
2598 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2599 cmd->num_addresses = CPU_TO_LE16(count);
2600 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2604 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2605 if (buf_size > I40E_AQ_LARGE_BUF)
2606 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2608 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2615 * i40e_aq_send_msg_to_vf
2616 * @hw: pointer to the hardware structure
2617 * @vfid: vf id to send msg
2618 * @v_opcode: opcodes for VF-PF communication
2619 * @v_retval: return error code
2620 * @msg: pointer to the msg buffer
2621 * @msglen: msg length
2622 * @cmd_details: pointer to command details
2626 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2627 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2628 struct i40e_asq_cmd_details *cmd_details)
2630 struct i40e_aq_desc desc;
2631 struct i40e_aqc_pf_vf_message *cmd =
2632 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2633 enum i40e_status_code status;
2635 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2636 cmd->id = CPU_TO_LE32(vfid);
2637 desc.cookie_high = CPU_TO_LE32(v_opcode);
2638 desc.cookie_low = CPU_TO_LE32(v_retval);
2639 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2641 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2643 if (msglen > I40E_AQ_LARGE_BUF)
2644 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2645 desc.datalen = CPU_TO_LE16(msglen);
2647 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2653 * i40e_aq_debug_read_register
2654 * @hw: pointer to the hw struct
2655 * @reg_addr: register address
2656 * @reg_val: register value
2657 * @cmd_details: pointer to command details structure or NULL
2659 * Read the register using the admin queue commands
2661 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2662 u32 reg_addr, u64 *reg_val,
2663 struct i40e_asq_cmd_details *cmd_details)
2665 struct i40e_aq_desc desc;
2666 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2667 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2668 enum i40e_status_code status;
2670 if (reg_val == NULL)
2671 return I40E_ERR_PARAM;
2673 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2675 cmd_resp->address = CPU_TO_LE32(reg_addr);
2677 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2679 if (status == I40E_SUCCESS) {
2680 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2681 (u64)LE32_TO_CPU(cmd_resp->value_low);
2688 * i40e_aq_debug_write_register
2689 * @hw: pointer to the hw struct
2690 * @reg_addr: register address
2691 * @reg_val: register value
2692 * @cmd_details: pointer to command details structure or NULL
2694 * Write to a register using the admin queue commands
2696 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2697 u32 reg_addr, u64 reg_val,
2698 struct i40e_asq_cmd_details *cmd_details)
2700 struct i40e_aq_desc desc;
2701 struct i40e_aqc_debug_reg_read_write *cmd =
2702 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2703 enum i40e_status_code status;
2705 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2707 cmd->address = CPU_TO_LE32(reg_addr);
2708 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2709 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2711 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2717 * i40e_aq_get_hmc_resource_profile
2718 * @hw: pointer to the hw struct
2719 * @profile: type of profile the HMC is to be set as
2720 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2721 * @cmd_details: pointer to command details structure or NULL
2723 * query the HMC profile of the device.
2725 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2726 enum i40e_aq_hmc_profile *profile,
2727 u8 *pe_vf_enabled_count,
2728 struct i40e_asq_cmd_details *cmd_details)
2730 struct i40e_aq_desc desc;
2731 struct i40e_aq_get_set_hmc_resource_profile *resp =
2732 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2733 enum i40e_status_code status;
2735 i40e_fill_default_direct_cmd_desc(&desc,
2736 i40e_aqc_opc_query_hmc_resource_profile);
2737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2739 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2740 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2741 *pe_vf_enabled_count = resp->pe_vf_enabled &
2742 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2748 * i40e_aq_set_hmc_resource_profile
2749 * @hw: pointer to the hw struct
2750 * @profile: type of profile the HMC is to be set as
2751 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2752 * @cmd_details: pointer to command details structure or NULL
2754 * set the HMC profile of the device.
2756 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2757 enum i40e_aq_hmc_profile profile,
2758 u8 pe_vf_enabled_count,
2759 struct i40e_asq_cmd_details *cmd_details)
2761 struct i40e_aq_desc desc;
2762 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2763 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2764 enum i40e_status_code status;
2766 i40e_fill_default_direct_cmd_desc(&desc,
2767 i40e_aqc_opc_set_hmc_resource_profile);
2769 cmd->pm_profile = (u8)profile;
2770 cmd->pe_vf_enabled = pe_vf_enabled_count;
2772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2778 * i40e_aq_request_resource
2779 * @hw: pointer to the hw struct
2780 * @resource: resource id
2781 * @access: access type
2782 * @sdp_number: resource number
2783 * @timeout: the maximum time in ms that the driver may hold the resource
2784 * @cmd_details: pointer to command details structure or NULL
2786 * requests common resource using the admin queue commands
2788 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2789 enum i40e_aq_resources_ids resource,
2790 enum i40e_aq_resource_access_type access,
2791 u8 sdp_number, u64 *timeout,
2792 struct i40e_asq_cmd_details *cmd_details)
2794 struct i40e_aq_desc desc;
2795 struct i40e_aqc_request_resource *cmd_resp =
2796 (struct i40e_aqc_request_resource *)&desc.params.raw;
2797 enum i40e_status_code status;
2799 DEBUGFUNC("i40e_aq_request_resource");
2801 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2803 cmd_resp->resource_id = CPU_TO_LE16(resource);
2804 cmd_resp->access_type = CPU_TO_LE16(access);
2805 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2808 /* The completion specifies the maximum time in ms that the driver
2809 * may hold the resource in the Timeout field.
2810 * If the resource is held by someone else, the command completes with
2811 * busy return value and the timeout field indicates the maximum time
2812 * the current owner of the resource has to free it.
2814 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2815 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2821 * i40e_aq_release_resource
2822 * @hw: pointer to the hw struct
2823 * @resource: resource id
2824 * @sdp_number: resource number
2825 * @cmd_details: pointer to command details structure or NULL
2827 * release common resource using the admin queue commands
2829 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2830 enum i40e_aq_resources_ids resource,
2832 struct i40e_asq_cmd_details *cmd_details)
2834 struct i40e_aq_desc desc;
2835 struct i40e_aqc_request_resource *cmd =
2836 (struct i40e_aqc_request_resource *)&desc.params.raw;
2837 enum i40e_status_code status;
2839 DEBUGFUNC("i40e_aq_release_resource");
2841 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2843 cmd->resource_id = CPU_TO_LE16(resource);
2844 cmd->resource_number = CPU_TO_LE32(sdp_number);
2846 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2853 * @hw: pointer to the hw struct
2854 * @module_pointer: module pointer location in words from the NVM beginning
2855 * @offset: byte offset from the module beginning
2856 * @length: length of the section to be read (in bytes from the offset)
2857 * @data: command buffer (size [bytes] = length)
2858 * @last_command: tells if this is the last command in a series
2859 * @cmd_details: pointer to command details structure or NULL
2861 * Read the NVM using the admin queue commands
2863 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2864 u32 offset, u16 length, void *data,
2866 struct i40e_asq_cmd_details *cmd_details)
2868 struct i40e_aq_desc desc;
2869 struct i40e_aqc_nvm_update *cmd =
2870 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2871 enum i40e_status_code status;
2873 DEBUGFUNC("i40e_aq_read_nvm");
2875 /* In offset the highest byte must be zeroed. */
2876 if (offset & 0xFF000000) {
2877 status = I40E_ERR_PARAM;
2878 goto i40e_aq_read_nvm_exit;
2881 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2883 /* If this is the last command in a series, set the proper flag. */
2885 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2886 cmd->module_pointer = module_pointer;
2887 cmd->offset = CPU_TO_LE32(offset);
2888 cmd->length = CPU_TO_LE16(length);
2890 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2891 if (length > I40E_AQ_LARGE_BUF)
2892 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2894 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2896 i40e_aq_read_nvm_exit:
2901 * i40e_aq_read_nvm_config - read an nvm config block
2902 * @hw: pointer to the hw struct
2903 * @cmd_flags: NVM access admin command bits
2904 * @field_id: field or feature id
2905 * @data: buffer for result
2906 * @buf_size: buffer size
2907 * @element_count: pointer to count of elements read by FW
2908 * @cmd_details: pointer to command details structure or NULL
2910 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
2911 u8 cmd_flags, u32 field_id, void *data,
2912 u16 buf_size, u16 *element_count,
2913 struct i40e_asq_cmd_details *cmd_details)
2915 struct i40e_aq_desc desc;
2916 struct i40e_aqc_nvm_config_read *cmd =
2917 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
2918 enum i40e_status_code status;
2920 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
2921 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
2922 if (buf_size > I40E_AQ_LARGE_BUF)
2923 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2925 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2926 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
2927 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
2928 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
2930 cmd->element_id_msw = 0;
2932 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2934 if (!status && element_count)
2935 *element_count = LE16_TO_CPU(cmd->element_count);
2941 * i40e_aq_write_nvm_config - write an nvm config block
2942 * @hw: pointer to the hw struct
2943 * @cmd_flags: NVM access admin command bits
2944 * @data: buffer for result
2945 * @buf_size: buffer size
2946 * @element_count: count of elements to be written
2947 * @cmd_details: pointer to command details structure or NULL
2949 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
2950 u8 cmd_flags, void *data, u16 buf_size,
2952 struct i40e_asq_cmd_details *cmd_details)
2954 struct i40e_aq_desc desc;
2955 struct i40e_aqc_nvm_config_write *cmd =
2956 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
2957 enum i40e_status_code status;
2959 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
2960 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2961 if (buf_size > I40E_AQ_LARGE_BUF)
2962 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2964 cmd->element_count = CPU_TO_LE16(element_count);
2965 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
2966 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
2973 * @hw: pointer to the hw struct
2974 * @module_pointer: module pointer location in words from the NVM beginning
2975 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2976 * @length: length of the section to be erased (expressed in 4 KB)
2977 * @last_command: tells if this is the last command in a series
2978 * @cmd_details: pointer to command details structure or NULL
2980 * Erase the NVM sector using the admin queue commands
2982 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2983 u32 offset, u16 length, bool last_command,
2984 struct i40e_asq_cmd_details *cmd_details)
2986 struct i40e_aq_desc desc;
2987 struct i40e_aqc_nvm_update *cmd =
2988 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2989 enum i40e_status_code status;
2991 DEBUGFUNC("i40e_aq_erase_nvm");
2993 /* In offset the highest byte must be zeroed. */
2994 if (offset & 0xFF000000) {
2995 status = I40E_ERR_PARAM;
2996 goto i40e_aq_erase_nvm_exit;
2999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3001 /* If this is the last command in a series, set the proper flag. */
3003 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3004 cmd->module_pointer = module_pointer;
3005 cmd->offset = CPU_TO_LE32(offset);
3006 cmd->length = CPU_TO_LE16(length);
3008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3010 i40e_aq_erase_nvm_exit:
3014 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3015 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3016 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3017 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3018 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3019 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3020 #define I40E_DEV_FUNC_CAP_VF 0x13
3021 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3022 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3023 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3024 #define I40E_DEV_FUNC_CAP_VSI 0x17
3025 #define I40E_DEV_FUNC_CAP_DCB 0x18
3026 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3027 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3028 #define I40E_DEV_FUNC_CAP_RSS 0x40
3029 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3030 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3031 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3032 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3033 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3034 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3035 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
3036 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3037 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3038 #define I40E_DEV_FUNC_CAP_LED 0x61
3039 #define I40E_DEV_FUNC_CAP_SDP 0x62
3040 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3043 * i40e_parse_discover_capabilities
3044 * @hw: pointer to the hw struct
3045 * @buff: pointer to a buffer containing device/function capability records
3046 * @cap_count: number of capability records in the list
3047 * @list_type_opc: type of capabilities list to parse
3049 * Parse the device/function capabilities list.
3051 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3053 enum i40e_admin_queue_opc list_type_opc)
3055 struct i40e_aqc_list_capabilities_element_resp *cap;
3056 u32 valid_functions, num_functions;
3057 u32 number, logical_id, phys_id;
3058 struct i40e_hw_capabilities *p;
3062 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3064 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3065 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3066 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3067 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3071 for (i = 0; i < cap_count; i++, cap++) {
3072 id = LE16_TO_CPU(cap->id);
3073 number = LE32_TO_CPU(cap->number);
3074 logical_id = LE32_TO_CPU(cap->logical_id);
3075 phys_id = LE32_TO_CPU(cap->phys_id);
3078 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3079 p->switch_mode = number;
3081 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3082 p->management_mode = number;
3084 case I40E_DEV_FUNC_CAP_NPAR:
3085 p->npar_enable = number;
3087 case I40E_DEV_FUNC_CAP_OS2BMC:
3090 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3091 p->valid_functions = number;
3093 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3095 p->sr_iov_1_1 = true;
3097 case I40E_DEV_FUNC_CAP_VF:
3098 p->num_vfs = number;
3099 p->vf_base_id = logical_id;
3101 case I40E_DEV_FUNC_CAP_VMDQ:
3105 case I40E_DEV_FUNC_CAP_802_1_QBG:
3107 p->evb_802_1_qbg = true;
3109 case I40E_DEV_FUNC_CAP_802_1_QBH:
3111 p->evb_802_1_qbh = true;
3113 case I40E_DEV_FUNC_CAP_VSI:
3114 p->num_vsis = number;
3116 case I40E_DEV_FUNC_CAP_DCB:
3119 p->enabled_tcmap = logical_id;
3123 case I40E_DEV_FUNC_CAP_FCOE:
3127 case I40E_DEV_FUNC_CAP_ISCSI:
3131 case I40E_DEV_FUNC_CAP_RSS:
3133 p->rss_table_size = number;
3134 p->rss_table_entry_width = logical_id;
3136 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3137 p->num_rx_qp = number;
3138 p->base_queue = phys_id;
3140 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3141 p->num_tx_qp = number;
3142 p->base_queue = phys_id;
3144 case I40E_DEV_FUNC_CAP_MSIX:
3145 p->num_msix_vectors = number;
3147 case I40E_DEV_FUNC_CAP_MSIX_VF:
3148 p->num_msix_vectors_vf = number;
3150 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
3152 p->mfp_mode_1 = true;
3154 case I40E_DEV_FUNC_CAP_CEM:
3158 case I40E_DEV_FUNC_CAP_IWARP:
3162 case I40E_DEV_FUNC_CAP_LED:
3163 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3164 p->led[phys_id] = true;
3166 case I40E_DEV_FUNC_CAP_SDP:
3167 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3168 p->sdp[phys_id] = true;
3170 case I40E_DEV_FUNC_CAP_MDIO:
3172 p->mdio_port_num = phys_id;
3173 p->mdio_port_mode = logical_id;
3176 case I40E_DEV_FUNC_CAP_IEEE_1588:
3178 p->ieee_1588 = true;
3180 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3182 p->fd_filters_guaranteed = number;
3183 p->fd_filters_best_effort = logical_id;
3190 #ifdef I40E_FCOE_ENA
3191 /* Software override ensuring FCoE is disabled if npar or mfp
3192 * mode because it is not supported in these modes.
3194 if (p->npar_enable || p->mfp_mode_1)
3197 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3201 /* count the enabled ports (aka the "not disabled" ports) */
3203 for (i = 0; i < 4; i++) {
3204 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3207 /* use AQ read to get the physical register offset instead
3208 * of the port relative offset
3210 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3211 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3215 valid_functions = p->valid_functions;
3217 while (valid_functions) {
3218 if (valid_functions & 1)
3220 valid_functions >>= 1;
3223 /* partition id is 1-based, and functions are evenly spread
3224 * across the ports as partitions
3226 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3227 hw->num_partitions = num_functions / hw->num_ports;
3229 /* additional HW specific goodies that might
3230 * someday be HW version specific
3232 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3236 * i40e_aq_discover_capabilities
3237 * @hw: pointer to the hw struct
3238 * @buff: a virtual buffer to hold the capabilities
3239 * @buff_size: Size of the virtual buffer
3240 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3241 * @list_type_opc: capabilities type to discover - pass in the command opcode
3242 * @cmd_details: pointer to command details structure or NULL
3244 * Get the device capabilities descriptions from the firmware
3246 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3247 void *buff, u16 buff_size, u16 *data_size,
3248 enum i40e_admin_queue_opc list_type_opc,
3249 struct i40e_asq_cmd_details *cmd_details)
3251 struct i40e_aqc_list_capabilites *cmd;
3252 struct i40e_aq_desc desc;
3253 enum i40e_status_code status = I40E_SUCCESS;
3255 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3257 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3258 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3259 status = I40E_ERR_PARAM;
3263 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3265 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3266 if (buff_size > I40E_AQ_LARGE_BUF)
3267 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3269 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3270 *data_size = LE16_TO_CPU(desc.datalen);
3275 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3283 * i40e_aq_update_nvm
3284 * @hw: pointer to the hw struct
3285 * @module_pointer: module pointer location in words from the NVM beginning
3286 * @offset: byte offset from the module beginning
3287 * @length: length of the section to be written (in bytes from the offset)
3288 * @data: command buffer (size [bytes] = length)
3289 * @last_command: tells if this is the last command in a series
3290 * @cmd_details: pointer to command details structure or NULL
3292 * Update the NVM using the admin queue commands
3294 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3295 u32 offset, u16 length, void *data,
3297 struct i40e_asq_cmd_details *cmd_details)
3299 struct i40e_aq_desc desc;
3300 struct i40e_aqc_nvm_update *cmd =
3301 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3302 enum i40e_status_code status;
3304 DEBUGFUNC("i40e_aq_update_nvm");
3306 /* In offset the highest byte must be zeroed. */
3307 if (offset & 0xFF000000) {
3308 status = I40E_ERR_PARAM;
3309 goto i40e_aq_update_nvm_exit;
3312 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3314 /* If this is the last command in a series, set the proper flag. */
3316 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3317 cmd->module_pointer = module_pointer;
3318 cmd->offset = CPU_TO_LE32(offset);
3319 cmd->length = CPU_TO_LE16(length);
3321 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3322 if (length > I40E_AQ_LARGE_BUF)
3323 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3325 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3327 i40e_aq_update_nvm_exit:
3332 * i40e_aq_get_lldp_mib
3333 * @hw: pointer to the hw struct
3334 * @bridge_type: type of bridge requested
3335 * @mib_type: Local, Remote or both Local and Remote MIBs
3336 * @buff: pointer to a user supplied buffer to store the MIB block
3337 * @buff_size: size of the buffer (in bytes)
3338 * @local_len : length of the returned Local LLDP MIB
3339 * @remote_len: length of the returned Remote LLDP MIB
3340 * @cmd_details: pointer to command details structure or NULL
3342 * Requests the complete LLDP MIB (entire packet).
3344 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3345 u8 mib_type, void *buff, u16 buff_size,
3346 u16 *local_len, u16 *remote_len,
3347 struct i40e_asq_cmd_details *cmd_details)
3349 struct i40e_aq_desc desc;
3350 struct i40e_aqc_lldp_get_mib *cmd =
3351 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3352 struct i40e_aqc_lldp_get_mib *resp =
3353 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3354 enum i40e_status_code status;
3356 if (buff_size == 0 || !buff)
3357 return I40E_ERR_PARAM;
3359 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3360 /* Indirect Command */
3361 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3363 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3364 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3365 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3367 desc.datalen = CPU_TO_LE16(buff_size);
3369 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3370 if (buff_size > I40E_AQ_LARGE_BUF)
3371 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3373 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3375 if (local_len != NULL)
3376 *local_len = LE16_TO_CPU(resp->local_len);
3377 if (remote_len != NULL)
3378 *remote_len = LE16_TO_CPU(resp->remote_len);
3385 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3386 * @hw: pointer to the hw struct
3387 * @mib_type: Local, Remote or both Local and Remote MIBs
3388 * @buff: pointer to a user supplied buffer to store the MIB block
3389 * @buff_size: size of the buffer (in bytes)
3390 * @cmd_details: pointer to command details structure or NULL
3394 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3395 u8 mib_type, void *buff, u16 buff_size,
3396 struct i40e_asq_cmd_details *cmd_details)
3398 struct i40e_aq_desc desc;
3399 struct i40e_aqc_lldp_set_local_mib *cmd =
3400 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3401 enum i40e_status_code status;
3403 if (buff_size == 0 || !buff)
3404 return I40E_ERR_PARAM;
3406 i40e_fill_default_direct_cmd_desc(&desc,
3407 i40e_aqc_opc_lldp_set_local_mib);
3408 /* Indirect Command */
3409 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3410 if (buff_size > I40E_AQ_LARGE_BUF)
3411 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3412 desc.datalen = CPU_TO_LE16(buff_size);
3414 cmd->type = mib_type;
3415 cmd->length = CPU_TO_LE16(buff_size);
3416 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3417 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3419 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3424 * i40e_aq_cfg_lldp_mib_change_event
3425 * @hw: pointer to the hw struct
3426 * @enable_update: Enable or Disable event posting
3427 * @cmd_details: pointer to command details structure or NULL
3429 * Enable or Disable posting of an event on ARQ when LLDP MIB
3430 * associated with the interface changes
3432 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3434 struct i40e_asq_cmd_details *cmd_details)
3436 struct i40e_aq_desc desc;
3437 struct i40e_aqc_lldp_update_mib *cmd =
3438 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3439 enum i40e_status_code status;
3441 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3444 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3446 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3452 * i40e_aq_add_lldp_tlv
3453 * @hw: pointer to the hw struct
3454 * @bridge_type: type of bridge
3455 * @buff: buffer with TLV to add
3456 * @buff_size: length of the buffer
3457 * @tlv_len: length of the TLV to be added
3458 * @mib_len: length of the LLDP MIB returned in response
3459 * @cmd_details: pointer to command details structure or NULL
3461 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3462 * it is responsibility of the caller to make sure that the TLV is not
3463 * already present in the LLDPDU.
3464 * In return firmware will write the complete LLDP MIB with the newly
3465 * added TLV in the response buffer.
3467 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3468 void *buff, u16 buff_size, u16 tlv_len,
3470 struct i40e_asq_cmd_details *cmd_details)
3472 struct i40e_aq_desc desc;
3473 struct i40e_aqc_lldp_add_tlv *cmd =
3474 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3475 enum i40e_status_code status;
3477 if (buff_size == 0 || !buff || tlv_len == 0)
3478 return I40E_ERR_PARAM;
3480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3482 /* Indirect Command */
3483 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3484 if (buff_size > I40E_AQ_LARGE_BUF)
3485 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3486 desc.datalen = CPU_TO_LE16(buff_size);
3488 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3489 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3490 cmd->len = CPU_TO_LE16(tlv_len);
3492 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3494 if (mib_len != NULL)
3495 *mib_len = LE16_TO_CPU(desc.datalen);
3502 * i40e_aq_update_lldp_tlv
3503 * @hw: pointer to the hw struct
3504 * @bridge_type: type of bridge
3505 * @buff: buffer with TLV to update
3506 * @buff_size: size of the buffer holding original and updated TLVs
3507 * @old_len: Length of the Original TLV
3508 * @new_len: Length of the Updated TLV
3509 * @offset: offset of the updated TLV in the buff
3510 * @mib_len: length of the returned LLDP MIB
3511 * @cmd_details: pointer to command details structure or NULL
3513 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3514 * Firmware will place the complete LLDP MIB in response buffer with the
3517 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3518 u8 bridge_type, void *buff, u16 buff_size,
3519 u16 old_len, u16 new_len, u16 offset,
3521 struct i40e_asq_cmd_details *cmd_details)
3523 struct i40e_aq_desc desc;
3524 struct i40e_aqc_lldp_update_tlv *cmd =
3525 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3526 enum i40e_status_code status;
3528 if (buff_size == 0 || !buff || offset == 0 ||
3529 old_len == 0 || new_len == 0)
3530 return I40E_ERR_PARAM;
3532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3534 /* Indirect Command */
3535 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3536 if (buff_size > I40E_AQ_LARGE_BUF)
3537 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3538 desc.datalen = CPU_TO_LE16(buff_size);
3540 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3541 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3542 cmd->old_len = CPU_TO_LE16(old_len);
3543 cmd->new_offset = CPU_TO_LE16(offset);
3544 cmd->new_len = CPU_TO_LE16(new_len);
3546 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3548 if (mib_len != NULL)
3549 *mib_len = LE16_TO_CPU(desc.datalen);
3556 * i40e_aq_delete_lldp_tlv
3557 * @hw: pointer to the hw struct
3558 * @bridge_type: type of bridge
3559 * @buff: pointer to a user supplied buffer that has the TLV
3560 * @buff_size: length of the buffer
3561 * @tlv_len: length of the TLV to be deleted
3562 * @mib_len: length of the returned LLDP MIB
3563 * @cmd_details: pointer to command details structure or NULL
3565 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3566 * The firmware places the entire LLDP MIB in the response buffer.
3568 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3569 u8 bridge_type, void *buff, u16 buff_size,
3570 u16 tlv_len, u16 *mib_len,
3571 struct i40e_asq_cmd_details *cmd_details)
3573 struct i40e_aq_desc desc;
3574 struct i40e_aqc_lldp_add_tlv *cmd =
3575 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3576 enum i40e_status_code status;
3578 if (buff_size == 0 || !buff)
3579 return I40E_ERR_PARAM;
3581 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3583 /* Indirect Command */
3584 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3585 if (buff_size > I40E_AQ_LARGE_BUF)
3586 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3587 desc.datalen = CPU_TO_LE16(buff_size);
3588 cmd->len = CPU_TO_LE16(tlv_len);
3589 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3590 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3592 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3594 if (mib_len != NULL)
3595 *mib_len = LE16_TO_CPU(desc.datalen);
3603 * @hw: pointer to the hw struct
3604 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3605 * @cmd_details: pointer to command details structure or NULL
3607 * Stop or Shutdown the embedded LLDP Agent
3609 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3610 struct i40e_asq_cmd_details *cmd_details)
3612 struct i40e_aq_desc desc;
3613 struct i40e_aqc_lldp_stop *cmd =
3614 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3615 enum i40e_status_code status;
3617 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3620 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3628 * i40e_aq_start_lldp
3629 * @hw: pointer to the hw struct
3630 * @cmd_details: pointer to command details structure or NULL
3632 * Start the embedded LLDP Agent on all ports.
3634 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3635 struct i40e_asq_cmd_details *cmd_details)
3637 struct i40e_aq_desc desc;
3638 struct i40e_aqc_lldp_start *cmd =
3639 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3640 enum i40e_status_code status;
3642 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3644 cmd->command = I40E_AQ_LLDP_AGENT_START;
3646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3652 * i40e_aq_get_cee_dcb_config
3653 * @hw: pointer to the hw struct
3654 * @buff: response buffer that stores CEE operational configuration
3655 * @buff_size: size of the buffer passed
3656 * @cmd_details: pointer to command details structure or NULL
3658 * Get CEE DCBX mode operational configuration from firmware
3660 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3661 void *buff, u16 buff_size,
3662 struct i40e_asq_cmd_details *cmd_details)
3664 struct i40e_aq_desc desc;
3665 enum i40e_status_code status;
3667 if (buff_size == 0 || !buff)
3668 return I40E_ERR_PARAM;
3670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3672 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3673 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3680 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3681 * @hw: pointer to the hw struct
3682 * @start_agent: True if DCBx Agent needs to be Started
3683 * False if DCBx Agent needs to be Stopped
3684 * @cmd_details: pointer to command details structure or NULL
3686 * Start/Stop the embedded dcbx Agent
3688 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3690 struct i40e_asq_cmd_details *cmd_details)
3692 struct i40e_aq_desc desc;
3693 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3694 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3696 enum i40e_status_code status;
3698 i40e_fill_default_direct_cmd_desc(&desc,
3699 i40e_aqc_opc_lldp_stop_start_spec_agent);
3702 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3704 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3710 * i40e_aq_add_udp_tunnel
3711 * @hw: pointer to the hw struct
3712 * @udp_port: the UDP port to add
3713 * @header_len: length of the tunneling header length in DWords
3714 * @protocol_index: protocol index type
3715 * @filter_index: pointer to filter index
3716 * @cmd_details: pointer to command details structure or NULL
3718 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3719 u16 udp_port, u8 protocol_index,
3721 struct i40e_asq_cmd_details *cmd_details)
3723 struct i40e_aq_desc desc;
3724 struct i40e_aqc_add_udp_tunnel *cmd =
3725 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3726 struct i40e_aqc_del_udp_tunnel_completion *resp =
3727 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3728 enum i40e_status_code status;
3730 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3732 cmd->udp_port = CPU_TO_LE16(udp_port);
3733 cmd->protocol_type = protocol_index;
3735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3737 if (!status && filter_index)
3738 *filter_index = resp->index;
3744 * i40e_aq_del_udp_tunnel
3745 * @hw: pointer to the hw struct
3746 * @index: filter index
3747 * @cmd_details: pointer to command details structure or NULL
3749 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3750 struct i40e_asq_cmd_details *cmd_details)
3752 struct i40e_aq_desc desc;
3753 struct i40e_aqc_remove_udp_tunnel *cmd =
3754 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3755 enum i40e_status_code status;
3757 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3767 * i40e_aq_get_switch_resource_alloc (0x0204)
3768 * @hw: pointer to the hw struct
3769 * @num_entries: pointer to u8 to store the number of resource entries returned
3770 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3771 * to store the resource information for all resource types. Each
3772 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3773 * @count: size, in bytes, of the buffer provided
3774 * @cmd_details: pointer to command details structure or NULL
3776 * Query the resources allocated to a function.
3778 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3780 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3782 struct i40e_asq_cmd_details *cmd_details)
3784 struct i40e_aq_desc desc;
3785 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3786 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3787 enum i40e_status_code status;
3788 u16 length = count * sizeof(*buf);
3790 i40e_fill_default_direct_cmd_desc(&desc,
3791 i40e_aqc_opc_get_switch_resource_alloc);
3793 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3794 if (length > I40E_AQ_LARGE_BUF)
3795 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3797 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3799 if (!status && num_entries)
3800 *num_entries = cmd_resp->num_entries;
3806 * i40e_aq_delete_element - Delete switch element
3807 * @hw: pointer to the hw struct
3808 * @seid: the SEID to delete from the switch
3809 * @cmd_details: pointer to command details structure or NULL
3811 * This deletes a switch element from the switch.
3813 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3814 struct i40e_asq_cmd_details *cmd_details)
3816 struct i40e_aq_desc desc;
3817 struct i40e_aqc_switch_seid *cmd =
3818 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3819 enum i40e_status_code status;
3822 return I40E_ERR_PARAM;
3824 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3826 cmd->seid = CPU_TO_LE16(seid);
3828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3834 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3835 * @hw: pointer to the hw struct
3836 * @flags: component flags
3837 * @mac_seid: uplink seid (MAC SEID)
3838 * @vsi_seid: connected vsi seid
3839 * @ret_seid: seid of create pv component
3841 * This instantiates an i40e port virtualizer with specified flags.
3842 * Depending on specified flags the port virtualizer can act as a
3843 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3845 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3846 u16 mac_seid, u16 vsi_seid,
3849 struct i40e_aq_desc desc;
3850 struct i40e_aqc_add_update_pv *cmd =
3851 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3852 struct i40e_aqc_add_update_pv_completion *resp =
3853 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3854 enum i40e_status_code status;
3857 return I40E_ERR_PARAM;
3859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3860 cmd->command_flags = CPU_TO_LE16(flags);
3861 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3862 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3864 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3865 if (!status && ret_seid)
3866 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3872 * i40e_aq_add_tag - Add an S/E-tag
3873 * @hw: pointer to the hw struct
3874 * @direct_to_queue: should s-tag direct flow to a specific queue
3875 * @vsi_seid: VSI SEID to use this tag
3876 * @tag: value of the tag
3877 * @queue_num: queue number, only valid is direct_to_queue is true
3878 * @tags_used: return value, number of tags in use by this PF
3879 * @tags_free: return value, number of unallocated tags
3880 * @cmd_details: pointer to command details structure or NULL
3882 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3883 * the number of tags allocated by the PF, and the number of unallocated
3886 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
3887 u16 vsi_seid, u16 tag, u16 queue_num,
3888 u16 *tags_used, u16 *tags_free,
3889 struct i40e_asq_cmd_details *cmd_details)
3891 struct i40e_aq_desc desc;
3892 struct i40e_aqc_add_tag *cmd =
3893 (struct i40e_aqc_add_tag *)&desc.params.raw;
3894 struct i40e_aqc_add_remove_tag_completion *resp =
3895 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3896 enum i40e_status_code status;
3899 return I40E_ERR_PARAM;
3901 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
3903 cmd->seid = CPU_TO_LE16(vsi_seid);
3904 cmd->tag = CPU_TO_LE16(tag);
3905 if (direct_to_queue) {
3906 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
3907 cmd->queue_number = CPU_TO_LE16(queue_num);
3910 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3913 if (tags_used != NULL)
3914 *tags_used = LE16_TO_CPU(resp->tags_used);
3915 if (tags_free != NULL)
3916 *tags_free = LE16_TO_CPU(resp->tags_free);
3923 * i40e_aq_remove_tag - Remove an S- or E-tag
3924 * @hw: pointer to the hw struct
3925 * @vsi_seid: VSI SEID this tag is associated with
3926 * @tag: value of the S-tag to delete
3927 * @tags_used: return value, number of tags in use by this PF
3928 * @tags_free: return value, number of unallocated tags
3929 * @cmd_details: pointer to command details structure or NULL
3931 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
3932 * the number of tags allocated by the PF, and the number of unallocated
3935 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
3936 u16 tag, u16 *tags_used, u16 *tags_free,
3937 struct i40e_asq_cmd_details *cmd_details)
3939 struct i40e_aq_desc desc;
3940 struct i40e_aqc_remove_tag *cmd =
3941 (struct i40e_aqc_remove_tag *)&desc.params.raw;
3942 struct i40e_aqc_add_remove_tag_completion *resp =
3943 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
3944 enum i40e_status_code status;
3947 return I40E_ERR_PARAM;
3949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
3951 cmd->seid = CPU_TO_LE16(vsi_seid);
3952 cmd->tag = CPU_TO_LE16(tag);
3954 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3957 if (tags_used != NULL)
3958 *tags_used = LE16_TO_CPU(resp->tags_used);
3959 if (tags_free != NULL)
3960 *tags_free = LE16_TO_CPU(resp->tags_free);
3967 * i40e_aq_add_mcast_etag - Add a multicast E-tag
3968 * @hw: pointer to the hw struct
3969 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
3970 * @etag: value of E-tag to add
3971 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
3972 * @buf: address of indirect buffer
3973 * @tags_used: return value, number of E-tags in use by this port
3974 * @tags_free: return value, number of unallocated M-tags
3975 * @cmd_details: pointer to command details structure or NULL
3977 * This associates a multicast E-tag to a port virtualizer. It will return
3978 * the number of tags allocated by the PF, and the number of unallocated
3981 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
3982 * num_tags_in_buf long.
3984 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
3985 u16 etag, u8 num_tags_in_buf, void *buf,
3986 u16 *tags_used, u16 *tags_free,
3987 struct i40e_asq_cmd_details *cmd_details)
3989 struct i40e_aq_desc desc;
3990 struct i40e_aqc_add_remove_mcast_etag *cmd =
3991 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
3992 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
3993 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
3994 enum i40e_status_code status;
3995 u16 length = sizeof(u16) * num_tags_in_buf;
3997 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
3998 return I40E_ERR_PARAM;
4000 i40e_fill_default_direct_cmd_desc(&desc,
4001 i40e_aqc_opc_add_multicast_etag);
4003 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4004 cmd->etag = CPU_TO_LE16(etag);
4005 cmd->num_unicast_etags = num_tags_in_buf;
4007 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4008 if (length > I40E_AQ_LARGE_BUF)
4009 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4011 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4014 if (tags_used != NULL)
4015 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4016 if (tags_free != NULL)
4017 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4024 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4025 * @hw: pointer to the hw struct
4026 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4027 * @etag: value of the E-tag to remove
4028 * @tags_used: return value, number of tags in use by this port
4029 * @tags_free: return value, number of unallocated tags
4030 * @cmd_details: pointer to command details structure or NULL
4032 * This deletes an E-tag from the port virtualizer. It will return
4033 * the number of tags allocated by the port, and the number of unallocated
4036 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4037 u16 etag, u16 *tags_used, u16 *tags_free,
4038 struct i40e_asq_cmd_details *cmd_details)
4040 struct i40e_aq_desc desc;
4041 struct i40e_aqc_add_remove_mcast_etag *cmd =
4042 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4043 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4044 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4045 enum i40e_status_code status;
4049 return I40E_ERR_PARAM;
4051 i40e_fill_default_direct_cmd_desc(&desc,
4052 i40e_aqc_opc_remove_multicast_etag);
4054 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4055 cmd->etag = CPU_TO_LE16(etag);
4057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4060 if (tags_used != NULL)
4061 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4062 if (tags_free != NULL)
4063 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4070 * i40e_aq_update_tag - Update an S/E-tag
4071 * @hw: pointer to the hw struct
4072 * @vsi_seid: VSI SEID using this S-tag
4073 * @old_tag: old tag value
4074 * @new_tag: new tag value
4075 * @tags_used: return value, number of tags in use by this PF
4076 * @tags_free: return value, number of unallocated tags
4077 * @cmd_details: pointer to command details structure or NULL
4079 * This updates the value of the tag currently attached to this VSI
4080 * in the switch complex. It will return the number of tags allocated
4081 * by the PF, and the number of unallocated tags available.
4083 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4084 u16 old_tag, u16 new_tag, u16 *tags_used,
4086 struct i40e_asq_cmd_details *cmd_details)
4088 struct i40e_aq_desc desc;
4089 struct i40e_aqc_update_tag *cmd =
4090 (struct i40e_aqc_update_tag *)&desc.params.raw;
4091 struct i40e_aqc_update_tag_completion *resp =
4092 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4093 enum i40e_status_code status;
4096 return I40E_ERR_PARAM;
4098 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4100 cmd->seid = CPU_TO_LE16(vsi_seid);
4101 cmd->old_tag = CPU_TO_LE16(old_tag);
4102 cmd->new_tag = CPU_TO_LE16(new_tag);
4104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4107 if (tags_used != NULL)
4108 *tags_used = LE16_TO_CPU(resp->tags_used);
4109 if (tags_free != NULL)
4110 *tags_free = LE16_TO_CPU(resp->tags_free);
4117 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4118 * @hw: pointer to the hw struct
4119 * @tcmap: TC map for request/release any ignore PFC condition
4120 * @request: request or release ignore PFC condition
4121 * @tcmap_ret: return TCs for which PFC is currently ignored
4122 * @cmd_details: pointer to command details structure or NULL
4124 * This sends out request/release to ignore PFC condition for a TC.
4125 * It will return the TCs for which PFC is currently ignored.
4127 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4128 bool request, u8 *tcmap_ret,
4129 struct i40e_asq_cmd_details *cmd_details)
4131 struct i40e_aq_desc desc;
4132 struct i40e_aqc_pfc_ignore *cmd_resp =
4133 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4134 enum i40e_status_code status;
4136 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4139 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4141 cmd_resp->tc_bitmap = tcmap;
4143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4146 if (tcmap_ret != NULL)
4147 *tcmap_ret = cmd_resp->tc_bitmap;
4154 * i40e_aq_dcb_updated - DCB Updated Command
4155 * @hw: pointer to the hw struct
4156 * @cmd_details: pointer to command details structure or NULL
4158 * When LLDP is handled in PF this command is used by the PF
4159 * to notify EMP that a DCB setting is modified.
4160 * When LLDP is handled in EMP this command is used by the PF
4161 * to notify EMP whenever one of the following parameters get
4163 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4164 * - PCIRTT in PRTDCB_GENC.PCIRTT
4165 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4166 * EMP will return when the shared RPB settings have been
4167 * recomputed and modified. The retval field in the descriptor
4168 * will be set to 0 when RPB is modified.
4170 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4171 struct i40e_asq_cmd_details *cmd_details)
4173 struct i40e_aq_desc desc;
4174 enum i40e_status_code status;
4176 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4178 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4184 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4185 * @hw: pointer to the hw struct
4186 * @seid: defines the SEID of the switch for which the stats are requested
4187 * @vlan_id: the VLAN ID for which the statistics are requested
4188 * @stat_index: index of the statistics counters block assigned to this VLAN
4189 * @cmd_details: pointer to command details structure or NULL
4191 * XL710 supports 128 smonVlanStats counters.This command is used to
4192 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4195 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4196 u16 vlan_id, u16 *stat_index,
4197 struct i40e_asq_cmd_details *cmd_details)
4199 struct i40e_aq_desc desc;
4200 struct i40e_aqc_add_remove_statistics *cmd_resp =
4201 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4202 enum i40e_status_code status;
4204 if ((seid == 0) || (stat_index == NULL))
4205 return I40E_ERR_PARAM;
4207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4209 cmd_resp->seid = CPU_TO_LE16(seid);
4210 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4214 if (!status && stat_index)
4215 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4221 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4222 * @hw: pointer to the hw struct
4223 * @seid: defines the SEID of the switch for which the stats are requested
4224 * @vlan_id: the VLAN ID for which the statistics are requested
4225 * @stat_index: index of the statistics counters block assigned to this VLAN
4226 * @cmd_details: pointer to command details structure or NULL
4228 * XL710 supports 128 smonVlanStats counters.This command is used to
4229 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4232 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4233 u16 vlan_id, u16 stat_index,
4234 struct i40e_asq_cmd_details *cmd_details)
4236 struct i40e_aq_desc desc;
4237 struct i40e_aqc_add_remove_statistics *cmd =
4238 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4239 enum i40e_status_code status;
4242 return I40E_ERR_PARAM;
4244 i40e_fill_default_direct_cmd_desc(&desc,
4245 i40e_aqc_opc_remove_statistics);
4247 cmd->seid = CPU_TO_LE16(seid);
4248 cmd->vlan = CPU_TO_LE16(vlan_id);
4249 cmd->stat_index = CPU_TO_LE16(stat_index);
4251 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4257 * i40e_aq_set_port_parameters - set physical port parameters.
4258 * @hw: pointer to the hw struct
4259 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4260 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4261 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4262 * @double_vlan: if set double VLAN is enabled
4263 * @cmd_details: pointer to command details structure or NULL
4265 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4266 u16 bad_frame_vsi, bool save_bad_pac,
4267 bool pad_short_pac, bool double_vlan,
4268 struct i40e_asq_cmd_details *cmd_details)
4270 struct i40e_aqc_set_port_parameters *cmd;
4271 enum i40e_status_code status;
4272 struct i40e_aq_desc desc;
4273 u16 command_flags = 0;
4275 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4277 i40e_fill_default_direct_cmd_desc(&desc,
4278 i40e_aqc_opc_set_port_parameters);
4280 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4282 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4284 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4286 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4287 cmd->command_flags = CPU_TO_LE16(command_flags);
4289 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4295 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4296 * @hw: pointer to the hw struct
4297 * @seid: seid for the physical port/switching component/vsi
4298 * @buff: Indirect buffer to hold data parameters and response
4299 * @buff_size: Indirect buffer size
4300 * @opcode: Tx scheduler AQ command opcode
4301 * @cmd_details: pointer to command details structure or NULL
4303 * Generic command handler for Tx scheduler AQ commands
4305 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4306 void *buff, u16 buff_size,
4307 enum i40e_admin_queue_opc opcode,
4308 struct i40e_asq_cmd_details *cmd_details)
4310 struct i40e_aq_desc desc;
4311 struct i40e_aqc_tx_sched_ind *cmd =
4312 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4313 enum i40e_status_code status;
4314 bool cmd_param_flag = false;
4317 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4318 case i40e_aqc_opc_configure_vsi_tc_bw:
4319 case i40e_aqc_opc_enable_switching_comp_ets:
4320 case i40e_aqc_opc_modify_switching_comp_ets:
4321 case i40e_aqc_opc_disable_switching_comp_ets:
4322 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4323 case i40e_aqc_opc_configure_switching_comp_bw_config:
4324 cmd_param_flag = true;
4326 case i40e_aqc_opc_query_vsi_bw_config:
4327 case i40e_aqc_opc_query_vsi_ets_sla_config:
4328 case i40e_aqc_opc_query_switching_comp_ets_config:
4329 case i40e_aqc_opc_query_port_ets_config:
4330 case i40e_aqc_opc_query_switching_comp_bw_config:
4331 cmd_param_flag = false;
4334 return I40E_ERR_PARAM;
4337 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4339 /* Indirect command */
4340 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4342 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4343 if (buff_size > I40E_AQ_LARGE_BUF)
4344 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4346 desc.datalen = CPU_TO_LE16(buff_size);
4348 cmd->vsi_seid = CPU_TO_LE16(seid);
4350 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4356 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4357 * @hw: pointer to the hw struct
4359 * @credit: BW limit credits (0 = disabled)
4360 * @max_credit: Max BW limit credits
4361 * @cmd_details: pointer to command details structure or NULL
4363 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4364 u16 seid, u16 credit, u8 max_credit,
4365 struct i40e_asq_cmd_details *cmd_details)
4367 struct i40e_aq_desc desc;
4368 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4369 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4370 enum i40e_status_code status;
4372 i40e_fill_default_direct_cmd_desc(&desc,
4373 i40e_aqc_opc_configure_vsi_bw_limit);
4375 cmd->vsi_seid = CPU_TO_LE16(seid);
4376 cmd->credit = CPU_TO_LE16(credit);
4377 cmd->max_credit = max_credit;
4379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4385 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4386 * @hw: pointer to the hw struct
4387 * @seid: switching component seid
4388 * @credit: BW limit credits (0 = disabled)
4389 * @max_bw: Max BW limit credits
4390 * @cmd_details: pointer to command details structure or NULL
4392 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4393 u16 seid, u16 credit, u8 max_bw,
4394 struct i40e_asq_cmd_details *cmd_details)
4396 struct i40e_aq_desc desc;
4397 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4398 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4399 enum i40e_status_code status;
4401 i40e_fill_default_direct_cmd_desc(&desc,
4402 i40e_aqc_opc_configure_switching_comp_bw_limit);
4404 cmd->seid = CPU_TO_LE16(seid);
4405 cmd->credit = CPU_TO_LE16(credit);
4406 cmd->max_bw = max_bw;
4408 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4414 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4415 * @hw: pointer to the hw struct
4417 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4418 * @cmd_details: pointer to command details structure or NULL
4420 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4422 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4423 struct i40e_asq_cmd_details *cmd_details)
4425 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4426 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4431 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4432 * @hw: pointer to the hw struct
4434 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4435 * @cmd_details: pointer to command details structure or NULL
4437 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4439 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4440 struct i40e_asq_cmd_details *cmd_details)
4442 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4443 i40e_aqc_opc_configure_vsi_tc_bw,
4448 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4449 * @hw: pointer to the hw struct
4450 * @seid: seid of the switching component
4451 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4452 * @cmd_details: pointer to command details structure or NULL
4454 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4455 struct i40e_hw *hw, u16 seid,
4456 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4457 struct i40e_asq_cmd_details *cmd_details)
4459 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4460 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4465 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4466 * @hw: pointer to the hw struct
4467 * @seid: seid of the VSI
4468 * @bw_data: Buffer to hold VSI BW configuration
4469 * @cmd_details: pointer to command details structure or NULL
4471 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4473 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4474 struct i40e_asq_cmd_details *cmd_details)
4476 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4477 i40e_aqc_opc_query_vsi_bw_config,
4482 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4483 * @hw: pointer to the hw struct
4484 * @seid: seid of the VSI
4485 * @bw_data: Buffer to hold VSI BW configuration per TC
4486 * @cmd_details: pointer to command details structure or NULL
4488 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4490 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4491 struct i40e_asq_cmd_details *cmd_details)
4493 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4494 i40e_aqc_opc_query_vsi_ets_sla_config,
4499 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4500 * @hw: pointer to the hw struct
4501 * @seid: seid of the switching component
4502 * @bw_data: Buffer to hold switching component's per TC BW config
4503 * @cmd_details: pointer to command details structure or NULL
4505 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4507 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4508 struct i40e_asq_cmd_details *cmd_details)
4510 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4511 i40e_aqc_opc_query_switching_comp_ets_config,
4516 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4517 * @hw: pointer to the hw struct
4518 * @seid: seid of the VSI or switching component connected to Physical Port
4519 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4520 * @cmd_details: pointer to command details structure or NULL
4522 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4524 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4525 struct i40e_asq_cmd_details *cmd_details)
4527 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4528 i40e_aqc_opc_query_port_ets_config,
4533 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4534 * @hw: pointer to the hw struct
4535 * @seid: seid of the switching component
4536 * @bw_data: Buffer to hold switching component's BW configuration
4537 * @cmd_details: pointer to command details structure or NULL
4539 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4541 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4542 struct i40e_asq_cmd_details *cmd_details)
4544 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4545 i40e_aqc_opc_query_switching_comp_bw_config,
4550 * i40e_validate_filter_settings
4551 * @hw: pointer to the hardware structure
4552 * @settings: Filter control settings
4554 * Check and validate the filter control settings passed.
4555 * The function checks for the valid filter/context sizes being
4556 * passed for FCoE and PE.
4558 * Returns I40E_SUCCESS if the values passed are valid and within
4559 * range else returns an error.
4561 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4562 struct i40e_filter_control_settings *settings)
4564 u32 fcoe_cntx_size, fcoe_filt_size;
4565 u32 pe_cntx_size, pe_filt_size;
4570 /* Validate FCoE settings passed */
4571 switch (settings->fcoe_filt_num) {
4572 case I40E_HASH_FILTER_SIZE_1K:
4573 case I40E_HASH_FILTER_SIZE_2K:
4574 case I40E_HASH_FILTER_SIZE_4K:
4575 case I40E_HASH_FILTER_SIZE_8K:
4576 case I40E_HASH_FILTER_SIZE_16K:
4577 case I40E_HASH_FILTER_SIZE_32K:
4578 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4579 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4582 return I40E_ERR_PARAM;
4585 switch (settings->fcoe_cntx_num) {
4586 case I40E_DMA_CNTX_SIZE_512:
4587 case I40E_DMA_CNTX_SIZE_1K:
4588 case I40E_DMA_CNTX_SIZE_2K:
4589 case I40E_DMA_CNTX_SIZE_4K:
4590 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4591 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4594 return I40E_ERR_PARAM;
4597 /* Validate PE settings passed */
4598 switch (settings->pe_filt_num) {
4599 case I40E_HASH_FILTER_SIZE_1K:
4600 case I40E_HASH_FILTER_SIZE_2K:
4601 case I40E_HASH_FILTER_SIZE_4K:
4602 case I40E_HASH_FILTER_SIZE_8K:
4603 case I40E_HASH_FILTER_SIZE_16K:
4604 case I40E_HASH_FILTER_SIZE_32K:
4605 case I40E_HASH_FILTER_SIZE_64K:
4606 case I40E_HASH_FILTER_SIZE_128K:
4607 case I40E_HASH_FILTER_SIZE_256K:
4608 case I40E_HASH_FILTER_SIZE_512K:
4609 case I40E_HASH_FILTER_SIZE_1M:
4610 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4611 pe_filt_size <<= (u32)settings->pe_filt_num;
4614 return I40E_ERR_PARAM;
4617 switch (settings->pe_cntx_num) {
4618 case I40E_DMA_CNTX_SIZE_512:
4619 case I40E_DMA_CNTX_SIZE_1K:
4620 case I40E_DMA_CNTX_SIZE_2K:
4621 case I40E_DMA_CNTX_SIZE_4K:
4622 case I40E_DMA_CNTX_SIZE_8K:
4623 case I40E_DMA_CNTX_SIZE_16K:
4624 case I40E_DMA_CNTX_SIZE_32K:
4625 case I40E_DMA_CNTX_SIZE_64K:
4626 case I40E_DMA_CNTX_SIZE_128K:
4627 case I40E_DMA_CNTX_SIZE_256K:
4628 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4629 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4632 return I40E_ERR_PARAM;
4635 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4636 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4637 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4638 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4639 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4640 return I40E_ERR_INVALID_SIZE;
4642 return I40E_SUCCESS;
4646 * i40e_set_filter_control
4647 * @hw: pointer to the hardware structure
4648 * @settings: Filter control settings
4650 * Set the Queue Filters for PE/FCoE and enable filters required
4651 * for a single PF. It is expected that these settings are programmed
4652 * at the driver initialization time.
4654 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4655 struct i40e_filter_control_settings *settings)
4657 enum i40e_status_code ret = I40E_SUCCESS;
4658 u32 hash_lut_size = 0;
4662 return I40E_ERR_PARAM;
4664 /* Validate the input settings */
4665 ret = i40e_validate_filter_settings(hw, settings);
4669 /* Read the PF Queue Filter control register */
4670 val = rd32(hw, I40E_PFQF_CTL_0);
4672 /* Program required PE hash buckets for the PF */
4673 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4674 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4675 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4676 /* Program required PE contexts for the PF */
4677 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4678 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4679 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4681 /* Program required FCoE hash buckets for the PF */
4682 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4683 val |= ((u32)settings->fcoe_filt_num <<
4684 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4685 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4686 /* Program required FCoE DDP contexts for the PF */
4687 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4688 val |= ((u32)settings->fcoe_cntx_num <<
4689 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4690 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4692 /* Program Hash LUT size for the PF */
4693 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4694 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4696 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4697 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4699 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4700 if (settings->enable_fdir)
4701 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4702 if (settings->enable_ethtype)
4703 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4704 if (settings->enable_macvlan)
4705 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4707 wr32(hw, I40E_PFQF_CTL_0, val);
4709 return I40E_SUCCESS;
4713 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4714 * @hw: pointer to the hw struct
4715 * @mac_addr: MAC address to use in the filter
4716 * @ethtype: Ethertype to use in the filter
4717 * @flags: Flags that needs to be applied to the filter
4718 * @vsi_seid: seid of the control VSI
4719 * @queue: VSI queue number to send the packet to
4720 * @is_add: Add control packet filter if True else remove
4721 * @stats: Structure to hold information on control filter counts
4722 * @cmd_details: pointer to command details structure or NULL
4724 * This command will Add or Remove control packet filter for a control VSI.
4725 * In return it will update the total number of perfect filter count in
4728 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4729 u8 *mac_addr, u16 ethtype, u16 flags,
4730 u16 vsi_seid, u16 queue, bool is_add,
4731 struct i40e_control_filter_stats *stats,
4732 struct i40e_asq_cmd_details *cmd_details)
4734 struct i40e_aq_desc desc;
4735 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4736 (struct i40e_aqc_add_remove_control_packet_filter *)
4738 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4739 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4741 enum i40e_status_code status;
4744 return I40E_ERR_PARAM;
4747 i40e_fill_default_direct_cmd_desc(&desc,
4748 i40e_aqc_opc_add_control_packet_filter);
4749 cmd->queue = CPU_TO_LE16(queue);
4751 i40e_fill_default_direct_cmd_desc(&desc,
4752 i40e_aqc_opc_remove_control_packet_filter);
4756 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4757 I40E_NONDMA_TO_NONDMA);
4759 cmd->etype = CPU_TO_LE16(ethtype);
4760 cmd->flags = CPU_TO_LE16(flags);
4761 cmd->seid = CPU_TO_LE16(vsi_seid);
4763 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4765 if (!status && stats) {
4766 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4767 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4768 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4769 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4776 * i40e_aq_add_cloud_filters
4777 * @hw: pointer to the hardware structure
4778 * @seid: VSI seid to add cloud filters from
4779 * @filters: Buffer which contains the filters to be added
4780 * @filter_count: number of filters contained in the buffer
4782 * Set the cloud filters for a given VSI. The contents of the
4783 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4784 * in by the caller of the function.
4787 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4789 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4792 struct i40e_aq_desc desc;
4793 struct i40e_aqc_add_remove_cloud_filters *cmd =
4794 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4796 enum i40e_status_code status;
4798 i40e_fill_default_direct_cmd_desc(&desc,
4799 i40e_aqc_opc_add_cloud_filters);
4801 buff_len = filter_count * sizeof(*filters);
4802 desc.datalen = CPU_TO_LE16(buff_len);
4803 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4804 cmd->num_filters = filter_count;
4805 cmd->seid = CPU_TO_LE16(seid);
4807 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4813 * i40e_aq_remove_cloud_filters
4814 * @hw: pointer to the hardware structure
4815 * @seid: VSI seid to remove cloud filters from
4816 * @filters: Buffer which contains the filters to be removed
4817 * @filter_count: number of filters contained in the buffer
4819 * Remove the cloud filters for a given VSI. The contents of the
4820 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4821 * in by the caller of the function.
4824 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4826 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4829 struct i40e_aq_desc desc;
4830 struct i40e_aqc_add_remove_cloud_filters *cmd =
4831 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4832 enum i40e_status_code status;
4835 i40e_fill_default_direct_cmd_desc(&desc,
4836 i40e_aqc_opc_remove_cloud_filters);
4838 buff_len = filter_count * sizeof(*filters);
4839 desc.datalen = CPU_TO_LE16(buff_len);
4840 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4841 cmd->num_filters = filter_count;
4842 cmd->seid = CPU_TO_LE16(seid);
4844 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4850 * i40e_aq_alternate_write
4851 * @hw: pointer to the hardware structure
4852 * @reg_addr0: address of first dword to be read
4853 * @reg_val0: value to be written under 'reg_addr0'
4854 * @reg_addr1: address of second dword to be read
4855 * @reg_val1: value to be written under 'reg_addr1'
4857 * Write one or two dwords to alternate structure. Fields are indicated
4858 * by 'reg_addr0' and 'reg_addr1' register numbers.
4861 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
4862 u32 reg_addr0, u32 reg_val0,
4863 u32 reg_addr1, u32 reg_val1)
4865 struct i40e_aq_desc desc;
4866 struct i40e_aqc_alternate_write *cmd_resp =
4867 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4868 enum i40e_status_code status;
4870 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
4871 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4872 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4873 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
4874 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
4876 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4882 * i40e_aq_alternate_write_indirect
4883 * @hw: pointer to the hardware structure
4884 * @addr: address of a first register to be modified
4885 * @dw_count: number of alternate structure fields to write
4886 * @buffer: pointer to the command buffer
4888 * Write 'dw_count' dwords from 'buffer' to alternate structure
4889 * starting at 'addr'.
4892 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
4893 u32 addr, u32 dw_count, void *buffer)
4895 struct i40e_aq_desc desc;
4896 struct i40e_aqc_alternate_ind_write *cmd_resp =
4897 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4898 enum i40e_status_code status;
4901 return I40E_ERR_PARAM;
4903 /* Indirect command */
4904 i40e_fill_default_direct_cmd_desc(&desc,
4905 i40e_aqc_opc_alternate_write_indirect);
4907 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4908 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4909 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4910 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4912 cmd_resp->address = CPU_TO_LE32(addr);
4913 cmd_resp->length = CPU_TO_LE32(dw_count);
4914 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
4915 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
4917 status = i40e_asq_send_command(hw, &desc, buffer,
4918 I40E_LO_DWORD(4*dw_count), NULL);
4924 * i40e_aq_alternate_read
4925 * @hw: pointer to the hardware structure
4926 * @reg_addr0: address of first dword to be read
4927 * @reg_val0: pointer for data read from 'reg_addr0'
4928 * @reg_addr1: address of second dword to be read
4929 * @reg_val1: pointer for data read from 'reg_addr1'
4931 * Read one or two dwords from alternate structure. Fields are indicated
4932 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4933 * is not passed then only register at 'reg_addr0' is read.
4936 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
4937 u32 reg_addr0, u32 *reg_val0,
4938 u32 reg_addr1, u32 *reg_val1)
4940 struct i40e_aq_desc desc;
4941 struct i40e_aqc_alternate_write *cmd_resp =
4942 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4943 enum i40e_status_code status;
4945 if (reg_val0 == NULL)
4946 return I40E_ERR_PARAM;
4948 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4949 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
4950 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
4952 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4954 if (status == I40E_SUCCESS) {
4955 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
4957 if (reg_val1 != NULL)
4958 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
4965 * i40e_aq_alternate_read_indirect
4966 * @hw: pointer to the hardware structure
4967 * @addr: address of the alternate structure field
4968 * @dw_count: number of alternate structure fields to read
4969 * @buffer: pointer to the command buffer
4971 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
4972 * place them in 'buffer'. The buffer should be allocated by caller.
4975 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
4976 u32 addr, u32 dw_count, void *buffer)
4978 struct i40e_aq_desc desc;
4979 struct i40e_aqc_alternate_ind_write *cmd_resp =
4980 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
4981 enum i40e_status_code status;
4984 return I40E_ERR_PARAM;
4986 /* Indirect command */
4987 i40e_fill_default_direct_cmd_desc(&desc,
4988 i40e_aqc_opc_alternate_read_indirect);
4990 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
4991 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
4992 if (dw_count > (I40E_AQ_LARGE_BUF/4))
4993 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4995 cmd_resp->address = CPU_TO_LE32(addr);
4996 cmd_resp->length = CPU_TO_LE32(dw_count);
4997 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
4998 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5000 status = i40e_asq_send_command(hw, &desc, buffer,
5001 I40E_LO_DWORD(4*dw_count), NULL);
5007 * i40e_aq_alternate_clear
5008 * @hw: pointer to the HW structure.
5010 * Clear the alternate structures of the port from which the function
5014 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5016 struct i40e_aq_desc desc;
5017 enum i40e_status_code status;
5019 i40e_fill_default_direct_cmd_desc(&desc,
5020 i40e_aqc_opc_alternate_clear_port);
5022 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5028 * i40e_aq_alternate_write_done
5029 * @hw: pointer to the HW structure.
5030 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5031 * @reset_needed: indicates the SW should trigger GLOBAL reset
5033 * Indicates to the FW that alternate structures have been changed.
5036 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5037 u8 bios_mode, bool *reset_needed)
5039 struct i40e_aq_desc desc;
5040 struct i40e_aqc_alternate_write_done *cmd =
5041 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5042 enum i40e_status_code status;
5044 if (reset_needed == NULL)
5045 return I40E_ERR_PARAM;
5047 i40e_fill_default_direct_cmd_desc(&desc,
5048 i40e_aqc_opc_alternate_write_done);
5050 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5052 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5053 if (!status && reset_needed)
5054 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5055 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5061 * i40e_aq_set_oem_mode
5062 * @hw: pointer to the HW structure.
5063 * @oem_mode: the OEM mode to be used
5065 * Sets the device to a specific operating mode. Currently the only supported
5066 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5069 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5072 struct i40e_aq_desc desc;
5073 struct i40e_aqc_alternate_write_done *cmd =
5074 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5075 enum i40e_status_code status;
5077 i40e_fill_default_direct_cmd_desc(&desc,
5078 i40e_aqc_opc_alternate_set_mode);
5080 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5082 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5088 * i40e_aq_resume_port_tx
5089 * @hw: pointer to the hardware structure
5090 * @cmd_details: pointer to command details structure or NULL
5092 * Resume port's Tx traffic
5094 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5095 struct i40e_asq_cmd_details *cmd_details)
5097 struct i40e_aq_desc desc;
5098 enum i40e_status_code status;
5100 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5102 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5108 * i40e_set_pci_config_data - store PCI bus info
5109 * @hw: pointer to hardware structure
5110 * @link_status: the link status word from PCI config space
5112 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5114 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5116 hw->bus.type = i40e_bus_type_pci_express;
5118 switch (link_status & I40E_PCI_LINK_WIDTH) {
5119 case I40E_PCI_LINK_WIDTH_1:
5120 hw->bus.width = i40e_bus_width_pcie_x1;
5122 case I40E_PCI_LINK_WIDTH_2:
5123 hw->bus.width = i40e_bus_width_pcie_x2;
5125 case I40E_PCI_LINK_WIDTH_4:
5126 hw->bus.width = i40e_bus_width_pcie_x4;
5128 case I40E_PCI_LINK_WIDTH_8:
5129 hw->bus.width = i40e_bus_width_pcie_x8;
5132 hw->bus.width = i40e_bus_width_unknown;
5136 switch (link_status & I40E_PCI_LINK_SPEED) {
5137 case I40E_PCI_LINK_SPEED_2500:
5138 hw->bus.speed = i40e_bus_speed_2500;
5140 case I40E_PCI_LINK_SPEED_5000:
5141 hw->bus.speed = i40e_bus_speed_5000;
5143 case I40E_PCI_LINK_SPEED_8000:
5144 hw->bus.speed = i40e_bus_speed_8000;
5147 hw->bus.speed = i40e_bus_speed_unknown;
5153 * i40e_read_bw_from_alt_ram
5154 * @hw: pointer to the hardware structure
5155 * @max_bw: pointer for max_bw read
5156 * @min_bw: pointer for min_bw read
5157 * @min_valid: pointer for bool that is true if min_bw is a valid value
5158 * @max_valid: pointer for bool that is true if max_bw is a valid value
5160 * Read bw from the alternate ram for the given pf
5162 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5163 u32 *max_bw, u32 *min_bw,
5164 bool *min_valid, bool *max_valid)
5166 enum i40e_status_code status;
5167 u32 max_bw_addr, min_bw_addr;
5169 /* Calculate the address of the min/max bw registers */
5170 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5171 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5172 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5173 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5174 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5175 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5177 /* Read the bandwidths from alt ram */
5178 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5179 min_bw_addr, min_bw);
5181 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5186 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5195 * i40e_aq_configure_partition_bw
5196 * @hw: pointer to the hardware structure
5197 * @bw_data: Buffer holding valid pfs and bw limits
5198 * @cmd_details: pointer to command details
5200 * Configure partitions guaranteed/max bw
5202 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5203 struct i40e_aqc_configure_partition_bw_data *bw_data,
5204 struct i40e_asq_cmd_details *cmd_details)
5206 enum i40e_status_code status;
5207 struct i40e_aq_desc desc;
5208 u16 bwd_size = sizeof(*bw_data);
5210 i40e_fill_default_direct_cmd_desc(&desc,
5211 i40e_aqc_opc_configure_partition_bw);
5213 /* Indirect command */
5214 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5215 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5217 if (bwd_size > I40E_AQ_LARGE_BUF)
5218 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5220 desc.datalen = CPU_TO_LE16(bwd_size);
5222 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5226 #endif /* PF_DRIVER */
5230 * i40e_aq_send_msg_to_pf
5231 * @hw: pointer to the hardware structure
5232 * @v_opcode: opcodes for VF-PF communication
5233 * @v_retval: return error code
5234 * @msg: pointer to the msg buffer
5235 * @msglen: msg length
5236 * @cmd_details: pointer to command details
5238 * Send message to PF driver using admin queue. By default, this message
5239 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5240 * completion before returning.
5242 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5243 enum i40e_virtchnl_ops v_opcode,
5244 enum i40e_status_code v_retval,
5245 u8 *msg, u16 msglen,
5246 struct i40e_asq_cmd_details *cmd_details)
5248 struct i40e_aq_desc desc;
5249 struct i40e_asq_cmd_details details;
5250 enum i40e_status_code status;
5252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5253 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5254 desc.cookie_high = CPU_TO_LE32(v_opcode);
5255 desc.cookie_low = CPU_TO_LE32(v_retval);
5257 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5258 | I40E_AQ_FLAG_RD));
5259 if (msglen > I40E_AQ_LARGE_BUF)
5260 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5261 desc.datalen = CPU_TO_LE16(msglen);
5264 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5265 details.async = true;
5266 cmd_details = &details;
5268 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5269 msglen, cmd_details);
5274 * i40e_vf_parse_hw_config
5275 * @hw: pointer to the hardware structure
5276 * @msg: pointer to the virtual channel VF resource structure
5278 * Given a VF resource message from the PF, populate the hw struct
5279 * with appropriate information.
5281 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5282 struct i40e_virtchnl_vf_resource *msg)
5284 struct i40e_virtchnl_vsi_resource *vsi_res;
5287 vsi_res = &msg->vsi_res[0];
5289 hw->dev_caps.num_vsis = msg->num_vsis;
5290 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5291 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5292 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5293 hw->dev_caps.dcb = msg->vf_offload_flags &
5294 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5295 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5296 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5297 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5298 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5299 for (i = 0; i < msg->num_vsis; i++) {
5300 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5301 i40e_memcpy(hw->mac.perm_addr,
5302 vsi_res->default_mac_addr,
5303 I40E_ETH_LENGTH_OF_ADDRESS,
5304 I40E_NONDMA_TO_NONDMA);
5305 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5306 I40E_ETH_LENGTH_OF_ADDRESS,
5307 I40E_NONDMA_TO_NONDMA);
5315 * @hw: pointer to the hardware structure
5317 * Send a VF_RESET message to the PF. Does not wait for response from PF
5318 * as none will be forthcoming. Immediately after calling this function,
5319 * the admin queue should be shut down and (optionally) reinitialized.
5321 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5323 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5324 I40E_SUCCESS, NULL, 0, NULL);
5326 #endif /* VF_DRIVER */