1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 case I40E_DEV_ID_25G_B:
71 case I40E_DEV_ID_25G_SFP28:
72 hw->mac.type = I40E_MAC_XL710;
75 #ifdef X722_A0_SUPPORT
76 case I40E_DEV_ID_X722_A0:
78 case I40E_DEV_ID_KX_X722:
79 case I40E_DEV_ID_QSFP_X722:
80 case I40E_DEV_ID_SFP_X722:
81 case I40E_DEV_ID_1G_BASE_T_X722:
82 case I40E_DEV_ID_10G_BASE_T_X722:
83 case I40E_DEV_ID_SFP_I_X722:
84 case I40E_DEV_ID_QSFP_I_X722:
85 hw->mac.type = I40E_MAC_X722;
89 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
90 case I40E_DEV_ID_X722_VF:
91 case I40E_DEV_ID_X722_VF_HV:
92 #ifdef X722_A0_SUPPORT
93 case I40E_DEV_ID_X722_A0_VF:
95 hw->mac.type = I40E_MAC_X722_VF;
97 #endif /* INTEGRATED_VF || VF_DRIVER */
98 #endif /* X722_SUPPORT */
99 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
101 case I40E_DEV_ID_VF_HV:
102 hw->mac.type = I40E_MAC_VF;
106 hw->mac.type = I40E_MAC_GENERIC;
110 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
113 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
114 hw->mac.type, status);
118 #ifndef I40E_NDIS_SUPPORT
120 * i40e_aq_str - convert AQ err code to a string
121 * @hw: pointer to the HW structure
122 * @aq_err: the AQ error code to convert
124 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
129 case I40E_AQ_RC_EPERM:
130 return "I40E_AQ_RC_EPERM";
131 case I40E_AQ_RC_ENOENT:
132 return "I40E_AQ_RC_ENOENT";
133 case I40E_AQ_RC_ESRCH:
134 return "I40E_AQ_RC_ESRCH";
135 case I40E_AQ_RC_EINTR:
136 return "I40E_AQ_RC_EINTR";
138 return "I40E_AQ_RC_EIO";
139 case I40E_AQ_RC_ENXIO:
140 return "I40E_AQ_RC_ENXIO";
141 case I40E_AQ_RC_E2BIG:
142 return "I40E_AQ_RC_E2BIG";
143 case I40E_AQ_RC_EAGAIN:
144 return "I40E_AQ_RC_EAGAIN";
145 case I40E_AQ_RC_ENOMEM:
146 return "I40E_AQ_RC_ENOMEM";
147 case I40E_AQ_RC_EACCES:
148 return "I40E_AQ_RC_EACCES";
149 case I40E_AQ_RC_EFAULT:
150 return "I40E_AQ_RC_EFAULT";
151 case I40E_AQ_RC_EBUSY:
152 return "I40E_AQ_RC_EBUSY";
153 case I40E_AQ_RC_EEXIST:
154 return "I40E_AQ_RC_EEXIST";
155 case I40E_AQ_RC_EINVAL:
156 return "I40E_AQ_RC_EINVAL";
157 case I40E_AQ_RC_ENOTTY:
158 return "I40E_AQ_RC_ENOTTY";
159 case I40E_AQ_RC_ENOSPC:
160 return "I40E_AQ_RC_ENOSPC";
161 case I40E_AQ_RC_ENOSYS:
162 return "I40E_AQ_RC_ENOSYS";
163 case I40E_AQ_RC_ERANGE:
164 return "I40E_AQ_RC_ERANGE";
165 case I40E_AQ_RC_EFLUSHED:
166 return "I40E_AQ_RC_EFLUSHED";
167 case I40E_AQ_RC_BAD_ADDR:
168 return "I40E_AQ_RC_BAD_ADDR";
169 case I40E_AQ_RC_EMODE:
170 return "I40E_AQ_RC_EMODE";
171 case I40E_AQ_RC_EFBIG:
172 return "I40E_AQ_RC_EFBIG";
175 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
180 * i40e_stat_str - convert status err code to a string
181 * @hw: pointer to the HW structure
182 * @stat_err: the status error code to convert
184 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
190 return "I40E_ERR_NVM";
191 case I40E_ERR_NVM_CHECKSUM:
192 return "I40E_ERR_NVM_CHECKSUM";
194 return "I40E_ERR_PHY";
195 case I40E_ERR_CONFIG:
196 return "I40E_ERR_CONFIG";
198 return "I40E_ERR_PARAM";
199 case I40E_ERR_MAC_TYPE:
200 return "I40E_ERR_MAC_TYPE";
201 case I40E_ERR_UNKNOWN_PHY:
202 return "I40E_ERR_UNKNOWN_PHY";
203 case I40E_ERR_LINK_SETUP:
204 return "I40E_ERR_LINK_SETUP";
205 case I40E_ERR_ADAPTER_STOPPED:
206 return "I40E_ERR_ADAPTER_STOPPED";
207 case I40E_ERR_INVALID_MAC_ADDR:
208 return "I40E_ERR_INVALID_MAC_ADDR";
209 case I40E_ERR_DEVICE_NOT_SUPPORTED:
210 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
211 case I40E_ERR_MASTER_REQUESTS_PENDING:
212 return "I40E_ERR_MASTER_REQUESTS_PENDING";
213 case I40E_ERR_INVALID_LINK_SETTINGS:
214 return "I40E_ERR_INVALID_LINK_SETTINGS";
215 case I40E_ERR_AUTONEG_NOT_COMPLETE:
216 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
217 case I40E_ERR_RESET_FAILED:
218 return "I40E_ERR_RESET_FAILED";
219 case I40E_ERR_SWFW_SYNC:
220 return "I40E_ERR_SWFW_SYNC";
221 case I40E_ERR_NO_AVAILABLE_VSI:
222 return "I40E_ERR_NO_AVAILABLE_VSI";
223 case I40E_ERR_NO_MEMORY:
224 return "I40E_ERR_NO_MEMORY";
225 case I40E_ERR_BAD_PTR:
226 return "I40E_ERR_BAD_PTR";
227 case I40E_ERR_RING_FULL:
228 return "I40E_ERR_RING_FULL";
229 case I40E_ERR_INVALID_PD_ID:
230 return "I40E_ERR_INVALID_PD_ID";
231 case I40E_ERR_INVALID_QP_ID:
232 return "I40E_ERR_INVALID_QP_ID";
233 case I40E_ERR_INVALID_CQ_ID:
234 return "I40E_ERR_INVALID_CQ_ID";
235 case I40E_ERR_INVALID_CEQ_ID:
236 return "I40E_ERR_INVALID_CEQ_ID";
237 case I40E_ERR_INVALID_AEQ_ID:
238 return "I40E_ERR_INVALID_AEQ_ID";
239 case I40E_ERR_INVALID_SIZE:
240 return "I40E_ERR_INVALID_SIZE";
241 case I40E_ERR_INVALID_ARP_INDEX:
242 return "I40E_ERR_INVALID_ARP_INDEX";
243 case I40E_ERR_INVALID_FPM_FUNC_ID:
244 return "I40E_ERR_INVALID_FPM_FUNC_ID";
245 case I40E_ERR_QP_INVALID_MSG_SIZE:
246 return "I40E_ERR_QP_INVALID_MSG_SIZE";
247 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
248 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
249 case I40E_ERR_INVALID_FRAG_COUNT:
250 return "I40E_ERR_INVALID_FRAG_COUNT";
251 case I40E_ERR_QUEUE_EMPTY:
252 return "I40E_ERR_QUEUE_EMPTY";
253 case I40E_ERR_INVALID_ALIGNMENT:
254 return "I40E_ERR_INVALID_ALIGNMENT";
255 case I40E_ERR_FLUSHED_QUEUE:
256 return "I40E_ERR_FLUSHED_QUEUE";
257 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
258 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
259 case I40E_ERR_INVALID_IMM_DATA_SIZE:
260 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
261 case I40E_ERR_TIMEOUT:
262 return "I40E_ERR_TIMEOUT";
263 case I40E_ERR_OPCODE_MISMATCH:
264 return "I40E_ERR_OPCODE_MISMATCH";
265 case I40E_ERR_CQP_COMPL_ERROR:
266 return "I40E_ERR_CQP_COMPL_ERROR";
267 case I40E_ERR_INVALID_VF_ID:
268 return "I40E_ERR_INVALID_VF_ID";
269 case I40E_ERR_INVALID_HMCFN_ID:
270 return "I40E_ERR_INVALID_HMCFN_ID";
271 case I40E_ERR_BACKING_PAGE_ERROR:
272 return "I40E_ERR_BACKING_PAGE_ERROR";
273 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
274 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
275 case I40E_ERR_INVALID_PBLE_INDEX:
276 return "I40E_ERR_INVALID_PBLE_INDEX";
277 case I40E_ERR_INVALID_SD_INDEX:
278 return "I40E_ERR_INVALID_SD_INDEX";
279 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
280 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
281 case I40E_ERR_INVALID_SD_TYPE:
282 return "I40E_ERR_INVALID_SD_TYPE";
283 case I40E_ERR_MEMCPY_FAILED:
284 return "I40E_ERR_MEMCPY_FAILED";
285 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
286 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
287 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
288 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
289 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
290 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
291 case I40E_ERR_SRQ_ENABLED:
292 return "I40E_ERR_SRQ_ENABLED";
293 case I40E_ERR_ADMIN_QUEUE_ERROR:
294 return "I40E_ERR_ADMIN_QUEUE_ERROR";
295 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
296 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
297 case I40E_ERR_BUF_TOO_SHORT:
298 return "I40E_ERR_BUF_TOO_SHORT";
299 case I40E_ERR_ADMIN_QUEUE_FULL:
300 return "I40E_ERR_ADMIN_QUEUE_FULL";
301 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
302 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
303 case I40E_ERR_BAD_IWARP_CQE:
304 return "I40E_ERR_BAD_IWARP_CQE";
305 case I40E_ERR_NVM_BLANK_MODE:
306 return "I40E_ERR_NVM_BLANK_MODE";
307 case I40E_ERR_NOT_IMPLEMENTED:
308 return "I40E_ERR_NOT_IMPLEMENTED";
309 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
310 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
311 case I40E_ERR_DIAG_TEST_FAILED:
312 return "I40E_ERR_DIAG_TEST_FAILED";
313 case I40E_ERR_NOT_READY:
314 return "I40E_ERR_NOT_READY";
315 case I40E_NOT_SUPPORTED:
316 return "I40E_NOT_SUPPORTED";
317 case I40E_ERR_FIRMWARE_API_VERSION:
318 return "I40E_ERR_FIRMWARE_API_VERSION";
321 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
325 #endif /* I40E_NDIS_SUPPORT */
328 * @hw: debug mask related to admin queue
330 * @desc: pointer to admin queue descriptor
331 * @buffer: pointer to command buffer
332 * @buf_len: max length of buffer
334 * Dumps debug log about adminq command with descriptor contents.
336 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
337 void *buffer, u16 buf_len)
339 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
340 u16 len = LE16_TO_CPU(aq_desc->datalen);
341 u8 *buf = (u8 *)buffer;
344 if ((!(mask & hw->debug_mask)) || (desc == NULL))
348 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
349 LE16_TO_CPU(aq_desc->opcode),
350 LE16_TO_CPU(aq_desc->flags),
351 LE16_TO_CPU(aq_desc->datalen),
352 LE16_TO_CPU(aq_desc->retval));
353 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
354 LE32_TO_CPU(aq_desc->cookie_high),
355 LE32_TO_CPU(aq_desc->cookie_low));
356 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
357 LE32_TO_CPU(aq_desc->params.internal.param0),
358 LE32_TO_CPU(aq_desc->params.internal.param1));
359 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
360 LE32_TO_CPU(aq_desc->params.external.addr_high),
361 LE32_TO_CPU(aq_desc->params.external.addr_low));
363 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
364 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
367 /* write the full 16-byte chunks */
368 for (i = 0; i < (len - 16); i += 16)
370 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
371 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
372 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
373 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
374 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
375 /* the most we could have left is 16 bytes, pad with zeros */
380 memset(d_buf, 0, sizeof(d_buf));
381 for (j = 0; i < len; j++, i++)
384 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
385 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
386 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
387 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
388 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
394 * i40e_check_asq_alive
395 * @hw: pointer to the hw struct
397 * Returns true if Queue is enabled else false.
399 bool i40e_check_asq_alive(struct i40e_hw *hw)
405 return !!(rd32(hw, hw->aq.asq.len) &
406 I40E_PF_ATQLEN_ATQENABLE_MASK);
408 return !!(rd32(hw, hw->aq.asq.len) &
409 I40E_PF_ATQLEN_ATQENABLE_MASK);
410 #endif /* INTEGRATED_VF */
411 #endif /* PF_DRIVER */
415 return !!(rd32(hw, hw->aq.asq.len) &
416 I40E_VF_ATQLEN1_ATQENABLE_MASK);
418 return !!(rd32(hw, hw->aq.asq.len) &
419 I40E_VF_ATQLEN1_ATQENABLE_MASK);
420 #endif /* INTEGRATED_VF */
421 #endif /* VF_DRIVER */
426 * i40e_aq_queue_shutdown
427 * @hw: pointer to the hw struct
428 * @unloading: is the driver unloading itself
430 * Tell the Firmware that we're shutting down the AdminQ and whether
431 * or not the driver is unloading as well.
433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
436 struct i40e_aq_desc desc;
437 struct i40e_aqc_queue_shutdown *cmd =
438 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
439 enum i40e_status_code status;
441 i40e_fill_default_direct_cmd_desc(&desc,
442 i40e_aqc_opc_queue_shutdown);
445 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
446 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
453 * i40e_aq_get_set_rss_lut
454 * @hw: pointer to the hardware structure
455 * @vsi_id: vsi fw index
456 * @pf_lut: for PF table set true, for VSI table set false
457 * @lut: pointer to the lut buffer provided by the caller
458 * @lut_size: size of the lut buffer
459 * @set: set true to set the table, false to get the table
461 * Internal function to get or set RSS look up table
463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
464 u16 vsi_id, bool pf_lut,
465 u8 *lut, u16 lut_size,
468 enum i40e_status_code status;
469 struct i40e_aq_desc desc;
470 struct i40e_aqc_get_set_rss_lut *cmd_resp =
471 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
474 i40e_fill_default_direct_cmd_desc(&desc,
475 i40e_aqc_opc_set_rss_lut);
477 i40e_fill_default_direct_cmd_desc(&desc,
478 i40e_aqc_opc_get_rss_lut);
480 /* Indirect command */
481 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
482 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
485 CPU_TO_LE16((u16)((vsi_id <<
486 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
488 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
491 cmd_resp->flags |= CPU_TO_LE16((u16)
492 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
493 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
496 cmd_resp->flags |= CPU_TO_LE16((u16)
497 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
498 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
499 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
501 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
507 * i40e_aq_get_rss_lut
508 * @hw: pointer to the hardware structure
509 * @vsi_id: vsi fw index
510 * @pf_lut: for PF table set true, for VSI table set false
511 * @lut: pointer to the lut buffer provided by the caller
512 * @lut_size: size of the lut buffer
514 * get the RSS lookup table, PF or VSI type
516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
517 bool pf_lut, u8 *lut, u16 lut_size)
519 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
524 * i40e_aq_set_rss_lut
525 * @hw: pointer to the hardware structure
526 * @vsi_id: vsi fw index
527 * @pf_lut: for PF table set true, for VSI table set false
528 * @lut: pointer to the lut buffer provided by the caller
529 * @lut_size: size of the lut buffer
531 * set the RSS lookup table, PF or VSI type
533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
534 bool pf_lut, u8 *lut, u16 lut_size)
536 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
540 * i40e_aq_get_set_rss_key
541 * @hw: pointer to the hw struct
542 * @vsi_id: vsi fw index
543 * @key: pointer to key info struct
544 * @set: set true to set the key, false to get the key
546 * get the RSS key per VSI
548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
550 struct i40e_aqc_get_set_rss_key_data *key,
553 enum i40e_status_code status;
554 struct i40e_aq_desc desc;
555 struct i40e_aqc_get_set_rss_key *cmd_resp =
556 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
557 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
560 i40e_fill_default_direct_cmd_desc(&desc,
561 i40e_aqc_opc_set_rss_key);
563 i40e_fill_default_direct_cmd_desc(&desc,
564 i40e_aqc_opc_get_rss_key);
566 /* Indirect command */
567 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
568 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
571 CPU_TO_LE16((u16)((vsi_id <<
572 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
573 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
574 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
576 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
582 * i40e_aq_get_rss_key
583 * @hw: pointer to the hw struct
584 * @vsi_id: vsi fw index
585 * @key: pointer to key info struct
588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
590 struct i40e_aqc_get_set_rss_key_data *key)
592 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
596 * i40e_aq_set_rss_key
597 * @hw: pointer to the hw struct
598 * @vsi_id: vsi fw index
599 * @key: pointer to key info struct
601 * set the RSS key per VSI
603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
605 struct i40e_aqc_get_set_rss_key_data *key)
607 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
609 #endif /* X722_SUPPORT */
611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
612 * hardware to a bit-field that can be used by SW to more easily determine the
615 * Macros are used to shorten the table lines and make this table human
618 * We store the PTYPE in the top byte of the bit field - this is just so that
619 * we can check that the table doesn't have a row missing, as the index into
620 * the table should be the PTYPE.
624 * IF NOT i40e_ptype_lookup[ptype].known
627 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
628 * Use the rest of the fields to look at the tunnels, inner protocols, etc
630 * Use the enum i40e_rx_l2_ptype to decode the packet type
634 /* macro to make the table lines short */
635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
638 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
639 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
640 I40E_RX_PTYPE_##OUTER_FRAG, \
641 I40E_RX_PTYPE_TUNNEL_##T, \
642 I40E_RX_PTYPE_TUNNEL_END_##TE, \
643 I40E_RX_PTYPE_##TEF, \
644 I40E_RX_PTYPE_INNER_PROT_##I, \
645 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
648 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
650 /* shorter macros makes the table fit but are terse */
651 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
652 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
653 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
657 /* L2 Packet types */
658 I40E_PTT_UNUSED_ENTRY(0),
659 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
660 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
661 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(4),
663 I40E_PTT_UNUSED_ENTRY(5),
664 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
666 I40E_PTT_UNUSED_ENTRY(8),
667 I40E_PTT_UNUSED_ENTRY(9),
668 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
669 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
670 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
676 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
678 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
681 /* Non Tunneled IPv4 */
682 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
683 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
684 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
685 I40E_PTT_UNUSED_ENTRY(25),
686 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
687 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
688 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
691 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
692 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
693 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
694 I40E_PTT_UNUSED_ENTRY(32),
695 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
696 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
697 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
700 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
701 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
702 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(39),
704 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
705 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
706 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
708 /* IPv4 --> GRE/NAT */
709 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
711 /* IPv4 --> GRE/NAT --> IPv4 */
712 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
713 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
714 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
715 I40E_PTT_UNUSED_ENTRY(47),
716 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
717 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
718 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
720 /* IPv4 --> GRE/NAT --> IPv6 */
721 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
722 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
723 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(54),
725 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
726 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
727 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
729 /* IPv4 --> GRE/NAT --> MAC */
730 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
732 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
733 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
734 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
735 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
736 I40E_PTT_UNUSED_ENTRY(62),
737 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
738 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
739 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
741 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
742 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
743 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
744 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(69),
746 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
747 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
748 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
750 /* IPv4 --> GRE/NAT --> MAC/VLAN */
751 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
753 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
754 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
755 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
756 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
757 I40E_PTT_UNUSED_ENTRY(77),
758 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
759 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
760 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
762 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
763 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
764 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
765 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(84),
767 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
768 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
769 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
771 /* Non Tunneled IPv6 */
772 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
773 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
774 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
775 I40E_PTT_UNUSED_ENTRY(91),
776 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
777 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
778 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
781 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
782 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
783 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
784 I40E_PTT_UNUSED_ENTRY(98),
785 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
786 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
787 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
790 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
791 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
792 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(105),
794 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
795 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
796 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
798 /* IPv6 --> GRE/NAT */
799 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
801 /* IPv6 --> GRE/NAT -> IPv4 */
802 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
803 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
804 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
805 I40E_PTT_UNUSED_ENTRY(113),
806 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
807 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
808 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
810 /* IPv6 --> GRE/NAT -> IPv6 */
811 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
812 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
813 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(120),
815 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
816 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
817 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
819 /* IPv6 --> GRE/NAT -> MAC */
820 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
822 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
823 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
824 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
825 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
826 I40E_PTT_UNUSED_ENTRY(128),
827 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
828 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
829 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
831 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
832 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
833 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
834 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(135),
836 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
837 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
838 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
840 /* IPv6 --> GRE/NAT -> MAC/VLAN */
841 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
843 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
844 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
845 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
846 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
847 I40E_PTT_UNUSED_ENTRY(143),
848 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
849 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
850 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
852 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
853 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
854 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
855 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
856 I40E_PTT_UNUSED_ENTRY(150),
857 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
858 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
859 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
862 I40E_PTT_UNUSED_ENTRY(154),
863 I40E_PTT_UNUSED_ENTRY(155),
864 I40E_PTT_UNUSED_ENTRY(156),
865 I40E_PTT_UNUSED_ENTRY(157),
866 I40E_PTT_UNUSED_ENTRY(158),
867 I40E_PTT_UNUSED_ENTRY(159),
869 I40E_PTT_UNUSED_ENTRY(160),
870 I40E_PTT_UNUSED_ENTRY(161),
871 I40E_PTT_UNUSED_ENTRY(162),
872 I40E_PTT_UNUSED_ENTRY(163),
873 I40E_PTT_UNUSED_ENTRY(164),
874 I40E_PTT_UNUSED_ENTRY(165),
875 I40E_PTT_UNUSED_ENTRY(166),
876 I40E_PTT_UNUSED_ENTRY(167),
877 I40E_PTT_UNUSED_ENTRY(168),
878 I40E_PTT_UNUSED_ENTRY(169),
880 I40E_PTT_UNUSED_ENTRY(170),
881 I40E_PTT_UNUSED_ENTRY(171),
882 I40E_PTT_UNUSED_ENTRY(172),
883 I40E_PTT_UNUSED_ENTRY(173),
884 I40E_PTT_UNUSED_ENTRY(174),
885 I40E_PTT_UNUSED_ENTRY(175),
886 I40E_PTT_UNUSED_ENTRY(176),
887 I40E_PTT_UNUSED_ENTRY(177),
888 I40E_PTT_UNUSED_ENTRY(178),
889 I40E_PTT_UNUSED_ENTRY(179),
891 I40E_PTT_UNUSED_ENTRY(180),
892 I40E_PTT_UNUSED_ENTRY(181),
893 I40E_PTT_UNUSED_ENTRY(182),
894 I40E_PTT_UNUSED_ENTRY(183),
895 I40E_PTT_UNUSED_ENTRY(184),
896 I40E_PTT_UNUSED_ENTRY(185),
897 I40E_PTT_UNUSED_ENTRY(186),
898 I40E_PTT_UNUSED_ENTRY(187),
899 I40E_PTT_UNUSED_ENTRY(188),
900 I40E_PTT_UNUSED_ENTRY(189),
902 I40E_PTT_UNUSED_ENTRY(190),
903 I40E_PTT_UNUSED_ENTRY(191),
904 I40E_PTT_UNUSED_ENTRY(192),
905 I40E_PTT_UNUSED_ENTRY(193),
906 I40E_PTT_UNUSED_ENTRY(194),
907 I40E_PTT_UNUSED_ENTRY(195),
908 I40E_PTT_UNUSED_ENTRY(196),
909 I40E_PTT_UNUSED_ENTRY(197),
910 I40E_PTT_UNUSED_ENTRY(198),
911 I40E_PTT_UNUSED_ENTRY(199),
913 I40E_PTT_UNUSED_ENTRY(200),
914 I40E_PTT_UNUSED_ENTRY(201),
915 I40E_PTT_UNUSED_ENTRY(202),
916 I40E_PTT_UNUSED_ENTRY(203),
917 I40E_PTT_UNUSED_ENTRY(204),
918 I40E_PTT_UNUSED_ENTRY(205),
919 I40E_PTT_UNUSED_ENTRY(206),
920 I40E_PTT_UNUSED_ENTRY(207),
921 I40E_PTT_UNUSED_ENTRY(208),
922 I40E_PTT_UNUSED_ENTRY(209),
924 I40E_PTT_UNUSED_ENTRY(210),
925 I40E_PTT_UNUSED_ENTRY(211),
926 I40E_PTT_UNUSED_ENTRY(212),
927 I40E_PTT_UNUSED_ENTRY(213),
928 I40E_PTT_UNUSED_ENTRY(214),
929 I40E_PTT_UNUSED_ENTRY(215),
930 I40E_PTT_UNUSED_ENTRY(216),
931 I40E_PTT_UNUSED_ENTRY(217),
932 I40E_PTT_UNUSED_ENTRY(218),
933 I40E_PTT_UNUSED_ENTRY(219),
935 I40E_PTT_UNUSED_ENTRY(220),
936 I40E_PTT_UNUSED_ENTRY(221),
937 I40E_PTT_UNUSED_ENTRY(222),
938 I40E_PTT_UNUSED_ENTRY(223),
939 I40E_PTT_UNUSED_ENTRY(224),
940 I40E_PTT_UNUSED_ENTRY(225),
941 I40E_PTT_UNUSED_ENTRY(226),
942 I40E_PTT_UNUSED_ENTRY(227),
943 I40E_PTT_UNUSED_ENTRY(228),
944 I40E_PTT_UNUSED_ENTRY(229),
946 I40E_PTT_UNUSED_ENTRY(230),
947 I40E_PTT_UNUSED_ENTRY(231),
948 I40E_PTT_UNUSED_ENTRY(232),
949 I40E_PTT_UNUSED_ENTRY(233),
950 I40E_PTT_UNUSED_ENTRY(234),
951 I40E_PTT_UNUSED_ENTRY(235),
952 I40E_PTT_UNUSED_ENTRY(236),
953 I40E_PTT_UNUSED_ENTRY(237),
954 I40E_PTT_UNUSED_ENTRY(238),
955 I40E_PTT_UNUSED_ENTRY(239),
957 I40E_PTT_UNUSED_ENTRY(240),
958 I40E_PTT_UNUSED_ENTRY(241),
959 I40E_PTT_UNUSED_ENTRY(242),
960 I40E_PTT_UNUSED_ENTRY(243),
961 I40E_PTT_UNUSED_ENTRY(244),
962 I40E_PTT_UNUSED_ENTRY(245),
963 I40E_PTT_UNUSED_ENTRY(246),
964 I40E_PTT_UNUSED_ENTRY(247),
965 I40E_PTT_UNUSED_ENTRY(248),
966 I40E_PTT_UNUSED_ENTRY(249),
968 I40E_PTT_UNUSED_ENTRY(250),
969 I40E_PTT_UNUSED_ENTRY(251),
970 I40E_PTT_UNUSED_ENTRY(252),
971 I40E_PTT_UNUSED_ENTRY(253),
972 I40E_PTT_UNUSED_ENTRY(254),
973 I40E_PTT_UNUSED_ENTRY(255)
978 * i40e_validate_mac_addr - Validate unicast MAC address
979 * @mac_addr: pointer to MAC address
981 * Tests a MAC address to ensure it is a valid Individual Address
983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
985 enum i40e_status_code status = I40E_SUCCESS;
987 DEBUGFUNC("i40e_validate_mac_addr");
989 /* Broadcast addresses ARE multicast addresses
990 * Make sure it is not a multicast address
991 * Reject the zero address
993 if (I40E_IS_MULTICAST(mac_addr) ||
994 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
995 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
996 status = I40E_ERR_INVALID_MAC_ADDR;
1003 * i40e_init_shared_code - Initialize the shared code
1004 * @hw: pointer to hardware structure
1006 * This assigns the MAC type and PHY code and inits the NVM.
1007 * Does not touch the hardware. This function must be called prior to any
1008 * other function in the shared code. The i40e_hw structure should be
1009 * memset to 0 prior to calling this function. The following fields in
1010 * hw structure should be filled in prior to calling this function:
1011 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012 * subsystem_vendor_id, and revision_id
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1016 enum i40e_status_code status = I40E_SUCCESS;
1017 u32 port, ari, func_rid;
1019 DEBUGFUNC("i40e_init_shared_code");
1021 i40e_set_mac_type(hw);
1023 switch (hw->mac.type) {
1024 case I40E_MAC_XL710:
1030 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1033 hw->phy.get_link_info = true;
1035 /* Determine port number and PF number*/
1036 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038 hw->port = (u8)port;
1039 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1043 hw->pf_id = (u8)(func_rid & 0xff);
1045 hw->pf_id = (u8)(func_rid & 0x7);
1048 if (hw->mac.type == I40E_MAC_X722)
1049 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1052 status = i40e_init_nvm(hw);
1057 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1058 * @hw: pointer to the hw struct
1059 * @flags: a return indicator of what addresses were added to the addr store
1060 * @addrs: the requestor's mac addr store
1061 * @cmd_details: pointer to command details structure or NULL
1063 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1065 struct i40e_aqc_mac_address_read_data *addrs,
1066 struct i40e_asq_cmd_details *cmd_details)
1068 struct i40e_aq_desc desc;
1069 struct i40e_aqc_mac_address_read *cmd_data =
1070 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1071 enum i40e_status_code status;
1073 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1074 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1076 status = i40e_asq_send_command(hw, &desc, addrs,
1077 sizeof(*addrs), cmd_details);
1078 *flags = LE16_TO_CPU(cmd_data->command_flags);
1084 * i40e_aq_mac_address_write - Change the MAC addresses
1085 * @hw: pointer to the hw struct
1086 * @flags: indicates which MAC to be written
1087 * @mac_addr: address to write
1088 * @cmd_details: pointer to command details structure or NULL
1090 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1091 u16 flags, u8 *mac_addr,
1092 struct i40e_asq_cmd_details *cmd_details)
1094 struct i40e_aq_desc desc;
1095 struct i40e_aqc_mac_address_write *cmd_data =
1096 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1097 enum i40e_status_code status;
1099 i40e_fill_default_direct_cmd_desc(&desc,
1100 i40e_aqc_opc_mac_address_write);
1101 cmd_data->command_flags = CPU_TO_LE16(flags);
1102 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1103 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1104 ((u32)mac_addr[3] << 16) |
1105 ((u32)mac_addr[4] << 8) |
1108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1114 * i40e_get_mac_addr - get MAC address
1115 * @hw: pointer to the HW structure
1116 * @mac_addr: pointer to MAC address
1118 * Reads the adapter's MAC address from register
1120 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1122 struct i40e_aqc_mac_address_read_data addrs;
1123 enum i40e_status_code status;
1126 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1128 if (flags & I40E_AQC_LAN_ADDR_VALID)
1129 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1135 * i40e_get_port_mac_addr - get Port MAC address
1136 * @hw: pointer to the HW structure
1137 * @mac_addr: pointer to Port MAC address
1139 * Reads the adapter's Port MAC address
1141 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 struct i40e_aqc_mac_address_read_data addrs;
1144 enum i40e_status_code status;
1147 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1151 if (flags & I40E_AQC_PORT_ADDR_VALID)
1152 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1154 status = I40E_ERR_INVALID_MAC_ADDR;
1160 * i40e_pre_tx_queue_cfg - pre tx queue configure
1161 * @hw: pointer to the HW structure
1162 * @queue: target pf queue index
1163 * @enable: state change request
1165 * Handles hw requirement to indicate intention to enable
1166 * or disable target queue.
1168 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1174 if (abs_queue_idx >= 128) {
1175 reg_block = abs_queue_idx / 128;
1176 abs_queue_idx %= 128;
1179 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1180 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1181 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1184 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1192 * i40e_read_pba_string - Reads part number string from EEPROM
1193 * @hw: pointer to hardware structure
1194 * @pba_num: stores the part number string from the EEPROM
1195 * @pba_num_size: part number string buffer length
1197 * Reads the part number string from the EEPROM.
1199 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1202 enum i40e_status_code status = I40E_SUCCESS;
1208 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1209 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1210 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1214 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1215 if (status != I40E_SUCCESS) {
1216 DEBUGOUT("Failed to read PBA Block pointer.\n");
1220 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1221 if (status != I40E_SUCCESS) {
1222 DEBUGOUT("Failed to read PBA Block size.\n");
1226 /* Subtract one to get PBA word count (PBA Size word is included in
1230 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1231 DEBUGOUT("Buffer to small for PBA data.\n");
1232 return I40E_ERR_PARAM;
1235 for (i = 0; i < pba_size; i++) {
1236 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1237 if (status != I40E_SUCCESS) {
1238 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1242 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1243 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1245 pba_num[(pba_size * 2)] = '\0';
1251 * i40e_get_media_type - Gets media type
1252 * @hw: pointer to the hardware structure
1254 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1256 enum i40e_media_type media;
1258 switch (hw->phy.link_info.phy_type) {
1259 case I40E_PHY_TYPE_10GBASE_SR:
1260 case I40E_PHY_TYPE_10GBASE_LR:
1261 case I40E_PHY_TYPE_1000BASE_SX:
1262 case I40E_PHY_TYPE_1000BASE_LX:
1263 case I40E_PHY_TYPE_40GBASE_SR4:
1264 case I40E_PHY_TYPE_40GBASE_LR4:
1265 media = I40E_MEDIA_TYPE_FIBER;
1267 case I40E_PHY_TYPE_100BASE_TX:
1268 case I40E_PHY_TYPE_1000BASE_T:
1269 case I40E_PHY_TYPE_10GBASE_T:
1270 media = I40E_MEDIA_TYPE_BASET;
1272 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1273 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1274 case I40E_PHY_TYPE_10GBASE_CR1:
1275 case I40E_PHY_TYPE_40GBASE_CR4:
1276 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1277 case I40E_PHY_TYPE_40GBASE_AOC:
1278 case I40E_PHY_TYPE_10GBASE_AOC:
1279 media = I40E_MEDIA_TYPE_DA;
1281 case I40E_PHY_TYPE_1000BASE_KX:
1282 case I40E_PHY_TYPE_10GBASE_KX4:
1283 case I40E_PHY_TYPE_10GBASE_KR:
1284 case I40E_PHY_TYPE_40GBASE_KR4:
1285 case I40E_PHY_TYPE_20GBASE_KR2:
1286 media = I40E_MEDIA_TYPE_BACKPLANE;
1288 case I40E_PHY_TYPE_SGMII:
1289 case I40E_PHY_TYPE_XAUI:
1290 case I40E_PHY_TYPE_XFI:
1291 case I40E_PHY_TYPE_XLAUI:
1292 case I40E_PHY_TYPE_XLPPI:
1294 media = I40E_MEDIA_TYPE_UNKNOWN;
1301 #define I40E_PF_RESET_WAIT_COUNT 200
1303 * i40e_pf_reset - Reset the PF
1304 * @hw: pointer to the hardware structure
1306 * Assuming someone else has triggered a global reset,
1307 * assure the global reset is complete and then reset the PF
1309 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1316 /* Poll for Global Reset steady state in case of recent GRST.
1317 * The grst delay value is in 100ms units, and we'll wait a
1318 * couple counts longer to be sure we don't just miss the end.
1320 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1321 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1322 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1324 grst_del = grst_del * 20;
1326 for (cnt = 0; cnt < grst_del; cnt++) {
1327 reg = rd32(hw, I40E_GLGEN_RSTAT);
1328 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1330 i40e_msec_delay(100);
1332 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1333 DEBUGOUT("Global reset polling failed to complete.\n");
1334 return I40E_ERR_RESET_FAILED;
1337 /* Now Wait for the FW to be ready */
1338 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1339 reg = rd32(hw, I40E_GLNVM_ULD);
1340 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1341 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1342 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1343 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1344 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1347 i40e_msec_delay(10);
1349 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1350 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1351 DEBUGOUT("wait for FW Reset complete timedout\n");
1352 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1353 return I40E_ERR_RESET_FAILED;
1356 /* If there was a Global Reset in progress when we got here,
1357 * we don't need to do the PF Reset
1360 reg = rd32(hw, I40E_PFGEN_CTRL);
1361 wr32(hw, I40E_PFGEN_CTRL,
1362 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1363 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1364 reg = rd32(hw, I40E_PFGEN_CTRL);
1365 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1369 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1370 DEBUGOUT("PF reset polling failed to complete.\n");
1371 return I40E_ERR_RESET_FAILED;
1375 i40e_clear_pxe_mode(hw);
1378 return I40E_SUCCESS;
1382 * i40e_clear_hw - clear out any left over hw state
1383 * @hw: pointer to the hw struct
1385 * Clear queues and interrupts, typically called at init time,
1386 * but after the capabilities have been found so we know how many
1387 * queues and msix vectors have been allocated.
1389 void i40e_clear_hw(struct i40e_hw *hw)
1391 u32 num_queues, base_queue;
1399 /* get number of interrupts, queues, and vfs */
1400 val = rd32(hw, I40E_GLPCI_CNF2);
1401 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1402 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1403 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1404 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1406 val = rd32(hw, I40E_PFLAN_QALLOC);
1407 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1408 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1409 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1410 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1411 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1412 num_queues = (j - base_queue) + 1;
1416 val = rd32(hw, I40E_PF_VT_PFALLOC);
1417 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1418 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1419 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1420 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1421 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1422 num_vfs = (j - i) + 1;
1426 /* stop all the interrupts */
1427 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1428 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1429 for (i = 0; i < num_pf_int - 2; i++)
1430 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1432 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1433 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1434 wr32(hw, I40E_PFINT_LNKLST0, val);
1435 for (i = 0; i < num_pf_int - 2; i++)
1436 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1437 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1438 for (i = 0; i < num_vfs; i++)
1439 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1440 for (i = 0; i < num_vf_int - 2; i++)
1441 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1443 /* warn the HW of the coming Tx disables */
1444 for (i = 0; i < num_queues; i++) {
1445 u32 abs_queue_idx = base_queue + i;
1448 if (abs_queue_idx >= 128) {
1449 reg_block = abs_queue_idx / 128;
1450 abs_queue_idx %= 128;
1453 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1454 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1455 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1456 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1458 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1460 i40e_usec_delay(400);
1462 /* stop all the queues */
1463 for (i = 0; i < num_queues; i++) {
1464 wr32(hw, I40E_QINT_TQCTL(i), 0);
1465 wr32(hw, I40E_QTX_ENA(i), 0);
1466 wr32(hw, I40E_QINT_RQCTL(i), 0);
1467 wr32(hw, I40E_QRX_ENA(i), 0);
1470 /* short wait for all queue disables to settle */
1471 i40e_usec_delay(50);
1475 * i40e_clear_pxe_mode - clear pxe operations mode
1476 * @hw: pointer to the hw struct
1478 * Make sure all PXE mode settings are cleared, including things
1479 * like descriptor fetch/write-back mode.
1481 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1483 if (i40e_check_asq_alive(hw))
1484 i40e_aq_clear_pxe_mode(hw, NULL);
1488 * i40e_led_is_mine - helper to find matching led
1489 * @hw: pointer to the hw struct
1490 * @idx: index into GPIO registers
1492 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1494 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1499 if (!hw->func_caps.led[idx])
1502 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1503 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1504 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1506 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1507 * if it is not our port then ignore
1509 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1516 #define I40E_COMBINED_ACTIVITY 0xA
1517 #define I40E_FILTER_ACTIVITY 0xE
1518 #define I40E_LINK_ACTIVITY 0xC
1519 #define I40E_MAC_ACTIVITY 0xD
1520 #define I40E_LED0 22
1523 * i40e_led_get - return current on/off mode
1524 * @hw: pointer to the hw struct
1526 * The value returned is the 'mode' field as defined in the
1527 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1528 * values are variations of possible behaviors relating to
1529 * blink, link, and wire.
1531 u32 i40e_led_get(struct i40e_hw *hw)
1533 u32 current_mode = 0;
1537 /* as per the documentation GPIO 22-29 are the LED
1538 * GPIO pins named LED0..LED7
1540 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1541 u32 gpio_val = i40e_led_is_mine(hw, i);
1546 /* ignore gpio LED src mode entries related to the activity
1549 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1550 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1551 switch (current_mode) {
1552 case I40E_COMBINED_ACTIVITY:
1553 case I40E_FILTER_ACTIVITY:
1554 case I40E_MAC_ACTIVITY:
1560 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1561 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1569 * i40e_led_set - set new on/off mode
1570 * @hw: pointer to the hw struct
1571 * @mode: 0=off, 0xf=on (else see manual for mode details)
1572 * @blink: true if the LED should blink when on, false if steady
1574 * if this function is used to turn on the blink it should
1575 * be used to disable the blink when restoring the original state.
1577 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1579 u32 current_mode = 0;
1582 if (mode & 0xfffffff0)
1583 DEBUGOUT1("invalid mode passed in %X\n", mode);
1585 /* as per the documentation GPIO 22-29 are the LED
1586 * GPIO pins named LED0..LED7
1588 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1589 u32 gpio_val = i40e_led_is_mine(hw, i);
1594 /* ignore gpio LED src mode entries related to the activity
1597 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1598 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1599 switch (current_mode) {
1600 case I40E_COMBINED_ACTIVITY:
1601 case I40E_FILTER_ACTIVITY:
1602 case I40E_MAC_ACTIVITY:
1608 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1609 /* this & is a bit of paranoia, but serves as a range check */
1610 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1611 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1613 if (mode == I40E_LINK_ACTIVITY)
1617 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1619 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1621 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1626 /* Admin command wrappers */
1629 * i40e_aq_get_phy_capabilities
1630 * @hw: pointer to the hw struct
1631 * @abilities: structure for PHY capabilities to be filled
1632 * @qualified_modules: report Qualified Modules
1633 * @report_init: report init capabilities (active are default)
1634 * @cmd_details: pointer to command details structure or NULL
1636 * Returns the various PHY abilities supported on the Port.
1638 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1639 bool qualified_modules, bool report_init,
1640 struct i40e_aq_get_phy_abilities_resp *abilities,
1641 struct i40e_asq_cmd_details *cmd_details)
1643 struct i40e_aq_desc desc;
1644 enum i40e_status_code status;
1645 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1648 return I40E_ERR_PARAM;
1650 i40e_fill_default_direct_cmd_desc(&desc,
1651 i40e_aqc_opc_get_phy_abilities);
1653 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1654 if (abilities_size > I40E_AQ_LARGE_BUF)
1655 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1657 if (qualified_modules)
1658 desc.params.external.param0 |=
1659 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1662 desc.params.external.param0 |=
1663 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1665 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1668 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1669 status = I40E_ERR_UNKNOWN_PHY;
1672 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1678 * i40e_aq_set_phy_config
1679 * @hw: pointer to the hw struct
1680 * @config: structure with PHY configuration to be set
1681 * @cmd_details: pointer to command details structure or NULL
1683 * Set the various PHY configuration parameters
1684 * supported on the Port.One or more of the Set PHY config parameters may be
1685 * ignored in an MFP mode as the PF may not have the privilege to set some
1686 * of the PHY Config parameters. This status will be indicated by the
1689 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1690 struct i40e_aq_set_phy_config *config,
1691 struct i40e_asq_cmd_details *cmd_details)
1693 struct i40e_aq_desc desc;
1694 struct i40e_aq_set_phy_config *cmd =
1695 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1696 enum i40e_status_code status;
1699 return I40E_ERR_PARAM;
1701 i40e_fill_default_direct_cmd_desc(&desc,
1702 i40e_aqc_opc_set_phy_config);
1706 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1713 * @hw: pointer to the hw struct
1715 * Set the requested flow control mode using set_phy_config.
1717 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1718 bool atomic_restart)
1720 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1721 struct i40e_aq_get_phy_abilities_resp abilities;
1722 struct i40e_aq_set_phy_config config;
1723 enum i40e_status_code status;
1724 u8 pause_mask = 0x0;
1730 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1731 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1733 case I40E_FC_RX_PAUSE:
1734 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1736 case I40E_FC_TX_PAUSE:
1737 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1743 /* Get the current phy config */
1744 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1747 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1751 memset(&config, 0, sizeof(config));
1752 /* clear the old pause settings */
1753 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1754 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1755 /* set the new abilities */
1756 config.abilities |= pause_mask;
1757 /* If the abilities have changed, then set the new config */
1758 if (config.abilities != abilities.abilities) {
1759 /* Auto restart link so settings take effect */
1761 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1762 /* Copy over all the old settings */
1763 config.phy_type = abilities.phy_type;
1764 config.link_speed = abilities.link_speed;
1765 config.eee_capability = abilities.eee_capability;
1766 config.eeer = abilities.eeer_val;
1767 config.low_power_ctrl = abilities.d3_lpan;
1768 status = i40e_aq_set_phy_config(hw, &config, NULL);
1771 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1773 /* Update the link info */
1774 status = i40e_update_link_info(hw);
1776 /* Wait a little bit (on 40G cards it sometimes takes a really
1777 * long time for link to come back from the atomic reset)
1780 i40e_msec_delay(1000);
1781 status = i40e_update_link_info(hw);
1784 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1790 * i40e_aq_set_mac_config
1791 * @hw: pointer to the hw struct
1792 * @max_frame_size: Maximum Frame Size to be supported by the port
1793 * @crc_en: Tell HW to append a CRC to outgoing frames
1794 * @pacing: Pacing configurations
1795 * @cmd_details: pointer to command details structure or NULL
1797 * Configure MAC settings for frame size, jumbo frame support and the
1798 * addition of a CRC by the hardware.
1800 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1802 bool crc_en, u16 pacing,
1803 struct i40e_asq_cmd_details *cmd_details)
1805 struct i40e_aq_desc desc;
1806 struct i40e_aq_set_mac_config *cmd =
1807 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1808 enum i40e_status_code status;
1810 if (max_frame_size == 0)
1811 return I40E_ERR_PARAM;
1813 i40e_fill_default_direct_cmd_desc(&desc,
1814 i40e_aqc_opc_set_mac_config);
1816 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1817 cmd->params = ((u8)pacing & 0x0F) << 3;
1819 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1821 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1827 * i40e_aq_clear_pxe_mode
1828 * @hw: pointer to the hw struct
1829 * @cmd_details: pointer to command details structure or NULL
1831 * Tell the firmware that the driver is taking over from PXE
1833 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1834 struct i40e_asq_cmd_details *cmd_details)
1836 enum i40e_status_code status;
1837 struct i40e_aq_desc desc;
1838 struct i40e_aqc_clear_pxe *cmd =
1839 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1841 i40e_fill_default_direct_cmd_desc(&desc,
1842 i40e_aqc_opc_clear_pxe_mode);
1846 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1848 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1854 * i40e_aq_set_link_restart_an
1855 * @hw: pointer to the hw struct
1856 * @enable_link: if true: enable link, if false: disable link
1857 * @cmd_details: pointer to command details structure or NULL
1859 * Sets up the link and restarts the Auto-Negotiation over the link.
1861 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1862 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1864 struct i40e_aq_desc desc;
1865 struct i40e_aqc_set_link_restart_an *cmd =
1866 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1867 enum i40e_status_code status;
1869 i40e_fill_default_direct_cmd_desc(&desc,
1870 i40e_aqc_opc_set_link_restart_an);
1872 cmd->command = I40E_AQ_PHY_RESTART_AN;
1874 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1876 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1878 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1884 * i40e_aq_get_link_info
1885 * @hw: pointer to the hw struct
1886 * @enable_lse: enable/disable LinkStatusEvent reporting
1887 * @link: pointer to link status structure - optional
1888 * @cmd_details: pointer to command details structure or NULL
1890 * Returns the link status of the adapter.
1892 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1893 bool enable_lse, struct i40e_link_status *link,
1894 struct i40e_asq_cmd_details *cmd_details)
1896 struct i40e_aq_desc desc;
1897 struct i40e_aqc_get_link_status *resp =
1898 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1899 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1900 enum i40e_status_code status;
1901 bool tx_pause, rx_pause;
1904 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1907 command_flags = I40E_AQ_LSE_ENABLE;
1909 command_flags = I40E_AQ_LSE_DISABLE;
1910 resp->command_flags = CPU_TO_LE16(command_flags);
1912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1914 if (status != I40E_SUCCESS)
1915 goto aq_get_link_info_exit;
1917 /* save off old link status information */
1918 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1919 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1921 /* update link status */
1922 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1923 hw->phy.media_type = i40e_get_media_type(hw);
1924 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1925 hw_link_info->link_info = resp->link_info;
1926 hw_link_info->an_info = resp->an_info;
1927 hw_link_info->ext_info = resp->ext_info;
1928 hw_link_info->loopback = resp->loopback;
1929 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1930 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1932 /* update fc info */
1933 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1934 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1935 if (tx_pause & rx_pause)
1936 hw->fc.current_mode = I40E_FC_FULL;
1938 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1940 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1942 hw->fc.current_mode = I40E_FC_NONE;
1944 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1945 hw_link_info->crc_enable = true;
1947 hw_link_info->crc_enable = false;
1949 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1950 hw_link_info->lse_enable = true;
1952 hw_link_info->lse_enable = false;
1954 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1955 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1956 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1958 /* save link status information */
1960 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1961 I40E_NONDMA_TO_NONDMA);
1963 /* flag cleared so helper functions don't call AQ again */
1964 hw->phy.get_link_info = false;
1966 aq_get_link_info_exit:
1971 * i40e_aq_set_phy_int_mask
1972 * @hw: pointer to the hw struct
1973 * @mask: interrupt mask to be set
1974 * @cmd_details: pointer to command details structure or NULL
1976 * Set link interrupt mask.
1978 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1980 struct i40e_asq_cmd_details *cmd_details)
1982 struct i40e_aq_desc desc;
1983 struct i40e_aqc_set_phy_int_mask *cmd =
1984 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1985 enum i40e_status_code status;
1987 i40e_fill_default_direct_cmd_desc(&desc,
1988 i40e_aqc_opc_set_phy_int_mask);
1990 cmd->event_mask = CPU_TO_LE16(mask);
1992 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1998 * i40e_aq_get_local_advt_reg
1999 * @hw: pointer to the hw struct
2000 * @advt_reg: local AN advertisement register value
2001 * @cmd_details: pointer to command details structure or NULL
2003 * Get the Local AN advertisement register value.
2005 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2007 struct i40e_asq_cmd_details *cmd_details)
2009 struct i40e_aq_desc desc;
2010 struct i40e_aqc_an_advt_reg *resp =
2011 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2012 enum i40e_status_code status;
2014 i40e_fill_default_direct_cmd_desc(&desc,
2015 i40e_aqc_opc_get_local_advt_reg);
2017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2019 if (status != I40E_SUCCESS)
2020 goto aq_get_local_advt_reg_exit;
2022 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2023 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2025 aq_get_local_advt_reg_exit:
2030 * i40e_aq_set_local_advt_reg
2031 * @hw: pointer to the hw struct
2032 * @advt_reg: local AN advertisement register value
2033 * @cmd_details: pointer to command details structure or NULL
2035 * Get the Local AN advertisement register value.
2037 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2039 struct i40e_asq_cmd_details *cmd_details)
2041 struct i40e_aq_desc desc;
2042 struct i40e_aqc_an_advt_reg *cmd =
2043 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2044 enum i40e_status_code status;
2046 i40e_fill_default_direct_cmd_desc(&desc,
2047 i40e_aqc_opc_get_local_advt_reg);
2049 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2050 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2052 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2058 * i40e_aq_get_partner_advt
2059 * @hw: pointer to the hw struct
2060 * @advt_reg: AN partner advertisement register value
2061 * @cmd_details: pointer to command details structure or NULL
2063 * Get the link partner AN advertisement register value.
2065 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2067 struct i40e_asq_cmd_details *cmd_details)
2069 struct i40e_aq_desc desc;
2070 struct i40e_aqc_an_advt_reg *resp =
2071 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2072 enum i40e_status_code status;
2074 i40e_fill_default_direct_cmd_desc(&desc,
2075 i40e_aqc_opc_get_partner_advt);
2077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2079 if (status != I40E_SUCCESS)
2080 goto aq_get_partner_advt_exit;
2082 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2083 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2085 aq_get_partner_advt_exit:
2090 * i40e_aq_set_lb_modes
2091 * @hw: pointer to the hw struct
2092 * @lb_modes: loopback mode to be set
2093 * @cmd_details: pointer to command details structure or NULL
2095 * Sets loopback modes.
2097 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2099 struct i40e_asq_cmd_details *cmd_details)
2101 struct i40e_aq_desc desc;
2102 struct i40e_aqc_set_lb_mode *cmd =
2103 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2104 enum i40e_status_code status;
2106 i40e_fill_default_direct_cmd_desc(&desc,
2107 i40e_aqc_opc_set_lb_modes);
2109 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2111 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2117 * i40e_aq_set_phy_debug
2118 * @hw: pointer to the hw struct
2119 * @cmd_flags: debug command flags
2120 * @cmd_details: pointer to command details structure or NULL
2122 * Reset the external PHY.
2124 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2125 struct i40e_asq_cmd_details *cmd_details)
2127 struct i40e_aq_desc desc;
2128 struct i40e_aqc_set_phy_debug *cmd =
2129 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2130 enum i40e_status_code status;
2132 i40e_fill_default_direct_cmd_desc(&desc,
2133 i40e_aqc_opc_set_phy_debug);
2135 cmd->command_flags = cmd_flags;
2137 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2144 * @hw: pointer to the hw struct
2145 * @vsi_ctx: pointer to a vsi context struct
2146 * @cmd_details: pointer to command details structure or NULL
2148 * Add a VSI context to the hardware.
2150 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2151 struct i40e_vsi_context *vsi_ctx,
2152 struct i40e_asq_cmd_details *cmd_details)
2154 struct i40e_aq_desc desc;
2155 struct i40e_aqc_add_get_update_vsi *cmd =
2156 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2157 struct i40e_aqc_add_get_update_vsi_completion *resp =
2158 (struct i40e_aqc_add_get_update_vsi_completion *)
2160 enum i40e_status_code status;
2162 i40e_fill_default_direct_cmd_desc(&desc,
2163 i40e_aqc_opc_add_vsi);
2165 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2166 cmd->connection_type = vsi_ctx->connection_type;
2167 cmd->vf_id = vsi_ctx->vf_num;
2168 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2170 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2172 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2173 sizeof(vsi_ctx->info), cmd_details);
2175 if (status != I40E_SUCCESS)
2176 goto aq_add_vsi_exit;
2178 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2179 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2180 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2181 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2188 * i40e_aq_set_default_vsi
2189 * @hw: pointer to the hw struct
2191 * @cmd_details: pointer to command details structure or NULL
2193 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2195 struct i40e_asq_cmd_details *cmd_details)
2197 struct i40e_aq_desc desc;
2198 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2199 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2201 enum i40e_status_code status;
2203 i40e_fill_default_direct_cmd_desc(&desc,
2204 i40e_aqc_opc_set_vsi_promiscuous_modes);
2206 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2207 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2208 cmd->seid = CPU_TO_LE16(seid);
2210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2216 * i40e_aq_set_vsi_unicast_promiscuous
2217 * @hw: pointer to the hw struct
2219 * @set: set unicast promiscuous enable/disable
2220 * @cmd_details: pointer to command details structure or NULL
2221 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2223 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2225 struct i40e_asq_cmd_details *cmd_details,
2226 bool rx_only_promisc)
2228 struct i40e_aq_desc desc;
2229 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2230 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2231 enum i40e_status_code status;
2234 i40e_fill_default_direct_cmd_desc(&desc,
2235 i40e_aqc_opc_set_vsi_promiscuous_modes);
2238 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2239 if (rx_only_promisc &&
2240 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2241 (hw->aq.api_maj_ver > 1)))
2242 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2245 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2247 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2248 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2249 (hw->aq.api_maj_ver > 1))
2250 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2252 cmd->seid = CPU_TO_LE16(seid);
2253 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2259 * i40e_aq_set_vsi_multicast_promiscuous
2260 * @hw: pointer to the hw struct
2262 * @set: set multicast promiscuous enable/disable
2263 * @cmd_details: pointer to command details structure or NULL
2265 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2266 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2268 struct i40e_aq_desc desc;
2269 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2270 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2271 enum i40e_status_code status;
2274 i40e_fill_default_direct_cmd_desc(&desc,
2275 i40e_aqc_opc_set_vsi_promiscuous_modes);
2278 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2280 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2282 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2284 cmd->seid = CPU_TO_LE16(seid);
2285 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2291 * i40e_aq_set_vsi_mc_promisc_on_vlan
2292 * @hw: pointer to the hw struct
2294 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2295 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2296 * @cmd_details: pointer to command details structure or NULL
2298 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2299 u16 seid, bool enable, u16 vid,
2300 struct i40e_asq_cmd_details *cmd_details)
2302 struct i40e_aq_desc desc;
2303 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2304 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2305 enum i40e_status_code status;
2308 i40e_fill_default_direct_cmd_desc(&desc,
2309 i40e_aqc_opc_set_vsi_promiscuous_modes);
2312 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2314 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2315 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2316 cmd->seid = CPU_TO_LE16(seid);
2317 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2319 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2325 * i40e_aq_set_vsi_uc_promisc_on_vlan
2326 * @hw: pointer to the hw struct
2328 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2329 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2330 * @cmd_details: pointer to command details structure or NULL
2332 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2333 u16 seid, bool enable, u16 vid,
2334 struct i40e_asq_cmd_details *cmd_details)
2336 struct i40e_aq_desc desc;
2337 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2338 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2339 enum i40e_status_code status;
2342 i40e_fill_default_direct_cmd_desc(&desc,
2343 i40e_aqc_opc_set_vsi_promiscuous_modes);
2346 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2348 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2349 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2350 cmd->seid = CPU_TO_LE16(seid);
2351 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2353 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2359 * i40e_aq_set_vsi_broadcast
2360 * @hw: pointer to the hw struct
2362 * @set_filter: true to set filter, false to clear filter
2363 * @cmd_details: pointer to command details structure or NULL
2365 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2367 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2368 u16 seid, bool set_filter,
2369 struct i40e_asq_cmd_details *cmd_details)
2371 struct i40e_aq_desc desc;
2372 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2373 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2374 enum i40e_status_code status;
2376 i40e_fill_default_direct_cmd_desc(&desc,
2377 i40e_aqc_opc_set_vsi_promiscuous_modes);
2380 cmd->promiscuous_flags
2381 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2383 cmd->promiscuous_flags
2384 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2386 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2387 cmd->seid = CPU_TO_LE16(seid);
2388 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2394 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2395 * @hw: pointer to the hw struct
2397 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2398 * @cmd_details: pointer to command details structure or NULL
2400 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2401 u16 seid, bool enable,
2402 struct i40e_asq_cmd_details *cmd_details)
2404 struct i40e_aq_desc desc;
2405 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2406 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2407 enum i40e_status_code status;
2410 i40e_fill_default_direct_cmd_desc(&desc,
2411 i40e_aqc_opc_set_vsi_promiscuous_modes);
2413 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2415 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2416 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2417 cmd->seid = CPU_TO_LE16(seid);
2419 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2425 * i40e_get_vsi_params - get VSI configuration info
2426 * @hw: pointer to the hw struct
2427 * @vsi_ctx: pointer to a vsi context struct
2428 * @cmd_details: pointer to command details structure or NULL
2430 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2431 struct i40e_vsi_context *vsi_ctx,
2432 struct i40e_asq_cmd_details *cmd_details)
2434 struct i40e_aq_desc desc;
2435 struct i40e_aqc_add_get_update_vsi *cmd =
2436 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2437 struct i40e_aqc_add_get_update_vsi_completion *resp =
2438 (struct i40e_aqc_add_get_update_vsi_completion *)
2440 enum i40e_status_code status;
2442 UNREFERENCED_1PARAMETER(cmd_details);
2443 i40e_fill_default_direct_cmd_desc(&desc,
2444 i40e_aqc_opc_get_vsi_parameters);
2446 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2448 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2450 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2451 sizeof(vsi_ctx->info), NULL);
2453 if (status != I40E_SUCCESS)
2454 goto aq_get_vsi_params_exit;
2456 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2457 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2458 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2459 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2461 aq_get_vsi_params_exit:
2466 * i40e_aq_update_vsi_params
2467 * @hw: pointer to the hw struct
2468 * @vsi_ctx: pointer to a vsi context struct
2469 * @cmd_details: pointer to command details structure or NULL
2471 * Update a VSI context.
2473 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2474 struct i40e_vsi_context *vsi_ctx,
2475 struct i40e_asq_cmd_details *cmd_details)
2477 struct i40e_aq_desc desc;
2478 struct i40e_aqc_add_get_update_vsi *cmd =
2479 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2480 struct i40e_aqc_add_get_update_vsi_completion *resp =
2481 (struct i40e_aqc_add_get_update_vsi_completion *)
2483 enum i40e_status_code status;
2485 i40e_fill_default_direct_cmd_desc(&desc,
2486 i40e_aqc_opc_update_vsi_parameters);
2487 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2489 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2491 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2492 sizeof(vsi_ctx->info), cmd_details);
2494 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2495 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2501 * i40e_aq_get_switch_config
2502 * @hw: pointer to the hardware structure
2503 * @buf: pointer to the result buffer
2504 * @buf_size: length of input buffer
2505 * @start_seid: seid to start for the report, 0 == beginning
2506 * @cmd_details: pointer to command details structure or NULL
2508 * Fill the buf with switch configuration returned from AdminQ command
2510 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2511 struct i40e_aqc_get_switch_config_resp *buf,
2512 u16 buf_size, u16 *start_seid,
2513 struct i40e_asq_cmd_details *cmd_details)
2515 struct i40e_aq_desc desc;
2516 struct i40e_aqc_switch_seid *scfg =
2517 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2518 enum i40e_status_code status;
2520 i40e_fill_default_direct_cmd_desc(&desc,
2521 i40e_aqc_opc_get_switch_config);
2522 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2523 if (buf_size > I40E_AQ_LARGE_BUF)
2524 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2525 scfg->seid = CPU_TO_LE16(*start_seid);
2527 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2528 *start_seid = LE16_TO_CPU(scfg->seid);
2534 * i40e_aq_set_switch_config
2535 * @hw: pointer to the hardware structure
2536 * @flags: bit flag values to set
2537 * @valid_flags: which bit flags to set
2538 * @cmd_details: pointer to command details structure or NULL
2540 * Set switch configuration bits
2542 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2543 u16 flags, u16 valid_flags,
2544 struct i40e_asq_cmd_details *cmd_details)
2546 struct i40e_aq_desc desc;
2547 struct i40e_aqc_set_switch_config *scfg =
2548 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2549 enum i40e_status_code status;
2551 i40e_fill_default_direct_cmd_desc(&desc,
2552 i40e_aqc_opc_set_switch_config);
2553 scfg->flags = CPU_TO_LE16(flags);
2554 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2556 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2562 * i40e_aq_get_firmware_version
2563 * @hw: pointer to the hw struct
2564 * @fw_major_version: firmware major version
2565 * @fw_minor_version: firmware minor version
2566 * @fw_build: firmware build number
2567 * @api_major_version: major queue version
2568 * @api_minor_version: minor queue version
2569 * @cmd_details: pointer to command details structure or NULL
2571 * Get the firmware version from the admin queue commands
2573 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2574 u16 *fw_major_version, u16 *fw_minor_version,
2576 u16 *api_major_version, u16 *api_minor_version,
2577 struct i40e_asq_cmd_details *cmd_details)
2579 struct i40e_aq_desc desc;
2580 struct i40e_aqc_get_version *resp =
2581 (struct i40e_aqc_get_version *)&desc.params.raw;
2582 enum i40e_status_code status;
2584 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2586 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2588 if (status == I40E_SUCCESS) {
2589 if (fw_major_version != NULL)
2590 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2591 if (fw_minor_version != NULL)
2592 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2593 if (fw_build != NULL)
2594 *fw_build = LE32_TO_CPU(resp->fw_build);
2595 if (api_major_version != NULL)
2596 *api_major_version = LE16_TO_CPU(resp->api_major);
2597 if (api_minor_version != NULL)
2598 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2600 /* A workaround to fix the API version in SW */
2601 if (api_major_version && api_minor_version &&
2602 fw_major_version && fw_minor_version &&
2603 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2604 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2605 (*fw_major_version > 4)))
2606 *api_minor_version = 2;
2613 * i40e_aq_send_driver_version
2614 * @hw: pointer to the hw struct
2615 * @dv: driver's major, minor version
2616 * @cmd_details: pointer to command details structure or NULL
2618 * Send the driver version to the firmware
2620 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2621 struct i40e_driver_version *dv,
2622 struct i40e_asq_cmd_details *cmd_details)
2624 struct i40e_aq_desc desc;
2625 struct i40e_aqc_driver_version *cmd =
2626 (struct i40e_aqc_driver_version *)&desc.params.raw;
2627 enum i40e_status_code status;
2631 return I40E_ERR_PARAM;
2633 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2635 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2636 cmd->driver_major_ver = dv->major_version;
2637 cmd->driver_minor_ver = dv->minor_version;
2638 cmd->driver_build_ver = dv->build_version;
2639 cmd->driver_subbuild_ver = dv->subbuild_version;
2642 while (len < sizeof(dv->driver_string) &&
2643 (dv->driver_string[len] < 0x80) &&
2644 dv->driver_string[len])
2646 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2653 * i40e_get_link_status - get status of the HW network link
2654 * @hw: pointer to the hw struct
2655 * @link_up: pointer to bool (true/false = linkup/linkdown)
2657 * Variable link_up true if link is up, false if link is down.
2658 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2660 * Side effect: LinkStatusEvent reporting becomes enabled
2662 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2664 enum i40e_status_code status = I40E_SUCCESS;
2666 if (hw->phy.get_link_info) {
2667 status = i40e_update_link_info(hw);
2669 if (status != I40E_SUCCESS)
2670 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2674 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2680 * i40e_updatelink_status - update status of the HW network link
2681 * @hw: pointer to the hw struct
2683 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2685 struct i40e_aq_get_phy_abilities_resp abilities;
2686 enum i40e_status_code status = I40E_SUCCESS;
2688 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2692 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2693 status = i40e_aq_get_phy_capabilities(hw, false, false,
2698 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2699 sizeof(hw->phy.link_info.module_type));
2706 * i40e_get_link_speed
2707 * @hw: pointer to the hw struct
2709 * Returns the link speed of the adapter.
2711 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2713 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2714 enum i40e_status_code status = I40E_SUCCESS;
2716 if (hw->phy.get_link_info) {
2717 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2719 if (status != I40E_SUCCESS)
2720 goto i40e_link_speed_exit;
2723 speed = hw->phy.link_info.link_speed;
2725 i40e_link_speed_exit:
2730 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2731 * @hw: pointer to the hw struct
2732 * @uplink_seid: the MAC or other gizmo SEID
2733 * @downlink_seid: the VSI SEID
2734 * @enabled_tc: bitmap of TCs to be enabled
2735 * @default_port: true for default port VSI, false for control port
2736 * @veb_seid: pointer to where to put the resulting VEB SEID
2737 * @enable_stats: true to turn on VEB stats
2738 * @cmd_details: pointer to command details structure or NULL
2740 * This asks the FW to add a VEB between the uplink and downlink
2741 * elements. If the uplink SEID is 0, this will be a floating VEB.
2743 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2744 u16 downlink_seid, u8 enabled_tc,
2745 bool default_port, u16 *veb_seid,
2747 struct i40e_asq_cmd_details *cmd_details)
2749 struct i40e_aq_desc desc;
2750 struct i40e_aqc_add_veb *cmd =
2751 (struct i40e_aqc_add_veb *)&desc.params.raw;
2752 struct i40e_aqc_add_veb_completion *resp =
2753 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2754 enum i40e_status_code status;
2757 /* SEIDs need to either both be set or both be 0 for floating VEB */
2758 if (!!uplink_seid != !!downlink_seid)
2759 return I40E_ERR_PARAM;
2761 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2763 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2764 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2765 cmd->enable_tcs = enabled_tc;
2767 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2769 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2771 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2773 /* reverse logic here: set the bitflag to disable the stats */
2775 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2777 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2781 if (!status && veb_seid)
2782 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2788 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2789 * @hw: pointer to the hw struct
2790 * @veb_seid: the SEID of the VEB to query
2791 * @switch_id: the uplink switch id
2792 * @floating: set to true if the VEB is floating
2793 * @statistic_index: index of the stats counter block for this VEB
2794 * @vebs_used: number of VEB's used by function
2795 * @vebs_free: total VEB's not reserved by any function
2796 * @cmd_details: pointer to command details structure or NULL
2798 * This retrieves the parameters for a particular VEB, specified by
2799 * uplink_seid, and returns them to the caller.
2801 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2802 u16 veb_seid, u16 *switch_id,
2803 bool *floating, u16 *statistic_index,
2804 u16 *vebs_used, u16 *vebs_free,
2805 struct i40e_asq_cmd_details *cmd_details)
2807 struct i40e_aq_desc desc;
2808 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2809 (struct i40e_aqc_get_veb_parameters_completion *)
2811 enum i40e_status_code status;
2814 return I40E_ERR_PARAM;
2816 i40e_fill_default_direct_cmd_desc(&desc,
2817 i40e_aqc_opc_get_veb_parameters);
2818 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2820 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2825 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2826 if (statistic_index)
2827 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2829 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2831 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2833 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2835 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2846 * i40e_aq_add_macvlan
2847 * @hw: pointer to the hw struct
2848 * @seid: VSI for the mac address
2849 * @mv_list: list of macvlans to be added
2850 * @count: length of the list
2851 * @cmd_details: pointer to command details structure or NULL
2853 * Add MAC/VLAN addresses to the HW filtering
2855 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2856 struct i40e_aqc_add_macvlan_element_data *mv_list,
2857 u16 count, struct i40e_asq_cmd_details *cmd_details)
2859 struct i40e_aq_desc desc;
2860 struct i40e_aqc_macvlan *cmd =
2861 (struct i40e_aqc_macvlan *)&desc.params.raw;
2862 enum i40e_status_code status;
2866 if (count == 0 || !mv_list || !hw)
2867 return I40E_ERR_PARAM;
2869 buf_size = count * sizeof(*mv_list);
2871 /* prep the rest of the request */
2872 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2873 cmd->num_addresses = CPU_TO_LE16(count);
2874 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2878 for (i = 0; i < count; i++)
2879 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2881 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2883 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2884 if (buf_size > I40E_AQ_LARGE_BUF)
2885 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2887 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2894 * i40e_aq_remove_macvlan
2895 * @hw: pointer to the hw struct
2896 * @seid: VSI for the mac address
2897 * @mv_list: list of macvlans to be removed
2898 * @count: length of the list
2899 * @cmd_details: pointer to command details structure or NULL
2901 * Remove MAC/VLAN addresses from the HW filtering
2903 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2904 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2905 u16 count, struct i40e_asq_cmd_details *cmd_details)
2907 struct i40e_aq_desc desc;
2908 struct i40e_aqc_macvlan *cmd =
2909 (struct i40e_aqc_macvlan *)&desc.params.raw;
2910 enum i40e_status_code status;
2913 if (count == 0 || !mv_list || !hw)
2914 return I40E_ERR_PARAM;
2916 buf_size = count * sizeof(*mv_list);
2918 /* prep the rest of the request */
2919 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2920 cmd->num_addresses = CPU_TO_LE16(count);
2921 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2925 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2926 if (buf_size > I40E_AQ_LARGE_BUF)
2927 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2929 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2936 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2937 * @hw: pointer to the hw struct
2938 * @opcode: AQ opcode for add or delete mirror rule
2939 * @sw_seid: Switch SEID (to which rule refers)
2940 * @rule_type: Rule Type (ingress/egress/VLAN)
2941 * @id: Destination VSI SEID or Rule ID
2942 * @count: length of the list
2943 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2944 * @cmd_details: pointer to command details structure or NULL
2945 * @rule_id: Rule ID returned from FW
2946 * @rule_used: Number of rules used in internal switch
2947 * @rule_free: Number of rules free in internal switch
2949 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2950 * VEBs/VEPA elements only
2952 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2953 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2954 u16 count, __le16 *mr_list,
2955 struct i40e_asq_cmd_details *cmd_details,
2956 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2958 struct i40e_aq_desc desc;
2959 struct i40e_aqc_add_delete_mirror_rule *cmd =
2960 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2961 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2962 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2963 enum i40e_status_code status;
2966 buf_size = count * sizeof(*mr_list);
2968 /* prep the rest of the request */
2969 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2970 cmd->seid = CPU_TO_LE16(sw_seid);
2971 cmd->rule_type = CPU_TO_LE16(rule_type &
2972 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2973 cmd->num_entries = CPU_TO_LE16(count);
2974 /* Dest VSI for add, rule_id for delete */
2975 cmd->destination = CPU_TO_LE16(id);
2977 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2979 if (buf_size > I40E_AQ_LARGE_BUF)
2980 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2983 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2985 if (status == I40E_SUCCESS ||
2986 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2988 *rule_id = LE16_TO_CPU(resp->rule_id);
2990 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2992 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2998 * i40e_aq_add_mirrorrule - add a mirror rule
2999 * @hw: pointer to the hw struct
3000 * @sw_seid: Switch SEID (to which rule refers)
3001 * @rule_type: Rule Type (ingress/egress/VLAN)
3002 * @dest_vsi: SEID of VSI to which packets will be mirrored
3003 * @count: length of the list
3004 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3005 * @cmd_details: pointer to command details structure or NULL
3006 * @rule_id: Rule ID returned from FW
3007 * @rule_used: Number of rules used in internal switch
3008 * @rule_free: Number of rules free in internal switch
3010 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3012 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3013 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3014 struct i40e_asq_cmd_details *cmd_details,
3015 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3017 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3018 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3019 if (count == 0 || !mr_list)
3020 return I40E_ERR_PARAM;
3023 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3024 rule_type, dest_vsi, count, mr_list,
3025 cmd_details, rule_id, rules_used, rules_free);
3029 * i40e_aq_delete_mirrorrule - delete a mirror rule
3030 * @hw: pointer to the hw struct
3031 * @sw_seid: Switch SEID (to which rule refers)
3032 * @rule_type: Rule Type (ingress/egress/VLAN)
3033 * @count: length of the list
3034 * @rule_id: Rule ID that is returned in the receive desc as part of
3036 * @mr_list: list of mirrored VLAN IDs to be removed
3037 * @cmd_details: pointer to command details structure or NULL
3038 * @rule_used: Number of rules used in internal switch
3039 * @rule_free: Number of rules free in internal switch
3041 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3043 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3044 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3045 struct i40e_asq_cmd_details *cmd_details,
3046 u16 *rules_used, u16 *rules_free)
3048 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3049 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3050 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3051 * mirroring. For other rule_type, count and rule_type should
3054 if (count == 0 || !mr_list)
3055 return I40E_ERR_PARAM;
3058 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3059 rule_type, rule_id, count, mr_list,
3060 cmd_details, NULL, rules_used, rules_free);
3064 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3065 * @hw: pointer to the hw struct
3066 * @seid: VSI for the vlan filters
3067 * @v_list: list of vlan filters to be added
3068 * @count: length of the list
3069 * @cmd_details: pointer to command details structure or NULL
3071 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3072 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3073 u8 count, struct i40e_asq_cmd_details *cmd_details)
3075 struct i40e_aq_desc desc;
3076 struct i40e_aqc_macvlan *cmd =
3077 (struct i40e_aqc_macvlan *)&desc.params.raw;
3078 enum i40e_status_code status;
3081 if (count == 0 || !v_list || !hw)
3082 return I40E_ERR_PARAM;
3084 buf_size = count * sizeof(*v_list);
3086 /* prep the rest of the request */
3087 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3088 cmd->num_addresses = CPU_TO_LE16(count);
3089 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3093 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3094 if (buf_size > I40E_AQ_LARGE_BUF)
3095 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3097 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3104 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3105 * @hw: pointer to the hw struct
3106 * @seid: VSI for the vlan filters
3107 * @v_list: list of macvlans to be removed
3108 * @count: length of the list
3109 * @cmd_details: pointer to command details structure or NULL
3111 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3112 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3113 u8 count, struct i40e_asq_cmd_details *cmd_details)
3115 struct i40e_aq_desc desc;
3116 struct i40e_aqc_macvlan *cmd =
3117 (struct i40e_aqc_macvlan *)&desc.params.raw;
3118 enum i40e_status_code status;
3121 if (count == 0 || !v_list || !hw)
3122 return I40E_ERR_PARAM;
3124 buf_size = count * sizeof(*v_list);
3126 /* prep the rest of the request */
3127 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3128 cmd->num_addresses = CPU_TO_LE16(count);
3129 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3133 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3134 if (buf_size > I40E_AQ_LARGE_BUF)
3135 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3137 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3144 * i40e_aq_send_msg_to_vf
3145 * @hw: pointer to the hardware structure
3146 * @vfid: vf id to send msg
3147 * @v_opcode: opcodes for VF-PF communication
3148 * @v_retval: return error code
3149 * @msg: pointer to the msg buffer
3150 * @msglen: msg length
3151 * @cmd_details: pointer to command details
3155 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3156 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3157 struct i40e_asq_cmd_details *cmd_details)
3159 struct i40e_aq_desc desc;
3160 struct i40e_aqc_pf_vf_message *cmd =
3161 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3162 enum i40e_status_code status;
3164 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3165 cmd->id = CPU_TO_LE32(vfid);
3166 desc.cookie_high = CPU_TO_LE32(v_opcode);
3167 desc.cookie_low = CPU_TO_LE32(v_retval);
3168 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3170 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3172 if (msglen > I40E_AQ_LARGE_BUF)
3173 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3174 desc.datalen = CPU_TO_LE16(msglen);
3176 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3182 * i40e_aq_debug_read_register
3183 * @hw: pointer to the hw struct
3184 * @reg_addr: register address
3185 * @reg_val: register value
3186 * @cmd_details: pointer to command details structure or NULL
3188 * Read the register using the admin queue commands
3190 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3191 u32 reg_addr, u64 *reg_val,
3192 struct i40e_asq_cmd_details *cmd_details)
3194 struct i40e_aq_desc desc;
3195 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3196 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3197 enum i40e_status_code status;
3199 if (reg_val == NULL)
3200 return I40E_ERR_PARAM;
3202 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3204 cmd_resp->address = CPU_TO_LE32(reg_addr);
3206 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3208 if (status == I40E_SUCCESS) {
3209 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3210 (u64)LE32_TO_CPU(cmd_resp->value_low);
3217 * i40e_aq_debug_write_register
3218 * @hw: pointer to the hw struct
3219 * @reg_addr: register address
3220 * @reg_val: register value
3221 * @cmd_details: pointer to command details structure or NULL
3223 * Write to a register using the admin queue commands
3225 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3226 u32 reg_addr, u64 reg_val,
3227 struct i40e_asq_cmd_details *cmd_details)
3229 struct i40e_aq_desc desc;
3230 struct i40e_aqc_debug_reg_read_write *cmd =
3231 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3232 enum i40e_status_code status;
3234 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3236 cmd->address = CPU_TO_LE32(reg_addr);
3237 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3238 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3240 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3246 * i40e_aq_request_resource
3247 * @hw: pointer to the hw struct
3248 * @resource: resource id
3249 * @access: access type
3250 * @sdp_number: resource number
3251 * @timeout: the maximum time in ms that the driver may hold the resource
3252 * @cmd_details: pointer to command details structure or NULL
3254 * requests common resource using the admin queue commands
3256 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3257 enum i40e_aq_resources_ids resource,
3258 enum i40e_aq_resource_access_type access,
3259 u8 sdp_number, u64 *timeout,
3260 struct i40e_asq_cmd_details *cmd_details)
3262 struct i40e_aq_desc desc;
3263 struct i40e_aqc_request_resource *cmd_resp =
3264 (struct i40e_aqc_request_resource *)&desc.params.raw;
3265 enum i40e_status_code status;
3267 DEBUGFUNC("i40e_aq_request_resource");
3269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3271 cmd_resp->resource_id = CPU_TO_LE16(resource);
3272 cmd_resp->access_type = CPU_TO_LE16(access);
3273 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3275 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3276 /* The completion specifies the maximum time in ms that the driver
3277 * may hold the resource in the Timeout field.
3278 * If the resource is held by someone else, the command completes with
3279 * busy return value and the timeout field indicates the maximum time
3280 * the current owner of the resource has to free it.
3282 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3283 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3289 * i40e_aq_release_resource
3290 * @hw: pointer to the hw struct
3291 * @resource: resource id
3292 * @sdp_number: resource number
3293 * @cmd_details: pointer to command details structure or NULL
3295 * release common resource using the admin queue commands
3297 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3298 enum i40e_aq_resources_ids resource,
3300 struct i40e_asq_cmd_details *cmd_details)
3302 struct i40e_aq_desc desc;
3303 struct i40e_aqc_request_resource *cmd =
3304 (struct i40e_aqc_request_resource *)&desc.params.raw;
3305 enum i40e_status_code status;
3307 DEBUGFUNC("i40e_aq_release_resource");
3309 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3311 cmd->resource_id = CPU_TO_LE16(resource);
3312 cmd->resource_number = CPU_TO_LE32(sdp_number);
3314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3321 * @hw: pointer to the hw struct
3322 * @module_pointer: module pointer location in words from the NVM beginning
3323 * @offset: byte offset from the module beginning
3324 * @length: length of the section to be read (in bytes from the offset)
3325 * @data: command buffer (size [bytes] = length)
3326 * @last_command: tells if this is the last command in a series
3327 * @cmd_details: pointer to command details structure or NULL
3329 * Read the NVM using the admin queue commands
3331 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3332 u32 offset, u16 length, void *data,
3334 struct i40e_asq_cmd_details *cmd_details)
3336 struct i40e_aq_desc desc;
3337 struct i40e_aqc_nvm_update *cmd =
3338 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3339 enum i40e_status_code status;
3341 DEBUGFUNC("i40e_aq_read_nvm");
3343 /* In offset the highest byte must be zeroed. */
3344 if (offset & 0xFF000000) {
3345 status = I40E_ERR_PARAM;
3346 goto i40e_aq_read_nvm_exit;
3349 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3351 /* If this is the last command in a series, set the proper flag. */
3353 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3354 cmd->module_pointer = module_pointer;
3355 cmd->offset = CPU_TO_LE32(offset);
3356 cmd->length = CPU_TO_LE16(length);
3358 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3359 if (length > I40E_AQ_LARGE_BUF)
3360 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3362 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3364 i40e_aq_read_nvm_exit:
3369 * i40e_aq_read_nvm_config - read an nvm config block
3370 * @hw: pointer to the hw struct
3371 * @cmd_flags: NVM access admin command bits
3372 * @field_id: field or feature id
3373 * @data: buffer for result
3374 * @buf_size: buffer size
3375 * @element_count: pointer to count of elements read by FW
3376 * @cmd_details: pointer to command details structure or NULL
3378 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3379 u8 cmd_flags, u32 field_id, void *data,
3380 u16 buf_size, u16 *element_count,
3381 struct i40e_asq_cmd_details *cmd_details)
3383 struct i40e_aq_desc desc;
3384 struct i40e_aqc_nvm_config_read *cmd =
3385 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3386 enum i40e_status_code status;
3388 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3389 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3390 if (buf_size > I40E_AQ_LARGE_BUF)
3391 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3393 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3394 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3395 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3396 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3398 cmd->element_id_msw = 0;
3400 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3402 if (!status && element_count)
3403 *element_count = LE16_TO_CPU(cmd->element_count);
3409 * i40e_aq_write_nvm_config - write an nvm config block
3410 * @hw: pointer to the hw struct
3411 * @cmd_flags: NVM access admin command bits
3412 * @data: buffer for result
3413 * @buf_size: buffer size
3414 * @element_count: count of elements to be written
3415 * @cmd_details: pointer to command details structure or NULL
3417 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3418 u8 cmd_flags, void *data, u16 buf_size,
3420 struct i40e_asq_cmd_details *cmd_details)
3422 struct i40e_aq_desc desc;
3423 struct i40e_aqc_nvm_config_write *cmd =
3424 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3425 enum i40e_status_code status;
3427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3428 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3429 if (buf_size > I40E_AQ_LARGE_BUF)
3430 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3432 cmd->element_count = CPU_TO_LE16(element_count);
3433 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3434 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3440 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3441 * @hw: pointer to the hw struct
3442 * @cmd_details: pointer to command details structure or NULL
3444 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3445 void *buff, u16 buff_size,
3446 struct i40e_asq_cmd_details *cmd_details)
3448 struct i40e_aq_desc desc;
3449 enum i40e_status_code status;
3451 UNREFERENCED_2PARAMETER(buff, buff_size);
3453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3455 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3456 status = I40E_ERR_NOT_IMPLEMENTED;
3463 * @hw: pointer to the hw struct
3464 * @module_pointer: module pointer location in words from the NVM beginning
3465 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3466 * @length: length of the section to be erased (expressed in 4 KB)
3467 * @last_command: tells if this is the last command in a series
3468 * @cmd_details: pointer to command details structure or NULL
3470 * Erase the NVM sector using the admin queue commands
3472 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3473 u32 offset, u16 length, bool last_command,
3474 struct i40e_asq_cmd_details *cmd_details)
3476 struct i40e_aq_desc desc;
3477 struct i40e_aqc_nvm_update *cmd =
3478 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3479 enum i40e_status_code status;
3481 DEBUGFUNC("i40e_aq_erase_nvm");
3483 /* In offset the highest byte must be zeroed. */
3484 if (offset & 0xFF000000) {
3485 status = I40E_ERR_PARAM;
3486 goto i40e_aq_erase_nvm_exit;
3489 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3491 /* If this is the last command in a series, set the proper flag. */
3493 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3494 cmd->module_pointer = module_pointer;
3495 cmd->offset = CPU_TO_LE32(offset);
3496 cmd->length = CPU_TO_LE16(length);
3498 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3500 i40e_aq_erase_nvm_exit:
3505 * i40e_parse_discover_capabilities
3506 * @hw: pointer to the hw struct
3507 * @buff: pointer to a buffer containing device/function capability records
3508 * @cap_count: number of capability records in the list
3509 * @list_type_opc: type of capabilities list to parse
3511 * Parse the device/function capabilities list.
3513 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3515 enum i40e_admin_queue_opc list_type_opc)
3517 struct i40e_aqc_list_capabilities_element_resp *cap;
3518 u32 valid_functions, num_functions;
3519 u32 number, logical_id, phys_id;
3520 struct i40e_hw_capabilities *p;
3525 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3527 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3528 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3529 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3530 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3534 for (i = 0; i < cap_count; i++, cap++) {
3535 id = LE16_TO_CPU(cap->id);
3536 number = LE32_TO_CPU(cap->number);
3537 logical_id = LE32_TO_CPU(cap->logical_id);
3538 phys_id = LE32_TO_CPU(cap->phys_id);
3539 major_rev = cap->major_rev;
3542 case I40E_AQ_CAP_ID_SWITCH_MODE:
3543 p->switch_mode = number;
3544 i40e_debug(hw, I40E_DEBUG_INIT,
3545 "HW Capability: Switch mode = %d\n",
3548 case I40E_AQ_CAP_ID_MNG_MODE:
3549 p->management_mode = number;
3550 i40e_debug(hw, I40E_DEBUG_INIT,
3551 "HW Capability: Management Mode = %d\n",
3552 p->management_mode);
3554 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3555 p->npar_enable = number;
3556 i40e_debug(hw, I40E_DEBUG_INIT,
3557 "HW Capability: NPAR enable = %d\n",
3560 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3562 i40e_debug(hw, I40E_DEBUG_INIT,
3563 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3565 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3566 p->valid_functions = number;
3567 i40e_debug(hw, I40E_DEBUG_INIT,
3568 "HW Capability: Valid Functions = %d\n",
3569 p->valid_functions);
3571 case I40E_AQ_CAP_ID_SRIOV:
3573 p->sr_iov_1_1 = true;
3574 i40e_debug(hw, I40E_DEBUG_INIT,
3575 "HW Capability: SR-IOV = %d\n",
3578 case I40E_AQ_CAP_ID_VF:
3579 p->num_vfs = number;
3580 p->vf_base_id = logical_id;
3581 i40e_debug(hw, I40E_DEBUG_INIT,
3582 "HW Capability: VF count = %d\n",
3584 i40e_debug(hw, I40E_DEBUG_INIT,
3585 "HW Capability: VF base_id = %d\n",
3588 case I40E_AQ_CAP_ID_VMDQ:
3591 i40e_debug(hw, I40E_DEBUG_INIT,
3592 "HW Capability: VMDQ = %d\n", p->vmdq);
3594 case I40E_AQ_CAP_ID_8021QBG:
3596 p->evb_802_1_qbg = true;
3597 i40e_debug(hw, I40E_DEBUG_INIT,
3598 "HW Capability: 802.1Qbg = %d\n", number);
3600 case I40E_AQ_CAP_ID_8021QBR:
3602 p->evb_802_1_qbh = true;
3603 i40e_debug(hw, I40E_DEBUG_INIT,
3604 "HW Capability: 802.1Qbh = %d\n", number);
3606 case I40E_AQ_CAP_ID_VSI:
3607 p->num_vsis = number;
3608 i40e_debug(hw, I40E_DEBUG_INIT,
3609 "HW Capability: VSI count = %d\n",
3612 case I40E_AQ_CAP_ID_DCB:
3615 p->enabled_tcmap = logical_id;
3618 i40e_debug(hw, I40E_DEBUG_INIT,
3619 "HW Capability: DCB = %d\n", p->dcb);
3620 i40e_debug(hw, I40E_DEBUG_INIT,
3621 "HW Capability: TC Mapping = %d\n",
3623 i40e_debug(hw, I40E_DEBUG_INIT,
3624 "HW Capability: TC Max = %d\n", p->maxtc);
3626 case I40E_AQ_CAP_ID_FCOE:
3629 i40e_debug(hw, I40E_DEBUG_INIT,
3630 "HW Capability: FCOE = %d\n", p->fcoe);
3632 case I40E_AQ_CAP_ID_ISCSI:
3635 i40e_debug(hw, I40E_DEBUG_INIT,
3636 "HW Capability: iSCSI = %d\n", p->iscsi);
3638 case I40E_AQ_CAP_ID_RSS:
3640 p->rss_table_size = number;
3641 p->rss_table_entry_width = logical_id;
3642 i40e_debug(hw, I40E_DEBUG_INIT,
3643 "HW Capability: RSS = %d\n", p->rss);
3644 i40e_debug(hw, I40E_DEBUG_INIT,
3645 "HW Capability: RSS table size = %d\n",
3647 i40e_debug(hw, I40E_DEBUG_INIT,
3648 "HW Capability: RSS table width = %d\n",
3649 p->rss_table_entry_width);
3651 case I40E_AQ_CAP_ID_RXQ:
3652 p->num_rx_qp = number;
3653 p->base_queue = phys_id;
3654 i40e_debug(hw, I40E_DEBUG_INIT,
3655 "HW Capability: Rx QP = %d\n", number);
3656 i40e_debug(hw, I40E_DEBUG_INIT,
3657 "HW Capability: base_queue = %d\n",
3660 case I40E_AQ_CAP_ID_TXQ:
3661 p->num_tx_qp = number;
3662 p->base_queue = phys_id;
3663 i40e_debug(hw, I40E_DEBUG_INIT,
3664 "HW Capability: Tx QP = %d\n", number);
3665 i40e_debug(hw, I40E_DEBUG_INIT,
3666 "HW Capability: base_queue = %d\n",
3669 case I40E_AQ_CAP_ID_MSIX:
3670 p->num_msix_vectors = number;
3671 i40e_debug(hw, I40E_DEBUG_INIT,
3672 "HW Capability: MSIX vector count = %d\n",
3673 p->num_msix_vectors);
3675 case I40E_AQ_CAP_ID_VF_MSIX:
3676 p->num_msix_vectors_vf = number;
3677 i40e_debug(hw, I40E_DEBUG_INIT,
3678 "HW Capability: MSIX VF vector count = %d\n",
3679 p->num_msix_vectors_vf);
3681 case I40E_AQ_CAP_ID_FLEX10:
3682 if (major_rev == 1) {
3684 p->flex10_enable = true;
3685 p->flex10_capable = true;
3688 /* Capability revision >= 2 */
3690 p->flex10_enable = true;
3692 p->flex10_capable = true;
3694 p->flex10_mode = logical_id;
3695 p->flex10_status = phys_id;
3696 i40e_debug(hw, I40E_DEBUG_INIT,
3697 "HW Capability: Flex10 mode = %d\n",
3699 i40e_debug(hw, I40E_DEBUG_INIT,
3700 "HW Capability: Flex10 status = %d\n",
3703 case I40E_AQ_CAP_ID_CEM:
3706 i40e_debug(hw, I40E_DEBUG_INIT,
3707 "HW Capability: CEM = %d\n", p->mgmt_cem);
3709 case I40E_AQ_CAP_ID_IWARP:
3712 i40e_debug(hw, I40E_DEBUG_INIT,
3713 "HW Capability: iWARP = %d\n", p->iwarp);
3715 case I40E_AQ_CAP_ID_LED:
3716 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3717 p->led[phys_id] = true;
3718 i40e_debug(hw, I40E_DEBUG_INIT,
3719 "HW Capability: LED - PIN %d\n", phys_id);
3721 case I40E_AQ_CAP_ID_SDP:
3722 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3723 p->sdp[phys_id] = true;
3724 i40e_debug(hw, I40E_DEBUG_INIT,
3725 "HW Capability: SDP - PIN %d\n", phys_id);
3727 case I40E_AQ_CAP_ID_MDIO:
3729 p->mdio_port_num = phys_id;
3730 p->mdio_port_mode = logical_id;
3732 i40e_debug(hw, I40E_DEBUG_INIT,
3733 "HW Capability: MDIO port number = %d\n",
3735 i40e_debug(hw, I40E_DEBUG_INIT,
3736 "HW Capability: MDIO port mode = %d\n",
3739 case I40E_AQ_CAP_ID_1588:
3741 p->ieee_1588 = true;
3742 i40e_debug(hw, I40E_DEBUG_INIT,
3743 "HW Capability: IEEE 1588 = %d\n",
3746 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3748 p->fd_filters_guaranteed = number;
3749 p->fd_filters_best_effort = logical_id;
3750 i40e_debug(hw, I40E_DEBUG_INIT,
3751 "HW Capability: Flow Director = 1\n");
3752 i40e_debug(hw, I40E_DEBUG_INIT,
3753 "HW Capability: Guaranteed FD filters = %d\n",
3754 p->fd_filters_guaranteed);
3756 case I40E_AQ_CAP_ID_WSR_PROT:
3757 p->wr_csr_prot = (u64)number;
3758 p->wr_csr_prot |= (u64)logical_id << 32;
3759 i40e_debug(hw, I40E_DEBUG_INIT,
3760 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3761 (p->wr_csr_prot & 0xffff));
3764 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3765 hw->num_wol_proxy_filters = (u16)number;
3766 hw->wol_proxy_vsi_seid = (u16)logical_id;
3767 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3768 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3769 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3771 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3772 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3773 p->proxy_support = p->proxy_support;
3774 i40e_debug(hw, I40E_DEBUG_INIT,
3775 "HW Capability: WOL proxy filters = %d\n",
3776 hw->num_wol_proxy_filters);
3785 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3787 #ifdef I40E_FCOE_ENA
3788 /* Software override ensuring FCoE is disabled if npar or mfp
3789 * mode because it is not supported in these modes.
3791 if (p->npar_enable || p->flex10_enable)
3794 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3798 /* count the enabled ports (aka the "not disabled" ports) */
3800 for (i = 0; i < 4; i++) {
3801 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3804 /* use AQ read to get the physical register offset instead
3805 * of the port relative offset
3807 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3808 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3812 valid_functions = p->valid_functions;
3814 while (valid_functions) {
3815 if (valid_functions & 1)
3817 valid_functions >>= 1;
3820 /* partition id is 1-based, and functions are evenly spread
3821 * across the ports as partitions
3823 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3824 hw->num_partitions = num_functions / hw->num_ports;
3826 /* additional HW specific goodies that might
3827 * someday be HW version specific
3829 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3833 * i40e_aq_discover_capabilities
3834 * @hw: pointer to the hw struct
3835 * @buff: a virtual buffer to hold the capabilities
3836 * @buff_size: Size of the virtual buffer
3837 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3838 * @list_type_opc: capabilities type to discover - pass in the command opcode
3839 * @cmd_details: pointer to command details structure or NULL
3841 * Get the device capabilities descriptions from the firmware
3843 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3844 void *buff, u16 buff_size, u16 *data_size,
3845 enum i40e_admin_queue_opc list_type_opc,
3846 struct i40e_asq_cmd_details *cmd_details)
3848 struct i40e_aqc_list_capabilites *cmd;
3849 struct i40e_aq_desc desc;
3850 enum i40e_status_code status = I40E_SUCCESS;
3852 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3854 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3855 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3856 status = I40E_ERR_PARAM;
3860 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3862 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3863 if (buff_size > I40E_AQ_LARGE_BUF)
3864 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3866 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3867 *data_size = LE16_TO_CPU(desc.datalen);
3872 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3880 * i40e_aq_update_nvm
3881 * @hw: pointer to the hw struct
3882 * @module_pointer: module pointer location in words from the NVM beginning
3883 * @offset: byte offset from the module beginning
3884 * @length: length of the section to be written (in bytes from the offset)
3885 * @data: command buffer (size [bytes] = length)
3886 * @last_command: tells if this is the last command in a series
3887 * @cmd_details: pointer to command details structure or NULL
3889 * Update the NVM using the admin queue commands
3891 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3892 u32 offset, u16 length, void *data,
3894 struct i40e_asq_cmd_details *cmd_details)
3896 struct i40e_aq_desc desc;
3897 struct i40e_aqc_nvm_update *cmd =
3898 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3899 enum i40e_status_code status;
3901 DEBUGFUNC("i40e_aq_update_nvm");
3903 /* In offset the highest byte must be zeroed. */
3904 if (offset & 0xFF000000) {
3905 status = I40E_ERR_PARAM;
3906 goto i40e_aq_update_nvm_exit;
3909 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3911 /* If this is the last command in a series, set the proper flag. */
3913 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3914 cmd->module_pointer = module_pointer;
3915 cmd->offset = CPU_TO_LE32(offset);
3916 cmd->length = CPU_TO_LE16(length);
3918 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3919 if (length > I40E_AQ_LARGE_BUF)
3920 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3922 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3924 i40e_aq_update_nvm_exit:
3929 * i40e_aq_get_lldp_mib
3930 * @hw: pointer to the hw struct
3931 * @bridge_type: type of bridge requested
3932 * @mib_type: Local, Remote or both Local and Remote MIBs
3933 * @buff: pointer to a user supplied buffer to store the MIB block
3934 * @buff_size: size of the buffer (in bytes)
3935 * @local_len : length of the returned Local LLDP MIB
3936 * @remote_len: length of the returned Remote LLDP MIB
3937 * @cmd_details: pointer to command details structure or NULL
3939 * Requests the complete LLDP MIB (entire packet).
3941 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3942 u8 mib_type, void *buff, u16 buff_size,
3943 u16 *local_len, u16 *remote_len,
3944 struct i40e_asq_cmd_details *cmd_details)
3946 struct i40e_aq_desc desc;
3947 struct i40e_aqc_lldp_get_mib *cmd =
3948 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3949 struct i40e_aqc_lldp_get_mib *resp =
3950 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3951 enum i40e_status_code status;
3953 if (buff_size == 0 || !buff)
3954 return I40E_ERR_PARAM;
3956 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3957 /* Indirect Command */
3958 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3960 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3961 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3962 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3964 desc.datalen = CPU_TO_LE16(buff_size);
3966 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3967 if (buff_size > I40E_AQ_LARGE_BUF)
3968 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3970 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3972 if (local_len != NULL)
3973 *local_len = LE16_TO_CPU(resp->local_len);
3974 if (remote_len != NULL)
3975 *remote_len = LE16_TO_CPU(resp->remote_len);
3982 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3983 * @hw: pointer to the hw struct
3984 * @mib_type: Local, Remote or both Local and Remote MIBs
3985 * @buff: pointer to a user supplied buffer to store the MIB block
3986 * @buff_size: size of the buffer (in bytes)
3987 * @cmd_details: pointer to command details structure or NULL
3991 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3992 u8 mib_type, void *buff, u16 buff_size,
3993 struct i40e_asq_cmd_details *cmd_details)
3995 struct i40e_aq_desc desc;
3996 struct i40e_aqc_lldp_set_local_mib *cmd =
3997 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3998 enum i40e_status_code status;
4000 if (buff_size == 0 || !buff)
4001 return I40E_ERR_PARAM;
4003 i40e_fill_default_direct_cmd_desc(&desc,
4004 i40e_aqc_opc_lldp_set_local_mib);
4005 /* Indirect Command */
4006 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4007 if (buff_size > I40E_AQ_LARGE_BUF)
4008 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4009 desc.datalen = CPU_TO_LE16(buff_size);
4011 cmd->type = mib_type;
4012 cmd->length = CPU_TO_LE16(buff_size);
4013 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4014 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4016 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4021 * i40e_aq_cfg_lldp_mib_change_event
4022 * @hw: pointer to the hw struct
4023 * @enable_update: Enable or Disable event posting
4024 * @cmd_details: pointer to command details structure or NULL
4026 * Enable or Disable posting of an event on ARQ when LLDP MIB
4027 * associated with the interface changes
4029 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4031 struct i40e_asq_cmd_details *cmd_details)
4033 struct i40e_aq_desc desc;
4034 struct i40e_aqc_lldp_update_mib *cmd =
4035 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4036 enum i40e_status_code status;
4038 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4041 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4043 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4049 * i40e_aq_add_lldp_tlv
4050 * @hw: pointer to the hw struct
4051 * @bridge_type: type of bridge
4052 * @buff: buffer with TLV to add
4053 * @buff_size: length of the buffer
4054 * @tlv_len: length of the TLV to be added
4055 * @mib_len: length of the LLDP MIB returned in response
4056 * @cmd_details: pointer to command details structure or NULL
4058 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4059 * it is responsibility of the caller to make sure that the TLV is not
4060 * already present in the LLDPDU.
4061 * In return firmware will write the complete LLDP MIB with the newly
4062 * added TLV in the response buffer.
4064 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4065 void *buff, u16 buff_size, u16 tlv_len,
4067 struct i40e_asq_cmd_details *cmd_details)
4069 struct i40e_aq_desc desc;
4070 struct i40e_aqc_lldp_add_tlv *cmd =
4071 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4072 enum i40e_status_code status;
4074 if (buff_size == 0 || !buff || tlv_len == 0)
4075 return I40E_ERR_PARAM;
4077 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4079 /* Indirect Command */
4080 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4081 if (buff_size > I40E_AQ_LARGE_BUF)
4082 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4083 desc.datalen = CPU_TO_LE16(buff_size);
4085 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4086 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4087 cmd->len = CPU_TO_LE16(tlv_len);
4089 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4091 if (mib_len != NULL)
4092 *mib_len = LE16_TO_CPU(desc.datalen);
4099 * i40e_aq_update_lldp_tlv
4100 * @hw: pointer to the hw struct
4101 * @bridge_type: type of bridge
4102 * @buff: buffer with TLV to update
4103 * @buff_size: size of the buffer holding original and updated TLVs
4104 * @old_len: Length of the Original TLV
4105 * @new_len: Length of the Updated TLV
4106 * @offset: offset of the updated TLV in the buff
4107 * @mib_len: length of the returned LLDP MIB
4108 * @cmd_details: pointer to command details structure or NULL
4110 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4111 * Firmware will place the complete LLDP MIB in response buffer with the
4114 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4115 u8 bridge_type, void *buff, u16 buff_size,
4116 u16 old_len, u16 new_len, u16 offset,
4118 struct i40e_asq_cmd_details *cmd_details)
4120 struct i40e_aq_desc desc;
4121 struct i40e_aqc_lldp_update_tlv *cmd =
4122 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4123 enum i40e_status_code status;
4125 if (buff_size == 0 || !buff || offset == 0 ||
4126 old_len == 0 || new_len == 0)
4127 return I40E_ERR_PARAM;
4129 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4131 /* Indirect Command */
4132 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4133 if (buff_size > I40E_AQ_LARGE_BUF)
4134 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4135 desc.datalen = CPU_TO_LE16(buff_size);
4137 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4138 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4139 cmd->old_len = CPU_TO_LE16(old_len);
4140 cmd->new_offset = CPU_TO_LE16(offset);
4141 cmd->new_len = CPU_TO_LE16(new_len);
4143 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4145 if (mib_len != NULL)
4146 *mib_len = LE16_TO_CPU(desc.datalen);
4153 * i40e_aq_delete_lldp_tlv
4154 * @hw: pointer to the hw struct
4155 * @bridge_type: type of bridge
4156 * @buff: pointer to a user supplied buffer that has the TLV
4157 * @buff_size: length of the buffer
4158 * @tlv_len: length of the TLV to be deleted
4159 * @mib_len: length of the returned LLDP MIB
4160 * @cmd_details: pointer to command details structure or NULL
4162 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4163 * The firmware places the entire LLDP MIB in the response buffer.
4165 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4166 u8 bridge_type, void *buff, u16 buff_size,
4167 u16 tlv_len, u16 *mib_len,
4168 struct i40e_asq_cmd_details *cmd_details)
4170 struct i40e_aq_desc desc;
4171 struct i40e_aqc_lldp_add_tlv *cmd =
4172 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4173 enum i40e_status_code status;
4175 if (buff_size == 0 || !buff)
4176 return I40E_ERR_PARAM;
4178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4180 /* Indirect Command */
4181 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4182 if (buff_size > I40E_AQ_LARGE_BUF)
4183 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4184 desc.datalen = CPU_TO_LE16(buff_size);
4185 cmd->len = CPU_TO_LE16(tlv_len);
4186 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4187 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4189 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4191 if (mib_len != NULL)
4192 *mib_len = LE16_TO_CPU(desc.datalen);
4200 * @hw: pointer to the hw struct
4201 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4202 * @cmd_details: pointer to command details structure or NULL
4204 * Stop or Shutdown the embedded LLDP Agent
4206 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4207 struct i40e_asq_cmd_details *cmd_details)
4209 struct i40e_aq_desc desc;
4210 struct i40e_aqc_lldp_stop *cmd =
4211 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4212 enum i40e_status_code status;
4214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4217 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4225 * i40e_aq_start_lldp
4226 * @hw: pointer to the hw struct
4227 * @cmd_details: pointer to command details structure or NULL
4229 * Start the embedded LLDP Agent on all ports.
4231 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4232 struct i40e_asq_cmd_details *cmd_details)
4234 struct i40e_aq_desc desc;
4235 struct i40e_aqc_lldp_start *cmd =
4236 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4237 enum i40e_status_code status;
4239 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4241 cmd->command = I40E_AQ_LLDP_AGENT_START;
4243 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4249 * i40e_aq_get_cee_dcb_config
4250 * @hw: pointer to the hw struct
4251 * @buff: response buffer that stores CEE operational configuration
4252 * @buff_size: size of the buffer passed
4253 * @cmd_details: pointer to command details structure or NULL
4255 * Get CEE DCBX mode operational configuration from firmware
4257 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4258 void *buff, u16 buff_size,
4259 struct i40e_asq_cmd_details *cmd_details)
4261 struct i40e_aq_desc desc;
4262 enum i40e_status_code status;
4264 if (buff_size == 0 || !buff)
4265 return I40E_ERR_PARAM;
4267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4270 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4277 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4278 * @hw: pointer to the hw struct
4279 * @start_agent: True if DCBx Agent needs to be Started
4280 * False if DCBx Agent needs to be Stopped
4281 * @cmd_details: pointer to command details structure or NULL
4283 * Start/Stop the embedded dcbx Agent
4285 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4287 struct i40e_asq_cmd_details *cmd_details)
4289 struct i40e_aq_desc desc;
4290 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4291 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4293 enum i40e_status_code status;
4295 i40e_fill_default_direct_cmd_desc(&desc,
4296 i40e_aqc_opc_lldp_stop_start_spec_agent);
4299 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4301 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4307 * i40e_aq_add_udp_tunnel
4308 * @hw: pointer to the hw struct
4309 * @udp_port: the UDP port to add
4310 * @header_len: length of the tunneling header length in DWords
4311 * @protocol_index: protocol index type
4312 * @filter_index: pointer to filter index
4313 * @cmd_details: pointer to command details structure or NULL
4315 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4316 u16 udp_port, u8 protocol_index,
4318 struct i40e_asq_cmd_details *cmd_details)
4320 struct i40e_aq_desc desc;
4321 struct i40e_aqc_add_udp_tunnel *cmd =
4322 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4323 struct i40e_aqc_del_udp_tunnel_completion *resp =
4324 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4325 enum i40e_status_code status;
4327 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4329 cmd->udp_port = CPU_TO_LE16(udp_port);
4330 cmd->protocol_type = protocol_index;
4332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4334 if (!status && filter_index)
4335 *filter_index = resp->index;
4341 * i40e_aq_del_udp_tunnel
4342 * @hw: pointer to the hw struct
4343 * @index: filter index
4344 * @cmd_details: pointer to command details structure or NULL
4346 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4347 struct i40e_asq_cmd_details *cmd_details)
4349 struct i40e_aq_desc desc;
4350 struct i40e_aqc_remove_udp_tunnel *cmd =
4351 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4352 enum i40e_status_code status;
4354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4358 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4364 * i40e_aq_get_switch_resource_alloc (0x0204)
4365 * @hw: pointer to the hw struct
4366 * @num_entries: pointer to u8 to store the number of resource entries returned
4367 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4368 * to store the resource information for all resource types. Each
4369 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4370 * @count: size, in bytes, of the buffer provided
4371 * @cmd_details: pointer to command details structure or NULL
4373 * Query the resources allocated to a function.
4375 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4377 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4379 struct i40e_asq_cmd_details *cmd_details)
4381 struct i40e_aq_desc desc;
4382 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4383 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4384 enum i40e_status_code status;
4385 u16 length = count * sizeof(*buf);
4387 i40e_fill_default_direct_cmd_desc(&desc,
4388 i40e_aqc_opc_get_switch_resource_alloc);
4390 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4391 if (length > I40E_AQ_LARGE_BUF)
4392 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4394 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4396 if (!status && num_entries)
4397 *num_entries = cmd_resp->num_entries;
4403 * i40e_aq_delete_element - Delete switch element
4404 * @hw: pointer to the hw struct
4405 * @seid: the SEID to delete from the switch
4406 * @cmd_details: pointer to command details structure or NULL
4408 * This deletes a switch element from the switch.
4410 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4411 struct i40e_asq_cmd_details *cmd_details)
4413 struct i40e_aq_desc desc;
4414 struct i40e_aqc_switch_seid *cmd =
4415 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4416 enum i40e_status_code status;
4419 return I40E_ERR_PARAM;
4421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4423 cmd->seid = CPU_TO_LE16(seid);
4425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4431 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4432 * @hw: pointer to the hw struct
4433 * @flags: component flags
4434 * @mac_seid: uplink seid (MAC SEID)
4435 * @vsi_seid: connected vsi seid
4436 * @ret_seid: seid of create pv component
4438 * This instantiates an i40e port virtualizer with specified flags.
4439 * Depending on specified flags the port virtualizer can act as a
4440 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4442 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4443 u16 mac_seid, u16 vsi_seid,
4446 struct i40e_aq_desc desc;
4447 struct i40e_aqc_add_update_pv *cmd =
4448 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4449 struct i40e_aqc_add_update_pv_completion *resp =
4450 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4451 enum i40e_status_code status;
4454 return I40E_ERR_PARAM;
4456 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4457 cmd->command_flags = CPU_TO_LE16(flags);
4458 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4459 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4461 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4462 if (!status && ret_seid)
4463 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4469 * i40e_aq_add_tag - Add an S/E-tag
4470 * @hw: pointer to the hw struct
4471 * @direct_to_queue: should s-tag direct flow to a specific queue
4472 * @vsi_seid: VSI SEID to use this tag
4473 * @tag: value of the tag
4474 * @queue_num: queue number, only valid is direct_to_queue is true
4475 * @tags_used: return value, number of tags in use by this PF
4476 * @tags_free: return value, number of unallocated tags
4477 * @cmd_details: pointer to command details structure or NULL
4479 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4480 * the number of tags allocated by the PF, and the number of unallocated
4483 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4484 u16 vsi_seid, u16 tag, u16 queue_num,
4485 u16 *tags_used, u16 *tags_free,
4486 struct i40e_asq_cmd_details *cmd_details)
4488 struct i40e_aq_desc desc;
4489 struct i40e_aqc_add_tag *cmd =
4490 (struct i40e_aqc_add_tag *)&desc.params.raw;
4491 struct i40e_aqc_add_remove_tag_completion *resp =
4492 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4493 enum i40e_status_code status;
4496 return I40E_ERR_PARAM;
4498 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4500 cmd->seid = CPU_TO_LE16(vsi_seid);
4501 cmd->tag = CPU_TO_LE16(tag);
4502 if (direct_to_queue) {
4503 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4504 cmd->queue_number = CPU_TO_LE16(queue_num);
4507 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4510 if (tags_used != NULL)
4511 *tags_used = LE16_TO_CPU(resp->tags_used);
4512 if (tags_free != NULL)
4513 *tags_free = LE16_TO_CPU(resp->tags_free);
4520 * i40e_aq_remove_tag - Remove an S- or E-tag
4521 * @hw: pointer to the hw struct
4522 * @vsi_seid: VSI SEID this tag is associated with
4523 * @tag: value of the S-tag to delete
4524 * @tags_used: return value, number of tags in use by this PF
4525 * @tags_free: return value, number of unallocated tags
4526 * @cmd_details: pointer to command details structure or NULL
4528 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4529 * the number of tags allocated by the PF, and the number of unallocated
4532 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4533 u16 tag, u16 *tags_used, u16 *tags_free,
4534 struct i40e_asq_cmd_details *cmd_details)
4536 struct i40e_aq_desc desc;
4537 struct i40e_aqc_remove_tag *cmd =
4538 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4539 struct i40e_aqc_add_remove_tag_completion *resp =
4540 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4541 enum i40e_status_code status;
4544 return I40E_ERR_PARAM;
4546 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4548 cmd->seid = CPU_TO_LE16(vsi_seid);
4549 cmd->tag = CPU_TO_LE16(tag);
4551 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4554 if (tags_used != NULL)
4555 *tags_used = LE16_TO_CPU(resp->tags_used);
4556 if (tags_free != NULL)
4557 *tags_free = LE16_TO_CPU(resp->tags_free);
4564 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4565 * @hw: pointer to the hw struct
4566 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4567 * @etag: value of E-tag to add
4568 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4569 * @buf: address of indirect buffer
4570 * @tags_used: return value, number of E-tags in use by this port
4571 * @tags_free: return value, number of unallocated M-tags
4572 * @cmd_details: pointer to command details structure or NULL
4574 * This associates a multicast E-tag to a port virtualizer. It will return
4575 * the number of tags allocated by the PF, and the number of unallocated
4578 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4579 * num_tags_in_buf long.
4581 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4582 u16 etag, u8 num_tags_in_buf, void *buf,
4583 u16 *tags_used, u16 *tags_free,
4584 struct i40e_asq_cmd_details *cmd_details)
4586 struct i40e_aq_desc desc;
4587 struct i40e_aqc_add_remove_mcast_etag *cmd =
4588 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4589 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4590 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4591 enum i40e_status_code status;
4592 u16 length = sizeof(u16) * num_tags_in_buf;
4594 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4595 return I40E_ERR_PARAM;
4597 i40e_fill_default_direct_cmd_desc(&desc,
4598 i40e_aqc_opc_add_multicast_etag);
4600 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4601 cmd->etag = CPU_TO_LE16(etag);
4602 cmd->num_unicast_etags = num_tags_in_buf;
4604 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4605 if (length > I40E_AQ_LARGE_BUF)
4606 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4608 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4611 if (tags_used != NULL)
4612 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4613 if (tags_free != NULL)
4614 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4621 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4622 * @hw: pointer to the hw struct
4623 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4624 * @etag: value of the E-tag to remove
4625 * @tags_used: return value, number of tags in use by this port
4626 * @tags_free: return value, number of unallocated tags
4627 * @cmd_details: pointer to command details structure or NULL
4629 * This deletes an E-tag from the port virtualizer. It will return
4630 * the number of tags allocated by the port, and the number of unallocated
4633 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4634 u16 etag, u16 *tags_used, u16 *tags_free,
4635 struct i40e_asq_cmd_details *cmd_details)
4637 struct i40e_aq_desc desc;
4638 struct i40e_aqc_add_remove_mcast_etag *cmd =
4639 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4640 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4641 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4642 enum i40e_status_code status;
4646 return I40E_ERR_PARAM;
4648 i40e_fill_default_direct_cmd_desc(&desc,
4649 i40e_aqc_opc_remove_multicast_etag);
4651 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4652 cmd->etag = CPU_TO_LE16(etag);
4654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4657 if (tags_used != NULL)
4658 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4659 if (tags_free != NULL)
4660 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4667 * i40e_aq_update_tag - Update an S/E-tag
4668 * @hw: pointer to the hw struct
4669 * @vsi_seid: VSI SEID using this S-tag
4670 * @old_tag: old tag value
4671 * @new_tag: new tag value
4672 * @tags_used: return value, number of tags in use by this PF
4673 * @tags_free: return value, number of unallocated tags
4674 * @cmd_details: pointer to command details structure or NULL
4676 * This updates the value of the tag currently attached to this VSI
4677 * in the switch complex. It will return the number of tags allocated
4678 * by the PF, and the number of unallocated tags available.
4680 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4681 u16 old_tag, u16 new_tag, u16 *tags_used,
4683 struct i40e_asq_cmd_details *cmd_details)
4685 struct i40e_aq_desc desc;
4686 struct i40e_aqc_update_tag *cmd =
4687 (struct i40e_aqc_update_tag *)&desc.params.raw;
4688 struct i40e_aqc_update_tag_completion *resp =
4689 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4690 enum i40e_status_code status;
4693 return I40E_ERR_PARAM;
4695 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4697 cmd->seid = CPU_TO_LE16(vsi_seid);
4698 cmd->old_tag = CPU_TO_LE16(old_tag);
4699 cmd->new_tag = CPU_TO_LE16(new_tag);
4701 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4704 if (tags_used != NULL)
4705 *tags_used = LE16_TO_CPU(resp->tags_used);
4706 if (tags_free != NULL)
4707 *tags_free = LE16_TO_CPU(resp->tags_free);
4714 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4715 * @hw: pointer to the hw struct
4716 * @tcmap: TC map for request/release any ignore PFC condition
4717 * @request: request or release ignore PFC condition
4718 * @tcmap_ret: return TCs for which PFC is currently ignored
4719 * @cmd_details: pointer to command details structure or NULL
4721 * This sends out request/release to ignore PFC condition for a TC.
4722 * It will return the TCs for which PFC is currently ignored.
4724 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4725 bool request, u8 *tcmap_ret,
4726 struct i40e_asq_cmd_details *cmd_details)
4728 struct i40e_aq_desc desc;
4729 struct i40e_aqc_pfc_ignore *cmd_resp =
4730 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4731 enum i40e_status_code status;
4733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4736 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4738 cmd_resp->tc_bitmap = tcmap;
4740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4743 if (tcmap_ret != NULL)
4744 *tcmap_ret = cmd_resp->tc_bitmap;
4751 * i40e_aq_dcb_updated - DCB Updated Command
4752 * @hw: pointer to the hw struct
4753 * @cmd_details: pointer to command details structure or NULL
4755 * When LLDP is handled in PF this command is used by the PF
4756 * to notify EMP that a DCB setting is modified.
4757 * When LLDP is handled in EMP this command is used by the PF
4758 * to notify EMP whenever one of the following parameters get
4760 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4761 * - PCIRTT in PRTDCB_GENC.PCIRTT
4762 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4763 * EMP will return when the shared RPB settings have been
4764 * recomputed and modified. The retval field in the descriptor
4765 * will be set to 0 when RPB is modified.
4767 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4768 struct i40e_asq_cmd_details *cmd_details)
4770 struct i40e_aq_desc desc;
4771 enum i40e_status_code status;
4773 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4775 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4781 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4782 * @hw: pointer to the hw struct
4783 * @seid: defines the SEID of the switch for which the stats are requested
4784 * @vlan_id: the VLAN ID for which the statistics are requested
4785 * @stat_index: index of the statistics counters block assigned to this VLAN
4786 * @cmd_details: pointer to command details structure or NULL
4788 * XL710 supports 128 smonVlanStats counters.This command is used to
4789 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4792 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4793 u16 vlan_id, u16 *stat_index,
4794 struct i40e_asq_cmd_details *cmd_details)
4796 struct i40e_aq_desc desc;
4797 struct i40e_aqc_add_remove_statistics *cmd_resp =
4798 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4799 enum i40e_status_code status;
4801 if ((seid == 0) || (stat_index == NULL))
4802 return I40E_ERR_PARAM;
4804 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4806 cmd_resp->seid = CPU_TO_LE16(seid);
4807 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4809 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4811 if (!status && stat_index)
4812 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4818 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4819 * @hw: pointer to the hw struct
4820 * @seid: defines the SEID of the switch for which the stats are requested
4821 * @vlan_id: the VLAN ID for which the statistics are requested
4822 * @stat_index: index of the statistics counters block assigned to this VLAN
4823 * @cmd_details: pointer to command details structure or NULL
4825 * XL710 supports 128 smonVlanStats counters.This command is used to
4826 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4829 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4830 u16 vlan_id, u16 stat_index,
4831 struct i40e_asq_cmd_details *cmd_details)
4833 struct i40e_aq_desc desc;
4834 struct i40e_aqc_add_remove_statistics *cmd =
4835 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4836 enum i40e_status_code status;
4839 return I40E_ERR_PARAM;
4841 i40e_fill_default_direct_cmd_desc(&desc,
4842 i40e_aqc_opc_remove_statistics);
4844 cmd->seid = CPU_TO_LE16(seid);
4845 cmd->vlan = CPU_TO_LE16(vlan_id);
4846 cmd->stat_index = CPU_TO_LE16(stat_index);
4848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4854 * i40e_aq_set_port_parameters - set physical port parameters.
4855 * @hw: pointer to the hw struct
4856 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4857 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4858 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4859 * @double_vlan: if set double VLAN is enabled
4860 * @cmd_details: pointer to command details structure or NULL
4862 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4863 u16 bad_frame_vsi, bool save_bad_pac,
4864 bool pad_short_pac, bool double_vlan,
4865 struct i40e_asq_cmd_details *cmd_details)
4867 struct i40e_aqc_set_port_parameters *cmd;
4868 enum i40e_status_code status;
4869 struct i40e_aq_desc desc;
4870 u16 command_flags = 0;
4872 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4874 i40e_fill_default_direct_cmd_desc(&desc,
4875 i40e_aqc_opc_set_port_parameters);
4877 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4879 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4881 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4883 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4884 cmd->command_flags = CPU_TO_LE16(command_flags);
4886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4892 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4893 * @hw: pointer to the hw struct
4894 * @seid: seid for the physical port/switching component/vsi
4895 * @buff: Indirect buffer to hold data parameters and response
4896 * @buff_size: Indirect buffer size
4897 * @opcode: Tx scheduler AQ command opcode
4898 * @cmd_details: pointer to command details structure or NULL
4900 * Generic command handler for Tx scheduler AQ commands
4902 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4903 void *buff, u16 buff_size,
4904 enum i40e_admin_queue_opc opcode,
4905 struct i40e_asq_cmd_details *cmd_details)
4907 struct i40e_aq_desc desc;
4908 struct i40e_aqc_tx_sched_ind *cmd =
4909 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4910 enum i40e_status_code status;
4911 bool cmd_param_flag = false;
4914 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4915 case i40e_aqc_opc_configure_vsi_tc_bw:
4916 case i40e_aqc_opc_enable_switching_comp_ets:
4917 case i40e_aqc_opc_modify_switching_comp_ets:
4918 case i40e_aqc_opc_disable_switching_comp_ets:
4919 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4920 case i40e_aqc_opc_configure_switching_comp_bw_config:
4921 cmd_param_flag = true;
4923 case i40e_aqc_opc_query_vsi_bw_config:
4924 case i40e_aqc_opc_query_vsi_ets_sla_config:
4925 case i40e_aqc_opc_query_switching_comp_ets_config:
4926 case i40e_aqc_opc_query_port_ets_config:
4927 case i40e_aqc_opc_query_switching_comp_bw_config:
4928 cmd_param_flag = false;
4931 return I40E_ERR_PARAM;
4934 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4936 /* Indirect command */
4937 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4939 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4940 if (buff_size > I40E_AQ_LARGE_BUF)
4941 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4943 desc.datalen = CPU_TO_LE16(buff_size);
4945 cmd->vsi_seid = CPU_TO_LE16(seid);
4947 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4953 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4954 * @hw: pointer to the hw struct
4956 * @credit: BW limit credits (0 = disabled)
4957 * @max_credit: Max BW limit credits
4958 * @cmd_details: pointer to command details structure or NULL
4960 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4961 u16 seid, u16 credit, u8 max_credit,
4962 struct i40e_asq_cmd_details *cmd_details)
4964 struct i40e_aq_desc desc;
4965 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4966 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4967 enum i40e_status_code status;
4969 i40e_fill_default_direct_cmd_desc(&desc,
4970 i40e_aqc_opc_configure_vsi_bw_limit);
4972 cmd->vsi_seid = CPU_TO_LE16(seid);
4973 cmd->credit = CPU_TO_LE16(credit);
4974 cmd->max_credit = max_credit;
4976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4982 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4983 * @hw: pointer to the hw struct
4984 * @seid: switching component seid
4985 * @credit: BW limit credits (0 = disabled)
4986 * @max_bw: Max BW limit credits
4987 * @cmd_details: pointer to command details structure or NULL
4989 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4990 u16 seid, u16 credit, u8 max_bw,
4991 struct i40e_asq_cmd_details *cmd_details)
4993 struct i40e_aq_desc desc;
4994 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4995 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4996 enum i40e_status_code status;
4998 i40e_fill_default_direct_cmd_desc(&desc,
4999 i40e_aqc_opc_configure_switching_comp_bw_limit);
5001 cmd->seid = CPU_TO_LE16(seid);
5002 cmd->credit = CPU_TO_LE16(credit);
5003 cmd->max_bw = max_bw;
5005 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5011 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5012 * @hw: pointer to the hw struct
5014 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5015 * @cmd_details: pointer to command details structure or NULL
5017 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5019 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5020 struct i40e_asq_cmd_details *cmd_details)
5022 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5023 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5028 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5029 * @hw: pointer to the hw struct
5031 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5032 * @cmd_details: pointer to command details structure or NULL
5034 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5036 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5037 struct i40e_asq_cmd_details *cmd_details)
5039 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5040 i40e_aqc_opc_configure_vsi_tc_bw,
5045 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5046 * @hw: pointer to the hw struct
5047 * @seid: seid of the switching component connected to Physical Port
5048 * @ets_data: Buffer holding ETS parameters
5049 * @cmd_details: pointer to command details structure or NULL
5051 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5053 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5054 enum i40e_admin_queue_opc opcode,
5055 struct i40e_asq_cmd_details *cmd_details)
5057 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5058 sizeof(*ets_data), opcode, cmd_details);
5062 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5063 * @hw: pointer to the hw struct
5064 * @seid: seid of the switching component
5065 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5066 * @cmd_details: pointer to command details structure or NULL
5068 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5070 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5071 struct i40e_asq_cmd_details *cmd_details)
5073 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5074 i40e_aqc_opc_configure_switching_comp_bw_config,
5079 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5080 * @hw: pointer to the hw struct
5081 * @seid: seid of the switching component
5082 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5083 * @cmd_details: pointer to command details structure or NULL
5085 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5086 struct i40e_hw *hw, u16 seid,
5087 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5088 struct i40e_asq_cmd_details *cmd_details)
5090 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5091 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5096 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5097 * @hw: pointer to the hw struct
5098 * @seid: seid of the VSI
5099 * @bw_data: Buffer to hold VSI BW configuration
5100 * @cmd_details: pointer to command details structure or NULL
5102 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5104 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5105 struct i40e_asq_cmd_details *cmd_details)
5107 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5108 i40e_aqc_opc_query_vsi_bw_config,
5113 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5114 * @hw: pointer to the hw struct
5115 * @seid: seid of the VSI
5116 * @bw_data: Buffer to hold VSI BW configuration per TC
5117 * @cmd_details: pointer to command details structure or NULL
5119 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5121 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5122 struct i40e_asq_cmd_details *cmd_details)
5124 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5125 i40e_aqc_opc_query_vsi_ets_sla_config,
5130 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5131 * @hw: pointer to the hw struct
5132 * @seid: seid of the switching component
5133 * @bw_data: Buffer to hold switching component's per TC BW config
5134 * @cmd_details: pointer to command details structure or NULL
5136 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5138 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5139 struct i40e_asq_cmd_details *cmd_details)
5141 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5142 i40e_aqc_opc_query_switching_comp_ets_config,
5147 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5148 * @hw: pointer to the hw struct
5149 * @seid: seid of the VSI or switching component connected to Physical Port
5150 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5151 * @cmd_details: pointer to command details structure or NULL
5153 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5155 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5156 struct i40e_asq_cmd_details *cmd_details)
5158 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5159 i40e_aqc_opc_query_port_ets_config,
5164 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5165 * @hw: pointer to the hw struct
5166 * @seid: seid of the switching component
5167 * @bw_data: Buffer to hold switching component's BW configuration
5168 * @cmd_details: pointer to command details structure or NULL
5170 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5172 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5173 struct i40e_asq_cmd_details *cmd_details)
5175 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5176 i40e_aqc_opc_query_switching_comp_bw_config,
5181 * i40e_validate_filter_settings
5182 * @hw: pointer to the hardware structure
5183 * @settings: Filter control settings
5185 * Check and validate the filter control settings passed.
5186 * The function checks for the valid filter/context sizes being
5187 * passed for FCoE and PE.
5189 * Returns I40E_SUCCESS if the values passed are valid and within
5190 * range else returns an error.
5192 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5193 struct i40e_filter_control_settings *settings)
5195 u32 fcoe_cntx_size, fcoe_filt_size;
5196 u32 pe_cntx_size, pe_filt_size;
5201 /* Validate FCoE settings passed */
5202 switch (settings->fcoe_filt_num) {
5203 case I40E_HASH_FILTER_SIZE_1K:
5204 case I40E_HASH_FILTER_SIZE_2K:
5205 case I40E_HASH_FILTER_SIZE_4K:
5206 case I40E_HASH_FILTER_SIZE_8K:
5207 case I40E_HASH_FILTER_SIZE_16K:
5208 case I40E_HASH_FILTER_SIZE_32K:
5209 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5210 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5213 return I40E_ERR_PARAM;
5216 switch (settings->fcoe_cntx_num) {
5217 case I40E_DMA_CNTX_SIZE_512:
5218 case I40E_DMA_CNTX_SIZE_1K:
5219 case I40E_DMA_CNTX_SIZE_2K:
5220 case I40E_DMA_CNTX_SIZE_4K:
5221 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5222 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5225 return I40E_ERR_PARAM;
5228 /* Validate PE settings passed */
5229 switch (settings->pe_filt_num) {
5230 case I40E_HASH_FILTER_SIZE_1K:
5231 case I40E_HASH_FILTER_SIZE_2K:
5232 case I40E_HASH_FILTER_SIZE_4K:
5233 case I40E_HASH_FILTER_SIZE_8K:
5234 case I40E_HASH_FILTER_SIZE_16K:
5235 case I40E_HASH_FILTER_SIZE_32K:
5236 case I40E_HASH_FILTER_SIZE_64K:
5237 case I40E_HASH_FILTER_SIZE_128K:
5238 case I40E_HASH_FILTER_SIZE_256K:
5239 case I40E_HASH_FILTER_SIZE_512K:
5240 case I40E_HASH_FILTER_SIZE_1M:
5241 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5242 pe_filt_size <<= (u32)settings->pe_filt_num;
5245 return I40E_ERR_PARAM;
5248 switch (settings->pe_cntx_num) {
5249 case I40E_DMA_CNTX_SIZE_512:
5250 case I40E_DMA_CNTX_SIZE_1K:
5251 case I40E_DMA_CNTX_SIZE_2K:
5252 case I40E_DMA_CNTX_SIZE_4K:
5253 case I40E_DMA_CNTX_SIZE_8K:
5254 case I40E_DMA_CNTX_SIZE_16K:
5255 case I40E_DMA_CNTX_SIZE_32K:
5256 case I40E_DMA_CNTX_SIZE_64K:
5257 case I40E_DMA_CNTX_SIZE_128K:
5258 case I40E_DMA_CNTX_SIZE_256K:
5259 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5260 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5263 return I40E_ERR_PARAM;
5266 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5267 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5268 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5269 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5270 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5271 return I40E_ERR_INVALID_SIZE;
5273 return I40E_SUCCESS;
5277 * i40e_set_filter_control
5278 * @hw: pointer to the hardware structure
5279 * @settings: Filter control settings
5281 * Set the Queue Filters for PE/FCoE and enable filters required
5282 * for a single PF. It is expected that these settings are programmed
5283 * at the driver initialization time.
5285 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5286 struct i40e_filter_control_settings *settings)
5288 enum i40e_status_code ret = I40E_SUCCESS;
5289 u32 hash_lut_size = 0;
5293 return I40E_ERR_PARAM;
5295 /* Validate the input settings */
5296 ret = i40e_validate_filter_settings(hw, settings);
5300 /* Read the PF Queue Filter control register */
5301 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5303 /* Program required PE hash buckets for the PF */
5304 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5305 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5306 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5307 /* Program required PE contexts for the PF */
5308 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5309 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5310 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5312 /* Program required FCoE hash buckets for the PF */
5313 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5314 val |= ((u32)settings->fcoe_filt_num <<
5315 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5316 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5317 /* Program required FCoE DDP contexts for the PF */
5318 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5319 val |= ((u32)settings->fcoe_cntx_num <<
5320 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5321 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5323 /* Program Hash LUT size for the PF */
5324 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5325 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5327 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5328 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5330 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5331 if (settings->enable_fdir)
5332 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5333 if (settings->enable_ethtype)
5334 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5335 if (settings->enable_macvlan)
5336 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5338 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5340 return I40E_SUCCESS;
5344 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5345 * @hw: pointer to the hw struct
5346 * @mac_addr: MAC address to use in the filter
5347 * @ethtype: Ethertype to use in the filter
5348 * @flags: Flags that needs to be applied to the filter
5349 * @vsi_seid: seid of the control VSI
5350 * @queue: VSI queue number to send the packet to
5351 * @is_add: Add control packet filter if True else remove
5352 * @stats: Structure to hold information on control filter counts
5353 * @cmd_details: pointer to command details structure or NULL
5355 * This command will Add or Remove control packet filter for a control VSI.
5356 * In return it will update the total number of perfect filter count in
5359 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5360 u8 *mac_addr, u16 ethtype, u16 flags,
5361 u16 vsi_seid, u16 queue, bool is_add,
5362 struct i40e_control_filter_stats *stats,
5363 struct i40e_asq_cmd_details *cmd_details)
5365 struct i40e_aq_desc desc;
5366 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5367 (struct i40e_aqc_add_remove_control_packet_filter *)
5369 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5370 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5372 enum i40e_status_code status;
5375 return I40E_ERR_PARAM;
5378 i40e_fill_default_direct_cmd_desc(&desc,
5379 i40e_aqc_opc_add_control_packet_filter);
5380 cmd->queue = CPU_TO_LE16(queue);
5382 i40e_fill_default_direct_cmd_desc(&desc,
5383 i40e_aqc_opc_remove_control_packet_filter);
5387 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5388 I40E_NONDMA_TO_NONDMA);
5390 cmd->etype = CPU_TO_LE16(ethtype);
5391 cmd->flags = CPU_TO_LE16(flags);
5392 cmd->seid = CPU_TO_LE16(vsi_seid);
5394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5396 if (!status && stats) {
5397 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5398 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5399 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5400 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5407 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5408 * @hw: pointer to the hw struct
5409 * @seid: VSI seid to add ethertype filter from
5411 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5412 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5415 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5416 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5417 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5418 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5419 enum i40e_status_code status;
5421 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5422 seid, 0, true, NULL,
5425 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5429 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5430 * @filters: list of cloud filters
5431 * @filter_count: length of list
5433 * There's an issue in the device where the Geneve VNI layout needs
5434 * to be shifted 1 byte over from the VxLAN VNI
5436 STATIC void i40e_fix_up_geneve_vni(
5437 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5440 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5443 for (i = 0; i < filter_count; i++) {
5447 tnl_type = (le16_to_cpu(f[i].flags) &
5448 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5449 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5450 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5451 ti = le32_to_cpu(f[i].tenant_id);
5452 f[i].tenant_id = cpu_to_le32(ti << 8);
5458 * i40e_aq_add_cloud_filters
5459 * @hw: pointer to the hardware structure
5460 * @seid: VSI seid to add cloud filters from
5461 * @filters: Buffer which contains the filters to be added
5462 * @filter_count: number of filters contained in the buffer
5464 * Set the cloud filters for a given VSI. The contents of the
5465 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5466 * in by the caller of the function.
5469 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5471 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5474 struct i40e_aq_desc desc;
5475 struct i40e_aqc_add_remove_cloud_filters *cmd =
5476 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5477 enum i40e_status_code status;
5480 i40e_fill_default_direct_cmd_desc(&desc,
5481 i40e_aqc_opc_add_cloud_filters);
5483 buff_len = filter_count * sizeof(*filters);
5484 desc.datalen = CPU_TO_LE16(buff_len);
5485 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5486 cmd->num_filters = filter_count;
5487 cmd->seid = CPU_TO_LE16(seid);
5489 i40e_fix_up_geneve_vni(filters, filter_count);
5491 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5497 * i40e_aq_remove_cloud_filters
5498 * @hw: pointer to the hardware structure
5499 * @seid: VSI seid to remove cloud filters from
5500 * @filters: Buffer which contains the filters to be removed
5501 * @filter_count: number of filters contained in the buffer
5503 * Remove the cloud filters for a given VSI. The contents of the
5504 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5505 * in by the caller of the function.
5508 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5510 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5513 struct i40e_aq_desc desc;
5514 struct i40e_aqc_add_remove_cloud_filters *cmd =
5515 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5516 enum i40e_status_code status;
5519 i40e_fill_default_direct_cmd_desc(&desc,
5520 i40e_aqc_opc_remove_cloud_filters);
5522 buff_len = filter_count * sizeof(*filters);
5523 desc.datalen = CPU_TO_LE16(buff_len);
5524 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5525 cmd->num_filters = filter_count;
5526 cmd->seid = CPU_TO_LE16(seid);
5528 i40e_fix_up_geneve_vni(filters, filter_count);
5530 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5536 * i40e_aq_alternate_write
5537 * @hw: pointer to the hardware structure
5538 * @reg_addr0: address of first dword to be read
5539 * @reg_val0: value to be written under 'reg_addr0'
5540 * @reg_addr1: address of second dword to be read
5541 * @reg_val1: value to be written under 'reg_addr1'
5543 * Write one or two dwords to alternate structure. Fields are indicated
5544 * by 'reg_addr0' and 'reg_addr1' register numbers.
5547 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5548 u32 reg_addr0, u32 reg_val0,
5549 u32 reg_addr1, u32 reg_val1)
5551 struct i40e_aq_desc desc;
5552 struct i40e_aqc_alternate_write *cmd_resp =
5553 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5554 enum i40e_status_code status;
5556 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5557 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5558 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5559 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5560 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5562 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5568 * i40e_aq_alternate_write_indirect
5569 * @hw: pointer to the hardware structure
5570 * @addr: address of a first register to be modified
5571 * @dw_count: number of alternate structure fields to write
5572 * @buffer: pointer to the command buffer
5574 * Write 'dw_count' dwords from 'buffer' to alternate structure
5575 * starting at 'addr'.
5578 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5579 u32 addr, u32 dw_count, void *buffer)
5581 struct i40e_aq_desc desc;
5582 struct i40e_aqc_alternate_ind_write *cmd_resp =
5583 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5584 enum i40e_status_code status;
5587 return I40E_ERR_PARAM;
5589 /* Indirect command */
5590 i40e_fill_default_direct_cmd_desc(&desc,
5591 i40e_aqc_opc_alternate_write_indirect);
5593 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5594 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5595 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5596 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5598 cmd_resp->address = CPU_TO_LE32(addr);
5599 cmd_resp->length = CPU_TO_LE32(dw_count);
5601 status = i40e_asq_send_command(hw, &desc, buffer,
5602 I40E_LO_DWORD(4*dw_count), NULL);
5608 * i40e_aq_alternate_read
5609 * @hw: pointer to the hardware structure
5610 * @reg_addr0: address of first dword to be read
5611 * @reg_val0: pointer for data read from 'reg_addr0'
5612 * @reg_addr1: address of second dword to be read
5613 * @reg_val1: pointer for data read from 'reg_addr1'
5615 * Read one or two dwords from alternate structure. Fields are indicated
5616 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5617 * is not passed then only register at 'reg_addr0' is read.
5620 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5621 u32 reg_addr0, u32 *reg_val0,
5622 u32 reg_addr1, u32 *reg_val1)
5624 struct i40e_aq_desc desc;
5625 struct i40e_aqc_alternate_write *cmd_resp =
5626 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5627 enum i40e_status_code status;
5629 if (reg_val0 == NULL)
5630 return I40E_ERR_PARAM;
5632 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5633 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5634 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5636 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5638 if (status == I40E_SUCCESS) {
5639 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5641 if (reg_val1 != NULL)
5642 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5649 * i40e_aq_alternate_read_indirect
5650 * @hw: pointer to the hardware structure
5651 * @addr: address of the alternate structure field
5652 * @dw_count: number of alternate structure fields to read
5653 * @buffer: pointer to the command buffer
5655 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5656 * place them in 'buffer'. The buffer should be allocated by caller.
5659 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5660 u32 addr, u32 dw_count, void *buffer)
5662 struct i40e_aq_desc desc;
5663 struct i40e_aqc_alternate_ind_write *cmd_resp =
5664 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5665 enum i40e_status_code status;
5668 return I40E_ERR_PARAM;
5670 /* Indirect command */
5671 i40e_fill_default_direct_cmd_desc(&desc,
5672 i40e_aqc_opc_alternate_read_indirect);
5674 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5675 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5676 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5677 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5679 cmd_resp->address = CPU_TO_LE32(addr);
5680 cmd_resp->length = CPU_TO_LE32(dw_count);
5682 status = i40e_asq_send_command(hw, &desc, buffer,
5683 I40E_LO_DWORD(4*dw_count), NULL);
5689 * i40e_aq_alternate_clear
5690 * @hw: pointer to the HW structure.
5692 * Clear the alternate structures of the port from which the function
5696 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5698 struct i40e_aq_desc desc;
5699 enum i40e_status_code status;
5701 i40e_fill_default_direct_cmd_desc(&desc,
5702 i40e_aqc_opc_alternate_clear_port);
5704 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5710 * i40e_aq_alternate_write_done
5711 * @hw: pointer to the HW structure.
5712 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5713 * @reset_needed: indicates the SW should trigger GLOBAL reset
5715 * Indicates to the FW that alternate structures have been changed.
5718 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5719 u8 bios_mode, bool *reset_needed)
5721 struct i40e_aq_desc desc;
5722 struct i40e_aqc_alternate_write_done *cmd =
5723 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5724 enum i40e_status_code status;
5726 if (reset_needed == NULL)
5727 return I40E_ERR_PARAM;
5729 i40e_fill_default_direct_cmd_desc(&desc,
5730 i40e_aqc_opc_alternate_write_done);
5732 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5734 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5735 if (!status && reset_needed)
5736 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5737 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5743 * i40e_aq_set_oem_mode
5744 * @hw: pointer to the HW structure.
5745 * @oem_mode: the OEM mode to be used
5747 * Sets the device to a specific operating mode. Currently the only supported
5748 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5751 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5754 struct i40e_aq_desc desc;
5755 struct i40e_aqc_alternate_write_done *cmd =
5756 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5757 enum i40e_status_code status;
5759 i40e_fill_default_direct_cmd_desc(&desc,
5760 i40e_aqc_opc_alternate_set_mode);
5762 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5764 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5770 * i40e_aq_resume_port_tx
5771 * @hw: pointer to the hardware structure
5772 * @cmd_details: pointer to command details structure or NULL
5774 * Resume port's Tx traffic
5776 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5777 struct i40e_asq_cmd_details *cmd_details)
5779 struct i40e_aq_desc desc;
5780 enum i40e_status_code status;
5782 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5784 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5790 * i40e_set_pci_config_data - store PCI bus info
5791 * @hw: pointer to hardware structure
5792 * @link_status: the link status word from PCI config space
5794 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5796 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5798 hw->bus.type = i40e_bus_type_pci_express;
5800 switch (link_status & I40E_PCI_LINK_WIDTH) {
5801 case I40E_PCI_LINK_WIDTH_1:
5802 hw->bus.width = i40e_bus_width_pcie_x1;
5804 case I40E_PCI_LINK_WIDTH_2:
5805 hw->bus.width = i40e_bus_width_pcie_x2;
5807 case I40E_PCI_LINK_WIDTH_4:
5808 hw->bus.width = i40e_bus_width_pcie_x4;
5810 case I40E_PCI_LINK_WIDTH_8:
5811 hw->bus.width = i40e_bus_width_pcie_x8;
5814 hw->bus.width = i40e_bus_width_unknown;
5818 switch (link_status & I40E_PCI_LINK_SPEED) {
5819 case I40E_PCI_LINK_SPEED_2500:
5820 hw->bus.speed = i40e_bus_speed_2500;
5822 case I40E_PCI_LINK_SPEED_5000:
5823 hw->bus.speed = i40e_bus_speed_5000;
5825 case I40E_PCI_LINK_SPEED_8000:
5826 hw->bus.speed = i40e_bus_speed_8000;
5829 hw->bus.speed = i40e_bus_speed_unknown;
5835 * i40e_aq_debug_dump
5836 * @hw: pointer to the hardware structure
5837 * @cluster_id: specific cluster to dump
5838 * @table_id: table id within cluster
5839 * @start_index: index of line in the block to read
5840 * @buff_size: dump buffer size
5841 * @buff: dump buffer
5842 * @ret_buff_size: actual buffer size returned
5843 * @ret_next_table: next block to read
5844 * @ret_next_index: next index to read
5846 * Dump internal FW/HW data for debug purposes.
5849 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5850 u8 table_id, u32 start_index, u16 buff_size,
5851 void *buff, u16 *ret_buff_size,
5852 u8 *ret_next_table, u32 *ret_next_index,
5853 struct i40e_asq_cmd_details *cmd_details)
5855 struct i40e_aq_desc desc;
5856 struct i40e_aqc_debug_dump_internals *cmd =
5857 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5858 struct i40e_aqc_debug_dump_internals *resp =
5859 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5860 enum i40e_status_code status;
5862 if (buff_size == 0 || !buff)
5863 return I40E_ERR_PARAM;
5865 i40e_fill_default_direct_cmd_desc(&desc,
5866 i40e_aqc_opc_debug_dump_internals);
5867 /* Indirect Command */
5868 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5869 if (buff_size > I40E_AQ_LARGE_BUF)
5870 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5872 cmd->cluster_id = cluster_id;
5873 cmd->table_id = table_id;
5874 cmd->idx = CPU_TO_LE32(start_index);
5876 desc.datalen = CPU_TO_LE16(buff_size);
5878 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5880 if (ret_buff_size != NULL)
5881 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5882 if (ret_next_table != NULL)
5883 *ret_next_table = resp->table_id;
5884 if (ret_next_index != NULL)
5885 *ret_next_index = LE32_TO_CPU(resp->idx);
5892 * i40e_read_bw_from_alt_ram
5893 * @hw: pointer to the hardware structure
5894 * @max_bw: pointer for max_bw read
5895 * @min_bw: pointer for min_bw read
5896 * @min_valid: pointer for bool that is true if min_bw is a valid value
5897 * @max_valid: pointer for bool that is true if max_bw is a valid value
5899 * Read bw from the alternate ram for the given pf
5901 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5902 u32 *max_bw, u32 *min_bw,
5903 bool *min_valid, bool *max_valid)
5905 enum i40e_status_code status;
5906 u32 max_bw_addr, min_bw_addr;
5908 /* Calculate the address of the min/max bw registers */
5909 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5910 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5911 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5912 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5913 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5914 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5916 /* Read the bandwidths from alt ram */
5917 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5918 min_bw_addr, min_bw);
5920 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5925 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5934 * i40e_aq_configure_partition_bw
5935 * @hw: pointer to the hardware structure
5936 * @bw_data: Buffer holding valid pfs and bw limits
5937 * @cmd_details: pointer to command details
5939 * Configure partitions guaranteed/max bw
5941 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5942 struct i40e_aqc_configure_partition_bw_data *bw_data,
5943 struct i40e_asq_cmd_details *cmd_details)
5945 enum i40e_status_code status;
5946 struct i40e_aq_desc desc;
5947 u16 bwd_size = sizeof(*bw_data);
5949 i40e_fill_default_direct_cmd_desc(&desc,
5950 i40e_aqc_opc_configure_partition_bw);
5952 /* Indirect command */
5953 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5954 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5956 if (bwd_size > I40E_AQ_LARGE_BUF)
5957 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5959 desc.datalen = CPU_TO_LE16(bwd_size);
5961 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5967 * i40e_read_phy_register
5968 * @hw: pointer to the HW structure
5969 * @page: registers page number
5970 * @reg: register address in the page
5971 * @phy_adr: PHY address on MDIO interface
5972 * @value: PHY register value
5974 * Reads specified PHY register value
5976 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5977 u8 page, u16 reg, u8 phy_addr,
5980 enum i40e_status_code status = I40E_ERR_TIMEOUT;
5983 u8 port_num = (u8)hw->func_caps.mdio_port_num;
5985 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
5986 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5987 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5988 (I40E_MDIO_OPCODE_ADDRESS) |
5989 (I40E_MDIO_STCODE) |
5990 (I40E_GLGEN_MSCA_MDICMD_MASK) |
5991 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
5992 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
5994 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
5995 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
5996 status = I40E_SUCCESS;
5999 i40e_usec_delay(10);
6004 i40e_debug(hw, I40E_DEBUG_PHY,
6005 "PHY: Can't write command to external PHY.\n");
6009 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6010 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6011 (I40E_MDIO_OPCODE_READ) |
6012 (I40E_MDIO_STCODE) |
6013 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6014 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6015 status = I40E_ERR_TIMEOUT;
6017 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6019 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6020 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6021 status = I40E_SUCCESS;
6024 i40e_usec_delay(10);
6029 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6030 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6031 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6033 i40e_debug(hw, I40E_DEBUG_PHY,
6034 "PHY: Can't read register value from external PHY.\n");
6042 * i40e_write_phy_register
6043 * @hw: pointer to the HW structure
6044 * @page: registers page number
6045 * @reg: register address in the page
6046 * @phy_adr: PHY address on MDIO interface
6047 * @value: PHY register value
6049 * Writes value to specified PHY register
6051 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6052 u8 page, u16 reg, u8 phy_addr,
6055 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6058 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6060 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6061 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6062 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6063 (I40E_MDIO_OPCODE_ADDRESS) |
6064 (I40E_MDIO_STCODE) |
6065 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6066 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6067 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6069 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6070 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6071 status = I40E_SUCCESS;
6074 i40e_usec_delay(10);
6078 i40e_debug(hw, I40E_DEBUG_PHY,
6079 "PHY: Can't write command to external PHY.\n");
6083 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6084 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6086 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6087 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6088 (I40E_MDIO_OPCODE_WRITE) |
6089 (I40E_MDIO_STCODE) |
6090 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6091 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6092 status = I40E_ERR_TIMEOUT;
6094 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6096 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6097 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6098 status = I40E_SUCCESS;
6101 i40e_usec_delay(10);
6110 * i40e_get_phy_address
6111 * @hw: pointer to the HW structure
6112 * @dev_num: PHY port num that address we want
6113 * @phy_addr: Returned PHY address
6115 * Gets PHY address for current port
6117 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6119 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6120 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6122 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6126 * i40e_blink_phy_led
6127 * @hw: pointer to the HW structure
6128 * @time: time how long led will blinks in secs
6129 * @interval: gap between LED on and off in msecs
6131 * Blinks PHY link LED
6133 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6134 u32 time, u32 interval)
6136 enum i40e_status_code status = I40E_SUCCESS;
6141 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6145 i = rd32(hw, I40E_PFGEN_PORTNUM);
6146 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6147 phy_addr = i40e_get_phy_address(hw, port_num);
6149 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6151 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6152 led_addr, phy_addr, &led_reg);
6154 goto phy_blinking_end;
6156 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6158 status = i40e_write_phy_register(hw,
6159 I40E_PHY_COM_REG_PAGE,
6163 goto phy_blinking_end;
6168 if (time > 0 && interval > 0) {
6169 for (i = 0; i < time * 1000; i += interval) {
6170 status = i40e_read_phy_register(hw,
6171 I40E_PHY_COM_REG_PAGE,
6175 goto restore_config;
6176 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6179 led_reg = I40E_PHY_LED_MANUAL_ON;
6180 status = i40e_write_phy_register(hw,
6181 I40E_PHY_COM_REG_PAGE,
6185 goto restore_config;
6186 i40e_msec_delay(interval);
6191 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6199 * i40e_led_get_phy - return current on/off mode
6200 * @hw: pointer to the hw struct
6201 * @led_addr: address of led register to use
6202 * @val: original value of register to use
6205 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6208 enum i40e_status_code status = I40E_SUCCESS;
6216 temp_addr = I40E_PHY_LED_PROV_REG_1;
6217 i = rd32(hw, I40E_PFGEN_PORTNUM);
6218 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6219 phy_addr = i40e_get_phy_address(hw, port_num);
6221 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6223 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6224 temp_addr, phy_addr, ®_val);
6228 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6229 *led_addr = temp_addr;
6238 * @hw: pointer to the HW structure
6239 * @on: true or false
6240 * @mode: original val plus bit for set or ignore
6241 * Set led's on or off when controlled by the PHY
6244 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6245 u16 led_addr, u32 mode)
6247 enum i40e_status_code status = I40E_SUCCESS;
6254 i = rd32(hw, I40E_PFGEN_PORTNUM);
6255 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6256 phy_addr = i40e_get_phy_address(hw, port_num);
6258 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6259 phy_addr, &led_reg);
6263 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6265 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6266 led_addr, phy_addr, led_reg);
6270 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6271 led_addr, phy_addr, &led_reg);
6273 goto restore_config;
6275 led_reg = I40E_PHY_LED_MANUAL_ON;
6278 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6279 led_addr, phy_addr, led_reg);
6281 goto restore_config;
6282 if (mode & I40E_PHY_LED_MODE_ORIG) {
6283 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6284 status = i40e_write_phy_register(hw,
6285 I40E_PHY_COM_REG_PAGE,
6286 led_addr, phy_addr, led_ctl);
6290 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6294 #endif /* PF_DRIVER */
6297 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6298 * @hw: pointer to the hw struct
6299 * @reg_addr: register address
6300 * @reg_val: ptr to register value
6301 * @cmd_details: pointer to command details structure or NULL
6303 * Use the firmware to read the Rx control register,
6304 * especially useful if the Rx unit is under heavy pressure
6306 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6307 u32 reg_addr, u32 *reg_val,
6308 struct i40e_asq_cmd_details *cmd_details)
6310 struct i40e_aq_desc desc;
6311 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6312 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6313 enum i40e_status_code status;
6315 if (reg_val == NULL)
6316 return I40E_ERR_PARAM;
6318 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6320 cmd_resp->address = CPU_TO_LE32(reg_addr);
6322 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6324 if (status == I40E_SUCCESS)
6325 *reg_val = LE32_TO_CPU(cmd_resp->value);
6331 * i40e_read_rx_ctl - read from an Rx control register
6332 * @hw: pointer to the hw struct
6333 * @reg_addr: register address
6335 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6337 enum i40e_status_code status = I40E_SUCCESS;
6342 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6343 if (!use_register) {
6345 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6346 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6353 /* if the AQ access failed, try the old-fashioned way */
6354 if (status || use_register)
6355 val = rd32(hw, reg_addr);
6361 * i40e_aq_rx_ctl_write_register
6362 * @hw: pointer to the hw struct
6363 * @reg_addr: register address
6364 * @reg_val: register value
6365 * @cmd_details: pointer to command details structure or NULL
6367 * Use the firmware to write to an Rx control register,
6368 * especially useful if the Rx unit is under heavy pressure
6370 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6371 u32 reg_addr, u32 reg_val,
6372 struct i40e_asq_cmd_details *cmd_details)
6374 struct i40e_aq_desc desc;
6375 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6376 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6377 enum i40e_status_code status;
6379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6381 cmd->address = CPU_TO_LE32(reg_addr);
6382 cmd->value = CPU_TO_LE32(reg_val);
6384 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6390 * i40e_write_rx_ctl - write to an Rx control register
6391 * @hw: pointer to the hw struct
6392 * @reg_addr: register address
6393 * @reg_val: register value
6395 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6397 enum i40e_status_code status = I40E_SUCCESS;
6401 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6402 if (!use_register) {
6404 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6406 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6413 /* if the AQ access failed, try the old-fashioned way */
6414 if (status || use_register)
6415 wr32(hw, reg_addr, reg_val);
6420 * i40e_aq_send_msg_to_pf
6421 * @hw: pointer to the hardware structure
6422 * @v_opcode: opcodes for VF-PF communication
6423 * @v_retval: return error code
6424 * @msg: pointer to the msg buffer
6425 * @msglen: msg length
6426 * @cmd_details: pointer to command details
6428 * Send message to PF driver using admin queue. By default, this message
6429 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6430 * completion before returning.
6432 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6433 enum i40e_virtchnl_ops v_opcode,
6434 enum i40e_status_code v_retval,
6435 u8 *msg, u16 msglen,
6436 struct i40e_asq_cmd_details *cmd_details)
6438 struct i40e_aq_desc desc;
6439 struct i40e_asq_cmd_details details;
6440 enum i40e_status_code status;
6442 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6443 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6444 desc.cookie_high = CPU_TO_LE32(v_opcode);
6445 desc.cookie_low = CPU_TO_LE32(v_retval);
6447 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6448 | I40E_AQ_FLAG_RD));
6449 if (msglen > I40E_AQ_LARGE_BUF)
6450 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6451 desc.datalen = CPU_TO_LE16(msglen);
6454 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6455 details.async = true;
6456 cmd_details = &details;
6458 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6459 msglen, cmd_details);
6464 * i40e_vf_parse_hw_config
6465 * @hw: pointer to the hardware structure
6466 * @msg: pointer to the virtual channel VF resource structure
6468 * Given a VF resource message from the PF, populate the hw struct
6469 * with appropriate information.
6471 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6472 struct i40e_virtchnl_vf_resource *msg)
6474 struct i40e_virtchnl_vsi_resource *vsi_res;
6477 vsi_res = &msg->vsi_res[0];
6479 hw->dev_caps.num_vsis = msg->num_vsis;
6480 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6481 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6482 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6483 hw->dev_caps.dcb = msg->vf_offload_flags &
6484 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6485 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6486 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6487 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6488 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6489 for (i = 0; i < msg->num_vsis; i++) {
6490 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6491 i40e_memcpy(hw->mac.perm_addr,
6492 vsi_res->default_mac_addr,
6493 I40E_ETH_LENGTH_OF_ADDRESS,
6494 I40E_NONDMA_TO_NONDMA);
6495 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6496 I40E_ETH_LENGTH_OF_ADDRESS,
6497 I40E_NONDMA_TO_NONDMA);
6505 * @hw: pointer to the hardware structure
6507 * Send a VF_RESET message to the PF. Does not wait for response from PF
6508 * as none will be forthcoming. Immediately after calling this function,
6509 * the admin queue should be shut down and (optionally) reinitialized.
6511 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6513 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6514 I40E_SUCCESS, NULL, 0, NULL);
6516 #endif /* VF_DRIVER */
6520 * i40e_aq_set_arp_proxy_config
6521 * @hw: pointer to the HW structure
6522 * @proxy_config - pointer to proxy config command table struct
6523 * @cmd_details: pointer to command details
6525 * Set ARP offload parameters from pre-populated
6526 * i40e_aqc_arp_proxy_data struct
6528 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6529 struct i40e_aqc_arp_proxy_data *proxy_config,
6530 struct i40e_asq_cmd_details *cmd_details)
6532 struct i40e_aq_desc desc;
6533 enum i40e_status_code status;
6536 return I40E_ERR_PARAM;
6538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6540 desc.params.external.addr_high =
6541 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6542 desc.params.external.addr_low =
6543 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6545 status = i40e_asq_send_command(hw, &desc, proxy_config,
6546 sizeof(struct i40e_aqc_arp_proxy_data),
6553 * i40e_aq_opc_set_ns_proxy_table_entry
6554 * @hw: pointer to the HW structure
6555 * @ns_proxy_table_entry: pointer to NS table entry command struct
6556 * @cmd_details: pointer to command details
6558 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6559 * from pre-populated i40e_aqc_ns_proxy_data struct
6561 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6562 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6563 struct i40e_asq_cmd_details *cmd_details)
6565 struct i40e_aq_desc desc;
6566 enum i40e_status_code status;
6568 if (!ns_proxy_table_entry)
6569 return I40E_ERR_PARAM;
6571 i40e_fill_default_direct_cmd_desc(&desc,
6572 i40e_aqc_opc_set_ns_proxy_table_entry);
6574 desc.params.external.addr_high =
6575 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6576 desc.params.external.addr_low =
6577 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6579 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6580 sizeof(struct i40e_aqc_ns_proxy_data),
6587 * i40e_aq_set_clear_wol_filter
6588 * @hw: pointer to the hw struct
6589 * @filter_index: index of filter to modify (0-7)
6590 * @filter: buffer containing filter to be set
6591 * @set_filter: true to set filter, false to clear filter
6592 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6593 * if false, pass through packets may cause wake-up
6594 * @filter_valid: true if filter action is valid
6595 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6596 * @cmd_details: pointer to command details structure or NULL
6598 * Set or clear WoL filter for port attached to the PF
6600 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6602 struct i40e_aqc_set_wol_filter_data *filter,
6603 bool set_filter, bool no_wol_tco,
6604 bool filter_valid, bool no_wol_tco_valid,
6605 struct i40e_asq_cmd_details *cmd_details)
6607 struct i40e_aq_desc desc;
6608 struct i40e_aqc_set_wol_filter *cmd =
6609 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6610 enum i40e_status_code status;
6612 u16 valid_flags = 0;
6615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6617 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6618 return I40E_ERR_PARAM;
6619 cmd->filter_index = CPU_TO_LE16(filter_index);
6623 return I40E_ERR_PARAM;
6624 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6625 buff_len = sizeof(*filter);
6628 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6629 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6632 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6633 if (no_wol_tco_valid)
6634 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6635 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6637 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6638 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6640 status = i40e_asq_send_command(hw, &desc, filter,
6641 buff_len, cmd_details);
6647 * i40e_aq_get_wake_event_reason
6648 * @hw: pointer to the hw struct
6649 * @wake_reason: return value, index of matching filter
6650 * @cmd_details: pointer to command details structure or NULL
6652 * Get information for the reason of a Wake Up event
6654 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6656 struct i40e_asq_cmd_details *cmd_details)
6658 struct i40e_aq_desc desc;
6659 struct i40e_aqc_get_wake_reason_completion *resp =
6660 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6661 enum i40e_status_code status;
6663 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6667 if (status == I40E_SUCCESS)
6668 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6673 #endif /* X722_SUPPORT */