1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 #ifdef X722_A0_SUPPORT
75 case I40E_DEV_ID_X722_A0:
77 case I40E_DEV_ID_SFP_X722:
78 case I40E_DEV_ID_1G_BASE_T_X722:
79 case I40E_DEV_ID_10G_BASE_T_X722:
80 hw->mac.type = I40E_MAC_X722;
84 case I40E_DEV_ID_X722_VF:
85 case I40E_DEV_ID_X722_VF_HV:
86 hw->mac.type = I40E_MAC_X722_VF;
90 case I40E_DEV_ID_VF_HV:
91 hw->mac.type = I40E_MAC_VF;
94 hw->mac.type = I40E_MAC_GENERIC;
98 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
101 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
102 hw->mac.type, status);
106 #ifndef I40E_NDIS_SUPPORT
108 * i40e_aq_str - convert AQ err code to a string
109 * @hw: pointer to the HW structure
110 * @aq_err: the AQ error code to convert
112 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
117 case I40E_AQ_RC_EPERM:
118 return "I40E_AQ_RC_EPERM";
119 case I40E_AQ_RC_ENOENT:
120 return "I40E_AQ_RC_ENOENT";
121 case I40E_AQ_RC_ESRCH:
122 return "I40E_AQ_RC_ESRCH";
123 case I40E_AQ_RC_EINTR:
124 return "I40E_AQ_RC_EINTR";
126 return "I40E_AQ_RC_EIO";
127 case I40E_AQ_RC_ENXIO:
128 return "I40E_AQ_RC_ENXIO";
129 case I40E_AQ_RC_E2BIG:
130 return "I40E_AQ_RC_E2BIG";
131 case I40E_AQ_RC_EAGAIN:
132 return "I40E_AQ_RC_EAGAIN";
133 case I40E_AQ_RC_ENOMEM:
134 return "I40E_AQ_RC_ENOMEM";
135 case I40E_AQ_RC_EACCES:
136 return "I40E_AQ_RC_EACCES";
137 case I40E_AQ_RC_EFAULT:
138 return "I40E_AQ_RC_EFAULT";
139 case I40E_AQ_RC_EBUSY:
140 return "I40E_AQ_RC_EBUSY";
141 case I40E_AQ_RC_EEXIST:
142 return "I40E_AQ_RC_EEXIST";
143 case I40E_AQ_RC_EINVAL:
144 return "I40E_AQ_RC_EINVAL";
145 case I40E_AQ_RC_ENOTTY:
146 return "I40E_AQ_RC_ENOTTY";
147 case I40E_AQ_RC_ENOSPC:
148 return "I40E_AQ_RC_ENOSPC";
149 case I40E_AQ_RC_ENOSYS:
150 return "I40E_AQ_RC_ENOSYS";
151 case I40E_AQ_RC_ERANGE:
152 return "I40E_AQ_RC_ERANGE";
153 case I40E_AQ_RC_EFLUSHED:
154 return "I40E_AQ_RC_EFLUSHED";
155 case I40E_AQ_RC_BAD_ADDR:
156 return "I40E_AQ_RC_BAD_ADDR";
157 case I40E_AQ_RC_EMODE:
158 return "I40E_AQ_RC_EMODE";
159 case I40E_AQ_RC_EFBIG:
160 return "I40E_AQ_RC_EFBIG";
163 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
168 * i40e_stat_str - convert status err code to a string
169 * @hw: pointer to the HW structure
170 * @stat_err: the status error code to convert
172 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
178 return "I40E_ERR_NVM";
179 case I40E_ERR_NVM_CHECKSUM:
180 return "I40E_ERR_NVM_CHECKSUM";
182 return "I40E_ERR_PHY";
183 case I40E_ERR_CONFIG:
184 return "I40E_ERR_CONFIG";
186 return "I40E_ERR_PARAM";
187 case I40E_ERR_MAC_TYPE:
188 return "I40E_ERR_MAC_TYPE";
189 case I40E_ERR_UNKNOWN_PHY:
190 return "I40E_ERR_UNKNOWN_PHY";
191 case I40E_ERR_LINK_SETUP:
192 return "I40E_ERR_LINK_SETUP";
193 case I40E_ERR_ADAPTER_STOPPED:
194 return "I40E_ERR_ADAPTER_STOPPED";
195 case I40E_ERR_INVALID_MAC_ADDR:
196 return "I40E_ERR_INVALID_MAC_ADDR";
197 case I40E_ERR_DEVICE_NOT_SUPPORTED:
198 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
199 case I40E_ERR_MASTER_REQUESTS_PENDING:
200 return "I40E_ERR_MASTER_REQUESTS_PENDING";
201 case I40E_ERR_INVALID_LINK_SETTINGS:
202 return "I40E_ERR_INVALID_LINK_SETTINGS";
203 case I40E_ERR_AUTONEG_NOT_COMPLETE:
204 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
205 case I40E_ERR_RESET_FAILED:
206 return "I40E_ERR_RESET_FAILED";
207 case I40E_ERR_SWFW_SYNC:
208 return "I40E_ERR_SWFW_SYNC";
209 case I40E_ERR_NO_AVAILABLE_VSI:
210 return "I40E_ERR_NO_AVAILABLE_VSI";
211 case I40E_ERR_NO_MEMORY:
212 return "I40E_ERR_NO_MEMORY";
213 case I40E_ERR_BAD_PTR:
214 return "I40E_ERR_BAD_PTR";
215 case I40E_ERR_RING_FULL:
216 return "I40E_ERR_RING_FULL";
217 case I40E_ERR_INVALID_PD_ID:
218 return "I40E_ERR_INVALID_PD_ID";
219 case I40E_ERR_INVALID_QP_ID:
220 return "I40E_ERR_INVALID_QP_ID";
221 case I40E_ERR_INVALID_CQ_ID:
222 return "I40E_ERR_INVALID_CQ_ID";
223 case I40E_ERR_INVALID_CEQ_ID:
224 return "I40E_ERR_INVALID_CEQ_ID";
225 case I40E_ERR_INVALID_AEQ_ID:
226 return "I40E_ERR_INVALID_AEQ_ID";
227 case I40E_ERR_INVALID_SIZE:
228 return "I40E_ERR_INVALID_SIZE";
229 case I40E_ERR_INVALID_ARP_INDEX:
230 return "I40E_ERR_INVALID_ARP_INDEX";
231 case I40E_ERR_INVALID_FPM_FUNC_ID:
232 return "I40E_ERR_INVALID_FPM_FUNC_ID";
233 case I40E_ERR_QP_INVALID_MSG_SIZE:
234 return "I40E_ERR_QP_INVALID_MSG_SIZE";
235 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
236 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
237 case I40E_ERR_INVALID_FRAG_COUNT:
238 return "I40E_ERR_INVALID_FRAG_COUNT";
239 case I40E_ERR_QUEUE_EMPTY:
240 return "I40E_ERR_QUEUE_EMPTY";
241 case I40E_ERR_INVALID_ALIGNMENT:
242 return "I40E_ERR_INVALID_ALIGNMENT";
243 case I40E_ERR_FLUSHED_QUEUE:
244 return "I40E_ERR_FLUSHED_QUEUE";
245 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
246 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
247 case I40E_ERR_INVALID_IMM_DATA_SIZE:
248 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
249 case I40E_ERR_TIMEOUT:
250 return "I40E_ERR_TIMEOUT";
251 case I40E_ERR_OPCODE_MISMATCH:
252 return "I40E_ERR_OPCODE_MISMATCH";
253 case I40E_ERR_CQP_COMPL_ERROR:
254 return "I40E_ERR_CQP_COMPL_ERROR";
255 case I40E_ERR_INVALID_VF_ID:
256 return "I40E_ERR_INVALID_VF_ID";
257 case I40E_ERR_INVALID_HMCFN_ID:
258 return "I40E_ERR_INVALID_HMCFN_ID";
259 case I40E_ERR_BACKING_PAGE_ERROR:
260 return "I40E_ERR_BACKING_PAGE_ERROR";
261 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
262 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
263 case I40E_ERR_INVALID_PBLE_INDEX:
264 return "I40E_ERR_INVALID_PBLE_INDEX";
265 case I40E_ERR_INVALID_SD_INDEX:
266 return "I40E_ERR_INVALID_SD_INDEX";
267 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
268 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
269 case I40E_ERR_INVALID_SD_TYPE:
270 return "I40E_ERR_INVALID_SD_TYPE";
271 case I40E_ERR_MEMCPY_FAILED:
272 return "I40E_ERR_MEMCPY_FAILED";
273 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
274 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
275 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
276 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
277 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
278 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
279 case I40E_ERR_SRQ_ENABLED:
280 return "I40E_ERR_SRQ_ENABLED";
281 case I40E_ERR_ADMIN_QUEUE_ERROR:
282 return "I40E_ERR_ADMIN_QUEUE_ERROR";
283 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
284 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
285 case I40E_ERR_BUF_TOO_SHORT:
286 return "I40E_ERR_BUF_TOO_SHORT";
287 case I40E_ERR_ADMIN_QUEUE_FULL:
288 return "I40E_ERR_ADMIN_QUEUE_FULL";
289 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
290 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
291 case I40E_ERR_BAD_IWARP_CQE:
292 return "I40E_ERR_BAD_IWARP_CQE";
293 case I40E_ERR_NVM_BLANK_MODE:
294 return "I40E_ERR_NVM_BLANK_MODE";
295 case I40E_ERR_NOT_IMPLEMENTED:
296 return "I40E_ERR_NOT_IMPLEMENTED";
297 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
298 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
299 case I40E_ERR_DIAG_TEST_FAILED:
300 return "I40E_ERR_DIAG_TEST_FAILED";
301 case I40E_ERR_NOT_READY:
302 return "I40E_ERR_NOT_READY";
303 case I40E_NOT_SUPPORTED:
304 return "I40E_NOT_SUPPORTED";
305 case I40E_ERR_FIRMWARE_API_VERSION:
306 return "I40E_ERR_FIRMWARE_API_VERSION";
309 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
313 #endif /* I40E_NDIS_SUPPORT */
316 * @hw: debug mask related to admin queue
318 * @desc: pointer to admin queue descriptor
319 * @buffer: pointer to command buffer
320 * @buf_len: max length of buffer
322 * Dumps debug log about adminq command with descriptor contents.
324 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
325 void *buffer, u16 buf_len)
327 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
328 u16 len = LE16_TO_CPU(aq_desc->datalen);
329 u8 *buf = (u8 *)buffer;
332 if ((!(mask & hw->debug_mask)) || (desc == NULL))
336 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
337 LE16_TO_CPU(aq_desc->opcode),
338 LE16_TO_CPU(aq_desc->flags),
339 LE16_TO_CPU(aq_desc->datalen),
340 LE16_TO_CPU(aq_desc->retval));
341 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
342 LE32_TO_CPU(aq_desc->cookie_high),
343 LE32_TO_CPU(aq_desc->cookie_low));
344 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
345 LE32_TO_CPU(aq_desc->params.internal.param0),
346 LE32_TO_CPU(aq_desc->params.internal.param1));
347 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
348 LE32_TO_CPU(aq_desc->params.external.addr_high),
349 LE32_TO_CPU(aq_desc->params.external.addr_low));
351 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
352 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
355 /* write the full 16-byte chunks */
356 for (i = 0; i < (len - 16); i += 16)
358 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
359 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
360 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
361 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
362 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
363 /* the most we could have left is 16 bytes, pad with zeros */
368 memset(d_buf, 0, sizeof(d_buf));
369 for (j = 0; i < len; j++, i++)
372 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
373 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
374 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
375 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
376 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
382 * i40e_check_asq_alive
383 * @hw: pointer to the hw struct
385 * Returns true if Queue is enabled else false.
387 bool i40e_check_asq_alive(struct i40e_hw *hw)
393 return !!(rd32(hw, hw->aq.asq.len) &
394 I40E_PF_ATQLEN_ATQENABLE_MASK);
396 return !!(rd32(hw, hw->aq.asq.len) &
397 I40E_PF_ATQLEN_ATQENABLE_MASK);
398 #endif /* INTEGRATED_VF */
399 #endif /* PF_DRIVER */
403 return !!(rd32(hw, hw->aq.asq.len) &
404 I40E_VF_ATQLEN1_ATQENABLE_MASK);
406 return !!(rd32(hw, hw->aq.asq.len) &
407 I40E_VF_ATQLEN1_ATQENABLE_MASK);
408 #endif /* INTEGRATED_VF */
409 #endif /* VF_DRIVER */
414 * i40e_aq_queue_shutdown
415 * @hw: pointer to the hw struct
416 * @unloading: is the driver unloading itself
418 * Tell the Firmware that we're shutting down the AdminQ and whether
419 * or not the driver is unloading as well.
421 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
424 struct i40e_aq_desc desc;
425 struct i40e_aqc_queue_shutdown *cmd =
426 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
427 enum i40e_status_code status;
429 i40e_fill_default_direct_cmd_desc(&desc,
430 i40e_aqc_opc_queue_shutdown);
433 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
434 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
441 * i40e_aq_get_set_rss_lut
442 * @hw: pointer to the hardware structure
443 * @vsi_id: vsi fw index
444 * @pf_lut: for PF table set true, for VSI table set false
445 * @lut: pointer to the lut buffer provided by the caller
446 * @lut_size: size of the lut buffer
447 * @set: set true to set the table, false to get the table
449 * Internal function to get or set RSS look up table
451 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
452 u16 vsi_id, bool pf_lut,
453 u8 *lut, u16 lut_size,
456 enum i40e_status_code status;
457 struct i40e_aq_desc desc;
458 struct i40e_aqc_get_set_rss_lut *cmd_resp =
459 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
462 i40e_fill_default_direct_cmd_desc(&desc,
463 i40e_aqc_opc_set_rss_lut);
465 i40e_fill_default_direct_cmd_desc(&desc,
466 i40e_aqc_opc_get_rss_lut);
468 /* Indirect command */
469 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
470 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
473 CPU_TO_LE16((u16)((vsi_id <<
474 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
475 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
476 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
479 cmd_resp->flags |= CPU_TO_LE16((u16)
480 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
481 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
482 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
484 cmd_resp->flags |= CPU_TO_LE16((u16)
485 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
486 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
487 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
489 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
495 * i40e_aq_get_rss_lut
496 * @hw: pointer to the hardware structure
497 * @vsi_id: vsi fw index
498 * @pf_lut: for PF table set true, for VSI table set false
499 * @lut: pointer to the lut buffer provided by the caller
500 * @lut_size: size of the lut buffer
502 * get the RSS lookup table, PF or VSI type
504 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
505 bool pf_lut, u8 *lut, u16 lut_size)
507 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
512 * i40e_aq_set_rss_lut
513 * @hw: pointer to the hardware structure
514 * @vsi_id: vsi fw index
515 * @pf_lut: for PF table set true, for VSI table set false
516 * @lut: pointer to the lut buffer provided by the caller
517 * @lut_size: size of the lut buffer
519 * set the RSS lookup table, PF or VSI type
521 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
522 bool pf_lut, u8 *lut, u16 lut_size)
524 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
528 * i40e_aq_get_set_rss_key
529 * @hw: pointer to the hw struct
530 * @vsi_id: vsi fw index
531 * @key: pointer to key info struct
532 * @set: set true to set the key, false to get the key
534 * get the RSS key per VSI
536 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
538 struct i40e_aqc_get_set_rss_key_data *key,
541 enum i40e_status_code status;
542 struct i40e_aq_desc desc;
543 struct i40e_aqc_get_set_rss_key *cmd_resp =
544 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
545 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
548 i40e_fill_default_direct_cmd_desc(&desc,
549 i40e_aqc_opc_set_rss_key);
551 i40e_fill_default_direct_cmd_desc(&desc,
552 i40e_aqc_opc_get_rss_key);
554 /* Indirect command */
555 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
556 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
559 CPU_TO_LE16((u16)((vsi_id <<
560 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
561 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
562 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
564 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
570 * i40e_aq_get_rss_key
571 * @hw: pointer to the hw struct
572 * @vsi_id: vsi fw index
573 * @key: pointer to key info struct
576 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
578 struct i40e_aqc_get_set_rss_key_data *key)
580 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
584 * i40e_aq_set_rss_key
585 * @hw: pointer to the hw struct
586 * @vsi_id: vsi fw index
587 * @key: pointer to key info struct
589 * set the RSS key per VSI
591 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
593 struct i40e_aqc_get_set_rss_key_data *key)
595 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
597 #endif /* X722_SUPPORT */
599 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
600 * hardware to a bit-field that can be used by SW to more easily determine the
603 * Macros are used to shorten the table lines and make this table human
606 * We store the PTYPE in the top byte of the bit field - this is just so that
607 * we can check that the table doesn't have a row missing, as the index into
608 * the table should be the PTYPE.
612 * IF NOT i40e_ptype_lookup[ptype].known
615 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
616 * Use the rest of the fields to look at the tunnels, inner protocols, etc
618 * Use the enum i40e_rx_l2_ptype to decode the packet type
622 /* macro to make the table lines short */
623 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
626 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
627 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
628 I40E_RX_PTYPE_##OUTER_FRAG, \
629 I40E_RX_PTYPE_TUNNEL_##T, \
630 I40E_RX_PTYPE_TUNNEL_END_##TE, \
631 I40E_RX_PTYPE_##TEF, \
632 I40E_RX_PTYPE_INNER_PROT_##I, \
633 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
635 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
636 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
638 /* shorter macros makes the table fit but are terse */
639 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
640 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
641 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
643 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
644 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
645 /* L2 Packet types */
646 I40E_PTT_UNUSED_ENTRY(0),
647 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
648 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
649 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
650 I40E_PTT_UNUSED_ENTRY(4),
651 I40E_PTT_UNUSED_ENTRY(5),
652 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
653 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
654 I40E_PTT_UNUSED_ENTRY(8),
655 I40E_PTT_UNUSED_ENTRY(9),
656 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
657 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
658 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
659 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
660 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
661 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
662 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
663 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
664 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
665 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
666 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 /* Non Tunneled IPv4 */
670 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
673 I40E_PTT_UNUSED_ENTRY(25),
674 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
675 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
676 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
679 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
680 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
681 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
682 I40E_PTT_UNUSED_ENTRY(32),
683 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
684 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
685 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
688 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
689 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
690 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
691 I40E_PTT_UNUSED_ENTRY(39),
692 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
693 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
694 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
696 /* IPv4 --> GRE/NAT */
697 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
699 /* IPv4 --> GRE/NAT --> IPv4 */
700 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
701 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
702 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(47),
704 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
705 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
706 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
708 /* IPv4 --> GRE/NAT --> IPv6 */
709 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
710 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
711 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
712 I40E_PTT_UNUSED_ENTRY(54),
713 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
714 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
715 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
717 /* IPv4 --> GRE/NAT --> MAC */
718 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
720 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
721 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
722 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
723 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(62),
725 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
726 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
727 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
729 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
730 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
731 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
732 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
733 I40E_PTT_UNUSED_ENTRY(69),
734 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
735 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
736 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
738 /* IPv4 --> GRE/NAT --> MAC/VLAN */
739 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
741 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
742 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
743 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
744 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(77),
746 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
747 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
748 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
750 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
751 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
752 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
753 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
754 I40E_PTT_UNUSED_ENTRY(84),
755 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
756 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
757 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
759 /* Non Tunneled IPv6 */
760 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
761 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
762 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
763 I40E_PTT_UNUSED_ENTRY(91),
764 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
765 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
766 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
769 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
770 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
771 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
772 I40E_PTT_UNUSED_ENTRY(98),
773 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
774 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
775 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
778 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
779 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
780 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
781 I40E_PTT_UNUSED_ENTRY(105),
782 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
783 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
784 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
786 /* IPv6 --> GRE/NAT */
787 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
789 /* IPv6 --> GRE/NAT -> IPv4 */
790 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
791 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
792 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
793 I40E_PTT_UNUSED_ENTRY(113),
794 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
795 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
796 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
798 /* IPv6 --> GRE/NAT -> IPv6 */
799 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
800 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
801 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
802 I40E_PTT_UNUSED_ENTRY(120),
803 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
804 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
805 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
807 /* IPv6 --> GRE/NAT -> MAC */
808 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
810 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
811 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
812 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
813 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
814 I40E_PTT_UNUSED_ENTRY(128),
815 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
816 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
817 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
819 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
820 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
821 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
822 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
823 I40E_PTT_UNUSED_ENTRY(135),
824 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
825 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
826 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
828 /* IPv6 --> GRE/NAT -> MAC/VLAN */
829 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
831 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
832 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
833 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
834 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
835 I40E_PTT_UNUSED_ENTRY(143),
836 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
837 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
838 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
840 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
841 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
842 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
843 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
844 I40E_PTT_UNUSED_ENTRY(150),
845 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
846 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
847 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
850 I40E_PTT_UNUSED_ENTRY(154),
851 I40E_PTT_UNUSED_ENTRY(155),
852 I40E_PTT_UNUSED_ENTRY(156),
853 I40E_PTT_UNUSED_ENTRY(157),
854 I40E_PTT_UNUSED_ENTRY(158),
855 I40E_PTT_UNUSED_ENTRY(159),
857 I40E_PTT_UNUSED_ENTRY(160),
858 I40E_PTT_UNUSED_ENTRY(161),
859 I40E_PTT_UNUSED_ENTRY(162),
860 I40E_PTT_UNUSED_ENTRY(163),
861 I40E_PTT_UNUSED_ENTRY(164),
862 I40E_PTT_UNUSED_ENTRY(165),
863 I40E_PTT_UNUSED_ENTRY(166),
864 I40E_PTT_UNUSED_ENTRY(167),
865 I40E_PTT_UNUSED_ENTRY(168),
866 I40E_PTT_UNUSED_ENTRY(169),
868 I40E_PTT_UNUSED_ENTRY(170),
869 I40E_PTT_UNUSED_ENTRY(171),
870 I40E_PTT_UNUSED_ENTRY(172),
871 I40E_PTT_UNUSED_ENTRY(173),
872 I40E_PTT_UNUSED_ENTRY(174),
873 I40E_PTT_UNUSED_ENTRY(175),
874 I40E_PTT_UNUSED_ENTRY(176),
875 I40E_PTT_UNUSED_ENTRY(177),
876 I40E_PTT_UNUSED_ENTRY(178),
877 I40E_PTT_UNUSED_ENTRY(179),
879 I40E_PTT_UNUSED_ENTRY(180),
880 I40E_PTT_UNUSED_ENTRY(181),
881 I40E_PTT_UNUSED_ENTRY(182),
882 I40E_PTT_UNUSED_ENTRY(183),
883 I40E_PTT_UNUSED_ENTRY(184),
884 I40E_PTT_UNUSED_ENTRY(185),
885 I40E_PTT_UNUSED_ENTRY(186),
886 I40E_PTT_UNUSED_ENTRY(187),
887 I40E_PTT_UNUSED_ENTRY(188),
888 I40E_PTT_UNUSED_ENTRY(189),
890 I40E_PTT_UNUSED_ENTRY(190),
891 I40E_PTT_UNUSED_ENTRY(191),
892 I40E_PTT_UNUSED_ENTRY(192),
893 I40E_PTT_UNUSED_ENTRY(193),
894 I40E_PTT_UNUSED_ENTRY(194),
895 I40E_PTT_UNUSED_ENTRY(195),
896 I40E_PTT_UNUSED_ENTRY(196),
897 I40E_PTT_UNUSED_ENTRY(197),
898 I40E_PTT_UNUSED_ENTRY(198),
899 I40E_PTT_UNUSED_ENTRY(199),
901 I40E_PTT_UNUSED_ENTRY(200),
902 I40E_PTT_UNUSED_ENTRY(201),
903 I40E_PTT_UNUSED_ENTRY(202),
904 I40E_PTT_UNUSED_ENTRY(203),
905 I40E_PTT_UNUSED_ENTRY(204),
906 I40E_PTT_UNUSED_ENTRY(205),
907 I40E_PTT_UNUSED_ENTRY(206),
908 I40E_PTT_UNUSED_ENTRY(207),
909 I40E_PTT_UNUSED_ENTRY(208),
910 I40E_PTT_UNUSED_ENTRY(209),
912 I40E_PTT_UNUSED_ENTRY(210),
913 I40E_PTT_UNUSED_ENTRY(211),
914 I40E_PTT_UNUSED_ENTRY(212),
915 I40E_PTT_UNUSED_ENTRY(213),
916 I40E_PTT_UNUSED_ENTRY(214),
917 I40E_PTT_UNUSED_ENTRY(215),
918 I40E_PTT_UNUSED_ENTRY(216),
919 I40E_PTT_UNUSED_ENTRY(217),
920 I40E_PTT_UNUSED_ENTRY(218),
921 I40E_PTT_UNUSED_ENTRY(219),
923 I40E_PTT_UNUSED_ENTRY(220),
924 I40E_PTT_UNUSED_ENTRY(221),
925 I40E_PTT_UNUSED_ENTRY(222),
926 I40E_PTT_UNUSED_ENTRY(223),
927 I40E_PTT_UNUSED_ENTRY(224),
928 I40E_PTT_UNUSED_ENTRY(225),
929 I40E_PTT_UNUSED_ENTRY(226),
930 I40E_PTT_UNUSED_ENTRY(227),
931 I40E_PTT_UNUSED_ENTRY(228),
932 I40E_PTT_UNUSED_ENTRY(229),
934 I40E_PTT_UNUSED_ENTRY(230),
935 I40E_PTT_UNUSED_ENTRY(231),
936 I40E_PTT_UNUSED_ENTRY(232),
937 I40E_PTT_UNUSED_ENTRY(233),
938 I40E_PTT_UNUSED_ENTRY(234),
939 I40E_PTT_UNUSED_ENTRY(235),
940 I40E_PTT_UNUSED_ENTRY(236),
941 I40E_PTT_UNUSED_ENTRY(237),
942 I40E_PTT_UNUSED_ENTRY(238),
943 I40E_PTT_UNUSED_ENTRY(239),
945 I40E_PTT_UNUSED_ENTRY(240),
946 I40E_PTT_UNUSED_ENTRY(241),
947 I40E_PTT_UNUSED_ENTRY(242),
948 I40E_PTT_UNUSED_ENTRY(243),
949 I40E_PTT_UNUSED_ENTRY(244),
950 I40E_PTT_UNUSED_ENTRY(245),
951 I40E_PTT_UNUSED_ENTRY(246),
952 I40E_PTT_UNUSED_ENTRY(247),
953 I40E_PTT_UNUSED_ENTRY(248),
954 I40E_PTT_UNUSED_ENTRY(249),
956 I40E_PTT_UNUSED_ENTRY(250),
957 I40E_PTT_UNUSED_ENTRY(251),
958 I40E_PTT_UNUSED_ENTRY(252),
959 I40E_PTT_UNUSED_ENTRY(253),
960 I40E_PTT_UNUSED_ENTRY(254),
961 I40E_PTT_UNUSED_ENTRY(255)
966 * i40e_validate_mac_addr - Validate unicast MAC address
967 * @mac_addr: pointer to MAC address
969 * Tests a MAC address to ensure it is a valid Individual Address
971 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
973 enum i40e_status_code status = I40E_SUCCESS;
975 DEBUGFUNC("i40e_validate_mac_addr");
977 /* Broadcast addresses ARE multicast addresses
978 * Make sure it is not a multicast address
979 * Reject the zero address
981 if (I40E_IS_MULTICAST(mac_addr) ||
982 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
983 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
984 status = I40E_ERR_INVALID_MAC_ADDR;
991 * i40e_init_shared_code - Initialize the shared code
992 * @hw: pointer to hardware structure
994 * This assigns the MAC type and PHY code and inits the NVM.
995 * Does not touch the hardware. This function must be called prior to any
996 * other function in the shared code. The i40e_hw structure should be
997 * memset to 0 prior to calling this function. The following fields in
998 * hw structure should be filled in prior to calling this function:
999 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1000 * subsystem_vendor_id, and revision_id
1002 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1004 enum i40e_status_code status = I40E_SUCCESS;
1005 u32 port, ari, func_rid;
1007 DEBUGFUNC("i40e_init_shared_code");
1009 i40e_set_mac_type(hw);
1011 switch (hw->mac.type) {
1012 case I40E_MAC_XL710:
1018 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1021 hw->phy.get_link_info = true;
1023 /* Determine port number and PF number*/
1024 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1025 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1026 hw->port = (u8)port;
1027 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1028 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1029 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1031 hw->pf_id = (u8)(func_rid & 0xff);
1033 hw->pf_id = (u8)(func_rid & 0x7);
1036 if (hw->mac.type == I40E_MAC_X722)
1037 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1040 status = i40e_init_nvm(hw);
1045 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1046 * @hw: pointer to the hw struct
1047 * @flags: a return indicator of what addresses were added to the addr store
1048 * @addrs: the requestor's mac addr store
1049 * @cmd_details: pointer to command details structure or NULL
1051 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1053 struct i40e_aqc_mac_address_read_data *addrs,
1054 struct i40e_asq_cmd_details *cmd_details)
1056 struct i40e_aq_desc desc;
1057 struct i40e_aqc_mac_address_read *cmd_data =
1058 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1059 enum i40e_status_code status;
1061 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1062 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1064 status = i40e_asq_send_command(hw, &desc, addrs,
1065 sizeof(*addrs), cmd_details);
1066 *flags = LE16_TO_CPU(cmd_data->command_flags);
1072 * i40e_aq_mac_address_write - Change the MAC addresses
1073 * @hw: pointer to the hw struct
1074 * @flags: indicates which MAC to be written
1075 * @mac_addr: address to write
1076 * @cmd_details: pointer to command details structure or NULL
1078 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1079 u16 flags, u8 *mac_addr,
1080 struct i40e_asq_cmd_details *cmd_details)
1082 struct i40e_aq_desc desc;
1083 struct i40e_aqc_mac_address_write *cmd_data =
1084 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1085 enum i40e_status_code status;
1087 i40e_fill_default_direct_cmd_desc(&desc,
1088 i40e_aqc_opc_mac_address_write);
1089 cmd_data->command_flags = CPU_TO_LE16(flags);
1090 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1091 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1092 ((u32)mac_addr[3] << 16) |
1093 ((u32)mac_addr[4] << 8) |
1096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1102 * i40e_get_mac_addr - get MAC address
1103 * @hw: pointer to the HW structure
1104 * @mac_addr: pointer to MAC address
1106 * Reads the adapter's MAC address from register
1108 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1110 struct i40e_aqc_mac_address_read_data addrs;
1111 enum i40e_status_code status;
1114 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1116 if (flags & I40E_AQC_LAN_ADDR_VALID)
1117 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1123 * i40e_get_port_mac_addr - get Port MAC address
1124 * @hw: pointer to the HW structure
1125 * @mac_addr: pointer to Port MAC address
1127 * Reads the adapter's Port MAC address
1129 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1131 struct i40e_aqc_mac_address_read_data addrs;
1132 enum i40e_status_code status;
1135 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1139 if (flags & I40E_AQC_PORT_ADDR_VALID)
1140 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1142 status = I40E_ERR_INVALID_MAC_ADDR;
1148 * i40e_pre_tx_queue_cfg - pre tx queue configure
1149 * @hw: pointer to the HW structure
1150 * @queue: target pf queue index
1151 * @enable: state change request
1153 * Handles hw requirement to indicate intention to enable
1154 * or disable target queue.
1156 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1158 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1162 if (abs_queue_idx >= 128) {
1163 reg_block = abs_queue_idx / 128;
1164 abs_queue_idx %= 128;
1167 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1168 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1169 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1172 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1174 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1176 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1180 * i40e_read_pba_string - Reads part number string from EEPROM
1181 * @hw: pointer to hardware structure
1182 * @pba_num: stores the part number string from the EEPROM
1183 * @pba_num_size: part number string buffer length
1185 * Reads the part number string from the EEPROM.
1187 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1190 enum i40e_status_code status = I40E_SUCCESS;
1196 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1197 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1198 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1202 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1203 if (status != I40E_SUCCESS) {
1204 DEBUGOUT("Failed to read PBA Block pointer.\n");
1208 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1209 if (status != I40E_SUCCESS) {
1210 DEBUGOUT("Failed to read PBA Block size.\n");
1214 /* Subtract one to get PBA word count (PBA Size word is included in
1218 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1219 DEBUGOUT("Buffer to small for PBA data.\n");
1220 return I40E_ERR_PARAM;
1223 for (i = 0; i < pba_size; i++) {
1224 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1225 if (status != I40E_SUCCESS) {
1226 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1230 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1231 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1233 pba_num[(pba_size * 2)] = '\0';
1239 * i40e_get_media_type - Gets media type
1240 * @hw: pointer to the hardware structure
1242 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1244 enum i40e_media_type media;
1246 switch (hw->phy.link_info.phy_type) {
1247 case I40E_PHY_TYPE_10GBASE_SR:
1248 case I40E_PHY_TYPE_10GBASE_LR:
1249 case I40E_PHY_TYPE_1000BASE_SX:
1250 case I40E_PHY_TYPE_1000BASE_LX:
1251 case I40E_PHY_TYPE_40GBASE_SR4:
1252 case I40E_PHY_TYPE_40GBASE_LR4:
1253 media = I40E_MEDIA_TYPE_FIBER;
1255 case I40E_PHY_TYPE_100BASE_TX:
1256 case I40E_PHY_TYPE_1000BASE_T:
1257 case I40E_PHY_TYPE_10GBASE_T:
1258 media = I40E_MEDIA_TYPE_BASET;
1260 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1261 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1262 case I40E_PHY_TYPE_10GBASE_CR1:
1263 case I40E_PHY_TYPE_40GBASE_CR4:
1264 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1265 case I40E_PHY_TYPE_40GBASE_AOC:
1266 case I40E_PHY_TYPE_10GBASE_AOC:
1267 media = I40E_MEDIA_TYPE_DA;
1269 case I40E_PHY_TYPE_1000BASE_KX:
1270 case I40E_PHY_TYPE_10GBASE_KX4:
1271 case I40E_PHY_TYPE_10GBASE_KR:
1272 case I40E_PHY_TYPE_40GBASE_KR4:
1273 case I40E_PHY_TYPE_20GBASE_KR2:
1274 media = I40E_MEDIA_TYPE_BACKPLANE;
1276 case I40E_PHY_TYPE_SGMII:
1277 case I40E_PHY_TYPE_XAUI:
1278 case I40E_PHY_TYPE_XFI:
1279 case I40E_PHY_TYPE_XLAUI:
1280 case I40E_PHY_TYPE_XLPPI:
1282 media = I40E_MEDIA_TYPE_UNKNOWN;
1289 #define I40E_PF_RESET_WAIT_COUNT 200
1291 * i40e_pf_reset - Reset the PF
1292 * @hw: pointer to the hardware structure
1294 * Assuming someone else has triggered a global reset,
1295 * assure the global reset is complete and then reset the PF
1297 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1304 /* Poll for Global Reset steady state in case of recent GRST.
1305 * The grst delay value is in 100ms units, and we'll wait a
1306 * couple counts longer to be sure we don't just miss the end.
1308 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1309 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1310 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1311 #ifdef I40E_ESS_SUPPORT
1312 /* It can take upto 15 secs for GRST steady state */
1313 grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1315 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1316 reg = rd32(hw, I40E_GLGEN_RSTAT);
1317 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1319 i40e_msec_delay(100);
1321 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1322 DEBUGOUT("Global reset polling failed to complete.\n");
1323 return I40E_ERR_RESET_FAILED;
1326 /* Now Wait for the FW to be ready */
1327 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1328 reg = rd32(hw, I40E_GLNVM_ULD);
1329 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1330 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1331 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1332 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1333 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1336 i40e_msec_delay(10);
1338 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1339 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1340 DEBUGOUT("wait for FW Reset complete timedout\n");
1341 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1342 return I40E_ERR_RESET_FAILED;
1345 /* If there was a Global Reset in progress when we got here,
1346 * we don't need to do the PF Reset
1349 reg = rd32(hw, I40E_PFGEN_CTRL);
1350 wr32(hw, I40E_PFGEN_CTRL,
1351 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1352 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1353 reg = rd32(hw, I40E_PFGEN_CTRL);
1354 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1358 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1359 DEBUGOUT("PF reset polling failed to complete.\n");
1360 return I40E_ERR_RESET_FAILED;
1364 i40e_clear_pxe_mode(hw);
1367 return I40E_SUCCESS;
1371 * i40e_clear_hw - clear out any left over hw state
1372 * @hw: pointer to the hw struct
1374 * Clear queues and interrupts, typically called at init time,
1375 * but after the capabilities have been found so we know how many
1376 * queues and msix vectors have been allocated.
1378 void i40e_clear_hw(struct i40e_hw *hw)
1380 u32 num_queues, base_queue;
1388 /* get number of interrupts, queues, and vfs */
1389 val = rd32(hw, I40E_GLPCI_CNF2);
1390 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1391 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1392 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1393 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1395 val = rd32(hw, I40E_PFLAN_QALLOC);
1396 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1397 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1398 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1399 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1400 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1401 num_queues = (j - base_queue) + 1;
1405 val = rd32(hw, I40E_PF_VT_PFALLOC);
1406 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1407 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1408 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1409 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1410 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1411 num_vfs = (j - i) + 1;
1415 /* stop all the interrupts */
1416 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1417 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1418 for (i = 0; i < num_pf_int - 2; i++)
1419 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1421 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1422 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1423 wr32(hw, I40E_PFINT_LNKLST0, val);
1424 for (i = 0; i < num_pf_int - 2; i++)
1425 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1426 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1427 for (i = 0; i < num_vfs; i++)
1428 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1429 for (i = 0; i < num_vf_int - 2; i++)
1430 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1432 /* warn the HW of the coming Tx disables */
1433 for (i = 0; i < num_queues; i++) {
1434 u32 abs_queue_idx = base_queue + i;
1437 if (abs_queue_idx >= 128) {
1438 reg_block = abs_queue_idx / 128;
1439 abs_queue_idx %= 128;
1442 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1443 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1444 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1445 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1447 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1449 i40e_usec_delay(400);
1451 /* stop all the queues */
1452 for (i = 0; i < num_queues; i++) {
1453 wr32(hw, I40E_QINT_TQCTL(i), 0);
1454 wr32(hw, I40E_QTX_ENA(i), 0);
1455 wr32(hw, I40E_QINT_RQCTL(i), 0);
1456 wr32(hw, I40E_QRX_ENA(i), 0);
1459 /* short wait for all queue disables to settle */
1460 i40e_usec_delay(50);
1464 * i40e_clear_pxe_mode - clear pxe operations mode
1465 * @hw: pointer to the hw struct
1467 * Make sure all PXE mode settings are cleared, including things
1468 * like descriptor fetch/write-back mode.
1470 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1472 if (i40e_check_asq_alive(hw))
1473 i40e_aq_clear_pxe_mode(hw, NULL);
1477 * i40e_led_is_mine - helper to find matching led
1478 * @hw: pointer to the hw struct
1479 * @idx: index into GPIO registers
1481 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1483 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1488 if (!hw->func_caps.led[idx])
1491 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1492 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1493 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1495 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1496 * if it is not our port then ignore
1498 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1505 #define I40E_COMBINED_ACTIVITY 0xA
1506 #define I40E_FILTER_ACTIVITY 0xE
1507 #define I40E_LINK_ACTIVITY 0xC
1508 #define I40E_MAC_ACTIVITY 0xD
1509 #define I40E_LED0 22
1512 * i40e_led_get - return current on/off mode
1513 * @hw: pointer to the hw struct
1515 * The value returned is the 'mode' field as defined in the
1516 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1517 * values are variations of possible behaviors relating to
1518 * blink, link, and wire.
1520 u32 i40e_led_get(struct i40e_hw *hw)
1522 u32 current_mode = 0;
1526 /* as per the documentation GPIO 22-29 are the LED
1527 * GPIO pins named LED0..LED7
1529 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1530 u32 gpio_val = i40e_led_is_mine(hw, i);
1535 /* ignore gpio LED src mode entries related to the activity LEDs */
1536 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1537 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1538 switch (current_mode) {
1539 case I40E_COMBINED_ACTIVITY:
1540 case I40E_FILTER_ACTIVITY:
1541 case I40E_MAC_ACTIVITY:
1547 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1556 * i40e_led_set - set new on/off mode
1557 * @hw: pointer to the hw struct
1558 * @mode: 0=off, 0xf=on (else see manual for mode details)
1559 * @blink: true if the LED should blink when on, false if steady
1561 * if this function is used to turn on the blink it should
1562 * be used to disable the blink when restoring the original state.
1564 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1566 u32 current_mode = 0;
1569 if (mode & 0xfffffff0)
1570 DEBUGOUT1("invalid mode passed in %X\n", mode);
1572 /* as per the documentation GPIO 22-29 are the LED
1573 * GPIO pins named LED0..LED7
1575 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1576 u32 gpio_val = i40e_led_is_mine(hw, i);
1581 /* ignore gpio LED src mode entries related to the activity LEDs */
1582 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1583 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1584 switch (current_mode) {
1585 case I40E_COMBINED_ACTIVITY:
1586 case I40E_FILTER_ACTIVITY:
1587 case I40E_MAC_ACTIVITY:
1593 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1594 /* this & is a bit of paranoia, but serves as a range check */
1595 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1596 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1598 if (mode == I40E_LINK_ACTIVITY)
1602 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1604 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1606 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1611 /* Admin command wrappers */
1614 * i40e_aq_get_phy_capabilities
1615 * @hw: pointer to the hw struct
1616 * @abilities: structure for PHY capabilities to be filled
1617 * @qualified_modules: report Qualified Modules
1618 * @report_init: report init capabilities (active are default)
1619 * @cmd_details: pointer to command details structure or NULL
1621 * Returns the various PHY abilities supported on the Port.
1623 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1624 bool qualified_modules, bool report_init,
1625 struct i40e_aq_get_phy_abilities_resp *abilities,
1626 struct i40e_asq_cmd_details *cmd_details)
1628 struct i40e_aq_desc desc;
1629 enum i40e_status_code status;
1630 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1633 return I40E_ERR_PARAM;
1635 i40e_fill_default_direct_cmd_desc(&desc,
1636 i40e_aqc_opc_get_phy_abilities);
1638 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1639 if (abilities_size > I40E_AQ_LARGE_BUF)
1640 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1642 if (qualified_modules)
1643 desc.params.external.param0 |=
1644 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1647 desc.params.external.param0 |=
1648 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1650 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1653 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1654 status = I40E_ERR_UNKNOWN_PHY;
1657 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1663 * i40e_aq_set_phy_config
1664 * @hw: pointer to the hw struct
1665 * @config: structure with PHY configuration to be set
1666 * @cmd_details: pointer to command details structure or NULL
1668 * Set the various PHY configuration parameters
1669 * supported on the Port.One or more of the Set PHY config parameters may be
1670 * ignored in an MFP mode as the PF may not have the privilege to set some
1671 * of the PHY Config parameters. This status will be indicated by the
1674 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1675 struct i40e_aq_set_phy_config *config,
1676 struct i40e_asq_cmd_details *cmd_details)
1678 struct i40e_aq_desc desc;
1679 struct i40e_aq_set_phy_config *cmd =
1680 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1681 enum i40e_status_code status;
1684 return I40E_ERR_PARAM;
1686 i40e_fill_default_direct_cmd_desc(&desc,
1687 i40e_aqc_opc_set_phy_config);
1691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1698 * @hw: pointer to the hw struct
1700 * Set the requested flow control mode using set_phy_config.
1702 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1703 bool atomic_restart)
1705 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1706 struct i40e_aq_get_phy_abilities_resp abilities;
1707 struct i40e_aq_set_phy_config config;
1708 enum i40e_status_code status;
1709 u8 pause_mask = 0x0;
1715 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1716 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1718 case I40E_FC_RX_PAUSE:
1719 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1721 case I40E_FC_TX_PAUSE:
1722 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1728 /* Get the current phy config */
1729 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1732 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1736 memset(&config, 0, sizeof(config));
1737 /* clear the old pause settings */
1738 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1739 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1740 /* set the new abilities */
1741 config.abilities |= pause_mask;
1742 /* If the abilities have changed, then set the new config */
1743 if (config.abilities != abilities.abilities) {
1744 /* Auto restart link so settings take effect */
1746 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1747 /* Copy over all the old settings */
1748 config.phy_type = abilities.phy_type;
1749 config.link_speed = abilities.link_speed;
1750 config.eee_capability = abilities.eee_capability;
1751 config.eeer = abilities.eeer_val;
1752 config.low_power_ctrl = abilities.d3_lpan;
1753 status = i40e_aq_set_phy_config(hw, &config, NULL);
1756 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1758 /* Update the link info */
1759 status = i40e_update_link_info(hw);
1761 /* Wait a little bit (on 40G cards it sometimes takes a really
1762 * long time for link to come back from the atomic reset)
1765 i40e_msec_delay(1000);
1766 status = i40e_update_link_info(hw);
1769 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1775 * i40e_aq_set_mac_config
1776 * @hw: pointer to the hw struct
1777 * @max_frame_size: Maximum Frame Size to be supported by the port
1778 * @crc_en: Tell HW to append a CRC to outgoing frames
1779 * @pacing: Pacing configurations
1780 * @cmd_details: pointer to command details structure or NULL
1782 * Configure MAC settings for frame size, jumbo frame support and the
1783 * addition of a CRC by the hardware.
1785 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1787 bool crc_en, u16 pacing,
1788 struct i40e_asq_cmd_details *cmd_details)
1790 struct i40e_aq_desc desc;
1791 struct i40e_aq_set_mac_config *cmd =
1792 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1793 enum i40e_status_code status;
1795 if (max_frame_size == 0)
1796 return I40E_ERR_PARAM;
1798 i40e_fill_default_direct_cmd_desc(&desc,
1799 i40e_aqc_opc_set_mac_config);
1801 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1802 cmd->params = ((u8)pacing & 0x0F) << 3;
1804 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1806 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1812 * i40e_aq_clear_pxe_mode
1813 * @hw: pointer to the hw struct
1814 * @cmd_details: pointer to command details structure or NULL
1816 * Tell the firmware that the driver is taking over from PXE
1818 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1819 struct i40e_asq_cmd_details *cmd_details)
1821 enum i40e_status_code status;
1822 struct i40e_aq_desc desc;
1823 struct i40e_aqc_clear_pxe *cmd =
1824 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1826 i40e_fill_default_direct_cmd_desc(&desc,
1827 i40e_aqc_opc_clear_pxe_mode);
1831 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1833 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1839 * i40e_aq_set_link_restart_an
1840 * @hw: pointer to the hw struct
1841 * @enable_link: if true: enable link, if false: disable link
1842 * @cmd_details: pointer to command details structure or NULL
1844 * Sets up the link and restarts the Auto-Negotiation over the link.
1846 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1847 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1849 struct i40e_aq_desc desc;
1850 struct i40e_aqc_set_link_restart_an *cmd =
1851 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1852 enum i40e_status_code status;
1854 i40e_fill_default_direct_cmd_desc(&desc,
1855 i40e_aqc_opc_set_link_restart_an);
1857 cmd->command = I40E_AQ_PHY_RESTART_AN;
1859 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1861 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1863 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1869 * i40e_aq_get_link_info
1870 * @hw: pointer to the hw struct
1871 * @enable_lse: enable/disable LinkStatusEvent reporting
1872 * @link: pointer to link status structure - optional
1873 * @cmd_details: pointer to command details structure or NULL
1875 * Returns the link status of the adapter.
1877 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1878 bool enable_lse, struct i40e_link_status *link,
1879 struct i40e_asq_cmd_details *cmd_details)
1881 struct i40e_aq_desc desc;
1882 struct i40e_aqc_get_link_status *resp =
1883 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1884 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1885 enum i40e_status_code status;
1886 bool tx_pause, rx_pause;
1889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1892 command_flags = I40E_AQ_LSE_ENABLE;
1894 command_flags = I40E_AQ_LSE_DISABLE;
1895 resp->command_flags = CPU_TO_LE16(command_flags);
1897 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1899 if (status != I40E_SUCCESS)
1900 goto aq_get_link_info_exit;
1902 /* save off old link status information */
1903 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1904 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1906 /* update link status */
1907 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1908 hw->phy.media_type = i40e_get_media_type(hw);
1909 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1910 hw_link_info->link_info = resp->link_info;
1911 hw_link_info->an_info = resp->an_info;
1912 hw_link_info->ext_info = resp->ext_info;
1913 hw_link_info->loopback = resp->loopback;
1914 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1915 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1917 /* update fc info */
1918 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1919 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1920 if (tx_pause & rx_pause)
1921 hw->fc.current_mode = I40E_FC_FULL;
1923 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1925 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1927 hw->fc.current_mode = I40E_FC_NONE;
1929 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1930 hw_link_info->crc_enable = true;
1932 hw_link_info->crc_enable = false;
1934 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1935 hw_link_info->lse_enable = true;
1937 hw_link_info->lse_enable = false;
1939 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1940 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1941 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1943 /* save link status information */
1945 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1946 I40E_NONDMA_TO_NONDMA);
1948 /* flag cleared so helper functions don't call AQ again */
1949 hw->phy.get_link_info = false;
1951 aq_get_link_info_exit:
1956 * i40e_aq_set_phy_int_mask
1957 * @hw: pointer to the hw struct
1958 * @mask: interrupt mask to be set
1959 * @cmd_details: pointer to command details structure or NULL
1961 * Set link interrupt mask.
1963 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1965 struct i40e_asq_cmd_details *cmd_details)
1967 struct i40e_aq_desc desc;
1968 struct i40e_aqc_set_phy_int_mask *cmd =
1969 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1970 enum i40e_status_code status;
1972 i40e_fill_default_direct_cmd_desc(&desc,
1973 i40e_aqc_opc_set_phy_int_mask);
1975 cmd->event_mask = CPU_TO_LE16(mask);
1977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1983 * i40e_aq_get_local_advt_reg
1984 * @hw: pointer to the hw struct
1985 * @advt_reg: local AN advertisement register value
1986 * @cmd_details: pointer to command details structure or NULL
1988 * Get the Local AN advertisement register value.
1990 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1992 struct i40e_asq_cmd_details *cmd_details)
1994 struct i40e_aq_desc desc;
1995 struct i40e_aqc_an_advt_reg *resp =
1996 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1997 enum i40e_status_code status;
1999 i40e_fill_default_direct_cmd_desc(&desc,
2000 i40e_aqc_opc_get_local_advt_reg);
2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2004 if (status != I40E_SUCCESS)
2005 goto aq_get_local_advt_reg_exit;
2007 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2008 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2010 aq_get_local_advt_reg_exit:
2015 * i40e_aq_set_local_advt_reg
2016 * @hw: pointer to the hw struct
2017 * @advt_reg: local AN advertisement register value
2018 * @cmd_details: pointer to command details structure or NULL
2020 * Get the Local AN advertisement register value.
2022 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2024 struct i40e_asq_cmd_details *cmd_details)
2026 struct i40e_aq_desc desc;
2027 struct i40e_aqc_an_advt_reg *cmd =
2028 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2029 enum i40e_status_code status;
2031 i40e_fill_default_direct_cmd_desc(&desc,
2032 i40e_aqc_opc_get_local_advt_reg);
2034 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2035 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2037 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2043 * i40e_aq_get_partner_advt
2044 * @hw: pointer to the hw struct
2045 * @advt_reg: AN partner advertisement register value
2046 * @cmd_details: pointer to command details structure or NULL
2048 * Get the link partner AN advertisement register value.
2050 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2052 struct i40e_asq_cmd_details *cmd_details)
2054 struct i40e_aq_desc desc;
2055 struct i40e_aqc_an_advt_reg *resp =
2056 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2057 enum i40e_status_code status;
2059 i40e_fill_default_direct_cmd_desc(&desc,
2060 i40e_aqc_opc_get_partner_advt);
2062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064 if (status != I40E_SUCCESS)
2065 goto aq_get_partner_advt_exit;
2067 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2068 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2070 aq_get_partner_advt_exit:
2075 * i40e_aq_set_lb_modes
2076 * @hw: pointer to the hw struct
2077 * @lb_modes: loopback mode to be set
2078 * @cmd_details: pointer to command details structure or NULL
2080 * Sets loopback modes.
2082 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2084 struct i40e_asq_cmd_details *cmd_details)
2086 struct i40e_aq_desc desc;
2087 struct i40e_aqc_set_lb_mode *cmd =
2088 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2089 enum i40e_status_code status;
2091 i40e_fill_default_direct_cmd_desc(&desc,
2092 i40e_aqc_opc_set_lb_modes);
2094 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102 * i40e_aq_set_phy_debug
2103 * @hw: pointer to the hw struct
2104 * @cmd_flags: debug command flags
2105 * @cmd_details: pointer to command details structure or NULL
2107 * Reset the external PHY.
2109 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2110 struct i40e_asq_cmd_details *cmd_details)
2112 struct i40e_aq_desc desc;
2113 struct i40e_aqc_set_phy_debug *cmd =
2114 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2115 enum i40e_status_code status;
2117 i40e_fill_default_direct_cmd_desc(&desc,
2118 i40e_aqc_opc_set_phy_debug);
2120 cmd->command_flags = cmd_flags;
2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2129 * @hw: pointer to the hw struct
2130 * @vsi_ctx: pointer to a vsi context struct
2131 * @cmd_details: pointer to command details structure or NULL
2133 * Add a VSI context to the hardware.
2135 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2136 struct i40e_vsi_context *vsi_ctx,
2137 struct i40e_asq_cmd_details *cmd_details)
2139 struct i40e_aq_desc desc;
2140 struct i40e_aqc_add_get_update_vsi *cmd =
2141 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2142 struct i40e_aqc_add_get_update_vsi_completion *resp =
2143 (struct i40e_aqc_add_get_update_vsi_completion *)
2145 enum i40e_status_code status;
2147 i40e_fill_default_direct_cmd_desc(&desc,
2148 i40e_aqc_opc_add_vsi);
2150 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2151 cmd->connection_type = vsi_ctx->connection_type;
2152 cmd->vf_id = vsi_ctx->vf_num;
2153 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2155 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2157 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2158 sizeof(vsi_ctx->info), cmd_details);
2160 if (status != I40E_SUCCESS)
2161 goto aq_add_vsi_exit;
2163 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2164 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2165 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2166 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2173 * i40e_aq_set_default_vsi
2174 * @hw: pointer to the hw struct
2176 * @cmd_details: pointer to command details structure or NULL
2178 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2180 struct i40e_asq_cmd_details *cmd_details)
2182 struct i40e_aq_desc desc;
2183 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2184 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2186 enum i40e_status_code status;
2188 i40e_fill_default_direct_cmd_desc(&desc,
2189 i40e_aqc_opc_set_vsi_promiscuous_modes);
2191 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2192 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2193 cmd->seid = CPU_TO_LE16(seid);
2195 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2201 * i40e_aq_set_vsi_unicast_promiscuous
2202 * @hw: pointer to the hw struct
2204 * @set: set unicast promiscuous enable/disable
2205 * @cmd_details: pointer to command details structure or NULL
2207 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2209 struct i40e_asq_cmd_details *cmd_details)
2211 struct i40e_aq_desc desc;
2212 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2213 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2214 enum i40e_status_code status;
2217 i40e_fill_default_direct_cmd_desc(&desc,
2218 i40e_aqc_opc_set_vsi_promiscuous_modes);
2221 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2223 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2225 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2227 cmd->seid = CPU_TO_LE16(seid);
2228 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2234 * i40e_aq_set_vsi_multicast_promiscuous
2235 * @hw: pointer to the hw struct
2237 * @set: set multicast promiscuous enable/disable
2238 * @cmd_details: pointer to command details structure or NULL
2240 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2241 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2243 struct i40e_aq_desc desc;
2244 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2245 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2246 enum i40e_status_code status;
2249 i40e_fill_default_direct_cmd_desc(&desc,
2250 i40e_aqc_opc_set_vsi_promiscuous_modes);
2253 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2255 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2257 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2259 cmd->seid = CPU_TO_LE16(seid);
2260 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2266 * i40e_aq_set_vsi_mc_promisc_on_vlan
2267 * @hw: pointer to the hw struct
2269 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2270 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2271 * @cmd_details: pointer to command details structure or NULL
2273 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2274 u16 seid, bool enable, u16 vid,
2275 struct i40e_asq_cmd_details *cmd_details)
2277 struct i40e_aq_desc desc;
2278 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2279 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2280 enum i40e_status_code status;
2283 i40e_fill_default_direct_cmd_desc(&desc,
2284 i40e_aqc_opc_set_vsi_promiscuous_modes);
2287 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2289 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2290 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2291 cmd->seid = CPU_TO_LE16(seid);
2292 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2294 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2300 * i40e_aq_set_vsi_uc_promisc_on_vlan
2301 * @hw: pointer to the hw struct
2303 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2304 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2305 * @cmd_details: pointer to command details structure or NULL
2307 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2308 u16 seid, bool enable, u16 vid,
2309 struct i40e_asq_cmd_details *cmd_details)
2311 struct i40e_aq_desc desc;
2312 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2313 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2314 enum i40e_status_code status;
2317 i40e_fill_default_direct_cmd_desc(&desc,
2318 i40e_aqc_opc_set_vsi_promiscuous_modes);
2321 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2323 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2324 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2325 cmd->seid = CPU_TO_LE16(seid);
2326 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2334 * i40e_aq_set_vsi_broadcast
2335 * @hw: pointer to the hw struct
2337 * @set_filter: true to set filter, false to clear filter
2338 * @cmd_details: pointer to command details structure or NULL
2340 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2342 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2343 u16 seid, bool set_filter,
2344 struct i40e_asq_cmd_details *cmd_details)
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2348 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2349 enum i40e_status_code status;
2351 i40e_fill_default_direct_cmd_desc(&desc,
2352 i40e_aqc_opc_set_vsi_promiscuous_modes);
2355 cmd->promiscuous_flags
2356 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2358 cmd->promiscuous_flags
2359 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2361 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2362 cmd->seid = CPU_TO_LE16(seid);
2363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2369 * i40e_get_vsi_params - get VSI configuration info
2370 * @hw: pointer to the hw struct
2371 * @vsi_ctx: pointer to a vsi context struct
2372 * @cmd_details: pointer to command details structure or NULL
2374 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2375 struct i40e_vsi_context *vsi_ctx,
2376 struct i40e_asq_cmd_details *cmd_details)
2378 struct i40e_aq_desc desc;
2379 struct i40e_aqc_add_get_update_vsi *cmd =
2380 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2381 struct i40e_aqc_add_get_update_vsi_completion *resp =
2382 (struct i40e_aqc_add_get_update_vsi_completion *)
2384 enum i40e_status_code status;
2386 UNREFERENCED_1PARAMETER(cmd_details);
2387 i40e_fill_default_direct_cmd_desc(&desc,
2388 i40e_aqc_opc_get_vsi_parameters);
2390 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2392 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2394 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2395 sizeof(vsi_ctx->info), NULL);
2397 if (status != I40E_SUCCESS)
2398 goto aq_get_vsi_params_exit;
2400 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2401 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2402 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2403 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2405 aq_get_vsi_params_exit:
2410 * i40e_aq_update_vsi_params
2411 * @hw: pointer to the hw struct
2412 * @vsi_ctx: pointer to a vsi context struct
2413 * @cmd_details: pointer to command details structure or NULL
2415 * Update a VSI context.
2417 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2418 struct i40e_vsi_context *vsi_ctx,
2419 struct i40e_asq_cmd_details *cmd_details)
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_add_get_update_vsi *cmd =
2423 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2424 enum i40e_status_code status;
2426 i40e_fill_default_direct_cmd_desc(&desc,
2427 i40e_aqc_opc_update_vsi_parameters);
2428 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2430 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2432 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2433 sizeof(vsi_ctx->info), cmd_details);
2439 * i40e_aq_get_switch_config
2440 * @hw: pointer to the hardware structure
2441 * @buf: pointer to the result buffer
2442 * @buf_size: length of input buffer
2443 * @start_seid: seid to start for the report, 0 == beginning
2444 * @cmd_details: pointer to command details structure or NULL
2446 * Fill the buf with switch configuration returned from AdminQ command
2448 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2449 struct i40e_aqc_get_switch_config_resp *buf,
2450 u16 buf_size, u16 *start_seid,
2451 struct i40e_asq_cmd_details *cmd_details)
2453 struct i40e_aq_desc desc;
2454 struct i40e_aqc_switch_seid *scfg =
2455 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2456 enum i40e_status_code status;
2458 i40e_fill_default_direct_cmd_desc(&desc,
2459 i40e_aqc_opc_get_switch_config);
2460 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2461 if (buf_size > I40E_AQ_LARGE_BUF)
2462 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2463 scfg->seid = CPU_TO_LE16(*start_seid);
2465 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2466 *start_seid = LE16_TO_CPU(scfg->seid);
2472 * i40e_aq_get_firmware_version
2473 * @hw: pointer to the hw struct
2474 * @fw_major_version: firmware major version
2475 * @fw_minor_version: firmware minor version
2476 * @fw_build: firmware build number
2477 * @api_major_version: major queue version
2478 * @api_minor_version: minor queue version
2479 * @cmd_details: pointer to command details structure or NULL
2481 * Get the firmware version from the admin queue commands
2483 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2484 u16 *fw_major_version, u16 *fw_minor_version,
2486 u16 *api_major_version, u16 *api_minor_version,
2487 struct i40e_asq_cmd_details *cmd_details)
2489 struct i40e_aq_desc desc;
2490 struct i40e_aqc_get_version *resp =
2491 (struct i40e_aqc_get_version *)&desc.params.raw;
2492 enum i40e_status_code status;
2494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2496 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2498 if (status == I40E_SUCCESS) {
2499 if (fw_major_version != NULL)
2500 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2501 if (fw_minor_version != NULL)
2502 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2503 if (fw_build != NULL)
2504 *fw_build = LE32_TO_CPU(resp->fw_build);
2505 if (api_major_version != NULL)
2506 *api_major_version = LE16_TO_CPU(resp->api_major);
2507 if (api_minor_version != NULL)
2508 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2510 /* A workaround to fix the API version in SW */
2511 if (api_major_version && api_minor_version &&
2512 fw_major_version && fw_minor_version &&
2513 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2514 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2515 (*fw_major_version > 4)))
2516 *api_minor_version = 2;
2523 * i40e_aq_send_driver_version
2524 * @hw: pointer to the hw struct
2525 * @dv: driver's major, minor version
2526 * @cmd_details: pointer to command details structure or NULL
2528 * Send the driver version to the firmware
2530 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2531 struct i40e_driver_version *dv,
2532 struct i40e_asq_cmd_details *cmd_details)
2534 struct i40e_aq_desc desc;
2535 struct i40e_aqc_driver_version *cmd =
2536 (struct i40e_aqc_driver_version *)&desc.params.raw;
2537 enum i40e_status_code status;
2541 return I40E_ERR_PARAM;
2543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2545 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2546 cmd->driver_major_ver = dv->major_version;
2547 cmd->driver_minor_ver = dv->minor_version;
2548 cmd->driver_build_ver = dv->build_version;
2549 cmd->driver_subbuild_ver = dv->subbuild_version;
2552 while (len < sizeof(dv->driver_string) &&
2553 (dv->driver_string[len] < 0x80) &&
2554 dv->driver_string[len])
2556 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2563 * i40e_get_link_status - get status of the HW network link
2564 * @hw: pointer to the hw struct
2565 * @link_up: pointer to bool (true/false = linkup/linkdown)
2567 * Variable link_up true if link is up, false if link is down.
2568 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2570 * Side effect: LinkStatusEvent reporting becomes enabled
2572 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2574 enum i40e_status_code status = I40E_SUCCESS;
2576 if (hw->phy.get_link_info) {
2577 status = i40e_update_link_info(hw);
2579 if (status != I40E_SUCCESS)
2580 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2584 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2590 * i40e_updatelink_status - update status of the HW network link
2591 * @hw: pointer to the hw struct
2593 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2595 struct i40e_aq_get_phy_abilities_resp abilities;
2596 enum i40e_status_code status = I40E_SUCCESS;
2598 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2602 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2607 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2608 sizeof(hw->phy.link_info.module_type));
2614 * i40e_get_link_speed
2615 * @hw: pointer to the hw struct
2617 * Returns the link speed of the adapter.
2619 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2621 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2622 enum i40e_status_code status = I40E_SUCCESS;
2624 if (hw->phy.get_link_info) {
2625 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2627 if (status != I40E_SUCCESS)
2628 goto i40e_link_speed_exit;
2631 speed = hw->phy.link_info.link_speed;
2633 i40e_link_speed_exit:
2638 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2639 * @hw: pointer to the hw struct
2640 * @uplink_seid: the MAC or other gizmo SEID
2641 * @downlink_seid: the VSI SEID
2642 * @enabled_tc: bitmap of TCs to be enabled
2643 * @default_port: true for default port VSI, false for control port
2644 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2645 * @veb_seid: pointer to where to put the resulting VEB SEID
2646 * @cmd_details: pointer to command details structure or NULL
2648 * This asks the FW to add a VEB between the uplink and downlink
2649 * elements. If the uplink SEID is 0, this will be a floating VEB.
2651 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2652 u16 downlink_seid, u8 enabled_tc,
2653 bool default_port, bool enable_l2_filtering,
2655 struct i40e_asq_cmd_details *cmd_details)
2657 struct i40e_aq_desc desc;
2658 struct i40e_aqc_add_veb *cmd =
2659 (struct i40e_aqc_add_veb *)&desc.params.raw;
2660 struct i40e_aqc_add_veb_completion *resp =
2661 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2662 enum i40e_status_code status;
2665 /* SEIDs need to either both be set or both be 0 for floating VEB */
2666 if (!!uplink_seid != !!downlink_seid)
2667 return I40E_ERR_PARAM;
2669 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2671 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2672 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2673 cmd->enable_tcs = enabled_tc;
2675 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2677 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2679 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2681 if (enable_l2_filtering)
2682 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2684 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2688 if (!status && veb_seid)
2689 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2695 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2696 * @hw: pointer to the hw struct
2697 * @veb_seid: the SEID of the VEB to query
2698 * @switch_id: the uplink switch id
2699 * @floating: set to true if the VEB is floating
2700 * @statistic_index: index of the stats counter block for this VEB
2701 * @vebs_used: number of VEB's used by function
2702 * @vebs_free: total VEB's not reserved by any function
2703 * @cmd_details: pointer to command details structure or NULL
2705 * This retrieves the parameters for a particular VEB, specified by
2706 * uplink_seid, and returns them to the caller.
2708 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2709 u16 veb_seid, u16 *switch_id,
2710 bool *floating, u16 *statistic_index,
2711 u16 *vebs_used, u16 *vebs_free,
2712 struct i40e_asq_cmd_details *cmd_details)
2714 struct i40e_aq_desc desc;
2715 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2716 (struct i40e_aqc_get_veb_parameters_completion *)
2718 enum i40e_status_code status;
2721 return I40E_ERR_PARAM;
2723 i40e_fill_default_direct_cmd_desc(&desc,
2724 i40e_aqc_opc_get_veb_parameters);
2725 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2727 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2732 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2733 if (statistic_index)
2734 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2736 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2738 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2740 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2741 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2752 * i40e_aq_add_macvlan
2753 * @hw: pointer to the hw struct
2754 * @seid: VSI for the mac address
2755 * @mv_list: list of macvlans to be added
2756 * @count: length of the list
2757 * @cmd_details: pointer to command details structure or NULL
2759 * Add MAC/VLAN addresses to the HW filtering
2761 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2762 struct i40e_aqc_add_macvlan_element_data *mv_list,
2763 u16 count, struct i40e_asq_cmd_details *cmd_details)
2765 struct i40e_aq_desc desc;
2766 struct i40e_aqc_macvlan *cmd =
2767 (struct i40e_aqc_macvlan *)&desc.params.raw;
2768 enum i40e_status_code status;
2771 if (count == 0 || !mv_list || !hw)
2772 return I40E_ERR_PARAM;
2774 buf_size = count * sizeof(*mv_list);
2776 /* prep the rest of the request */
2777 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2778 cmd->num_addresses = CPU_TO_LE16(count);
2779 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2783 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2784 if (buf_size > I40E_AQ_LARGE_BUF)
2785 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2787 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2794 * i40e_aq_remove_macvlan
2795 * @hw: pointer to the hw struct
2796 * @seid: VSI for the mac address
2797 * @mv_list: list of macvlans to be removed
2798 * @count: length of the list
2799 * @cmd_details: pointer to command details structure or NULL
2801 * Remove MAC/VLAN addresses from the HW filtering
2803 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2804 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2805 u16 count, struct i40e_asq_cmd_details *cmd_details)
2807 struct i40e_aq_desc desc;
2808 struct i40e_aqc_macvlan *cmd =
2809 (struct i40e_aqc_macvlan *)&desc.params.raw;
2810 enum i40e_status_code status;
2813 if (count == 0 || !mv_list || !hw)
2814 return I40E_ERR_PARAM;
2816 buf_size = count * sizeof(*mv_list);
2818 /* prep the rest of the request */
2819 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2820 cmd->num_addresses = CPU_TO_LE16(count);
2821 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2825 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2826 if (buf_size > I40E_AQ_LARGE_BUF)
2827 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2829 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2836 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2837 * @hw: pointer to the hw struct
2838 * @seid: VSI for the vlan filters
2839 * @v_list: list of vlan filters to be added
2840 * @count: length of the list
2841 * @cmd_details: pointer to command details structure or NULL
2843 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2844 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2845 u8 count, struct i40e_asq_cmd_details *cmd_details)
2847 struct i40e_aq_desc desc;
2848 struct i40e_aqc_macvlan *cmd =
2849 (struct i40e_aqc_macvlan *)&desc.params.raw;
2850 enum i40e_status_code status;
2853 if (count == 0 || !v_list || !hw)
2854 return I40E_ERR_PARAM;
2856 buf_size = count * sizeof(*v_list);
2858 /* prep the rest of the request */
2859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2860 cmd->num_addresses = CPU_TO_LE16(count);
2861 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2865 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2866 if (buf_size > I40E_AQ_LARGE_BUF)
2867 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2869 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2876 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2877 * @hw: pointer to the hw struct
2878 * @seid: VSI for the vlan filters
2879 * @v_list: list of macvlans to be removed
2880 * @count: length of the list
2881 * @cmd_details: pointer to command details structure or NULL
2883 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2884 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2885 u8 count, struct i40e_asq_cmd_details *cmd_details)
2887 struct i40e_aq_desc desc;
2888 struct i40e_aqc_macvlan *cmd =
2889 (struct i40e_aqc_macvlan *)&desc.params.raw;
2890 enum i40e_status_code status;
2893 if (count == 0 || !v_list || !hw)
2894 return I40E_ERR_PARAM;
2896 buf_size = count * sizeof(*v_list);
2898 /* prep the rest of the request */
2899 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2900 cmd->num_addresses = CPU_TO_LE16(count);
2901 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2905 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2906 if (buf_size > I40E_AQ_LARGE_BUF)
2907 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2909 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2916 * i40e_aq_send_msg_to_vf
2917 * @hw: pointer to the hardware structure
2918 * @vfid: vf id to send msg
2919 * @v_opcode: opcodes for VF-PF communication
2920 * @v_retval: return error code
2921 * @msg: pointer to the msg buffer
2922 * @msglen: msg length
2923 * @cmd_details: pointer to command details
2927 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2928 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2929 struct i40e_asq_cmd_details *cmd_details)
2931 struct i40e_aq_desc desc;
2932 struct i40e_aqc_pf_vf_message *cmd =
2933 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2934 enum i40e_status_code status;
2936 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2937 cmd->id = CPU_TO_LE32(vfid);
2938 desc.cookie_high = CPU_TO_LE32(v_opcode);
2939 desc.cookie_low = CPU_TO_LE32(v_retval);
2940 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2942 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2944 if (msglen > I40E_AQ_LARGE_BUF)
2945 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2946 desc.datalen = CPU_TO_LE16(msglen);
2948 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2954 * i40e_aq_debug_read_register
2955 * @hw: pointer to the hw struct
2956 * @reg_addr: register address
2957 * @reg_val: register value
2958 * @cmd_details: pointer to command details structure or NULL
2960 * Read the register using the admin queue commands
2962 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2963 u32 reg_addr, u64 *reg_val,
2964 struct i40e_asq_cmd_details *cmd_details)
2966 struct i40e_aq_desc desc;
2967 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2968 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2969 enum i40e_status_code status;
2971 if (reg_val == NULL)
2972 return I40E_ERR_PARAM;
2974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2976 cmd_resp->address = CPU_TO_LE32(reg_addr);
2978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2980 if (status == I40E_SUCCESS) {
2981 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2982 (u64)LE32_TO_CPU(cmd_resp->value_low);
2989 * i40e_aq_debug_write_register
2990 * @hw: pointer to the hw struct
2991 * @reg_addr: register address
2992 * @reg_val: register value
2993 * @cmd_details: pointer to command details structure or NULL
2995 * Write to a register using the admin queue commands
2997 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2998 u32 reg_addr, u64 reg_val,
2999 struct i40e_asq_cmd_details *cmd_details)
3001 struct i40e_aq_desc desc;
3002 struct i40e_aqc_debug_reg_read_write *cmd =
3003 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3004 enum i40e_status_code status;
3006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3008 cmd->address = CPU_TO_LE32(reg_addr);
3009 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3010 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3012 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3018 * i40e_aq_get_hmc_resource_profile
3019 * @hw: pointer to the hw struct
3020 * @profile: type of profile the HMC is to be set as
3021 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3022 * @cmd_details: pointer to command details structure or NULL
3024 * query the HMC profile of the device.
3026 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3027 enum i40e_aq_hmc_profile *profile,
3028 u8 *pe_vf_enabled_count,
3029 struct i40e_asq_cmd_details *cmd_details)
3031 struct i40e_aq_desc desc;
3032 struct i40e_aq_get_set_hmc_resource_profile *resp =
3033 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3034 enum i40e_status_code status;
3036 i40e_fill_default_direct_cmd_desc(&desc,
3037 i40e_aqc_opc_query_hmc_resource_profile);
3038 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3040 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3041 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3042 *pe_vf_enabled_count = resp->pe_vf_enabled &
3043 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3049 * i40e_aq_set_hmc_resource_profile
3050 * @hw: pointer to the hw struct
3051 * @profile: type of profile the HMC is to be set as
3052 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3053 * @cmd_details: pointer to command details structure or NULL
3055 * set the HMC profile of the device.
3057 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3058 enum i40e_aq_hmc_profile profile,
3059 u8 pe_vf_enabled_count,
3060 struct i40e_asq_cmd_details *cmd_details)
3062 struct i40e_aq_desc desc;
3063 struct i40e_aq_get_set_hmc_resource_profile *cmd =
3064 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3065 enum i40e_status_code status;
3067 i40e_fill_default_direct_cmd_desc(&desc,
3068 i40e_aqc_opc_set_hmc_resource_profile);
3070 cmd->pm_profile = (u8)profile;
3071 cmd->pe_vf_enabled = pe_vf_enabled_count;
3073 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3079 * i40e_aq_request_resource
3080 * @hw: pointer to the hw struct
3081 * @resource: resource id
3082 * @access: access type
3083 * @sdp_number: resource number
3084 * @timeout: the maximum time in ms that the driver may hold the resource
3085 * @cmd_details: pointer to command details structure or NULL
3087 * requests common resource using the admin queue commands
3089 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3090 enum i40e_aq_resources_ids resource,
3091 enum i40e_aq_resource_access_type access,
3092 u8 sdp_number, u64 *timeout,
3093 struct i40e_asq_cmd_details *cmd_details)
3095 struct i40e_aq_desc desc;
3096 struct i40e_aqc_request_resource *cmd_resp =
3097 (struct i40e_aqc_request_resource *)&desc.params.raw;
3098 enum i40e_status_code status;
3100 DEBUGFUNC("i40e_aq_request_resource");
3102 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3104 cmd_resp->resource_id = CPU_TO_LE16(resource);
3105 cmd_resp->access_type = CPU_TO_LE16(access);
3106 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3109 /* The completion specifies the maximum time in ms that the driver
3110 * may hold the resource in the Timeout field.
3111 * If the resource is held by someone else, the command completes with
3112 * busy return value and the timeout field indicates the maximum time
3113 * the current owner of the resource has to free it.
3115 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3116 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3122 * i40e_aq_release_resource
3123 * @hw: pointer to the hw struct
3124 * @resource: resource id
3125 * @sdp_number: resource number
3126 * @cmd_details: pointer to command details structure or NULL
3128 * release common resource using the admin queue commands
3130 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3131 enum i40e_aq_resources_ids resource,
3133 struct i40e_asq_cmd_details *cmd_details)
3135 struct i40e_aq_desc desc;
3136 struct i40e_aqc_request_resource *cmd =
3137 (struct i40e_aqc_request_resource *)&desc.params.raw;
3138 enum i40e_status_code status;
3140 DEBUGFUNC("i40e_aq_release_resource");
3142 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3144 cmd->resource_id = CPU_TO_LE16(resource);
3145 cmd->resource_number = CPU_TO_LE32(sdp_number);
3147 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3154 * @hw: pointer to the hw struct
3155 * @module_pointer: module pointer location in words from the NVM beginning
3156 * @offset: byte offset from the module beginning
3157 * @length: length of the section to be read (in bytes from the offset)
3158 * @data: command buffer (size [bytes] = length)
3159 * @last_command: tells if this is the last command in a series
3160 * @cmd_details: pointer to command details structure or NULL
3162 * Read the NVM using the admin queue commands
3164 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3165 u32 offset, u16 length, void *data,
3167 struct i40e_asq_cmd_details *cmd_details)
3169 struct i40e_aq_desc desc;
3170 struct i40e_aqc_nvm_update *cmd =
3171 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3172 enum i40e_status_code status;
3174 DEBUGFUNC("i40e_aq_read_nvm");
3176 /* In offset the highest byte must be zeroed. */
3177 if (offset & 0xFF000000) {
3178 status = I40E_ERR_PARAM;
3179 goto i40e_aq_read_nvm_exit;
3182 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3184 /* If this is the last command in a series, set the proper flag. */
3186 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3187 cmd->module_pointer = module_pointer;
3188 cmd->offset = CPU_TO_LE32(offset);
3189 cmd->length = CPU_TO_LE16(length);
3191 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3192 if (length > I40E_AQ_LARGE_BUF)
3193 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3195 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3197 i40e_aq_read_nvm_exit:
3202 * i40e_aq_read_nvm_config - read an nvm config block
3203 * @hw: pointer to the hw struct
3204 * @cmd_flags: NVM access admin command bits
3205 * @field_id: field or feature id
3206 * @data: buffer for result
3207 * @buf_size: buffer size
3208 * @element_count: pointer to count of elements read by FW
3209 * @cmd_details: pointer to command details structure or NULL
3211 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3212 u8 cmd_flags, u32 field_id, void *data,
3213 u16 buf_size, u16 *element_count,
3214 struct i40e_asq_cmd_details *cmd_details)
3216 struct i40e_aq_desc desc;
3217 struct i40e_aqc_nvm_config_read *cmd =
3218 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3219 enum i40e_status_code status;
3221 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3222 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3223 if (buf_size > I40E_AQ_LARGE_BUF)
3224 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3226 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3227 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3228 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3229 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3231 cmd->element_id_msw = 0;
3233 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3235 if (!status && element_count)
3236 *element_count = LE16_TO_CPU(cmd->element_count);
3242 * i40e_aq_write_nvm_config - write an nvm config block
3243 * @hw: pointer to the hw struct
3244 * @cmd_flags: NVM access admin command bits
3245 * @data: buffer for result
3246 * @buf_size: buffer size
3247 * @element_count: count of elements to be written
3248 * @cmd_details: pointer to command details structure or NULL
3250 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3251 u8 cmd_flags, void *data, u16 buf_size,
3253 struct i40e_asq_cmd_details *cmd_details)
3255 struct i40e_aq_desc desc;
3256 struct i40e_aqc_nvm_config_write *cmd =
3257 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3258 enum i40e_status_code status;
3260 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3261 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3262 if (buf_size > I40E_AQ_LARGE_BUF)
3263 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3265 cmd->element_count = CPU_TO_LE16(element_count);
3266 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3267 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3273 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3274 * @hw: pointer to the hw struct
3275 * @cmd_details: pointer to command details structure or NULL
3277 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3278 void *buff, u16 buff_size,
3279 struct i40e_asq_cmd_details *cmd_details)
3281 struct i40e_aq_desc desc;
3282 enum i40e_status_code status;
3284 UNREFERENCED_2PARAMETER(buff, buff_size);
3286 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3287 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3288 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3289 status = I40E_ERR_NOT_IMPLEMENTED;
3296 * @hw: pointer to the hw struct
3297 * @module_pointer: module pointer location in words from the NVM beginning
3298 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3299 * @length: length of the section to be erased (expressed in 4 KB)
3300 * @last_command: tells if this is the last command in a series
3301 * @cmd_details: pointer to command details structure or NULL
3303 * Erase the NVM sector using the admin queue commands
3305 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3306 u32 offset, u16 length, bool last_command,
3307 struct i40e_asq_cmd_details *cmd_details)
3309 struct i40e_aq_desc desc;
3310 struct i40e_aqc_nvm_update *cmd =
3311 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3312 enum i40e_status_code status;
3314 DEBUGFUNC("i40e_aq_erase_nvm");
3316 /* In offset the highest byte must be zeroed. */
3317 if (offset & 0xFF000000) {
3318 status = I40E_ERR_PARAM;
3319 goto i40e_aq_erase_nvm_exit;
3322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3324 /* If this is the last command in a series, set the proper flag. */
3326 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3327 cmd->module_pointer = module_pointer;
3328 cmd->offset = CPU_TO_LE32(offset);
3329 cmd->length = CPU_TO_LE16(length);
3331 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3333 i40e_aq_erase_nvm_exit:
3337 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3338 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3339 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3340 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3341 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3343 #define I40E_DEV_FUNC_CAP_WOL_PROXY 0x08
3345 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3346 #define I40E_DEV_FUNC_CAP_VF 0x13
3347 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3348 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3349 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3350 #define I40E_DEV_FUNC_CAP_VSI 0x17
3351 #define I40E_DEV_FUNC_CAP_DCB 0x18
3352 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3353 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3354 #define I40E_DEV_FUNC_CAP_RSS 0x40
3355 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3356 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3357 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3358 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3359 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3360 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3361 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1
3362 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3363 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3364 #define I40E_DEV_FUNC_CAP_LED 0x61
3365 #define I40E_DEV_FUNC_CAP_SDP 0x62
3366 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3367 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64
3370 * i40e_parse_discover_capabilities
3371 * @hw: pointer to the hw struct
3372 * @buff: pointer to a buffer containing device/function capability records
3373 * @cap_count: number of capability records in the list
3374 * @list_type_opc: type of capabilities list to parse
3376 * Parse the device/function capabilities list.
3378 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3380 enum i40e_admin_queue_opc list_type_opc)
3382 struct i40e_aqc_list_capabilities_element_resp *cap;
3383 u32 valid_functions, num_functions;
3384 u32 number, logical_id, phys_id;
3385 struct i40e_hw_capabilities *p;
3390 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3392 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3393 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3394 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3395 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3399 for (i = 0; i < cap_count; i++, cap++) {
3400 id = LE16_TO_CPU(cap->id);
3401 number = LE32_TO_CPU(cap->number);
3402 logical_id = LE32_TO_CPU(cap->logical_id);
3403 phys_id = LE32_TO_CPU(cap->phys_id);
3404 major_rev = cap->major_rev;
3407 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3408 p->switch_mode = number;
3410 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3411 p->management_mode = number;
3413 case I40E_DEV_FUNC_CAP_NPAR:
3414 p->npar_enable = number;
3416 case I40E_DEV_FUNC_CAP_OS2BMC:
3419 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3420 p->valid_functions = number;
3422 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3424 p->sr_iov_1_1 = true;
3426 case I40E_DEV_FUNC_CAP_VF:
3427 p->num_vfs = number;
3428 p->vf_base_id = logical_id;
3430 case I40E_DEV_FUNC_CAP_VMDQ:
3434 case I40E_DEV_FUNC_CAP_802_1_QBG:
3436 p->evb_802_1_qbg = true;
3438 case I40E_DEV_FUNC_CAP_802_1_QBH:
3440 p->evb_802_1_qbh = true;
3442 case I40E_DEV_FUNC_CAP_VSI:
3443 p->num_vsis = number;
3445 case I40E_DEV_FUNC_CAP_DCB:
3448 p->enabled_tcmap = logical_id;
3452 case I40E_DEV_FUNC_CAP_FCOE:
3456 case I40E_DEV_FUNC_CAP_ISCSI:
3460 case I40E_DEV_FUNC_CAP_RSS:
3462 p->rss_table_size = number;
3463 p->rss_table_entry_width = logical_id;
3465 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3466 p->num_rx_qp = number;
3467 p->base_queue = phys_id;
3469 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3470 p->num_tx_qp = number;
3471 p->base_queue = phys_id;
3473 case I40E_DEV_FUNC_CAP_MSIX:
3474 p->num_msix_vectors = number;
3476 case I40E_DEV_FUNC_CAP_MSIX_VF:
3477 p->num_msix_vectors_vf = number;
3479 case I40E_DEV_FUNC_CAP_FLEX10:
3480 if (major_rev == 1) {
3482 p->flex10_enable = true;
3483 p->flex10_capable = true;
3486 /* Capability revision >= 2 */
3488 p->flex10_enable = true;
3490 p->flex10_capable = true;
3492 p->flex10_mode = logical_id;
3493 p->flex10_status = phys_id;
3495 case I40E_DEV_FUNC_CAP_CEM:
3499 case I40E_DEV_FUNC_CAP_IWARP:
3503 case I40E_DEV_FUNC_CAP_LED:
3504 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3505 p->led[phys_id] = true;
3507 case I40E_DEV_FUNC_CAP_SDP:
3508 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3509 p->sdp[phys_id] = true;
3511 case I40E_DEV_FUNC_CAP_MDIO:
3513 p->mdio_port_num = phys_id;
3514 p->mdio_port_mode = logical_id;
3517 case I40E_DEV_FUNC_CAP_IEEE_1588:
3519 p->ieee_1588 = true;
3521 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3523 p->fd_filters_guaranteed = number;
3524 p->fd_filters_best_effort = logical_id;
3526 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
3527 p->wr_csr_prot = (u64)number;
3528 p->wr_csr_prot |= (u64)logical_id << 32;
3531 case I40E_DEV_FUNC_CAP_WOL_PROXY:
3532 hw->num_wol_proxy_filters = (u16)number;
3533 hw->wol_proxy_vsi_seid = (u16)logical_id;
3534 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3535 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3536 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3538 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3539 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3540 p->proxy_support = p->proxy_support;
3549 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3551 #ifdef I40E_FCOE_ENA
3552 /* Software override ensuring FCoE is disabled if npar or mfp
3553 * mode because it is not supported in these modes.
3555 if (p->npar_enable || p->flex10_enable)
3558 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3562 /* count the enabled ports (aka the "not disabled" ports) */
3564 for (i = 0; i < 4; i++) {
3565 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3568 /* use AQ read to get the physical register offset instead
3569 * of the port relative offset
3571 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3572 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3576 valid_functions = p->valid_functions;
3578 while (valid_functions) {
3579 if (valid_functions & 1)
3581 valid_functions >>= 1;
3584 /* partition id is 1-based, and functions are evenly spread
3585 * across the ports as partitions
3587 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3588 hw->num_partitions = num_functions / hw->num_ports;
3590 /* additional HW specific goodies that might
3591 * someday be HW version specific
3593 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3597 * i40e_aq_discover_capabilities
3598 * @hw: pointer to the hw struct
3599 * @buff: a virtual buffer to hold the capabilities
3600 * @buff_size: Size of the virtual buffer
3601 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3602 * @list_type_opc: capabilities type to discover - pass in the command opcode
3603 * @cmd_details: pointer to command details structure or NULL
3605 * Get the device capabilities descriptions from the firmware
3607 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3608 void *buff, u16 buff_size, u16 *data_size,
3609 enum i40e_admin_queue_opc list_type_opc,
3610 struct i40e_asq_cmd_details *cmd_details)
3612 struct i40e_aqc_list_capabilites *cmd;
3613 struct i40e_aq_desc desc;
3614 enum i40e_status_code status = I40E_SUCCESS;
3616 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3618 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3619 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3620 status = I40E_ERR_PARAM;
3624 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3626 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3627 if (buff_size > I40E_AQ_LARGE_BUF)
3628 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3630 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3631 *data_size = LE16_TO_CPU(desc.datalen);
3636 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3644 * i40e_aq_update_nvm
3645 * @hw: pointer to the hw struct
3646 * @module_pointer: module pointer location in words from the NVM beginning
3647 * @offset: byte offset from the module beginning
3648 * @length: length of the section to be written (in bytes from the offset)
3649 * @data: command buffer (size [bytes] = length)
3650 * @last_command: tells if this is the last command in a series
3651 * @cmd_details: pointer to command details structure or NULL
3653 * Update the NVM using the admin queue commands
3655 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3656 u32 offset, u16 length, void *data,
3658 struct i40e_asq_cmd_details *cmd_details)
3660 struct i40e_aq_desc desc;
3661 struct i40e_aqc_nvm_update *cmd =
3662 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3663 enum i40e_status_code status;
3665 DEBUGFUNC("i40e_aq_update_nvm");
3667 /* In offset the highest byte must be zeroed. */
3668 if (offset & 0xFF000000) {
3669 status = I40E_ERR_PARAM;
3670 goto i40e_aq_update_nvm_exit;
3673 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3675 /* If this is the last command in a series, set the proper flag. */
3677 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3678 cmd->module_pointer = module_pointer;
3679 cmd->offset = CPU_TO_LE32(offset);
3680 cmd->length = CPU_TO_LE16(length);
3682 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3683 if (length > I40E_AQ_LARGE_BUF)
3684 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3686 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3688 i40e_aq_update_nvm_exit:
3693 * i40e_aq_get_lldp_mib
3694 * @hw: pointer to the hw struct
3695 * @bridge_type: type of bridge requested
3696 * @mib_type: Local, Remote or both Local and Remote MIBs
3697 * @buff: pointer to a user supplied buffer to store the MIB block
3698 * @buff_size: size of the buffer (in bytes)
3699 * @local_len : length of the returned Local LLDP MIB
3700 * @remote_len: length of the returned Remote LLDP MIB
3701 * @cmd_details: pointer to command details structure or NULL
3703 * Requests the complete LLDP MIB (entire packet).
3705 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3706 u8 mib_type, void *buff, u16 buff_size,
3707 u16 *local_len, u16 *remote_len,
3708 struct i40e_asq_cmd_details *cmd_details)
3710 struct i40e_aq_desc desc;
3711 struct i40e_aqc_lldp_get_mib *cmd =
3712 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3713 struct i40e_aqc_lldp_get_mib *resp =
3714 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3715 enum i40e_status_code status;
3717 if (buff_size == 0 || !buff)
3718 return I40E_ERR_PARAM;
3720 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3721 /* Indirect Command */
3722 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3724 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3725 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3726 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3728 desc.datalen = CPU_TO_LE16(buff_size);
3730 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3731 if (buff_size > I40E_AQ_LARGE_BUF)
3732 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3734 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3736 if (local_len != NULL)
3737 *local_len = LE16_TO_CPU(resp->local_len);
3738 if (remote_len != NULL)
3739 *remote_len = LE16_TO_CPU(resp->remote_len);
3746 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3747 * @hw: pointer to the hw struct
3748 * @mib_type: Local, Remote or both Local and Remote MIBs
3749 * @buff: pointer to a user supplied buffer to store the MIB block
3750 * @buff_size: size of the buffer (in bytes)
3751 * @cmd_details: pointer to command details structure or NULL
3755 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3756 u8 mib_type, void *buff, u16 buff_size,
3757 struct i40e_asq_cmd_details *cmd_details)
3759 struct i40e_aq_desc desc;
3760 struct i40e_aqc_lldp_set_local_mib *cmd =
3761 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3762 enum i40e_status_code status;
3764 if (buff_size == 0 || !buff)
3765 return I40E_ERR_PARAM;
3767 i40e_fill_default_direct_cmd_desc(&desc,
3768 i40e_aqc_opc_lldp_set_local_mib);
3769 /* Indirect Command */
3770 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3771 if (buff_size > I40E_AQ_LARGE_BUF)
3772 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3773 desc.datalen = CPU_TO_LE16(buff_size);
3775 cmd->type = mib_type;
3776 cmd->length = CPU_TO_LE16(buff_size);
3777 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3778 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3780 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3785 * i40e_aq_cfg_lldp_mib_change_event
3786 * @hw: pointer to the hw struct
3787 * @enable_update: Enable or Disable event posting
3788 * @cmd_details: pointer to command details structure or NULL
3790 * Enable or Disable posting of an event on ARQ when LLDP MIB
3791 * associated with the interface changes
3793 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3795 struct i40e_asq_cmd_details *cmd_details)
3797 struct i40e_aq_desc desc;
3798 struct i40e_aqc_lldp_update_mib *cmd =
3799 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3800 enum i40e_status_code status;
3802 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3805 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3813 * i40e_aq_add_lldp_tlv
3814 * @hw: pointer to the hw struct
3815 * @bridge_type: type of bridge
3816 * @buff: buffer with TLV to add
3817 * @buff_size: length of the buffer
3818 * @tlv_len: length of the TLV to be added
3819 * @mib_len: length of the LLDP MIB returned in response
3820 * @cmd_details: pointer to command details structure or NULL
3822 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3823 * it is responsibility of the caller to make sure that the TLV is not
3824 * already present in the LLDPDU.
3825 * In return firmware will write the complete LLDP MIB with the newly
3826 * added TLV in the response buffer.
3828 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3829 void *buff, u16 buff_size, u16 tlv_len,
3831 struct i40e_asq_cmd_details *cmd_details)
3833 struct i40e_aq_desc desc;
3834 struct i40e_aqc_lldp_add_tlv *cmd =
3835 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3836 enum i40e_status_code status;
3838 if (buff_size == 0 || !buff || tlv_len == 0)
3839 return I40E_ERR_PARAM;
3841 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3843 /* Indirect Command */
3844 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3845 if (buff_size > I40E_AQ_LARGE_BUF)
3846 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3847 desc.datalen = CPU_TO_LE16(buff_size);
3849 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3850 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3851 cmd->len = CPU_TO_LE16(tlv_len);
3853 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3855 if (mib_len != NULL)
3856 *mib_len = LE16_TO_CPU(desc.datalen);
3863 * i40e_aq_update_lldp_tlv
3864 * @hw: pointer to the hw struct
3865 * @bridge_type: type of bridge
3866 * @buff: buffer with TLV to update
3867 * @buff_size: size of the buffer holding original and updated TLVs
3868 * @old_len: Length of the Original TLV
3869 * @new_len: Length of the Updated TLV
3870 * @offset: offset of the updated TLV in the buff
3871 * @mib_len: length of the returned LLDP MIB
3872 * @cmd_details: pointer to command details structure or NULL
3874 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3875 * Firmware will place the complete LLDP MIB in response buffer with the
3878 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3879 u8 bridge_type, void *buff, u16 buff_size,
3880 u16 old_len, u16 new_len, u16 offset,
3882 struct i40e_asq_cmd_details *cmd_details)
3884 struct i40e_aq_desc desc;
3885 struct i40e_aqc_lldp_update_tlv *cmd =
3886 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3887 enum i40e_status_code status;
3889 if (buff_size == 0 || !buff || offset == 0 ||
3890 old_len == 0 || new_len == 0)
3891 return I40E_ERR_PARAM;
3893 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3895 /* Indirect Command */
3896 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3897 if (buff_size > I40E_AQ_LARGE_BUF)
3898 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3899 desc.datalen = CPU_TO_LE16(buff_size);
3901 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3902 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3903 cmd->old_len = CPU_TO_LE16(old_len);
3904 cmd->new_offset = CPU_TO_LE16(offset);
3905 cmd->new_len = CPU_TO_LE16(new_len);
3907 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3909 if (mib_len != NULL)
3910 *mib_len = LE16_TO_CPU(desc.datalen);
3917 * i40e_aq_delete_lldp_tlv
3918 * @hw: pointer to the hw struct
3919 * @bridge_type: type of bridge
3920 * @buff: pointer to a user supplied buffer that has the TLV
3921 * @buff_size: length of the buffer
3922 * @tlv_len: length of the TLV to be deleted
3923 * @mib_len: length of the returned LLDP MIB
3924 * @cmd_details: pointer to command details structure or NULL
3926 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3927 * The firmware places the entire LLDP MIB in the response buffer.
3929 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3930 u8 bridge_type, void *buff, u16 buff_size,
3931 u16 tlv_len, u16 *mib_len,
3932 struct i40e_asq_cmd_details *cmd_details)
3934 struct i40e_aq_desc desc;
3935 struct i40e_aqc_lldp_add_tlv *cmd =
3936 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3937 enum i40e_status_code status;
3939 if (buff_size == 0 || !buff)
3940 return I40E_ERR_PARAM;
3942 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3944 /* Indirect Command */
3945 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3946 if (buff_size > I40E_AQ_LARGE_BUF)
3947 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3948 desc.datalen = CPU_TO_LE16(buff_size);
3949 cmd->len = CPU_TO_LE16(tlv_len);
3950 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3951 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3953 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3955 if (mib_len != NULL)
3956 *mib_len = LE16_TO_CPU(desc.datalen);
3964 * @hw: pointer to the hw struct
3965 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3966 * @cmd_details: pointer to command details structure or NULL
3968 * Stop or Shutdown the embedded LLDP Agent
3970 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3971 struct i40e_asq_cmd_details *cmd_details)
3973 struct i40e_aq_desc desc;
3974 struct i40e_aqc_lldp_stop *cmd =
3975 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3976 enum i40e_status_code status;
3978 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3981 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3983 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3989 * i40e_aq_start_lldp
3990 * @hw: pointer to the hw struct
3991 * @cmd_details: pointer to command details structure or NULL
3993 * Start the embedded LLDP Agent on all ports.
3995 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3996 struct i40e_asq_cmd_details *cmd_details)
3998 struct i40e_aq_desc desc;
3999 struct i40e_aqc_lldp_start *cmd =
4000 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4001 enum i40e_status_code status;
4003 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4005 cmd->command = I40E_AQ_LLDP_AGENT_START;
4007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4013 * i40e_aq_get_cee_dcb_config
4014 * @hw: pointer to the hw struct
4015 * @buff: response buffer that stores CEE operational configuration
4016 * @buff_size: size of the buffer passed
4017 * @cmd_details: pointer to command details structure or NULL
4019 * Get CEE DCBX mode operational configuration from firmware
4021 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4022 void *buff, u16 buff_size,
4023 struct i40e_asq_cmd_details *cmd_details)
4025 struct i40e_aq_desc desc;
4026 enum i40e_status_code status;
4028 if (buff_size == 0 || !buff)
4029 return I40E_ERR_PARAM;
4031 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4033 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4034 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4041 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4042 * @hw: pointer to the hw struct
4043 * @start_agent: True if DCBx Agent needs to be Started
4044 * False if DCBx Agent needs to be Stopped
4045 * @cmd_details: pointer to command details structure or NULL
4047 * Start/Stop the embedded dcbx Agent
4049 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4051 struct i40e_asq_cmd_details *cmd_details)
4053 struct i40e_aq_desc desc;
4054 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4055 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4057 enum i40e_status_code status;
4059 i40e_fill_default_direct_cmd_desc(&desc,
4060 i40e_aqc_opc_lldp_stop_start_spec_agent);
4063 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4065 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4071 * i40e_aq_add_udp_tunnel
4072 * @hw: pointer to the hw struct
4073 * @udp_port: the UDP port to add
4074 * @header_len: length of the tunneling header length in DWords
4075 * @protocol_index: protocol index type
4076 * @filter_index: pointer to filter index
4077 * @cmd_details: pointer to command details structure or NULL
4079 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4080 u16 udp_port, u8 protocol_index,
4082 struct i40e_asq_cmd_details *cmd_details)
4084 struct i40e_aq_desc desc;
4085 struct i40e_aqc_add_udp_tunnel *cmd =
4086 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4087 struct i40e_aqc_del_udp_tunnel_completion *resp =
4088 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4089 enum i40e_status_code status;
4091 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4093 cmd->udp_port = CPU_TO_LE16(udp_port);
4094 cmd->protocol_type = protocol_index;
4096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4098 if (!status && filter_index)
4099 *filter_index = resp->index;
4105 * i40e_aq_del_udp_tunnel
4106 * @hw: pointer to the hw struct
4107 * @index: filter index
4108 * @cmd_details: pointer to command details structure or NULL
4110 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4111 struct i40e_asq_cmd_details *cmd_details)
4113 struct i40e_aq_desc desc;
4114 struct i40e_aqc_remove_udp_tunnel *cmd =
4115 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4116 enum i40e_status_code status;
4118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4128 * i40e_aq_get_switch_resource_alloc (0x0204)
4129 * @hw: pointer to the hw struct
4130 * @num_entries: pointer to u8 to store the number of resource entries returned
4131 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4132 * to store the resource information for all resource types. Each
4133 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4134 * @count: size, in bytes, of the buffer provided
4135 * @cmd_details: pointer to command details structure or NULL
4137 * Query the resources allocated to a function.
4139 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4141 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4143 struct i40e_asq_cmd_details *cmd_details)
4145 struct i40e_aq_desc desc;
4146 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4147 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4148 enum i40e_status_code status;
4149 u16 length = count * sizeof(*buf);
4151 i40e_fill_default_direct_cmd_desc(&desc,
4152 i40e_aqc_opc_get_switch_resource_alloc);
4154 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4155 if (length > I40E_AQ_LARGE_BUF)
4156 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4158 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4160 if (!status && num_entries)
4161 *num_entries = cmd_resp->num_entries;
4167 * i40e_aq_delete_element - Delete switch element
4168 * @hw: pointer to the hw struct
4169 * @seid: the SEID to delete from the switch
4170 * @cmd_details: pointer to command details structure or NULL
4172 * This deletes a switch element from the switch.
4174 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4175 struct i40e_asq_cmd_details *cmd_details)
4177 struct i40e_aq_desc desc;
4178 struct i40e_aqc_switch_seid *cmd =
4179 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4180 enum i40e_status_code status;
4183 return I40E_ERR_PARAM;
4185 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4187 cmd->seid = CPU_TO_LE16(seid);
4189 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4195 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4196 * @hw: pointer to the hw struct
4197 * @flags: component flags
4198 * @mac_seid: uplink seid (MAC SEID)
4199 * @vsi_seid: connected vsi seid
4200 * @ret_seid: seid of create pv component
4202 * This instantiates an i40e port virtualizer with specified flags.
4203 * Depending on specified flags the port virtualizer can act as a
4204 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4206 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4207 u16 mac_seid, u16 vsi_seid,
4210 struct i40e_aq_desc desc;
4211 struct i40e_aqc_add_update_pv *cmd =
4212 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4213 struct i40e_aqc_add_update_pv_completion *resp =
4214 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4215 enum i40e_status_code status;
4218 return I40E_ERR_PARAM;
4220 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4221 cmd->command_flags = CPU_TO_LE16(flags);
4222 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4223 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4225 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4226 if (!status && ret_seid)
4227 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4233 * i40e_aq_add_tag - Add an S/E-tag
4234 * @hw: pointer to the hw struct
4235 * @direct_to_queue: should s-tag direct flow to a specific queue
4236 * @vsi_seid: VSI SEID to use this tag
4237 * @tag: value of the tag
4238 * @queue_num: queue number, only valid is direct_to_queue is true
4239 * @tags_used: return value, number of tags in use by this PF
4240 * @tags_free: return value, number of unallocated tags
4241 * @cmd_details: pointer to command details structure or NULL
4243 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4244 * the number of tags allocated by the PF, and the number of unallocated
4247 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4248 u16 vsi_seid, u16 tag, u16 queue_num,
4249 u16 *tags_used, u16 *tags_free,
4250 struct i40e_asq_cmd_details *cmd_details)
4252 struct i40e_aq_desc desc;
4253 struct i40e_aqc_add_tag *cmd =
4254 (struct i40e_aqc_add_tag *)&desc.params.raw;
4255 struct i40e_aqc_add_remove_tag_completion *resp =
4256 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4257 enum i40e_status_code status;
4260 return I40E_ERR_PARAM;
4262 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4264 cmd->seid = CPU_TO_LE16(vsi_seid);
4265 cmd->tag = CPU_TO_LE16(tag);
4266 if (direct_to_queue) {
4267 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4268 cmd->queue_number = CPU_TO_LE16(queue_num);
4271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4274 if (tags_used != NULL)
4275 *tags_used = LE16_TO_CPU(resp->tags_used);
4276 if (tags_free != NULL)
4277 *tags_free = LE16_TO_CPU(resp->tags_free);
4284 * i40e_aq_remove_tag - Remove an S- or E-tag
4285 * @hw: pointer to the hw struct
4286 * @vsi_seid: VSI SEID this tag is associated with
4287 * @tag: value of the S-tag to delete
4288 * @tags_used: return value, number of tags in use by this PF
4289 * @tags_free: return value, number of unallocated tags
4290 * @cmd_details: pointer to command details structure or NULL
4292 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4293 * the number of tags allocated by the PF, and the number of unallocated
4296 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4297 u16 tag, u16 *tags_used, u16 *tags_free,
4298 struct i40e_asq_cmd_details *cmd_details)
4300 struct i40e_aq_desc desc;
4301 struct i40e_aqc_remove_tag *cmd =
4302 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4303 struct i40e_aqc_add_remove_tag_completion *resp =
4304 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4305 enum i40e_status_code status;
4308 return I40E_ERR_PARAM;
4310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4312 cmd->seid = CPU_TO_LE16(vsi_seid);
4313 cmd->tag = CPU_TO_LE16(tag);
4315 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4318 if (tags_used != NULL)
4319 *tags_used = LE16_TO_CPU(resp->tags_used);
4320 if (tags_free != NULL)
4321 *tags_free = LE16_TO_CPU(resp->tags_free);
4328 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4329 * @hw: pointer to the hw struct
4330 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4331 * @etag: value of E-tag to add
4332 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4333 * @buf: address of indirect buffer
4334 * @tags_used: return value, number of E-tags in use by this port
4335 * @tags_free: return value, number of unallocated M-tags
4336 * @cmd_details: pointer to command details structure or NULL
4338 * This associates a multicast E-tag to a port virtualizer. It will return
4339 * the number of tags allocated by the PF, and the number of unallocated
4342 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4343 * num_tags_in_buf long.
4345 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4346 u16 etag, u8 num_tags_in_buf, void *buf,
4347 u16 *tags_used, u16 *tags_free,
4348 struct i40e_asq_cmd_details *cmd_details)
4350 struct i40e_aq_desc desc;
4351 struct i40e_aqc_add_remove_mcast_etag *cmd =
4352 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4353 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4354 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4355 enum i40e_status_code status;
4356 u16 length = sizeof(u16) * num_tags_in_buf;
4358 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4359 return I40E_ERR_PARAM;
4361 i40e_fill_default_direct_cmd_desc(&desc,
4362 i40e_aqc_opc_add_multicast_etag);
4364 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4365 cmd->etag = CPU_TO_LE16(etag);
4366 cmd->num_unicast_etags = num_tags_in_buf;
4368 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4369 if (length > I40E_AQ_LARGE_BUF)
4370 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4372 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4375 if (tags_used != NULL)
4376 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4377 if (tags_free != NULL)
4378 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4385 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4386 * @hw: pointer to the hw struct
4387 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4388 * @etag: value of the E-tag to remove
4389 * @tags_used: return value, number of tags in use by this port
4390 * @tags_free: return value, number of unallocated tags
4391 * @cmd_details: pointer to command details structure or NULL
4393 * This deletes an E-tag from the port virtualizer. It will return
4394 * the number of tags allocated by the port, and the number of unallocated
4397 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4398 u16 etag, u16 *tags_used, u16 *tags_free,
4399 struct i40e_asq_cmd_details *cmd_details)
4401 struct i40e_aq_desc desc;
4402 struct i40e_aqc_add_remove_mcast_etag *cmd =
4403 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4404 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4405 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4406 enum i40e_status_code status;
4410 return I40E_ERR_PARAM;
4412 i40e_fill_default_direct_cmd_desc(&desc,
4413 i40e_aqc_opc_remove_multicast_etag);
4415 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4416 cmd->etag = CPU_TO_LE16(etag);
4418 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4421 if (tags_used != NULL)
4422 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4423 if (tags_free != NULL)
4424 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4431 * i40e_aq_update_tag - Update an S/E-tag
4432 * @hw: pointer to the hw struct
4433 * @vsi_seid: VSI SEID using this S-tag
4434 * @old_tag: old tag value
4435 * @new_tag: new tag value
4436 * @tags_used: return value, number of tags in use by this PF
4437 * @tags_free: return value, number of unallocated tags
4438 * @cmd_details: pointer to command details structure or NULL
4440 * This updates the value of the tag currently attached to this VSI
4441 * in the switch complex. It will return the number of tags allocated
4442 * by the PF, and the number of unallocated tags available.
4444 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4445 u16 old_tag, u16 new_tag, u16 *tags_used,
4447 struct i40e_asq_cmd_details *cmd_details)
4449 struct i40e_aq_desc desc;
4450 struct i40e_aqc_update_tag *cmd =
4451 (struct i40e_aqc_update_tag *)&desc.params.raw;
4452 struct i40e_aqc_update_tag_completion *resp =
4453 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4454 enum i40e_status_code status;
4457 return I40E_ERR_PARAM;
4459 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4461 cmd->seid = CPU_TO_LE16(vsi_seid);
4462 cmd->old_tag = CPU_TO_LE16(old_tag);
4463 cmd->new_tag = CPU_TO_LE16(new_tag);
4465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4468 if (tags_used != NULL)
4469 *tags_used = LE16_TO_CPU(resp->tags_used);
4470 if (tags_free != NULL)
4471 *tags_free = LE16_TO_CPU(resp->tags_free);
4478 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4479 * @hw: pointer to the hw struct
4480 * @tcmap: TC map for request/release any ignore PFC condition
4481 * @request: request or release ignore PFC condition
4482 * @tcmap_ret: return TCs for which PFC is currently ignored
4483 * @cmd_details: pointer to command details structure or NULL
4485 * This sends out request/release to ignore PFC condition for a TC.
4486 * It will return the TCs for which PFC is currently ignored.
4488 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4489 bool request, u8 *tcmap_ret,
4490 struct i40e_asq_cmd_details *cmd_details)
4492 struct i40e_aq_desc desc;
4493 struct i40e_aqc_pfc_ignore *cmd_resp =
4494 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4495 enum i40e_status_code status;
4497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4500 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4502 cmd_resp->tc_bitmap = tcmap;
4504 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4507 if (tcmap_ret != NULL)
4508 *tcmap_ret = cmd_resp->tc_bitmap;
4515 * i40e_aq_dcb_updated - DCB Updated Command
4516 * @hw: pointer to the hw struct
4517 * @cmd_details: pointer to command details structure or NULL
4519 * When LLDP is handled in PF this command is used by the PF
4520 * to notify EMP that a DCB setting is modified.
4521 * When LLDP is handled in EMP this command is used by the PF
4522 * to notify EMP whenever one of the following parameters get
4524 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4525 * - PCIRTT in PRTDCB_GENC.PCIRTT
4526 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4527 * EMP will return when the shared RPB settings have been
4528 * recomputed and modified. The retval field in the descriptor
4529 * will be set to 0 when RPB is modified.
4531 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4532 struct i40e_asq_cmd_details *cmd_details)
4534 struct i40e_aq_desc desc;
4535 enum i40e_status_code status;
4537 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4539 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4545 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4546 * @hw: pointer to the hw struct
4547 * @seid: defines the SEID of the switch for which the stats are requested
4548 * @vlan_id: the VLAN ID for which the statistics are requested
4549 * @stat_index: index of the statistics counters block assigned to this VLAN
4550 * @cmd_details: pointer to command details structure or NULL
4552 * XL710 supports 128 smonVlanStats counters.This command is used to
4553 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4556 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4557 u16 vlan_id, u16 *stat_index,
4558 struct i40e_asq_cmd_details *cmd_details)
4560 struct i40e_aq_desc desc;
4561 struct i40e_aqc_add_remove_statistics *cmd_resp =
4562 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4563 enum i40e_status_code status;
4565 if ((seid == 0) || (stat_index == NULL))
4566 return I40E_ERR_PARAM;
4568 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4570 cmd_resp->seid = CPU_TO_LE16(seid);
4571 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4573 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4575 if (!status && stat_index)
4576 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4582 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4583 * @hw: pointer to the hw struct
4584 * @seid: defines the SEID of the switch for which the stats are requested
4585 * @vlan_id: the VLAN ID for which the statistics are requested
4586 * @stat_index: index of the statistics counters block assigned to this VLAN
4587 * @cmd_details: pointer to command details structure or NULL
4589 * XL710 supports 128 smonVlanStats counters.This command is used to
4590 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4593 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4594 u16 vlan_id, u16 stat_index,
4595 struct i40e_asq_cmd_details *cmd_details)
4597 struct i40e_aq_desc desc;
4598 struct i40e_aqc_add_remove_statistics *cmd =
4599 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4600 enum i40e_status_code status;
4603 return I40E_ERR_PARAM;
4605 i40e_fill_default_direct_cmd_desc(&desc,
4606 i40e_aqc_opc_remove_statistics);
4608 cmd->seid = CPU_TO_LE16(seid);
4609 cmd->vlan = CPU_TO_LE16(vlan_id);
4610 cmd->stat_index = CPU_TO_LE16(stat_index);
4612 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4618 * i40e_aq_set_port_parameters - set physical port parameters.
4619 * @hw: pointer to the hw struct
4620 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4621 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4622 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4623 * @double_vlan: if set double VLAN is enabled
4624 * @cmd_details: pointer to command details structure or NULL
4626 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4627 u16 bad_frame_vsi, bool save_bad_pac,
4628 bool pad_short_pac, bool double_vlan,
4629 struct i40e_asq_cmd_details *cmd_details)
4631 struct i40e_aqc_set_port_parameters *cmd;
4632 enum i40e_status_code status;
4633 struct i40e_aq_desc desc;
4634 u16 command_flags = 0;
4636 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4638 i40e_fill_default_direct_cmd_desc(&desc,
4639 i40e_aqc_opc_set_port_parameters);
4641 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4643 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4645 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4647 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4648 cmd->command_flags = CPU_TO_LE16(command_flags);
4650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4656 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4657 * @hw: pointer to the hw struct
4658 * @seid: seid for the physical port/switching component/vsi
4659 * @buff: Indirect buffer to hold data parameters and response
4660 * @buff_size: Indirect buffer size
4661 * @opcode: Tx scheduler AQ command opcode
4662 * @cmd_details: pointer to command details structure or NULL
4664 * Generic command handler for Tx scheduler AQ commands
4666 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4667 void *buff, u16 buff_size,
4668 enum i40e_admin_queue_opc opcode,
4669 struct i40e_asq_cmd_details *cmd_details)
4671 struct i40e_aq_desc desc;
4672 struct i40e_aqc_tx_sched_ind *cmd =
4673 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4674 enum i40e_status_code status;
4675 bool cmd_param_flag = false;
4678 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4679 case i40e_aqc_opc_configure_vsi_tc_bw:
4680 case i40e_aqc_opc_enable_switching_comp_ets:
4681 case i40e_aqc_opc_modify_switching_comp_ets:
4682 case i40e_aqc_opc_disable_switching_comp_ets:
4683 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4684 case i40e_aqc_opc_configure_switching_comp_bw_config:
4685 cmd_param_flag = true;
4687 case i40e_aqc_opc_query_vsi_bw_config:
4688 case i40e_aqc_opc_query_vsi_ets_sla_config:
4689 case i40e_aqc_opc_query_switching_comp_ets_config:
4690 case i40e_aqc_opc_query_port_ets_config:
4691 case i40e_aqc_opc_query_switching_comp_bw_config:
4692 cmd_param_flag = false;
4695 return I40E_ERR_PARAM;
4698 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4700 /* Indirect command */
4701 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4704 if (buff_size > I40E_AQ_LARGE_BUF)
4705 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4707 desc.datalen = CPU_TO_LE16(buff_size);
4709 cmd->vsi_seid = CPU_TO_LE16(seid);
4711 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4717 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4718 * @hw: pointer to the hw struct
4720 * @credit: BW limit credits (0 = disabled)
4721 * @max_credit: Max BW limit credits
4722 * @cmd_details: pointer to command details structure or NULL
4724 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4725 u16 seid, u16 credit, u8 max_credit,
4726 struct i40e_asq_cmd_details *cmd_details)
4728 struct i40e_aq_desc desc;
4729 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4730 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4731 enum i40e_status_code status;
4733 i40e_fill_default_direct_cmd_desc(&desc,
4734 i40e_aqc_opc_configure_vsi_bw_limit);
4736 cmd->vsi_seid = CPU_TO_LE16(seid);
4737 cmd->credit = CPU_TO_LE16(credit);
4738 cmd->max_credit = max_credit;
4740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4746 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4747 * @hw: pointer to the hw struct
4748 * @seid: switching component seid
4749 * @credit: BW limit credits (0 = disabled)
4750 * @max_bw: Max BW limit credits
4751 * @cmd_details: pointer to command details structure or NULL
4753 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4754 u16 seid, u16 credit, u8 max_bw,
4755 struct i40e_asq_cmd_details *cmd_details)
4757 struct i40e_aq_desc desc;
4758 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4759 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4760 enum i40e_status_code status;
4762 i40e_fill_default_direct_cmd_desc(&desc,
4763 i40e_aqc_opc_configure_switching_comp_bw_limit);
4765 cmd->seid = CPU_TO_LE16(seid);
4766 cmd->credit = CPU_TO_LE16(credit);
4767 cmd->max_bw = max_bw;
4769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4775 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4776 * @hw: pointer to the hw struct
4778 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4779 * @cmd_details: pointer to command details structure or NULL
4781 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4783 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4784 struct i40e_asq_cmd_details *cmd_details)
4786 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4787 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4792 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4793 * @hw: pointer to the hw struct
4795 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4796 * @cmd_details: pointer to command details structure or NULL
4798 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4800 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4801 struct i40e_asq_cmd_details *cmd_details)
4803 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4804 i40e_aqc_opc_configure_vsi_tc_bw,
4809 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4810 * @hw: pointer to the hw struct
4811 * @seid: seid of the switching component connected to Physical Port
4812 * @ets_data: Buffer holding ETS parameters
4813 * @cmd_details: pointer to command details structure or NULL
4815 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4817 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4818 enum i40e_admin_queue_opc opcode,
4819 struct i40e_asq_cmd_details *cmd_details)
4821 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4822 sizeof(*ets_data), opcode, cmd_details);
4826 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4827 * @hw: pointer to the hw struct
4828 * @seid: seid of the switching component
4829 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4830 * @cmd_details: pointer to command details structure or NULL
4832 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4834 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4835 struct i40e_asq_cmd_details *cmd_details)
4837 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4838 i40e_aqc_opc_configure_switching_comp_bw_config,
4843 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4844 * @hw: pointer to the hw struct
4845 * @seid: seid of the switching component
4846 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4847 * @cmd_details: pointer to command details structure or NULL
4849 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4850 struct i40e_hw *hw, u16 seid,
4851 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4852 struct i40e_asq_cmd_details *cmd_details)
4854 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4855 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4860 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4861 * @hw: pointer to the hw struct
4862 * @seid: seid of the VSI
4863 * @bw_data: Buffer to hold VSI BW configuration
4864 * @cmd_details: pointer to command details structure or NULL
4866 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4868 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4869 struct i40e_asq_cmd_details *cmd_details)
4871 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4872 i40e_aqc_opc_query_vsi_bw_config,
4877 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4878 * @hw: pointer to the hw struct
4879 * @seid: seid of the VSI
4880 * @bw_data: Buffer to hold VSI BW configuration per TC
4881 * @cmd_details: pointer to command details structure or NULL
4883 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4885 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4886 struct i40e_asq_cmd_details *cmd_details)
4888 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4889 i40e_aqc_opc_query_vsi_ets_sla_config,
4894 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4895 * @hw: pointer to the hw struct
4896 * @seid: seid of the switching component
4897 * @bw_data: Buffer to hold switching component's per TC BW config
4898 * @cmd_details: pointer to command details structure or NULL
4900 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4902 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4903 struct i40e_asq_cmd_details *cmd_details)
4905 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4906 i40e_aqc_opc_query_switching_comp_ets_config,
4911 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4912 * @hw: pointer to the hw struct
4913 * @seid: seid of the VSI or switching component connected to Physical Port
4914 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4915 * @cmd_details: pointer to command details structure or NULL
4917 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4919 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4920 struct i40e_asq_cmd_details *cmd_details)
4922 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4923 i40e_aqc_opc_query_port_ets_config,
4928 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4929 * @hw: pointer to the hw struct
4930 * @seid: seid of the switching component
4931 * @bw_data: Buffer to hold switching component's BW configuration
4932 * @cmd_details: pointer to command details structure or NULL
4934 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4936 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4937 struct i40e_asq_cmd_details *cmd_details)
4939 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4940 i40e_aqc_opc_query_switching_comp_bw_config,
4945 * i40e_validate_filter_settings
4946 * @hw: pointer to the hardware structure
4947 * @settings: Filter control settings
4949 * Check and validate the filter control settings passed.
4950 * The function checks for the valid filter/context sizes being
4951 * passed for FCoE and PE.
4953 * Returns I40E_SUCCESS if the values passed are valid and within
4954 * range else returns an error.
4956 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4957 struct i40e_filter_control_settings *settings)
4959 u32 fcoe_cntx_size, fcoe_filt_size;
4960 u32 pe_cntx_size, pe_filt_size;
4965 /* Validate FCoE settings passed */
4966 switch (settings->fcoe_filt_num) {
4967 case I40E_HASH_FILTER_SIZE_1K:
4968 case I40E_HASH_FILTER_SIZE_2K:
4969 case I40E_HASH_FILTER_SIZE_4K:
4970 case I40E_HASH_FILTER_SIZE_8K:
4971 case I40E_HASH_FILTER_SIZE_16K:
4972 case I40E_HASH_FILTER_SIZE_32K:
4973 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4974 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4977 return I40E_ERR_PARAM;
4980 switch (settings->fcoe_cntx_num) {
4981 case I40E_DMA_CNTX_SIZE_512:
4982 case I40E_DMA_CNTX_SIZE_1K:
4983 case I40E_DMA_CNTX_SIZE_2K:
4984 case I40E_DMA_CNTX_SIZE_4K:
4985 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4986 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4989 return I40E_ERR_PARAM;
4992 /* Validate PE settings passed */
4993 switch (settings->pe_filt_num) {
4994 case I40E_HASH_FILTER_SIZE_1K:
4995 case I40E_HASH_FILTER_SIZE_2K:
4996 case I40E_HASH_FILTER_SIZE_4K:
4997 case I40E_HASH_FILTER_SIZE_8K:
4998 case I40E_HASH_FILTER_SIZE_16K:
4999 case I40E_HASH_FILTER_SIZE_32K:
5000 case I40E_HASH_FILTER_SIZE_64K:
5001 case I40E_HASH_FILTER_SIZE_128K:
5002 case I40E_HASH_FILTER_SIZE_256K:
5003 case I40E_HASH_FILTER_SIZE_512K:
5004 case I40E_HASH_FILTER_SIZE_1M:
5005 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5006 pe_filt_size <<= (u32)settings->pe_filt_num;
5009 return I40E_ERR_PARAM;
5012 switch (settings->pe_cntx_num) {
5013 case I40E_DMA_CNTX_SIZE_512:
5014 case I40E_DMA_CNTX_SIZE_1K:
5015 case I40E_DMA_CNTX_SIZE_2K:
5016 case I40E_DMA_CNTX_SIZE_4K:
5017 case I40E_DMA_CNTX_SIZE_8K:
5018 case I40E_DMA_CNTX_SIZE_16K:
5019 case I40E_DMA_CNTX_SIZE_32K:
5020 case I40E_DMA_CNTX_SIZE_64K:
5021 case I40E_DMA_CNTX_SIZE_128K:
5022 case I40E_DMA_CNTX_SIZE_256K:
5023 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5024 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5027 return I40E_ERR_PARAM;
5030 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5031 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5032 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5033 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5034 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5035 return I40E_ERR_INVALID_SIZE;
5037 return I40E_SUCCESS;
5041 * i40e_set_filter_control
5042 * @hw: pointer to the hardware structure
5043 * @settings: Filter control settings
5045 * Set the Queue Filters for PE/FCoE and enable filters required
5046 * for a single PF. It is expected that these settings are programmed
5047 * at the driver initialization time.
5049 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5050 struct i40e_filter_control_settings *settings)
5052 enum i40e_status_code ret = I40E_SUCCESS;
5053 u32 hash_lut_size = 0;
5057 return I40E_ERR_PARAM;
5059 /* Validate the input settings */
5060 ret = i40e_validate_filter_settings(hw, settings);
5064 /* Read the PF Queue Filter control register */
5065 val = rd32(hw, I40E_PFQF_CTL_0);
5067 /* Program required PE hash buckets for the PF */
5068 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5069 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5070 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5071 /* Program required PE contexts for the PF */
5072 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5073 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5074 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5076 /* Program required FCoE hash buckets for the PF */
5077 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5078 val |= ((u32)settings->fcoe_filt_num <<
5079 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5080 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5081 /* Program required FCoE DDP contexts for the PF */
5082 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5083 val |= ((u32)settings->fcoe_cntx_num <<
5084 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5085 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5087 /* Program Hash LUT size for the PF */
5088 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5089 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5091 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5092 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5094 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5095 if (settings->enable_fdir)
5096 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5097 if (settings->enable_ethtype)
5098 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5099 if (settings->enable_macvlan)
5100 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5102 wr32(hw, I40E_PFQF_CTL_0, val);
5104 return I40E_SUCCESS;
5108 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5109 * @hw: pointer to the hw struct
5110 * @mac_addr: MAC address to use in the filter
5111 * @ethtype: Ethertype to use in the filter
5112 * @flags: Flags that needs to be applied to the filter
5113 * @vsi_seid: seid of the control VSI
5114 * @queue: VSI queue number to send the packet to
5115 * @is_add: Add control packet filter if True else remove
5116 * @stats: Structure to hold information on control filter counts
5117 * @cmd_details: pointer to command details structure or NULL
5119 * This command will Add or Remove control packet filter for a control VSI.
5120 * In return it will update the total number of perfect filter count in
5123 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5124 u8 *mac_addr, u16 ethtype, u16 flags,
5125 u16 vsi_seid, u16 queue, bool is_add,
5126 struct i40e_control_filter_stats *stats,
5127 struct i40e_asq_cmd_details *cmd_details)
5129 struct i40e_aq_desc desc;
5130 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5131 (struct i40e_aqc_add_remove_control_packet_filter *)
5133 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5134 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5136 enum i40e_status_code status;
5139 return I40E_ERR_PARAM;
5142 i40e_fill_default_direct_cmd_desc(&desc,
5143 i40e_aqc_opc_add_control_packet_filter);
5144 cmd->queue = CPU_TO_LE16(queue);
5146 i40e_fill_default_direct_cmd_desc(&desc,
5147 i40e_aqc_opc_remove_control_packet_filter);
5151 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5152 I40E_NONDMA_TO_NONDMA);
5154 cmd->etype = CPU_TO_LE16(ethtype);
5155 cmd->flags = CPU_TO_LE16(flags);
5156 cmd->seid = CPU_TO_LE16(vsi_seid);
5158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5160 if (!status && stats) {
5161 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5162 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5163 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5164 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5171 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5172 * @hw: pointer to the hw struct
5173 * @seid: VSI seid to add ethertype filter from
5175 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5176 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5179 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5180 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5181 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5182 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5183 enum i40e_status_code status;
5185 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5186 seid, 0, true, NULL,
5189 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5193 * i40e_aq_add_cloud_filters
5194 * @hw: pointer to the hardware structure
5195 * @seid: VSI seid to add cloud filters from
5196 * @filters: Buffer which contains the filters to be added
5197 * @filter_count: number of filters contained in the buffer
5199 * Set the cloud filters for a given VSI. The contents of the
5200 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5201 * in by the caller of the function.
5204 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5206 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5209 struct i40e_aq_desc desc;
5210 struct i40e_aqc_add_remove_cloud_filters *cmd =
5211 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5213 enum i40e_status_code status;
5215 i40e_fill_default_direct_cmd_desc(&desc,
5216 i40e_aqc_opc_add_cloud_filters);
5218 buff_len = filter_count * sizeof(*filters);
5219 desc.datalen = CPU_TO_LE16(buff_len);
5220 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5221 cmd->num_filters = filter_count;
5222 cmd->seid = CPU_TO_LE16(seid);
5224 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5230 * i40e_aq_remove_cloud_filters
5231 * @hw: pointer to the hardware structure
5232 * @seid: VSI seid to remove cloud filters from
5233 * @filters: Buffer which contains the filters to be removed
5234 * @filter_count: number of filters contained in the buffer
5236 * Remove the cloud filters for a given VSI. The contents of the
5237 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5238 * in by the caller of the function.
5241 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5243 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5246 struct i40e_aq_desc desc;
5247 struct i40e_aqc_add_remove_cloud_filters *cmd =
5248 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5249 enum i40e_status_code status;
5252 i40e_fill_default_direct_cmd_desc(&desc,
5253 i40e_aqc_opc_remove_cloud_filters);
5255 buff_len = filter_count * sizeof(*filters);
5256 desc.datalen = CPU_TO_LE16(buff_len);
5257 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5258 cmd->num_filters = filter_count;
5259 cmd->seid = CPU_TO_LE16(seid);
5261 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5267 * i40e_aq_alternate_write
5268 * @hw: pointer to the hardware structure
5269 * @reg_addr0: address of first dword to be read
5270 * @reg_val0: value to be written under 'reg_addr0'
5271 * @reg_addr1: address of second dword to be read
5272 * @reg_val1: value to be written under 'reg_addr1'
5274 * Write one or two dwords to alternate structure. Fields are indicated
5275 * by 'reg_addr0' and 'reg_addr1' register numbers.
5278 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5279 u32 reg_addr0, u32 reg_val0,
5280 u32 reg_addr1, u32 reg_val1)
5282 struct i40e_aq_desc desc;
5283 struct i40e_aqc_alternate_write *cmd_resp =
5284 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5285 enum i40e_status_code status;
5287 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5288 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5289 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5290 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5291 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5293 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5299 * i40e_aq_alternate_write_indirect
5300 * @hw: pointer to the hardware structure
5301 * @addr: address of a first register to be modified
5302 * @dw_count: number of alternate structure fields to write
5303 * @buffer: pointer to the command buffer
5305 * Write 'dw_count' dwords from 'buffer' to alternate structure
5306 * starting at 'addr'.
5309 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5310 u32 addr, u32 dw_count, void *buffer)
5312 struct i40e_aq_desc desc;
5313 struct i40e_aqc_alternate_ind_write *cmd_resp =
5314 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5315 enum i40e_status_code status;
5318 return I40E_ERR_PARAM;
5320 /* Indirect command */
5321 i40e_fill_default_direct_cmd_desc(&desc,
5322 i40e_aqc_opc_alternate_write_indirect);
5324 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5325 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5326 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5327 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5329 cmd_resp->address = CPU_TO_LE32(addr);
5330 cmd_resp->length = CPU_TO_LE32(dw_count);
5332 status = i40e_asq_send_command(hw, &desc, buffer,
5333 I40E_LO_DWORD(4*dw_count), NULL);
5339 * i40e_aq_alternate_read
5340 * @hw: pointer to the hardware structure
5341 * @reg_addr0: address of first dword to be read
5342 * @reg_val0: pointer for data read from 'reg_addr0'
5343 * @reg_addr1: address of second dword to be read
5344 * @reg_val1: pointer for data read from 'reg_addr1'
5346 * Read one or two dwords from alternate structure. Fields are indicated
5347 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5348 * is not passed then only register at 'reg_addr0' is read.
5351 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5352 u32 reg_addr0, u32 *reg_val0,
5353 u32 reg_addr1, u32 *reg_val1)
5355 struct i40e_aq_desc desc;
5356 struct i40e_aqc_alternate_write *cmd_resp =
5357 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5358 enum i40e_status_code status;
5360 if (reg_val0 == NULL)
5361 return I40E_ERR_PARAM;
5363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5364 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5365 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5367 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5369 if (status == I40E_SUCCESS) {
5370 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5372 if (reg_val1 != NULL)
5373 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5380 * i40e_aq_alternate_read_indirect
5381 * @hw: pointer to the hardware structure
5382 * @addr: address of the alternate structure field
5383 * @dw_count: number of alternate structure fields to read
5384 * @buffer: pointer to the command buffer
5386 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5387 * place them in 'buffer'. The buffer should be allocated by caller.
5390 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5391 u32 addr, u32 dw_count, void *buffer)
5393 struct i40e_aq_desc desc;
5394 struct i40e_aqc_alternate_ind_write *cmd_resp =
5395 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5396 enum i40e_status_code status;
5399 return I40E_ERR_PARAM;
5401 /* Indirect command */
5402 i40e_fill_default_direct_cmd_desc(&desc,
5403 i40e_aqc_opc_alternate_read_indirect);
5405 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5406 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5407 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5408 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5410 cmd_resp->address = CPU_TO_LE32(addr);
5411 cmd_resp->length = CPU_TO_LE32(dw_count);
5413 status = i40e_asq_send_command(hw, &desc, buffer,
5414 I40E_LO_DWORD(4*dw_count), NULL);
5420 * i40e_aq_alternate_clear
5421 * @hw: pointer to the HW structure.
5423 * Clear the alternate structures of the port from which the function
5427 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5429 struct i40e_aq_desc desc;
5430 enum i40e_status_code status;
5432 i40e_fill_default_direct_cmd_desc(&desc,
5433 i40e_aqc_opc_alternate_clear_port);
5435 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5441 * i40e_aq_alternate_write_done
5442 * @hw: pointer to the HW structure.
5443 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5444 * @reset_needed: indicates the SW should trigger GLOBAL reset
5446 * Indicates to the FW that alternate structures have been changed.
5449 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5450 u8 bios_mode, bool *reset_needed)
5452 struct i40e_aq_desc desc;
5453 struct i40e_aqc_alternate_write_done *cmd =
5454 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5455 enum i40e_status_code status;
5457 if (reset_needed == NULL)
5458 return I40E_ERR_PARAM;
5460 i40e_fill_default_direct_cmd_desc(&desc,
5461 i40e_aqc_opc_alternate_write_done);
5463 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5465 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5466 if (!status && reset_needed)
5467 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5468 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5474 * i40e_aq_set_oem_mode
5475 * @hw: pointer to the HW structure.
5476 * @oem_mode: the OEM mode to be used
5478 * Sets the device to a specific operating mode. Currently the only supported
5479 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5482 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5485 struct i40e_aq_desc desc;
5486 struct i40e_aqc_alternate_write_done *cmd =
5487 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5488 enum i40e_status_code status;
5490 i40e_fill_default_direct_cmd_desc(&desc,
5491 i40e_aqc_opc_alternate_set_mode);
5493 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5495 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5501 * i40e_aq_resume_port_tx
5502 * @hw: pointer to the hardware structure
5503 * @cmd_details: pointer to command details structure or NULL
5505 * Resume port's Tx traffic
5507 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5508 struct i40e_asq_cmd_details *cmd_details)
5510 struct i40e_aq_desc desc;
5511 enum i40e_status_code status;
5513 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5515 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5521 * i40e_set_pci_config_data - store PCI bus info
5522 * @hw: pointer to hardware structure
5523 * @link_status: the link status word from PCI config space
5525 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5527 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5529 hw->bus.type = i40e_bus_type_pci_express;
5531 switch (link_status & I40E_PCI_LINK_WIDTH) {
5532 case I40E_PCI_LINK_WIDTH_1:
5533 hw->bus.width = i40e_bus_width_pcie_x1;
5535 case I40E_PCI_LINK_WIDTH_2:
5536 hw->bus.width = i40e_bus_width_pcie_x2;
5538 case I40E_PCI_LINK_WIDTH_4:
5539 hw->bus.width = i40e_bus_width_pcie_x4;
5541 case I40E_PCI_LINK_WIDTH_8:
5542 hw->bus.width = i40e_bus_width_pcie_x8;
5545 hw->bus.width = i40e_bus_width_unknown;
5549 switch (link_status & I40E_PCI_LINK_SPEED) {
5550 case I40E_PCI_LINK_SPEED_2500:
5551 hw->bus.speed = i40e_bus_speed_2500;
5553 case I40E_PCI_LINK_SPEED_5000:
5554 hw->bus.speed = i40e_bus_speed_5000;
5556 case I40E_PCI_LINK_SPEED_8000:
5557 hw->bus.speed = i40e_bus_speed_8000;
5560 hw->bus.speed = i40e_bus_speed_unknown;
5566 * i40e_aq_debug_dump
5567 * @hw: pointer to the hardware structure
5568 * @cluster_id: specific cluster to dump
5569 * @table_id: table id within cluster
5570 * @start_index: index of line in the block to read
5571 * @buff_size: dump buffer size
5572 * @buff: dump buffer
5573 * @ret_buff_size: actual buffer size returned
5574 * @ret_next_table: next block to read
5575 * @ret_next_index: next index to read
5577 * Dump internal FW/HW data for debug purposes.
5580 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5581 u8 table_id, u32 start_index, u16 buff_size,
5582 void *buff, u16 *ret_buff_size,
5583 u8 *ret_next_table, u32 *ret_next_index,
5584 struct i40e_asq_cmd_details *cmd_details)
5586 struct i40e_aq_desc desc;
5587 struct i40e_aqc_debug_dump_internals *cmd =
5588 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5589 struct i40e_aqc_debug_dump_internals *resp =
5590 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5591 enum i40e_status_code status;
5593 if (buff_size == 0 || !buff)
5594 return I40E_ERR_PARAM;
5596 i40e_fill_default_direct_cmd_desc(&desc,
5597 i40e_aqc_opc_debug_dump_internals);
5598 /* Indirect Command */
5599 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5600 if (buff_size > I40E_AQ_LARGE_BUF)
5601 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5603 cmd->cluster_id = cluster_id;
5604 cmd->table_id = table_id;
5605 cmd->idx = CPU_TO_LE32(start_index);
5607 desc.datalen = CPU_TO_LE16(buff_size);
5609 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5611 if (ret_buff_size != NULL)
5612 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5613 if (ret_next_table != NULL)
5614 *ret_next_table = resp->table_id;
5615 if (ret_next_index != NULL)
5616 *ret_next_index = LE32_TO_CPU(resp->idx);
5623 * i40e_read_bw_from_alt_ram
5624 * @hw: pointer to the hardware structure
5625 * @max_bw: pointer for max_bw read
5626 * @min_bw: pointer for min_bw read
5627 * @min_valid: pointer for bool that is true if min_bw is a valid value
5628 * @max_valid: pointer for bool that is true if max_bw is a valid value
5630 * Read bw from the alternate ram for the given pf
5632 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5633 u32 *max_bw, u32 *min_bw,
5634 bool *min_valid, bool *max_valid)
5636 enum i40e_status_code status;
5637 u32 max_bw_addr, min_bw_addr;
5639 /* Calculate the address of the min/max bw registers */
5640 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5641 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5642 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5643 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5644 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5645 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5647 /* Read the bandwidths from alt ram */
5648 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5649 min_bw_addr, min_bw);
5651 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5656 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5665 * i40e_aq_configure_partition_bw
5666 * @hw: pointer to the hardware structure
5667 * @bw_data: Buffer holding valid pfs and bw limits
5668 * @cmd_details: pointer to command details
5670 * Configure partitions guaranteed/max bw
5672 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5673 struct i40e_aqc_configure_partition_bw_data *bw_data,
5674 struct i40e_asq_cmd_details *cmd_details)
5676 enum i40e_status_code status;
5677 struct i40e_aq_desc desc;
5678 u16 bwd_size = sizeof(*bw_data);
5680 i40e_fill_default_direct_cmd_desc(&desc,
5681 i40e_aqc_opc_configure_partition_bw);
5683 /* Indirect command */
5684 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5685 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5687 if (bwd_size > I40E_AQ_LARGE_BUF)
5688 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5690 desc.datalen = CPU_TO_LE16(bwd_size);
5692 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5696 #endif /* PF_DRIVER */
5700 * i40e_aq_send_msg_to_pf
5701 * @hw: pointer to the hardware structure
5702 * @v_opcode: opcodes for VF-PF communication
5703 * @v_retval: return error code
5704 * @msg: pointer to the msg buffer
5705 * @msglen: msg length
5706 * @cmd_details: pointer to command details
5708 * Send message to PF driver using admin queue. By default, this message
5709 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5710 * completion before returning.
5712 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5713 enum i40e_virtchnl_ops v_opcode,
5714 enum i40e_status_code v_retval,
5715 u8 *msg, u16 msglen,
5716 struct i40e_asq_cmd_details *cmd_details)
5718 struct i40e_aq_desc desc;
5719 struct i40e_asq_cmd_details details;
5720 enum i40e_status_code status;
5722 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5723 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5724 desc.cookie_high = CPU_TO_LE32(v_opcode);
5725 desc.cookie_low = CPU_TO_LE32(v_retval);
5727 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5728 | I40E_AQ_FLAG_RD));
5729 if (msglen > I40E_AQ_LARGE_BUF)
5730 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5731 desc.datalen = CPU_TO_LE16(msglen);
5734 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5735 details.async = true;
5736 cmd_details = &details;
5738 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5739 msglen, cmd_details);
5744 * i40e_vf_parse_hw_config
5745 * @hw: pointer to the hardware structure
5746 * @msg: pointer to the virtual channel VF resource structure
5748 * Given a VF resource message from the PF, populate the hw struct
5749 * with appropriate information.
5751 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5752 struct i40e_virtchnl_vf_resource *msg)
5754 struct i40e_virtchnl_vsi_resource *vsi_res;
5757 vsi_res = &msg->vsi_res[0];
5759 hw->dev_caps.num_vsis = msg->num_vsis;
5760 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5761 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5762 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5763 hw->dev_caps.dcb = msg->vf_offload_flags &
5764 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5765 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5766 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5767 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5768 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5769 for (i = 0; i < msg->num_vsis; i++) {
5770 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5771 i40e_memcpy(hw->mac.perm_addr,
5772 vsi_res->default_mac_addr,
5773 I40E_ETH_LENGTH_OF_ADDRESS,
5774 I40E_NONDMA_TO_NONDMA);
5775 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5776 I40E_ETH_LENGTH_OF_ADDRESS,
5777 I40E_NONDMA_TO_NONDMA);
5785 * @hw: pointer to the hardware structure
5787 * Send a VF_RESET message to the PF. Does not wait for response from PF
5788 * as none will be forthcoming. Immediately after calling this function,
5789 * the admin queue should be shut down and (optionally) reinitialized.
5791 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5793 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5794 I40E_SUCCESS, NULL, 0, NULL);
5796 #endif /* VF_DRIVER */
5800 * i40e_aq_set_arp_proxy_config
5801 * @hw: pointer to the HW structure
5802 * @proxy_config - pointer to proxy config command table struct
5803 * @cmd_details: pointer to command details
5805 * Set ARP offload parameters from pre-populated
5806 * i40e_aqc_arp_proxy_data struct
5808 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
5809 struct i40e_aqc_arp_proxy_data *proxy_config,
5810 struct i40e_asq_cmd_details *cmd_details)
5812 struct i40e_aq_desc desc;
5813 struct i40e_aqc_set_proxy_config *cmd =
5814 (struct i40e_aqc_set_proxy_config *) &desc.params.raw;
5815 enum i40e_status_code status;
5818 return I40E_ERR_PARAM;
5820 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
5822 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
5823 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
5825 status = i40e_asq_send_command(hw, &desc, proxy_config,
5826 sizeof(struct i40e_aqc_arp_proxy_data),
5833 * i40e_aq_opc_set_ns_proxy_table_entry
5834 * @hw: pointer to the HW structure
5835 * @ns_proxy_table_entry: pointer to NS table entry command struct
5836 * @cmd_details: pointer to command details
5838 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
5839 * from pre-populated i40e_aqc_ns_proxy_data struct
5841 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
5842 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
5843 struct i40e_asq_cmd_details *cmd_details)
5845 struct i40e_aq_desc desc;
5846 struct i40e_aqc_set_ns_proxy_table_entry *cmd =
5847 (struct i40e_aqc_set_ns_proxy_table_entry *) &desc.params.raw;
5848 enum i40e_status_code status;
5850 if (!ns_proxy_table_entry)
5851 return I40E_ERR_PARAM;
5853 i40e_fill_default_direct_cmd_desc(&desc,
5854 i40e_aqc_opc_set_ns_proxy_table_entry);
5857 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
5859 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
5861 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
5862 sizeof(struct i40e_aqc_ns_proxy_data),
5869 * i40e_aq_set_clear_wol_filter
5870 * @hw: pointer to the hw struct
5871 * @filter_index: index of filter to modify (0-7)
5872 * @filter: buffer containing filter to be set
5873 * @set_filter: true to set filter, false to clear filter
5874 * @no_wol_tco: if true, pass through packets cannot cause wake-up
5875 * if false, pass through packets may cause wake-up
5876 * @filter_valid: true if filter action is valid
5877 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
5878 * @cmd_details: pointer to command details structure or NULL
5880 * Set or clear WoL filter for port attached to the PF
5882 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
5884 struct i40e_aqc_set_wol_filter_data *filter,
5885 bool set_filter, bool no_wol_tco,
5886 bool filter_valid, bool no_wol_tco_valid,
5887 struct i40e_asq_cmd_details *cmd_details)
5889 struct i40e_aq_desc desc;
5890 struct i40e_aqc_set_wol_filter *cmd =
5891 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
5892 enum i40e_status_code status;
5894 u16 valid_flags = 0;
5897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
5899 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
5900 return I40E_ERR_PARAM;
5901 cmd->filter_index = CPU_TO_LE16(filter_index);
5905 return I40E_ERR_PARAM;
5906 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
5907 buff_len = sizeof(*filter);
5910 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
5911 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
5914 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
5915 if (no_wol_tco_valid)
5916 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
5917 cmd->valid_flags = CPU_TO_LE16(valid_flags);
5919 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
5920 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
5922 status = i40e_asq_send_command(hw, &desc, filter,
5923 buff_len, cmd_details);
5929 * i40e_aq_get_wake_event_reason
5930 * @hw: pointer to the hw struct
5931 * @wake_reason: return value, index of matching filter
5932 * @cmd_details: pointer to command details structure or NULL
5934 * Get information for the reason of a Wake Up event
5936 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
5938 struct i40e_asq_cmd_details *cmd_details)
5940 struct i40e_aq_desc desc;
5941 struct i40e_aqc_get_wake_reason_completion *resp =
5942 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
5943 enum i40e_status_code status;
5945 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
5947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5949 if (status == I40E_SUCCESS)
5950 *wake_reason = LE16_TO_CPU(resp->wake_reason);
5955 #endif /* X722_SUPPORT */