drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_A:
  62                 case I40E_DEV_ID_KX_B:
  63                 case I40E_DEV_ID_KX_C:
  64                 case I40E_DEV_ID_QSFP_A:
  65                 case I40E_DEV_ID_QSFP_B:
  66                 case I40E_DEV_ID_QSFP_C:
  67                 case I40E_DEV_ID_10G_BASE_T:
  68                 case I40E_DEV_ID_10G_BASE_T4:
  69                 case I40E_DEV_ID_20G_KR2:
  70                 case I40E_DEV_ID_20G_KR2_A:
  71                         hw->mac.type = I40E_MAC_XL710;
  72                         break;
  73                 case I40E_DEV_ID_VF:
  74                 case I40E_DEV_ID_VF_HV:
  75                         hw->mac.type = I40E_MAC_VF;
  76                         break;
  77                 default:
  78                         hw->mac.type = I40E_MAC_GENERIC;
  79                         break;
  80                 }
  81         } else {
  82                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  83         }
  84
  85         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  86                   hw->mac.type, status);
  87         return status;
  88 }
  89
  90 #ifndef I40E_NDIS_SUPPORT
  91 /**
  92  * i40e_aq_str - convert AQ err code to a string
  93  * @hw: pointer to the HW structure
  94  * @aq_err: the AQ error code to convert
  95  **/
  96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  97 {
  98         switch (aq_err) {
  99         case I40E_AQ_RC_OK:
 100                 return "OK";
 101         case I40E_AQ_RC_EPERM:
 102                 return "I40E_AQ_RC_EPERM";
 103         case I40E_AQ_RC_ENOENT:
 104                 return "I40E_AQ_RC_ENOENT";
 105         case I40E_AQ_RC_ESRCH:
 106                 return "I40E_AQ_RC_ESRCH";
 107         case I40E_AQ_RC_EINTR:
 108                 return "I40E_AQ_RC_EINTR";
 109         case I40E_AQ_RC_EIO:
 110                 return "I40E_AQ_RC_EIO";
 111         case I40E_AQ_RC_ENXIO:
 112                 return "I40E_AQ_RC_ENXIO";
 113         case I40E_AQ_RC_E2BIG:
 114                 return "I40E_AQ_RC_E2BIG";
 115         case I40E_AQ_RC_EAGAIN:
 116                 return "I40E_AQ_RC_EAGAIN";
 117         case I40E_AQ_RC_ENOMEM:
 118                 return "I40E_AQ_RC_ENOMEM";
 119         case I40E_AQ_RC_EACCES:
 120                 return "I40E_AQ_RC_EACCES";
 121         case I40E_AQ_RC_EFAULT:
 122                 return "I40E_AQ_RC_EFAULT";
 123         case I40E_AQ_RC_EBUSY:
 124                 return "I40E_AQ_RC_EBUSY";
 125         case I40E_AQ_RC_EEXIST:
 126                 return "I40E_AQ_RC_EEXIST";
 127         case I40E_AQ_RC_EINVAL:
 128                 return "I40E_AQ_RC_EINVAL";
 129         case I40E_AQ_RC_ENOTTY:
 130                 return "I40E_AQ_RC_ENOTTY";
 131         case I40E_AQ_RC_ENOSPC:
 132                 return "I40E_AQ_RC_ENOSPC";
 133         case I40E_AQ_RC_ENOSYS:
 134                 return "I40E_AQ_RC_ENOSYS";
 135         case I40E_AQ_RC_ERANGE:
 136                 return "I40E_AQ_RC_ERANGE";
 137         case I40E_AQ_RC_EFLUSHED:
 138                 return "I40E_AQ_RC_EFLUSHED";
 139         case I40E_AQ_RC_BAD_ADDR:
 140                 return "I40E_AQ_RC_BAD_ADDR";
 141         case I40E_AQ_RC_EMODE:
 142                 return "I40E_AQ_RC_EMODE";
 143         case I40E_AQ_RC_EFBIG:
 144                 return "I40E_AQ_RC_EFBIG";
 145         }
 146
 147         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 148         return hw->err_str;
 149 }
 150
 151 /**
 152  * i40e_stat_str - convert status err code to a string
 153  * @hw: pointer to the HW structure
 154  * @stat_err: the status error code to convert
 155  **/
 156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 157 {
 158         switch (stat_err) {
 159         case I40E_SUCCESS:
 160                 return "OK";
 161         case I40E_ERR_NVM:
 162                 return "I40E_ERR_NVM";
 163         case I40E_ERR_NVM_CHECKSUM:
 164                 return "I40E_ERR_NVM_CHECKSUM";
 165         case I40E_ERR_PHY:
 166                 return "I40E_ERR_PHY";
 167         case I40E_ERR_CONFIG:
 168                 return "I40E_ERR_CONFIG";
 169         case I40E_ERR_PARAM:
 170                 return "I40E_ERR_PARAM";
 171         case I40E_ERR_MAC_TYPE:
 172                 return "I40E_ERR_MAC_TYPE";
 173         case I40E_ERR_UNKNOWN_PHY:
 174                 return "I40E_ERR_UNKNOWN_PHY";
 175         case I40E_ERR_LINK_SETUP:
 176                 return "I40E_ERR_LINK_SETUP";
 177         case I40E_ERR_ADAPTER_STOPPED:
 178                 return "I40E_ERR_ADAPTER_STOPPED";
 179         case I40E_ERR_INVALID_MAC_ADDR:
 180                 return "I40E_ERR_INVALID_MAC_ADDR";
 181         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 182                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 183         case I40E_ERR_MASTER_REQUESTS_PENDING:
 184                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 185         case I40E_ERR_INVALID_LINK_SETTINGS:
 186                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 187         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 188                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 189         case I40E_ERR_RESET_FAILED:
 190                 return "I40E_ERR_RESET_FAILED";
 191         case I40E_ERR_SWFW_SYNC:
 192                 return "I40E_ERR_SWFW_SYNC";
 193         case I40E_ERR_NO_AVAILABLE_VSI:
 194                 return "I40E_ERR_NO_AVAILABLE_VSI";
 195         case I40E_ERR_NO_MEMORY:
 196                 return "I40E_ERR_NO_MEMORY";
 197         case I40E_ERR_BAD_PTR:
 198                 return "I40E_ERR_BAD_PTR";
 199         case I40E_ERR_RING_FULL:
 200                 return "I40E_ERR_RING_FULL";
 201         case I40E_ERR_INVALID_PD_ID:
 202                 return "I40E_ERR_INVALID_PD_ID";
 203         case I40E_ERR_INVALID_QP_ID:
 204                 return "I40E_ERR_INVALID_QP_ID";
 205         case I40E_ERR_INVALID_CQ_ID:
 206                 return "I40E_ERR_INVALID_CQ_ID";
 207         case I40E_ERR_INVALID_CEQ_ID:
 208                 return "I40E_ERR_INVALID_CEQ_ID";
 209         case I40E_ERR_INVALID_AEQ_ID:
 210                 return "I40E_ERR_INVALID_AEQ_ID";
 211         case I40E_ERR_INVALID_SIZE:
 212                 return "I40E_ERR_INVALID_SIZE";
 213         case I40E_ERR_INVALID_ARP_INDEX:
 214                 return "I40E_ERR_INVALID_ARP_INDEX";
 215         case I40E_ERR_INVALID_FPM_FUNC_ID:
 216                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 217         case I40E_ERR_QP_INVALID_MSG_SIZE:
 218                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 219         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 220                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 221         case I40E_ERR_INVALID_FRAG_COUNT:
 222                 return "I40E_ERR_INVALID_FRAG_COUNT";
 223         case I40E_ERR_QUEUE_EMPTY:
 224                 return "I40E_ERR_QUEUE_EMPTY";
 225         case I40E_ERR_INVALID_ALIGNMENT:
 226                 return "I40E_ERR_INVALID_ALIGNMENT";
 227         case I40E_ERR_FLUSHED_QUEUE:
 228                 return "I40E_ERR_FLUSHED_QUEUE";
 229         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 230                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 231         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 232                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 233         case I40E_ERR_TIMEOUT:
 234                 return "I40E_ERR_TIMEOUT";
 235         case I40E_ERR_OPCODE_MISMATCH:
 236                 return "I40E_ERR_OPCODE_MISMATCH";
 237         case I40E_ERR_CQP_COMPL_ERROR:
 238                 return "I40E_ERR_CQP_COMPL_ERROR";
 239         case I40E_ERR_INVALID_VF_ID:
 240                 return "I40E_ERR_INVALID_VF_ID";
 241         case I40E_ERR_INVALID_HMCFN_ID:
 242                 return "I40E_ERR_INVALID_HMCFN_ID";
 243         case I40E_ERR_BACKING_PAGE_ERROR:
 244                 return "I40E_ERR_BACKING_PAGE_ERROR";
 245         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 246                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 247         case I40E_ERR_INVALID_PBLE_INDEX:
 248                 return "I40E_ERR_INVALID_PBLE_INDEX";
 249         case I40E_ERR_INVALID_SD_INDEX:
 250                 return "I40E_ERR_INVALID_SD_INDEX";
 251         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 252                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 253         case I40E_ERR_INVALID_SD_TYPE:
 254                 return "I40E_ERR_INVALID_SD_TYPE";
 255         case I40E_ERR_MEMCPY_FAILED:
 256                 return "I40E_ERR_MEMCPY_FAILED";
 257         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 258                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 259         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 260                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 261         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 262                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 263         case I40E_ERR_SRQ_ENABLED:
 264                 return "I40E_ERR_SRQ_ENABLED";
 265         case I40E_ERR_ADMIN_QUEUE_ERROR:
 266                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 267         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 268                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 269         case I40E_ERR_BUF_TOO_SHORT:
 270                 return "I40E_ERR_BUF_TOO_SHORT";
 271         case I40E_ERR_ADMIN_QUEUE_FULL:
 272                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 273         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 274                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 275         case I40E_ERR_BAD_IWARP_CQE:
 276                 return "I40E_ERR_BAD_IWARP_CQE";
 277         case I40E_ERR_NVM_BLANK_MODE:
 278                 return "I40E_ERR_NVM_BLANK_MODE";
 279         case I40E_ERR_NOT_IMPLEMENTED:
 280                 return "I40E_ERR_NOT_IMPLEMENTED";
 281         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 282                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 283         case I40E_ERR_DIAG_TEST_FAILED:
 284                 return "I40E_ERR_DIAG_TEST_FAILED";
 285         case I40E_ERR_NOT_READY:
 286                 return "I40E_ERR_NOT_READY";
 287         case I40E_NOT_SUPPORTED:
 288                 return "I40E_NOT_SUPPORTED";
 289         case I40E_ERR_FIRMWARE_API_VERSION:
 290                 return "I40E_ERR_FIRMWARE_API_VERSION";
 291         }
 292
 293         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 294         return hw->err_str;
 295 }
 296
 297 #endif /* I40E_NDIS_SUPPORT */
 298 /**
 299  * i40e_debug_aq
 300  * @hw: debug mask related to admin queue
 301  * @mask: debug mask
 302  * @desc: pointer to admin queue descriptor
 303  * @buffer: pointer to command buffer
 304  * @buf_len: max length of buffer
 305  *
 306  * Dumps debug log about adminq command with descriptor contents.
 307  **/
 308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 309                    void *buffer, u16 buf_len)
 310 {
 311         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 312         u16 len = LE16_TO_CPU(aq_desc->datalen);
 313         u8 *buf = (u8 *)buffer;
 314         u16 i = 0;
 315
 316         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 317                 return;
 318
 319         i40e_debug(hw, mask,
 320                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 321                    LE16_TO_CPU(aq_desc->opcode),
 322                    LE16_TO_CPU(aq_desc->flags),
 323                    LE16_TO_CPU(aq_desc->datalen),
 324                    LE16_TO_CPU(aq_desc->retval));
 325         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 326                    LE32_TO_CPU(aq_desc->cookie_high),
 327                    LE32_TO_CPU(aq_desc->cookie_low));
 328         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 329                    LE32_TO_CPU(aq_desc->params.internal.param0),
 330                    LE32_TO_CPU(aq_desc->params.internal.param1));
 331         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 333                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 334
 335         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 336                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 337                 if (buf_len < len)
 338                         len = buf_len;
 339                 /* write the full 16-byte chunks */
 340                 for (i = 0; i < (len - 16); i += 16)
 341                         i40e_debug(hw, mask,
 342                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 343                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 344                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 345                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 346                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 347                 /* the most we could have left is 16 bytes, pad with zeros */
 348                 if (i < len) {
 349                         char d_buf[16];
 350                         int j;
 351
 352                         memset(d_buf, 0, sizeof(d_buf));
 353                         for (j = 0; i < len; j++, i++)
 354                                 d_buf[j] = buf[i];
 355                         i40e_debug(hw, mask,
 356                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 357                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 358                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 359                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 360                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 361                 }
 362         }
 363 }
 364
 365 /**
 366  * i40e_check_asq_alive
 367  * @hw: pointer to the hw struct
 368  *
 369  * Returns true if Queue is enabled else false.
 370  **/
 371 bool i40e_check_asq_alive(struct i40e_hw *hw)
 372 {
 373         if (hw->aq.asq.len)
 374 #ifdef PF_DRIVER
 375 #ifdef INTEGRATED_VF
 376                 if (!i40e_is_vf(hw))
 377                         return !!(rd32(hw, hw->aq.asq.len) &
 378                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 379 #else
 380                 return !!(rd32(hw, hw->aq.asq.len) &
 381                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 382 #endif /* INTEGRATED_VF */
 383 #endif /* PF_DRIVER */
 384 #ifdef VF_DRIVER
 385 #ifdef INTEGRATED_VF
 386                 if (i40e_is_vf(hw))
 387                         return !!(rd32(hw, hw->aq.asq.len) &
 388                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 389 #else
 390                 return !!(rd32(hw, hw->aq.asq.len) &
 391                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 392 #endif /* INTEGRATED_VF */
 393 #endif /* VF_DRIVER */
 394         return false;
 395 }
 396
 397 /**
 398  * i40e_aq_queue_shutdown
 399  * @hw: pointer to the hw struct
 400  * @unloading: is the driver unloading itself
 401  *
 402  * Tell the Firmware that we're shutting down the AdminQ and whether
 403  * or not the driver is unloading as well.
 404  **/
 405 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 406                                              bool unloading)
 407 {
 408         struct i40e_aq_desc desc;
 409         struct i40e_aqc_queue_shutdown *cmd =
 410                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 411         enum i40e_status_code status;
 412
 413         i40e_fill_default_direct_cmd_desc(&desc,
 414                                           i40e_aqc_opc_queue_shutdown);
 415
 416         if (unloading)
 417                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 418         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 419
 420         return status;
 421 }
 422
 423 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 424  * hardware to a bit-field that can be used by SW to more easily determine the
 425  * packet type.
 426  *
 427  * Macros are used to shorten the table lines and make this table human
 428  * readable.
 429  *
 430  * We store the PTYPE in the top byte of the bit field - this is just so that
 431  * we can check that the table doesn't have a row missing, as the index into
 432  * the table should be the PTYPE.
 433  *
 434  * Typical work flow:
 435  *
 436  * IF NOT i40e_ptype_lookup[ptype].known
 437  * THEN
 438  *      Packet is unknown
 439  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 440  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 441  * ELSE
 442  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 443  * ENDIF
 444  */
 445
 446 /* macro to make the table lines short */
 447 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 448         {       PTYPE, \
 449                 1, \
 450                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 451                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 452                 I40E_RX_PTYPE_##OUTER_FRAG, \
 453                 I40E_RX_PTYPE_TUNNEL_##T, \
 454                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 455                 I40E_RX_PTYPE_##TEF, \
 456                 I40E_RX_PTYPE_INNER_PROT_##I, \
 457                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 458
 459 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 460                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 461
 462 /* shorter macros makes the table fit but are terse */
 463 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 464 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 465 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 466
 467 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 468 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 469         /* L2 Packet types */
 470         I40E_PTT_UNUSED_ENTRY(0),
 471         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 472         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 473         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 474         I40E_PTT_UNUSED_ENTRY(4),
 475         I40E_PTT_UNUSED_ENTRY(5),
 476         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 477         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 478         I40E_PTT_UNUSED_ENTRY(8),
 479         I40E_PTT_UNUSED_ENTRY(9),
 480         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 481         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 482         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 483         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 484         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 485         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 486         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 487         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 488         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 489         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 490         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 491         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 492
 493         /* Non Tunneled IPv4 */
 494         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 495         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 496         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 497         I40E_PTT_UNUSED_ENTRY(25),
 498         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 499         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 500         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 501
 502         /* IPv4 --> IPv4 */
 503         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 504         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 505         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 506         I40E_PTT_UNUSED_ENTRY(32),
 507         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 508         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 509         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 510
 511         /* IPv4 --> IPv6 */
 512         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 513         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 514         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 515         I40E_PTT_UNUSED_ENTRY(39),
 516         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 517         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 518         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 519
 520         /* IPv4 --> GRE/NAT */
 521         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 522
 523         /* IPv4 --> GRE/NAT --> IPv4 */
 524         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 525         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 526         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 527         I40E_PTT_UNUSED_ENTRY(47),
 528         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 529         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 530         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 531
 532         /* IPv4 --> GRE/NAT --> IPv6 */
 533         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 534         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 535         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 536         I40E_PTT_UNUSED_ENTRY(54),
 537         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 538         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 539         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 540
 541         /* IPv4 --> GRE/NAT --> MAC */
 542         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 543
 544         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 545         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 546         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 547         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 548         I40E_PTT_UNUSED_ENTRY(62),
 549         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 550         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 551         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 552
 553         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 554         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 555         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 556         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 557         I40E_PTT_UNUSED_ENTRY(69),
 558         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 559         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 560         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 561
 562         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 563         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 564
 565         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 566         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 567         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 568         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 569         I40E_PTT_UNUSED_ENTRY(77),
 570         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 571         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 572         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 573
 574         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 575         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 576         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 577         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 578         I40E_PTT_UNUSED_ENTRY(84),
 579         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 580         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 581         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 582
 583         /* Non Tunneled IPv6 */
 584         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 585         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 586         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 587         I40E_PTT_UNUSED_ENTRY(91),
 588         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 589         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 590         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 591
 592         /* IPv6 --> IPv4 */
 593         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 594         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 595         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 596         I40E_PTT_UNUSED_ENTRY(98),
 597         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 598         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 599         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 600
 601         /* IPv6 --> IPv6 */
 602         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 603         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 604         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 605         I40E_PTT_UNUSED_ENTRY(105),
 606         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 607         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 608         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 609
 610         /* IPv6 --> GRE/NAT */
 611         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 612
 613         /* IPv6 --> GRE/NAT -> IPv4 */
 614         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 615         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 616         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 617         I40E_PTT_UNUSED_ENTRY(113),
 618         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 619         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 620         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 621
 622         /* IPv6 --> GRE/NAT -> IPv6 */
 623         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 624         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 625         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 626         I40E_PTT_UNUSED_ENTRY(120),
 627         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 628         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 629         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 630
 631         /* IPv6 --> GRE/NAT -> MAC */
 632         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 633
 634         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 635         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 636         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 637         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 638         I40E_PTT_UNUSED_ENTRY(128),
 639         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 640         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 641         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 642
 643         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 644         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 645         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 646         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 647         I40E_PTT_UNUSED_ENTRY(135),
 648         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 649         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 650         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 651
 652         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 653         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 654
 655         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 656         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 657         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 658         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 659         I40E_PTT_UNUSED_ENTRY(143),
 660         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 661         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 662         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 663
 664         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 665         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 666         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 667         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 668         I40E_PTT_UNUSED_ENTRY(150),
 669         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 670         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 671         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 672
 673         /* unused entries */
 674         I40E_PTT_UNUSED_ENTRY(154),
 675         I40E_PTT_UNUSED_ENTRY(155),
 676         I40E_PTT_UNUSED_ENTRY(156),
 677         I40E_PTT_UNUSED_ENTRY(157),
 678         I40E_PTT_UNUSED_ENTRY(158),
 679         I40E_PTT_UNUSED_ENTRY(159),
 680
 681         I40E_PTT_UNUSED_ENTRY(160),
 682         I40E_PTT_UNUSED_ENTRY(161),
 683         I40E_PTT_UNUSED_ENTRY(162),
 684         I40E_PTT_UNUSED_ENTRY(163),
 685         I40E_PTT_UNUSED_ENTRY(164),
 686         I40E_PTT_UNUSED_ENTRY(165),
 687         I40E_PTT_UNUSED_ENTRY(166),
 688         I40E_PTT_UNUSED_ENTRY(167),
 689         I40E_PTT_UNUSED_ENTRY(168),
 690         I40E_PTT_UNUSED_ENTRY(169),
 691
 692         I40E_PTT_UNUSED_ENTRY(170),
 693         I40E_PTT_UNUSED_ENTRY(171),
 694         I40E_PTT_UNUSED_ENTRY(172),
 695         I40E_PTT_UNUSED_ENTRY(173),
 696         I40E_PTT_UNUSED_ENTRY(174),
 697         I40E_PTT_UNUSED_ENTRY(175),
 698         I40E_PTT_UNUSED_ENTRY(176),
 699         I40E_PTT_UNUSED_ENTRY(177),
 700         I40E_PTT_UNUSED_ENTRY(178),
 701         I40E_PTT_UNUSED_ENTRY(179),
 702
 703         I40E_PTT_UNUSED_ENTRY(180),
 704         I40E_PTT_UNUSED_ENTRY(181),
 705         I40E_PTT_UNUSED_ENTRY(182),
 706         I40E_PTT_UNUSED_ENTRY(183),
 707         I40E_PTT_UNUSED_ENTRY(184),
 708         I40E_PTT_UNUSED_ENTRY(185),
 709         I40E_PTT_UNUSED_ENTRY(186),
 710         I40E_PTT_UNUSED_ENTRY(187),
 711         I40E_PTT_UNUSED_ENTRY(188),
 712         I40E_PTT_UNUSED_ENTRY(189),
 713
 714         I40E_PTT_UNUSED_ENTRY(190),
 715         I40E_PTT_UNUSED_ENTRY(191),
 716         I40E_PTT_UNUSED_ENTRY(192),
 717         I40E_PTT_UNUSED_ENTRY(193),
 718         I40E_PTT_UNUSED_ENTRY(194),
 719         I40E_PTT_UNUSED_ENTRY(195),
 720         I40E_PTT_UNUSED_ENTRY(196),
 721         I40E_PTT_UNUSED_ENTRY(197),
 722         I40E_PTT_UNUSED_ENTRY(198),
 723         I40E_PTT_UNUSED_ENTRY(199),
 724
 725         I40E_PTT_UNUSED_ENTRY(200),
 726         I40E_PTT_UNUSED_ENTRY(201),
 727         I40E_PTT_UNUSED_ENTRY(202),
 728         I40E_PTT_UNUSED_ENTRY(203),
 729         I40E_PTT_UNUSED_ENTRY(204),
 730         I40E_PTT_UNUSED_ENTRY(205),
 731         I40E_PTT_UNUSED_ENTRY(206),
 732         I40E_PTT_UNUSED_ENTRY(207),
 733         I40E_PTT_UNUSED_ENTRY(208),
 734         I40E_PTT_UNUSED_ENTRY(209),
 735
 736         I40E_PTT_UNUSED_ENTRY(210),
 737         I40E_PTT_UNUSED_ENTRY(211),
 738         I40E_PTT_UNUSED_ENTRY(212),
 739         I40E_PTT_UNUSED_ENTRY(213),
 740         I40E_PTT_UNUSED_ENTRY(214),
 741         I40E_PTT_UNUSED_ENTRY(215),
 742         I40E_PTT_UNUSED_ENTRY(216),
 743         I40E_PTT_UNUSED_ENTRY(217),
 744         I40E_PTT_UNUSED_ENTRY(218),
 745         I40E_PTT_UNUSED_ENTRY(219),
 746
 747         I40E_PTT_UNUSED_ENTRY(220),
 748         I40E_PTT_UNUSED_ENTRY(221),
 749         I40E_PTT_UNUSED_ENTRY(222),
 750         I40E_PTT_UNUSED_ENTRY(223),
 751         I40E_PTT_UNUSED_ENTRY(224),
 752         I40E_PTT_UNUSED_ENTRY(225),
 753         I40E_PTT_UNUSED_ENTRY(226),
 754         I40E_PTT_UNUSED_ENTRY(227),
 755         I40E_PTT_UNUSED_ENTRY(228),
 756         I40E_PTT_UNUSED_ENTRY(229),
 757
 758         I40E_PTT_UNUSED_ENTRY(230),
 759         I40E_PTT_UNUSED_ENTRY(231),
 760         I40E_PTT_UNUSED_ENTRY(232),
 761         I40E_PTT_UNUSED_ENTRY(233),
 762         I40E_PTT_UNUSED_ENTRY(234),
 763         I40E_PTT_UNUSED_ENTRY(235),
 764         I40E_PTT_UNUSED_ENTRY(236),
 765         I40E_PTT_UNUSED_ENTRY(237),
 766         I40E_PTT_UNUSED_ENTRY(238),
 767         I40E_PTT_UNUSED_ENTRY(239),
 768
 769         I40E_PTT_UNUSED_ENTRY(240),
 770         I40E_PTT_UNUSED_ENTRY(241),
 771         I40E_PTT_UNUSED_ENTRY(242),
 772         I40E_PTT_UNUSED_ENTRY(243),
 773         I40E_PTT_UNUSED_ENTRY(244),
 774         I40E_PTT_UNUSED_ENTRY(245),
 775         I40E_PTT_UNUSED_ENTRY(246),
 776         I40E_PTT_UNUSED_ENTRY(247),
 777         I40E_PTT_UNUSED_ENTRY(248),
 778         I40E_PTT_UNUSED_ENTRY(249),
 779
 780         I40E_PTT_UNUSED_ENTRY(250),
 781         I40E_PTT_UNUSED_ENTRY(251),
 782         I40E_PTT_UNUSED_ENTRY(252),
 783         I40E_PTT_UNUSED_ENTRY(253),
 784         I40E_PTT_UNUSED_ENTRY(254),
 785         I40E_PTT_UNUSED_ENTRY(255)
 786 };
 787
 788
 789 /**
 790  * i40e_validate_mac_addr - Validate unicast MAC address
 791  * @mac_addr: pointer to MAC address
 792  *
 793  * Tests a MAC address to ensure it is a valid Individual Address
 794  **/
 795 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 796 {
 797         enum i40e_status_code status = I40E_SUCCESS;
 798
 799         DEBUGFUNC("i40e_validate_mac_addr");
 800
 801         /* Broadcast addresses ARE multicast addresses
 802          * Make sure it is not a multicast address
 803          * Reject the zero address
 804          */
 805         if (I40E_IS_MULTICAST(mac_addr) ||
 806             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 807               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 808                 status = I40E_ERR_INVALID_MAC_ADDR;
 809
 810         return status;
 811 }
 812 #ifdef PF_DRIVER
 813
 814 /**
 815  * i40e_init_shared_code - Initialize the shared code
 816  * @hw: pointer to hardware structure
 817  *
 818  * This assigns the MAC type and PHY code and inits the NVM.
 819  * Does not touch the hardware. This function must be called prior to any
 820  * other function in the shared code. The i40e_hw structure should be
 821  * memset to 0 prior to calling this function.  The following fields in
 822  * hw structure should be filled in prior to calling this function:
 823  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 824  * subsystem_vendor_id, and revision_id
 825  **/
 826 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 827 {
 828         enum i40e_status_code status = I40E_SUCCESS;
 829         u32 port, ari, func_rid;
 830
 831         DEBUGFUNC("i40e_init_shared_code");
 832
 833         i40e_set_mac_type(hw);
 834
 835         switch (hw->mac.type) {
 836         case I40E_MAC_XL710:
 837                 break;
 838         default:
 839                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 840         }
 841
 842         hw->phy.get_link_info = true;
 843
 844         /* Determine port number and PF number*/
 845         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 846                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 847         hw->port = (u8)port;
 848         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 849                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 850         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 851         if (ari)
 852                 hw->pf_id = (u8)(func_rid & 0xff);
 853         else
 854                 hw->pf_id = (u8)(func_rid & 0x7);
 855
 856         status = i40e_init_nvm(hw);
 857         return status;
 858 }
 859
 860 /**
 861  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 862  * @hw: pointer to the hw struct
 863  * @flags: a return indicator of what addresses were added to the addr store
 864  * @addrs: the requestor's mac addr store
 865  * @cmd_details: pointer to command details structure or NULL
 866  **/
 867 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
 868                                    u16 *flags,
 869                                    struct i40e_aqc_mac_address_read_data *addrs,
 870                                    struct i40e_asq_cmd_details *cmd_details)
 871 {
 872         struct i40e_aq_desc desc;
 873         struct i40e_aqc_mac_address_read *cmd_data =
 874                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 875         enum i40e_status_code status;
 876
 877         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 878         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
 879
 880         status = i40e_asq_send_command(hw, &desc, addrs,
 881                                        sizeof(*addrs), cmd_details);
 882         *flags = LE16_TO_CPU(cmd_data->command_flags);
 883
 884         return status;
 885 }
 886
 887 /**
 888  * i40e_aq_mac_address_write - Change the MAC addresses
 889  * @hw: pointer to the hw struct
 890  * @flags: indicates which MAC to be written
 891  * @mac_addr: address to write
 892  * @cmd_details: pointer to command details structure or NULL
 893  **/
 894 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
 895                                     u16 flags, u8 *mac_addr,
 896                                     struct i40e_asq_cmd_details *cmd_details)
 897 {
 898         struct i40e_aq_desc desc;
 899         struct i40e_aqc_mac_address_write *cmd_data =
 900                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 901         enum i40e_status_code status;
 902
 903         i40e_fill_default_direct_cmd_desc(&desc,
 904                                           i40e_aqc_opc_mac_address_write);
 905         cmd_data->command_flags = CPU_TO_LE16(flags);
 906         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
 907         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
 908                                         ((u32)mac_addr[3] << 16) |
 909                                         ((u32)mac_addr[4] << 8) |
 910                                         mac_addr[5]);
 911
 912         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 913
 914         return status;
 915 }
 916
 917 /**
 918  * i40e_get_mac_addr - get MAC address
 919  * @hw: pointer to the HW structure
 920  * @mac_addr: pointer to MAC address
 921  *
 922  * Reads the adapter's MAC address from register
 923  **/
 924 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
 925 {
 926         struct i40e_aqc_mac_address_read_data addrs;
 927         enum i40e_status_code status;
 928         u16 flags = 0;
 929
 930         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
 931
 932         if (flags & I40E_AQC_LAN_ADDR_VALID)
 933                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
 934
 935         return status;
 936 }
 937
 938 /**
 939  * i40e_get_port_mac_addr - get Port MAC address
 940  * @hw: pointer to the HW structure
 941  * @mac_addr: pointer to Port MAC address
 942  *
 943  * Reads the adapter's Port MAC address
 944  **/
 945 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
 946 {
 947         struct i40e_aqc_mac_address_read_data addrs;
 948         enum i40e_status_code status;
 949         u16 flags = 0;
 950
 951         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
 952         if (status)
 953                 return status;
 954
 955         if (flags & I40E_AQC_PORT_ADDR_VALID)
 956                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
 957         else
 958                 status = I40E_ERR_INVALID_MAC_ADDR;
 959
 960         return status;
 961 }
 962
 963 /**
 964  * i40e_pre_tx_queue_cfg - pre tx queue configure
 965  * @hw: pointer to the HW structure
 966  * @queue: target pf queue index
 967  * @enable: state change request
 968  *
 969  * Handles hw requirement to indicate intention to enable
 970  * or disable target queue.
 971  **/
 972 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
 973 {
 974         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
 975         u32 reg_block = 0;
 976         u32 reg_val;
 977
 978         if (abs_queue_idx >= 128) {
 979                 reg_block = abs_queue_idx / 128;
 980                 abs_queue_idx %= 128;
 981         }
 982
 983         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
 984         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
 985         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
 986
 987         if (enable)
 988                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
 989         else
 990                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
 991
 992         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
 993 }
 994
 995 /**
 996  *  i40e_read_pba_string - Reads part number string from EEPROM
 997  *  @hw: pointer to hardware structure
 998  *  @pba_num: stores the part number string from the EEPROM
 999  *  @pba_num_size: part number string buffer length
1000  *
1001  *  Reads the part number string from the EEPROM.
1002  **/
1003 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1004                                             u32 pba_num_size)
1005 {
1006         enum i40e_status_code status = I40E_SUCCESS;
1007         u16 pba_word = 0;
1008         u16 pba_size = 0;
1009         u16 pba_ptr = 0;
1010         u16 i = 0;
1011
1012         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1013         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1014                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1015                 return status;
1016         }
1017
1018         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1019         if (status != I40E_SUCCESS) {
1020                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1021                 return status;
1022         }
1023
1024         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1025         if (status != I40E_SUCCESS) {
1026                 DEBUGOUT("Failed to read PBA Block size.\n");
1027                 return status;
1028         }
1029
1030         /* Subtract one to get PBA word count (PBA Size word is included in
1031          * total size)
1032          */
1033         pba_size--;
1034         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1035                 DEBUGOUT("Buffer to small for PBA data.\n");
1036                 return I40E_ERR_PARAM;
1037         }
1038
1039         for (i = 0; i < pba_size; i++) {
1040                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1041                 if (status != I40E_SUCCESS) {
1042                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1043                         return status;
1044                 }
1045
1046                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1047                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1048         }
1049         pba_num[(pba_size * 2)] = '\0';
1050
1051         return status;
1052 }
1053
1054 /**
1055  * i40e_get_media_type - Gets media type
1056  * @hw: pointer to the hardware structure
1057  **/
1058 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1059 {
1060         enum i40e_media_type media;
1061
1062         switch (hw->phy.link_info.phy_type) {
1063         case I40E_PHY_TYPE_10GBASE_SR:
1064         case I40E_PHY_TYPE_10GBASE_LR:
1065         case I40E_PHY_TYPE_1000BASE_SX:
1066         case I40E_PHY_TYPE_1000BASE_LX:
1067         case I40E_PHY_TYPE_40GBASE_SR4:
1068         case I40E_PHY_TYPE_40GBASE_LR4:
1069                 media = I40E_MEDIA_TYPE_FIBER;
1070                 break;
1071         case I40E_PHY_TYPE_100BASE_TX:
1072         case I40E_PHY_TYPE_1000BASE_T:
1073         case I40E_PHY_TYPE_10GBASE_T:
1074                 media = I40E_MEDIA_TYPE_BASET;
1075                 break;
1076         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1077         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1078         case I40E_PHY_TYPE_10GBASE_CR1:
1079         case I40E_PHY_TYPE_40GBASE_CR4:
1080         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1081         case I40E_PHY_TYPE_40GBASE_AOC:
1082         case I40E_PHY_TYPE_10GBASE_AOC:
1083                 media = I40E_MEDIA_TYPE_DA;
1084                 break;
1085         case I40E_PHY_TYPE_1000BASE_KX:
1086         case I40E_PHY_TYPE_10GBASE_KX4:
1087         case I40E_PHY_TYPE_10GBASE_KR:
1088         case I40E_PHY_TYPE_40GBASE_KR4:
1089         case I40E_PHY_TYPE_20GBASE_KR2:
1090                 media = I40E_MEDIA_TYPE_BACKPLANE;
1091                 break;
1092         case I40E_PHY_TYPE_SGMII:
1093         case I40E_PHY_TYPE_XAUI:
1094         case I40E_PHY_TYPE_XFI:
1095         case I40E_PHY_TYPE_XLAUI:
1096         case I40E_PHY_TYPE_XLPPI:
1097         default:
1098                 media = I40E_MEDIA_TYPE_UNKNOWN;
1099                 break;
1100         }
1101
1102         return media;
1103 }
1104
1105 #define I40E_PF_RESET_WAIT_COUNT        200
1106 /**
1107  * i40e_pf_reset - Reset the PF
1108  * @hw: pointer to the hardware structure
1109  *
1110  * Assuming someone else has triggered a global reset,
1111  * assure the global reset is complete and then reset the PF
1112  **/
1113 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1114 {
1115         u32 cnt = 0;
1116         u32 cnt1 = 0;
1117         u32 reg = 0;
1118         u32 grst_del;
1119
1120         /* Poll for Global Reset steady state in case of recent GRST.
1121          * The grst delay value is in 100ms units, and we'll wait a
1122          * couple counts longer to be sure we don't just miss the end.
1123          */
1124         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1125                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1126                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1127         for (cnt = 0; cnt < grst_del + 2; cnt++) {
1128                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1129                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1130                         break;
1131                 i40e_msec_delay(100);
1132         }
1133         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1134                 DEBUGOUT("Global reset polling failed to complete.\n");
1135                 return I40E_ERR_RESET_FAILED;
1136         }
1137
1138         /* Now Wait for the FW to be ready */
1139         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1140                 reg = rd32(hw, I40E_GLNVM_ULD);
1141                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1142                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1143                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1144                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1145                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1146                         break;
1147                 }
1148                 i40e_msec_delay(10);
1149         }
1150         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1151                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1152                 DEBUGOUT("wait for FW Reset complete timedout\n");
1153                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1154                 return I40E_ERR_RESET_FAILED;
1155         }
1156
1157         /* If there was a Global Reset in progress when we got here,
1158          * we don't need to do the PF Reset
1159          */
1160         if (!cnt) {
1161                 reg = rd32(hw, I40E_PFGEN_CTRL);
1162                 wr32(hw, I40E_PFGEN_CTRL,
1163                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1164                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1165                         reg = rd32(hw, I40E_PFGEN_CTRL);
1166                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1167                                 break;
1168                         i40e_msec_delay(1);
1169                 }
1170                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1171                         DEBUGOUT("PF reset polling failed to complete.\n");
1172                         return I40E_ERR_RESET_FAILED;
1173                 }
1174         }
1175
1176         i40e_clear_pxe_mode(hw);
1177
1178
1179         return I40E_SUCCESS;
1180 }
1181
1182 /**
1183  * i40e_clear_hw - clear out any left over hw state
1184  * @hw: pointer to the hw struct
1185  *
1186  * Clear queues and interrupts, typically called at init time,
1187  * but after the capabilities have been found so we know how many
1188  * queues and msix vectors have been allocated.
1189  **/
1190 void i40e_clear_hw(struct i40e_hw *hw)
1191 {
1192         u32 num_queues, base_queue;
1193         u32 num_pf_int;
1194         u32 num_vf_int;
1195         u32 num_vfs;
1196         u32 i, j;
1197         u32 val;
1198         u32 eol = 0x7ff;
1199
1200         /* get number of interrupts, queues, and vfs */
1201         val = rd32(hw, I40E_GLPCI_CNF2);
1202         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1203                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1204         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1205                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1206
1207         val = rd32(hw, I40E_PFLAN_QALLOC);
1208         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1209                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1210         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1211                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1212         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1213                 num_queues = (j - base_queue) + 1;
1214         else
1215                 num_queues = 0;
1216
1217         val = rd32(hw, I40E_PF_VT_PFALLOC);
1218         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1219                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1220         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1221                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1222         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1223                 num_vfs = (j - i) + 1;
1224         else
1225                 num_vfs = 0;
1226
1227         /* stop all the interrupts */
1228         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1229         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1230         for (i = 0; i < num_pf_int - 2; i++)
1231                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1232
1233         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1234         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1235         wr32(hw, I40E_PFINT_LNKLST0, val);
1236         for (i = 0; i < num_pf_int - 2; i++)
1237                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1238         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1239         for (i = 0; i < num_vfs; i++)
1240                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1241         for (i = 0; i < num_vf_int - 2; i++)
1242                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1243
1244         /* warn the HW of the coming Tx disables */
1245         for (i = 0; i < num_queues; i++) {
1246                 u32 abs_queue_idx = base_queue + i;
1247                 u32 reg_block = 0;
1248
1249                 if (abs_queue_idx >= 128) {
1250                         reg_block = abs_queue_idx / 128;
1251                         abs_queue_idx %= 128;
1252                 }
1253
1254                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1255                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1256                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1257                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1258
1259                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1260         }
1261         i40e_usec_delay(400);
1262
1263         /* stop all the queues */
1264         for (i = 0; i < num_queues; i++) {
1265                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1266                 wr32(hw, I40E_QTX_ENA(i), 0);
1267                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1268                 wr32(hw, I40E_QRX_ENA(i), 0);
1269         }
1270
1271         /* short wait for all queue disables to settle */
1272         i40e_usec_delay(50);
1273 }
1274
1275 /**
1276  * i40e_clear_pxe_mode - clear pxe operations mode
1277  * @hw: pointer to the hw struct
1278  *
1279  * Make sure all PXE mode settings are cleared, including things
1280  * like descriptor fetch/write-back mode.
1281  **/
1282 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1283 {
1284         if (i40e_check_asq_alive(hw))
1285                 i40e_aq_clear_pxe_mode(hw, NULL);
1286 }
1287
1288 /**
1289  * i40e_led_is_mine - helper to find matching led
1290  * @hw: pointer to the hw struct
1291  * @idx: index into GPIO registers
1292  *
1293  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1294  */
1295 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1296 {
1297         u32 gpio_val = 0;
1298         u32 port;
1299
1300         if (!hw->func_caps.led[idx])
1301                 return 0;
1302
1303         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1304         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1305                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1306
1307         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1308          * if it is not our port then ignore
1309          */
1310         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1311             (port != hw->port))
1312                 return 0;
1313
1314         return gpio_val;
1315 }
1316
1317 #define I40E_COMBINED_ACTIVITY 0xA
1318 #define I40E_FILTER_ACTIVITY 0xE
1319 #define I40E_LINK_ACTIVITY 0xC
1320 #define I40E_MAC_ACTIVITY 0xD
1321 #define I40E_LED0 22
1322
1323 /**
1324  * i40e_led_get - return current on/off mode
1325  * @hw: pointer to the hw struct
1326  *
1327  * The value returned is the 'mode' field as defined in the
1328  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1329  * values are variations of possible behaviors relating to
1330  * blink, link, and wire.
1331  **/
1332 u32 i40e_led_get(struct i40e_hw *hw)
1333 {
1334         u32 current_mode = 0;
1335         u32 mode = 0;
1336         int i;
1337
1338         /* as per the documentation GPIO 22-29 are the LED
1339          * GPIO pins named LED0..LED7
1340          */
1341         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1342                 u32 gpio_val = i40e_led_is_mine(hw, i);
1343
1344                 if (!gpio_val)
1345                         continue;
1346
1347                 /* ignore gpio LED src mode entries related to the activity LEDs */
1348                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1349                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1350                 switch (current_mode) {
1351                 case I40E_COMBINED_ACTIVITY:
1352                 case I40E_FILTER_ACTIVITY:
1353                 case I40E_MAC_ACTIVITY:
1354                         continue;
1355                 default:
1356                         break;
1357                 }
1358
1359                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1360                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1361                 break;
1362         }
1363
1364         return mode;
1365 }
1366
1367 /**
1368  * i40e_led_set - set new on/off mode
1369  * @hw: pointer to the hw struct
1370  * @mode: 0=off, 0xf=on (else see manual for mode details)
1371  * @blink: true if the LED should blink when on, false if steady
1372  *
1373  * if this function is used to turn on the blink it should
1374  * be used to disable the blink when restoring the original state.
1375  **/
1376 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1377 {
1378         u32 current_mode = 0;
1379         int i;
1380
1381         if (mode & 0xfffffff0)
1382                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1383
1384         /* as per the documentation GPIO 22-29 are the LED
1385          * GPIO pins named LED0..LED7
1386          */
1387         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1388                 u32 gpio_val = i40e_led_is_mine(hw, i);
1389
1390                 if (!gpio_val)
1391                         continue;
1392
1393                 /* ignore gpio LED src mode entries related to the activity LEDs */
1394                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1395                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1396                 switch (current_mode) {
1397                 case I40E_COMBINED_ACTIVITY:
1398                 case I40E_FILTER_ACTIVITY:
1399                 case I40E_MAC_ACTIVITY:
1400                         continue;
1401                 default:
1402                         break;
1403                 }
1404
1405                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1406                 /* this & is a bit of paranoia, but serves as a range check */
1407                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1408                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1409
1410                 if (mode == I40E_LINK_ACTIVITY)
1411                         blink = false;
1412
1413                 if (blink)
1414                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1415                 else
1416                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1417
1418                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1419                 break;
1420         }
1421 }
1422
1423 /* Admin command wrappers */
1424
1425 /**
1426  * i40e_aq_get_phy_capabilities
1427  * @hw: pointer to the hw struct
1428  * @abilities: structure for PHY capabilities to be filled
1429  * @qualified_modules: report Qualified Modules
1430  * @report_init: report init capabilities (active are default)
1431  * @cmd_details: pointer to command details structure or NULL
1432  *
1433  * Returns the various PHY abilities supported on the Port.
1434  **/
1435 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1436                         bool qualified_modules, bool report_init,
1437                         struct i40e_aq_get_phy_abilities_resp *abilities,
1438                         struct i40e_asq_cmd_details *cmd_details)
1439 {
1440         struct i40e_aq_desc desc;
1441         enum i40e_status_code status;
1442         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1443
1444         if (!abilities)
1445                 return I40E_ERR_PARAM;
1446
1447         i40e_fill_default_direct_cmd_desc(&desc,
1448                                           i40e_aqc_opc_get_phy_abilities);
1449
1450         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1451         if (abilities_size > I40E_AQ_LARGE_BUF)
1452                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1453
1454         if (qualified_modules)
1455                 desc.params.external.param0 |=
1456                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1457
1458         if (report_init)
1459                 desc.params.external.param0 |=
1460                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1461
1462         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1463                                     cmd_details);
1464
1465         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1466                 status = I40E_ERR_UNKNOWN_PHY;
1467
1468         if (report_init)
1469                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1470
1471         return status;
1472 }
1473
1474 /**
1475  * i40e_aq_set_phy_config
1476  * @hw: pointer to the hw struct
1477  * @config: structure with PHY configuration to be set
1478  * @cmd_details: pointer to command details structure or NULL
1479  *
1480  * Set the various PHY configuration parameters
1481  * supported on the Port.One or more of the Set PHY config parameters may be
1482  * ignored in an MFP mode as the PF may not have the privilege to set some
1483  * of the PHY Config parameters. This status will be indicated by the
1484  * command response.
1485  **/
1486 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1487                                 struct i40e_aq_set_phy_config *config,
1488                                 struct i40e_asq_cmd_details *cmd_details)
1489 {
1490         struct i40e_aq_desc desc;
1491         struct i40e_aq_set_phy_config *cmd =
1492                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1493         enum i40e_status_code status;
1494
1495         if (!config)
1496                 return I40E_ERR_PARAM;
1497
1498         i40e_fill_default_direct_cmd_desc(&desc,
1499                                           i40e_aqc_opc_set_phy_config);
1500
1501         *cmd = *config;
1502
1503         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1504
1505         return status;
1506 }
1507
1508 /**
1509  * i40e_set_fc
1510  * @hw: pointer to the hw struct
1511  *
1512  * Set the requested flow control mode using set_phy_config.
1513  **/
1514 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1515                                   bool atomic_restart)
1516 {
1517         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1518         struct i40e_aq_get_phy_abilities_resp abilities;
1519         struct i40e_aq_set_phy_config config;
1520         enum i40e_status_code status;
1521         u8 pause_mask = 0x0;
1522
1523         *aq_failures = 0x0;
1524
1525         switch (fc_mode) {
1526         case I40E_FC_FULL:
1527                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1528                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1529                 break;
1530         case I40E_FC_RX_PAUSE:
1531                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1532                 break;
1533         case I40E_FC_TX_PAUSE:
1534                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1535                 break;
1536         default:
1537                 break;
1538         }
1539
1540         /* Get the current phy config */
1541         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1542                                               NULL);
1543         if (status) {
1544                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1545                 return status;
1546         }
1547
1548         memset(&config, 0, sizeof(config));
1549         /* clear the old pause settings */
1550         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1551                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1552         /* set the new abilities */
1553         config.abilities |= pause_mask;
1554         /* If the abilities have changed, then set the new config */
1555         if (config.abilities != abilities.abilities) {
1556                 /* Auto restart link so settings take effect */
1557                 if (atomic_restart)
1558                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1559                 /* Copy over all the old settings */
1560                 config.phy_type = abilities.phy_type;
1561                 config.link_speed = abilities.link_speed;
1562                 config.eee_capability = abilities.eee_capability;
1563                 config.eeer = abilities.eeer_val;
1564                 config.low_power_ctrl = abilities.d3_lpan;
1565                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1566
1567                 if (status)
1568                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1569         }
1570         /* Update the link info */
1571         status = i40e_update_link_info(hw);
1572         if (status) {
1573                 /* Wait a little bit (on 40G cards it sometimes takes a really
1574                  * long time for link to come back from the atomic reset)
1575                  * and try once more
1576                  */
1577                 i40e_msec_delay(1000);
1578                 status = i40e_update_link_info(hw);
1579         }
1580         if (status)
1581                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1582
1583         return status;
1584 }
1585
1586 /**
1587  * i40e_aq_set_mac_config
1588  * @hw: pointer to the hw struct
1589  * @max_frame_size: Maximum Frame Size to be supported by the port
1590  * @crc_en: Tell HW to append a CRC to outgoing frames
1591  * @pacing: Pacing configurations
1592  * @cmd_details: pointer to command details structure or NULL
1593  *
1594  * Configure MAC settings for frame size, jumbo frame support and the
1595  * addition of a CRC by the hardware.
1596  **/
1597 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1598                                 u16 max_frame_size,
1599                                 bool crc_en, u16 pacing,
1600                                 struct i40e_asq_cmd_details *cmd_details)
1601 {
1602         struct i40e_aq_desc desc;
1603         struct i40e_aq_set_mac_config *cmd =
1604                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1605         enum i40e_status_code status;
1606
1607         if (max_frame_size == 0)
1608                 return I40E_ERR_PARAM;
1609
1610         i40e_fill_default_direct_cmd_desc(&desc,
1611                                           i40e_aqc_opc_set_mac_config);
1612
1613         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1614         cmd->params = ((u8)pacing & 0x0F) << 3;
1615         if (crc_en)
1616                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1617
1618         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1619
1620         return status;
1621 }
1622
1623 /**
1624  * i40e_aq_clear_pxe_mode
1625  * @hw: pointer to the hw struct
1626  * @cmd_details: pointer to command details structure or NULL
1627  *
1628  * Tell the firmware that the driver is taking over from PXE
1629  **/
1630 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1631                         struct i40e_asq_cmd_details *cmd_details)
1632 {
1633         enum i40e_status_code status;
1634         struct i40e_aq_desc desc;
1635         struct i40e_aqc_clear_pxe *cmd =
1636                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1637
1638         i40e_fill_default_direct_cmd_desc(&desc,
1639                                           i40e_aqc_opc_clear_pxe_mode);
1640
1641         cmd->rx_cnt = 0x2;
1642
1643         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1644
1645         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1646
1647         return status;
1648 }
1649
1650 /**
1651  * i40e_aq_set_link_restart_an
1652  * @hw: pointer to the hw struct
1653  * @enable_link: if true: enable link, if false: disable link
1654  * @cmd_details: pointer to command details structure or NULL
1655  *
1656  * Sets up the link and restarts the Auto-Negotiation over the link.
1657  **/
1658 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1659                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1660 {
1661         struct i40e_aq_desc desc;
1662         struct i40e_aqc_set_link_restart_an *cmd =
1663                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1664         enum i40e_status_code status;
1665
1666         i40e_fill_default_direct_cmd_desc(&desc,
1667                                           i40e_aqc_opc_set_link_restart_an);
1668
1669         cmd->command = I40E_AQ_PHY_RESTART_AN;
1670         if (enable_link)
1671                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1672         else
1673                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1674
1675         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1676
1677         return status;
1678 }
1679
1680 /**
1681  * i40e_aq_get_link_info
1682  * @hw: pointer to the hw struct
1683  * @enable_lse: enable/disable LinkStatusEvent reporting
1684  * @link: pointer to link status structure - optional
1685  * @cmd_details: pointer to command details structure or NULL
1686  *
1687  * Returns the link status of the adapter.
1688  **/
1689 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1690                                 bool enable_lse, struct i40e_link_status *link,
1691                                 struct i40e_asq_cmd_details *cmd_details)
1692 {
1693         struct i40e_aq_desc desc;
1694         struct i40e_aqc_get_link_status *resp =
1695                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1696         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1697         enum i40e_status_code status;
1698         bool tx_pause, rx_pause;
1699         u16 command_flags;
1700
1701         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1702
1703         if (enable_lse)
1704                 command_flags = I40E_AQ_LSE_ENABLE;
1705         else
1706                 command_flags = I40E_AQ_LSE_DISABLE;
1707         resp->command_flags = CPU_TO_LE16(command_flags);
1708
1709         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1710
1711         if (status != I40E_SUCCESS)
1712                 goto aq_get_link_info_exit;
1713
1714         /* save off old link status information */
1715         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1716                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1717
1718         /* update link status */
1719         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1720         hw->phy.media_type = i40e_get_media_type(hw);
1721         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1722         hw_link_info->link_info = resp->link_info;
1723         hw_link_info->an_info = resp->an_info;
1724         hw_link_info->ext_info = resp->ext_info;
1725         hw_link_info->loopback = resp->loopback;
1726         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1727         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1728
1729         /* update fc info */
1730         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1731         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1732         if (tx_pause & rx_pause)
1733                 hw->fc.current_mode = I40E_FC_FULL;
1734         else if (tx_pause)
1735                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1736         else if (rx_pause)
1737                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1738         else
1739                 hw->fc.current_mode = I40E_FC_NONE;
1740
1741         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1742                 hw_link_info->crc_enable = true;
1743         else
1744                 hw_link_info->crc_enable = false;
1745
1746         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1747                 hw_link_info->lse_enable = true;
1748         else
1749                 hw_link_info->lse_enable = false;
1750
1751         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1752              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1753                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1754
1755         /* save link status information */
1756         if (link)
1757                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1758                             I40E_NONDMA_TO_NONDMA);
1759
1760         /* flag cleared so helper functions don't call AQ again */
1761         hw->phy.get_link_info = false;
1762
1763 aq_get_link_info_exit:
1764         return status;
1765 }
1766
1767 /**
1768  * i40e_aq_set_phy_int_mask
1769  * @hw: pointer to the hw struct
1770  * @mask: interrupt mask to be set
1771  * @cmd_details: pointer to command details structure or NULL
1772  *
1773  * Set link interrupt mask.
1774  **/
1775 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1776                                 u16 mask,
1777                                 struct i40e_asq_cmd_details *cmd_details)
1778 {
1779         struct i40e_aq_desc desc;
1780         struct i40e_aqc_set_phy_int_mask *cmd =
1781                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1782         enum i40e_status_code status;
1783
1784         i40e_fill_default_direct_cmd_desc(&desc,
1785                                           i40e_aqc_opc_set_phy_int_mask);
1786
1787         cmd->event_mask = CPU_TO_LE16(mask);
1788
1789         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1790
1791         return status;
1792 }
1793
1794 /**
1795  * i40e_aq_get_local_advt_reg
1796  * @hw: pointer to the hw struct
1797  * @advt_reg: local AN advertisement register value
1798  * @cmd_details: pointer to command details structure or NULL
1799  *
1800  * Get the Local AN advertisement register value.
1801  **/
1802 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1803                                 u64 *advt_reg,
1804                                 struct i40e_asq_cmd_details *cmd_details)
1805 {
1806         struct i40e_aq_desc desc;
1807         struct i40e_aqc_an_advt_reg *resp =
1808                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1809         enum i40e_status_code status;
1810
1811         i40e_fill_default_direct_cmd_desc(&desc,
1812                                           i40e_aqc_opc_get_local_advt_reg);
1813
1814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816         if (status != I40E_SUCCESS)
1817                 goto aq_get_local_advt_reg_exit;
1818
1819         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1820         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1821
1822 aq_get_local_advt_reg_exit:
1823         return status;
1824 }
1825
1826 /**
1827  * i40e_aq_set_local_advt_reg
1828  * @hw: pointer to the hw struct
1829  * @advt_reg: local AN advertisement register value
1830  * @cmd_details: pointer to command details structure or NULL
1831  *
1832  * Get the Local AN advertisement register value.
1833  **/
1834 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1835                                 u64 advt_reg,
1836                                 struct i40e_asq_cmd_details *cmd_details)
1837 {
1838         struct i40e_aq_desc desc;
1839         struct i40e_aqc_an_advt_reg *cmd =
1840                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1841         enum i40e_status_code status;
1842
1843         i40e_fill_default_direct_cmd_desc(&desc,
1844                                           i40e_aqc_opc_get_local_advt_reg);
1845
1846         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1847         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1848
1849         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1850
1851         return status;
1852 }
1853
1854 /**
1855  * i40e_aq_get_partner_advt
1856  * @hw: pointer to the hw struct
1857  * @advt_reg: AN partner advertisement register value
1858  * @cmd_details: pointer to command details structure or NULL
1859  *
1860  * Get the link partner AN advertisement register value.
1861  **/
1862 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1863                                 u64 *advt_reg,
1864                                 struct i40e_asq_cmd_details *cmd_details)
1865 {
1866         struct i40e_aq_desc desc;
1867         struct i40e_aqc_an_advt_reg *resp =
1868                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1869         enum i40e_status_code status;
1870
1871         i40e_fill_default_direct_cmd_desc(&desc,
1872                                           i40e_aqc_opc_get_partner_advt);
1873
1874         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1875
1876         if (status != I40E_SUCCESS)
1877                 goto aq_get_partner_advt_exit;
1878
1879         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1880         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1881
1882 aq_get_partner_advt_exit:
1883         return status;
1884 }
1885
1886 /**
1887  * i40e_aq_set_lb_modes
1888  * @hw: pointer to the hw struct
1889  * @lb_modes: loopback mode to be set
1890  * @cmd_details: pointer to command details structure or NULL
1891  *
1892  * Sets loopback modes.
1893  **/
1894 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1895                                 u16 lb_modes,
1896                                 struct i40e_asq_cmd_details *cmd_details)
1897 {
1898         struct i40e_aq_desc desc;
1899         struct i40e_aqc_set_lb_mode *cmd =
1900                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1901         enum i40e_status_code status;
1902
1903         i40e_fill_default_direct_cmd_desc(&desc,
1904                                           i40e_aqc_opc_set_lb_modes);
1905
1906         cmd->lb_mode = CPU_TO_LE16(lb_modes);
1907
1908         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1909
1910         return status;
1911 }
1912
1913 /**
1914  * i40e_aq_set_phy_debug
1915  * @hw: pointer to the hw struct
1916  * @cmd_flags: debug command flags
1917  * @cmd_details: pointer to command details structure or NULL
1918  *
1919  * Reset the external PHY.
1920  **/
1921 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1922                                 struct i40e_asq_cmd_details *cmd_details)
1923 {
1924         struct i40e_aq_desc desc;
1925         struct i40e_aqc_set_phy_debug *cmd =
1926                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1927         enum i40e_status_code status;
1928
1929         i40e_fill_default_direct_cmd_desc(&desc,
1930                                           i40e_aqc_opc_set_phy_debug);
1931
1932         cmd->command_flags = cmd_flags;
1933
1934         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1935
1936         return status;
1937 }
1938
1939 /**
1940  * i40e_aq_add_vsi
1941  * @hw: pointer to the hw struct
1942  * @vsi_ctx: pointer to a vsi context struct
1943  * @cmd_details: pointer to command details structure or NULL
1944  *
1945  * Add a VSI context to the hardware.
1946 **/
1947 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1948                                 struct i40e_vsi_context *vsi_ctx,
1949                                 struct i40e_asq_cmd_details *cmd_details)
1950 {
1951         struct i40e_aq_desc desc;
1952         struct i40e_aqc_add_get_update_vsi *cmd =
1953                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1954         struct i40e_aqc_add_get_update_vsi_completion *resp =
1955                 (struct i40e_aqc_add_get_update_vsi_completion *)
1956                 &desc.params.raw;
1957         enum i40e_status_code status;
1958
1959         i40e_fill_default_direct_cmd_desc(&desc,
1960                                           i40e_aqc_opc_add_vsi);
1961
1962         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1963         cmd->connection_type = vsi_ctx->connection_type;
1964         cmd->vf_id = vsi_ctx->vf_num;
1965         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1966
1967         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1968
1969         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1970                                     sizeof(vsi_ctx->info), cmd_details);
1971
1972         if (status != I40E_SUCCESS)
1973                 goto aq_add_vsi_exit;
1974
1975         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1976         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1977         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1978         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1979
1980 aq_add_vsi_exit:
1981         return status;
1982 }
1983
1984 /**
1985  * i40e_aq_set_default_vsi
1986  * @hw: pointer to the hw struct
1987  * @seid: vsi number
1988  * @cmd_details: pointer to command details structure or NULL
1989  **/
1990 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1991                                 u16 seid,
1992                                 struct i40e_asq_cmd_details *cmd_details)
1993 {
1994         struct i40e_aq_desc desc;
1995         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1996                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1997                 &desc.params.raw;
1998         enum i40e_status_code status;
1999
2000         i40e_fill_default_direct_cmd_desc(&desc,
2001                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2002
2003         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2004         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2005         cmd->seid = CPU_TO_LE16(seid);
2006
2007         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2008
2009         return status;
2010 }
2011
2012 /**
2013  * i40e_aq_set_vsi_unicast_promiscuous
2014  * @hw: pointer to the hw struct
2015  * @seid: vsi number
2016  * @set: set unicast promiscuous enable/disable
2017  * @cmd_details: pointer to command details structure or NULL
2018  **/
2019 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2020                                 u16 seid, bool set,
2021                                 struct i40e_asq_cmd_details *cmd_details)
2022 {
2023         struct i40e_aq_desc desc;
2024         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2025                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2026         enum i40e_status_code status;
2027         u16 flags = 0;
2028
2029         i40e_fill_default_direct_cmd_desc(&desc,
2030                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2031
2032         if (set)
2033                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2034
2035         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2036
2037         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2038
2039         cmd->seid = CPU_TO_LE16(seid);
2040         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2041
2042         return status;
2043 }
2044
2045 /**
2046  * i40e_aq_set_vsi_multicast_promiscuous
2047  * @hw: pointer to the hw struct
2048  * @seid: vsi number
2049  * @set: set multicast promiscuous enable/disable
2050  * @cmd_details: pointer to command details structure or NULL
2051  **/
2052 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2053                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2054 {
2055         struct i40e_aq_desc desc;
2056         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2057                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2058         enum i40e_status_code status;
2059         u16 flags = 0;
2060
2061         i40e_fill_default_direct_cmd_desc(&desc,
2062                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2063
2064         if (set)
2065                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2066
2067         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2068
2069         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2070
2071         cmd->seid = CPU_TO_LE16(seid);
2072         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2073
2074         return status;
2075 }
2076
2077 /**
2078  * i40e_aq_set_vsi_mc_promisc_on_vlan
2079  * @hw: pointer to the hw struct
2080  * @seid: vsi number
2081  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2082  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2083  * @cmd_details: pointer to command details structure or NULL
2084  **/
2085 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2086                                 u16 seid, bool enable, u16 vid,
2087                                 struct i40e_asq_cmd_details *cmd_details)
2088 {
2089         struct i40e_aq_desc desc;
2090         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2091                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2092         enum i40e_status_code status;
2093         u16 flags = 0;
2094
2095         i40e_fill_default_direct_cmd_desc(&desc,
2096                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2097
2098         if (enable)
2099                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2100
2101         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2102         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2103         cmd->seid = CPU_TO_LE16(seid);
2104         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2105
2106         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2107
2108         return status;
2109 }
2110
2111 /**
2112  * i40e_aq_set_vsi_uc_promisc_on_vlan
2113  * @hw: pointer to the hw struct
2114  * @seid: vsi number
2115  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2116  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2117  * @cmd_details: pointer to command details structure or NULL
2118  **/
2119 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2120                                 u16 seid, bool enable, u16 vid,
2121                                 struct i40e_asq_cmd_details *cmd_details)
2122 {
2123         struct i40e_aq_desc desc;
2124         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2125                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2126         enum i40e_status_code status;
2127         u16 flags = 0;
2128
2129         i40e_fill_default_direct_cmd_desc(&desc,
2130                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2131
2132         if (enable)
2133                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2134
2135         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2136         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2137         cmd->seid = CPU_TO_LE16(seid);
2138         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2139
2140         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2141
2142         return status;
2143 }
2144
2145 /**
2146  * i40e_aq_set_vsi_broadcast
2147  * @hw: pointer to the hw struct
2148  * @seid: vsi number
2149  * @set_filter: true to set filter, false to clear filter
2150  * @cmd_details: pointer to command details structure or NULL
2151  *
2152  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2153  **/
2154 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2155                                 u16 seid, bool set_filter,
2156                                 struct i40e_asq_cmd_details *cmd_details)
2157 {
2158         struct i40e_aq_desc desc;
2159         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2160                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2161         enum i40e_status_code status;
2162
2163         i40e_fill_default_direct_cmd_desc(&desc,
2164                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2165
2166         if (set_filter)
2167                 cmd->promiscuous_flags
2168                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2169         else
2170                 cmd->promiscuous_flags
2171                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2172
2173         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2174         cmd->seid = CPU_TO_LE16(seid);
2175         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2176
2177         return status;
2178 }
2179
2180 /**
2181  * i40e_get_vsi_params - get VSI configuration info
2182  * @hw: pointer to the hw struct
2183  * @vsi_ctx: pointer to a vsi context struct
2184  * @cmd_details: pointer to command details structure or NULL
2185  **/
2186 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2187                                 struct i40e_vsi_context *vsi_ctx,
2188                                 struct i40e_asq_cmd_details *cmd_details)
2189 {
2190         struct i40e_aq_desc desc;
2191         struct i40e_aqc_add_get_update_vsi *cmd =
2192                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2193         struct i40e_aqc_add_get_update_vsi_completion *resp =
2194                 (struct i40e_aqc_add_get_update_vsi_completion *)
2195                 &desc.params.raw;
2196         enum i40e_status_code status;
2197
2198         UNREFERENCED_1PARAMETER(cmd_details);
2199         i40e_fill_default_direct_cmd_desc(&desc,
2200                                           i40e_aqc_opc_get_vsi_parameters);
2201
2202         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2203
2204         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2205
2206         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2207                                     sizeof(vsi_ctx->info), NULL);
2208
2209         if (status != I40E_SUCCESS)
2210                 goto aq_get_vsi_params_exit;
2211
2212         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2213         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2214         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2215         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2216
2217 aq_get_vsi_params_exit:
2218         return status;
2219 }
2220
2221 /**
2222  * i40e_aq_update_vsi_params
2223  * @hw: pointer to the hw struct
2224  * @vsi_ctx: pointer to a vsi context struct
2225  * @cmd_details: pointer to command details structure or NULL
2226  *
2227  * Update a VSI context.
2228  **/
2229 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2230                                 struct i40e_vsi_context *vsi_ctx,
2231                                 struct i40e_asq_cmd_details *cmd_details)
2232 {
2233         struct i40e_aq_desc desc;
2234         struct i40e_aqc_add_get_update_vsi *cmd =
2235                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2236         enum i40e_status_code status;
2237
2238         i40e_fill_default_direct_cmd_desc(&desc,
2239                                           i40e_aqc_opc_update_vsi_parameters);
2240         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2241
2242         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2243
2244         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2245                                     sizeof(vsi_ctx->info), cmd_details);
2246
2247         return status;
2248 }
2249
2250 /**
2251  * i40e_aq_get_switch_config
2252  * @hw: pointer to the hardware structure
2253  * @buf: pointer to the result buffer
2254  * @buf_size: length of input buffer
2255  * @start_seid: seid to start for the report, 0 == beginning
2256  * @cmd_details: pointer to command details structure or NULL
2257  *
2258  * Fill the buf with switch configuration returned from AdminQ command
2259  **/
2260 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2261                                 struct i40e_aqc_get_switch_config_resp *buf,
2262                                 u16 buf_size, u16 *start_seid,
2263                                 struct i40e_asq_cmd_details *cmd_details)
2264 {
2265         struct i40e_aq_desc desc;
2266         struct i40e_aqc_switch_seid *scfg =
2267                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2268         enum i40e_status_code status;
2269
2270         i40e_fill_default_direct_cmd_desc(&desc,
2271                                           i40e_aqc_opc_get_switch_config);
2272         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2273         if (buf_size > I40E_AQ_LARGE_BUF)
2274                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2275         scfg->seid = CPU_TO_LE16(*start_seid);
2276
2277         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2278         *start_seid = LE16_TO_CPU(scfg->seid);
2279
2280         return status;
2281 }
2282
2283 /**
2284  * i40e_aq_get_firmware_version
2285  * @hw: pointer to the hw struct
2286  * @fw_major_version: firmware major version
2287  * @fw_minor_version: firmware minor version
2288  * @fw_build: firmware build number
2289  * @api_major_version: major queue version
2290  * @api_minor_version: minor queue version
2291  * @cmd_details: pointer to command details structure or NULL
2292  *
2293  * Get the firmware version from the admin queue commands
2294  **/
2295 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2296                                 u16 *fw_major_version, u16 *fw_minor_version,
2297                                 u32 *fw_build,
2298                                 u16 *api_major_version, u16 *api_minor_version,
2299                                 struct i40e_asq_cmd_details *cmd_details)
2300 {
2301         struct i40e_aq_desc desc;
2302         struct i40e_aqc_get_version *resp =
2303                 (struct i40e_aqc_get_version *)&desc.params.raw;
2304         enum i40e_status_code status;
2305
2306         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2307
2308         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2309
2310         if (status == I40E_SUCCESS) {
2311                 if (fw_major_version != NULL)
2312                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2313                 if (fw_minor_version != NULL)
2314                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2315                 if (fw_build != NULL)
2316                         *fw_build = LE32_TO_CPU(resp->fw_build);
2317                 if (api_major_version != NULL)
2318                         *api_major_version = LE16_TO_CPU(resp->api_major);
2319                 if (api_minor_version != NULL)
2320                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2321
2322                 /* A workaround to fix the API version in SW */
2323                 if (api_major_version && api_minor_version &&
2324                     fw_major_version && fw_minor_version &&
2325                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2326                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2327                      (*fw_major_version > 4)))
2328                         *api_minor_version = 2;
2329         }
2330
2331         return status;
2332 }
2333
2334 /**
2335  * i40e_aq_send_driver_version
2336  * @hw: pointer to the hw struct
2337  * @dv: driver's major, minor version
2338  * @cmd_details: pointer to command details structure or NULL
2339  *
2340  * Send the driver version to the firmware
2341  **/
2342 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2343                                 struct i40e_driver_version *dv,
2344                                 struct i40e_asq_cmd_details *cmd_details)
2345 {
2346         struct i40e_aq_desc desc;
2347         struct i40e_aqc_driver_version *cmd =
2348                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2349         enum i40e_status_code status;
2350         u16 len;
2351
2352         if (dv == NULL)
2353                 return I40E_ERR_PARAM;
2354
2355         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2356
2357         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2358         cmd->driver_major_ver = dv->major_version;
2359         cmd->driver_minor_ver = dv->minor_version;
2360         cmd->driver_build_ver = dv->build_version;
2361         cmd->driver_subbuild_ver = dv->subbuild_version;
2362
2363         len = 0;
2364         while (len < sizeof(dv->driver_string) &&
2365                (dv->driver_string[len] < 0x80) &&
2366                dv->driver_string[len])
2367                 len++;
2368         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2369                                        len, cmd_details);
2370
2371         return status;
2372 }
2373
2374 /**
2375  * i40e_get_link_status - get status of the HW network link
2376  * @hw: pointer to the hw struct
2377  * @link_up: pointer to bool (true/false = linkup/linkdown)
2378  *
2379  * Variable link_up true if link is up, false if link is down.
2380  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2381  *
2382  * Side effect: LinkStatusEvent reporting becomes enabled
2383  **/
2384 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2385 {
2386         enum i40e_status_code status = I40E_SUCCESS;
2387
2388         if (hw->phy.get_link_info) {
2389                 status = i40e_update_link_info(hw);
2390
2391                 if (status != I40E_SUCCESS)
2392                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2393                                    status);
2394         }
2395
2396         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2397
2398         return status;
2399 }
2400
2401 /**
2402  * i40e_updatelink_status - update status of the HW network link
2403  * @hw: pointer to the hw struct
2404  **/
2405 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2406 {
2407         struct i40e_aq_get_phy_abilities_resp abilities;
2408         enum i40e_status_code status = I40E_SUCCESS;
2409
2410         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2411         if (status)
2412                 return status;
2413
2414         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2415                                               NULL);
2416         if (status)
2417                 return status;
2418
2419         memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2420                 sizeof(hw->phy.link_info.module_type));
2421
2422         return status;
2423 }
2424
2425 /**
2426  * i40e_get_link_speed
2427  * @hw: pointer to the hw struct
2428  *
2429  * Returns the link speed of the adapter.
2430  **/
2431 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2432 {
2433         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2434         enum i40e_status_code status = I40E_SUCCESS;
2435
2436         if (hw->phy.get_link_info) {
2437                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2438
2439                 if (status != I40E_SUCCESS)
2440                         goto i40e_link_speed_exit;
2441         }
2442
2443         speed = hw->phy.link_info.link_speed;
2444
2445 i40e_link_speed_exit:
2446         return speed;
2447 }
2448
2449 /**
2450  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2451  * @hw: pointer to the hw struct
2452  * @uplink_seid: the MAC or other gizmo SEID
2453  * @downlink_seid: the VSI SEID
2454  * @enabled_tc: bitmap of TCs to be enabled
2455  * @default_port: true for default port VSI, false for control port
2456  * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2457  * @veb_seid: pointer to where to put the resulting VEB SEID
2458  * @cmd_details: pointer to command details structure or NULL
2459  *
2460  * This asks the FW to add a VEB between the uplink and downlink
2461  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2462  **/
2463 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2464                                 u16 downlink_seid, u8 enabled_tc,
2465                                 bool default_port, bool enable_l2_filtering,
2466                                 u16 *veb_seid,
2467                                 struct i40e_asq_cmd_details *cmd_details)
2468 {
2469         struct i40e_aq_desc desc;
2470         struct i40e_aqc_add_veb *cmd =
2471                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2472         struct i40e_aqc_add_veb_completion *resp =
2473                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2474         enum i40e_status_code status;
2475         u16 veb_flags = 0;
2476
2477         /* SEIDs need to either both be set or both be 0 for floating VEB */
2478         if (!!uplink_seid != !!downlink_seid)
2479                 return I40E_ERR_PARAM;
2480
2481         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2482
2483         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2484         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2485         cmd->enable_tcs = enabled_tc;
2486         if (!uplink_seid)
2487                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2488         if (default_port)
2489                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2490         else
2491                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2492
2493         if (enable_l2_filtering)
2494                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2495
2496         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2497
2498         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2499
2500         if (!status && veb_seid)
2501                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2502
2503         return status;
2504 }
2505
2506 /**
2507  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2508  * @hw: pointer to the hw struct
2509  * @veb_seid: the SEID of the VEB to query
2510  * @switch_id: the uplink switch id
2511  * @floating: set to true if the VEB is floating
2512  * @statistic_index: index of the stats counter block for this VEB
2513  * @vebs_used: number of VEB's used by function
2514  * @vebs_free: total VEB's not reserved by any function
2515  * @cmd_details: pointer to command details structure or NULL
2516  *
2517  * This retrieves the parameters for a particular VEB, specified by
2518  * uplink_seid, and returns them to the caller.
2519  **/
2520 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2521                                 u16 veb_seid, u16 *switch_id,
2522                                 bool *floating, u16 *statistic_index,
2523                                 u16 *vebs_used, u16 *vebs_free,
2524                                 struct i40e_asq_cmd_details *cmd_details)
2525 {
2526         struct i40e_aq_desc desc;
2527         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2528                 (struct i40e_aqc_get_veb_parameters_completion *)
2529                 &desc.params.raw;
2530         enum i40e_status_code status;
2531
2532         if (veb_seid == 0)
2533                 return I40E_ERR_PARAM;
2534
2535         i40e_fill_default_direct_cmd_desc(&desc,
2536                                           i40e_aqc_opc_get_veb_parameters);
2537         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2538
2539         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2540         if (status)
2541                 goto get_veb_exit;
2542
2543         if (switch_id)
2544                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2545         if (statistic_index)
2546                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2547         if (vebs_used)
2548                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2549         if (vebs_free)
2550                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2551         if (floating) {
2552                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2553                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2554                         *floating = true;
2555                 else
2556                         *floating = false;
2557         }
2558
2559 get_veb_exit:
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_aq_add_macvlan
2565  * @hw: pointer to the hw struct
2566  * @seid: VSI for the mac address
2567  * @mv_list: list of macvlans to be added
2568  * @count: length of the list
2569  * @cmd_details: pointer to command details structure or NULL
2570  *
2571  * Add MAC/VLAN addresses to the HW filtering
2572  **/
2573 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2574                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2575                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2576 {
2577         struct i40e_aq_desc desc;
2578         struct i40e_aqc_macvlan *cmd =
2579                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2580         enum i40e_status_code status;
2581         u16 buf_size;
2582
2583         if (count == 0 || !mv_list || !hw)
2584                 return I40E_ERR_PARAM;
2585
2586         buf_size = count * sizeof(*mv_list);
2587
2588         /* prep the rest of the request */
2589         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2590         cmd->num_addresses = CPU_TO_LE16(count);
2591         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2592         cmd->seid[1] = 0;
2593         cmd->seid[2] = 0;
2594
2595         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2596         if (buf_size > I40E_AQ_LARGE_BUF)
2597                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2598
2599         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2600                                     cmd_details);
2601
2602         return status;
2603 }
2604
2605 /**
2606  * i40e_aq_remove_macvlan
2607  * @hw: pointer to the hw struct
2608  * @seid: VSI for the mac address
2609  * @mv_list: list of macvlans to be removed
2610  * @count: length of the list
2611  * @cmd_details: pointer to command details structure or NULL
2612  *
2613  * Remove MAC/VLAN addresses from the HW filtering
2614  **/
2615 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2616                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2617                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2618 {
2619         struct i40e_aq_desc desc;
2620         struct i40e_aqc_macvlan *cmd =
2621                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2622         enum i40e_status_code status;
2623         u16 buf_size;
2624
2625         if (count == 0 || !mv_list || !hw)
2626                 return I40E_ERR_PARAM;
2627
2628         buf_size = count * sizeof(*mv_list);
2629
2630         /* prep the rest of the request */
2631         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2632         cmd->num_addresses = CPU_TO_LE16(count);
2633         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2634         cmd->seid[1] = 0;
2635         cmd->seid[2] = 0;
2636
2637         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2638         if (buf_size > I40E_AQ_LARGE_BUF)
2639                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2640
2641         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2642                                        cmd_details);
2643
2644         return status;
2645 }
2646
2647 /**
2648  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2649  * @hw: pointer to the hw struct
2650  * @seid: VSI for the vlan filters
2651  * @v_list: list of vlan filters to be added
2652  * @count: length of the list
2653  * @cmd_details: pointer to command details structure or NULL
2654  **/
2655 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2656                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2657                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2658 {
2659         struct i40e_aq_desc desc;
2660         struct i40e_aqc_macvlan *cmd =
2661                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2662         enum i40e_status_code status;
2663         u16 buf_size;
2664
2665         if (count == 0 || !v_list || !hw)
2666                 return I40E_ERR_PARAM;
2667
2668         buf_size = count * sizeof(*v_list);
2669
2670         /* prep the rest of the request */
2671         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2672         cmd->num_addresses = CPU_TO_LE16(count);
2673         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2674         cmd->seid[1] = 0;
2675         cmd->seid[2] = 0;
2676
2677         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2678         if (buf_size > I40E_AQ_LARGE_BUF)
2679                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2680
2681         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2682                                        cmd_details);
2683
2684         return status;
2685 }
2686
2687 /**
2688  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2689  * @hw: pointer to the hw struct
2690  * @seid: VSI for the vlan filters
2691  * @v_list: list of macvlans to be removed
2692  * @count: length of the list
2693  * @cmd_details: pointer to command details structure or NULL
2694  **/
2695 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2696                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2697                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2698 {
2699         struct i40e_aq_desc desc;
2700         struct i40e_aqc_macvlan *cmd =
2701                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2702         enum i40e_status_code status;
2703         u16 buf_size;
2704
2705         if (count == 0 || !v_list || !hw)
2706                 return I40E_ERR_PARAM;
2707
2708         buf_size = count * sizeof(*v_list);
2709
2710         /* prep the rest of the request */
2711         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2712         cmd->num_addresses = CPU_TO_LE16(count);
2713         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2714         cmd->seid[1] = 0;
2715         cmd->seid[2] = 0;
2716
2717         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2718         if (buf_size > I40E_AQ_LARGE_BUF)
2719                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2720
2721         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2722                                        cmd_details);
2723
2724         return status;
2725 }
2726
2727 /**
2728  * i40e_aq_send_msg_to_vf
2729  * @hw: pointer to the hardware structure
2730  * @vfid: vf id to send msg
2731  * @v_opcode: opcodes for VF-PF communication
2732  * @v_retval: return error code
2733  * @msg: pointer to the msg buffer
2734  * @msglen: msg length
2735  * @cmd_details: pointer to command details
2736  *
2737  * send msg to vf
2738  **/
2739 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2740                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2741                                 struct i40e_asq_cmd_details *cmd_details)
2742 {
2743         struct i40e_aq_desc desc;
2744         struct i40e_aqc_pf_vf_message *cmd =
2745                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2746         enum i40e_status_code status;
2747
2748         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2749         cmd->id = CPU_TO_LE32(vfid);
2750         desc.cookie_high = CPU_TO_LE32(v_opcode);
2751         desc.cookie_low = CPU_TO_LE32(v_retval);
2752         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2753         if (msglen) {
2754                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2755                                                 I40E_AQ_FLAG_RD));
2756                 if (msglen > I40E_AQ_LARGE_BUF)
2757                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2758                 desc.datalen = CPU_TO_LE16(msglen);
2759         }
2760         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2761
2762         return status;
2763 }
2764
2765 /**
2766  * i40e_aq_debug_read_register
2767  * @hw: pointer to the hw struct
2768  * @reg_addr: register address
2769  * @reg_val: register value
2770  * @cmd_details: pointer to command details structure or NULL
2771  *
2772  * Read the register using the admin queue commands
2773  **/
2774 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2775                                 u32 reg_addr, u64 *reg_val,
2776                                 struct i40e_asq_cmd_details *cmd_details)
2777 {
2778         struct i40e_aq_desc desc;
2779         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2780                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2781         enum i40e_status_code status;
2782
2783         if (reg_val == NULL)
2784                 return I40E_ERR_PARAM;
2785
2786         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2787
2788         cmd_resp->address = CPU_TO_LE32(reg_addr);
2789
2790         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2791
2792         if (status == I40E_SUCCESS) {
2793                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2794                            (u64)LE32_TO_CPU(cmd_resp->value_low);
2795         }
2796
2797         return status;
2798 }
2799
2800 /**
2801  * i40e_aq_debug_write_register
2802  * @hw: pointer to the hw struct
2803  * @reg_addr: register address
2804  * @reg_val: register value
2805  * @cmd_details: pointer to command details structure or NULL
2806  *
2807  * Write to a register using the admin queue commands
2808  **/
2809 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2810                                 u32 reg_addr, u64 reg_val,
2811                                 struct i40e_asq_cmd_details *cmd_details)
2812 {
2813         struct i40e_aq_desc desc;
2814         struct i40e_aqc_debug_reg_read_write *cmd =
2815                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2816         enum i40e_status_code status;
2817
2818         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2819
2820         cmd->address = CPU_TO_LE32(reg_addr);
2821         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2822         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2823
2824         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2825
2826         return status;
2827 }
2828
2829 /**
2830  * i40e_aq_get_hmc_resource_profile
2831  * @hw: pointer to the hw struct
2832  * @profile: type of profile the HMC is to be set as
2833  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2834  * @cmd_details: pointer to command details structure or NULL
2835  *
2836  * query the HMC profile of the device.
2837  **/
2838 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2839                                 enum i40e_aq_hmc_profile *profile,
2840                                 u8 *pe_vf_enabled_count,
2841                                 struct i40e_asq_cmd_details *cmd_details)
2842 {
2843         struct i40e_aq_desc desc;
2844         struct i40e_aq_get_set_hmc_resource_profile *resp =
2845                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2846         enum i40e_status_code status;
2847
2848         i40e_fill_default_direct_cmd_desc(&desc,
2849                                 i40e_aqc_opc_query_hmc_resource_profile);
2850         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2851
2852         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2853                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2854         *pe_vf_enabled_count = resp->pe_vf_enabled &
2855                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2856
2857         return status;
2858 }
2859
2860 /**
2861  * i40e_aq_set_hmc_resource_profile
2862  * @hw: pointer to the hw struct
2863  * @profile: type of profile the HMC is to be set as
2864  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2865  * @cmd_details: pointer to command details structure or NULL
2866  *
2867  * set the HMC profile of the device.
2868  **/
2869 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2870                                 enum i40e_aq_hmc_profile profile,
2871                                 u8 pe_vf_enabled_count,
2872                                 struct i40e_asq_cmd_details *cmd_details)
2873 {
2874         struct i40e_aq_desc desc;
2875         struct i40e_aq_get_set_hmc_resource_profile *cmd =
2876                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2877         enum i40e_status_code status;
2878
2879         i40e_fill_default_direct_cmd_desc(&desc,
2880                                         i40e_aqc_opc_set_hmc_resource_profile);
2881
2882         cmd->pm_profile = (u8)profile;
2883         cmd->pe_vf_enabled = pe_vf_enabled_count;
2884
2885         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2886
2887         return status;
2888 }
2889
2890 /**
2891  * i40e_aq_request_resource
2892  * @hw: pointer to the hw struct
2893  * @resource: resource id
2894  * @access: access type
2895  * @sdp_number: resource number
2896  * @timeout: the maximum time in ms that the driver may hold the resource
2897  * @cmd_details: pointer to command details structure or NULL
2898  *
2899  * requests common resource using the admin queue commands
2900  **/
2901 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2902                                 enum i40e_aq_resources_ids resource,
2903                                 enum i40e_aq_resource_access_type access,
2904                                 u8 sdp_number, u64 *timeout,
2905                                 struct i40e_asq_cmd_details *cmd_details)
2906 {
2907         struct i40e_aq_desc desc;
2908         struct i40e_aqc_request_resource *cmd_resp =
2909                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2910         enum i40e_status_code status;
2911
2912         DEBUGFUNC("i40e_aq_request_resource");
2913
2914         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2915
2916         cmd_resp->resource_id = CPU_TO_LE16(resource);
2917         cmd_resp->access_type = CPU_TO_LE16(access);
2918         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2919
2920         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2921         /* The completion specifies the maximum time in ms that the driver
2922          * may hold the resource in the Timeout field.
2923          * If the resource is held by someone else, the command completes with
2924          * busy return value and the timeout field indicates the maximum time
2925          * the current owner of the resource has to free it.
2926          */
2927         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2928                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2929
2930         return status;
2931 }
2932
2933 /**
2934  * i40e_aq_release_resource
2935  * @hw: pointer to the hw struct
2936  * @resource: resource id
2937  * @sdp_number: resource number
2938  * @cmd_details: pointer to command details structure or NULL
2939  *
2940  * release common resource using the admin queue commands
2941  **/
2942 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2943                                 enum i40e_aq_resources_ids resource,
2944                                 u8 sdp_number,
2945                                 struct i40e_asq_cmd_details *cmd_details)
2946 {
2947         struct i40e_aq_desc desc;
2948         struct i40e_aqc_request_resource *cmd =
2949                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2950         enum i40e_status_code status;
2951
2952         DEBUGFUNC("i40e_aq_release_resource");
2953
2954         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2955
2956         cmd->resource_id = CPU_TO_LE16(resource);
2957         cmd->resource_number = CPU_TO_LE32(sdp_number);
2958
2959         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2960
2961         return status;
2962 }
2963
2964 /**
2965  * i40e_aq_read_nvm
2966  * @hw: pointer to the hw struct
2967  * @module_pointer: module pointer location in words from the NVM beginning
2968  * @offset: byte offset from the module beginning
2969  * @length: length of the section to be read (in bytes from the offset)
2970  * @data: command buffer (size [bytes] = length)
2971  * @last_command: tells if this is the last command in a series
2972  * @cmd_details: pointer to command details structure or NULL
2973  *
2974  * Read the NVM using the admin queue commands
2975  **/
2976 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2977                                 u32 offset, u16 length, void *data,
2978                                 bool last_command,
2979                                 struct i40e_asq_cmd_details *cmd_details)
2980 {
2981         struct i40e_aq_desc desc;
2982         struct i40e_aqc_nvm_update *cmd =
2983                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2984         enum i40e_status_code status;
2985
2986         DEBUGFUNC("i40e_aq_read_nvm");
2987
2988         /* In offset the highest byte must be zeroed. */
2989         if (offset & 0xFF000000) {
2990                 status = I40E_ERR_PARAM;
2991                 goto i40e_aq_read_nvm_exit;
2992         }
2993
2994         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2995
2996         /* If this is the last command in a series, set the proper flag. */
2997         if (last_command)
2998                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2999         cmd->module_pointer = module_pointer;
3000         cmd->offset = CPU_TO_LE32(offset);
3001         cmd->length = CPU_TO_LE16(length);
3002
3003         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3004         if (length > I40E_AQ_LARGE_BUF)
3005                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3006
3007         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3008
3009 i40e_aq_read_nvm_exit:
3010         return status;
3011 }
3012
3013 /**
3014  * i40e_aq_read_nvm_config - read an nvm config block
3015  * @hw: pointer to the hw struct
3016  * @cmd_flags: NVM access admin command bits
3017  * @field_id: field or feature id
3018  * @data: buffer for result
3019  * @buf_size: buffer size
3020  * @element_count: pointer to count of elements read by FW
3021  * @cmd_details: pointer to command details structure or NULL
3022  **/
3023 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3024                                 u8 cmd_flags, u32 field_id, void *data,
3025                                 u16 buf_size, u16 *element_count,
3026                                 struct i40e_asq_cmd_details *cmd_details)
3027 {
3028         struct i40e_aq_desc desc;
3029         struct i40e_aqc_nvm_config_read *cmd =
3030                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3031         enum i40e_status_code status;
3032
3033         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3034         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3035         if (buf_size > I40E_AQ_LARGE_BUF)
3036                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3037
3038         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3039         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3040         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3041                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3042         else
3043                 cmd->element_id_msw = 0;
3044
3045         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3046
3047         if (!status && element_count)
3048                 *element_count = LE16_TO_CPU(cmd->element_count);
3049
3050         return status;
3051 }
3052
3053 /**
3054  * i40e_aq_write_nvm_config - write an nvm config block
3055  * @hw: pointer to the hw struct
3056  * @cmd_flags: NVM access admin command bits
3057  * @data: buffer for result
3058  * @buf_size: buffer size
3059  * @element_count: count of elements to be written
3060  * @cmd_details: pointer to command details structure or NULL
3061  **/
3062 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3063                                 u8 cmd_flags, void *data, u16 buf_size,
3064                                 u16 element_count,
3065                                 struct i40e_asq_cmd_details *cmd_details)
3066 {
3067         struct i40e_aq_desc desc;
3068         struct i40e_aqc_nvm_config_write *cmd =
3069                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3070         enum i40e_status_code status;
3071
3072         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3073         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3074         if (buf_size > I40E_AQ_LARGE_BUF)
3075                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3076
3077         cmd->element_count = CPU_TO_LE16(element_count);
3078         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3079         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3080
3081         return status;
3082 }
3083
3084 /**
3085  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3086  * @hw: pointer to the hw struct
3087  * @cmd_details: pointer to command details structure or NULL
3088  **/
3089 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3090                                 void *buff, u16 buff_size,
3091                                 struct i40e_asq_cmd_details *cmd_details)
3092 {
3093         struct i40e_aq_desc desc;
3094         enum i40e_status_code status;
3095
3096         UNREFERENCED_2PARAMETER(buff, buff_size);
3097
3098         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3100         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3101                 status = I40E_ERR_NOT_IMPLEMENTED;
3102
3103         return status;
3104 }
3105
3106 /**
3107  * i40e_aq_erase_nvm
3108  * @hw: pointer to the hw struct
3109  * @module_pointer: module pointer location in words from the NVM beginning
3110  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3111  * @length: length of the section to be erased (expressed in 4 KB)
3112  * @last_command: tells if this is the last command in a series
3113  * @cmd_details: pointer to command details structure or NULL
3114  *
3115  * Erase the NVM sector using the admin queue commands
3116  **/
3117 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3118                                 u32 offset, u16 length, bool last_command,
3119                                 struct i40e_asq_cmd_details *cmd_details)
3120 {
3121         struct i40e_aq_desc desc;
3122         struct i40e_aqc_nvm_update *cmd =
3123                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3124         enum i40e_status_code status;
3125
3126         DEBUGFUNC("i40e_aq_erase_nvm");
3127
3128         /* In offset the highest byte must be zeroed. */
3129         if (offset & 0xFF000000) {
3130                 status = I40E_ERR_PARAM;
3131                 goto i40e_aq_erase_nvm_exit;
3132         }
3133
3134         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3135
3136         /* If this is the last command in a series, set the proper flag. */
3137         if (last_command)
3138                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3139         cmd->module_pointer = module_pointer;
3140         cmd->offset = CPU_TO_LE32(offset);
3141         cmd->length = CPU_TO_LE16(length);
3142
3143         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3144
3145 i40e_aq_erase_nvm_exit:
3146         return status;
3147 }
3148
3149 #define I40E_DEV_FUNC_CAP_SWITCH_MODE   0x01
3150 #define I40E_DEV_FUNC_CAP_MGMT_MODE     0x02
3151 #define I40E_DEV_FUNC_CAP_NPAR          0x03
3152 #define I40E_DEV_FUNC_CAP_OS2BMC        0x04
3153 #define I40E_DEV_FUNC_CAP_VALID_FUNC    0x05
3154 #define I40E_DEV_FUNC_CAP_SRIOV_1_1     0x12
3155 #define I40E_DEV_FUNC_CAP_VF            0x13
3156 #define I40E_DEV_FUNC_CAP_VMDQ          0x14
3157 #define I40E_DEV_FUNC_CAP_802_1_QBG     0x15
3158 #define I40E_DEV_FUNC_CAP_802_1_QBH     0x16
3159 #define I40E_DEV_FUNC_CAP_VSI           0x17
3160 #define I40E_DEV_FUNC_CAP_DCB           0x18
3161 #define I40E_DEV_FUNC_CAP_FCOE          0x21
3162 #define I40E_DEV_FUNC_CAP_ISCSI         0x22
3163 #define I40E_DEV_FUNC_CAP_RSS           0x40
3164 #define I40E_DEV_FUNC_CAP_RX_QUEUES     0x41
3165 #define I40E_DEV_FUNC_CAP_TX_QUEUES     0x42
3166 #define I40E_DEV_FUNC_CAP_MSIX          0x43
3167 #define I40E_DEV_FUNC_CAP_MSIX_VF       0x44
3168 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3169 #define I40E_DEV_FUNC_CAP_IEEE_1588     0x46
3170 #define I40E_DEV_FUNC_CAP_MFP_MODE_1    0xF1
3171 #define I40E_DEV_FUNC_CAP_CEM           0xF2
3172 #define I40E_DEV_FUNC_CAP_IWARP         0x51
3173 #define I40E_DEV_FUNC_CAP_LED           0x61
3174 #define I40E_DEV_FUNC_CAP_SDP           0x62
3175 #define I40E_DEV_FUNC_CAP_MDIO          0x63
3176
3177 /**
3178  * i40e_parse_discover_capabilities
3179  * @hw: pointer to the hw struct
3180  * @buff: pointer to a buffer containing device/function capability records
3181  * @cap_count: number of capability records in the list
3182  * @list_type_opc: type of capabilities list to parse
3183  *
3184  * Parse the device/function capabilities list.
3185  **/
3186 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3187                                      u32 cap_count,
3188                                      enum i40e_admin_queue_opc list_type_opc)
3189 {
3190         struct i40e_aqc_list_capabilities_element_resp *cap;
3191         u32 valid_functions, num_functions;
3192         u32 number, logical_id, phys_id;
3193         struct i40e_hw_capabilities *p;
3194         u32 i = 0;
3195         u16 id;
3196
3197         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3198
3199         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3200                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3201         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3202                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3203         else
3204                 return;
3205
3206         for (i = 0; i < cap_count; i++, cap++) {
3207                 id = LE16_TO_CPU(cap->id);
3208                 number = LE32_TO_CPU(cap->number);
3209                 logical_id = LE32_TO_CPU(cap->logical_id);
3210                 phys_id = LE32_TO_CPU(cap->phys_id);
3211
3212                 switch (id) {
3213                 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3214                         p->switch_mode = number;
3215                         break;
3216                 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3217                         p->management_mode = number;
3218                         break;
3219                 case I40E_DEV_FUNC_CAP_NPAR:
3220                         p->npar_enable = number;
3221                         break;
3222                 case I40E_DEV_FUNC_CAP_OS2BMC:
3223                         p->os2bmc = number;
3224                         break;
3225                 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3226                         p->valid_functions = number;
3227                         break;
3228                 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3229                         if (number == 1)
3230                                 p->sr_iov_1_1 = true;
3231                         break;
3232                 case I40E_DEV_FUNC_CAP_VF:
3233                         p->num_vfs = number;
3234                         p->vf_base_id = logical_id;
3235                         break;
3236                 case I40E_DEV_FUNC_CAP_VMDQ:
3237                         if (number == 1)
3238                                 p->vmdq = true;
3239                         break;
3240                 case I40E_DEV_FUNC_CAP_802_1_QBG:
3241                         if (number == 1)
3242                                 p->evb_802_1_qbg = true;
3243                         break;
3244                 case I40E_DEV_FUNC_CAP_802_1_QBH:
3245                         if (number == 1)
3246                                 p->evb_802_1_qbh = true;
3247                         break;
3248                 case I40E_DEV_FUNC_CAP_VSI:
3249                         p->num_vsis = number;
3250                         break;
3251                 case I40E_DEV_FUNC_CAP_DCB:
3252                         if (number == 1) {
3253                                 p->dcb = true;
3254                                 p->enabled_tcmap = logical_id;
3255                                 p->maxtc = phys_id;
3256                         }
3257                         break;
3258                 case I40E_DEV_FUNC_CAP_FCOE:
3259                         if (number == 1)
3260                                 p->fcoe = true;
3261                         break;
3262                 case I40E_DEV_FUNC_CAP_ISCSI:
3263                         if (number == 1)
3264                                 p->iscsi = true;
3265                         break;
3266                 case I40E_DEV_FUNC_CAP_RSS:
3267                         p->rss = true;
3268                         p->rss_table_size = number;
3269                         p->rss_table_entry_width = logical_id;
3270                         break;
3271                 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3272                         p->num_rx_qp = number;
3273                         p->base_queue = phys_id;
3274                         break;
3275                 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3276                         p->num_tx_qp = number;
3277                         p->base_queue = phys_id;
3278                         break;
3279                 case I40E_DEV_FUNC_CAP_MSIX:
3280                         p->num_msix_vectors = number;
3281                         break;
3282                 case I40E_DEV_FUNC_CAP_MSIX_VF:
3283                         p->num_msix_vectors_vf = number;
3284                         break;
3285                 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
3286                         if (number == 1)
3287                                 p->mfp_mode_1 = true;
3288                         break;
3289                 case I40E_DEV_FUNC_CAP_CEM:
3290                         if (number == 1)
3291                                 p->mgmt_cem = true;
3292                         break;
3293                 case I40E_DEV_FUNC_CAP_IWARP:
3294                         if (number == 1)
3295                                 p->iwarp = true;
3296                         break;
3297                 case I40E_DEV_FUNC_CAP_LED:
3298                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3299                                 p->led[phys_id] = true;
3300                         break;
3301                 case I40E_DEV_FUNC_CAP_SDP:
3302                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3303                                 p->sdp[phys_id] = true;
3304                         break;
3305                 case I40E_DEV_FUNC_CAP_MDIO:
3306                         if (number == 1) {
3307                                 p->mdio_port_num = phys_id;
3308                                 p->mdio_port_mode = logical_id;
3309                         }
3310                         break;
3311                 case I40E_DEV_FUNC_CAP_IEEE_1588:
3312                         if (number == 1)
3313                                 p->ieee_1588 = true;
3314                         break;
3315                 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3316                         p->fd = true;
3317                         p->fd_filters_guaranteed = number;
3318                         p->fd_filters_best_effort = logical_id;
3319                         break;
3320                 default:
3321                         break;
3322                 }
3323         }
3324
3325 #ifdef I40E_FCOE_ENA
3326         /* Software override ensuring FCoE is disabled if npar or mfp
3327          * mode because it is not supported in these modes.
3328          */
3329         if (p->npar_enable || p->mfp_mode_1)
3330                 p->fcoe = false;
3331 #else
3332         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3333         p->fcoe = false;
3334 #endif
3335
3336         /* count the enabled ports (aka the "not disabled" ports) */
3337         hw->num_ports = 0;
3338         for (i = 0; i < 4; i++) {
3339                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3340                 u64 port_cfg = 0;
3341
3342                 /* use AQ read to get the physical register offset instead
3343                  * of the port relative offset
3344                  */
3345                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3346                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3347                         hw->num_ports++;
3348         }
3349
3350         valid_functions = p->valid_functions;
3351         num_functions = 0;
3352         while (valid_functions) {
3353                 if (valid_functions & 1)
3354                         num_functions++;
3355                 valid_functions >>= 1;
3356         }
3357
3358         /* partition id is 1-based, and functions are evenly spread
3359          * across the ports as partitions
3360          */
3361         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3362         hw->num_partitions = num_functions / hw->num_ports;
3363
3364         /* additional HW specific goodies that might
3365          * someday be HW version specific
3366          */
3367         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3368 }
3369
3370 /**
3371  * i40e_aq_discover_capabilities
3372  * @hw: pointer to the hw struct
3373  * @buff: a virtual buffer to hold the capabilities
3374  * @buff_size: Size of the virtual buffer
3375  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3376  * @list_type_opc: capabilities type to discover - pass in the command opcode
3377  * @cmd_details: pointer to command details structure or NULL
3378  *
3379  * Get the device capabilities descriptions from the firmware
3380  **/
3381 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3382                                 void *buff, u16 buff_size, u16 *data_size,
3383                                 enum i40e_admin_queue_opc list_type_opc,
3384                                 struct i40e_asq_cmd_details *cmd_details)
3385 {
3386         struct i40e_aqc_list_capabilites *cmd;
3387         struct i40e_aq_desc desc;
3388         enum i40e_status_code status = I40E_SUCCESS;
3389
3390         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3391
3392         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3393                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3394                 status = I40E_ERR_PARAM;
3395                 goto exit;
3396         }
3397
3398         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3399
3400         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3401         if (buff_size > I40E_AQ_LARGE_BUF)
3402                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3403
3404         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3405         *data_size = LE16_TO_CPU(desc.datalen);
3406
3407         if (status)
3408                 goto exit;
3409
3410         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3411                                          list_type_opc);
3412
3413 exit:
3414         return status;
3415 }
3416
3417 /**
3418  * i40e_aq_update_nvm
3419  * @hw: pointer to the hw struct
3420  * @module_pointer: module pointer location in words from the NVM beginning
3421  * @offset: byte offset from the module beginning
3422  * @length: length of the section to be written (in bytes from the offset)
3423  * @data: command buffer (size [bytes] = length)
3424  * @last_command: tells if this is the last command in a series
3425  * @cmd_details: pointer to command details structure or NULL
3426  *
3427  * Update the NVM using the admin queue commands
3428  **/
3429 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3430                                 u32 offset, u16 length, void *data,
3431                                 bool last_command,
3432                                 struct i40e_asq_cmd_details *cmd_details)
3433 {
3434         struct i40e_aq_desc desc;
3435         struct i40e_aqc_nvm_update *cmd =
3436                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3437         enum i40e_status_code status;
3438
3439         DEBUGFUNC("i40e_aq_update_nvm");
3440
3441         /* In offset the highest byte must be zeroed. */
3442         if (offset & 0xFF000000) {
3443                 status = I40E_ERR_PARAM;
3444                 goto i40e_aq_update_nvm_exit;
3445         }
3446
3447         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3448
3449         /* If this is the last command in a series, set the proper flag. */
3450         if (last_command)
3451                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3452         cmd->module_pointer = module_pointer;
3453         cmd->offset = CPU_TO_LE32(offset);
3454         cmd->length = CPU_TO_LE16(length);
3455
3456         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3457         if (length > I40E_AQ_LARGE_BUF)
3458                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3459
3460         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3461
3462 i40e_aq_update_nvm_exit:
3463         return status;
3464 }
3465
3466 /**
3467  * i40e_aq_get_lldp_mib
3468  * @hw: pointer to the hw struct
3469  * @bridge_type: type of bridge requested
3470  * @mib_type: Local, Remote or both Local and Remote MIBs
3471  * @buff: pointer to a user supplied buffer to store the MIB block
3472  * @buff_size: size of the buffer (in bytes)
3473  * @local_len : length of the returned Local LLDP MIB
3474  * @remote_len: length of the returned Remote LLDP MIB
3475  * @cmd_details: pointer to command details structure or NULL
3476  *
3477  * Requests the complete LLDP MIB (entire packet).
3478  **/
3479 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3480                                 u8 mib_type, void *buff, u16 buff_size,
3481                                 u16 *local_len, u16 *remote_len,
3482                                 struct i40e_asq_cmd_details *cmd_details)
3483 {
3484         struct i40e_aq_desc desc;
3485         struct i40e_aqc_lldp_get_mib *cmd =
3486                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3487         struct i40e_aqc_lldp_get_mib *resp =
3488                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3489         enum i40e_status_code status;
3490
3491         if (buff_size == 0 || !buff)
3492                 return I40E_ERR_PARAM;
3493
3494         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3495         /* Indirect Command */
3496         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3497
3498         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3499         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3500                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3501
3502         desc.datalen = CPU_TO_LE16(buff_size);
3503
3504         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3505         if (buff_size > I40E_AQ_LARGE_BUF)
3506                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3507
3508         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3509         if (!status) {
3510                 if (local_len != NULL)
3511                         *local_len = LE16_TO_CPU(resp->local_len);
3512                 if (remote_len != NULL)
3513                         *remote_len = LE16_TO_CPU(resp->remote_len);
3514         }
3515
3516         return status;
3517 }
3518
3519  /**
3520  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3521  * @hw: pointer to the hw struct
3522  * @mib_type: Local, Remote or both Local and Remote MIBs
3523  * @buff: pointer to a user supplied buffer to store the MIB block
3524  * @buff_size: size of the buffer (in bytes)
3525  * @cmd_details: pointer to command details structure or NULL
3526  *
3527  * Set the LLDP MIB.
3528  **/
3529 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3530                                 u8 mib_type, void *buff, u16 buff_size,
3531                                 struct i40e_asq_cmd_details *cmd_details)
3532 {
3533         struct i40e_aq_desc desc;
3534         struct i40e_aqc_lldp_set_local_mib *cmd =
3535                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3536         enum i40e_status_code status;
3537
3538         if (buff_size == 0 || !buff)
3539                 return I40E_ERR_PARAM;
3540
3541         i40e_fill_default_direct_cmd_desc(&desc,
3542                                 i40e_aqc_opc_lldp_set_local_mib);
3543         /* Indirect Command */
3544         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3545         if (buff_size > I40E_AQ_LARGE_BUF)
3546                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3547         desc.datalen = CPU_TO_LE16(buff_size);
3548
3549         cmd->type = mib_type;
3550         cmd->length = CPU_TO_LE16(buff_size);
3551         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3552         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3553
3554         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3555         return status;
3556 }
3557
3558 /**
3559  * i40e_aq_cfg_lldp_mib_change_event
3560  * @hw: pointer to the hw struct
3561  * @enable_update: Enable or Disable event posting
3562  * @cmd_details: pointer to command details structure or NULL
3563  *
3564  * Enable or Disable posting of an event on ARQ when LLDP MIB
3565  * associated with the interface changes
3566  **/
3567 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3568                                 bool enable_update,
3569                                 struct i40e_asq_cmd_details *cmd_details)
3570 {
3571         struct i40e_aq_desc desc;
3572         struct i40e_aqc_lldp_update_mib *cmd =
3573                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3574         enum i40e_status_code status;
3575
3576         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3577
3578         if (!enable_update)
3579                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3580
3581         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3582
3583         return status;
3584 }
3585
3586 /**
3587  * i40e_aq_add_lldp_tlv
3588  * @hw: pointer to the hw struct
3589  * @bridge_type: type of bridge
3590  * @buff: buffer with TLV to add
3591  * @buff_size: length of the buffer
3592  * @tlv_len: length of the TLV to be added
3593  * @mib_len: length of the LLDP MIB returned in response
3594  * @cmd_details: pointer to command details structure or NULL
3595  *
3596  * Add the specified TLV to LLDP Local MIB for the given bridge type,
3597  * it is responsibility of the caller to make sure that the TLV is not
3598  * already present in the LLDPDU.
3599  * In return firmware will write the complete LLDP MIB with the newly
3600  * added TLV in the response buffer.
3601  **/
3602 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3603                                 void *buff, u16 buff_size, u16 tlv_len,
3604                                 u16 *mib_len,
3605                                 struct i40e_asq_cmd_details *cmd_details)
3606 {
3607         struct i40e_aq_desc desc;
3608         struct i40e_aqc_lldp_add_tlv *cmd =
3609                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3610         enum i40e_status_code status;
3611
3612         if (buff_size == 0 || !buff || tlv_len == 0)
3613                 return I40E_ERR_PARAM;
3614
3615         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3616
3617         /* Indirect Command */
3618         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3619         if (buff_size > I40E_AQ_LARGE_BUF)
3620                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3621         desc.datalen = CPU_TO_LE16(buff_size);
3622
3623         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3624                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3625         cmd->len = CPU_TO_LE16(tlv_len);
3626
3627         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3628         if (!status) {
3629                 if (mib_len != NULL)
3630                         *mib_len = LE16_TO_CPU(desc.datalen);
3631         }
3632
3633         return status;
3634 }
3635
3636 /**
3637  * i40e_aq_update_lldp_tlv
3638  * @hw: pointer to the hw struct
3639  * @bridge_type: type of bridge
3640  * @buff: buffer with TLV to update
3641  * @buff_size: size of the buffer holding original and updated TLVs
3642  * @old_len: Length of the Original TLV
3643  * @new_len: Length of the Updated TLV
3644  * @offset: offset of the updated TLV in the buff
3645  * @mib_len: length of the returned LLDP MIB
3646  * @cmd_details: pointer to command details structure or NULL
3647  *
3648  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3649  * Firmware will place the complete LLDP MIB in response buffer with the
3650  * updated TLV.
3651  **/
3652 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3653                                 u8 bridge_type, void *buff, u16 buff_size,
3654                                 u16 old_len, u16 new_len, u16 offset,
3655                                 u16 *mib_len,
3656                                 struct i40e_asq_cmd_details *cmd_details)
3657 {
3658         struct i40e_aq_desc desc;
3659         struct i40e_aqc_lldp_update_tlv *cmd =
3660                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3661         enum i40e_status_code status;
3662
3663         if (buff_size == 0 || !buff || offset == 0 ||
3664             old_len == 0 || new_len == 0)
3665                 return I40E_ERR_PARAM;
3666
3667         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3668
3669         /* Indirect Command */
3670         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3671         if (buff_size > I40E_AQ_LARGE_BUF)
3672                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3673         desc.datalen = CPU_TO_LE16(buff_size);
3674
3675         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3676                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3677         cmd->old_len = CPU_TO_LE16(old_len);
3678         cmd->new_offset = CPU_TO_LE16(offset);
3679         cmd->new_len = CPU_TO_LE16(new_len);
3680
3681         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3682         if (!status) {
3683                 if (mib_len != NULL)
3684                         *mib_len = LE16_TO_CPU(desc.datalen);
3685         }
3686
3687         return status;
3688 }
3689
3690 /**
3691  * i40e_aq_delete_lldp_tlv
3692  * @hw: pointer to the hw struct
3693  * @bridge_type: type of bridge
3694  * @buff: pointer to a user supplied buffer that has the TLV
3695  * @buff_size: length of the buffer
3696  * @tlv_len: length of the TLV to be deleted
3697  * @mib_len: length of the returned LLDP MIB
3698  * @cmd_details: pointer to command details structure or NULL
3699  *
3700  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3701  * The firmware places the entire LLDP MIB in the response buffer.
3702  **/
3703 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3704                                 u8 bridge_type, void *buff, u16 buff_size,
3705                                 u16 tlv_len, u16 *mib_len,
3706                                 struct i40e_asq_cmd_details *cmd_details)
3707 {
3708         struct i40e_aq_desc desc;
3709         struct i40e_aqc_lldp_add_tlv *cmd =
3710                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3711         enum i40e_status_code status;
3712
3713         if (buff_size == 0 || !buff)
3714                 return I40E_ERR_PARAM;
3715
3716         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3717
3718         /* Indirect Command */
3719         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3720         if (buff_size > I40E_AQ_LARGE_BUF)
3721                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3722         desc.datalen = CPU_TO_LE16(buff_size);
3723         cmd->len = CPU_TO_LE16(tlv_len);
3724         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3725                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3726
3727         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3728         if (!status) {
3729                 if (mib_len != NULL)
3730                         *mib_len = LE16_TO_CPU(desc.datalen);
3731         }
3732
3733         return status;
3734 }
3735
3736 /**
3737  * i40e_aq_stop_lldp
3738  * @hw: pointer to the hw struct
3739  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3740  * @cmd_details: pointer to command details structure or NULL
3741  *
3742  * Stop or Shutdown the embedded LLDP Agent
3743  **/
3744 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3745                                 struct i40e_asq_cmd_details *cmd_details)
3746 {
3747         struct i40e_aq_desc desc;
3748         struct i40e_aqc_lldp_stop *cmd =
3749                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3750         enum i40e_status_code status;
3751
3752         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3753
3754         if (shutdown_agent)
3755                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3756
3757         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3758
3759         return status;
3760 }
3761
3762 /**
3763  * i40e_aq_start_lldp
3764  * @hw: pointer to the hw struct
3765  * @cmd_details: pointer to command details structure or NULL
3766  *
3767  * Start the embedded LLDP Agent on all ports.
3768  **/
3769 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3770                                 struct i40e_asq_cmd_details *cmd_details)
3771 {
3772         struct i40e_aq_desc desc;
3773         struct i40e_aqc_lldp_start *cmd =
3774                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3775         enum i40e_status_code status;
3776
3777         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3778
3779         cmd->command = I40E_AQ_LLDP_AGENT_START;
3780
3781         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3782
3783         return status;
3784 }
3785
3786 /**
3787  * i40e_aq_get_cee_dcb_config
3788  * @hw: pointer to the hw struct
3789  * @buff: response buffer that stores CEE operational configuration
3790  * @buff_size: size of the buffer passed
3791  * @cmd_details: pointer to command details structure or NULL
3792  *
3793  * Get CEE DCBX mode operational configuration from firmware
3794  **/
3795 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3796                                 void *buff, u16 buff_size,
3797                                 struct i40e_asq_cmd_details *cmd_details)
3798 {
3799         struct i40e_aq_desc desc;
3800         enum i40e_status_code status;
3801
3802         if (buff_size == 0 || !buff)
3803                 return I40E_ERR_PARAM;
3804
3805         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3806
3807         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3808         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3809                                        cmd_details);
3810
3811         return status;
3812 }
3813
3814 /**
3815  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3816  * @hw: pointer to the hw struct
3817  * @start_agent: True if DCBx Agent needs to be Started
3818  *                              False if DCBx Agent needs to be Stopped
3819  * @cmd_details: pointer to command details structure or NULL
3820  *
3821  * Start/Stop the embedded dcbx Agent
3822  **/
3823 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3824                                 bool start_agent,
3825                                 struct i40e_asq_cmd_details *cmd_details)
3826 {
3827         struct i40e_aq_desc desc;
3828         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3829                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3830                                 &desc.params.raw;
3831         enum i40e_status_code status;
3832
3833         i40e_fill_default_direct_cmd_desc(&desc,
3834                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
3835
3836         if (start_agent)
3837                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3838
3839         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3840
3841         return status;
3842 }
3843
3844 /**
3845  * i40e_aq_add_udp_tunnel
3846  * @hw: pointer to the hw struct
3847  * @udp_port: the UDP port to add
3848  * @header_len: length of the tunneling header length in DWords
3849  * @protocol_index: protocol index type
3850  * @filter_index: pointer to filter index
3851  * @cmd_details: pointer to command details structure or NULL
3852  **/
3853 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3854                                 u16 udp_port, u8 protocol_index,
3855                                 u8 *filter_index,
3856                                 struct i40e_asq_cmd_details *cmd_details)
3857 {
3858         struct i40e_aq_desc desc;
3859         struct i40e_aqc_add_udp_tunnel *cmd =
3860                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3861         struct i40e_aqc_del_udp_tunnel_completion *resp =
3862                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3863         enum i40e_status_code status;
3864
3865         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3866
3867         cmd->udp_port = CPU_TO_LE16(udp_port);
3868         cmd->protocol_type = protocol_index;
3869
3870         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3871
3872         if (!status && filter_index)
3873                 *filter_index = resp->index;
3874
3875         return status;
3876 }
3877
3878 /**
3879  * i40e_aq_del_udp_tunnel
3880  * @hw: pointer to the hw struct
3881  * @index: filter index
3882  * @cmd_details: pointer to command details structure or NULL
3883  **/
3884 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3885                                 struct i40e_asq_cmd_details *cmd_details)
3886 {
3887         struct i40e_aq_desc desc;
3888         struct i40e_aqc_remove_udp_tunnel *cmd =
3889                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3890         enum i40e_status_code status;
3891
3892         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3893
3894         cmd->index = index;
3895
3896         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3897
3898         return status;
3899 }
3900
3901 /**
3902  * i40e_aq_get_switch_resource_alloc (0x0204)
3903  * @hw: pointer to the hw struct
3904  * @num_entries: pointer to u8 to store the number of resource entries returned
3905  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
3906  *        to store the resource information for all resource types.  Each
3907  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
3908  * @count: size, in bytes, of the buffer provided
3909  * @cmd_details: pointer to command details structure or NULL
3910  *
3911  * Query the resources allocated to a function.
3912  **/
3913 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3914                         u8 *num_entries,
3915                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3916                         u16 count,
3917                         struct i40e_asq_cmd_details *cmd_details)
3918 {
3919         struct i40e_aq_desc desc;
3920         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3921                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3922         enum i40e_status_code status;
3923         u16 length = count * sizeof(*buf);
3924
3925         i40e_fill_default_direct_cmd_desc(&desc,
3926                                         i40e_aqc_opc_get_switch_resource_alloc);
3927
3928         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3929         if (length > I40E_AQ_LARGE_BUF)
3930                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3931
3932         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3933
3934         if (!status && num_entries)
3935                 *num_entries = cmd_resp->num_entries;
3936
3937         return status;
3938 }
3939
3940 /**
3941  * i40e_aq_delete_element - Delete switch element
3942  * @hw: pointer to the hw struct
3943  * @seid: the SEID to delete from the switch
3944  * @cmd_details: pointer to command details structure or NULL
3945  *
3946  * This deletes a switch element from the switch.
3947  **/
3948 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3949                                 struct i40e_asq_cmd_details *cmd_details)
3950 {
3951         struct i40e_aq_desc desc;
3952         struct i40e_aqc_switch_seid *cmd =
3953                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3954         enum i40e_status_code status;
3955
3956         if (seid == 0)
3957                 return I40E_ERR_PARAM;
3958
3959         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3960
3961         cmd->seid = CPU_TO_LE16(seid);
3962
3963         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3964
3965         return status;
3966 }
3967
3968 /**
3969  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3970  * @hw: pointer to the hw struct
3971  * @flags: component flags
3972  * @mac_seid: uplink seid (MAC SEID)
3973  * @vsi_seid: connected vsi seid
3974  * @ret_seid: seid of create pv component
3975  *
3976  * This instantiates an i40e port virtualizer with specified flags.
3977  * Depending on specified flags the port virtualizer can act as a
3978  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3979  */
3980 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3981                                        u16 mac_seid, u16 vsi_seid,
3982                                        u16 *ret_seid)
3983 {
3984         struct i40e_aq_desc desc;
3985         struct i40e_aqc_add_update_pv *cmd =
3986                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3987         struct i40e_aqc_add_update_pv_completion *resp =
3988                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3989         enum i40e_status_code status;
3990
3991         if (vsi_seid == 0)
3992                 return I40E_ERR_PARAM;
3993
3994         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3995         cmd->command_flags = CPU_TO_LE16(flags);
3996         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3997         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3998
3999         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4000         if (!status && ret_seid)
4001                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4002
4003         return status;
4004 }
4005
4006 /**
4007  * i40e_aq_add_tag - Add an S/E-tag
4008  * @hw: pointer to the hw struct
4009  * @direct_to_queue: should s-tag direct flow to a specific queue
4010  * @vsi_seid: VSI SEID to use this tag
4011  * @tag: value of the tag
4012  * @queue_num: queue number, only valid is direct_to_queue is true
4013  * @tags_used: return value, number of tags in use by this PF
4014  * @tags_free: return value, number of unallocated tags
4015  * @cmd_details: pointer to command details structure or NULL
4016  *
4017  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4018  * the number of tags allocated by the PF, and the number of unallocated
4019  * tags available.
4020  **/
4021 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4022                                 u16 vsi_seid, u16 tag, u16 queue_num,
4023                                 u16 *tags_used, u16 *tags_free,
4024                                 struct i40e_asq_cmd_details *cmd_details)
4025 {
4026         struct i40e_aq_desc desc;
4027         struct i40e_aqc_add_tag *cmd =
4028                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4029         struct i40e_aqc_add_remove_tag_completion *resp =
4030                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4031         enum i40e_status_code status;
4032
4033         if (vsi_seid == 0)
4034                 return I40E_ERR_PARAM;
4035
4036         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4037
4038         cmd->seid = CPU_TO_LE16(vsi_seid);
4039         cmd->tag = CPU_TO_LE16(tag);
4040         if (direct_to_queue) {
4041                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4042                 cmd->queue_number = CPU_TO_LE16(queue_num);
4043         }
4044
4045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4046
4047         if (!status) {
4048                 if (tags_used != NULL)
4049                         *tags_used = LE16_TO_CPU(resp->tags_used);
4050                 if (tags_free != NULL)
4051                         *tags_free = LE16_TO_CPU(resp->tags_free);
4052         }
4053
4054         return status;
4055 }
4056
4057 /**
4058  * i40e_aq_remove_tag - Remove an S- or E-tag
4059  * @hw: pointer to the hw struct
4060  * @vsi_seid: VSI SEID this tag is associated with
4061  * @tag: value of the S-tag to delete
4062  * @tags_used: return value, number of tags in use by this PF
4063  * @tags_free: return value, number of unallocated tags
4064  * @cmd_details: pointer to command details structure or NULL
4065  *
4066  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4067  * the number of tags allocated by the PF, and the number of unallocated
4068  * tags available.
4069  **/
4070 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4071                                 u16 tag, u16 *tags_used, u16 *tags_free,
4072                                 struct i40e_asq_cmd_details *cmd_details)
4073 {
4074         struct i40e_aq_desc desc;
4075         struct i40e_aqc_remove_tag *cmd =
4076                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4077         struct i40e_aqc_add_remove_tag_completion *resp =
4078                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4079         enum i40e_status_code status;
4080
4081         if (vsi_seid == 0)
4082                 return I40E_ERR_PARAM;
4083
4084         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4085
4086         cmd->seid = CPU_TO_LE16(vsi_seid);
4087         cmd->tag = CPU_TO_LE16(tag);
4088
4089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4090
4091         if (!status) {
4092                 if (tags_used != NULL)
4093                         *tags_used = LE16_TO_CPU(resp->tags_used);
4094                 if (tags_free != NULL)
4095                         *tags_free = LE16_TO_CPU(resp->tags_free);
4096         }
4097
4098         return status;
4099 }
4100
4101 /**
4102  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4103  * @hw: pointer to the hw struct
4104  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4105  * @etag: value of E-tag to add
4106  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4107  * @buf: address of indirect buffer
4108  * @tags_used: return value, number of E-tags in use by this port
4109  * @tags_free: return value, number of unallocated M-tags
4110  * @cmd_details: pointer to command details structure or NULL
4111  *
4112  * This associates a multicast E-tag to a port virtualizer.  It will return
4113  * the number of tags allocated by the PF, and the number of unallocated
4114  * tags available.
4115  *
4116  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4117  * num_tags_in_buf long.
4118  **/
4119 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4120                                 u16 etag, u8 num_tags_in_buf, void *buf,
4121                                 u16 *tags_used, u16 *tags_free,
4122                                 struct i40e_asq_cmd_details *cmd_details)
4123 {
4124         struct i40e_aq_desc desc;
4125         struct i40e_aqc_add_remove_mcast_etag *cmd =
4126                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4127         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4128            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4129         enum i40e_status_code status;
4130         u16 length = sizeof(u16) * num_tags_in_buf;
4131
4132         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4133                 return I40E_ERR_PARAM;
4134
4135         i40e_fill_default_direct_cmd_desc(&desc,
4136                                           i40e_aqc_opc_add_multicast_etag);
4137
4138         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4139         cmd->etag = CPU_TO_LE16(etag);
4140         cmd->num_unicast_etags = num_tags_in_buf;
4141
4142         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4143         if (length > I40E_AQ_LARGE_BUF)
4144                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4145
4146         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4147
4148         if (!status) {
4149                 if (tags_used != NULL)
4150                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4151                 if (tags_free != NULL)
4152                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4153         }
4154
4155         return status;
4156 }
4157
4158 /**
4159  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4160  * @hw: pointer to the hw struct
4161  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4162  * @etag: value of the E-tag to remove
4163  * @tags_used: return value, number of tags in use by this port
4164  * @tags_free: return value, number of unallocated tags
4165  * @cmd_details: pointer to command details structure or NULL
4166  *
4167  * This deletes an E-tag from the port virtualizer.  It will return
4168  * the number of tags allocated by the port, and the number of unallocated
4169  * tags available.
4170  **/
4171 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4172                                 u16 etag, u16 *tags_used, u16 *tags_free,
4173                                 struct i40e_asq_cmd_details *cmd_details)
4174 {
4175         struct i40e_aq_desc desc;
4176         struct i40e_aqc_add_remove_mcast_etag *cmd =
4177                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4178         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4179            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4180         enum i40e_status_code status;
4181
4182
4183         if (pv_seid == 0)
4184                 return I40E_ERR_PARAM;
4185
4186         i40e_fill_default_direct_cmd_desc(&desc,
4187                                           i40e_aqc_opc_remove_multicast_etag);
4188
4189         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4190         cmd->etag = CPU_TO_LE16(etag);
4191
4192         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4193
4194         if (!status) {
4195                 if (tags_used != NULL)
4196                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4197                 if (tags_free != NULL)
4198                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4199         }
4200
4201         return status;
4202 }
4203
4204 /**
4205  * i40e_aq_update_tag - Update an S/E-tag
4206  * @hw: pointer to the hw struct
4207  * @vsi_seid: VSI SEID using this S-tag
4208  * @old_tag: old tag value
4209  * @new_tag: new tag value
4210  * @tags_used: return value, number of tags in use by this PF
4211  * @tags_free: return value, number of unallocated tags
4212  * @cmd_details: pointer to command details structure or NULL
4213  *
4214  * This updates the value of the tag currently attached to this VSI
4215  * in the switch complex.  It will return the number of tags allocated
4216  * by the PF, and the number of unallocated tags available.
4217  **/
4218 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4219                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4220                                 u16 *tags_free,
4221                                 struct i40e_asq_cmd_details *cmd_details)
4222 {
4223         struct i40e_aq_desc desc;
4224         struct i40e_aqc_update_tag *cmd =
4225                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4226         struct i40e_aqc_update_tag_completion *resp =
4227                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4228         enum i40e_status_code status;
4229
4230         if (vsi_seid == 0)
4231                 return I40E_ERR_PARAM;
4232
4233         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4234
4235         cmd->seid = CPU_TO_LE16(vsi_seid);
4236         cmd->old_tag = CPU_TO_LE16(old_tag);
4237         cmd->new_tag = CPU_TO_LE16(new_tag);
4238
4239         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4240
4241         if (!status) {
4242                 if (tags_used != NULL)
4243                         *tags_used = LE16_TO_CPU(resp->tags_used);
4244                 if (tags_free != NULL)
4245                         *tags_free = LE16_TO_CPU(resp->tags_free);
4246         }
4247
4248         return status;
4249 }
4250
4251 /**
4252  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4253  * @hw: pointer to the hw struct
4254  * @tcmap: TC map for request/release any ignore PFC condition
4255  * @request: request or release ignore PFC condition
4256  * @tcmap_ret: return TCs for which PFC is currently ignored
4257  * @cmd_details: pointer to command details structure or NULL
4258  *
4259  * This sends out request/release to ignore PFC condition for a TC.
4260  * It will return the TCs for which PFC is currently ignored.
4261  **/
4262 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4263                                 bool request, u8 *tcmap_ret,
4264                                 struct i40e_asq_cmd_details *cmd_details)
4265 {
4266         struct i40e_aq_desc desc;
4267         struct i40e_aqc_pfc_ignore *cmd_resp =
4268                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4269         enum i40e_status_code status;
4270
4271         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4272
4273         if (request)
4274                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4275
4276         cmd_resp->tc_bitmap = tcmap;
4277
4278         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4279
4280         if (!status) {
4281                 if (tcmap_ret != NULL)
4282                         *tcmap_ret = cmd_resp->tc_bitmap;
4283         }
4284
4285         return status;
4286 }
4287
4288 /**
4289  * i40e_aq_dcb_updated - DCB Updated Command
4290  * @hw: pointer to the hw struct
4291  * @cmd_details: pointer to command details structure or NULL
4292  *
4293  * When LLDP is handled in PF this command is used by the PF
4294  * to notify EMP that a DCB setting is modified.
4295  * When LLDP is handled in EMP this command is used by the PF
4296  * to notify EMP whenever one of the following parameters get
4297  * modified:
4298  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4299  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4300  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4301  * EMP will return when the shared RPB settings have been
4302  * recomputed and modified. The retval field in the descriptor
4303  * will be set to 0 when RPB is modified.
4304  **/
4305 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4306                                 struct i40e_asq_cmd_details *cmd_details)
4307 {
4308         struct i40e_aq_desc desc;
4309         enum i40e_status_code status;
4310
4311         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4312
4313         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4314
4315         return status;
4316 }
4317
4318 /**
4319  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4320  * @hw: pointer to the hw struct
4321  * @seid: defines the SEID of the switch for which the stats are requested
4322  * @vlan_id: the VLAN ID for which the statistics are requested
4323  * @stat_index: index of the statistics counters block assigned to this VLAN
4324  * @cmd_details: pointer to command details structure or NULL
4325  *
4326  * XL710 supports 128 smonVlanStats counters.This command is used to
4327  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4328  * switch.
4329  **/
4330 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4331                                 u16 vlan_id, u16 *stat_index,
4332                                 struct i40e_asq_cmd_details *cmd_details)
4333 {
4334         struct i40e_aq_desc desc;
4335         struct i40e_aqc_add_remove_statistics *cmd_resp =
4336                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4337         enum i40e_status_code status;
4338
4339         if ((seid == 0) || (stat_index == NULL))
4340                 return I40E_ERR_PARAM;
4341
4342         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4343
4344         cmd_resp->seid = CPU_TO_LE16(seid);
4345         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4346
4347         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4348
4349         if (!status && stat_index)
4350                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4351
4352         return status;
4353 }
4354
4355 /**
4356  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4357  * @hw: pointer to the hw struct
4358  * @seid: defines the SEID of the switch for which the stats are requested
4359  * @vlan_id: the VLAN ID for which the statistics are requested
4360  * @stat_index: index of the statistics counters block assigned to this VLAN
4361  * @cmd_details: pointer to command details structure or NULL
4362  *
4363  * XL710 supports 128 smonVlanStats counters.This command is used to
4364  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4365  * switch.
4366  **/
4367 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4368                                 u16 vlan_id, u16 stat_index,
4369                                 struct i40e_asq_cmd_details *cmd_details)
4370 {
4371         struct i40e_aq_desc desc;
4372         struct i40e_aqc_add_remove_statistics *cmd =
4373                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4374         enum i40e_status_code status;
4375
4376         if (seid == 0)
4377                 return I40E_ERR_PARAM;
4378
4379         i40e_fill_default_direct_cmd_desc(&desc,
4380                                           i40e_aqc_opc_remove_statistics);
4381
4382         cmd->seid = CPU_TO_LE16(seid);
4383         cmd->vlan  = CPU_TO_LE16(vlan_id);
4384         cmd->stat_index = CPU_TO_LE16(stat_index);
4385
4386         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4387
4388         return status;
4389 }
4390
4391 /**
4392  * i40e_aq_set_port_parameters - set physical port parameters.
4393  * @hw: pointer to the hw struct
4394  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4395  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4396  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4397  * @double_vlan: if set double VLAN is enabled
4398  * @cmd_details: pointer to command details structure or NULL
4399  **/
4400 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4401                                 u16 bad_frame_vsi, bool save_bad_pac,
4402                                 bool pad_short_pac, bool double_vlan,
4403                                 struct i40e_asq_cmd_details *cmd_details)
4404 {
4405         struct i40e_aqc_set_port_parameters *cmd;
4406         enum i40e_status_code status;
4407         struct i40e_aq_desc desc;
4408         u16 command_flags = 0;
4409
4410         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4411
4412         i40e_fill_default_direct_cmd_desc(&desc,
4413                                           i40e_aqc_opc_set_port_parameters);
4414
4415         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4416         if (save_bad_pac)
4417                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4418         if (pad_short_pac)
4419                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4420         if (double_vlan)
4421                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4422         cmd->command_flags = CPU_TO_LE16(command_flags);
4423
4424         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4425
4426         return status;
4427 }
4428
4429 /**
4430  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4431  * @hw: pointer to the hw struct
4432  * @seid: seid for the physical port/switching component/vsi
4433  * @buff: Indirect buffer to hold data parameters and response
4434  * @buff_size: Indirect buffer size
4435  * @opcode: Tx scheduler AQ command opcode
4436  * @cmd_details: pointer to command details structure or NULL
4437  *
4438  * Generic command handler for Tx scheduler AQ commands
4439  **/
4440 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4441                                 void *buff, u16 buff_size,
4442                                  enum i40e_admin_queue_opc opcode,
4443                                 struct i40e_asq_cmd_details *cmd_details)
4444 {
4445         struct i40e_aq_desc desc;
4446         struct i40e_aqc_tx_sched_ind *cmd =
4447                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4448         enum i40e_status_code status;
4449         bool cmd_param_flag = false;
4450
4451         switch (opcode) {
4452         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4453         case i40e_aqc_opc_configure_vsi_tc_bw:
4454         case i40e_aqc_opc_enable_switching_comp_ets:
4455         case i40e_aqc_opc_modify_switching_comp_ets:
4456         case i40e_aqc_opc_disable_switching_comp_ets:
4457         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4458         case i40e_aqc_opc_configure_switching_comp_bw_config:
4459                 cmd_param_flag = true;
4460                 break;
4461         case i40e_aqc_opc_query_vsi_bw_config:
4462         case i40e_aqc_opc_query_vsi_ets_sla_config:
4463         case i40e_aqc_opc_query_switching_comp_ets_config:
4464         case i40e_aqc_opc_query_port_ets_config:
4465         case i40e_aqc_opc_query_switching_comp_bw_config:
4466                 cmd_param_flag = false;
4467                 break;
4468         default:
4469                 return I40E_ERR_PARAM;
4470         }
4471
4472         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4473
4474         /* Indirect command */
4475         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4476         if (cmd_param_flag)
4477                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4478         if (buff_size > I40E_AQ_LARGE_BUF)
4479                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4480
4481         desc.datalen = CPU_TO_LE16(buff_size);
4482
4483         cmd->vsi_seid = CPU_TO_LE16(seid);
4484
4485         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4486
4487         return status;
4488 }
4489
4490 /**
4491  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4492  * @hw: pointer to the hw struct
4493  * @seid: VSI seid
4494  * @credit: BW limit credits (0 = disabled)
4495  * @max_credit: Max BW limit credits
4496  * @cmd_details: pointer to command details structure or NULL
4497  **/
4498 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4499                                 u16 seid, u16 credit, u8 max_credit,
4500                                 struct i40e_asq_cmd_details *cmd_details)
4501 {
4502         struct i40e_aq_desc desc;
4503         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4504                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4505         enum i40e_status_code status;
4506
4507         i40e_fill_default_direct_cmd_desc(&desc,
4508                                           i40e_aqc_opc_configure_vsi_bw_limit);
4509
4510         cmd->vsi_seid = CPU_TO_LE16(seid);
4511         cmd->credit = CPU_TO_LE16(credit);
4512         cmd->max_credit = max_credit;
4513
4514         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4515
4516         return status;
4517 }
4518
4519 /**
4520  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4521  * @hw: pointer to the hw struct
4522  * @seid: switching component seid
4523  * @credit: BW limit credits (0 = disabled)
4524  * @max_bw: Max BW limit credits
4525  * @cmd_details: pointer to command details structure or NULL
4526  **/
4527 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4528                                 u16 seid, u16 credit, u8 max_bw,
4529                                 struct i40e_asq_cmd_details *cmd_details)
4530 {
4531         struct i40e_aq_desc desc;
4532         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4533           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4534         enum i40e_status_code status;
4535
4536         i40e_fill_default_direct_cmd_desc(&desc,
4537                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4538
4539         cmd->seid = CPU_TO_LE16(seid);
4540         cmd->credit = CPU_TO_LE16(credit);
4541         cmd->max_bw = max_bw;
4542
4543         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4544
4545         return status;
4546 }
4547
4548 /**
4549  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4550  * @hw: pointer to the hw struct
4551  * @seid: VSI seid
4552  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4553  * @cmd_details: pointer to command details structure or NULL
4554  **/
4555 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4556                         u16 seid,
4557                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4558                         struct i40e_asq_cmd_details *cmd_details)
4559 {
4560         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4561                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4562                                     cmd_details);
4563 }
4564
4565 /**
4566  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4567  * @hw: pointer to the hw struct
4568  * @seid: VSI seid
4569  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4570  * @cmd_details: pointer to command details structure or NULL
4571  **/
4572 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4573                         u16 seid,
4574                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4575                         struct i40e_asq_cmd_details *cmd_details)
4576 {
4577         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4578                                     i40e_aqc_opc_configure_vsi_tc_bw,
4579                                     cmd_details);
4580 }
4581
4582 /**
4583  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4584  * @hw: pointer to the hw struct
4585  * @seid: seid of the switching component connected to Physical Port
4586  * @ets_data: Buffer holding ETS parameters
4587  * @cmd_details: pointer to command details structure or NULL
4588  **/
4589 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4590                 u16 seid,
4591                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4592                 enum i40e_admin_queue_opc opcode,
4593                 struct i40e_asq_cmd_details *cmd_details)
4594 {
4595         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4596                                     sizeof(*ets_data), opcode, cmd_details);
4597 }
4598
4599 /**
4600  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4601  * @hw: pointer to the hw struct
4602  * @seid: seid of the switching component
4603  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4604  * @cmd_details: pointer to command details structure or NULL
4605  **/
4606 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4607         u16 seid,
4608         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4609         struct i40e_asq_cmd_details *cmd_details)
4610 {
4611         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4612                             i40e_aqc_opc_configure_switching_comp_bw_config,
4613                             cmd_details);
4614 }
4615
4616 /**
4617  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4618  * @hw: pointer to the hw struct
4619  * @seid: seid of the switching component
4620  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4621  * @cmd_details: pointer to command details structure or NULL
4622  **/
4623 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4624         struct i40e_hw *hw, u16 seid,
4625         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4626         struct i40e_asq_cmd_details *cmd_details)
4627 {
4628         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4629                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4630                             cmd_details);
4631 }
4632
4633 /**
4634  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4635  * @hw: pointer to the hw struct
4636  * @seid: seid of the VSI
4637  * @bw_data: Buffer to hold VSI BW configuration
4638  * @cmd_details: pointer to command details structure or NULL
4639  **/
4640 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4641                         u16 seid,
4642                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4643                         struct i40e_asq_cmd_details *cmd_details)
4644 {
4645         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4646                                     i40e_aqc_opc_query_vsi_bw_config,
4647                                     cmd_details);
4648 }
4649
4650 /**
4651  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4652  * @hw: pointer to the hw struct
4653  * @seid: seid of the VSI
4654  * @bw_data: Buffer to hold VSI BW configuration per TC
4655  * @cmd_details: pointer to command details structure or NULL
4656  **/
4657 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4658                         u16 seid,
4659                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4660                         struct i40e_asq_cmd_details *cmd_details)
4661 {
4662         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4663                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4664                                     cmd_details);
4665 }
4666
4667 /**
4668  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4669  * @hw: pointer to the hw struct
4670  * @seid: seid of the switching component
4671  * @bw_data: Buffer to hold switching component's per TC BW config
4672  * @cmd_details: pointer to command details structure or NULL
4673  **/
4674 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4675                 u16 seid,
4676                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4677                 struct i40e_asq_cmd_details *cmd_details)
4678 {
4679         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4680                                    i40e_aqc_opc_query_switching_comp_ets_config,
4681                                    cmd_details);
4682 }
4683
4684 /**
4685  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4686  * @hw: pointer to the hw struct
4687  * @seid: seid of the VSI or switching component connected to Physical Port
4688  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4689  * @cmd_details: pointer to command details structure or NULL
4690  **/
4691 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4692                         u16 seid,
4693                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4694                         struct i40e_asq_cmd_details *cmd_details)
4695 {
4696         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4697                                     i40e_aqc_opc_query_port_ets_config,
4698                                     cmd_details);
4699 }
4700
4701 /**
4702  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4703  * @hw: pointer to the hw struct
4704  * @seid: seid of the switching component
4705  * @bw_data: Buffer to hold switching component's BW configuration
4706  * @cmd_details: pointer to command details structure or NULL
4707  **/
4708 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4709                 u16 seid,
4710                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4711                 struct i40e_asq_cmd_details *cmd_details)
4712 {
4713         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4714                                     i40e_aqc_opc_query_switching_comp_bw_config,
4715                                     cmd_details);
4716 }
4717
4718 /**
4719  * i40e_validate_filter_settings
4720  * @hw: pointer to the hardware structure
4721  * @settings: Filter control settings
4722  *
4723  * Check and validate the filter control settings passed.
4724  * The function checks for the valid filter/context sizes being
4725  * passed for FCoE and PE.
4726  *
4727  * Returns I40E_SUCCESS if the values passed are valid and within
4728  * range else returns an error.
4729  **/
4730 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4731                                 struct i40e_filter_control_settings *settings)
4732 {
4733         u32 fcoe_cntx_size, fcoe_filt_size;
4734         u32 pe_cntx_size, pe_filt_size;
4735         u32 fcoe_fmax;
4736
4737         u32 val;
4738
4739         /* Validate FCoE settings passed */
4740         switch (settings->fcoe_filt_num) {
4741         case I40E_HASH_FILTER_SIZE_1K:
4742         case I40E_HASH_FILTER_SIZE_2K:
4743         case I40E_HASH_FILTER_SIZE_4K:
4744         case I40E_HASH_FILTER_SIZE_8K:
4745         case I40E_HASH_FILTER_SIZE_16K:
4746         case I40E_HASH_FILTER_SIZE_32K:
4747                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4748                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4749                 break;
4750         default:
4751                 return I40E_ERR_PARAM;
4752         }
4753
4754         switch (settings->fcoe_cntx_num) {
4755         case I40E_DMA_CNTX_SIZE_512:
4756         case I40E_DMA_CNTX_SIZE_1K:
4757         case I40E_DMA_CNTX_SIZE_2K:
4758         case I40E_DMA_CNTX_SIZE_4K:
4759                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4760                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4761                 break;
4762         default:
4763                 return I40E_ERR_PARAM;
4764         }
4765
4766         /* Validate PE settings passed */
4767         switch (settings->pe_filt_num) {
4768         case I40E_HASH_FILTER_SIZE_1K:
4769         case I40E_HASH_FILTER_SIZE_2K:
4770         case I40E_HASH_FILTER_SIZE_4K:
4771         case I40E_HASH_FILTER_SIZE_8K:
4772         case I40E_HASH_FILTER_SIZE_16K:
4773         case I40E_HASH_FILTER_SIZE_32K:
4774         case I40E_HASH_FILTER_SIZE_64K:
4775         case I40E_HASH_FILTER_SIZE_128K:
4776         case I40E_HASH_FILTER_SIZE_256K:
4777         case I40E_HASH_FILTER_SIZE_512K:
4778         case I40E_HASH_FILTER_SIZE_1M:
4779                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4780                 pe_filt_size <<= (u32)settings->pe_filt_num;
4781                 break;
4782         default:
4783                 return I40E_ERR_PARAM;
4784         }
4785
4786         switch (settings->pe_cntx_num) {
4787         case I40E_DMA_CNTX_SIZE_512:
4788         case I40E_DMA_CNTX_SIZE_1K:
4789         case I40E_DMA_CNTX_SIZE_2K:
4790         case I40E_DMA_CNTX_SIZE_4K:
4791         case I40E_DMA_CNTX_SIZE_8K:
4792         case I40E_DMA_CNTX_SIZE_16K:
4793         case I40E_DMA_CNTX_SIZE_32K:
4794         case I40E_DMA_CNTX_SIZE_64K:
4795         case I40E_DMA_CNTX_SIZE_128K:
4796         case I40E_DMA_CNTX_SIZE_256K:
4797                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4798                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4799                 break;
4800         default:
4801                 return I40E_ERR_PARAM;
4802         }
4803
4804         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4805         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4806         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4807                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4808         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4809                 return I40E_ERR_INVALID_SIZE;
4810
4811         return I40E_SUCCESS;
4812 }
4813
4814 /**
4815  * i40e_set_filter_control
4816  * @hw: pointer to the hardware structure
4817  * @settings: Filter control settings
4818  *
4819  * Set the Queue Filters for PE/FCoE and enable filters required
4820  * for a single PF. It is expected that these settings are programmed
4821  * at the driver initialization time.
4822  **/
4823 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4824                                 struct i40e_filter_control_settings *settings)
4825 {
4826         enum i40e_status_code ret = I40E_SUCCESS;
4827         u32 hash_lut_size = 0;
4828         u32 val;
4829
4830         if (!settings)
4831                 return I40E_ERR_PARAM;
4832
4833         /* Validate the input settings */
4834         ret = i40e_validate_filter_settings(hw, settings);
4835         if (ret)
4836                 return ret;
4837
4838         /* Read the PF Queue Filter control register */
4839         val = rd32(hw, I40E_PFQF_CTL_0);
4840
4841         /* Program required PE hash buckets for the PF */
4842         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4843         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4844                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4845         /* Program required PE contexts for the PF */
4846         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4847         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4848                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4849
4850         /* Program required FCoE hash buckets for the PF */
4851         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4852         val |= ((u32)settings->fcoe_filt_num <<
4853                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4854                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4855         /* Program required FCoE DDP contexts for the PF */
4856         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4857         val |= ((u32)settings->fcoe_cntx_num <<
4858                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4859                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4860
4861         /* Program Hash LUT size for the PF */
4862         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4863         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4864                 hash_lut_size = 1;
4865         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4866                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4867
4868         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4869         if (settings->enable_fdir)
4870                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4871         if (settings->enable_ethtype)
4872                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4873         if (settings->enable_macvlan)
4874                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4875
4876         wr32(hw, I40E_PFQF_CTL_0, val);
4877
4878         return I40E_SUCCESS;
4879 }
4880
4881 /**
4882  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4883  * @hw: pointer to the hw struct
4884  * @mac_addr: MAC address to use in the filter
4885  * @ethtype: Ethertype to use in the filter
4886  * @flags: Flags that needs to be applied to the filter
4887  * @vsi_seid: seid of the control VSI
4888  * @queue: VSI queue number to send the packet to
4889  * @is_add: Add control packet filter if True else remove
4890  * @stats: Structure to hold information on control filter counts
4891  * @cmd_details: pointer to command details structure or NULL
4892  *
4893  * This command will Add or Remove control packet filter for a control VSI.
4894  * In return it will update the total number of perfect filter count in
4895  * the stats member.
4896  **/
4897 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4898                                 u8 *mac_addr, u16 ethtype, u16 flags,
4899                                 u16 vsi_seid, u16 queue, bool is_add,
4900                                 struct i40e_control_filter_stats *stats,
4901                                 struct i40e_asq_cmd_details *cmd_details)
4902 {
4903         struct i40e_aq_desc desc;
4904         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4905                 (struct i40e_aqc_add_remove_control_packet_filter *)
4906                 &desc.params.raw;
4907         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4908                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4909                 &desc.params.raw;
4910         enum i40e_status_code status;
4911
4912         if (vsi_seid == 0)
4913                 return I40E_ERR_PARAM;
4914
4915         if (is_add) {
4916                 i40e_fill_default_direct_cmd_desc(&desc,
4917                                 i40e_aqc_opc_add_control_packet_filter);
4918                 cmd->queue = CPU_TO_LE16(queue);
4919         } else {
4920                 i40e_fill_default_direct_cmd_desc(&desc,
4921                                 i40e_aqc_opc_remove_control_packet_filter);
4922         }
4923
4924         if (mac_addr)
4925                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4926                             I40E_NONDMA_TO_NONDMA);
4927
4928         cmd->etype = CPU_TO_LE16(ethtype);
4929         cmd->flags = CPU_TO_LE16(flags);
4930         cmd->seid = CPU_TO_LE16(vsi_seid);
4931
4932         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4933
4934         if (!status && stats) {
4935                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4936                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4937                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4938                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4939         }
4940
4941         return status;
4942 }
4943
4944 /**
4945  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4946  * @hw: pointer to the hw struct
4947  * @seid: VSI seid to add ethertype filter from
4948  **/
4949 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4950 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4951                                                     u16 seid)
4952 {
4953         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4954                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4955                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4956         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4957         enum i40e_status_code status;
4958
4959         status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
4960                                                        seid, 0, true, NULL,
4961                                                        NULL);
4962         if (status)
4963                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4964 }
4965
4966 /**
4967  * i40e_aq_add_cloud_filters
4968  * @hw: pointer to the hardware structure
4969  * @seid: VSI seid to add cloud filters from
4970  * @filters: Buffer which contains the filters to be added
4971  * @filter_count: number of filters contained in the buffer
4972  *
4973  * Set the cloud filters for a given VSI.  The contents of the
4974  * i40e_aqc_add_remove_cloud_filters_element_data are filled
4975  * in by the caller of the function.
4976  *
4977  **/
4978 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4979         u16 seid,
4980         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4981         u8 filter_count)
4982 {
4983         struct i40e_aq_desc desc;
4984         struct i40e_aqc_add_remove_cloud_filters *cmd =
4985         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4986         u16 buff_len;
4987         enum i40e_status_code status;
4988
4989         i40e_fill_default_direct_cmd_desc(&desc,
4990                                           i40e_aqc_opc_add_cloud_filters);
4991
4992         buff_len = filter_count * sizeof(*filters);
4993         desc.datalen = CPU_TO_LE16(buff_len);
4994         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4995         cmd->num_filters = filter_count;
4996         cmd->seid = CPU_TO_LE16(seid);
4997
4998         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4999
5000         return status;
5001 }
5002
5003 /**
5004  * i40e_aq_remove_cloud_filters
5005  * @hw: pointer to the hardware structure
5006  * @seid: VSI seid to remove cloud filters from
5007  * @filters: Buffer which contains the filters to be removed
5008  * @filter_count: number of filters contained in the buffer
5009  *
5010  * Remove the cloud filters for a given VSI.  The contents of the
5011  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5012  * in by the caller of the function.
5013  *
5014  **/
5015 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5016                 u16 seid,
5017                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5018                 u8 filter_count)
5019 {
5020         struct i40e_aq_desc desc;
5021         struct i40e_aqc_add_remove_cloud_filters *cmd =
5022         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5023         enum i40e_status_code status;
5024         u16 buff_len;
5025
5026         i40e_fill_default_direct_cmd_desc(&desc,
5027                                           i40e_aqc_opc_remove_cloud_filters);
5028
5029         buff_len = filter_count * sizeof(*filters);
5030         desc.datalen = CPU_TO_LE16(buff_len);
5031         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5032         cmd->num_filters = filter_count;
5033         cmd->seid = CPU_TO_LE16(seid);
5034
5035         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5036
5037         return status;
5038 }
5039
5040 /**
5041  * i40e_aq_alternate_write
5042  * @hw: pointer to the hardware structure
5043  * @reg_addr0: address of first dword to be read
5044  * @reg_val0: value to be written under 'reg_addr0'
5045  * @reg_addr1: address of second dword to be read
5046  * @reg_val1: value to be written under 'reg_addr1'
5047  *
5048  * Write one or two dwords to alternate structure. Fields are indicated
5049  * by 'reg_addr0' and 'reg_addr1' register numbers.
5050  *
5051  **/
5052 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5053                                 u32 reg_addr0, u32 reg_val0,
5054                                 u32 reg_addr1, u32 reg_val1)
5055 {
5056         struct i40e_aq_desc desc;
5057         struct i40e_aqc_alternate_write *cmd_resp =
5058                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5059         enum i40e_status_code status;
5060
5061         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5062         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5063         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5064         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5065         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5066
5067         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5068
5069         return status;
5070 }
5071
5072 /**
5073  * i40e_aq_alternate_write_indirect
5074  * @hw: pointer to the hardware structure
5075  * @addr: address of a first register to be modified
5076  * @dw_count: number of alternate structure fields to write
5077  * @buffer: pointer to the command buffer
5078  *
5079  * Write 'dw_count' dwords from 'buffer' to alternate structure
5080  * starting at 'addr'.
5081  *
5082  **/
5083 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5084                                 u32 addr, u32 dw_count, void *buffer)
5085 {
5086         struct i40e_aq_desc desc;
5087         struct i40e_aqc_alternate_ind_write *cmd_resp =
5088                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5089         enum i40e_status_code status;
5090
5091         if (buffer == NULL)
5092                 return I40E_ERR_PARAM;
5093
5094         /* Indirect command */
5095         i40e_fill_default_direct_cmd_desc(&desc,
5096                                          i40e_aqc_opc_alternate_write_indirect);
5097
5098         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5099         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5100         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5101                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5102
5103         cmd_resp->address = CPU_TO_LE32(addr);
5104         cmd_resp->length = CPU_TO_LE32(dw_count);
5105         cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
5106         cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5107
5108         status = i40e_asq_send_command(hw, &desc, buffer,
5109                                        I40E_LO_DWORD(4*dw_count), NULL);
5110
5111         return status;
5112 }
5113
5114 /**
5115  * i40e_aq_alternate_read
5116  * @hw: pointer to the hardware structure
5117  * @reg_addr0: address of first dword to be read
5118  * @reg_val0: pointer for data read from 'reg_addr0'
5119  * @reg_addr1: address of second dword to be read
5120  * @reg_val1: pointer for data read from 'reg_addr1'
5121  *
5122  * Read one or two dwords from alternate structure. Fields are indicated
5123  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5124  * is not passed then only register at 'reg_addr0' is read.
5125  *
5126  **/
5127 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5128                                 u32 reg_addr0, u32 *reg_val0,
5129                                 u32 reg_addr1, u32 *reg_val1)
5130 {
5131         struct i40e_aq_desc desc;
5132         struct i40e_aqc_alternate_write *cmd_resp =
5133                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5134         enum i40e_status_code status;
5135
5136         if (reg_val0 == NULL)
5137                 return I40E_ERR_PARAM;
5138
5139         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5140         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5141         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5142
5143         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5144
5145         if (status == I40E_SUCCESS) {
5146                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5147
5148                 if (reg_val1 != NULL)
5149                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5150         }
5151
5152         return status;
5153 }
5154
5155 /**
5156  * i40e_aq_alternate_read_indirect
5157  * @hw: pointer to the hardware structure
5158  * @addr: address of the alternate structure field
5159  * @dw_count: number of alternate structure fields to read
5160  * @buffer: pointer to the command buffer
5161  *
5162  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5163  * place them in 'buffer'. The buffer should be allocated by caller.
5164  *
5165  **/
5166 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5167                                 u32 addr, u32 dw_count, void *buffer)
5168 {
5169         struct i40e_aq_desc desc;
5170         struct i40e_aqc_alternate_ind_write *cmd_resp =
5171                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5172         enum i40e_status_code status;
5173
5174         if (buffer == NULL)
5175                 return I40E_ERR_PARAM;
5176
5177         /* Indirect command */
5178         i40e_fill_default_direct_cmd_desc(&desc,
5179                 i40e_aqc_opc_alternate_read_indirect);
5180
5181         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5182         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5183         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5184                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5185
5186         cmd_resp->address = CPU_TO_LE32(addr);
5187         cmd_resp->length = CPU_TO_LE32(dw_count);
5188         cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
5189         cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5190
5191         status = i40e_asq_send_command(hw, &desc, buffer,
5192                                        I40E_LO_DWORD(4*dw_count), NULL);
5193
5194         return status;
5195 }
5196
5197 /**
5198  *  i40e_aq_alternate_clear
5199  *  @hw: pointer to the HW structure.
5200  *
5201  *  Clear the alternate structures of the port from which the function
5202  *  is called.
5203  *
5204  **/
5205 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5206 {
5207         struct i40e_aq_desc desc;
5208         enum i40e_status_code status;
5209
5210         i40e_fill_default_direct_cmd_desc(&desc,
5211                                           i40e_aqc_opc_alternate_clear_port);
5212
5213         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5214
5215         return status;
5216 }
5217
5218 /**
5219  *  i40e_aq_alternate_write_done
5220  *  @hw: pointer to the HW structure.
5221  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5222  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5223  *
5224  *  Indicates to the FW that alternate structures have been changed.
5225  *
5226  **/
5227 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5228                 u8 bios_mode, bool *reset_needed)
5229 {
5230         struct i40e_aq_desc desc;
5231         struct i40e_aqc_alternate_write_done *cmd =
5232                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5233         enum i40e_status_code status;
5234
5235         if (reset_needed == NULL)
5236                 return I40E_ERR_PARAM;
5237
5238         i40e_fill_default_direct_cmd_desc(&desc,
5239                                           i40e_aqc_opc_alternate_write_done);
5240
5241         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5242
5243         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5244         if (!status && reset_needed)
5245                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5246                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5247
5248         return status;
5249 }
5250
5251 /**
5252  *  i40e_aq_set_oem_mode
5253  *  @hw: pointer to the HW structure.
5254  *  @oem_mode: the OEM mode to be used
5255  *
5256  *  Sets the device to a specific operating mode. Currently the only supported
5257  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5258  *
5259  **/
5260 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5261                 u8 oem_mode)
5262 {
5263         struct i40e_aq_desc desc;
5264         struct i40e_aqc_alternate_write_done *cmd =
5265                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5266         enum i40e_status_code status;
5267
5268         i40e_fill_default_direct_cmd_desc(&desc,
5269                                           i40e_aqc_opc_alternate_set_mode);
5270
5271         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5272
5273         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5274
5275         return status;
5276 }
5277
5278 /**
5279  * i40e_aq_resume_port_tx
5280  * @hw: pointer to the hardware structure
5281  * @cmd_details: pointer to command details structure or NULL
5282  *
5283  * Resume port's Tx traffic
5284  **/
5285 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5286                                 struct i40e_asq_cmd_details *cmd_details)
5287 {
5288         struct i40e_aq_desc desc;
5289         enum i40e_status_code status;
5290
5291         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5292
5293         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5294
5295         return status;
5296 }
5297
5298 /**
5299  * i40e_set_pci_config_data - store PCI bus info
5300  * @hw: pointer to hardware structure
5301  * @link_status: the link status word from PCI config space
5302  *
5303  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5304  **/
5305 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5306 {
5307         hw->bus.type = i40e_bus_type_pci_express;
5308
5309         switch (link_status & I40E_PCI_LINK_WIDTH) {
5310         case I40E_PCI_LINK_WIDTH_1:
5311                 hw->bus.width = i40e_bus_width_pcie_x1;
5312                 break;
5313         case I40E_PCI_LINK_WIDTH_2:
5314                 hw->bus.width = i40e_bus_width_pcie_x2;
5315                 break;
5316         case I40E_PCI_LINK_WIDTH_4:
5317                 hw->bus.width = i40e_bus_width_pcie_x4;
5318                 break;
5319         case I40E_PCI_LINK_WIDTH_8:
5320                 hw->bus.width = i40e_bus_width_pcie_x8;
5321                 break;
5322         default:
5323                 hw->bus.width = i40e_bus_width_unknown;
5324                 break;
5325         }
5326
5327         switch (link_status & I40E_PCI_LINK_SPEED) {
5328         case I40E_PCI_LINK_SPEED_2500:
5329                 hw->bus.speed = i40e_bus_speed_2500;
5330                 break;
5331         case I40E_PCI_LINK_SPEED_5000:
5332                 hw->bus.speed = i40e_bus_speed_5000;
5333                 break;
5334         case I40E_PCI_LINK_SPEED_8000:
5335                 hw->bus.speed = i40e_bus_speed_8000;
5336                 break;
5337         default:
5338                 hw->bus.speed = i40e_bus_speed_unknown;
5339                 break;
5340         }
5341 }
5342
5343 /**
5344  * i40e_aq_debug_dump
5345  * @hw: pointer to the hardware structure
5346  * @cluster_id: specific cluster to dump
5347  * @table_id: table id within cluster
5348  * @start_index: index of line in the block to read
5349  * @buff_size: dump buffer size
5350  * @buff: dump buffer
5351  * @ret_buff_size: actual buffer size returned
5352  * @ret_next_table: next block to read
5353  * @ret_next_index: next index to read
5354  *
5355  * Dump internal FW/HW data for debug purposes.
5356  *
5357  **/
5358 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5359                                 u8 table_id, u32 start_index, u16 buff_size,
5360                                 void *buff, u16 *ret_buff_size,
5361                                 u8 *ret_next_table, u32 *ret_next_index,
5362                                 struct i40e_asq_cmd_details *cmd_details)
5363 {
5364         struct i40e_aq_desc desc;
5365         struct i40e_aqc_debug_dump_internals *cmd =
5366                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5367         struct i40e_aqc_debug_dump_internals *resp =
5368                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5369         enum i40e_status_code status;
5370
5371         if (buff_size == 0 || !buff)
5372                 return I40E_ERR_PARAM;
5373
5374         i40e_fill_default_direct_cmd_desc(&desc,
5375                                           i40e_aqc_opc_debug_dump_internals);
5376         /* Indirect Command */
5377         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5378         if (buff_size > I40E_AQ_LARGE_BUF)
5379                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5380
5381         cmd->cluster_id = cluster_id;
5382         cmd->table_id = table_id;
5383         cmd->idx = CPU_TO_LE32(start_index);
5384
5385         desc.datalen = CPU_TO_LE16(buff_size);
5386
5387         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5388         if (!status) {
5389                 if (ret_buff_size != NULL)
5390                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5391                 if (ret_next_table != NULL)
5392                         *ret_next_table = resp->table_id;
5393                 if (ret_next_index != NULL)
5394                         *ret_next_index = LE32_TO_CPU(resp->idx);
5395         }
5396
5397         return status;
5398 }
5399
5400 /**
5401  * i40e_read_bw_from_alt_ram
5402  * @hw: pointer to the hardware structure
5403  * @max_bw: pointer for max_bw read
5404  * @min_bw: pointer for min_bw read
5405  * @min_valid: pointer for bool that is true if min_bw is a valid value
5406  * @max_valid: pointer for bool that is true if max_bw is a valid value
5407  *
5408  * Read bw from the alternate ram for the given pf
5409  **/
5410 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5411                                         u32 *max_bw, u32 *min_bw,
5412                                         bool *min_valid, bool *max_valid)
5413 {
5414         enum i40e_status_code status;
5415         u32 max_bw_addr, min_bw_addr;
5416
5417         /* Calculate the address of the min/max bw registers */
5418         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5419                 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5420                 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5421         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5422                 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5423                 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5424
5425         /* Read the bandwidths from alt ram */
5426         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5427                                         min_bw_addr, min_bw);
5428
5429         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5430                 *min_valid = true;
5431         else
5432                 *min_valid = false;
5433
5434         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5435                 *max_valid = true;
5436         else
5437                 *max_valid = false;
5438
5439         return status;
5440 }
5441
5442 /**
5443  * i40e_aq_configure_partition_bw
5444  * @hw: pointer to the hardware structure
5445  * @bw_data: Buffer holding valid pfs and bw limits
5446  * @cmd_details: pointer to command details
5447  *
5448  * Configure partitions guaranteed/max bw
5449  **/
5450 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5451                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5452                         struct i40e_asq_cmd_details *cmd_details)
5453 {
5454         enum i40e_status_code status;
5455         struct i40e_aq_desc desc;
5456         u16 bwd_size = sizeof(*bw_data);
5457
5458         i40e_fill_default_direct_cmd_desc(&desc,
5459                                 i40e_aqc_opc_configure_partition_bw);
5460
5461         /* Indirect command */
5462         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5463         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5464
5465         if (bwd_size > I40E_AQ_LARGE_BUF)
5466                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5467
5468         desc.datalen = CPU_TO_LE16(bwd_size);
5469
5470         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5471
5472         return status;
5473 }
5474 #endif /* PF_DRIVER */
5475 #ifdef VF_DRIVER
5476
5477 /**
5478  * i40e_aq_send_msg_to_pf
5479  * @hw: pointer to the hardware structure
5480  * @v_opcode: opcodes for VF-PF communication
5481  * @v_retval: return error code
5482  * @msg: pointer to the msg buffer
5483  * @msglen: msg length
5484  * @cmd_details: pointer to command details
5485  *
5486  * Send message to PF driver using admin queue. By default, this message
5487  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5488  * completion before returning.
5489  **/
5490 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5491                                 enum i40e_virtchnl_ops v_opcode,
5492                                 enum i40e_status_code v_retval,
5493                                 u8 *msg, u16 msglen,
5494                                 struct i40e_asq_cmd_details *cmd_details)
5495 {
5496         struct i40e_aq_desc desc;
5497         struct i40e_asq_cmd_details details;
5498         enum i40e_status_code status;
5499
5500         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5501         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5502         desc.cookie_high = CPU_TO_LE32(v_opcode);
5503         desc.cookie_low = CPU_TO_LE32(v_retval);
5504         if (msglen) {
5505                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5506                                                 | I40E_AQ_FLAG_RD));
5507                 if (msglen > I40E_AQ_LARGE_BUF)
5508                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5509                 desc.datalen = CPU_TO_LE16(msglen);
5510         }
5511         if (!cmd_details) {
5512                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5513                 details.async = true;
5514                 cmd_details = &details;
5515         }
5516         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5517                                        msglen, cmd_details);
5518         return status;
5519 }
5520
5521 /**
5522  * i40e_vf_parse_hw_config
5523  * @hw: pointer to the hardware structure
5524  * @msg: pointer to the virtual channel VF resource structure
5525  *
5526  * Given a VF resource message from the PF, populate the hw struct
5527  * with appropriate information.
5528  **/
5529 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5530                              struct i40e_virtchnl_vf_resource *msg)
5531 {
5532         struct i40e_virtchnl_vsi_resource *vsi_res;
5533         int i;
5534
5535         vsi_res = &msg->vsi_res[0];
5536
5537         hw->dev_caps.num_vsis = msg->num_vsis;
5538         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5539         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5540         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5541         hw->dev_caps.dcb = msg->vf_offload_flags &
5542                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
5543         hw->dev_caps.fcoe = (msg->vf_offload_flags &
5544                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5545         hw->dev_caps.iwarp = (msg->vf_offload_flags &
5546                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5547         for (i = 0; i < msg->num_vsis; i++) {
5548                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5549                         i40e_memcpy(hw->mac.perm_addr,
5550                                     vsi_res->default_mac_addr,
5551                                     I40E_ETH_LENGTH_OF_ADDRESS,
5552                                     I40E_NONDMA_TO_NONDMA);
5553                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5554                                     I40E_ETH_LENGTH_OF_ADDRESS,
5555                                     I40E_NONDMA_TO_NONDMA);
5556                 }
5557                 vsi_res++;
5558         }
5559 }
5560
5561 /**
5562  * i40e_vf_reset
5563  * @hw: pointer to the hardware structure
5564  *
5565  * Send a VF_RESET message to the PF. Does not wait for response from PF
5566  * as none will be forthcoming. Immediately after calling this function,
5567  * the admin queue should be shut down and (optionally) reinitialized.
5568  **/
5569 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5570 {
5571         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5572                                       I40E_SUCCESS, NULL, 0, NULL);
5573 }
5574 #endif /* VF_DRIVER */