drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                 case I40E_DEV_ID_ADAPTIVE_VF:
  97                         hw->mac.type = I40E_MAC_VF;
  98                         break;
  99 #endif
 100                 default:
 101                         hw->mac.type = I40E_MAC_GENERIC;
 102                         break;
 103                 }
 104         } else {
 105                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 106         }
 107
 108         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 109                   hw->mac.type, status);
 110         return status;
 111 }
 112
 113 /**
 114  * i40e_aq_str - convert AQ err code to a string
 115  * @hw: pointer to the HW structure
 116  * @aq_err: the AQ error code to convert
 117  **/
 118 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 119 {
 120         switch (aq_err) {
 121         case I40E_AQ_RC_OK:
 122                 return "OK";
 123         case I40E_AQ_RC_EPERM:
 124                 return "I40E_AQ_RC_EPERM";
 125         case I40E_AQ_RC_ENOENT:
 126                 return "I40E_AQ_RC_ENOENT";
 127         case I40E_AQ_RC_ESRCH:
 128                 return "I40E_AQ_RC_ESRCH";
 129         case I40E_AQ_RC_EINTR:
 130                 return "I40E_AQ_RC_EINTR";
 131         case I40E_AQ_RC_EIO:
 132                 return "I40E_AQ_RC_EIO";
 133         case I40E_AQ_RC_ENXIO:
 134                 return "I40E_AQ_RC_ENXIO";
 135         case I40E_AQ_RC_E2BIG:
 136                 return "I40E_AQ_RC_E2BIG";
 137         case I40E_AQ_RC_EAGAIN:
 138                 return "I40E_AQ_RC_EAGAIN";
 139         case I40E_AQ_RC_ENOMEM:
 140                 return "I40E_AQ_RC_ENOMEM";
 141         case I40E_AQ_RC_EACCES:
 142                 return "I40E_AQ_RC_EACCES";
 143         case I40E_AQ_RC_EFAULT:
 144                 return "I40E_AQ_RC_EFAULT";
 145         case I40E_AQ_RC_EBUSY:
 146                 return "I40E_AQ_RC_EBUSY";
 147         case I40E_AQ_RC_EEXIST:
 148                 return "I40E_AQ_RC_EEXIST";
 149         case I40E_AQ_RC_EINVAL:
 150                 return "I40E_AQ_RC_EINVAL";
 151         case I40E_AQ_RC_ENOTTY:
 152                 return "I40E_AQ_RC_ENOTTY";
 153         case I40E_AQ_RC_ENOSPC:
 154                 return "I40E_AQ_RC_ENOSPC";
 155         case I40E_AQ_RC_ENOSYS:
 156                 return "I40E_AQ_RC_ENOSYS";
 157         case I40E_AQ_RC_ERANGE:
 158                 return "I40E_AQ_RC_ERANGE";
 159         case I40E_AQ_RC_EFLUSHED:
 160                 return "I40E_AQ_RC_EFLUSHED";
 161         case I40E_AQ_RC_BAD_ADDR:
 162                 return "I40E_AQ_RC_BAD_ADDR";
 163         case I40E_AQ_RC_EMODE:
 164                 return "I40E_AQ_RC_EMODE";
 165         case I40E_AQ_RC_EFBIG:
 166                 return "I40E_AQ_RC_EFBIG";
 167         }
 168
 169         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 170         return hw->err_str;
 171 }
 172
 173 /**
 174  * i40e_stat_str - convert status err code to a string
 175  * @hw: pointer to the HW structure
 176  * @stat_err: the status error code to convert
 177  **/
 178 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 179 {
 180         switch (stat_err) {
 181         case I40E_SUCCESS:
 182                 return "OK";
 183         case I40E_ERR_NVM:
 184                 return "I40E_ERR_NVM";
 185         case I40E_ERR_NVM_CHECKSUM:
 186                 return "I40E_ERR_NVM_CHECKSUM";
 187         case I40E_ERR_PHY:
 188                 return "I40E_ERR_PHY";
 189         case I40E_ERR_CONFIG:
 190                 return "I40E_ERR_CONFIG";
 191         case I40E_ERR_PARAM:
 192                 return "I40E_ERR_PARAM";
 193         case I40E_ERR_MAC_TYPE:
 194                 return "I40E_ERR_MAC_TYPE";
 195         case I40E_ERR_UNKNOWN_PHY:
 196                 return "I40E_ERR_UNKNOWN_PHY";
 197         case I40E_ERR_LINK_SETUP:
 198                 return "I40E_ERR_LINK_SETUP";
 199         case I40E_ERR_ADAPTER_STOPPED:
 200                 return "I40E_ERR_ADAPTER_STOPPED";
 201         case I40E_ERR_INVALID_MAC_ADDR:
 202                 return "I40E_ERR_INVALID_MAC_ADDR";
 203         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 204                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 205         case I40E_ERR_MASTER_REQUESTS_PENDING:
 206                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 207         case I40E_ERR_INVALID_LINK_SETTINGS:
 208                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 209         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 210                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 211         case I40E_ERR_RESET_FAILED:
 212                 return "I40E_ERR_RESET_FAILED";
 213         case I40E_ERR_SWFW_SYNC:
 214                 return "I40E_ERR_SWFW_SYNC";
 215         case I40E_ERR_NO_AVAILABLE_VSI:
 216                 return "I40E_ERR_NO_AVAILABLE_VSI";
 217         case I40E_ERR_NO_MEMORY:
 218                 return "I40E_ERR_NO_MEMORY";
 219         case I40E_ERR_BAD_PTR:
 220                 return "I40E_ERR_BAD_PTR";
 221         case I40E_ERR_RING_FULL:
 222                 return "I40E_ERR_RING_FULL";
 223         case I40E_ERR_INVALID_PD_ID:
 224                 return "I40E_ERR_INVALID_PD_ID";
 225         case I40E_ERR_INVALID_QP_ID:
 226                 return "I40E_ERR_INVALID_QP_ID";
 227         case I40E_ERR_INVALID_CQ_ID:
 228                 return "I40E_ERR_INVALID_CQ_ID";
 229         case I40E_ERR_INVALID_CEQ_ID:
 230                 return "I40E_ERR_INVALID_CEQ_ID";
 231         case I40E_ERR_INVALID_AEQ_ID:
 232                 return "I40E_ERR_INVALID_AEQ_ID";
 233         case I40E_ERR_INVALID_SIZE:
 234                 return "I40E_ERR_INVALID_SIZE";
 235         case I40E_ERR_INVALID_ARP_INDEX:
 236                 return "I40E_ERR_INVALID_ARP_INDEX";
 237         case I40E_ERR_INVALID_FPM_FUNC_ID:
 238                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 239         case I40E_ERR_QP_INVALID_MSG_SIZE:
 240                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 241         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 242                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 243         case I40E_ERR_INVALID_FRAG_COUNT:
 244                 return "I40E_ERR_INVALID_FRAG_COUNT";
 245         case I40E_ERR_QUEUE_EMPTY:
 246                 return "I40E_ERR_QUEUE_EMPTY";
 247         case I40E_ERR_INVALID_ALIGNMENT:
 248                 return "I40E_ERR_INVALID_ALIGNMENT";
 249         case I40E_ERR_FLUSHED_QUEUE:
 250                 return "I40E_ERR_FLUSHED_QUEUE";
 251         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 252                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 253         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 254                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 255         case I40E_ERR_TIMEOUT:
 256                 return "I40E_ERR_TIMEOUT";
 257         case I40E_ERR_OPCODE_MISMATCH:
 258                 return "I40E_ERR_OPCODE_MISMATCH";
 259         case I40E_ERR_CQP_COMPL_ERROR:
 260                 return "I40E_ERR_CQP_COMPL_ERROR";
 261         case I40E_ERR_INVALID_VF_ID:
 262                 return "I40E_ERR_INVALID_VF_ID";
 263         case I40E_ERR_INVALID_HMCFN_ID:
 264                 return "I40E_ERR_INVALID_HMCFN_ID";
 265         case I40E_ERR_BACKING_PAGE_ERROR:
 266                 return "I40E_ERR_BACKING_PAGE_ERROR";
 267         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 268                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 269         case I40E_ERR_INVALID_PBLE_INDEX:
 270                 return "I40E_ERR_INVALID_PBLE_INDEX";
 271         case I40E_ERR_INVALID_SD_INDEX:
 272                 return "I40E_ERR_INVALID_SD_INDEX";
 273         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 274                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 275         case I40E_ERR_INVALID_SD_TYPE:
 276                 return "I40E_ERR_INVALID_SD_TYPE";
 277         case I40E_ERR_MEMCPY_FAILED:
 278                 return "I40E_ERR_MEMCPY_FAILED";
 279         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 280                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 281         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 283         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 284                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 285         case I40E_ERR_SRQ_ENABLED:
 286                 return "I40E_ERR_SRQ_ENABLED";
 287         case I40E_ERR_ADMIN_QUEUE_ERROR:
 288                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 289         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 290                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 291         case I40E_ERR_BUF_TOO_SHORT:
 292                 return "I40E_ERR_BUF_TOO_SHORT";
 293         case I40E_ERR_ADMIN_QUEUE_FULL:
 294                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 295         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 296                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 297         case I40E_ERR_BAD_IWARP_CQE:
 298                 return "I40E_ERR_BAD_IWARP_CQE";
 299         case I40E_ERR_NVM_BLANK_MODE:
 300                 return "I40E_ERR_NVM_BLANK_MODE";
 301         case I40E_ERR_NOT_IMPLEMENTED:
 302                 return "I40E_ERR_NOT_IMPLEMENTED";
 303         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 304                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 305         case I40E_ERR_DIAG_TEST_FAILED:
 306                 return "I40E_ERR_DIAG_TEST_FAILED";
 307         case I40E_ERR_NOT_READY:
 308                 return "I40E_ERR_NOT_READY";
 309         case I40E_NOT_SUPPORTED:
 310                 return "I40E_NOT_SUPPORTED";
 311         case I40E_ERR_FIRMWARE_API_VERSION:
 312                 return "I40E_ERR_FIRMWARE_API_VERSION";
 313         }
 314
 315         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 316         return hw->err_str;
 317 }
 318
 319 /**
 320  * i40e_debug_aq
 321  * @hw: debug mask related to admin queue
 322  * @mask: debug mask
 323  * @desc: pointer to admin queue descriptor
 324  * @buffer: pointer to command buffer
 325  * @buf_len: max length of buffer
 326  *
 327  * Dumps debug log about adminq command with descriptor contents.
 328  **/
 329 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 330                    void *buffer, u16 buf_len)
 331 {
 332         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 333         u8 *buf = (u8 *)buffer;
 334         u16 len;
 335         u16 i = 0;
 336
 337         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 338                 return;
 339
 340         len = LE16_TO_CPU(aq_desc->datalen);
 341
 342         i40e_debug(hw, mask,
 343                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 344                    LE16_TO_CPU(aq_desc->opcode),
 345                    LE16_TO_CPU(aq_desc->flags),
 346                    LE16_TO_CPU(aq_desc->datalen),
 347                    LE16_TO_CPU(aq_desc->retval));
 348         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->cookie_high),
 350                    LE32_TO_CPU(aq_desc->cookie_low));
 351         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.internal.param0),
 353                    LE32_TO_CPU(aq_desc->params.internal.param1));
 354         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 355                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 356                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 357
 358         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 359                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 360                 if (buf_len < len)
 361                         len = buf_len;
 362                 /* write the full 16-byte chunks */
 363                 for (i = 0; i < (len - 16); i += 16)
 364                         i40e_debug(hw, mask,
 365                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 366                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 367                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 368                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 369                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 370                 /* the most we could have left is 16 bytes, pad with zeros */
 371                 if (i < len) {
 372                         char d_buf[16];
 373                         int j, i_sav;
 374
 375                         i_sav = i;
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446
 447 /**
 448  * i40e_aq_get_set_rss_lut
 449  * @hw: pointer to the hardware structure
 450  * @vsi_id: vsi fw index
 451  * @pf_lut: for PF table set true, for VSI table set false
 452  * @lut: pointer to the lut buffer provided by the caller
 453  * @lut_size: size of the lut buffer
 454  * @set: set true to set the table, false to get the table
 455  *
 456  * Internal function to get or set RSS look up table
 457  **/
 458 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 459                                                      u16 vsi_id, bool pf_lut,
 460                                                      u8 *lut, u16 lut_size,
 461                                                      bool set)
 462 {
 463         enum i40e_status_code status;
 464         struct i40e_aq_desc desc;
 465         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 466                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 467
 468         if (set)
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_set_rss_lut);
 471         else
 472                 i40e_fill_default_direct_cmd_desc(&desc,
 473                                                   i40e_aqc_opc_get_rss_lut);
 474
 475         /* Indirect command */
 476         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 478
 479         cmd_resp->vsi_id =
 480                         CPU_TO_LE16((u16)((vsi_id <<
 481                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 483         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 484
 485         if (pf_lut)
 486                 cmd_resp->flags |= CPU_TO_LE16((u16)
 487                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 488                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 490         else
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495
 496         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 497
 498         return status;
 499 }
 500
 501 /**
 502  * i40e_aq_get_rss_lut
 503  * @hw: pointer to the hardware structure
 504  * @vsi_id: vsi fw index
 505  * @pf_lut: for PF table set true, for VSI table set false
 506  * @lut: pointer to the lut buffer provided by the caller
 507  * @lut_size: size of the lut buffer
 508  *
 509  * get the RSS lookup table, PF or VSI type
 510  **/
 511 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 512                                           bool pf_lut, u8 *lut, u16 lut_size)
 513 {
 514         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 515                                        false);
 516 }
 517
 518 /**
 519  * i40e_aq_set_rss_lut
 520  * @hw: pointer to the hardware structure
 521  * @vsi_id: vsi fw index
 522  * @pf_lut: for PF table set true, for VSI table set false
 523  * @lut: pointer to the lut buffer provided by the caller
 524  * @lut_size: size of the lut buffer
 525  *
 526  * set the RSS lookup table, PF or VSI type
 527  **/
 528 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 529                                           bool pf_lut, u8 *lut, u16 lut_size)
 530 {
 531         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 532 }
 533
 534 /**
 535  * i40e_aq_get_set_rss_key
 536  * @hw: pointer to the hw struct
 537  * @vsi_id: vsi fw index
 538  * @key: pointer to key info struct
 539  * @set: set true to set the key, false to get the key
 540  *
 541  * get the RSS key per VSI
 542  **/
 543 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 544                                       u16 vsi_id,
 545                                       struct i40e_aqc_get_set_rss_key_data *key,
 546                                       bool set)
 547 {
 548         enum i40e_status_code status;
 549         struct i40e_aq_desc desc;
 550         struct i40e_aqc_get_set_rss_key *cmd_resp =
 551                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 552         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 553
 554         if (set)
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_set_rss_key);
 557         else
 558                 i40e_fill_default_direct_cmd_desc(&desc,
 559                                                   i40e_aqc_opc_get_rss_key);
 560
 561         /* Indirect command */
 562         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 564
 565         cmd_resp->vsi_id =
 566                         CPU_TO_LE16((u16)((vsi_id <<
 567                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 569         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 570
 571         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 572
 573         return status;
 574 }
 575
 576 /**
 577  * i40e_aq_get_rss_key
 578  * @hw: pointer to the hw struct
 579  * @vsi_id: vsi fw index
 580  * @key: pointer to key info struct
 581  *
 582  **/
 583 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 584                                       u16 vsi_id,
 585                                       struct i40e_aqc_get_set_rss_key_data *key)
 586 {
 587         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 588 }
 589
 590 /**
 591  * i40e_aq_set_rss_key
 592  * @hw: pointer to the hw struct
 593  * @vsi_id: vsi fw index
 594  * @key: pointer to key info struct
 595  *
 596  * set the RSS key per VSI
 597  **/
 598 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 599                                       u16 vsi_id,
 600                                       struct i40e_aqc_get_set_rss_key_data *key)
 601 {
 602         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 603 }
 604
 605 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 606  * hardware to a bit-field that can be used by SW to more easily determine the
 607  * packet type.
 608  *
 609  * Macros are used to shorten the table lines and make this table human
 610  * readable.
 611  *
 612  * We store the PTYPE in the top byte of the bit field - this is just so that
 613  * we can check that the table doesn't have a row missing, as the index into
 614  * the table should be the PTYPE.
 615  *
 616  * Typical work flow:
 617  *
 618  * IF NOT i40e_ptype_lookup[ptype].known
 619  * THEN
 620  *      Packet is unknown
 621  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 622  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 623  * ELSE
 624  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 625  * ENDIF
 626  */
 627
 628 /* macro to make the table lines short */
 629 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 630         {       PTYPE, \
 631                 1, \
 632                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 633                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 634                 I40E_RX_PTYPE_##OUTER_FRAG, \
 635                 I40E_RX_PTYPE_TUNNEL_##T, \
 636                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 637                 I40E_RX_PTYPE_##TEF, \
 638                 I40E_RX_PTYPE_INNER_PROT_##I, \
 639                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 640
 641 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 642                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 643
 644 /* shorter macros makes the table fit but are terse */
 645 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 646 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 647 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 648
 649 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 650 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 651         /* L2 Packet types */
 652         I40E_PTT_UNUSED_ENTRY(0),
 653         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 654         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 655         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT_UNUSED_ENTRY(4),
 657         I40E_PTT_UNUSED_ENTRY(5),
 658         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 659         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT_UNUSED_ENTRY(8),
 661         I40E_PTT_UNUSED_ENTRY(9),
 662         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 663         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 664         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674
 675         /* Non Tunneled IPv4 */
 676         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 679         I40E_PTT_UNUSED_ENTRY(25),
 680         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 681         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 682         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 683
 684         /* IPv4 --> IPv4 */
 685         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 686         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 687         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 688         I40E_PTT_UNUSED_ENTRY(32),
 689         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 690         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 691         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 692
 693         /* IPv4 --> IPv6 */
 694         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 695         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 696         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 697         I40E_PTT_UNUSED_ENTRY(39),
 698         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 699         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 700         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 701
 702         /* IPv4 --> GRE/NAT */
 703         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 704
 705         /* IPv4 --> GRE/NAT --> IPv4 */
 706         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 707         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 708         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 709         I40E_PTT_UNUSED_ENTRY(47),
 710         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 711         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 712         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 713
 714         /* IPv4 --> GRE/NAT --> IPv6 */
 715         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 716         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 717         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 718         I40E_PTT_UNUSED_ENTRY(54),
 719         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 720         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 721         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 722
 723         /* IPv4 --> GRE/NAT --> MAC */
 724         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 725
 726         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 727         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 728         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 729         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 730         I40E_PTT_UNUSED_ENTRY(62),
 731         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 732         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 733         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 734
 735         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 736         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 737         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 738         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 739         I40E_PTT_UNUSED_ENTRY(69),
 740         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 741         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 742         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 743
 744         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 745         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 746
 747         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 748         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(77),
 752         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 757         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(84),
 761         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 764
 765         /* Non Tunneled IPv6 */
 766         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 767         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 768         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 769         I40E_PTT_UNUSED_ENTRY(91),
 770         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 771         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 772         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 773
 774         /* IPv6 --> IPv4 */
 775         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 776         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 777         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 778         I40E_PTT_UNUSED_ENTRY(98),
 779         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 780         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 781         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 782
 783         /* IPv6 --> IPv6 */
 784         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 785         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 786         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 787         I40E_PTT_UNUSED_ENTRY(105),
 788         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 789         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 790         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 791
 792         /* IPv6 --> GRE/NAT */
 793         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 794
 795         /* IPv6 --> GRE/NAT -> IPv4 */
 796         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 797         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 798         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 799         I40E_PTT_UNUSED_ENTRY(113),
 800         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 801         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 802         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 803
 804         /* IPv6 --> GRE/NAT -> IPv6 */
 805         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 806         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 807         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 808         I40E_PTT_UNUSED_ENTRY(120),
 809         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 810         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 811         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 812
 813         /* IPv6 --> GRE/NAT -> MAC */
 814         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 815
 816         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 817         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 818         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 819         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 820         I40E_PTT_UNUSED_ENTRY(128),
 821         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 822         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 823         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 824
 825         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 826         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 827         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 828         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 829         I40E_PTT_UNUSED_ENTRY(135),
 830         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 831         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 832         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 835         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 836
 837         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 838         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 839         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 840         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 841         I40E_PTT_UNUSED_ENTRY(143),
 842         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 843         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 844         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 845
 846         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 847         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 848         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 849         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 850         I40E_PTT_UNUSED_ENTRY(150),
 851         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 852         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 853         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 854
 855         /* unused entries */
 856         I40E_PTT_UNUSED_ENTRY(154),
 857         I40E_PTT_UNUSED_ENTRY(155),
 858         I40E_PTT_UNUSED_ENTRY(156),
 859         I40E_PTT_UNUSED_ENTRY(157),
 860         I40E_PTT_UNUSED_ENTRY(158),
 861         I40E_PTT_UNUSED_ENTRY(159),
 862
 863         I40E_PTT_UNUSED_ENTRY(160),
 864         I40E_PTT_UNUSED_ENTRY(161),
 865         I40E_PTT_UNUSED_ENTRY(162),
 866         I40E_PTT_UNUSED_ENTRY(163),
 867         I40E_PTT_UNUSED_ENTRY(164),
 868         I40E_PTT_UNUSED_ENTRY(165),
 869         I40E_PTT_UNUSED_ENTRY(166),
 870         I40E_PTT_UNUSED_ENTRY(167),
 871         I40E_PTT_UNUSED_ENTRY(168),
 872         I40E_PTT_UNUSED_ENTRY(169),
 873
 874         I40E_PTT_UNUSED_ENTRY(170),
 875         I40E_PTT_UNUSED_ENTRY(171),
 876         I40E_PTT_UNUSED_ENTRY(172),
 877         I40E_PTT_UNUSED_ENTRY(173),
 878         I40E_PTT_UNUSED_ENTRY(174),
 879         I40E_PTT_UNUSED_ENTRY(175),
 880         I40E_PTT_UNUSED_ENTRY(176),
 881         I40E_PTT_UNUSED_ENTRY(177),
 882         I40E_PTT_UNUSED_ENTRY(178),
 883         I40E_PTT_UNUSED_ENTRY(179),
 884
 885         I40E_PTT_UNUSED_ENTRY(180),
 886         I40E_PTT_UNUSED_ENTRY(181),
 887         I40E_PTT_UNUSED_ENTRY(182),
 888         I40E_PTT_UNUSED_ENTRY(183),
 889         I40E_PTT_UNUSED_ENTRY(184),
 890         I40E_PTT_UNUSED_ENTRY(185),
 891         I40E_PTT_UNUSED_ENTRY(186),
 892         I40E_PTT_UNUSED_ENTRY(187),
 893         I40E_PTT_UNUSED_ENTRY(188),
 894         I40E_PTT_UNUSED_ENTRY(189),
 895
 896         I40E_PTT_UNUSED_ENTRY(190),
 897         I40E_PTT_UNUSED_ENTRY(191),
 898         I40E_PTT_UNUSED_ENTRY(192),
 899         I40E_PTT_UNUSED_ENTRY(193),
 900         I40E_PTT_UNUSED_ENTRY(194),
 901         I40E_PTT_UNUSED_ENTRY(195),
 902         I40E_PTT_UNUSED_ENTRY(196),
 903         I40E_PTT_UNUSED_ENTRY(197),
 904         I40E_PTT_UNUSED_ENTRY(198),
 905         I40E_PTT_UNUSED_ENTRY(199),
 906
 907         I40E_PTT_UNUSED_ENTRY(200),
 908         I40E_PTT_UNUSED_ENTRY(201),
 909         I40E_PTT_UNUSED_ENTRY(202),
 910         I40E_PTT_UNUSED_ENTRY(203),
 911         I40E_PTT_UNUSED_ENTRY(204),
 912         I40E_PTT_UNUSED_ENTRY(205),
 913         I40E_PTT_UNUSED_ENTRY(206),
 914         I40E_PTT_UNUSED_ENTRY(207),
 915         I40E_PTT_UNUSED_ENTRY(208),
 916         I40E_PTT_UNUSED_ENTRY(209),
 917
 918         I40E_PTT_UNUSED_ENTRY(210),
 919         I40E_PTT_UNUSED_ENTRY(211),
 920         I40E_PTT_UNUSED_ENTRY(212),
 921         I40E_PTT_UNUSED_ENTRY(213),
 922         I40E_PTT_UNUSED_ENTRY(214),
 923         I40E_PTT_UNUSED_ENTRY(215),
 924         I40E_PTT_UNUSED_ENTRY(216),
 925         I40E_PTT_UNUSED_ENTRY(217),
 926         I40E_PTT_UNUSED_ENTRY(218),
 927         I40E_PTT_UNUSED_ENTRY(219),
 928
 929         I40E_PTT_UNUSED_ENTRY(220),
 930         I40E_PTT_UNUSED_ENTRY(221),
 931         I40E_PTT_UNUSED_ENTRY(222),
 932         I40E_PTT_UNUSED_ENTRY(223),
 933         I40E_PTT_UNUSED_ENTRY(224),
 934         I40E_PTT_UNUSED_ENTRY(225),
 935         I40E_PTT_UNUSED_ENTRY(226),
 936         I40E_PTT_UNUSED_ENTRY(227),
 937         I40E_PTT_UNUSED_ENTRY(228),
 938         I40E_PTT_UNUSED_ENTRY(229),
 939
 940         I40E_PTT_UNUSED_ENTRY(230),
 941         I40E_PTT_UNUSED_ENTRY(231),
 942         I40E_PTT_UNUSED_ENTRY(232),
 943         I40E_PTT_UNUSED_ENTRY(233),
 944         I40E_PTT_UNUSED_ENTRY(234),
 945         I40E_PTT_UNUSED_ENTRY(235),
 946         I40E_PTT_UNUSED_ENTRY(236),
 947         I40E_PTT_UNUSED_ENTRY(237),
 948         I40E_PTT_UNUSED_ENTRY(238),
 949         I40E_PTT_UNUSED_ENTRY(239),
 950
 951         I40E_PTT_UNUSED_ENTRY(240),
 952         I40E_PTT_UNUSED_ENTRY(241),
 953         I40E_PTT_UNUSED_ENTRY(242),
 954         I40E_PTT_UNUSED_ENTRY(243),
 955         I40E_PTT_UNUSED_ENTRY(244),
 956         I40E_PTT_UNUSED_ENTRY(245),
 957         I40E_PTT_UNUSED_ENTRY(246),
 958         I40E_PTT_UNUSED_ENTRY(247),
 959         I40E_PTT_UNUSED_ENTRY(248),
 960         I40E_PTT_UNUSED_ENTRY(249),
 961
 962         I40E_PTT_UNUSED_ENTRY(250),
 963         I40E_PTT_UNUSED_ENTRY(251),
 964         I40E_PTT_UNUSED_ENTRY(252),
 965         I40E_PTT_UNUSED_ENTRY(253),
 966         I40E_PTT_UNUSED_ENTRY(254),
 967         I40E_PTT_UNUSED_ENTRY(255)
 968 };
 969
 970
 971 /**
 972  * i40e_validate_mac_addr - Validate unicast MAC address
 973  * @mac_addr: pointer to MAC address
 974  *
 975  * Tests a MAC address to ensure it is a valid Individual Address
 976  **/
 977 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 978 {
 979         enum i40e_status_code status = I40E_SUCCESS;
 980
 981         DEBUGFUNC("i40e_validate_mac_addr");
 982
 983         /* Broadcast addresses ARE multicast addresses
 984          * Make sure it is not a multicast address
 985          * Reject the zero address
 986          */
 987         if (I40E_IS_MULTICAST(mac_addr) ||
 988             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 989               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 990                 status = I40E_ERR_INVALID_MAC_ADDR;
 991
 992         return status;
 993 }
 994 #ifdef PF_DRIVER
 995
 996 /**
 997  * i40e_init_shared_code - Initialize the shared code
 998  * @hw: pointer to hardware structure
 999  *
1000  * This assigns the MAC type and PHY code and inits the NVM.
1001  * Does not touch the hardware. This function must be called prior to any
1002  * other function in the shared code. The i40e_hw structure should be
1003  * memset to 0 prior to calling this function.  The following fields in
1004  * hw structure should be filled in prior to calling this function:
1005  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1006  * subsystem_vendor_id, and revision_id
1007  **/
1008 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1009 {
1010         enum i40e_status_code status = I40E_SUCCESS;
1011         u32 port, ari, func_rid;
1012
1013         DEBUGFUNC("i40e_init_shared_code");
1014
1015         i40e_set_mac_type(hw);
1016
1017         switch (hw->mac.type) {
1018         case I40E_MAC_XL710:
1019         case I40E_MAC_X722:
1020                 break;
1021         default:
1022                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1023         }
1024
1025         hw->phy.get_link_info = true;
1026
1027         /* Determine port number and PF number*/
1028         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1029                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1030         hw->port = (u8)port;
1031         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1032                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1033         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1034         if (ari)
1035                 hw->pf_id = (u8)(func_rid & 0xff);
1036         else
1037                 hw->pf_id = (u8)(func_rid & 0x7);
1038
1039         if (hw->mac.type == I40E_MAC_X722)
1040                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1041                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1042
1043         status = i40e_init_nvm(hw);
1044         return status;
1045 }
1046
1047 /**
1048  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1049  * @hw: pointer to the hw struct
1050  * @flags: a return indicator of what addresses were added to the addr store
1051  * @addrs: the requestor's mac addr store
1052  * @cmd_details: pointer to command details structure or NULL
1053  **/
1054 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1055                                    u16 *flags,
1056                                    struct i40e_aqc_mac_address_read_data *addrs,
1057                                    struct i40e_asq_cmd_details *cmd_details)
1058 {
1059         struct i40e_aq_desc desc;
1060         struct i40e_aqc_mac_address_read *cmd_data =
1061                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1062         enum i40e_status_code status;
1063
1064         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1065         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1066
1067         status = i40e_asq_send_command(hw, &desc, addrs,
1068                                        sizeof(*addrs), cmd_details);
1069         *flags = LE16_TO_CPU(cmd_data->command_flags);
1070
1071         return status;
1072 }
1073
1074 /**
1075  * i40e_aq_mac_address_write - Change the MAC addresses
1076  * @hw: pointer to the hw struct
1077  * @flags: indicates which MAC to be written
1078  * @mac_addr: address to write
1079  * @cmd_details: pointer to command details structure or NULL
1080  **/
1081 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1082                                     u16 flags, u8 *mac_addr,
1083                                     struct i40e_asq_cmd_details *cmd_details)
1084 {
1085         struct i40e_aq_desc desc;
1086         struct i40e_aqc_mac_address_write *cmd_data =
1087                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1088         enum i40e_status_code status;
1089
1090         i40e_fill_default_direct_cmd_desc(&desc,
1091                                           i40e_aqc_opc_mac_address_write);
1092         cmd_data->command_flags = CPU_TO_LE16(flags);
1093         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1094         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1095                                         ((u32)mac_addr[3] << 16) |
1096                                         ((u32)mac_addr[4] << 8) |
1097                                         mac_addr[5]);
1098
1099         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1100
1101         return status;
1102 }
1103
1104 /**
1105  * i40e_get_mac_addr - get MAC address
1106  * @hw: pointer to the HW structure
1107  * @mac_addr: pointer to MAC address
1108  *
1109  * Reads the adapter's MAC address from register
1110  **/
1111 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1112 {
1113         struct i40e_aqc_mac_address_read_data addrs;
1114         enum i40e_status_code status;
1115         u16 flags = 0;
1116
1117         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1118
1119         if (flags & I40E_AQC_LAN_ADDR_VALID)
1120                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1121                         I40E_NONDMA_TO_NONDMA);
1122
1123         return status;
1124 }
1125
1126 /**
1127  * i40e_get_port_mac_addr - get Port MAC address
1128  * @hw: pointer to the HW structure
1129  * @mac_addr: pointer to Port MAC address
1130  *
1131  * Reads the adapter's Port MAC address
1132  **/
1133 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1134 {
1135         struct i40e_aqc_mac_address_read_data addrs;
1136         enum i40e_status_code status;
1137         u16 flags = 0;
1138
1139         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1140         if (status)
1141                 return status;
1142
1143         if (flags & I40E_AQC_PORT_ADDR_VALID)
1144                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1145                         I40E_NONDMA_TO_NONDMA);
1146         else
1147                 status = I40E_ERR_INVALID_MAC_ADDR;
1148
1149         return status;
1150 }
1151
1152 /**
1153  * i40e_pre_tx_queue_cfg - pre tx queue configure
1154  * @hw: pointer to the HW structure
1155  * @queue: target pf queue index
1156  * @enable: state change request
1157  *
1158  * Handles hw requirement to indicate intention to enable
1159  * or disable target queue.
1160  **/
1161 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1162 {
1163         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1164         u32 reg_block = 0;
1165         u32 reg_val;
1166
1167         if (abs_queue_idx >= 128) {
1168                 reg_block = abs_queue_idx / 128;
1169                 abs_queue_idx %= 128;
1170         }
1171
1172         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1173         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1174         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1175
1176         if (enable)
1177                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1178         else
1179                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1180
1181         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1182 }
1183
1184 /**
1185  * i40e_get_san_mac_addr - get SAN MAC address
1186  * @hw: pointer to the HW structure
1187  * @mac_addr: pointer to SAN MAC address
1188  *
1189  * Reads the adapter's SAN MAC address from NVM
1190  **/
1191 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1192                                             u8 *mac_addr)
1193 {
1194         struct i40e_aqc_mac_address_read_data addrs;
1195         enum i40e_status_code status;
1196         u16 flags = 0;
1197
1198         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1199         if (status)
1200                 return status;
1201
1202         if (flags & I40E_AQC_SAN_ADDR_VALID)
1203                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1204                         I40E_NONDMA_TO_NONDMA);
1205         else
1206                 status = I40E_ERR_INVALID_MAC_ADDR;
1207
1208         return status;
1209 }
1210
1211 /**
1212  *  i40e_read_pba_string - Reads part number string from EEPROM
1213  *  @hw: pointer to hardware structure
1214  *  @pba_num: stores the part number string from the EEPROM
1215  *  @pba_num_size: part number string buffer length
1216  *
1217  *  Reads the part number string from the EEPROM.
1218  **/
1219 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1220                                             u32 pba_num_size)
1221 {
1222         enum i40e_status_code status = I40E_SUCCESS;
1223         u16 pba_word = 0;
1224         u16 pba_size = 0;
1225         u16 pba_ptr = 0;
1226         u16 i = 0;
1227
1228         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1229         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1230                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1231                 return status;
1232         }
1233
1234         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1235         if (status != I40E_SUCCESS) {
1236                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1237                 return status;
1238         }
1239
1240         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1241         if (status != I40E_SUCCESS) {
1242                 DEBUGOUT("Failed to read PBA Block size.\n");
1243                 return status;
1244         }
1245
1246         /* Subtract one to get PBA word count (PBA Size word is included in
1247          * total size)
1248          */
1249         pba_size--;
1250         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1251                 DEBUGOUT("Buffer to small for PBA data.\n");
1252                 return I40E_ERR_PARAM;
1253         }
1254
1255         for (i = 0; i < pba_size; i++) {
1256                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1257                 if (status != I40E_SUCCESS) {
1258                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1259                         return status;
1260                 }
1261
1262                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1263                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1264         }
1265         pba_num[(pba_size * 2)] = '\0';
1266
1267         return status;
1268 }
1269
1270 /**
1271  * i40e_get_media_type - Gets media type
1272  * @hw: pointer to the hardware structure
1273  **/
1274 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1275 {
1276         enum i40e_media_type media;
1277
1278         switch (hw->phy.link_info.phy_type) {
1279         case I40E_PHY_TYPE_10GBASE_SR:
1280         case I40E_PHY_TYPE_10GBASE_LR:
1281         case I40E_PHY_TYPE_1000BASE_SX:
1282         case I40E_PHY_TYPE_1000BASE_LX:
1283         case I40E_PHY_TYPE_40GBASE_SR4:
1284         case I40E_PHY_TYPE_40GBASE_LR4:
1285         case I40E_PHY_TYPE_25GBASE_LR:
1286         case I40E_PHY_TYPE_25GBASE_SR:
1287                 media = I40E_MEDIA_TYPE_FIBER;
1288                 break;
1289         case I40E_PHY_TYPE_100BASE_TX:
1290         case I40E_PHY_TYPE_1000BASE_T:
1291         case I40E_PHY_TYPE_10GBASE_T:
1292                 media = I40E_MEDIA_TYPE_BASET;
1293                 break;
1294         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1295         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1296         case I40E_PHY_TYPE_10GBASE_CR1:
1297         case I40E_PHY_TYPE_40GBASE_CR4:
1298         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1299         case I40E_PHY_TYPE_40GBASE_AOC:
1300         case I40E_PHY_TYPE_10GBASE_AOC:
1301         case I40E_PHY_TYPE_25GBASE_CR:
1302         case I40E_PHY_TYPE_25GBASE_AOC:
1303         case I40E_PHY_TYPE_25GBASE_ACC:
1304                 media = I40E_MEDIA_TYPE_DA;
1305                 break;
1306         case I40E_PHY_TYPE_1000BASE_KX:
1307         case I40E_PHY_TYPE_10GBASE_KX4:
1308         case I40E_PHY_TYPE_10GBASE_KR:
1309         case I40E_PHY_TYPE_40GBASE_KR4:
1310         case I40E_PHY_TYPE_20GBASE_KR2:
1311         case I40E_PHY_TYPE_25GBASE_KR:
1312                 media = I40E_MEDIA_TYPE_BACKPLANE;
1313                 break;
1314         case I40E_PHY_TYPE_SGMII:
1315         case I40E_PHY_TYPE_XAUI:
1316         case I40E_PHY_TYPE_XFI:
1317         case I40E_PHY_TYPE_XLAUI:
1318         case I40E_PHY_TYPE_XLPPI:
1319         default:
1320                 media = I40E_MEDIA_TYPE_UNKNOWN;
1321                 break;
1322         }
1323
1324         return media;
1325 }
1326
1327 #define I40E_PF_RESET_WAIT_COUNT        200
1328 /**
1329  * i40e_pf_reset - Reset the PF
1330  * @hw: pointer to the hardware structure
1331  *
1332  * Assuming someone else has triggered a global reset,
1333  * assure the global reset is complete and then reset the PF
1334  **/
1335 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1336 {
1337         u32 cnt = 0;
1338         u32 cnt1 = 0;
1339         u32 reg = 0;
1340         u32 grst_del;
1341
1342         /* Poll for Global Reset steady state in case of recent GRST.
1343          * The grst delay value is in 100ms units, and we'll wait a
1344          * couple counts longer to be sure we don't just miss the end.
1345          */
1346         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1347                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1348                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1349
1350         grst_del = grst_del * 20;
1351
1352         for (cnt = 0; cnt < grst_del; cnt++) {
1353                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1354                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1355                         break;
1356                 i40e_msec_delay(100);
1357         }
1358         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1359                 DEBUGOUT("Global reset polling failed to complete.\n");
1360                 return I40E_ERR_RESET_FAILED;
1361         }
1362
1363         /* Now Wait for the FW to be ready */
1364         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1365                 reg = rd32(hw, I40E_GLNVM_ULD);
1366                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1367                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1368                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1369                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1370                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1371                         break;
1372                 }
1373                 i40e_msec_delay(10);
1374         }
1375         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1376                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1377                 DEBUGOUT("wait for FW Reset complete timedout\n");
1378                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1379                 return I40E_ERR_RESET_FAILED;
1380         }
1381
1382         /* If there was a Global Reset in progress when we got here,
1383          * we don't need to do the PF Reset
1384          */
1385         if (!cnt) {
1386                 u32 reg2 = 0;
1387
1388                 reg = rd32(hw, I40E_PFGEN_CTRL);
1389                 wr32(hw, I40E_PFGEN_CTRL,
1390                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1391                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1392                         reg = rd32(hw, I40E_PFGEN_CTRL);
1393                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1394                                 break;
1395                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1396                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1397                                 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1398                                 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1399                                 return I40E_ERR_NOT_READY;
1400                         }
1401                         i40e_msec_delay(1);
1402                 }
1403                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1404                         DEBUGOUT("PF reset polling failed to complete.\n");
1405                         return I40E_ERR_RESET_FAILED;
1406                 }
1407         }
1408
1409         i40e_clear_pxe_mode(hw);
1410
1411
1412         return I40E_SUCCESS;
1413 }
1414
1415 /**
1416  * i40e_clear_hw - clear out any left over hw state
1417  * @hw: pointer to the hw struct
1418  *
1419  * Clear queues and interrupts, typically called at init time,
1420  * but after the capabilities have been found so we know how many
1421  * queues and msix vectors have been allocated.
1422  **/
1423 void i40e_clear_hw(struct i40e_hw *hw)
1424 {
1425         u32 num_queues, base_queue;
1426         u32 num_pf_int;
1427         u32 num_vf_int;
1428         u32 num_vfs;
1429         u32 i, j;
1430         u32 val;
1431         u32 eol = 0x7ff;
1432
1433         /* get number of interrupts, queues, and vfs */
1434         val = rd32(hw, I40E_GLPCI_CNF2);
1435         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1436                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1437         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1438                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1439
1440         val = rd32(hw, I40E_PFLAN_QALLOC);
1441         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1442                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1443         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1444                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1445         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1446                 num_queues = (j - base_queue) + 1;
1447         else
1448                 num_queues = 0;
1449
1450         val = rd32(hw, I40E_PF_VT_PFALLOC);
1451         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1452                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1453         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1454                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1455         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1456                 num_vfs = (j - i) + 1;
1457         else
1458                 num_vfs = 0;
1459
1460         /* stop all the interrupts */
1461         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1462         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1463         for (i = 0; i < num_pf_int - 2; i++)
1464                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1465
1466         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1467         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1468         wr32(hw, I40E_PFINT_LNKLST0, val);
1469         for (i = 0; i < num_pf_int - 2; i++)
1470                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1471         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1472         for (i = 0; i < num_vfs; i++)
1473                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1474         for (i = 0; i < num_vf_int - 2; i++)
1475                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1476
1477         /* warn the HW of the coming Tx disables */
1478         for (i = 0; i < num_queues; i++) {
1479                 u32 abs_queue_idx = base_queue + i;
1480                 u32 reg_block = 0;
1481
1482                 if (abs_queue_idx >= 128) {
1483                         reg_block = abs_queue_idx / 128;
1484                         abs_queue_idx %= 128;
1485                 }
1486
1487                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1488                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1489                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1490                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1491
1492                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1493         }
1494         i40e_usec_delay(400);
1495
1496         /* stop all the queues */
1497         for (i = 0; i < num_queues; i++) {
1498                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1499                 wr32(hw, I40E_QTX_ENA(i), 0);
1500                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1501                 wr32(hw, I40E_QRX_ENA(i), 0);
1502         }
1503
1504         /* short wait for all queue disables to settle */
1505         i40e_usec_delay(50);
1506 }
1507
1508 /**
1509  * i40e_clear_pxe_mode - clear pxe operations mode
1510  * @hw: pointer to the hw struct
1511  *
1512  * Make sure all PXE mode settings are cleared, including things
1513  * like descriptor fetch/write-back mode.
1514  **/
1515 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1516 {
1517         if (i40e_check_asq_alive(hw))
1518                 i40e_aq_clear_pxe_mode(hw, NULL);
1519 }
1520
1521 /**
1522  * i40e_led_is_mine - helper to find matching led
1523  * @hw: pointer to the hw struct
1524  * @idx: index into GPIO registers
1525  *
1526  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1527  */
1528 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1529 {
1530         u32 gpio_val = 0;
1531         u32 port;
1532
1533         if (!hw->func_caps.led[idx])
1534                 return 0;
1535
1536         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1537         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1538                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1539
1540         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1541          * if it is not our port then ignore
1542          */
1543         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1544             (port != hw->port))
1545                 return 0;
1546
1547         return gpio_val;
1548 }
1549
1550 #define I40E_COMBINED_ACTIVITY 0xA
1551 #define I40E_FILTER_ACTIVITY 0xE
1552 #define I40E_LINK_ACTIVITY 0xC
1553 #define I40E_MAC_ACTIVITY 0xD
1554 #define I40E_LED0 22
1555
1556 /**
1557  * i40e_led_get - return current on/off mode
1558  * @hw: pointer to the hw struct
1559  *
1560  * The value returned is the 'mode' field as defined in the
1561  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1562  * values are variations of possible behaviors relating to
1563  * blink, link, and wire.
1564  **/
1565 u32 i40e_led_get(struct i40e_hw *hw)
1566 {
1567         u32 current_mode = 0;
1568         u32 mode = 0;
1569         int i;
1570
1571         /* as per the documentation GPIO 22-29 are the LED
1572          * GPIO pins named LED0..LED7
1573          */
1574         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1575                 u32 gpio_val = i40e_led_is_mine(hw, i);
1576
1577                 if (!gpio_val)
1578                         continue;
1579
1580                 /* ignore gpio LED src mode entries related to the activity
1581                  *  LEDs
1582                  */
1583                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1584                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1585                 switch (current_mode) {
1586                 case I40E_COMBINED_ACTIVITY:
1587                 case I40E_FILTER_ACTIVITY:
1588                 case I40E_MAC_ACTIVITY:
1589                 case I40E_LINK_ACTIVITY:
1590                         continue;
1591                 default:
1592                         break;
1593                 }
1594
1595                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1596                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1597                 break;
1598         }
1599
1600         return mode;
1601 }
1602
1603 /**
1604  * i40e_led_set - set new on/off mode
1605  * @hw: pointer to the hw struct
1606  * @mode: 0=off, 0xf=on (else see manual for mode details)
1607  * @blink: true if the LED should blink when on, false if steady
1608  *
1609  * if this function is used to turn on the blink it should
1610  * be used to disable the blink when restoring the original state.
1611  **/
1612 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1613 {
1614         u32 current_mode = 0;
1615         int i;
1616
1617         if (mode & 0xfffffff0)
1618                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1619
1620         /* as per the documentation GPIO 22-29 are the LED
1621          * GPIO pins named LED0..LED7
1622          */
1623         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1624                 u32 gpio_val = i40e_led_is_mine(hw, i);
1625
1626                 if (!gpio_val)
1627                         continue;
1628
1629                 /* ignore gpio LED src mode entries related to the activity
1630                  * LEDs
1631                  */
1632                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1633                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1634                 switch (current_mode) {
1635                 case I40E_COMBINED_ACTIVITY:
1636                 case I40E_FILTER_ACTIVITY:
1637                 case I40E_MAC_ACTIVITY:
1638                 case I40E_LINK_ACTIVITY:
1639                         continue;
1640                 default:
1641                         break;
1642                 }
1643
1644                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1645                 /* this & is a bit of paranoia, but serves as a range check */
1646                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1647                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1648
1649                 if (blink)
1650                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1651                 else
1652                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1653
1654                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1655                 break;
1656         }
1657 }
1658
1659 /* Admin command wrappers */
1660
1661 /**
1662  * i40e_aq_get_phy_capabilities
1663  * @hw: pointer to the hw struct
1664  * @abilities: structure for PHY capabilities to be filled
1665  * @qualified_modules: report Qualified Modules
1666  * @report_init: report init capabilities (active are default)
1667  * @cmd_details: pointer to command details structure or NULL
1668  *
1669  * Returns the various PHY abilities supported on the Port.
1670  **/
1671 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1672                         bool qualified_modules, bool report_init,
1673                         struct i40e_aq_get_phy_abilities_resp *abilities,
1674                         struct i40e_asq_cmd_details *cmd_details)
1675 {
1676         struct i40e_aq_desc desc;
1677         enum i40e_status_code status;
1678         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1679         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1680
1681         if (!abilities)
1682                 return I40E_ERR_PARAM;
1683
1684         do {
1685                 i40e_fill_default_direct_cmd_desc(&desc,
1686                                                i40e_aqc_opc_get_phy_abilities);
1687
1688                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1689                 if (abilities_size > I40E_AQ_LARGE_BUF)
1690                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1691
1692                 if (qualified_modules)
1693                         desc.params.external.param0 |=
1694                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1695
1696                 if (report_init)
1697                         desc.params.external.param0 |=
1698                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1699
1700                 status = i40e_asq_send_command(hw, &desc, abilities,
1701                                                abilities_size, cmd_details);
1702
1703                 if (status != I40E_SUCCESS)
1704                         break;
1705
1706                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1707                         status = I40E_ERR_UNKNOWN_PHY;
1708                         break;
1709                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1710                         i40e_msec_delay(1);
1711                         total_delay++;
1712                         status = I40E_ERR_TIMEOUT;
1713                 }
1714         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1715                  (total_delay < max_delay));
1716
1717         if (status != I40E_SUCCESS)
1718                 return status;
1719
1720         if (report_init) {
1721                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1722                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1723                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1724                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1725                 } else {
1726                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1727                         hw->phy.phy_types |=
1728                                         ((u64)abilities->phy_type_ext << 32);
1729                 }
1730         }
1731
1732         return status;
1733 }
1734
1735 /**
1736  * i40e_aq_set_phy_config
1737  * @hw: pointer to the hw struct
1738  * @config: structure with PHY configuration to be set
1739  * @cmd_details: pointer to command details structure or NULL
1740  *
1741  * Set the various PHY configuration parameters
1742  * supported on the Port.One or more of the Set PHY config parameters may be
1743  * ignored in an MFP mode as the PF may not have the privilege to set some
1744  * of the PHY Config parameters. This status will be indicated by the
1745  * command response.
1746  **/
1747 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1748                                 struct i40e_aq_set_phy_config *config,
1749                                 struct i40e_asq_cmd_details *cmd_details)
1750 {
1751         struct i40e_aq_desc desc;
1752         struct i40e_aq_set_phy_config *cmd =
1753                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1754         enum i40e_status_code status;
1755
1756         if (!config)
1757                 return I40E_ERR_PARAM;
1758
1759         i40e_fill_default_direct_cmd_desc(&desc,
1760                                           i40e_aqc_opc_set_phy_config);
1761
1762         *cmd = *config;
1763
1764         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1765
1766         return status;
1767 }
1768
1769 /**
1770  * i40e_set_fc
1771  * @hw: pointer to the hw struct
1772  * @aq_failures: buffer to return AdminQ failure information
1773  * @atomic_restart: whether to enable atomic link restart
1774  *
1775  * Set the requested flow control mode using set_phy_config.
1776  **/
1777 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1778                                   bool atomic_restart)
1779 {
1780         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1781         struct i40e_aq_get_phy_abilities_resp abilities;
1782         struct i40e_aq_set_phy_config config;
1783         enum i40e_status_code status;
1784         u8 pause_mask = 0x0;
1785
1786         *aq_failures = 0x0;
1787
1788         switch (fc_mode) {
1789         case I40E_FC_FULL:
1790                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1791                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1792                 break;
1793         case I40E_FC_RX_PAUSE:
1794                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1795                 break;
1796         case I40E_FC_TX_PAUSE:
1797                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1798                 break;
1799         default:
1800                 break;
1801         }
1802
1803         /* Get the current phy config */
1804         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1805                                               NULL);
1806         if (status) {
1807                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1808                 return status;
1809         }
1810
1811         memset(&config, 0, sizeof(config));
1812         /* clear the old pause settings */
1813         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1814                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1815         /* set the new abilities */
1816         config.abilities |= pause_mask;
1817         /* If the abilities have changed, then set the new config */
1818         if (config.abilities != abilities.abilities) {
1819                 /* Auto restart link so settings take effect */
1820                 if (atomic_restart)
1821                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1822                 /* Copy over all the old settings */
1823                 config.phy_type = abilities.phy_type;
1824                 config.phy_type_ext = abilities.phy_type_ext;
1825                 config.link_speed = abilities.link_speed;
1826                 config.eee_capability = abilities.eee_capability;
1827                 config.eeer = abilities.eeer_val;
1828                 config.low_power_ctrl = abilities.d3_lpan;
1829                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1830                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1831                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1832
1833                 if (status)
1834                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1835         }
1836         /* Update the link info */
1837         status = i40e_update_link_info(hw);
1838         if (status) {
1839                 /* Wait a little bit (on 40G cards it sometimes takes a really
1840                  * long time for link to come back from the atomic reset)
1841                  * and try once more
1842                  */
1843                 i40e_msec_delay(1000);
1844                 status = i40e_update_link_info(hw);
1845         }
1846         if (status)
1847                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1848
1849         return status;
1850 }
1851
1852 /**
1853  * i40e_aq_set_mac_config
1854  * @hw: pointer to the hw struct
1855  * @max_frame_size: Maximum Frame Size to be supported by the port
1856  * @crc_en: Tell HW to append a CRC to outgoing frames
1857  * @pacing: Pacing configurations
1858  * @cmd_details: pointer to command details structure or NULL
1859  *
1860  * Configure MAC settings for frame size, jumbo frame support and the
1861  * addition of a CRC by the hardware.
1862  **/
1863 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1864                                 u16 max_frame_size,
1865                                 bool crc_en, u16 pacing,
1866                                 struct i40e_asq_cmd_details *cmd_details)
1867 {
1868         struct i40e_aq_desc desc;
1869         struct i40e_aq_set_mac_config *cmd =
1870                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1871         enum i40e_status_code status;
1872
1873         if (max_frame_size == 0)
1874                 return I40E_ERR_PARAM;
1875
1876         i40e_fill_default_direct_cmd_desc(&desc,
1877                                           i40e_aqc_opc_set_mac_config);
1878
1879         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1880         cmd->params = ((u8)pacing & 0x0F) << 3;
1881         if (crc_en)
1882                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1883
1884         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1885
1886         return status;
1887 }
1888
1889 /**
1890  * i40e_aq_clear_pxe_mode
1891  * @hw: pointer to the hw struct
1892  * @cmd_details: pointer to command details structure or NULL
1893  *
1894  * Tell the firmware that the driver is taking over from PXE
1895  **/
1896 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1897                         struct i40e_asq_cmd_details *cmd_details)
1898 {
1899         enum i40e_status_code status;
1900         struct i40e_aq_desc desc;
1901         struct i40e_aqc_clear_pxe *cmd =
1902                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1903
1904         i40e_fill_default_direct_cmd_desc(&desc,
1905                                           i40e_aqc_opc_clear_pxe_mode);
1906
1907         cmd->rx_cnt = 0x2;
1908
1909         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1910
1911         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1912
1913         return status;
1914 }
1915
1916 /**
1917  * i40e_aq_set_link_restart_an
1918  * @hw: pointer to the hw struct
1919  * @enable_link: if true: enable link, if false: disable link
1920  * @cmd_details: pointer to command details structure or NULL
1921  *
1922  * Sets up the link and restarts the Auto-Negotiation over the link.
1923  **/
1924 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1925                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1926 {
1927         struct i40e_aq_desc desc;
1928         struct i40e_aqc_set_link_restart_an *cmd =
1929                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1930         enum i40e_status_code status;
1931
1932         i40e_fill_default_direct_cmd_desc(&desc,
1933                                           i40e_aqc_opc_set_link_restart_an);
1934
1935         cmd->command = I40E_AQ_PHY_RESTART_AN;
1936         if (enable_link)
1937                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1938         else
1939                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1940
1941         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1942
1943         return status;
1944 }
1945
1946 /**
1947  * i40e_aq_get_link_info
1948  * @hw: pointer to the hw struct
1949  * @enable_lse: enable/disable LinkStatusEvent reporting
1950  * @link: pointer to link status structure - optional
1951  * @cmd_details: pointer to command details structure or NULL
1952  *
1953  * Returns the link status of the adapter.
1954  **/
1955 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1956                                 bool enable_lse, struct i40e_link_status *link,
1957                                 struct i40e_asq_cmd_details *cmd_details)
1958 {
1959         struct i40e_aq_desc desc;
1960         struct i40e_aqc_get_link_status *resp =
1961                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1962         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1963         enum i40e_status_code status;
1964         bool tx_pause, rx_pause;
1965         u16 command_flags;
1966
1967         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1968
1969         if (enable_lse)
1970                 command_flags = I40E_AQ_LSE_ENABLE;
1971         else
1972                 command_flags = I40E_AQ_LSE_DISABLE;
1973         resp->command_flags = CPU_TO_LE16(command_flags);
1974
1975         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1976
1977         if (status != I40E_SUCCESS)
1978                 goto aq_get_link_info_exit;
1979
1980         /* save off old link status information */
1981         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1982                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1983
1984         /* update link status */
1985         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1986         hw->phy.media_type = i40e_get_media_type(hw);
1987         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1988         hw_link_info->link_info = resp->link_info;
1989         hw_link_info->an_info = resp->an_info;
1990         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1991                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1992         hw_link_info->ext_info = resp->ext_info;
1993         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1994         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1995         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1996
1997         /* update fc info */
1998         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1999         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2000         if (tx_pause & rx_pause)
2001                 hw->fc.current_mode = I40E_FC_FULL;
2002         else if (tx_pause)
2003                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2004         else if (rx_pause)
2005                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2006         else
2007                 hw->fc.current_mode = I40E_FC_NONE;
2008
2009         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2010                 hw_link_info->crc_enable = true;
2011         else
2012                 hw_link_info->crc_enable = false;
2013
2014         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2015                 hw_link_info->lse_enable = true;
2016         else
2017                 hw_link_info->lse_enable = false;
2018
2019         if ((hw->mac.type == I40E_MAC_XL710) &&
2020             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2021              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2022                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2023
2024         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2025             hw->aq.api_min_ver >= 7) {
2026                 hw->phy.phy_types = LE32_TO_CPU(*(__le32 *)resp->link_type);
2027                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2028         }
2029
2030         /* save link status information */
2031         if (link)
2032                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2033                             I40E_NONDMA_TO_NONDMA);
2034
2035         /* flag cleared so helper functions don't call AQ again */
2036         hw->phy.get_link_info = false;
2037
2038 aq_get_link_info_exit:
2039         return status;
2040 }
2041
2042 /**
2043  * i40e_aq_set_phy_int_mask
2044  * @hw: pointer to the hw struct
2045  * @mask: interrupt mask to be set
2046  * @cmd_details: pointer to command details structure or NULL
2047  *
2048  * Set link interrupt mask.
2049  **/
2050 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2051                                 u16 mask,
2052                                 struct i40e_asq_cmd_details *cmd_details)
2053 {
2054         struct i40e_aq_desc desc;
2055         struct i40e_aqc_set_phy_int_mask *cmd =
2056                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2057         enum i40e_status_code status;
2058
2059         i40e_fill_default_direct_cmd_desc(&desc,
2060                                           i40e_aqc_opc_set_phy_int_mask);
2061
2062         cmd->event_mask = CPU_TO_LE16(mask);
2063
2064         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2065
2066         return status;
2067 }
2068
2069 /**
2070  * i40e_aq_get_local_advt_reg
2071  * @hw: pointer to the hw struct
2072  * @advt_reg: local AN advertisement register value
2073  * @cmd_details: pointer to command details structure or NULL
2074  *
2075  * Get the Local AN advertisement register value.
2076  **/
2077 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2078                                 u64 *advt_reg,
2079                                 struct i40e_asq_cmd_details *cmd_details)
2080 {
2081         struct i40e_aq_desc desc;
2082         struct i40e_aqc_an_advt_reg *resp =
2083                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2084         enum i40e_status_code status;
2085
2086         i40e_fill_default_direct_cmd_desc(&desc,
2087                                           i40e_aqc_opc_get_local_advt_reg);
2088
2089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2090
2091         if (status != I40E_SUCCESS)
2092                 goto aq_get_local_advt_reg_exit;
2093
2094         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2095         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2096
2097 aq_get_local_advt_reg_exit:
2098         return status;
2099 }
2100
2101 /**
2102  * i40e_aq_set_local_advt_reg
2103  * @hw: pointer to the hw struct
2104  * @advt_reg: local AN advertisement register value
2105  * @cmd_details: pointer to command details structure or NULL
2106  *
2107  * Get the Local AN advertisement register value.
2108  **/
2109 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2110                                 u64 advt_reg,
2111                                 struct i40e_asq_cmd_details *cmd_details)
2112 {
2113         struct i40e_aq_desc desc;
2114         struct i40e_aqc_an_advt_reg *cmd =
2115                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2116         enum i40e_status_code status;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                           i40e_aqc_opc_get_local_advt_reg);
2120
2121         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2122         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2123
2124         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2125
2126         return status;
2127 }
2128
2129 /**
2130  * i40e_aq_get_partner_advt
2131  * @hw: pointer to the hw struct
2132  * @advt_reg: AN partner advertisement register value
2133  * @cmd_details: pointer to command details structure or NULL
2134  *
2135  * Get the link partner AN advertisement register value.
2136  **/
2137 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2138                                 u64 *advt_reg,
2139                                 struct i40e_asq_cmd_details *cmd_details)
2140 {
2141         struct i40e_aq_desc desc;
2142         struct i40e_aqc_an_advt_reg *resp =
2143                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2144         enum i40e_status_code status;
2145
2146         i40e_fill_default_direct_cmd_desc(&desc,
2147                                           i40e_aqc_opc_get_partner_advt);
2148
2149         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2150
2151         if (status != I40E_SUCCESS)
2152                 goto aq_get_partner_advt_exit;
2153
2154         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2155         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2156
2157 aq_get_partner_advt_exit:
2158         return status;
2159 }
2160
2161 /**
2162  * i40e_aq_set_lb_modes
2163  * @hw: pointer to the hw struct
2164  * @lb_modes: loopback mode to be set
2165  * @cmd_details: pointer to command details structure or NULL
2166  *
2167  * Sets loopback modes.
2168  **/
2169 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2170                                 u16 lb_modes,
2171                                 struct i40e_asq_cmd_details *cmd_details)
2172 {
2173         struct i40e_aq_desc desc;
2174         struct i40e_aqc_set_lb_mode *cmd =
2175                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2176         enum i40e_status_code status;
2177
2178         i40e_fill_default_direct_cmd_desc(&desc,
2179                                           i40e_aqc_opc_set_lb_modes);
2180
2181         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2182
2183         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185         return status;
2186 }
2187
2188 /**
2189  * i40e_aq_set_phy_debug
2190  * @hw: pointer to the hw struct
2191  * @cmd_flags: debug command flags
2192  * @cmd_details: pointer to command details structure or NULL
2193  *
2194  * Reset the external PHY.
2195  **/
2196 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2197                                 struct i40e_asq_cmd_details *cmd_details)
2198 {
2199         struct i40e_aq_desc desc;
2200         struct i40e_aqc_set_phy_debug *cmd =
2201                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2202         enum i40e_status_code status;
2203
2204         i40e_fill_default_direct_cmd_desc(&desc,
2205                                           i40e_aqc_opc_set_phy_debug);
2206
2207         cmd->command_flags = cmd_flags;
2208
2209         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2210
2211         return status;
2212 }
2213
2214 /**
2215  * i40e_aq_add_vsi
2216  * @hw: pointer to the hw struct
2217  * @vsi_ctx: pointer to a vsi context struct
2218  * @cmd_details: pointer to command details structure or NULL
2219  *
2220  * Add a VSI context to the hardware.
2221 **/
2222 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2223                                 struct i40e_vsi_context *vsi_ctx,
2224                                 struct i40e_asq_cmd_details *cmd_details)
2225 {
2226         struct i40e_aq_desc desc;
2227         struct i40e_aqc_add_get_update_vsi *cmd =
2228                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2229         struct i40e_aqc_add_get_update_vsi_completion *resp =
2230                 (struct i40e_aqc_add_get_update_vsi_completion *)
2231                 &desc.params.raw;
2232         enum i40e_status_code status;
2233
2234         i40e_fill_default_direct_cmd_desc(&desc,
2235                                           i40e_aqc_opc_add_vsi);
2236
2237         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2238         cmd->connection_type = vsi_ctx->connection_type;
2239         cmd->vf_id = vsi_ctx->vf_num;
2240         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2241
2242         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2243
2244         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2245                                     sizeof(vsi_ctx->info), cmd_details);
2246
2247         if (status != I40E_SUCCESS)
2248                 goto aq_add_vsi_exit;
2249
2250         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2251         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2252         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2253         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2254
2255 aq_add_vsi_exit:
2256         return status;
2257 }
2258
2259 /**
2260  * i40e_aq_set_default_vsi
2261  * @hw: pointer to the hw struct
2262  * @seid: vsi number
2263  * @cmd_details: pointer to command details structure or NULL
2264  **/
2265 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2266                                 u16 seid,
2267                                 struct i40e_asq_cmd_details *cmd_details)
2268 {
2269         struct i40e_aq_desc desc;
2270         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2271                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2272                 &desc.params.raw;
2273         enum i40e_status_code status;
2274
2275         i40e_fill_default_direct_cmd_desc(&desc,
2276                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2277
2278         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2279         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2280         cmd->seid = CPU_TO_LE16(seid);
2281
2282         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2283
2284         return status;
2285 }
2286
2287 /**
2288  * i40e_aq_clear_default_vsi
2289  * @hw: pointer to the hw struct
2290  * @seid: vsi number
2291  * @cmd_details: pointer to command details structure or NULL
2292  **/
2293 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2294                                 u16 seid,
2295                                 struct i40e_asq_cmd_details *cmd_details)
2296 {
2297         struct i40e_aq_desc desc;
2298         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2299                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2300                 &desc.params.raw;
2301         enum i40e_status_code status;
2302
2303         i40e_fill_default_direct_cmd_desc(&desc,
2304                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2305
2306         cmd->promiscuous_flags = CPU_TO_LE16(0);
2307         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2308         cmd->seid = CPU_TO_LE16(seid);
2309
2310         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2311
2312         return status;
2313 }
2314
2315 /**
2316  * i40e_aq_set_vsi_unicast_promiscuous
2317  * @hw: pointer to the hw struct
2318  * @seid: vsi number
2319  * @set: set unicast promiscuous enable/disable
2320  * @cmd_details: pointer to command details structure or NULL
2321  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2322  **/
2323 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2324                                 u16 seid, bool set,
2325                                 struct i40e_asq_cmd_details *cmd_details,
2326                                 bool rx_only_promisc)
2327 {
2328         struct i40e_aq_desc desc;
2329         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2330                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2331         enum i40e_status_code status;
2332         u16 flags = 0;
2333
2334         i40e_fill_default_direct_cmd_desc(&desc,
2335                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2336
2337         if (set) {
2338                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2339                 if (rx_only_promisc &&
2340                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2341                      (hw->aq.api_maj_ver > 1)))
2342                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2343         }
2344
2345         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2346
2347         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2348         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2349              (hw->aq.api_maj_ver > 1))
2350                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2351
2352         cmd->seid = CPU_TO_LE16(seid);
2353         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2354
2355         return status;
2356 }
2357
2358 /**
2359  * i40e_aq_set_vsi_multicast_promiscuous
2360  * @hw: pointer to the hw struct
2361  * @seid: vsi number
2362  * @set: set multicast promiscuous enable/disable
2363  * @cmd_details: pointer to command details structure or NULL
2364  **/
2365 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2366                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2367 {
2368         struct i40e_aq_desc desc;
2369         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2370                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2371         enum i40e_status_code status;
2372         u16 flags = 0;
2373
2374         i40e_fill_default_direct_cmd_desc(&desc,
2375                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2376
2377         if (set)
2378                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2379
2380         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2381
2382         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2383
2384         cmd->seid = CPU_TO_LE16(seid);
2385         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2386
2387         return status;
2388 }
2389
2390 /**
2391 * i40e_aq_set_vsi_full_promiscuous
2392 * @hw: pointer to the hw struct
2393 * @seid: VSI number
2394 * @set: set promiscuous enable/disable
2395 * @cmd_details: pointer to command details structure or NULL
2396 **/
2397 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2398                                 u16 seid, bool set,
2399                                 struct i40e_asq_cmd_details *cmd_details)
2400 {
2401         struct i40e_aq_desc desc;
2402         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2403                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2404         enum i40e_status_code status;
2405         u16 flags = 0;
2406
2407         i40e_fill_default_direct_cmd_desc(&desc,
2408                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2409
2410         if (set)
2411                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2412                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2413                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2414
2415         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2416
2417         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2418                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2419                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2420
2421         cmd->seid = CPU_TO_LE16(seid);
2422         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2423
2424         return status;
2425 }
2426
2427 /**
2428  * i40e_aq_set_vsi_mc_promisc_on_vlan
2429  * @hw: pointer to the hw struct
2430  * @seid: vsi number
2431  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2432  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2433  * @cmd_details: pointer to command details structure or NULL
2434  **/
2435 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2436                                 u16 seid, bool enable, u16 vid,
2437                                 struct i40e_asq_cmd_details *cmd_details)
2438 {
2439         struct i40e_aq_desc desc;
2440         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2441                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2442         enum i40e_status_code status;
2443         u16 flags = 0;
2444
2445         i40e_fill_default_direct_cmd_desc(&desc,
2446                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2447
2448         if (enable)
2449                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2450
2451         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2452         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2453         cmd->seid = CPU_TO_LE16(seid);
2454         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2455
2456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2457
2458         return status;
2459 }
2460
2461 /**
2462  * i40e_aq_set_vsi_uc_promisc_on_vlan
2463  * @hw: pointer to the hw struct
2464  * @seid: vsi number
2465  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2466  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2467  * @cmd_details: pointer to command details structure or NULL
2468  **/
2469 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2470                                 u16 seid, bool enable, u16 vid,
2471                                 struct i40e_asq_cmd_details *cmd_details)
2472 {
2473         struct i40e_aq_desc desc;
2474         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2475                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2476         enum i40e_status_code status;
2477         u16 flags = 0;
2478
2479         i40e_fill_default_direct_cmd_desc(&desc,
2480                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2481
2482         if (enable)
2483                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2484
2485         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2486         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2487         cmd->seid = CPU_TO_LE16(seid);
2488         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2489
2490         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2491
2492         return status;
2493 }
2494
2495 /**
2496  * i40e_aq_set_vsi_bc_promisc_on_vlan
2497  * @hw: pointer to the hw struct
2498  * @seid: vsi number
2499  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2500  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2501  * @cmd_details: pointer to command details structure or NULL
2502  **/
2503 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2504                                 u16 seid, bool enable, u16 vid,
2505                                 struct i40e_asq_cmd_details *cmd_details)
2506 {
2507         struct i40e_aq_desc desc;
2508         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2509                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2510         enum i40e_status_code status;
2511         u16 flags = 0;
2512
2513         i40e_fill_default_direct_cmd_desc(&desc,
2514                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2515
2516         if (enable)
2517                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2518
2519         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2520         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2521         cmd->seid = CPU_TO_LE16(seid);
2522         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2523
2524         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2525
2526         return status;
2527 }
2528
2529 /**
2530  * i40e_aq_set_vsi_broadcast
2531  * @hw: pointer to the hw struct
2532  * @seid: vsi number
2533  * @set_filter: true to set filter, false to clear filter
2534  * @cmd_details: pointer to command details structure or NULL
2535  *
2536  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2537  **/
2538 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2539                                 u16 seid, bool set_filter,
2540                                 struct i40e_asq_cmd_details *cmd_details)
2541 {
2542         struct i40e_aq_desc desc;
2543         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2544                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2545         enum i40e_status_code status;
2546
2547         i40e_fill_default_direct_cmd_desc(&desc,
2548                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2549
2550         if (set_filter)
2551                 cmd->promiscuous_flags
2552                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2553         else
2554                 cmd->promiscuous_flags
2555                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2556
2557         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2558         cmd->seid = CPU_TO_LE16(seid);
2559         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2560
2561         return status;
2562 }
2563
2564 /**
2565  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2566  * @hw: pointer to the hw struct
2567  * @seid: vsi number
2568  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2569  * @cmd_details: pointer to command details structure or NULL
2570  **/
2571 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2572                                 u16 seid, bool enable,
2573                                 struct i40e_asq_cmd_details *cmd_details)
2574 {
2575         struct i40e_aq_desc desc;
2576         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2577                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2578         enum i40e_status_code status;
2579         u16 flags = 0;
2580
2581         i40e_fill_default_direct_cmd_desc(&desc,
2582                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2583         if (enable)
2584                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2585
2586         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2587         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2588         cmd->seid = CPU_TO_LE16(seid);
2589
2590         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2591
2592         return status;
2593 }
2594
2595 /**
2596  * i40e_get_vsi_params - get VSI configuration info
2597  * @hw: pointer to the hw struct
2598  * @vsi_ctx: pointer to a vsi context struct
2599  * @cmd_details: pointer to command details structure or NULL
2600  **/
2601 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2602                                 struct i40e_vsi_context *vsi_ctx,
2603                                 struct i40e_asq_cmd_details *cmd_details)
2604 {
2605         struct i40e_aq_desc desc;
2606         struct i40e_aqc_add_get_update_vsi *cmd =
2607                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2608         struct i40e_aqc_add_get_update_vsi_completion *resp =
2609                 (struct i40e_aqc_add_get_update_vsi_completion *)
2610                 &desc.params.raw;
2611         enum i40e_status_code status;
2612
2613         UNREFERENCED_1PARAMETER(cmd_details);
2614         i40e_fill_default_direct_cmd_desc(&desc,
2615                                           i40e_aqc_opc_get_vsi_parameters);
2616
2617         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2618
2619         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2620
2621         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2622                                     sizeof(vsi_ctx->info), NULL);
2623
2624         if (status != I40E_SUCCESS)
2625                 goto aq_get_vsi_params_exit;
2626
2627         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2628         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2629         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2630         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2631
2632 aq_get_vsi_params_exit:
2633         return status;
2634 }
2635
2636 /**
2637  * i40e_aq_update_vsi_params
2638  * @hw: pointer to the hw struct
2639  * @vsi_ctx: pointer to a vsi context struct
2640  * @cmd_details: pointer to command details structure or NULL
2641  *
2642  * Update a VSI context.
2643  **/
2644 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2645                                 struct i40e_vsi_context *vsi_ctx,
2646                                 struct i40e_asq_cmd_details *cmd_details)
2647 {
2648         struct i40e_aq_desc desc;
2649         struct i40e_aqc_add_get_update_vsi *cmd =
2650                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2651         struct i40e_aqc_add_get_update_vsi_completion *resp =
2652                 (struct i40e_aqc_add_get_update_vsi_completion *)
2653                 &desc.params.raw;
2654         enum i40e_status_code status;
2655
2656         i40e_fill_default_direct_cmd_desc(&desc,
2657                                           i40e_aqc_opc_update_vsi_parameters);
2658         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2659
2660         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2661
2662         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2663                                     sizeof(vsi_ctx->info), cmd_details);
2664
2665         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2666         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2667
2668         return status;
2669 }
2670
2671 /**
2672  * i40e_aq_get_switch_config
2673  * @hw: pointer to the hardware structure
2674  * @buf: pointer to the result buffer
2675  * @buf_size: length of input buffer
2676  * @start_seid: seid to start for the report, 0 == beginning
2677  * @cmd_details: pointer to command details structure or NULL
2678  *
2679  * Fill the buf with switch configuration returned from AdminQ command
2680  **/
2681 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2682                                 struct i40e_aqc_get_switch_config_resp *buf,
2683                                 u16 buf_size, u16 *start_seid,
2684                                 struct i40e_asq_cmd_details *cmd_details)
2685 {
2686         struct i40e_aq_desc desc;
2687         struct i40e_aqc_switch_seid *scfg =
2688                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2689         enum i40e_status_code status;
2690
2691         i40e_fill_default_direct_cmd_desc(&desc,
2692                                           i40e_aqc_opc_get_switch_config);
2693         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2694         if (buf_size > I40E_AQ_LARGE_BUF)
2695                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2696         scfg->seid = CPU_TO_LE16(*start_seid);
2697
2698         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2699         *start_seid = LE16_TO_CPU(scfg->seid);
2700
2701         return status;
2702 }
2703
2704 /**
2705  * i40e_aq_set_switch_config
2706  * @hw: pointer to the hardware structure
2707  * @flags: bit flag values to set
2708  * @valid_flags: which bit flags to set
2709  * @cmd_details: pointer to command details structure or NULL
2710  *
2711  * Set switch configuration bits
2712  **/
2713 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2714                                 u16 flags, u16 valid_flags,
2715                                 struct i40e_asq_cmd_details *cmd_details)
2716 {
2717         struct i40e_aq_desc desc;
2718         struct i40e_aqc_set_switch_config *scfg =
2719                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2720         enum i40e_status_code status;
2721
2722         i40e_fill_default_direct_cmd_desc(&desc,
2723                                           i40e_aqc_opc_set_switch_config);
2724         scfg->flags = CPU_TO_LE16(flags);
2725         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2726         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2727                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2728                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2729                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2730         }
2731         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2732
2733         return status;
2734 }
2735
2736 /**
2737  * i40e_aq_get_firmware_version
2738  * @hw: pointer to the hw struct
2739  * @fw_major_version: firmware major version
2740  * @fw_minor_version: firmware minor version
2741  * @fw_build: firmware build number
2742  * @api_major_version: major queue version
2743  * @api_minor_version: minor queue version
2744  * @cmd_details: pointer to command details structure or NULL
2745  *
2746  * Get the firmware version from the admin queue commands
2747  **/
2748 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2749                                 u16 *fw_major_version, u16 *fw_minor_version,
2750                                 u32 *fw_build,
2751                                 u16 *api_major_version, u16 *api_minor_version,
2752                                 struct i40e_asq_cmd_details *cmd_details)
2753 {
2754         struct i40e_aq_desc desc;
2755         struct i40e_aqc_get_version *resp =
2756                 (struct i40e_aqc_get_version *)&desc.params.raw;
2757         enum i40e_status_code status;
2758
2759         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2760
2761         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2762
2763         if (status == I40E_SUCCESS) {
2764                 if (fw_major_version != NULL)
2765                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2766                 if (fw_minor_version != NULL)
2767                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2768                 if (fw_build != NULL)
2769                         *fw_build = LE32_TO_CPU(resp->fw_build);
2770                 if (api_major_version != NULL)
2771                         *api_major_version = LE16_TO_CPU(resp->api_major);
2772                 if (api_minor_version != NULL)
2773                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2774
2775                 /* A workaround to fix the API version in SW */
2776                 if (api_major_version && api_minor_version &&
2777                     fw_major_version && fw_minor_version &&
2778                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2779                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2780                      (*fw_major_version > 4)))
2781                         *api_minor_version = 2;
2782         }
2783
2784         return status;
2785 }
2786
2787 /**
2788  * i40e_aq_send_driver_version
2789  * @hw: pointer to the hw struct
2790  * @dv: driver's major, minor version
2791  * @cmd_details: pointer to command details structure or NULL
2792  *
2793  * Send the driver version to the firmware
2794  **/
2795 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2796                                 struct i40e_driver_version *dv,
2797                                 struct i40e_asq_cmd_details *cmd_details)
2798 {
2799         struct i40e_aq_desc desc;
2800         struct i40e_aqc_driver_version *cmd =
2801                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2802         enum i40e_status_code status;
2803         u16 len;
2804
2805         if (dv == NULL)
2806                 return I40E_ERR_PARAM;
2807
2808         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2809
2810         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2811         cmd->driver_major_ver = dv->major_version;
2812         cmd->driver_minor_ver = dv->minor_version;
2813         cmd->driver_build_ver = dv->build_version;
2814         cmd->driver_subbuild_ver = dv->subbuild_version;
2815
2816         len = 0;
2817         while (len < sizeof(dv->driver_string) &&
2818                (dv->driver_string[len] < 0x80) &&
2819                dv->driver_string[len])
2820                 len++;
2821         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2822                                        len, cmd_details);
2823
2824         return status;
2825 }
2826
2827 /**
2828  * i40e_get_link_status - get status of the HW network link
2829  * @hw: pointer to the hw struct
2830  * @link_up: pointer to bool (true/false = linkup/linkdown)
2831  *
2832  * Variable link_up true if link is up, false if link is down.
2833  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2834  *
2835  * Side effect: LinkStatusEvent reporting becomes enabled
2836  **/
2837 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2838 {
2839         enum i40e_status_code status = I40E_SUCCESS;
2840
2841         if (hw->phy.get_link_info) {
2842                 status = i40e_update_link_info(hw);
2843
2844                 if (status != I40E_SUCCESS)
2845                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2846                                    status);
2847         }
2848
2849         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2850
2851         return status;
2852 }
2853
2854 /**
2855  * i40e_updatelink_status - update status of the HW network link
2856  * @hw: pointer to the hw struct
2857  **/
2858 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2859 {
2860         struct i40e_aq_get_phy_abilities_resp abilities;
2861         enum i40e_status_code status = I40E_SUCCESS;
2862
2863         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2864         if (status)
2865                 return status;
2866
2867         /* extra checking needed to ensure link info to user is timely */
2868         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2869             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2870              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2871                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2872                                                       &abilities, NULL);
2873                 if (status)
2874                         return status;
2875
2876                 hw->phy.link_info.req_fec_info =
2877                         abilities.fec_cfg_curr_mod_ext_info &
2878                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2879
2880                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2881                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2882         }
2883         return status;
2884 }
2885
2886
2887 /**
2888  * i40e_get_link_speed
2889  * @hw: pointer to the hw struct
2890  *
2891  * Returns the link speed of the adapter.
2892  **/
2893 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2894 {
2895         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2896         enum i40e_status_code status = I40E_SUCCESS;
2897
2898         if (hw->phy.get_link_info) {
2899                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2900
2901                 if (status != I40E_SUCCESS)
2902                         goto i40e_link_speed_exit;
2903         }
2904
2905         speed = hw->phy.link_info.link_speed;
2906
2907 i40e_link_speed_exit:
2908         return speed;
2909 }
2910
2911 /**
2912  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2913  * @hw: pointer to the hw struct
2914  * @uplink_seid: the MAC or other gizmo SEID
2915  * @downlink_seid: the VSI SEID
2916  * @enabled_tc: bitmap of TCs to be enabled
2917  * @default_port: true for default port VSI, false for control port
2918  * @veb_seid: pointer to where to put the resulting VEB SEID
2919  * @enable_stats: true to turn on VEB stats
2920  * @cmd_details: pointer to command details structure or NULL
2921  *
2922  * This asks the FW to add a VEB between the uplink and downlink
2923  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2924  **/
2925 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2926                                 u16 downlink_seid, u8 enabled_tc,
2927                                 bool default_port, u16 *veb_seid,
2928                                 bool enable_stats,
2929                                 struct i40e_asq_cmd_details *cmd_details)
2930 {
2931         struct i40e_aq_desc desc;
2932         struct i40e_aqc_add_veb *cmd =
2933                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2934         struct i40e_aqc_add_veb_completion *resp =
2935                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2936         enum i40e_status_code status;
2937         u16 veb_flags = 0;
2938
2939         /* SEIDs need to either both be set or both be 0 for floating VEB */
2940         if (!!uplink_seid != !!downlink_seid)
2941                 return I40E_ERR_PARAM;
2942
2943         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2944
2945         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2946         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2947         cmd->enable_tcs = enabled_tc;
2948         if (!uplink_seid)
2949                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2950         if (default_port)
2951                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2952         else
2953                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2954
2955         /* reverse logic here: set the bitflag to disable the stats */
2956         if (!enable_stats)
2957                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2958
2959         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2960
2961         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2962
2963         if (!status && veb_seid)
2964                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2965
2966         return status;
2967 }
2968
2969 /**
2970  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2971  * @hw: pointer to the hw struct
2972  * @veb_seid: the SEID of the VEB to query
2973  * @switch_id: the uplink switch id
2974  * @floating: set to true if the VEB is floating
2975  * @statistic_index: index of the stats counter block for this VEB
2976  * @vebs_used: number of VEB's used by function
2977  * @vebs_free: total VEB's not reserved by any function
2978  * @cmd_details: pointer to command details structure or NULL
2979  *
2980  * This retrieves the parameters for a particular VEB, specified by
2981  * uplink_seid, and returns them to the caller.
2982  **/
2983 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2984                                 u16 veb_seid, u16 *switch_id,
2985                                 bool *floating, u16 *statistic_index,
2986                                 u16 *vebs_used, u16 *vebs_free,
2987                                 struct i40e_asq_cmd_details *cmd_details)
2988 {
2989         struct i40e_aq_desc desc;
2990         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2991                 (struct i40e_aqc_get_veb_parameters_completion *)
2992                 &desc.params.raw;
2993         enum i40e_status_code status;
2994
2995         if (veb_seid == 0)
2996                 return I40E_ERR_PARAM;
2997
2998         i40e_fill_default_direct_cmd_desc(&desc,
2999                                           i40e_aqc_opc_get_veb_parameters);
3000         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3001
3002         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3003         if (status)
3004                 goto get_veb_exit;
3005
3006         if (switch_id)
3007                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3008         if (statistic_index)
3009                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3010         if (vebs_used)
3011                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3012         if (vebs_free)
3013                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3014         if (floating) {
3015                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3016
3017                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3018                         *floating = true;
3019                 else
3020                         *floating = false;
3021         }
3022
3023 get_veb_exit:
3024         return status;
3025 }
3026
3027 /**
3028  * i40e_aq_add_macvlan
3029  * @hw: pointer to the hw struct
3030  * @seid: VSI for the mac address
3031  * @mv_list: list of macvlans to be added
3032  * @count: length of the list
3033  * @cmd_details: pointer to command details structure or NULL
3034  *
3035  * Add MAC/VLAN addresses to the HW filtering
3036  **/
3037 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3038                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3039                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3040 {
3041         struct i40e_aq_desc desc;
3042         struct i40e_aqc_macvlan *cmd =
3043                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3044         enum i40e_status_code status;
3045         u16 buf_size;
3046         int i;
3047
3048         if (count == 0 || !mv_list || !hw)
3049                 return I40E_ERR_PARAM;
3050
3051         buf_size = count * sizeof(*mv_list);
3052
3053         /* prep the rest of the request */
3054         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3055         cmd->num_addresses = CPU_TO_LE16(count);
3056         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3057         cmd->seid[1] = 0;
3058         cmd->seid[2] = 0;
3059
3060         for (i = 0; i < count; i++)
3061                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3062                         mv_list[i].flags |=
3063                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3064
3065         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3066         if (buf_size > I40E_AQ_LARGE_BUF)
3067                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3068
3069         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3070                                        cmd_details);
3071
3072         return status;
3073 }
3074
3075 /**
3076  * i40e_aq_remove_macvlan
3077  * @hw: pointer to the hw struct
3078  * @seid: VSI for the mac address
3079  * @mv_list: list of macvlans to be removed
3080  * @count: length of the list
3081  * @cmd_details: pointer to command details structure or NULL
3082  *
3083  * Remove MAC/VLAN addresses from the HW filtering
3084  **/
3085 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3086                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3087                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3088 {
3089         struct i40e_aq_desc desc;
3090         struct i40e_aqc_macvlan *cmd =
3091                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3092         enum i40e_status_code status;
3093         u16 buf_size;
3094
3095         if (count == 0 || !mv_list || !hw)
3096                 return I40E_ERR_PARAM;
3097
3098         buf_size = count * sizeof(*mv_list);
3099
3100         /* prep the rest of the request */
3101         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3102         cmd->num_addresses = CPU_TO_LE16(count);
3103         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3104         cmd->seid[1] = 0;
3105         cmd->seid[2] = 0;
3106
3107         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3108         if (buf_size > I40E_AQ_LARGE_BUF)
3109                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3110
3111         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3112                                        cmd_details);
3113
3114         return status;
3115 }
3116
3117 /**
3118  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3119  * @hw: pointer to the hw struct
3120  * @opcode: AQ opcode for add or delete mirror rule
3121  * @sw_seid: Switch SEID (to which rule refers)
3122  * @rule_type: Rule Type (ingress/egress/VLAN)
3123  * @id: Destination VSI SEID or Rule ID
3124  * @count: length of the list
3125  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3126  * @cmd_details: pointer to command details structure or NULL
3127  * @rule_id: Rule ID returned from FW
3128  * @rules_used: Number of rules used in internal switch
3129  * @rules_free: Number of rules free in internal switch
3130  *
3131  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3132  * VEBs/VEPA elements only
3133  **/
3134 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3135                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3136                         u16 count, __le16 *mr_list,
3137                         struct i40e_asq_cmd_details *cmd_details,
3138                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3139 {
3140         struct i40e_aq_desc desc;
3141         struct i40e_aqc_add_delete_mirror_rule *cmd =
3142                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3143         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3144         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3145         enum i40e_status_code status;
3146         u16 buf_size;
3147
3148         buf_size = count * sizeof(*mr_list);
3149
3150         /* prep the rest of the request */
3151         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3152         cmd->seid = CPU_TO_LE16(sw_seid);
3153         cmd->rule_type = CPU_TO_LE16(rule_type &
3154                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3155         cmd->num_entries = CPU_TO_LE16(count);
3156         /* Dest VSI for add, rule_id for delete */
3157         cmd->destination = CPU_TO_LE16(id);
3158         if (mr_list) {
3159                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3160                                                 I40E_AQ_FLAG_RD));
3161                 if (buf_size > I40E_AQ_LARGE_BUF)
3162                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3163         }
3164
3165         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3166                                        cmd_details);
3167         if (status == I40E_SUCCESS ||
3168             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3169                 if (rule_id)
3170                         *rule_id = LE16_TO_CPU(resp->rule_id);
3171                 if (rules_used)
3172                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3173                 if (rules_free)
3174                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3175         }
3176         return status;
3177 }
3178
3179 /**
3180  * i40e_aq_add_mirrorrule - add a mirror rule
3181  * @hw: pointer to the hw struct
3182  * @sw_seid: Switch SEID (to which rule refers)
3183  * @rule_type: Rule Type (ingress/egress/VLAN)
3184  * @dest_vsi: SEID of VSI to which packets will be mirrored
3185  * @count: length of the list
3186  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3187  * @cmd_details: pointer to command details structure or NULL
3188  * @rule_id: Rule ID returned from FW
3189  * @rules_used: Number of rules used in internal switch
3190  * @rules_free: Number of rules free in internal switch
3191  *
3192  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3193  **/
3194 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3195                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3196                         struct i40e_asq_cmd_details *cmd_details,
3197                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3198 {
3199         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3200             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3201                 if (count == 0 || !mr_list)
3202                         return I40E_ERR_PARAM;
3203         }
3204
3205         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3206                                   rule_type, dest_vsi, count, mr_list,
3207                                   cmd_details, rule_id, rules_used, rules_free);
3208 }
3209
3210 /**
3211  * i40e_aq_delete_mirrorrule - delete a mirror rule
3212  * @hw: pointer to the hw struct
3213  * @sw_seid: Switch SEID (to which rule refers)
3214  * @rule_type: Rule Type (ingress/egress/VLAN)
3215  * @count: length of the list
3216  * @rule_id: Rule ID that is returned in the receive desc as part of
3217  *              add_mirrorrule.
3218  * @mr_list: list of mirrored VLAN IDs to be removed
3219  * @cmd_details: pointer to command details structure or NULL
3220  * @rules_used: Number of rules used in internal switch
3221  * @rules_free: Number of rules free in internal switch
3222  *
3223  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3224  **/
3225 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3226                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3227                         struct i40e_asq_cmd_details *cmd_details,
3228                         u16 *rules_used, u16 *rules_free)
3229 {
3230         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3231         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3232                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3233                  * mirroring. For other rule_type, count and rule_type should
3234                  * not matter.
3235                  */
3236                 if (count == 0 || !mr_list)
3237                         return I40E_ERR_PARAM;
3238         }
3239
3240         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3241                                   rule_type, rule_id, count, mr_list,
3242                                   cmd_details, NULL, rules_used, rules_free);
3243 }
3244
3245 /**
3246  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3247  * @hw: pointer to the hw struct
3248  * @seid: VSI for the vlan filters
3249  * @v_list: list of vlan filters to be added
3250  * @count: length of the list
3251  * @cmd_details: pointer to command details structure or NULL
3252  **/
3253 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3254                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3255                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3256 {
3257         struct i40e_aq_desc desc;
3258         struct i40e_aqc_macvlan *cmd =
3259                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3260         enum i40e_status_code status;
3261         u16 buf_size;
3262
3263         if (count == 0 || !v_list || !hw)
3264                 return I40E_ERR_PARAM;
3265
3266         buf_size = count * sizeof(*v_list);
3267
3268         /* prep the rest of the request */
3269         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3270         cmd->num_addresses = CPU_TO_LE16(count);
3271         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3272         cmd->seid[1] = 0;
3273         cmd->seid[2] = 0;
3274
3275         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3276         if (buf_size > I40E_AQ_LARGE_BUF)
3277                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3278
3279         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3280                                        cmd_details);
3281
3282         return status;
3283 }
3284
3285 /**
3286  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3287  * @hw: pointer to the hw struct
3288  * @seid: VSI for the vlan filters
3289  * @v_list: list of macvlans to be removed
3290  * @count: length of the list
3291  * @cmd_details: pointer to command details structure or NULL
3292  **/
3293 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3294                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3295                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3296 {
3297         struct i40e_aq_desc desc;
3298         struct i40e_aqc_macvlan *cmd =
3299                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3300         enum i40e_status_code status;
3301         u16 buf_size;
3302
3303         if (count == 0 || !v_list || !hw)
3304                 return I40E_ERR_PARAM;
3305
3306         buf_size = count * sizeof(*v_list);
3307
3308         /* prep the rest of the request */
3309         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3310         cmd->num_addresses = CPU_TO_LE16(count);
3311         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3312         cmd->seid[1] = 0;
3313         cmd->seid[2] = 0;
3314
3315         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3316         if (buf_size > I40E_AQ_LARGE_BUF)
3317                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3318
3319         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3320                                        cmd_details);
3321
3322         return status;
3323 }
3324
3325 /**
3326  * i40e_aq_send_msg_to_vf
3327  * @hw: pointer to the hardware structure
3328  * @vfid: vf id to send msg
3329  * @v_opcode: opcodes for VF-PF communication
3330  * @v_retval: return error code
3331  * @msg: pointer to the msg buffer
3332  * @msglen: msg length
3333  * @cmd_details: pointer to command details
3334  *
3335  * send msg to vf
3336  **/
3337 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3338                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3339                                 struct i40e_asq_cmd_details *cmd_details)
3340 {
3341         struct i40e_aq_desc desc;
3342         struct i40e_aqc_pf_vf_message *cmd =
3343                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3344         enum i40e_status_code status;
3345
3346         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3347         cmd->id = CPU_TO_LE32(vfid);
3348         desc.cookie_high = CPU_TO_LE32(v_opcode);
3349         desc.cookie_low = CPU_TO_LE32(v_retval);
3350         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3351         if (msglen) {
3352                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3353                                                 I40E_AQ_FLAG_RD));
3354                 if (msglen > I40E_AQ_LARGE_BUF)
3355                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3356                 desc.datalen = CPU_TO_LE16(msglen);
3357         }
3358         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3359
3360         return status;
3361 }
3362
3363 /**
3364  * i40e_aq_debug_read_register
3365  * @hw: pointer to the hw struct
3366  * @reg_addr: register address
3367  * @reg_val: register value
3368  * @cmd_details: pointer to command details structure or NULL
3369  *
3370  * Read the register using the admin queue commands
3371  **/
3372 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3373                                 u32 reg_addr, u64 *reg_val,
3374                                 struct i40e_asq_cmd_details *cmd_details)
3375 {
3376         struct i40e_aq_desc desc;
3377         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3378                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3379         enum i40e_status_code status;
3380
3381         if (reg_val == NULL)
3382                 return I40E_ERR_PARAM;
3383
3384         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3385
3386         cmd_resp->address = CPU_TO_LE32(reg_addr);
3387
3388         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3389
3390         if (status == I40E_SUCCESS) {
3391                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3392                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3393         }
3394
3395         return status;
3396 }
3397
3398 /**
3399  * i40e_aq_debug_write_register
3400  * @hw: pointer to the hw struct
3401  * @reg_addr: register address
3402  * @reg_val: register value
3403  * @cmd_details: pointer to command details structure or NULL
3404  *
3405  * Write to a register using the admin queue commands
3406  **/
3407 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3408                                 u32 reg_addr, u64 reg_val,
3409                                 struct i40e_asq_cmd_details *cmd_details)
3410 {
3411         struct i40e_aq_desc desc;
3412         struct i40e_aqc_debug_reg_read_write *cmd =
3413                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3414         enum i40e_status_code status;
3415
3416         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3417
3418         cmd->address = CPU_TO_LE32(reg_addr);
3419         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3420         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3421
3422         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3423
3424         return status;
3425 }
3426
3427 /**
3428  * i40e_aq_request_resource
3429  * @hw: pointer to the hw struct
3430  * @resource: resource id
3431  * @access: access type
3432  * @sdp_number: resource number
3433  * @timeout: the maximum time in ms that the driver may hold the resource
3434  * @cmd_details: pointer to command details structure or NULL
3435  *
3436  * requests common resource using the admin queue commands
3437  **/
3438 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3439                                 enum i40e_aq_resources_ids resource,
3440                                 enum i40e_aq_resource_access_type access,
3441                                 u8 sdp_number, u64 *timeout,
3442                                 struct i40e_asq_cmd_details *cmd_details)
3443 {
3444         struct i40e_aq_desc desc;
3445         struct i40e_aqc_request_resource *cmd_resp =
3446                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3447         enum i40e_status_code status;
3448
3449         DEBUGFUNC("i40e_aq_request_resource");
3450
3451         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3452
3453         cmd_resp->resource_id = CPU_TO_LE16(resource);
3454         cmd_resp->access_type = CPU_TO_LE16(access);
3455         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3456
3457         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3458         /* The completion specifies the maximum time in ms that the driver
3459          * may hold the resource in the Timeout field.
3460          * If the resource is held by someone else, the command completes with
3461          * busy return value and the timeout field indicates the maximum time
3462          * the current owner of the resource has to free it.
3463          */
3464         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3465                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3466
3467         return status;
3468 }
3469
3470 /**
3471  * i40e_aq_release_resource
3472  * @hw: pointer to the hw struct
3473  * @resource: resource id
3474  * @sdp_number: resource number
3475  * @cmd_details: pointer to command details structure or NULL
3476  *
3477  * release common resource using the admin queue commands
3478  **/
3479 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3480                                 enum i40e_aq_resources_ids resource,
3481                                 u8 sdp_number,
3482                                 struct i40e_asq_cmd_details *cmd_details)
3483 {
3484         struct i40e_aq_desc desc;
3485         struct i40e_aqc_request_resource *cmd =
3486                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3487         enum i40e_status_code status;
3488
3489         DEBUGFUNC("i40e_aq_release_resource");
3490
3491         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3492
3493         cmd->resource_id = CPU_TO_LE16(resource);
3494         cmd->resource_number = CPU_TO_LE32(sdp_number);
3495
3496         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3497
3498         return status;
3499 }
3500
3501 /**
3502  * i40e_aq_read_nvm
3503  * @hw: pointer to the hw struct
3504  * @module_pointer: module pointer location in words from the NVM beginning
3505  * @offset: byte offset from the module beginning
3506  * @length: length of the section to be read (in bytes from the offset)
3507  * @data: command buffer (size [bytes] = length)
3508  * @last_command: tells if this is the last command in a series
3509  * @cmd_details: pointer to command details structure or NULL
3510  *
3511  * Read the NVM using the admin queue commands
3512  **/
3513 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3514                                 u32 offset, u16 length, void *data,
3515                                 bool last_command,
3516                                 struct i40e_asq_cmd_details *cmd_details)
3517 {
3518         struct i40e_aq_desc desc;
3519         struct i40e_aqc_nvm_update *cmd =
3520                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3521         enum i40e_status_code status;
3522
3523         DEBUGFUNC("i40e_aq_read_nvm");
3524
3525         /* In offset the highest byte must be zeroed. */
3526         if (offset & 0xFF000000) {
3527                 status = I40E_ERR_PARAM;
3528                 goto i40e_aq_read_nvm_exit;
3529         }
3530
3531         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3532
3533         /* If this is the last command in a series, set the proper flag. */
3534         if (last_command)
3535                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3536         cmd->module_pointer = module_pointer;
3537         cmd->offset = CPU_TO_LE32(offset);
3538         cmd->length = CPU_TO_LE16(length);
3539
3540         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3541         if (length > I40E_AQ_LARGE_BUF)
3542                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3543
3544         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3545
3546 i40e_aq_read_nvm_exit:
3547         return status;
3548 }
3549
3550 /**
3551  * i40e_aq_read_nvm_config - read an nvm config block
3552  * @hw: pointer to the hw struct
3553  * @cmd_flags: NVM access admin command bits
3554  * @field_id: field or feature id
3555  * @data: buffer for result
3556  * @buf_size: buffer size
3557  * @element_count: pointer to count of elements read by FW
3558  * @cmd_details: pointer to command details structure or NULL
3559  **/
3560 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3561                                 u8 cmd_flags, u32 field_id, void *data,
3562                                 u16 buf_size, u16 *element_count,
3563                                 struct i40e_asq_cmd_details *cmd_details)
3564 {
3565         struct i40e_aq_desc desc;
3566         struct i40e_aqc_nvm_config_read *cmd =
3567                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3568         enum i40e_status_code status;
3569
3570         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3571         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3572         if (buf_size > I40E_AQ_LARGE_BUF)
3573                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3574
3575         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3576         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3577         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3578                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3579         else
3580                 cmd->element_id_msw = 0;
3581
3582         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3583
3584         if (!status && element_count)
3585                 *element_count = LE16_TO_CPU(cmd->element_count);
3586
3587         return status;
3588 }
3589
3590 /**
3591  * i40e_aq_write_nvm_config - write an nvm config block
3592  * @hw: pointer to the hw struct
3593  * @cmd_flags: NVM access admin command bits
3594  * @data: buffer for result
3595  * @buf_size: buffer size
3596  * @element_count: count of elements to be written
3597  * @cmd_details: pointer to command details structure or NULL
3598  **/
3599 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3600                                 u8 cmd_flags, void *data, u16 buf_size,
3601                                 u16 element_count,
3602                                 struct i40e_asq_cmd_details *cmd_details)
3603 {
3604         struct i40e_aq_desc desc;
3605         struct i40e_aqc_nvm_config_write *cmd =
3606                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3607         enum i40e_status_code status;
3608
3609         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3610         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3611         if (buf_size > I40E_AQ_LARGE_BUF)
3612                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3613
3614         cmd->element_count = CPU_TO_LE16(element_count);
3615         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3616         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3617
3618         return status;
3619 }
3620
3621 /**
3622  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3623  * @hw: pointer to the hw struct
3624  * @buff: buffer for result
3625  * @buff_size: buffer size
3626  * @cmd_details: pointer to command details structure or NULL
3627  **/
3628 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3629                                 void *buff, u16 buff_size,
3630                                 struct i40e_asq_cmd_details *cmd_details)
3631 {
3632         struct i40e_aq_desc desc;
3633         enum i40e_status_code status;
3634
3635         UNREFERENCED_2PARAMETER(buff, buff_size);
3636
3637         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3638         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3639         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3640                 status = I40E_ERR_NOT_IMPLEMENTED;
3641
3642         return status;
3643 }
3644
3645 /**
3646  * i40e_aq_erase_nvm
3647  * @hw: pointer to the hw struct
3648  * @module_pointer: module pointer location in words from the NVM beginning
3649  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3650  * @length: length of the section to be erased (expressed in 4 KB)
3651  * @last_command: tells if this is the last command in a series
3652  * @cmd_details: pointer to command details structure or NULL
3653  *
3654  * Erase the NVM sector using the admin queue commands
3655  **/
3656 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3657                                 u32 offset, u16 length, bool last_command,
3658                                 struct i40e_asq_cmd_details *cmd_details)
3659 {
3660         struct i40e_aq_desc desc;
3661         struct i40e_aqc_nvm_update *cmd =
3662                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3663         enum i40e_status_code status;
3664
3665         DEBUGFUNC("i40e_aq_erase_nvm");
3666
3667         /* In offset the highest byte must be zeroed. */
3668         if (offset & 0xFF000000) {
3669                 status = I40E_ERR_PARAM;
3670                 goto i40e_aq_erase_nvm_exit;
3671         }
3672
3673         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3674
3675         /* If this is the last command in a series, set the proper flag. */
3676         if (last_command)
3677                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3678         cmd->module_pointer = module_pointer;
3679         cmd->offset = CPU_TO_LE32(offset);
3680         cmd->length = CPU_TO_LE16(length);
3681
3682         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3683
3684 i40e_aq_erase_nvm_exit:
3685         return status;
3686 }
3687
3688 /**
3689  * i40e_parse_discover_capabilities
3690  * @hw: pointer to the hw struct
3691  * @buff: pointer to a buffer containing device/function capability records
3692  * @cap_count: number of capability records in the list
3693  * @list_type_opc: type of capabilities list to parse
3694  *
3695  * Parse the device/function capabilities list.
3696  **/
3697 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3698                                      u32 cap_count,
3699                                      enum i40e_admin_queue_opc list_type_opc)
3700 {
3701         struct i40e_aqc_list_capabilities_element_resp *cap;
3702         u32 valid_functions, num_functions;
3703         u32 number, logical_id, phys_id;
3704         struct i40e_hw_capabilities *p;
3705         u8 major_rev;
3706         u32 i = 0;
3707         u16 id;
3708
3709         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3710
3711         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3712                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3713         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3714                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3715         else
3716                 return;
3717
3718         for (i = 0; i < cap_count; i++, cap++) {
3719                 id = LE16_TO_CPU(cap->id);
3720                 number = LE32_TO_CPU(cap->number);
3721                 logical_id = LE32_TO_CPU(cap->logical_id);
3722                 phys_id = LE32_TO_CPU(cap->phys_id);
3723                 major_rev = cap->major_rev;
3724
3725                 switch (id) {
3726                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3727                         p->switch_mode = number;
3728                         i40e_debug(hw, I40E_DEBUG_INIT,
3729                                    "HW Capability: Switch mode = %d\n",
3730                                    p->switch_mode);
3731                         break;
3732                 case I40E_AQ_CAP_ID_MNG_MODE:
3733                         p->management_mode = number;
3734                         if (major_rev > 1) {
3735                                 p->mng_protocols_over_mctp = logical_id;
3736                                 i40e_debug(hw, I40E_DEBUG_INIT,
3737                                            "HW Capability: Protocols over MCTP = %d\n",
3738                                            p->mng_protocols_over_mctp);
3739                         } else {
3740                                 p->mng_protocols_over_mctp = 0;
3741                         }
3742                         i40e_debug(hw, I40E_DEBUG_INIT,
3743                                    "HW Capability: Management Mode = %d\n",
3744                                    p->management_mode);
3745                         break;
3746                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3747                         p->npar_enable = number;
3748                         i40e_debug(hw, I40E_DEBUG_INIT,
3749                                    "HW Capability: NPAR enable = %d\n",
3750                                    p->npar_enable);
3751                         break;
3752                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3753                         p->os2bmc = number;
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3756                         break;
3757                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3758                         p->valid_functions = number;
3759                         i40e_debug(hw, I40E_DEBUG_INIT,
3760                                    "HW Capability: Valid Functions = %d\n",
3761                                    p->valid_functions);
3762                         break;
3763                 case I40E_AQ_CAP_ID_SRIOV:
3764                         if (number == 1)
3765                                 p->sr_iov_1_1 = true;
3766                         i40e_debug(hw, I40E_DEBUG_INIT,
3767                                    "HW Capability: SR-IOV = %d\n",
3768                                    p->sr_iov_1_1);
3769                         break;
3770                 case I40E_AQ_CAP_ID_VF:
3771                         p->num_vfs = number;
3772                         p->vf_base_id = logical_id;
3773                         i40e_debug(hw, I40E_DEBUG_INIT,
3774                                    "HW Capability: VF count = %d\n",
3775                                    p->num_vfs);
3776                         i40e_debug(hw, I40E_DEBUG_INIT,
3777                                    "HW Capability: VF base_id = %d\n",
3778                                    p->vf_base_id);
3779                         break;
3780                 case I40E_AQ_CAP_ID_VMDQ:
3781                         if (number == 1)
3782                                 p->vmdq = true;
3783                         i40e_debug(hw, I40E_DEBUG_INIT,
3784                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3785                         break;
3786                 case I40E_AQ_CAP_ID_8021QBG:
3787                         if (number == 1)
3788                                 p->evb_802_1_qbg = true;
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: 802.1Qbg = %d\n", number);
3791                         break;
3792                 case I40E_AQ_CAP_ID_8021QBR:
3793                         if (number == 1)
3794                                 p->evb_802_1_qbh = true;
3795                         i40e_debug(hw, I40E_DEBUG_INIT,
3796                                    "HW Capability: 802.1Qbh = %d\n", number);
3797                         break;
3798                 case I40E_AQ_CAP_ID_VSI:
3799                         p->num_vsis = number;
3800                         i40e_debug(hw, I40E_DEBUG_INIT,
3801                                    "HW Capability: VSI count = %d\n",
3802                                    p->num_vsis);
3803                         break;
3804                 case I40E_AQ_CAP_ID_DCB:
3805                         if (number == 1) {
3806                                 p->dcb = true;
3807                                 p->enabled_tcmap = logical_id;
3808                                 p->maxtc = phys_id;
3809                         }
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: DCB = %d\n", p->dcb);
3812                         i40e_debug(hw, I40E_DEBUG_INIT,
3813                                    "HW Capability: TC Mapping = %d\n",
3814                                    logical_id);
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: TC Max = %d\n", p->maxtc);
3817                         break;
3818                 case I40E_AQ_CAP_ID_FCOE:
3819                         if (number == 1)
3820                                 p->fcoe = true;
3821                         i40e_debug(hw, I40E_DEBUG_INIT,
3822                                    "HW Capability: FCOE = %d\n", p->fcoe);
3823                         break;
3824                 case I40E_AQ_CAP_ID_ISCSI:
3825                         if (number == 1)
3826                                 p->iscsi = true;
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3829                         break;
3830                 case I40E_AQ_CAP_ID_RSS:
3831                         p->rss = true;
3832                         p->rss_table_size = number;
3833                         p->rss_table_entry_width = logical_id;
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: RSS = %d\n", p->rss);
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: RSS table size = %d\n",
3838                                    p->rss_table_size);
3839                         i40e_debug(hw, I40E_DEBUG_INIT,
3840                                    "HW Capability: RSS table width = %d\n",
3841                                    p->rss_table_entry_width);
3842                         break;
3843                 case I40E_AQ_CAP_ID_RXQ:
3844                         p->num_rx_qp = number;
3845                         p->base_queue = phys_id;
3846                         i40e_debug(hw, I40E_DEBUG_INIT,
3847                                    "HW Capability: Rx QP = %d\n", number);
3848                         i40e_debug(hw, I40E_DEBUG_INIT,
3849                                    "HW Capability: base_queue = %d\n",
3850                                    p->base_queue);
3851                         break;
3852                 case I40E_AQ_CAP_ID_TXQ:
3853                         p->num_tx_qp = number;
3854                         p->base_queue = phys_id;
3855                         i40e_debug(hw, I40E_DEBUG_INIT,
3856                                    "HW Capability: Tx QP = %d\n", number);
3857                         i40e_debug(hw, I40E_DEBUG_INIT,
3858                                    "HW Capability: base_queue = %d\n",
3859                                    p->base_queue);
3860                         break;
3861                 case I40E_AQ_CAP_ID_MSIX:
3862                         p->num_msix_vectors = number;
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: MSIX vector count = %d\n",
3865                                    p->num_msix_vectors);
3866                         break;
3867                 case I40E_AQ_CAP_ID_VF_MSIX:
3868                         p->num_msix_vectors_vf = number;
3869                         i40e_debug(hw, I40E_DEBUG_INIT,
3870                                    "HW Capability: MSIX VF vector count = %d\n",
3871                                    p->num_msix_vectors_vf);
3872                         break;
3873                 case I40E_AQ_CAP_ID_FLEX10:
3874                         if (major_rev == 1) {
3875                                 if (number == 1) {
3876                                         p->flex10_enable = true;
3877                                         p->flex10_capable = true;
3878                                 }
3879                         } else {
3880                                 /* Capability revision >= 2 */
3881                                 if (number & 1)
3882                                         p->flex10_enable = true;
3883                                 if (number & 2)
3884                                         p->flex10_capable = true;
3885                         }
3886                         p->flex10_mode = logical_id;
3887                         p->flex10_status = phys_id;
3888                         i40e_debug(hw, I40E_DEBUG_INIT,
3889                                    "HW Capability: Flex10 mode = %d\n",
3890                                    p->flex10_mode);
3891                         i40e_debug(hw, I40E_DEBUG_INIT,
3892                                    "HW Capability: Flex10 status = %d\n",
3893                                    p->flex10_status);
3894                         break;
3895                 case I40E_AQ_CAP_ID_CEM:
3896                         if (number == 1)
3897                                 p->mgmt_cem = true;
3898                         i40e_debug(hw, I40E_DEBUG_INIT,
3899                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3900                         break;
3901                 case I40E_AQ_CAP_ID_IWARP:
3902                         if (number == 1)
3903                                 p->iwarp = true;
3904                         i40e_debug(hw, I40E_DEBUG_INIT,
3905                                    "HW Capability: iWARP = %d\n", p->iwarp);
3906                         break;
3907                 case I40E_AQ_CAP_ID_LED:
3908                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3909                                 p->led[phys_id] = true;
3910                         i40e_debug(hw, I40E_DEBUG_INIT,
3911                                    "HW Capability: LED - PIN %d\n", phys_id);
3912                         break;
3913                 case I40E_AQ_CAP_ID_SDP:
3914                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3915                                 p->sdp[phys_id] = true;
3916                         i40e_debug(hw, I40E_DEBUG_INIT,
3917                                    "HW Capability: SDP - PIN %d\n", phys_id);
3918                         break;
3919                 case I40E_AQ_CAP_ID_MDIO:
3920                         if (number == 1) {
3921                                 p->mdio_port_num = phys_id;
3922                                 p->mdio_port_mode = logical_id;
3923                         }
3924                         i40e_debug(hw, I40E_DEBUG_INIT,
3925                                    "HW Capability: MDIO port number = %d\n",
3926                                    p->mdio_port_num);
3927                         i40e_debug(hw, I40E_DEBUG_INIT,
3928                                    "HW Capability: MDIO port mode = %d\n",
3929                                    p->mdio_port_mode);
3930                         break;
3931                 case I40E_AQ_CAP_ID_1588:
3932                         if (number == 1)
3933                                 p->ieee_1588 = true;
3934                         i40e_debug(hw, I40E_DEBUG_INIT,
3935                                    "HW Capability: IEEE 1588 = %d\n",
3936                                    p->ieee_1588);
3937                         break;
3938                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3939                         p->fd = true;
3940                         p->fd_filters_guaranteed = number;
3941                         p->fd_filters_best_effort = logical_id;
3942                         i40e_debug(hw, I40E_DEBUG_INIT,
3943                                    "HW Capability: Flow Director = 1\n");
3944                         i40e_debug(hw, I40E_DEBUG_INIT,
3945                                    "HW Capability: Guaranteed FD filters = %d\n",
3946                                    p->fd_filters_guaranteed);
3947                         break;
3948                 case I40E_AQ_CAP_ID_WSR_PROT:
3949                         p->wr_csr_prot = (u64)number;
3950                         p->wr_csr_prot |= (u64)logical_id << 32;
3951                         i40e_debug(hw, I40E_DEBUG_INIT,
3952                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3953                                    (p->wr_csr_prot & 0xffff));
3954                         break;
3955                 case I40E_AQ_CAP_ID_NVM_MGMT:
3956                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3957                                 p->sec_rev_disabled = true;
3958                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3959                                 p->update_disabled = true;
3960                         break;
3961                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3962                         hw->num_wol_proxy_filters = (u16)number;
3963                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3964                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3965                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3966                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3967                         else
3968                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3969                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3970                         i40e_debug(hw, I40E_DEBUG_INIT,
3971                                    "HW Capability: WOL proxy filters = %d\n",
3972                                    hw->num_wol_proxy_filters);
3973                         break;
3974                 default:
3975                         break;
3976                 }
3977         }
3978
3979         if (p->fcoe)
3980                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3981
3982         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3983         p->fcoe = false;
3984
3985         /* count the enabled ports (aka the "not disabled" ports) */
3986         hw->num_ports = 0;
3987         for (i = 0; i < 4; i++) {
3988                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3989                 u64 port_cfg = 0;
3990
3991                 /* use AQ read to get the physical register offset instead
3992                  * of the port relative offset
3993                  */
3994                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3995                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3996                         hw->num_ports++;
3997         }
3998
3999         valid_functions = p->valid_functions;
4000         num_functions = 0;
4001         while (valid_functions) {
4002                 if (valid_functions & 1)
4003                         num_functions++;
4004                 valid_functions >>= 1;
4005         }
4006
4007         /* partition id is 1-based, and functions are evenly spread
4008          * across the ports as partitions
4009          */
4010         if (hw->num_ports != 0) {
4011                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4012                 hw->num_partitions = num_functions / hw->num_ports;
4013         }
4014
4015         /* additional HW specific goodies that might
4016          * someday be HW version specific
4017          */
4018         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4019 }
4020
4021 /**
4022  * i40e_aq_discover_capabilities
4023  * @hw: pointer to the hw struct
4024  * @buff: a virtual buffer to hold the capabilities
4025  * @buff_size: Size of the virtual buffer
4026  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4027  * @list_type_opc: capabilities type to discover - pass in the command opcode
4028  * @cmd_details: pointer to command details structure or NULL
4029  *
4030  * Get the device capabilities descriptions from the firmware
4031  **/
4032 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4033                                 void *buff, u16 buff_size, u16 *data_size,
4034                                 enum i40e_admin_queue_opc list_type_opc,
4035                                 struct i40e_asq_cmd_details *cmd_details)
4036 {
4037         struct i40e_aqc_list_capabilites *cmd;
4038         struct i40e_aq_desc desc;
4039         enum i40e_status_code status = I40E_SUCCESS;
4040
4041         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4042
4043         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4044                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4045                 status = I40E_ERR_PARAM;
4046                 goto exit;
4047         }
4048
4049         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4050
4051         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4052         if (buff_size > I40E_AQ_LARGE_BUF)
4053                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4054
4055         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4056         *data_size = LE16_TO_CPU(desc.datalen);
4057
4058         if (status)
4059                 goto exit;
4060
4061         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4062                                          list_type_opc);
4063
4064 exit:
4065         return status;
4066 }
4067
4068 /**
4069  * i40e_aq_update_nvm
4070  * @hw: pointer to the hw struct
4071  * @module_pointer: module pointer location in words from the NVM beginning
4072  * @offset: byte offset from the module beginning
4073  * @length: length of the section to be written (in bytes from the offset)
4074  * @data: command buffer (size [bytes] = length)
4075  * @last_command: tells if this is the last command in a series
4076  * @preservation_flags: Preservation mode flags
4077  * @cmd_details: pointer to command details structure or NULL
4078  *
4079  * Update the NVM using the admin queue commands
4080  **/
4081 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4082                                 u32 offset, u16 length, void *data,
4083                                 bool last_command, u8 preservation_flags,
4084                                 struct i40e_asq_cmd_details *cmd_details)
4085 {
4086         struct i40e_aq_desc desc;
4087         struct i40e_aqc_nvm_update *cmd =
4088                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4089         enum i40e_status_code status;
4090
4091         DEBUGFUNC("i40e_aq_update_nvm");
4092
4093         /* In offset the highest byte must be zeroed. */
4094         if (offset & 0xFF000000) {
4095                 status = I40E_ERR_PARAM;
4096                 goto i40e_aq_update_nvm_exit;
4097         }
4098
4099         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4100
4101         /* If this is the last command in a series, set the proper flag. */
4102         if (last_command)
4103                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4104         if (hw->mac.type == I40E_MAC_X722) {
4105                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4106                         cmd->command_flags |=
4107                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4108                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4109                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4110                         cmd->command_flags |=
4111                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4112                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4113         }
4114         cmd->module_pointer = module_pointer;
4115         cmd->offset = CPU_TO_LE32(offset);
4116         cmd->length = CPU_TO_LE16(length);
4117
4118         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4119         if (length > I40E_AQ_LARGE_BUF)
4120                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4121
4122         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4123
4124 i40e_aq_update_nvm_exit:
4125         return status;
4126 }
4127
4128 /**
4129  * i40e_aq_get_lldp_mib
4130  * @hw: pointer to the hw struct
4131  * @bridge_type: type of bridge requested
4132  * @mib_type: Local, Remote or both Local and Remote MIBs
4133  * @buff: pointer to a user supplied buffer to store the MIB block
4134  * @buff_size: size of the buffer (in bytes)
4135  * @local_len : length of the returned Local LLDP MIB
4136  * @remote_len: length of the returned Remote LLDP MIB
4137  * @cmd_details: pointer to command details structure or NULL
4138  *
4139  * Requests the complete LLDP MIB (entire packet).
4140  **/
4141 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4142                                 u8 mib_type, void *buff, u16 buff_size,
4143                                 u16 *local_len, u16 *remote_len,
4144                                 struct i40e_asq_cmd_details *cmd_details)
4145 {
4146         struct i40e_aq_desc desc;
4147         struct i40e_aqc_lldp_get_mib *cmd =
4148                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4149         struct i40e_aqc_lldp_get_mib *resp =
4150                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4151         enum i40e_status_code status;
4152
4153         if (buff_size == 0 || !buff)
4154                 return I40E_ERR_PARAM;
4155
4156         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4157         /* Indirect Command */
4158         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4159
4160         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4161         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4162                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4163
4164         desc.datalen = CPU_TO_LE16(buff_size);
4165
4166         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4167         if (buff_size > I40E_AQ_LARGE_BUF)
4168                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4169
4170         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4171         if (!status) {
4172                 if (local_len != NULL)
4173                         *local_len = LE16_TO_CPU(resp->local_len);
4174                 if (remote_len != NULL)
4175                         *remote_len = LE16_TO_CPU(resp->remote_len);
4176         }
4177
4178         return status;
4179 }
4180
4181  /**
4182  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4183  * @hw: pointer to the hw struct
4184  * @mib_type: Local, Remote or both Local and Remote MIBs
4185  * @buff: pointer to a user supplied buffer to store the MIB block
4186  * @buff_size: size of the buffer (in bytes)
4187  * @cmd_details: pointer to command details structure or NULL
4188  *
4189  * Set the LLDP MIB.
4190  **/
4191 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4192                                 u8 mib_type, void *buff, u16 buff_size,
4193                                 struct i40e_asq_cmd_details *cmd_details)
4194 {
4195         struct i40e_aq_desc desc;
4196         struct i40e_aqc_lldp_set_local_mib *cmd =
4197                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4198         enum i40e_status_code status;
4199
4200         if (buff_size == 0 || !buff)
4201                 return I40E_ERR_PARAM;
4202
4203         i40e_fill_default_direct_cmd_desc(&desc,
4204                                 i40e_aqc_opc_lldp_set_local_mib);
4205         /* Indirect Command */
4206         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4207         if (buff_size > I40E_AQ_LARGE_BUF)
4208                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4209         desc.datalen = CPU_TO_LE16(buff_size);
4210
4211         cmd->type = mib_type;
4212         cmd->length = CPU_TO_LE16(buff_size);
4213         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4214         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4215
4216         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4217         return status;
4218 }
4219
4220 /**
4221  * i40e_aq_cfg_lldp_mib_change_event
4222  * @hw: pointer to the hw struct
4223  * @enable_update: Enable or Disable event posting
4224  * @cmd_details: pointer to command details structure or NULL
4225  *
4226  * Enable or Disable posting of an event on ARQ when LLDP MIB
4227  * associated with the interface changes
4228  **/
4229 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4230                                 bool enable_update,
4231                                 struct i40e_asq_cmd_details *cmd_details)
4232 {
4233         struct i40e_aq_desc desc;
4234         struct i40e_aqc_lldp_update_mib *cmd =
4235                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4236         enum i40e_status_code status;
4237
4238         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4239
4240         if (!enable_update)
4241                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4242
4243         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4244
4245         return status;
4246 }
4247
4248 /**
4249  * i40e_aq_add_lldp_tlv
4250  * @hw: pointer to the hw struct
4251  * @bridge_type: type of bridge
4252  * @buff: buffer with TLV to add
4253  * @buff_size: length of the buffer
4254  * @tlv_len: length of the TLV to be added
4255  * @mib_len: length of the LLDP MIB returned in response
4256  * @cmd_details: pointer to command details structure or NULL
4257  *
4258  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4259  * it is responsibility of the caller to make sure that the TLV is not
4260  * already present in the LLDPDU.
4261  * In return firmware will write the complete LLDP MIB with the newly
4262  * added TLV in the response buffer.
4263  **/
4264 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4265                                 void *buff, u16 buff_size, u16 tlv_len,
4266                                 u16 *mib_len,
4267                                 struct i40e_asq_cmd_details *cmd_details)
4268 {
4269         struct i40e_aq_desc desc;
4270         struct i40e_aqc_lldp_add_tlv *cmd =
4271                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4272         enum i40e_status_code status;
4273
4274         if (buff_size == 0 || !buff || tlv_len == 0)
4275                 return I40E_ERR_PARAM;
4276
4277         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4278
4279         /* Indirect Command */
4280         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4281         if (buff_size > I40E_AQ_LARGE_BUF)
4282                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4283         desc.datalen = CPU_TO_LE16(buff_size);
4284
4285         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4286                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4287         cmd->len = CPU_TO_LE16(tlv_len);
4288
4289         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4290         if (!status) {
4291                 if (mib_len != NULL)
4292                         *mib_len = LE16_TO_CPU(desc.datalen);
4293         }
4294
4295         return status;
4296 }
4297
4298 /**
4299  * i40e_aq_update_lldp_tlv
4300  * @hw: pointer to the hw struct
4301  * @bridge_type: type of bridge
4302  * @buff: buffer with TLV to update
4303  * @buff_size: size of the buffer holding original and updated TLVs
4304  * @old_len: Length of the Original TLV
4305  * @new_len: Length of the Updated TLV
4306  * @offset: offset of the updated TLV in the buff
4307  * @mib_len: length of the returned LLDP MIB
4308  * @cmd_details: pointer to command details structure or NULL
4309  *
4310  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4311  * Firmware will place the complete LLDP MIB in response buffer with the
4312  * updated TLV.
4313  **/
4314 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4315                                 u8 bridge_type, void *buff, u16 buff_size,
4316                                 u16 old_len, u16 new_len, u16 offset,
4317                                 u16 *mib_len,
4318                                 struct i40e_asq_cmd_details *cmd_details)
4319 {
4320         struct i40e_aq_desc desc;
4321         struct i40e_aqc_lldp_update_tlv *cmd =
4322                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4323         enum i40e_status_code status;
4324
4325         if (buff_size == 0 || !buff || offset == 0 ||
4326             old_len == 0 || new_len == 0)
4327                 return I40E_ERR_PARAM;
4328
4329         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4330
4331         /* Indirect Command */
4332         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4333         if (buff_size > I40E_AQ_LARGE_BUF)
4334                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4335         desc.datalen = CPU_TO_LE16(buff_size);
4336
4337         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4338                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4339         cmd->old_len = CPU_TO_LE16(old_len);
4340         cmd->new_offset = CPU_TO_LE16(offset);
4341         cmd->new_len = CPU_TO_LE16(new_len);
4342
4343         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4344         if (!status) {
4345                 if (mib_len != NULL)
4346                         *mib_len = LE16_TO_CPU(desc.datalen);
4347         }
4348
4349         return status;
4350 }
4351
4352 /**
4353  * i40e_aq_delete_lldp_tlv
4354  * @hw: pointer to the hw struct
4355  * @bridge_type: type of bridge
4356  * @buff: pointer to a user supplied buffer that has the TLV
4357  * @buff_size: length of the buffer
4358  * @tlv_len: length of the TLV to be deleted
4359  * @mib_len: length of the returned LLDP MIB
4360  * @cmd_details: pointer to command details structure or NULL
4361  *
4362  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4363  * The firmware places the entire LLDP MIB in the response buffer.
4364  **/
4365 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4366                                 u8 bridge_type, void *buff, u16 buff_size,
4367                                 u16 tlv_len, u16 *mib_len,
4368                                 struct i40e_asq_cmd_details *cmd_details)
4369 {
4370         struct i40e_aq_desc desc;
4371         struct i40e_aqc_lldp_add_tlv *cmd =
4372                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4373         enum i40e_status_code status;
4374
4375         if (buff_size == 0 || !buff)
4376                 return I40E_ERR_PARAM;
4377
4378         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4379
4380         /* Indirect Command */
4381         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4382         if (buff_size > I40E_AQ_LARGE_BUF)
4383                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4384         desc.datalen = CPU_TO_LE16(buff_size);
4385         cmd->len = CPU_TO_LE16(tlv_len);
4386         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4387                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4388
4389         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4390         if (!status) {
4391                 if (mib_len != NULL)
4392                         *mib_len = LE16_TO_CPU(desc.datalen);
4393         }
4394
4395         return status;
4396 }
4397
4398 /**
4399  * i40e_aq_stop_lldp
4400  * @hw: pointer to the hw struct
4401  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4402  * @cmd_details: pointer to command details structure or NULL
4403  *
4404  * Stop or Shutdown the embedded LLDP Agent
4405  **/
4406 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4407                                 struct i40e_asq_cmd_details *cmd_details)
4408 {
4409         struct i40e_aq_desc desc;
4410         struct i40e_aqc_lldp_stop *cmd =
4411                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4412         enum i40e_status_code status;
4413
4414         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4415
4416         if (shutdown_agent)
4417                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4418
4419         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4420
4421         return status;
4422 }
4423
4424 /**
4425  * i40e_aq_start_lldp
4426  * @hw: pointer to the hw struct
4427  * @cmd_details: pointer to command details structure or NULL
4428  *
4429  * Start the embedded LLDP Agent on all ports.
4430  **/
4431 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4432                                 struct i40e_asq_cmd_details *cmd_details)
4433 {
4434         struct i40e_aq_desc desc;
4435         struct i40e_aqc_lldp_start *cmd =
4436                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4437         enum i40e_status_code status;
4438
4439         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4440
4441         cmd->command = I40E_AQ_LLDP_AGENT_START;
4442         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4443
4444         return status;
4445 }
4446
4447 /**
4448  * i40e_aq_set_dcb_parameters
4449  * @hw: pointer to the hw struct
4450  * @cmd_details: pointer to command details structure or NULL
4451  * @dcb_enable: True if DCB configuration needs to be applied
4452  *
4453  **/
4454 enum i40e_status_code
4455 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4456                            struct i40e_asq_cmd_details *cmd_details)
4457 {
4458         struct i40e_aq_desc desc;
4459         struct i40e_aqc_set_dcb_parameters *cmd =
4460                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4461         enum i40e_status_code status;
4462
4463         i40e_fill_default_direct_cmd_desc(&desc,
4464                                           i40e_aqc_opc_set_dcb_parameters);
4465
4466         if (dcb_enable) {
4467                 cmd->valid_flags = I40E_DCB_VALID;
4468                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4469         }
4470         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4471
4472         return status;
4473 }
4474
4475 /**
4476  * i40e_aq_get_cee_dcb_config
4477  * @hw: pointer to the hw struct
4478  * @buff: response buffer that stores CEE operational configuration
4479  * @buff_size: size of the buffer passed
4480  * @cmd_details: pointer to command details structure or NULL
4481  *
4482  * Get CEE DCBX mode operational configuration from firmware
4483  **/
4484 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4485                                 void *buff, u16 buff_size,
4486                                 struct i40e_asq_cmd_details *cmd_details)
4487 {
4488         struct i40e_aq_desc desc;
4489         enum i40e_status_code status;
4490
4491         if (buff_size == 0 || !buff)
4492                 return I40E_ERR_PARAM;
4493
4494         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4495
4496         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4497         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4498                                        cmd_details);
4499
4500         return status;
4501 }
4502
4503 /**
4504  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4505  * @hw: pointer to the hw struct
4506  * @start_agent: True if DCBx Agent needs to be Started
4507  *                              False if DCBx Agent needs to be Stopped
4508  * @cmd_details: pointer to command details structure or NULL
4509  *
4510  * Start/Stop the embedded dcbx Agent
4511  **/
4512 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4513                                 bool start_agent,
4514                                 struct i40e_asq_cmd_details *cmd_details)
4515 {
4516         struct i40e_aq_desc desc;
4517         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4518                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4519                                 &desc.params.raw;
4520         enum i40e_status_code status;
4521
4522         i40e_fill_default_direct_cmd_desc(&desc,
4523                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4524
4525         if (start_agent)
4526                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4527
4528         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4529
4530         return status;
4531 }
4532
4533 /**
4534  * i40e_aq_add_udp_tunnel
4535  * @hw: pointer to the hw struct
4536  * @udp_port: the UDP port to add in Host byte order
4537  * @protocol_index: protocol index type
4538  * @filter_index: pointer to filter index
4539  * @cmd_details: pointer to command details structure or NULL
4540  *
4541  * Note: Firmware expects the udp_port value to be in Little Endian format,
4542  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4543  * Little Endian order.
4544  **/
4545 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4546                                 u16 udp_port, u8 protocol_index,
4547                                 u8 *filter_index,
4548                                 struct i40e_asq_cmd_details *cmd_details)
4549 {
4550         struct i40e_aq_desc desc;
4551         struct i40e_aqc_add_udp_tunnel *cmd =
4552                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4553         struct i40e_aqc_del_udp_tunnel_completion *resp =
4554                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4555         enum i40e_status_code status;
4556
4557         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4558
4559         cmd->udp_port = CPU_TO_LE16(udp_port);
4560         cmd->protocol_type = protocol_index;
4561
4562         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4563
4564         if (!status && filter_index)
4565                 *filter_index = resp->index;
4566
4567         return status;
4568 }
4569
4570 /**
4571  * i40e_aq_del_udp_tunnel
4572  * @hw: pointer to the hw struct
4573  * @index: filter index
4574  * @cmd_details: pointer to command details structure or NULL
4575  **/
4576 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4577                                 struct i40e_asq_cmd_details *cmd_details)
4578 {
4579         struct i40e_aq_desc desc;
4580         struct i40e_aqc_remove_udp_tunnel *cmd =
4581                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4582         enum i40e_status_code status;
4583
4584         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4585
4586         cmd->index = index;
4587
4588         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4589
4590         return status;
4591 }
4592
4593 /**
4594  * i40e_aq_get_switch_resource_alloc (0x0204)
4595  * @hw: pointer to the hw struct
4596  * @num_entries: pointer to u8 to store the number of resource entries returned
4597  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4598  *        to store the resource information for all resource types.  Each
4599  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4600  * @count: size, in bytes, of the buffer provided
4601  * @cmd_details: pointer to command details structure or NULL
4602  *
4603  * Query the resources allocated to a function.
4604  **/
4605 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4606                         u8 *num_entries,
4607                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4608                         u16 count,
4609                         struct i40e_asq_cmd_details *cmd_details)
4610 {
4611         struct i40e_aq_desc desc;
4612         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4613                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4614         enum i40e_status_code status;
4615         u16 length = count * sizeof(*buf);
4616
4617         i40e_fill_default_direct_cmd_desc(&desc,
4618                                         i40e_aqc_opc_get_switch_resource_alloc);
4619
4620         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4621         if (length > I40E_AQ_LARGE_BUF)
4622                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4623
4624         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4625
4626         if (!status && num_entries)
4627                 *num_entries = cmd_resp->num_entries;
4628
4629         return status;
4630 }
4631
4632 /**
4633  * i40e_aq_delete_element - Delete switch element
4634  * @hw: pointer to the hw struct
4635  * @seid: the SEID to delete from the switch
4636  * @cmd_details: pointer to command details structure or NULL
4637  *
4638  * This deletes a switch element from the switch.
4639  **/
4640 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4641                                 struct i40e_asq_cmd_details *cmd_details)
4642 {
4643         struct i40e_aq_desc desc;
4644         struct i40e_aqc_switch_seid *cmd =
4645                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4646         enum i40e_status_code status;
4647
4648         if (seid == 0)
4649                 return I40E_ERR_PARAM;
4650
4651         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4652
4653         cmd->seid = CPU_TO_LE16(seid);
4654
4655         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4656
4657         return status;
4658 }
4659
4660 /**
4661  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4662  * @hw: pointer to the hw struct
4663  * @flags: component flags
4664  * @mac_seid: uplink seid (MAC SEID)
4665  * @vsi_seid: connected vsi seid
4666  * @ret_seid: seid of create pv component
4667  *
4668  * This instantiates an i40e port virtualizer with specified flags.
4669  * Depending on specified flags the port virtualizer can act as a
4670  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4671  */
4672 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4673                                        u16 mac_seid, u16 vsi_seid,
4674                                        u16 *ret_seid)
4675 {
4676         struct i40e_aq_desc desc;
4677         struct i40e_aqc_add_update_pv *cmd =
4678                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4679         struct i40e_aqc_add_update_pv_completion *resp =
4680                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4681         enum i40e_status_code status;
4682
4683         if (vsi_seid == 0)
4684                 return I40E_ERR_PARAM;
4685
4686         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4687         cmd->command_flags = CPU_TO_LE16(flags);
4688         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4689         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4690
4691         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4692         if (!status && ret_seid)
4693                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4694
4695         return status;
4696 }
4697
4698 /**
4699  * i40e_aq_add_tag - Add an S/E-tag
4700  * @hw: pointer to the hw struct
4701  * @direct_to_queue: should s-tag direct flow to a specific queue
4702  * @vsi_seid: VSI SEID to use this tag
4703  * @tag: value of the tag
4704  * @queue_num: queue number, only valid is direct_to_queue is true
4705  * @tags_used: return value, number of tags in use by this PF
4706  * @tags_free: return value, number of unallocated tags
4707  * @cmd_details: pointer to command details structure or NULL
4708  *
4709  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4710  * the number of tags allocated by the PF, and the number of unallocated
4711  * tags available.
4712  **/
4713 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4714                                 u16 vsi_seid, u16 tag, u16 queue_num,
4715                                 u16 *tags_used, u16 *tags_free,
4716                                 struct i40e_asq_cmd_details *cmd_details)
4717 {
4718         struct i40e_aq_desc desc;
4719         struct i40e_aqc_add_tag *cmd =
4720                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4721         struct i40e_aqc_add_remove_tag_completion *resp =
4722                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4723         enum i40e_status_code status;
4724
4725         if (vsi_seid == 0)
4726                 return I40E_ERR_PARAM;
4727
4728         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4729
4730         cmd->seid = CPU_TO_LE16(vsi_seid);
4731         cmd->tag = CPU_TO_LE16(tag);
4732         if (direct_to_queue) {
4733                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4734                 cmd->queue_number = CPU_TO_LE16(queue_num);
4735         }
4736
4737         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4738
4739         if (!status) {
4740                 if (tags_used != NULL)
4741                         *tags_used = LE16_TO_CPU(resp->tags_used);
4742                 if (tags_free != NULL)
4743                         *tags_free = LE16_TO_CPU(resp->tags_free);
4744         }
4745
4746         return status;
4747 }
4748
4749 /**
4750  * i40e_aq_remove_tag - Remove an S- or E-tag
4751  * @hw: pointer to the hw struct
4752  * @vsi_seid: VSI SEID this tag is associated with
4753  * @tag: value of the S-tag to delete
4754  * @tags_used: return value, number of tags in use by this PF
4755  * @tags_free: return value, number of unallocated tags
4756  * @cmd_details: pointer to command details structure or NULL
4757  *
4758  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4759  * the number of tags allocated by the PF, and the number of unallocated
4760  * tags available.
4761  **/
4762 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4763                                 u16 tag, u16 *tags_used, u16 *tags_free,
4764                                 struct i40e_asq_cmd_details *cmd_details)
4765 {
4766         struct i40e_aq_desc desc;
4767         struct i40e_aqc_remove_tag *cmd =
4768                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4769         struct i40e_aqc_add_remove_tag_completion *resp =
4770                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4771         enum i40e_status_code status;
4772
4773         if (vsi_seid == 0)
4774                 return I40E_ERR_PARAM;
4775
4776         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4777
4778         cmd->seid = CPU_TO_LE16(vsi_seid);
4779         cmd->tag = CPU_TO_LE16(tag);
4780
4781         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4782
4783         if (!status) {
4784                 if (tags_used != NULL)
4785                         *tags_used = LE16_TO_CPU(resp->tags_used);
4786                 if (tags_free != NULL)
4787                         *tags_free = LE16_TO_CPU(resp->tags_free);
4788         }
4789
4790         return status;
4791 }
4792
4793 /**
4794  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4795  * @hw: pointer to the hw struct
4796  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4797  * @etag: value of E-tag to add
4798  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4799  * @buf: address of indirect buffer
4800  * @tags_used: return value, number of E-tags in use by this port
4801  * @tags_free: return value, number of unallocated M-tags
4802  * @cmd_details: pointer to command details structure or NULL
4803  *
4804  * This associates a multicast E-tag to a port virtualizer.  It will return
4805  * the number of tags allocated by the PF, and the number of unallocated
4806  * tags available.
4807  *
4808  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4809  * num_tags_in_buf long.
4810  **/
4811 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4812                                 u16 etag, u8 num_tags_in_buf, void *buf,
4813                                 u16 *tags_used, u16 *tags_free,
4814                                 struct i40e_asq_cmd_details *cmd_details)
4815 {
4816         struct i40e_aq_desc desc;
4817         struct i40e_aqc_add_remove_mcast_etag *cmd =
4818                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4819         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4820            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4821         enum i40e_status_code status;
4822         u16 length = sizeof(u16) * num_tags_in_buf;
4823
4824         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4825                 return I40E_ERR_PARAM;
4826
4827         i40e_fill_default_direct_cmd_desc(&desc,
4828                                           i40e_aqc_opc_add_multicast_etag);
4829
4830         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4831         cmd->etag = CPU_TO_LE16(etag);
4832         cmd->num_unicast_etags = num_tags_in_buf;
4833
4834         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4835         if (length > I40E_AQ_LARGE_BUF)
4836                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4837
4838         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4839
4840         if (!status) {
4841                 if (tags_used != NULL)
4842                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4843                 if (tags_free != NULL)
4844                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4845         }
4846
4847         return status;
4848 }
4849
4850 /**
4851  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4852  * @hw: pointer to the hw struct
4853  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4854  * @etag: value of the E-tag to remove
4855  * @tags_used: return value, number of tags in use by this port
4856  * @tags_free: return value, number of unallocated tags
4857  * @cmd_details: pointer to command details structure or NULL
4858  *
4859  * This deletes an E-tag from the port virtualizer.  It will return
4860  * the number of tags allocated by the port, and the number of unallocated
4861  * tags available.
4862  **/
4863 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4864                                 u16 etag, u16 *tags_used, u16 *tags_free,
4865                                 struct i40e_asq_cmd_details *cmd_details)
4866 {
4867         struct i40e_aq_desc desc;
4868         struct i40e_aqc_add_remove_mcast_etag *cmd =
4869                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4870         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4871            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4872         enum i40e_status_code status;
4873
4874
4875         if (pv_seid == 0)
4876                 return I40E_ERR_PARAM;
4877
4878         i40e_fill_default_direct_cmd_desc(&desc,
4879                                           i40e_aqc_opc_remove_multicast_etag);
4880
4881         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4882         cmd->etag = CPU_TO_LE16(etag);
4883
4884         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4885
4886         if (!status) {
4887                 if (tags_used != NULL)
4888                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4889                 if (tags_free != NULL)
4890                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4891         }
4892
4893         return status;
4894 }
4895
4896 /**
4897  * i40e_aq_update_tag - Update an S/E-tag
4898  * @hw: pointer to the hw struct
4899  * @vsi_seid: VSI SEID using this S-tag
4900  * @old_tag: old tag value
4901  * @new_tag: new tag value
4902  * @tags_used: return value, number of tags in use by this PF
4903  * @tags_free: return value, number of unallocated tags
4904  * @cmd_details: pointer to command details structure or NULL
4905  *
4906  * This updates the value of the tag currently attached to this VSI
4907  * in the switch complex.  It will return the number of tags allocated
4908  * by the PF, and the number of unallocated tags available.
4909  **/
4910 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4911                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4912                                 u16 *tags_free,
4913                                 struct i40e_asq_cmd_details *cmd_details)
4914 {
4915         struct i40e_aq_desc desc;
4916         struct i40e_aqc_update_tag *cmd =
4917                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4918         struct i40e_aqc_update_tag_completion *resp =
4919                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4920         enum i40e_status_code status;
4921
4922         if (vsi_seid == 0)
4923                 return I40E_ERR_PARAM;
4924
4925         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4926
4927         cmd->seid = CPU_TO_LE16(vsi_seid);
4928         cmd->old_tag = CPU_TO_LE16(old_tag);
4929         cmd->new_tag = CPU_TO_LE16(new_tag);
4930
4931         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4932
4933         if (!status) {
4934                 if (tags_used != NULL)
4935                         *tags_used = LE16_TO_CPU(resp->tags_used);
4936                 if (tags_free != NULL)
4937                         *tags_free = LE16_TO_CPU(resp->tags_free);
4938         }
4939
4940         return status;
4941 }
4942
4943 /**
4944  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4945  * @hw: pointer to the hw struct
4946  * @tcmap: TC map for request/release any ignore PFC condition
4947  * @request: request or release ignore PFC condition
4948  * @tcmap_ret: return TCs for which PFC is currently ignored
4949  * @cmd_details: pointer to command details structure or NULL
4950  *
4951  * This sends out request/release to ignore PFC condition for a TC.
4952  * It will return the TCs for which PFC is currently ignored.
4953  **/
4954 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4955                                 bool request, u8 *tcmap_ret,
4956                                 struct i40e_asq_cmd_details *cmd_details)
4957 {
4958         struct i40e_aq_desc desc;
4959         struct i40e_aqc_pfc_ignore *cmd_resp =
4960                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4961         enum i40e_status_code status;
4962
4963         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4964
4965         if (request)
4966                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4967
4968         cmd_resp->tc_bitmap = tcmap;
4969
4970         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4971
4972         if (!status) {
4973                 if (tcmap_ret != NULL)
4974                         *tcmap_ret = cmd_resp->tc_bitmap;
4975         }
4976
4977         return status;
4978 }
4979
4980 /**
4981  * i40e_aq_dcb_updated - DCB Updated Command
4982  * @hw: pointer to the hw struct
4983  * @cmd_details: pointer to command details structure or NULL
4984  *
4985  * When LLDP is handled in PF this command is used by the PF
4986  * to notify EMP that a DCB setting is modified.
4987  * When LLDP is handled in EMP this command is used by the PF
4988  * to notify EMP whenever one of the following parameters get
4989  * modified:
4990  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4991  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4992  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4993  * EMP will return when the shared RPB settings have been
4994  * recomputed and modified. The retval field in the descriptor
4995  * will be set to 0 when RPB is modified.
4996  **/
4997 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4998                                 struct i40e_asq_cmd_details *cmd_details)
4999 {
5000         struct i40e_aq_desc desc;
5001         enum i40e_status_code status;
5002
5003         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5004
5005         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5006
5007         return status;
5008 }
5009
5010 /**
5011  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5012  * @hw: pointer to the hw struct
5013  * @seid: defines the SEID of the switch for which the stats are requested
5014  * @vlan_id: the VLAN ID for which the statistics are requested
5015  * @stat_index: index of the statistics counters block assigned to this VLAN
5016  * @cmd_details: pointer to command details structure or NULL
5017  *
5018  * XL710 supports 128 smonVlanStats counters.This command is used to
5019  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5020  * switch.
5021  **/
5022 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5023                                 u16 vlan_id, u16 *stat_index,
5024                                 struct i40e_asq_cmd_details *cmd_details)
5025 {
5026         struct i40e_aq_desc desc;
5027         struct i40e_aqc_add_remove_statistics *cmd_resp =
5028                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5029         enum i40e_status_code status;
5030
5031         if ((seid == 0) || (stat_index == NULL))
5032                 return I40E_ERR_PARAM;
5033
5034         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5035
5036         cmd_resp->seid = CPU_TO_LE16(seid);
5037         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5038
5039         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5040
5041         if (!status && stat_index)
5042                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5043
5044         return status;
5045 }
5046
5047 /**
5048  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5049  * @hw: pointer to the hw struct
5050  * @seid: defines the SEID of the switch for which the stats are requested
5051  * @vlan_id: the VLAN ID for which the statistics are requested
5052  * @stat_index: index of the statistics counters block assigned to this VLAN
5053  * @cmd_details: pointer to command details structure or NULL
5054  *
5055  * XL710 supports 128 smonVlanStats counters.This command is used to
5056  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5057  * switch.
5058  **/
5059 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5060                                 u16 vlan_id, u16 stat_index,
5061                                 struct i40e_asq_cmd_details *cmd_details)
5062 {
5063         struct i40e_aq_desc desc;
5064         struct i40e_aqc_add_remove_statistics *cmd =
5065                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5066         enum i40e_status_code status;
5067
5068         if (seid == 0)
5069                 return I40E_ERR_PARAM;
5070
5071         i40e_fill_default_direct_cmd_desc(&desc,
5072                                           i40e_aqc_opc_remove_statistics);
5073
5074         cmd->seid = CPU_TO_LE16(seid);
5075         cmd->vlan  = CPU_TO_LE16(vlan_id);
5076         cmd->stat_index = CPU_TO_LE16(stat_index);
5077
5078         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5079
5080         return status;
5081 }
5082
5083 /**
5084  * i40e_aq_set_port_parameters - set physical port parameters.
5085  * @hw: pointer to the hw struct
5086  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5087  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5088  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5089  * @double_vlan: if set double VLAN is enabled
5090  * @cmd_details: pointer to command details structure or NULL
5091  **/
5092 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5093                                 u16 bad_frame_vsi, bool save_bad_pac,
5094                                 bool pad_short_pac, bool double_vlan,
5095                                 struct i40e_asq_cmd_details *cmd_details)
5096 {
5097         struct i40e_aqc_set_port_parameters *cmd;
5098         enum i40e_status_code status;
5099         struct i40e_aq_desc desc;
5100         u16 command_flags = 0;
5101
5102         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5103
5104         i40e_fill_default_direct_cmd_desc(&desc,
5105                                           i40e_aqc_opc_set_port_parameters);
5106
5107         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5108         if (save_bad_pac)
5109                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5110         if (pad_short_pac)
5111                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5112         if (double_vlan)
5113                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5114         cmd->command_flags = CPU_TO_LE16(command_flags);
5115
5116         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5117
5118         return status;
5119 }
5120
5121 /**
5122  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5123  * @hw: pointer to the hw struct
5124  * @seid: seid for the physical port/switching component/vsi
5125  * @buff: Indirect buffer to hold data parameters and response
5126  * @buff_size: Indirect buffer size
5127  * @opcode: Tx scheduler AQ command opcode
5128  * @cmd_details: pointer to command details structure or NULL
5129  *
5130  * Generic command handler for Tx scheduler AQ commands
5131  **/
5132 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5133                                 void *buff, u16 buff_size,
5134                                  enum i40e_admin_queue_opc opcode,
5135                                 struct i40e_asq_cmd_details *cmd_details)
5136 {
5137         struct i40e_aq_desc desc;
5138         struct i40e_aqc_tx_sched_ind *cmd =
5139                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5140         enum i40e_status_code status;
5141         bool cmd_param_flag = false;
5142
5143         switch (opcode) {
5144         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5145         case i40e_aqc_opc_configure_vsi_tc_bw:
5146         case i40e_aqc_opc_enable_switching_comp_ets:
5147         case i40e_aqc_opc_modify_switching_comp_ets:
5148         case i40e_aqc_opc_disable_switching_comp_ets:
5149         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5150         case i40e_aqc_opc_configure_switching_comp_bw_config:
5151                 cmd_param_flag = true;
5152                 break;
5153         case i40e_aqc_opc_query_vsi_bw_config:
5154         case i40e_aqc_opc_query_vsi_ets_sla_config:
5155         case i40e_aqc_opc_query_switching_comp_ets_config:
5156         case i40e_aqc_opc_query_port_ets_config:
5157         case i40e_aqc_opc_query_switching_comp_bw_config:
5158                 cmd_param_flag = false;
5159                 break;
5160         default:
5161                 return I40E_ERR_PARAM;
5162         }
5163
5164         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5165
5166         /* Indirect command */
5167         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5168         if (cmd_param_flag)
5169                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5170         if (buff_size > I40E_AQ_LARGE_BUF)
5171                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5172
5173         desc.datalen = CPU_TO_LE16(buff_size);
5174
5175         cmd->vsi_seid = CPU_TO_LE16(seid);
5176
5177         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5178
5179         return status;
5180 }
5181
5182 /**
5183  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5184  * @hw: pointer to the hw struct
5185  * @seid: VSI seid
5186  * @credit: BW limit credits (0 = disabled)
5187  * @max_credit: Max BW limit credits
5188  * @cmd_details: pointer to command details structure or NULL
5189  **/
5190 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5191                                 u16 seid, u16 credit, u8 max_credit,
5192                                 struct i40e_asq_cmd_details *cmd_details)
5193 {
5194         struct i40e_aq_desc desc;
5195         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5196                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5197         enum i40e_status_code status;
5198
5199         i40e_fill_default_direct_cmd_desc(&desc,
5200                                           i40e_aqc_opc_configure_vsi_bw_limit);
5201
5202         cmd->vsi_seid = CPU_TO_LE16(seid);
5203         cmd->credit = CPU_TO_LE16(credit);
5204         cmd->max_credit = max_credit;
5205
5206         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5207
5208         return status;
5209 }
5210
5211 /**
5212  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5213  * @hw: pointer to the hw struct
5214  * @seid: switching component seid
5215  * @credit: BW limit credits (0 = disabled)
5216  * @max_bw: Max BW limit credits
5217  * @cmd_details: pointer to command details structure or NULL
5218  **/
5219 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5220                                 u16 seid, u16 credit, u8 max_bw,
5221                                 struct i40e_asq_cmd_details *cmd_details)
5222 {
5223         struct i40e_aq_desc desc;
5224         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5225           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5226         enum i40e_status_code status;
5227
5228         i40e_fill_default_direct_cmd_desc(&desc,
5229                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5230
5231         cmd->seid = CPU_TO_LE16(seid);
5232         cmd->credit = CPU_TO_LE16(credit);
5233         cmd->max_bw = max_bw;
5234
5235         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5236
5237         return status;
5238 }
5239
5240 /**
5241  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5242  * @hw: pointer to the hw struct
5243  * @seid: VSI seid
5244  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5245  * @cmd_details: pointer to command details structure or NULL
5246  **/
5247 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5248                         u16 seid,
5249                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5250                         struct i40e_asq_cmd_details *cmd_details)
5251 {
5252         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5253                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5254                                     cmd_details);
5255 }
5256
5257 /**
5258  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5259  * @hw: pointer to the hw struct
5260  * @seid: VSI seid
5261  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5262  * @cmd_details: pointer to command details structure or NULL
5263  **/
5264 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5265                         u16 seid,
5266                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5267                         struct i40e_asq_cmd_details *cmd_details)
5268 {
5269         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5270                                     i40e_aqc_opc_configure_vsi_tc_bw,
5271                                     cmd_details);
5272 }
5273
5274 /**
5275  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5276  * @hw: pointer to the hw struct
5277  * @seid: seid of the switching component connected to Physical Port
5278  * @ets_data: Buffer holding ETS parameters
5279  * @opcode: Tx scheduler AQ command opcode
5280  * @cmd_details: pointer to command details structure or NULL
5281  **/
5282 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5283                 u16 seid,
5284                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5285                 enum i40e_admin_queue_opc opcode,
5286                 struct i40e_asq_cmd_details *cmd_details)
5287 {
5288         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5289                                     sizeof(*ets_data), opcode, cmd_details);
5290 }
5291
5292 /**
5293  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5294  * @hw: pointer to the hw struct
5295  * @seid: seid of the switching component
5296  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5297  * @cmd_details: pointer to command details structure or NULL
5298  **/
5299 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5300         u16 seid,
5301         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5302         struct i40e_asq_cmd_details *cmd_details)
5303 {
5304         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5305                             i40e_aqc_opc_configure_switching_comp_bw_config,
5306                             cmd_details);
5307 }
5308
5309 /**
5310  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5311  * @hw: pointer to the hw struct
5312  * @seid: seid of the switching component
5313  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5314  * @cmd_details: pointer to command details structure or NULL
5315  **/
5316 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5317         struct i40e_hw *hw, u16 seid,
5318         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5319         struct i40e_asq_cmd_details *cmd_details)
5320 {
5321         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5322                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5323                             cmd_details);
5324 }
5325
5326 /**
5327  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5328  * @hw: pointer to the hw struct
5329  * @seid: seid of the VSI
5330  * @bw_data: Buffer to hold VSI BW configuration
5331  * @cmd_details: pointer to command details structure or NULL
5332  **/
5333 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5334                         u16 seid,
5335                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5336                         struct i40e_asq_cmd_details *cmd_details)
5337 {
5338         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5339                                     i40e_aqc_opc_query_vsi_bw_config,
5340                                     cmd_details);
5341 }
5342
5343 /**
5344  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5345  * @hw: pointer to the hw struct
5346  * @seid: seid of the VSI
5347  * @bw_data: Buffer to hold VSI BW configuration per TC
5348  * @cmd_details: pointer to command details structure or NULL
5349  **/
5350 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5351                         u16 seid,
5352                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5353                         struct i40e_asq_cmd_details *cmd_details)
5354 {
5355         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5356                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5357                                     cmd_details);
5358 }
5359
5360 /**
5361  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5362  * @hw: pointer to the hw struct
5363  * @seid: seid of the switching component
5364  * @bw_data: Buffer to hold switching component's per TC BW config
5365  * @cmd_details: pointer to command details structure or NULL
5366  **/
5367 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5368                 u16 seid,
5369                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5370                 struct i40e_asq_cmd_details *cmd_details)
5371 {
5372         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5373                                    i40e_aqc_opc_query_switching_comp_ets_config,
5374                                    cmd_details);
5375 }
5376
5377 /**
5378  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5379  * @hw: pointer to the hw struct
5380  * @seid: seid of the VSI or switching component connected to Physical Port
5381  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5382  * @cmd_details: pointer to command details structure or NULL
5383  **/
5384 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5385                         u16 seid,
5386                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5387                         struct i40e_asq_cmd_details *cmd_details)
5388 {
5389         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5390                                     i40e_aqc_opc_query_port_ets_config,
5391                                     cmd_details);
5392 }
5393
5394 /**
5395  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5396  * @hw: pointer to the hw struct
5397  * @seid: seid of the switching component
5398  * @bw_data: Buffer to hold switching component's BW configuration
5399  * @cmd_details: pointer to command details structure or NULL
5400  **/
5401 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5402                 u16 seid,
5403                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5404                 struct i40e_asq_cmd_details *cmd_details)
5405 {
5406         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5407                                     i40e_aqc_opc_query_switching_comp_bw_config,
5408                                     cmd_details);
5409 }
5410
5411 /**
5412  * i40e_validate_filter_settings
5413  * @hw: pointer to the hardware structure
5414  * @settings: Filter control settings
5415  *
5416  * Check and validate the filter control settings passed.
5417  * The function checks for the valid filter/context sizes being
5418  * passed for FCoE and PE.
5419  *
5420  * Returns I40E_SUCCESS if the values passed are valid and within
5421  * range else returns an error.
5422  **/
5423 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5424                                 struct i40e_filter_control_settings *settings)
5425 {
5426         u32 fcoe_cntx_size, fcoe_filt_size;
5427         u32 pe_cntx_size, pe_filt_size;
5428         u32 fcoe_fmax;
5429
5430         u32 val;
5431
5432         /* Validate FCoE settings passed */
5433         switch (settings->fcoe_filt_num) {
5434         case I40E_HASH_FILTER_SIZE_1K:
5435         case I40E_HASH_FILTER_SIZE_2K:
5436         case I40E_HASH_FILTER_SIZE_4K:
5437         case I40E_HASH_FILTER_SIZE_8K:
5438         case I40E_HASH_FILTER_SIZE_16K:
5439         case I40E_HASH_FILTER_SIZE_32K:
5440                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5441                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5442                 break;
5443         default:
5444                 return I40E_ERR_PARAM;
5445         }
5446
5447         switch (settings->fcoe_cntx_num) {
5448         case I40E_DMA_CNTX_SIZE_512:
5449         case I40E_DMA_CNTX_SIZE_1K:
5450         case I40E_DMA_CNTX_SIZE_2K:
5451         case I40E_DMA_CNTX_SIZE_4K:
5452                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5453                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5454                 break;
5455         default:
5456                 return I40E_ERR_PARAM;
5457         }
5458
5459         /* Validate PE settings passed */
5460         switch (settings->pe_filt_num) {
5461         case I40E_HASH_FILTER_SIZE_1K:
5462         case I40E_HASH_FILTER_SIZE_2K:
5463         case I40E_HASH_FILTER_SIZE_4K:
5464         case I40E_HASH_FILTER_SIZE_8K:
5465         case I40E_HASH_FILTER_SIZE_16K:
5466         case I40E_HASH_FILTER_SIZE_32K:
5467         case I40E_HASH_FILTER_SIZE_64K:
5468         case I40E_HASH_FILTER_SIZE_128K:
5469         case I40E_HASH_FILTER_SIZE_256K:
5470         case I40E_HASH_FILTER_SIZE_512K:
5471         case I40E_HASH_FILTER_SIZE_1M:
5472                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5473                 pe_filt_size <<= (u32)settings->pe_filt_num;
5474                 break;
5475         default:
5476                 return I40E_ERR_PARAM;
5477         }
5478
5479         switch (settings->pe_cntx_num) {
5480         case I40E_DMA_CNTX_SIZE_512:
5481         case I40E_DMA_CNTX_SIZE_1K:
5482         case I40E_DMA_CNTX_SIZE_2K:
5483         case I40E_DMA_CNTX_SIZE_4K:
5484         case I40E_DMA_CNTX_SIZE_8K:
5485         case I40E_DMA_CNTX_SIZE_16K:
5486         case I40E_DMA_CNTX_SIZE_32K:
5487         case I40E_DMA_CNTX_SIZE_64K:
5488         case I40E_DMA_CNTX_SIZE_128K:
5489         case I40E_DMA_CNTX_SIZE_256K:
5490                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5491                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5492                 break;
5493         default:
5494                 return I40E_ERR_PARAM;
5495         }
5496
5497         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5498         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5499         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5500                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5501         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5502                 return I40E_ERR_INVALID_SIZE;
5503
5504         return I40E_SUCCESS;
5505 }
5506
5507 /**
5508  * i40e_set_filter_control
5509  * @hw: pointer to the hardware structure
5510  * @settings: Filter control settings
5511  *
5512  * Set the Queue Filters for PE/FCoE and enable filters required
5513  * for a single PF. It is expected that these settings are programmed
5514  * at the driver initialization time.
5515  **/
5516 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5517                                 struct i40e_filter_control_settings *settings)
5518 {
5519         enum i40e_status_code ret = I40E_SUCCESS;
5520         u32 hash_lut_size = 0;
5521         u32 val;
5522
5523         if (!settings)
5524                 return I40E_ERR_PARAM;
5525
5526         /* Validate the input settings */
5527         ret = i40e_validate_filter_settings(hw, settings);
5528         if (ret)
5529                 return ret;
5530
5531         /* Read the PF Queue Filter control register */
5532         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5533
5534         /* Program required PE hash buckets for the PF */
5535         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5536         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5537                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5538         /* Program required PE contexts for the PF */
5539         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5540         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5541                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5542
5543         /* Program required FCoE hash buckets for the PF */
5544         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5545         val |= ((u32)settings->fcoe_filt_num <<
5546                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5547                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5548         /* Program required FCoE DDP contexts for the PF */
5549         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5550         val |= ((u32)settings->fcoe_cntx_num <<
5551                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5552                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5553
5554         /* Program Hash LUT size for the PF */
5555         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5556         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5557                 hash_lut_size = 1;
5558         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5559                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5560
5561         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5562         if (settings->enable_fdir)
5563                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5564         if (settings->enable_ethtype)
5565                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5566         if (settings->enable_macvlan)
5567                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5568
5569         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5570
5571         return I40E_SUCCESS;
5572 }
5573
5574 /**
5575  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5576  * @hw: pointer to the hw struct
5577  * @mac_addr: MAC address to use in the filter
5578  * @ethtype: Ethertype to use in the filter
5579  * @flags: Flags that needs to be applied to the filter
5580  * @vsi_seid: seid of the control VSI
5581  * @queue: VSI queue number to send the packet to
5582  * @is_add: Add control packet filter if True else remove
5583  * @stats: Structure to hold information on control filter counts
5584  * @cmd_details: pointer to command details structure or NULL
5585  *
5586  * This command will Add or Remove control packet filter for a control VSI.
5587  * In return it will update the total number of perfect filter count in
5588  * the stats member.
5589  **/
5590 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5591                                 u8 *mac_addr, u16 ethtype, u16 flags,
5592                                 u16 vsi_seid, u16 queue, bool is_add,
5593                                 struct i40e_control_filter_stats *stats,
5594                                 struct i40e_asq_cmd_details *cmd_details)
5595 {
5596         struct i40e_aq_desc desc;
5597         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5598                 (struct i40e_aqc_add_remove_control_packet_filter *)
5599                 &desc.params.raw;
5600         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5601                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5602                 &desc.params.raw;
5603         enum i40e_status_code status;
5604
5605         if (vsi_seid == 0)
5606                 return I40E_ERR_PARAM;
5607
5608         if (is_add) {
5609                 i40e_fill_default_direct_cmd_desc(&desc,
5610                                 i40e_aqc_opc_add_control_packet_filter);
5611                 cmd->queue = CPU_TO_LE16(queue);
5612         } else {
5613                 i40e_fill_default_direct_cmd_desc(&desc,
5614                                 i40e_aqc_opc_remove_control_packet_filter);
5615         }
5616
5617         if (mac_addr)
5618                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5619                             I40E_NONDMA_TO_NONDMA);
5620
5621         cmd->etype = CPU_TO_LE16(ethtype);
5622         cmd->flags = CPU_TO_LE16(flags);
5623         cmd->seid = CPU_TO_LE16(vsi_seid);
5624
5625         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5626
5627         if (!status && stats) {
5628                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5629                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5630                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5631                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5632         }
5633
5634         return status;
5635 }
5636
5637 /**
5638  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5639  * @hw: pointer to the hw struct
5640  * @seid: VSI seid to add ethertype filter from
5641  **/
5642 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5643                                                     u16 seid)
5644 {
5645 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5646         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5647                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5648                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5649         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5650         enum i40e_status_code status;
5651
5652         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5653                                                        seid, 0, true, NULL,
5654                                                        NULL);
5655         if (status)
5656                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5657 }
5658
5659 /**
5660  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5661  * @filters: list of cloud filters
5662  * @filter_count: length of list
5663  *
5664  * There's an issue in the device where the Geneve VNI layout needs
5665  * to be shifted 1 byte over from the VxLAN VNI
5666  **/
5667 STATIC void i40e_fix_up_geneve_vni(
5668         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5669         u8 filter_count)
5670 {
5671         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5672         int i;
5673
5674         for (i = 0; i < filter_count; i++) {
5675                 u16 tnl_type;
5676                 u32 ti;
5677
5678                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5679                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5680                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5681                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5682                         ti = LE32_TO_CPU(f[i].tenant_id);
5683                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5684                 }
5685         }
5686 }
5687
5688 /**
5689  * i40e_aq_add_cloud_filters
5690  * @hw: pointer to the hardware structure
5691  * @seid: VSI seid to add cloud filters from
5692  * @filters: Buffer which contains the filters to be added
5693  * @filter_count: number of filters contained in the buffer
5694  *
5695  * Set the cloud filters for a given VSI.  The contents of the
5696  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5697  * in by the caller of the function.
5698  *
5699  **/
5700 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5701         u16 seid,
5702         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5703         u8 filter_count)
5704 {
5705         struct i40e_aq_desc desc;
5706         struct i40e_aqc_add_remove_cloud_filters *cmd =
5707         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5708         enum i40e_status_code status;
5709         u16 buff_len;
5710
5711         i40e_fill_default_direct_cmd_desc(&desc,
5712                                           i40e_aqc_opc_add_cloud_filters);
5713
5714         buff_len = filter_count * sizeof(*filters);
5715         desc.datalen = CPU_TO_LE16(buff_len);
5716         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5717         cmd->num_filters = filter_count;
5718         cmd->seid = CPU_TO_LE16(seid);
5719
5720         i40e_fix_up_geneve_vni(filters, filter_count);
5721
5722         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5723
5724         return status;
5725 }
5726
5727 /**
5728  * i40e_aq_add_cloud_filters_big_buffer
5729  * @hw: pointer to the hardware structure
5730  * @seid: VSI seid to add cloud filters from
5731  * @filters: Buffer which contains the filters in big buffer to be added
5732  * @filter_count: number of filters contained in the buffer
5733  *
5734  * Set the cloud filters for a given VSI.  The contents of the
5735  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5736  * the function.
5737  *
5738  **/
5739 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5740         u16 seid,
5741         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5742         u8 filter_count)
5743 {
5744         struct i40e_aq_desc desc;
5745         struct i40e_aqc_add_remove_cloud_filters *cmd =
5746         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5747         enum i40e_status_code status;
5748         u16 buff_len;
5749         int i;
5750
5751         i40e_fill_default_direct_cmd_desc(&desc,
5752                                           i40e_aqc_opc_add_cloud_filters);
5753
5754         buff_len = filter_count * sizeof(*filters);
5755         desc.datalen = CPU_TO_LE16(buff_len);
5756         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5757         cmd->num_filters = filter_count;
5758         cmd->seid = CPU_TO_LE16(seid);
5759         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5760
5761         /* adjust Geneve VNI for HW issue */
5762         for (i = 0; i < filter_count; i++) {
5763                 u16 tnl_type;
5764                 u32 ti;
5765
5766                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5767                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5768                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5769                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5770                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5771                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5772                 }
5773         }
5774
5775         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5776
5777         return status;
5778 }
5779
5780 /**
5781  * i40e_aq_remove_cloud_filters
5782  * @hw: pointer to the hardware structure
5783  * @seid: VSI seid to remove cloud filters from
5784  * @filters: Buffer which contains the filters to be removed
5785  * @filter_count: number of filters contained in the buffer
5786  *
5787  * Remove the cloud filters for a given VSI.  The contents of the
5788  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5789  * in by the caller of the function.
5790  *
5791  **/
5792 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5793         u16 seid,
5794         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5795         u8 filter_count)
5796 {
5797         struct i40e_aq_desc desc;
5798         struct i40e_aqc_add_remove_cloud_filters *cmd =
5799         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5800         enum i40e_status_code status;
5801         u16 buff_len;
5802
5803         i40e_fill_default_direct_cmd_desc(&desc,
5804                                           i40e_aqc_opc_remove_cloud_filters);
5805
5806         buff_len = filter_count * sizeof(*filters);
5807         desc.datalen = CPU_TO_LE16(buff_len);
5808         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5809         cmd->num_filters = filter_count;
5810         cmd->seid = CPU_TO_LE16(seid);
5811
5812         i40e_fix_up_geneve_vni(filters, filter_count);
5813
5814         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5815
5816         return status;
5817 }
5818
5819 /**
5820  * i40e_aq_remove_cloud_filters_big_buffer
5821  * @hw: pointer to the hardware structure
5822  * @seid: VSI seid to remove cloud filters from
5823  * @filters: Buffer which contains the filters in big buffer to be removed
5824  * @filter_count: number of filters contained in the buffer
5825  *
5826  * Remove the cloud filters for a given VSI.  The contents of the
5827  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5828  * the function.
5829  *
5830  **/
5831 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5832         struct i40e_hw *hw,
5833         u16 seid,
5834         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5835         u8 filter_count)
5836 {
5837         struct i40e_aq_desc desc;
5838         struct i40e_aqc_add_remove_cloud_filters *cmd =
5839         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5840         enum i40e_status_code status;
5841         u16 buff_len;
5842         int i;
5843
5844         i40e_fill_default_direct_cmd_desc(&desc,
5845                                           i40e_aqc_opc_remove_cloud_filters);
5846
5847         buff_len = filter_count * sizeof(*filters);
5848         desc.datalen = CPU_TO_LE16(buff_len);
5849         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5850         cmd->num_filters = filter_count;
5851         cmd->seid = CPU_TO_LE16(seid);
5852         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5853
5854         /* adjust Geneve VNI for HW issue */
5855         for (i = 0; i < filter_count; i++) {
5856                 u16 tnl_type;
5857                 u32 ti;
5858
5859                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5860                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5861                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5862                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5863                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5864                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5865                 }
5866         }
5867
5868         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5869
5870         return status;
5871 }
5872
5873 /**
5874  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5875  * @hw: pointer to the hw struct
5876  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5877  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5878  *
5879  **/
5880 enum
5881 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5882         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5883         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5884 {
5885         struct i40e_aq_desc desc;
5886         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5887                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5888         enum i40e_status_code status = I40E_SUCCESS;
5889         int i = 0;
5890
5891         i40e_fill_default_direct_cmd_desc(&desc,
5892                                           i40e_aqc_opc_replace_cloud_filters);
5893
5894         desc.datalen = CPU_TO_LE16(32);
5895         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5896         cmd->old_filter_type = filters->old_filter_type;
5897         cmd->new_filter_type = filters->new_filter_type;
5898         cmd->valid_flags = filters->valid_flags;
5899         cmd->tr_bit = filters->tr_bit;
5900
5901         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5902                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5903
5904         /* for get cloud filters command */
5905         for (i = 0; i < 32; i += 4) {
5906                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5907                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5908                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5909                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5910         }
5911
5912         return status;
5913 }
5914
5915
5916 /**
5917  * i40e_aq_alternate_write
5918  * @hw: pointer to the hardware structure
5919  * @reg_addr0: address of first dword to be read
5920  * @reg_val0: value to be written under 'reg_addr0'
5921  * @reg_addr1: address of second dword to be read
5922  * @reg_val1: value to be written under 'reg_addr1'
5923  *
5924  * Write one or two dwords to alternate structure. Fields are indicated
5925  * by 'reg_addr0' and 'reg_addr1' register numbers.
5926  *
5927  **/
5928 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5929                                 u32 reg_addr0, u32 reg_val0,
5930                                 u32 reg_addr1, u32 reg_val1)
5931 {
5932         struct i40e_aq_desc desc;
5933         struct i40e_aqc_alternate_write *cmd_resp =
5934                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5935         enum i40e_status_code status;
5936
5937         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5938         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5939         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5940         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5941         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5942
5943         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5944
5945         return status;
5946 }
5947
5948 /**
5949  * i40e_aq_alternate_write_indirect
5950  * @hw: pointer to the hardware structure
5951  * @addr: address of a first register to be modified
5952  * @dw_count: number of alternate structure fields to write
5953  * @buffer: pointer to the command buffer
5954  *
5955  * Write 'dw_count' dwords from 'buffer' to alternate structure
5956  * starting at 'addr'.
5957  *
5958  **/
5959 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5960                                 u32 addr, u32 dw_count, void *buffer)
5961 {
5962         struct i40e_aq_desc desc;
5963         struct i40e_aqc_alternate_ind_write *cmd_resp =
5964                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5965         enum i40e_status_code status;
5966
5967         if (buffer == NULL)
5968                 return I40E_ERR_PARAM;
5969
5970         /* Indirect command */
5971         i40e_fill_default_direct_cmd_desc(&desc,
5972                                          i40e_aqc_opc_alternate_write_indirect);
5973
5974         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5975         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5976         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5977                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5978
5979         cmd_resp->address = CPU_TO_LE32(addr);
5980         cmd_resp->length = CPU_TO_LE32(dw_count);
5981
5982         status = i40e_asq_send_command(hw, &desc, buffer,
5983                                        I40E_LO_DWORD(4*dw_count), NULL);
5984
5985         return status;
5986 }
5987
5988 /**
5989  * i40e_aq_alternate_read
5990  * @hw: pointer to the hardware structure
5991  * @reg_addr0: address of first dword to be read
5992  * @reg_val0: pointer for data read from 'reg_addr0'
5993  * @reg_addr1: address of second dword to be read
5994  * @reg_val1: pointer for data read from 'reg_addr1'
5995  *
5996  * Read one or two dwords from alternate structure. Fields are indicated
5997  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5998  * is not passed then only register at 'reg_addr0' is read.
5999  *
6000  **/
6001 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6002                                 u32 reg_addr0, u32 *reg_val0,
6003                                 u32 reg_addr1, u32 *reg_val1)
6004 {
6005         struct i40e_aq_desc desc;
6006         struct i40e_aqc_alternate_write *cmd_resp =
6007                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6008         enum i40e_status_code status;
6009
6010         if (reg_val0 == NULL)
6011                 return I40E_ERR_PARAM;
6012
6013         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6014         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6015         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6016
6017         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6018
6019         if (status == I40E_SUCCESS) {
6020                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6021
6022                 if (reg_val1 != NULL)
6023                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6024         }
6025
6026         return status;
6027 }
6028
6029 /**
6030  * i40e_aq_alternate_read_indirect
6031  * @hw: pointer to the hardware structure
6032  * @addr: address of the alternate structure field
6033  * @dw_count: number of alternate structure fields to read
6034  * @buffer: pointer to the command buffer
6035  *
6036  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6037  * place them in 'buffer'. The buffer should be allocated by caller.
6038  *
6039  **/
6040 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6041                                 u32 addr, u32 dw_count, void *buffer)
6042 {
6043         struct i40e_aq_desc desc;
6044         struct i40e_aqc_alternate_ind_write *cmd_resp =
6045                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6046         enum i40e_status_code status;
6047
6048         if (buffer == NULL)
6049                 return I40E_ERR_PARAM;
6050
6051         /* Indirect command */
6052         i40e_fill_default_direct_cmd_desc(&desc,
6053                 i40e_aqc_opc_alternate_read_indirect);
6054
6055         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6056         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6057         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6058                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6059
6060         cmd_resp->address = CPU_TO_LE32(addr);
6061         cmd_resp->length = CPU_TO_LE32(dw_count);
6062
6063         status = i40e_asq_send_command(hw, &desc, buffer,
6064                                        I40E_LO_DWORD(4*dw_count), NULL);
6065
6066         return status;
6067 }
6068
6069 /**
6070  *  i40e_aq_alternate_clear
6071  *  @hw: pointer to the HW structure.
6072  *
6073  *  Clear the alternate structures of the port from which the function
6074  *  is called.
6075  *
6076  **/
6077 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6078 {
6079         struct i40e_aq_desc desc;
6080         enum i40e_status_code status;
6081
6082         i40e_fill_default_direct_cmd_desc(&desc,
6083                                           i40e_aqc_opc_alternate_clear_port);
6084
6085         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6086
6087         return status;
6088 }
6089
6090 /**
6091  *  i40e_aq_alternate_write_done
6092  *  @hw: pointer to the HW structure.
6093  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6094  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6095  *
6096  *  Indicates to the FW that alternate structures have been changed.
6097  *
6098  **/
6099 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6100                 u8 bios_mode, bool *reset_needed)
6101 {
6102         struct i40e_aq_desc desc;
6103         struct i40e_aqc_alternate_write_done *cmd =
6104                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6105         enum i40e_status_code status;
6106
6107         if (reset_needed == NULL)
6108                 return I40E_ERR_PARAM;
6109
6110         i40e_fill_default_direct_cmd_desc(&desc,
6111                                           i40e_aqc_opc_alternate_write_done);
6112
6113         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6114
6115         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6116         if (!status && reset_needed)
6117                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6118                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6119
6120         return status;
6121 }
6122
6123 /**
6124  *  i40e_aq_set_oem_mode
6125  *  @hw: pointer to the HW structure.
6126  *  @oem_mode: the OEM mode to be used
6127  *
6128  *  Sets the device to a specific operating mode. Currently the only supported
6129  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6130  *
6131  **/
6132 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6133                 u8 oem_mode)
6134 {
6135         struct i40e_aq_desc desc;
6136         struct i40e_aqc_alternate_write_done *cmd =
6137                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6138         enum i40e_status_code status;
6139
6140         i40e_fill_default_direct_cmd_desc(&desc,
6141                                           i40e_aqc_opc_alternate_set_mode);
6142
6143         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6144
6145         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6146
6147         return status;
6148 }
6149
6150 /**
6151  * i40e_aq_resume_port_tx
6152  * @hw: pointer to the hardware structure
6153  * @cmd_details: pointer to command details structure or NULL
6154  *
6155  * Resume port's Tx traffic
6156  **/
6157 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6158                                 struct i40e_asq_cmd_details *cmd_details)
6159 {
6160         struct i40e_aq_desc desc;
6161         enum i40e_status_code status;
6162
6163         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6164
6165         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6166
6167         return status;
6168 }
6169
6170 /**
6171  * i40e_set_pci_config_data - store PCI bus info
6172  * @hw: pointer to hardware structure
6173  * @link_status: the link status word from PCI config space
6174  *
6175  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6176  **/
6177 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6178 {
6179         hw->bus.type = i40e_bus_type_pci_express;
6180
6181         switch (link_status & I40E_PCI_LINK_WIDTH) {
6182         case I40E_PCI_LINK_WIDTH_1:
6183                 hw->bus.width = i40e_bus_width_pcie_x1;
6184                 break;
6185         case I40E_PCI_LINK_WIDTH_2:
6186                 hw->bus.width = i40e_bus_width_pcie_x2;
6187                 break;
6188         case I40E_PCI_LINK_WIDTH_4:
6189                 hw->bus.width = i40e_bus_width_pcie_x4;
6190                 break;
6191         case I40E_PCI_LINK_WIDTH_8:
6192                 hw->bus.width = i40e_bus_width_pcie_x8;
6193                 break;
6194         default:
6195                 hw->bus.width = i40e_bus_width_unknown;
6196                 break;
6197         }
6198
6199         switch (link_status & I40E_PCI_LINK_SPEED) {
6200         case I40E_PCI_LINK_SPEED_2500:
6201                 hw->bus.speed = i40e_bus_speed_2500;
6202                 break;
6203         case I40E_PCI_LINK_SPEED_5000:
6204                 hw->bus.speed = i40e_bus_speed_5000;
6205                 break;
6206         case I40E_PCI_LINK_SPEED_8000:
6207                 hw->bus.speed = i40e_bus_speed_8000;
6208                 break;
6209         default:
6210                 hw->bus.speed = i40e_bus_speed_unknown;
6211                 break;
6212         }
6213 }
6214
6215 /**
6216  * i40e_aq_debug_dump
6217  * @hw: pointer to the hardware structure
6218  * @cluster_id: specific cluster to dump
6219  * @table_id: table id within cluster
6220  * @start_index: index of line in the block to read
6221  * @buff_size: dump buffer size
6222  * @buff: dump buffer
6223  * @ret_buff_size: actual buffer size returned
6224  * @ret_next_table: next block to read
6225  * @ret_next_index: next index to read
6226  * @cmd_details: pointer to command details structure or NULL
6227  *
6228  * Dump internal FW/HW data for debug purposes.
6229  *
6230  **/
6231 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6232                                 u8 table_id, u32 start_index, u16 buff_size,
6233                                 void *buff, u16 *ret_buff_size,
6234                                 u8 *ret_next_table, u32 *ret_next_index,
6235                                 struct i40e_asq_cmd_details *cmd_details)
6236 {
6237         struct i40e_aq_desc desc;
6238         struct i40e_aqc_debug_dump_internals *cmd =
6239                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6240         struct i40e_aqc_debug_dump_internals *resp =
6241                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6242         enum i40e_status_code status;
6243
6244         if (buff_size == 0 || !buff)
6245                 return I40E_ERR_PARAM;
6246
6247         i40e_fill_default_direct_cmd_desc(&desc,
6248                                           i40e_aqc_opc_debug_dump_internals);
6249         /* Indirect Command */
6250         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6251         if (buff_size > I40E_AQ_LARGE_BUF)
6252                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6253
6254         cmd->cluster_id = cluster_id;
6255         cmd->table_id = table_id;
6256         cmd->idx = CPU_TO_LE32(start_index);
6257
6258         desc.datalen = CPU_TO_LE16(buff_size);
6259
6260         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6261         if (!status) {
6262                 if (ret_buff_size != NULL)
6263                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6264                 if (ret_next_table != NULL)
6265                         *ret_next_table = resp->table_id;
6266                 if (ret_next_index != NULL)
6267                         *ret_next_index = LE32_TO_CPU(resp->idx);
6268         }
6269
6270         return status;
6271 }
6272
6273 /**
6274  * i40e_read_bw_from_alt_ram
6275  * @hw: pointer to the hardware structure
6276  * @max_bw: pointer for max_bw read
6277  * @min_bw: pointer for min_bw read
6278  * @min_valid: pointer for bool that is true if min_bw is a valid value
6279  * @max_valid: pointer for bool that is true if max_bw is a valid value
6280  *
6281  * Read bw from the alternate ram for the given pf
6282  **/
6283 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6284                                         u32 *max_bw, u32 *min_bw,
6285                                         bool *min_valid, bool *max_valid)
6286 {
6287         enum i40e_status_code status;
6288         u32 max_bw_addr, min_bw_addr;
6289
6290         /* Calculate the address of the min/max bw registers */
6291         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6292                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6293                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6294         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6295                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6296                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6297
6298         /* Read the bandwidths from alt ram */
6299         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6300                                         min_bw_addr, min_bw);
6301
6302         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6303                 *min_valid = true;
6304         else
6305                 *min_valid = false;
6306
6307         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6308                 *max_valid = true;
6309         else
6310                 *max_valid = false;
6311
6312         return status;
6313 }
6314
6315 /**
6316  * i40e_aq_configure_partition_bw
6317  * @hw: pointer to the hardware structure
6318  * @bw_data: Buffer holding valid pfs and bw limits
6319  * @cmd_details: pointer to command details
6320  *
6321  * Configure partitions guaranteed/max bw
6322  **/
6323 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6324                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6325                         struct i40e_asq_cmd_details *cmd_details)
6326 {
6327         enum i40e_status_code status;
6328         struct i40e_aq_desc desc;
6329         u16 bwd_size = sizeof(*bw_data);
6330
6331         i40e_fill_default_direct_cmd_desc(&desc,
6332                                 i40e_aqc_opc_configure_partition_bw);
6333
6334         /* Indirect command */
6335         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6336         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6337
6338         desc.datalen = CPU_TO_LE16(bwd_size);
6339
6340         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6341
6342         return status;
6343 }
6344
6345 /**
6346  * i40e_read_phy_register_clause22
6347  * @hw: pointer to the HW structure
6348  * @reg: register address in the page
6349  * @phy_addr: PHY address on MDIO interface
6350  * @value: PHY register value
6351  *
6352  * Reads specified PHY register value
6353  **/
6354 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6355                                         u16 reg, u8 phy_addr, u16 *value)
6356 {
6357         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6358         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6359         u32 command = 0;
6360         u16 retry = 1000;
6361
6362         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6363                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6364                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6365                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6366                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6367         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6368         do {
6369                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6370                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6371                         status = I40E_SUCCESS;
6372                         break;
6373                 }
6374                 i40e_usec_delay(10);
6375                 retry--;
6376         } while (retry);
6377
6378         if (status) {
6379                 i40e_debug(hw, I40E_DEBUG_PHY,
6380                            "PHY: Can't write command to external PHY.\n");
6381         } else {
6382                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6383                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6384                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6385         }
6386
6387         return status;
6388 }
6389
6390 /**
6391  * i40e_write_phy_register_clause22
6392  * @hw: pointer to the HW structure
6393  * @reg: register address in the page
6394  * @phy_addr: PHY address on MDIO interface
6395  * @value: PHY register value
6396  *
6397  * Writes specified PHY register value
6398  **/
6399 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6400                                         u16 reg, u8 phy_addr, u16 value)
6401 {
6402         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6403         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6404         u32 command  = 0;
6405         u16 retry = 1000;
6406
6407         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6408         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6409
6410         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6411                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6412                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6413                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6414                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6415
6416         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6417         do {
6418                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6419                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6420                         status = I40E_SUCCESS;
6421                         break;
6422                 }
6423                 i40e_usec_delay(10);
6424                 retry--;
6425         } while (retry);
6426
6427         return status;
6428 }
6429
6430 /**
6431  * i40e_read_phy_register_clause45
6432  * @hw: pointer to the HW structure
6433  * @page: registers page number
6434  * @reg: register address in the page
6435  * @phy_addr: PHY address on MDIO interface
6436  * @value: PHY register value
6437  *
6438  * Reads specified PHY register value
6439  **/
6440 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6441                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6442 {
6443         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6444         u32 command  = 0;
6445         u16 retry = 1000;
6446         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6447
6448         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6449                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6450                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6451                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6452                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6453                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6454                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6455         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6456         do {
6457                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6458                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6459                         status = I40E_SUCCESS;
6460                         break;
6461                 }
6462                 i40e_usec_delay(10);
6463                 retry--;
6464         } while (retry);
6465
6466         if (status) {
6467                 i40e_debug(hw, I40E_DEBUG_PHY,
6468                            "PHY: Can't write command to external PHY.\n");
6469                 goto phy_read_end;
6470         }
6471
6472         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6473                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6474                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6475                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6476                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6477                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6478         status = I40E_ERR_TIMEOUT;
6479         retry = 1000;
6480         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6481         do {
6482                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6483                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6484                         status = I40E_SUCCESS;
6485                         break;
6486                 }
6487                 i40e_usec_delay(10);
6488                 retry--;
6489         } while (retry);
6490
6491         if (!status) {
6492                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6493                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6494                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6495         } else {
6496                 i40e_debug(hw, I40E_DEBUG_PHY,
6497                            "PHY: Can't read register value from external PHY.\n");
6498         }
6499
6500 phy_read_end:
6501         return status;
6502 }
6503
6504 /**
6505  * i40e_write_phy_register_clause45
6506  * @hw: pointer to the HW structure
6507  * @page: registers page number
6508  * @reg: register address in the page
6509  * @phy_addr: PHY address on MDIO interface
6510  * @value: PHY register value
6511  *
6512  * Writes value to specified PHY register
6513  **/
6514 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6515                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6516 {
6517         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6518         u32 command  = 0;
6519         u16 retry = 1000;
6520         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6521
6522         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6523                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6524                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6525                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6526                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6527                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6528                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6529         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6530         do {
6531                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6532                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6533                         status = I40E_SUCCESS;
6534                         break;
6535                 }
6536                 i40e_usec_delay(10);
6537                 retry--;
6538         } while (retry);
6539         if (status) {
6540                 i40e_debug(hw, I40E_DEBUG_PHY,
6541                            "PHY: Can't write command to external PHY.\n");
6542                 goto phy_write_end;
6543         }
6544
6545         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6546         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6547
6548         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6549                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6550                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6551                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6552                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6553                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6554         status = I40E_ERR_TIMEOUT;
6555         retry = 1000;
6556         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6557         do {
6558                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6559                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6560                         status = I40E_SUCCESS;
6561                         break;
6562                 }
6563                 i40e_usec_delay(10);
6564                 retry--;
6565         } while (retry);
6566
6567 phy_write_end:
6568         return status;
6569 }
6570
6571 /**
6572  * i40e_write_phy_register
6573  * @hw: pointer to the HW structure
6574  * @page: registers page number
6575  * @reg: register address in the page
6576  * @phy_addr: PHY address on MDIO interface
6577  * @value: PHY register value
6578  *
6579  * Writes value to specified PHY register
6580  **/
6581 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6582                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6583 {
6584         enum i40e_status_code status;
6585
6586         switch (hw->device_id) {
6587         case I40E_DEV_ID_1G_BASE_T_X722:
6588                 status = i40e_write_phy_register_clause22(hw,
6589                         reg, phy_addr, value);
6590                 break;
6591         case I40E_DEV_ID_10G_BASE_T:
6592         case I40E_DEV_ID_10G_BASE_T4:
6593         case I40E_DEV_ID_10G_BASE_T_X722:
6594         case I40E_DEV_ID_25G_B:
6595         case I40E_DEV_ID_25G_SFP28:
6596                 status = i40e_write_phy_register_clause45(hw,
6597                         page, reg, phy_addr, value);
6598                 break;
6599         default:
6600                 status = I40E_ERR_UNKNOWN_PHY;
6601                 break;
6602         }
6603
6604         return status;
6605 }
6606
6607 /**
6608  * i40e_read_phy_register
6609  * @hw: pointer to the HW structure
6610  * @page: registers page number
6611  * @reg: register address in the page
6612  * @phy_addr: PHY address on MDIO interface
6613  * @value: PHY register value
6614  *
6615  * Reads specified PHY register value
6616  **/
6617 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6618                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6619 {
6620         enum i40e_status_code status;
6621
6622         switch (hw->device_id) {
6623         case I40E_DEV_ID_1G_BASE_T_X722:
6624                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6625                                                          value);
6626                 break;
6627         case I40E_DEV_ID_10G_BASE_T:
6628         case I40E_DEV_ID_10G_BASE_T4:
6629         case I40E_DEV_ID_10G_BASE_T_X722:
6630         case I40E_DEV_ID_25G_B:
6631         case I40E_DEV_ID_25G_SFP28:
6632                 status = i40e_read_phy_register_clause45(hw, page, reg,
6633                                                          phy_addr, value);
6634                 break;
6635         default:
6636                 status = I40E_ERR_UNKNOWN_PHY;
6637                 break;
6638         }
6639
6640         return status;
6641 }
6642
6643 /**
6644  * i40e_get_phy_address
6645  * @hw: pointer to the HW structure
6646  * @dev_num: PHY port num that address we want
6647  *
6648  * Gets PHY address for current port
6649  **/
6650 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6651 {
6652         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6653         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6654
6655         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6656 }
6657
6658 /**
6659  * i40e_blink_phy_led
6660  * @hw: pointer to the HW structure
6661  * @time: time how long led will blinks in secs
6662  * @interval: gap between LED on and off in msecs
6663  *
6664  * Blinks PHY link LED
6665  **/
6666 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6667                                               u32 time, u32 interval)
6668 {
6669         enum i40e_status_code status = I40E_SUCCESS;
6670         u32 i;
6671         u16 led_ctl = 0;
6672         u16 gpio_led_port;
6673         u16 led_reg;
6674         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6675         u8 phy_addr = 0;
6676         u8 port_num;
6677
6678         i = rd32(hw, I40E_PFGEN_PORTNUM);
6679         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6680         phy_addr = i40e_get_phy_address(hw, port_num);
6681
6682         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6683              led_addr++) {
6684                 status = i40e_read_phy_register_clause45(hw,
6685                                                          I40E_PHY_COM_REG_PAGE,
6686                                                          led_addr, phy_addr,
6687                                                          &led_reg);
6688                 if (status)
6689                         goto phy_blinking_end;
6690                 led_ctl = led_reg;
6691                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6692                         led_reg = 0;
6693                         status = i40e_write_phy_register_clause45(hw,
6694                                                          I40E_PHY_COM_REG_PAGE,
6695                                                          led_addr, phy_addr,
6696                                                          led_reg);
6697                         if (status)
6698                                 goto phy_blinking_end;
6699                         break;
6700                 }
6701         }
6702
6703         if (time > 0 && interval > 0) {
6704                 for (i = 0; i < time * 1000; i += interval) {
6705                         status = i40e_read_phy_register_clause45(hw,
6706                                                 I40E_PHY_COM_REG_PAGE,
6707                                                 led_addr, phy_addr, &led_reg);
6708                         if (status)
6709                                 goto restore_config;
6710                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6711                                 led_reg = 0;
6712                         else
6713                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6714                         status = i40e_write_phy_register_clause45(hw,
6715                                                 I40E_PHY_COM_REG_PAGE,
6716                                                 led_addr, phy_addr, led_reg);
6717                         if (status)
6718                                 goto restore_config;
6719                         i40e_msec_delay(interval);
6720                 }
6721         }
6722
6723 restore_config:
6724         status = i40e_write_phy_register_clause45(hw,
6725                                                   I40E_PHY_COM_REG_PAGE,
6726                                                   led_addr, phy_addr, led_ctl);
6727
6728 phy_blinking_end:
6729         return status;
6730 }
6731
6732 /**
6733  * i40e_led_get_reg - read LED register
6734  * @hw: pointer to the HW structure
6735  * @led_addr: LED register address
6736  * @reg_val: read register value
6737  **/
6738 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6739                                               u32 *reg_val)
6740 {
6741         enum i40e_status_code status;
6742         u8 phy_addr = 0;
6743
6744         *reg_val = 0;
6745         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6746                 status = i40e_aq_get_phy_register(hw,
6747                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6748                                                 I40E_PHY_COM_REG_PAGE,
6749                                                 I40E_PHY_LED_PROV_REG_1,
6750                                                 reg_val, NULL);
6751         } else {
6752                 phy_addr = i40e_get_phy_address(hw, hw->port);
6753                 status = i40e_read_phy_register_clause45(hw,
6754                                                          I40E_PHY_COM_REG_PAGE,
6755                                                          led_addr, phy_addr,
6756                                                          (u16 *)reg_val);
6757         }
6758         return status;
6759 }
6760
6761 /**
6762  * i40e_led_set_reg - write LED register
6763  * @hw: pointer to the HW structure
6764  * @led_addr: LED register address
6765  * @reg_val: register value to write
6766  **/
6767 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6768                                               u32 reg_val)
6769 {
6770         enum i40e_status_code status;
6771         u8 phy_addr = 0;
6772
6773         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6774                 status = i40e_aq_set_phy_register(hw,
6775                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6776                                                 I40E_PHY_COM_REG_PAGE,
6777                                                 I40E_PHY_LED_PROV_REG_1,
6778                                                 reg_val, NULL);
6779         } else {
6780                 phy_addr = i40e_get_phy_address(hw, hw->port);
6781                 status = i40e_write_phy_register_clause45(hw,
6782                                                           I40E_PHY_COM_REG_PAGE,
6783                                                           led_addr, phy_addr,
6784                                                           (u16)reg_val);
6785         }
6786
6787         return status;
6788 }
6789
6790 /**
6791  * i40e_led_get_phy - return current on/off mode
6792  * @hw: pointer to the hw struct
6793  * @led_addr: address of led register to use
6794  * @val: original value of register to use
6795  *
6796  **/
6797 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6798                                        u16 *val)
6799 {
6800         enum i40e_status_code status = I40E_SUCCESS;
6801         u16 gpio_led_port;
6802         u32 reg_val_aq;
6803         u16 temp_addr;
6804         u8 phy_addr = 0;
6805         u16 reg_val;
6806
6807         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6808                 status = i40e_aq_get_phy_register(hw,
6809                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6810                                                 I40E_PHY_COM_REG_PAGE,
6811                                                 I40E_PHY_LED_PROV_REG_1,
6812                                                 &reg_val_aq, NULL);
6813                 if (status == I40E_SUCCESS)
6814                         *val = (u16)reg_val_aq;
6815                 return status;
6816         }
6817         temp_addr = I40E_PHY_LED_PROV_REG_1;
6818         phy_addr = i40e_get_phy_address(hw, hw->port);
6819         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6820              temp_addr++) {
6821                 status = i40e_read_phy_register_clause45(hw,
6822                                                          I40E_PHY_COM_REG_PAGE,
6823                                                          temp_addr, phy_addr,
6824                                                          &reg_val);
6825                 if (status)
6826                         return status;
6827                 *val = reg_val;
6828                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6829                         *led_addr = temp_addr;
6830                         break;
6831                 }
6832         }
6833         return status;
6834 }
6835
6836 /**
6837  * i40e_led_set_phy
6838  * @hw: pointer to the HW structure
6839  * @on: true or false
6840  * @led_addr: address of led register to use
6841  * @mode: original val plus bit for set or ignore
6842  *
6843  * Set led's on or off when controlled by the PHY
6844  *
6845  **/
6846 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6847                                        u16 led_addr, u32 mode)
6848 {
6849         enum i40e_status_code status = I40E_SUCCESS;
6850         u32 led_ctl = 0;
6851         u32 led_reg = 0;
6852
6853         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6854         if (status)
6855                 return status;
6856         led_ctl = led_reg;
6857         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6858                 led_reg = 0;
6859                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6860                 if (status)
6861                         return status;
6862         }
6863         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6864         if (status)
6865                 goto restore_config;
6866         if (on)
6867                 led_reg = I40E_PHY_LED_MANUAL_ON;
6868         else
6869                 led_reg = 0;
6870         status = i40e_led_set_reg(hw, led_addr, led_reg);
6871         if (status)
6872                 goto restore_config;
6873         if (mode & I40E_PHY_LED_MODE_ORIG) {
6874                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6875                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6876         }
6877         return status;
6878
6879 restore_config:
6880         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6881         return status;
6882 }
6883 #endif /* PF_DRIVER */
6884
6885 /**
6886  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6887  * @hw: pointer to the hw struct
6888  * @reg_addr: register address
6889  * @reg_val: ptr to register value
6890  * @cmd_details: pointer to command details structure or NULL
6891  *
6892  * Use the firmware to read the Rx control register,
6893  * especially useful if the Rx unit is under heavy pressure
6894  **/
6895 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6896                                 u32 reg_addr, u32 *reg_val,
6897                                 struct i40e_asq_cmd_details *cmd_details)
6898 {
6899         struct i40e_aq_desc desc;
6900         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6901                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6902         enum i40e_status_code status;
6903
6904         if (reg_val == NULL)
6905                 return I40E_ERR_PARAM;
6906
6907         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6908
6909         cmd_resp->address = CPU_TO_LE32(reg_addr);
6910
6911         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6912
6913         if (status == I40E_SUCCESS)
6914                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6915
6916         return status;
6917 }
6918
6919 /**
6920  * i40e_read_rx_ctl - read from an Rx control register
6921  * @hw: pointer to the hw struct
6922  * @reg_addr: register address
6923  **/
6924 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6925 {
6926         enum i40e_status_code status = I40E_SUCCESS;
6927         bool use_register;
6928         int retry = 5;
6929         u32 val = 0;
6930
6931         use_register = (((hw->aq.api_maj_ver == 1) &&
6932                         (hw->aq.api_min_ver < 5)) ||
6933                         (hw->mac.type == I40E_MAC_X722));
6934         if (!use_register) {
6935 do_retry:
6936                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6937                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6938                         i40e_msec_delay(1);
6939                         retry--;
6940                         goto do_retry;
6941                 }
6942         }
6943
6944         /* if the AQ access failed, try the old-fashioned way */
6945         if (status || use_register)
6946                 val = rd32(hw, reg_addr);
6947
6948         return val;
6949 }
6950
6951 /**
6952  * i40e_aq_rx_ctl_write_register
6953  * @hw: pointer to the hw struct
6954  * @reg_addr: register address
6955  * @reg_val: register value
6956  * @cmd_details: pointer to command details structure or NULL
6957  *
6958  * Use the firmware to write to an Rx control register,
6959  * especially useful if the Rx unit is under heavy pressure
6960  **/
6961 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6962                                 u32 reg_addr, u32 reg_val,
6963                                 struct i40e_asq_cmd_details *cmd_details)
6964 {
6965         struct i40e_aq_desc desc;
6966         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6967                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6968         enum i40e_status_code status;
6969
6970         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6971
6972         cmd->address = CPU_TO_LE32(reg_addr);
6973         cmd->value = CPU_TO_LE32(reg_val);
6974
6975         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6976
6977         return status;
6978 }
6979
6980 /**
6981  * i40e_write_rx_ctl - write to an Rx control register
6982  * @hw: pointer to the hw struct
6983  * @reg_addr: register address
6984  * @reg_val: register value
6985  **/
6986 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6987 {
6988         enum i40e_status_code status = I40E_SUCCESS;
6989         bool use_register;
6990         int retry = 5;
6991
6992         use_register = (((hw->aq.api_maj_ver == 1) &&
6993                         (hw->aq.api_min_ver < 5)) ||
6994                         (hw->mac.type == I40E_MAC_X722));
6995         if (!use_register) {
6996 do_retry:
6997                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6998                                                        reg_val, NULL);
6999                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7000                         i40e_msec_delay(1);
7001                         retry--;
7002                         goto do_retry;
7003                 }
7004         }
7005
7006         /* if the AQ access failed, try the old-fashioned way */
7007         if (status || use_register)
7008                 wr32(hw, reg_addr, reg_val);
7009 }
7010
7011 /**
7012  * i40e_aq_set_phy_register
7013  * @hw: pointer to the hw struct
7014  * @phy_select: select which phy should be accessed
7015  * @dev_addr: PHY device address
7016  * @reg_addr: PHY register address
7017  * @reg_val: new register value
7018  * @cmd_details: pointer to command details structure or NULL
7019  *
7020  * Write the external PHY register.
7021  **/
7022 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7023                                 u8 phy_select, u8 dev_addr,
7024                                 u32 reg_addr, u32 reg_val,
7025                                 struct i40e_asq_cmd_details *cmd_details)
7026 {
7027         struct i40e_aq_desc desc;
7028         struct i40e_aqc_phy_register_access *cmd =
7029                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7030         enum i40e_status_code status;
7031
7032         i40e_fill_default_direct_cmd_desc(&desc,
7033                                           i40e_aqc_opc_set_phy_register);
7034
7035         cmd->phy_interface = phy_select;
7036         cmd->dev_addres = dev_addr;
7037         cmd->reg_address = CPU_TO_LE32(reg_addr);
7038         cmd->reg_value = CPU_TO_LE32(reg_val);
7039
7040         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7041
7042         return status;
7043 }
7044
7045 /**
7046  * i40e_aq_get_phy_register
7047  * @hw: pointer to the hw struct
7048  * @phy_select: select which phy should be accessed
7049  * @dev_addr: PHY device address
7050  * @reg_addr: PHY register address
7051  * @reg_val: read register value
7052  * @cmd_details: pointer to command details structure or NULL
7053  *
7054  * Read the external PHY register.
7055  **/
7056 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7057                                 u8 phy_select, u8 dev_addr,
7058                                 u32 reg_addr, u32 *reg_val,
7059                                 struct i40e_asq_cmd_details *cmd_details)
7060 {
7061         struct i40e_aq_desc desc;
7062         struct i40e_aqc_phy_register_access *cmd =
7063                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7064         enum i40e_status_code status;
7065
7066         i40e_fill_default_direct_cmd_desc(&desc,
7067                                           i40e_aqc_opc_get_phy_register);
7068
7069         cmd->phy_interface = phy_select;
7070         cmd->dev_addres = dev_addr;
7071         cmd->reg_address = CPU_TO_LE32(reg_addr);
7072
7073         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7074         if (!status)
7075                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7076
7077         return status;
7078 }
7079
7080 #ifdef VF_DRIVER
7081
7082 /**
7083  * i40e_aq_send_msg_to_pf
7084  * @hw: pointer to the hardware structure
7085  * @v_opcode: opcodes for VF-PF communication
7086  * @v_retval: return error code
7087  * @msg: pointer to the msg buffer
7088  * @msglen: msg length
7089  * @cmd_details: pointer to command details
7090  *
7091  * Send message to PF driver using admin queue. By default, this message
7092  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7093  * completion before returning.
7094  **/
7095 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7096                                 enum virtchnl_ops v_opcode,
7097                                 enum i40e_status_code v_retval,
7098                                 u8 *msg, u16 msglen,
7099                                 struct i40e_asq_cmd_details *cmd_details)
7100 {
7101         struct i40e_aq_desc desc;
7102         struct i40e_asq_cmd_details details;
7103         enum i40e_status_code status;
7104
7105         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7106         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7107         desc.cookie_high = CPU_TO_LE32(v_opcode);
7108         desc.cookie_low = CPU_TO_LE32(v_retval);
7109         if (msglen) {
7110                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7111                                                 | I40E_AQ_FLAG_RD));
7112                 if (msglen > I40E_AQ_LARGE_BUF)
7113                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7114                 desc.datalen = CPU_TO_LE16(msglen);
7115         }
7116         if (!cmd_details) {
7117                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7118                 details.async = true;
7119                 cmd_details = &details;
7120         }
7121         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7122                                        msglen, cmd_details);
7123         return status;
7124 }
7125
7126 /**
7127  * i40e_vf_parse_hw_config
7128  * @hw: pointer to the hardware structure
7129  * @msg: pointer to the virtual channel VF resource structure
7130  *
7131  * Given a VF resource message from the PF, populate the hw struct
7132  * with appropriate information.
7133  **/
7134 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7135                              struct virtchnl_vf_resource *msg)
7136 {
7137         struct virtchnl_vsi_resource *vsi_res;
7138         int i;
7139
7140         vsi_res = &msg->vsi_res[0];
7141
7142         hw->dev_caps.num_vsis = msg->num_vsis;
7143         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7144         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7145         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7146         hw->dev_caps.dcb = msg->vf_offload_flags &
7147                            VIRTCHNL_VF_OFFLOAD_L2;
7148         hw->dev_caps.iwarp = (msg->vf_offload_flags &
7149                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7150         for (i = 0; i < msg->num_vsis; i++) {
7151                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7152                         i40e_memcpy(hw->mac.perm_addr,
7153                                     vsi_res->default_mac_addr,
7154                                     ETH_ALEN,
7155                                     I40E_NONDMA_TO_NONDMA);
7156                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7157                                     ETH_ALEN,
7158                                     I40E_NONDMA_TO_NONDMA);
7159                 }
7160                 vsi_res++;
7161         }
7162 }
7163
7164 /**
7165  * i40e_vf_reset
7166  * @hw: pointer to the hardware structure
7167  *
7168  * Send a VF_RESET message to the PF. Does not wait for response from PF
7169  * as none will be forthcoming. Immediately after calling this function,
7170  * the admin queue should be shut down and (optionally) reinitialized.
7171  **/
7172 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7173 {
7174         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7175                                       I40E_SUCCESS, NULL, 0, NULL);
7176 }
7177 #endif /* VF_DRIVER */
7178
7179 /**
7180  * i40e_aq_set_arp_proxy_config
7181  * @hw: pointer to the HW structure
7182  * @proxy_config: pointer to proxy config command table struct
7183  * @cmd_details: pointer to command details
7184  *
7185  * Set ARP offload parameters from pre-populated
7186  * i40e_aqc_arp_proxy_data struct
7187  **/
7188 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7189                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7190                                 struct i40e_asq_cmd_details *cmd_details)
7191 {
7192         struct i40e_aq_desc desc;
7193         enum i40e_status_code status;
7194
7195         if (!proxy_config)
7196                 return I40E_ERR_PARAM;
7197
7198         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7199
7200         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7201         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7202         desc.params.external.addr_high =
7203                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7204         desc.params.external.addr_low =
7205                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7206         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7207
7208         status = i40e_asq_send_command(hw, &desc, proxy_config,
7209                                        sizeof(struct i40e_aqc_arp_proxy_data),
7210                                        cmd_details);
7211
7212         return status;
7213 }
7214
7215 /**
7216  * i40e_aq_opc_set_ns_proxy_table_entry
7217  * @hw: pointer to the HW structure
7218  * @ns_proxy_table_entry: pointer to NS table entry command struct
7219  * @cmd_details: pointer to command details
7220  *
7221  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7222  * from pre-populated i40e_aqc_ns_proxy_data struct
7223  **/
7224 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7225                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7226                         struct i40e_asq_cmd_details *cmd_details)
7227 {
7228         struct i40e_aq_desc desc;
7229         enum i40e_status_code status;
7230
7231         if (!ns_proxy_table_entry)
7232                 return I40E_ERR_PARAM;
7233
7234         i40e_fill_default_direct_cmd_desc(&desc,
7235                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7236
7237         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7238         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7239         desc.params.external.addr_high =
7240                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7241         desc.params.external.addr_low =
7242                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7243         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7244
7245         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7246                                        sizeof(struct i40e_aqc_ns_proxy_data),
7247                                        cmd_details);
7248
7249         return status;
7250 }
7251
7252 /**
7253  * i40e_aq_set_clear_wol_filter
7254  * @hw: pointer to the hw struct
7255  * @filter_index: index of filter to modify (0-7)
7256  * @filter: buffer containing filter to be set
7257  * @set_filter: true to set filter, false to clear filter
7258  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7259  *              if false, pass through packets may cause wake-up
7260  * @filter_valid: true if filter action is valid
7261  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7262  * @cmd_details: pointer to command details structure or NULL
7263  *
7264  * Set or clear WoL filter for port attached to the PF
7265  **/
7266 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7267                                 u8 filter_index,
7268                                 struct i40e_aqc_set_wol_filter_data *filter,
7269                                 bool set_filter, bool no_wol_tco,
7270                                 bool filter_valid, bool no_wol_tco_valid,
7271                                 struct i40e_asq_cmd_details *cmd_details)
7272 {
7273         struct i40e_aq_desc desc;
7274         struct i40e_aqc_set_wol_filter *cmd =
7275                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7276         enum i40e_status_code status;
7277         u16 cmd_flags = 0;
7278         u16 valid_flags = 0;
7279         u16 buff_len = 0;
7280
7281         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7282
7283         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7284                 return  I40E_ERR_PARAM;
7285         cmd->filter_index = CPU_TO_LE16(filter_index);
7286
7287         if (set_filter) {
7288                 if (!filter)
7289                         return  I40E_ERR_PARAM;
7290
7291                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7292                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7293         }
7294
7295         if (no_wol_tco)
7296                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7297         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7298
7299         if (filter_valid)
7300                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7301         if (no_wol_tco_valid)
7302                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7303         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7304
7305         buff_len = sizeof(*filter);
7306         desc.datalen = CPU_TO_LE16(buff_len);
7307
7308         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7309         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7310
7311         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7312         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7313
7314         status = i40e_asq_send_command(hw, &desc, filter,
7315                                        buff_len, cmd_details);
7316
7317         return status;
7318 }
7319
7320 /**
7321  * i40e_aq_get_wake_event_reason
7322  * @hw: pointer to the hw struct
7323  * @wake_reason: return value, index of matching filter
7324  * @cmd_details: pointer to command details structure or NULL
7325  *
7326  * Get information for the reason of a Wake Up event
7327  **/
7328 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7329                                 u16 *wake_reason,
7330                                 struct i40e_asq_cmd_details *cmd_details)
7331 {
7332         struct i40e_aq_desc desc;
7333         struct i40e_aqc_get_wake_reason_completion *resp =
7334                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7335         enum i40e_status_code status;
7336
7337         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7338
7339         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7340
7341         if (status == I40E_SUCCESS)
7342                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7343
7344         return status;
7345 }
7346
7347 /**
7348 * i40e_aq_clear_all_wol_filters
7349 * @hw: pointer to the hw struct
7350 * @cmd_details: pointer to command details structure or NULL
7351 *
7352 * Get information for the reason of a Wake Up event
7353 **/
7354 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7355         struct i40e_asq_cmd_details *cmd_details)
7356 {
7357         struct i40e_aq_desc desc;
7358         enum i40e_status_code status;
7359
7360         i40e_fill_default_direct_cmd_desc(&desc,
7361                                           i40e_aqc_opc_clear_all_wol_filters);
7362
7363         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7364
7365         return status;
7366 }
7367
7368 /**
7369  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7370  * @hw: pointer to the hw struct
7371  * @buff: command buffer (size in bytes = buff_size)
7372  * @buff_size: buffer size in bytes
7373  * @track_id: package tracking id
7374  * @error_offset: returns error offset
7375  * @error_info: returns error information
7376  * @cmd_details: pointer to command details structure or NULL
7377  **/
7378 enum
7379 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7380                                    u16 buff_size, u32 track_id,
7381                                    u32 *error_offset, u32 *error_info,
7382                                    struct i40e_asq_cmd_details *cmd_details)
7383 {
7384         struct i40e_aq_desc desc;
7385         struct i40e_aqc_write_personalization_profile *cmd =
7386                 (struct i40e_aqc_write_personalization_profile *)
7387                 &desc.params.raw;
7388         struct i40e_aqc_write_ddp_resp *resp;
7389         enum i40e_status_code status;
7390
7391         i40e_fill_default_direct_cmd_desc(&desc,
7392                                   i40e_aqc_opc_write_personalization_profile);
7393
7394         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7395         if (buff_size > I40E_AQ_LARGE_BUF)
7396                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7397
7398         desc.datalen = CPU_TO_LE16(buff_size);
7399
7400         cmd->profile_track_id = CPU_TO_LE32(track_id);
7401
7402         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7403         if (!status) {
7404                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7405                 if (error_offset)
7406                         *error_offset = LE32_TO_CPU(resp->error_offset);
7407                 if (error_info)
7408                         *error_info = LE32_TO_CPU(resp->error_info);
7409         }
7410
7411         return status;
7412 }
7413
7414 /**
7415  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7416  * @hw: pointer to the hw struct
7417  * @buff: command buffer (size in bytes = buff_size)
7418  * @buff_size: buffer size in bytes
7419  * @flags: AdminQ command flags
7420  * @cmd_details: pointer to command details structure or NULL
7421  **/
7422 enum
7423 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7424                                       u16 buff_size, u8 flags,
7425                                       struct i40e_asq_cmd_details *cmd_details)
7426 {
7427         struct i40e_aq_desc desc;
7428         struct i40e_aqc_get_applied_profiles *cmd =
7429                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7430         enum i40e_status_code status;
7431
7432         i40e_fill_default_direct_cmd_desc(&desc,
7433                           i40e_aqc_opc_get_personalization_profile_list);
7434
7435         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7436         if (buff_size > I40E_AQ_LARGE_BUF)
7437                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7438         desc.datalen = CPU_TO_LE16(buff_size);
7439
7440         cmd->flags = flags;
7441
7442         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7443
7444         return status;
7445 }
7446
7447 /**
7448  * i40e_find_segment_in_package
7449  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7450  * @pkg_hdr: pointer to the package header to be searched
7451  *
7452  * This function searches a package file for a particular segment type. On
7453  * success it returns a pointer to the segment header, otherwise it will
7454  * return NULL.
7455  **/
7456 struct i40e_generic_seg_header *
7457 i40e_find_segment_in_package(u32 segment_type,
7458                              struct i40e_package_header *pkg_hdr)
7459 {
7460         struct i40e_generic_seg_header *segment;
7461         u32 i;
7462
7463         /* Search all package segments for the requested segment type */
7464         for (i = 0; i < pkg_hdr->segment_count; i++) {
7465                 segment =
7466                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7467                          pkg_hdr->segment_offset[i]);
7468
7469                 if (segment->type == segment_type)
7470                         return segment;
7471         }
7472
7473         return NULL;
7474 }
7475
7476 /* Get section table in profile */
7477 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7478         do {                                                            \
7479                 struct i40e_profile_segment *p = (profile);             \
7480                 u32 count;                                              \
7481                 u32 *nvm;                                               \
7482                 count = p->device_table_count;                          \
7483                 nvm = (u32 *)&p->device_table[count];                   \
7484                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7485         } while (0)
7486
7487 /* Get section header in profile */
7488 #define I40E_SECTION_HEADER(profile, offset)                            \
7489         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7490
7491 /**
7492  * i40e_find_section_in_profile
7493  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7494  * @profile: pointer to the i40e segment header to be searched
7495  *
7496  * This function searches i40e segment for a particular section type. On
7497  * success it returns a pointer to the section header, otherwise it will
7498  * return NULL.
7499  **/
7500 struct i40e_profile_section_header *
7501 i40e_find_section_in_profile(u32 section_type,
7502                              struct i40e_profile_segment *profile)
7503 {
7504         struct i40e_profile_section_header *sec;
7505         struct i40e_section_table *sec_tbl;
7506         u32 sec_off;
7507         u32 i;
7508
7509         if (profile->header.type != SEGMENT_TYPE_I40E)
7510                 return NULL;
7511
7512         I40E_SECTION_TABLE(profile, sec_tbl);
7513
7514         for (i = 0; i < sec_tbl->section_count; i++) {
7515                 sec_off = sec_tbl->section_offset[i];
7516                 sec = I40E_SECTION_HEADER(profile, sec_off);
7517                 if (sec->section.type == section_type)
7518                         return sec;
7519         }
7520
7521         return NULL;
7522 }
7523
7524 /**
7525  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7526  * @hw: pointer to the hw struct
7527  * @aq: command buffer containing all data to execute AQ
7528  **/
7529 STATIC enum
7530 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7531                                           struct i40e_profile_aq_section *aq)
7532 {
7533         enum i40e_status_code status;
7534         struct i40e_aq_desc desc;
7535         u8 *msg = NULL;
7536         u16 msglen;
7537
7538         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7539         desc.flags |= CPU_TO_LE16(aq->flags);
7540         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7541                     I40E_NONDMA_TO_NONDMA);
7542
7543         msglen = aq->datalen;
7544         if (msglen) {
7545                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7546                                                 I40E_AQ_FLAG_RD));
7547                 if (msglen > I40E_AQ_LARGE_BUF)
7548                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7549                 desc.datalen = CPU_TO_LE16(msglen);
7550                 msg = &aq->data[0];
7551         }
7552
7553         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7554
7555         if (status != I40E_SUCCESS) {
7556                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7557                            "unable to exec DDP AQ opcode %u, error %d\n",
7558                            aq->opcode, status);
7559                 return status;
7560         }
7561
7562         /* copy returned desc to aq_buf */
7563         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7564                     I40E_NONDMA_TO_NONDMA);
7565
7566         return I40E_SUCCESS;
7567 }
7568
7569 /**
7570  * i40e_validate_profile
7571  * @hw: pointer to the hardware structure
7572  * @profile: pointer to the profile segment of the package to be validated
7573  * @track_id: package tracking id
7574  * @rollback: flag if the profile is for rollback.
7575  *
7576  * Validates supported devices and profile's sections.
7577  */
7578 STATIC enum i40e_status_code
7579 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7580                       u32 track_id, bool rollback)
7581 {
7582         struct i40e_profile_section_header *sec = NULL;
7583         enum i40e_status_code status = I40E_SUCCESS;
7584         struct i40e_section_table *sec_tbl;
7585         u32 vendor_dev_id;
7586         u32 dev_cnt;
7587         u32 sec_off;
7588         u32 i;
7589
7590         if (track_id == I40E_DDP_TRACKID_INVALID) {
7591                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7592                 return I40E_NOT_SUPPORTED;
7593         }
7594
7595         dev_cnt = profile->device_table_count;
7596         for (i = 0; i < dev_cnt; i++) {
7597                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7598                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7599                     hw->device_id == (vendor_dev_id & 0xFFFF))
7600                         break;
7601         }
7602         if (dev_cnt && (i == dev_cnt)) {
7603                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7604                            "Device doesn't support DDP\n");
7605                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7606         }
7607
7608         I40E_SECTION_TABLE(profile, sec_tbl);
7609
7610         /* Validate sections types */
7611         for (i = 0; i < sec_tbl->section_count; i++) {
7612                 sec_off = sec_tbl->section_offset[i];
7613                 sec = I40E_SECTION_HEADER(profile, sec_off);
7614                 if (rollback) {
7615                         if (sec->section.type == SECTION_TYPE_MMIO ||
7616                             sec->section.type == SECTION_TYPE_AQ ||
7617                             sec->section.type == SECTION_TYPE_RB_AQ) {
7618                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7619                                            "Not a roll-back package\n");
7620                                 return I40E_NOT_SUPPORTED;
7621                         }
7622                 } else {
7623                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7624                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7625                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7626                                            "Not an original package\n");
7627                                 return I40E_NOT_SUPPORTED;
7628                         }
7629                 }
7630         }
7631
7632         return status;
7633 }
7634
7635 /**
7636  * i40e_write_profile
7637  * @hw: pointer to the hardware structure
7638  * @profile: pointer to the profile segment of the package to be downloaded
7639  * @track_id: package tracking id
7640  *
7641  * Handles the download of a complete package.
7642  */
7643 enum i40e_status_code
7644 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7645                    u32 track_id)
7646 {
7647         enum i40e_status_code status = I40E_SUCCESS;
7648         struct i40e_section_table *sec_tbl;
7649         struct i40e_profile_section_header *sec = NULL;
7650         struct i40e_profile_aq_section *ddp_aq;
7651         u32 section_size = 0;
7652         u32 offset = 0, info = 0;
7653         u32 sec_off;
7654         u32 i;
7655
7656         status = i40e_validate_profile(hw, profile, track_id, false);
7657         if (status)
7658                 return status;
7659
7660         I40E_SECTION_TABLE(profile, sec_tbl);
7661
7662         for (i = 0; i < sec_tbl->section_count; i++) {
7663                 sec_off = sec_tbl->section_offset[i];
7664                 sec = I40E_SECTION_HEADER(profile, sec_off);
7665                 /* Process generic admin command */
7666                 if (sec->section.type == SECTION_TYPE_AQ) {
7667                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7668                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7669                         if (status) {
7670                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7671                                            "Failed to execute aq: section %d, opcode %u\n",
7672                                            i, ddp_aq->opcode);
7673                                 break;
7674                         }
7675                         sec->section.type = SECTION_TYPE_RB_AQ;
7676                 }
7677
7678                 /* Skip any non-mmio sections */
7679                 if (sec->section.type != SECTION_TYPE_MMIO)
7680                         continue;
7681
7682                 section_size = sec->section.size +
7683                         sizeof(struct i40e_profile_section_header);
7684
7685                 /* Write MMIO section */
7686                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7687                                            track_id, &offset, &info, NULL);
7688                 if (status) {
7689                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7690                                    "Failed to write profile: section %d, offset %d, info %d\n",
7691                                    i, offset, info);
7692                         break;
7693                 }
7694         }
7695         return status;
7696 }
7697
7698 /**
7699  * i40e_rollback_profile
7700  * @hw: pointer to the hardware structure
7701  * @profile: pointer to the profile segment of the package to be removed
7702  * @track_id: package tracking id
7703  *
7704  * Rolls back previously loaded package.
7705  */
7706 enum i40e_status_code
7707 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7708                       u32 track_id)
7709 {
7710         struct i40e_profile_section_header *sec = NULL;
7711         enum i40e_status_code status = I40E_SUCCESS;
7712         struct i40e_section_table *sec_tbl;
7713         u32 offset = 0, info = 0;
7714         u32 section_size = 0;
7715         u32 sec_off;
7716         int i;
7717
7718         status = i40e_validate_profile(hw, profile, track_id, true);
7719         if (status)
7720                 return status;
7721
7722         I40E_SECTION_TABLE(profile, sec_tbl);
7723
7724         /* For rollback write sections in reverse */
7725         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7726                 sec_off = sec_tbl->section_offset[i];
7727                 sec = I40E_SECTION_HEADER(profile, sec_off);
7728
7729                 /* Skip any non-rollback sections */
7730                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7731                         continue;
7732
7733                 section_size = sec->section.size +
7734                         sizeof(struct i40e_profile_section_header);
7735
7736                 /* Write roll-back MMIO section */
7737                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7738                                            track_id, &offset, &info, NULL);
7739                 if (status) {
7740                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7741                                    "Failed to write profile: section %d, offset %d, info %d\n",
7742                                    i, offset, info);
7743                         break;
7744                 }
7745         }
7746         return status;
7747 }
7748
7749 /**
7750  * i40e_add_pinfo_to_list
7751  * @hw: pointer to the hardware structure
7752  * @profile: pointer to the profile segment of the package
7753  * @profile_info_sec: buffer for information section
7754  * @track_id: package tracking id
7755  *
7756  * Register a profile to the list of loaded profiles.
7757  */
7758 enum i40e_status_code
7759 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7760                        struct i40e_profile_segment *profile,
7761                        u8 *profile_info_sec, u32 track_id)
7762 {
7763         enum i40e_status_code status = I40E_SUCCESS;
7764         struct i40e_profile_section_header *sec = NULL;
7765         struct i40e_profile_info *pinfo;
7766         u32 offset = 0, info = 0;
7767
7768         sec = (struct i40e_profile_section_header *)profile_info_sec;
7769         sec->tbl_size = 1;
7770         sec->data_end = sizeof(struct i40e_profile_section_header) +
7771                         sizeof(struct i40e_profile_info);
7772         sec->section.type = SECTION_TYPE_INFO;
7773         sec->section.offset = sizeof(struct i40e_profile_section_header);
7774         sec->section.size = sizeof(struct i40e_profile_info);
7775         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7776                                              sec->section.offset);
7777         pinfo->track_id = track_id;
7778         pinfo->version = profile->version;
7779         pinfo->op = I40E_DDP_ADD_TRACKID;
7780         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7781                     I40E_NONDMA_TO_NONDMA);
7782
7783         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7784                                    track_id, &offset, &info, NULL);
7785         return status;
7786 }