1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 hw->mac.type = I40E_MAC_XL710;
73 #ifdef X722_A0_SUPPORT
74 case I40E_DEV_ID_X722_A0:
76 case I40E_DEV_ID_KX_X722:
77 case I40E_DEV_ID_QSFP_X722:
78 case I40E_DEV_ID_SFP_X722:
79 case I40E_DEV_ID_1G_BASE_T_X722:
80 case I40E_DEV_ID_10G_BASE_T_X722:
81 hw->mac.type = I40E_MAC_X722;
85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
86 case I40E_DEV_ID_X722_VF:
87 case I40E_DEV_ID_X722_VF_HV:
88 #ifdef X722_A0_SUPPORT
89 case I40E_DEV_ID_X722_A0_VF:
91 hw->mac.type = I40E_MAC_X722_VF;
93 #endif /* INTEGRATED_VF || VF_DRIVER */
94 #endif /* X722_SUPPORT */
95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
97 case I40E_DEV_ID_VF_HV:
98 hw->mac.type = I40E_MAC_VF;
102 hw->mac.type = I40E_MAC_GENERIC;
106 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
109 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
110 hw->mac.type, status);
114 #ifndef I40E_NDIS_SUPPORT
116 * i40e_aq_str - convert AQ err code to a string
117 * @hw: pointer to the HW structure
118 * @aq_err: the AQ error code to convert
120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
125 case I40E_AQ_RC_EPERM:
126 return "I40E_AQ_RC_EPERM";
127 case I40E_AQ_RC_ENOENT:
128 return "I40E_AQ_RC_ENOENT";
129 case I40E_AQ_RC_ESRCH:
130 return "I40E_AQ_RC_ESRCH";
131 case I40E_AQ_RC_EINTR:
132 return "I40E_AQ_RC_EINTR";
134 return "I40E_AQ_RC_EIO";
135 case I40E_AQ_RC_ENXIO:
136 return "I40E_AQ_RC_ENXIO";
137 case I40E_AQ_RC_E2BIG:
138 return "I40E_AQ_RC_E2BIG";
139 case I40E_AQ_RC_EAGAIN:
140 return "I40E_AQ_RC_EAGAIN";
141 case I40E_AQ_RC_ENOMEM:
142 return "I40E_AQ_RC_ENOMEM";
143 case I40E_AQ_RC_EACCES:
144 return "I40E_AQ_RC_EACCES";
145 case I40E_AQ_RC_EFAULT:
146 return "I40E_AQ_RC_EFAULT";
147 case I40E_AQ_RC_EBUSY:
148 return "I40E_AQ_RC_EBUSY";
149 case I40E_AQ_RC_EEXIST:
150 return "I40E_AQ_RC_EEXIST";
151 case I40E_AQ_RC_EINVAL:
152 return "I40E_AQ_RC_EINVAL";
153 case I40E_AQ_RC_ENOTTY:
154 return "I40E_AQ_RC_ENOTTY";
155 case I40E_AQ_RC_ENOSPC:
156 return "I40E_AQ_RC_ENOSPC";
157 case I40E_AQ_RC_ENOSYS:
158 return "I40E_AQ_RC_ENOSYS";
159 case I40E_AQ_RC_ERANGE:
160 return "I40E_AQ_RC_ERANGE";
161 case I40E_AQ_RC_EFLUSHED:
162 return "I40E_AQ_RC_EFLUSHED";
163 case I40E_AQ_RC_BAD_ADDR:
164 return "I40E_AQ_RC_BAD_ADDR";
165 case I40E_AQ_RC_EMODE:
166 return "I40E_AQ_RC_EMODE";
167 case I40E_AQ_RC_EFBIG:
168 return "I40E_AQ_RC_EFBIG";
171 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
176 * i40e_stat_str - convert status err code to a string
177 * @hw: pointer to the HW structure
178 * @stat_err: the status error code to convert
180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
186 return "I40E_ERR_NVM";
187 case I40E_ERR_NVM_CHECKSUM:
188 return "I40E_ERR_NVM_CHECKSUM";
190 return "I40E_ERR_PHY";
191 case I40E_ERR_CONFIG:
192 return "I40E_ERR_CONFIG";
194 return "I40E_ERR_PARAM";
195 case I40E_ERR_MAC_TYPE:
196 return "I40E_ERR_MAC_TYPE";
197 case I40E_ERR_UNKNOWN_PHY:
198 return "I40E_ERR_UNKNOWN_PHY";
199 case I40E_ERR_LINK_SETUP:
200 return "I40E_ERR_LINK_SETUP";
201 case I40E_ERR_ADAPTER_STOPPED:
202 return "I40E_ERR_ADAPTER_STOPPED";
203 case I40E_ERR_INVALID_MAC_ADDR:
204 return "I40E_ERR_INVALID_MAC_ADDR";
205 case I40E_ERR_DEVICE_NOT_SUPPORTED:
206 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
207 case I40E_ERR_MASTER_REQUESTS_PENDING:
208 return "I40E_ERR_MASTER_REQUESTS_PENDING";
209 case I40E_ERR_INVALID_LINK_SETTINGS:
210 return "I40E_ERR_INVALID_LINK_SETTINGS";
211 case I40E_ERR_AUTONEG_NOT_COMPLETE:
212 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
213 case I40E_ERR_RESET_FAILED:
214 return "I40E_ERR_RESET_FAILED";
215 case I40E_ERR_SWFW_SYNC:
216 return "I40E_ERR_SWFW_SYNC";
217 case I40E_ERR_NO_AVAILABLE_VSI:
218 return "I40E_ERR_NO_AVAILABLE_VSI";
219 case I40E_ERR_NO_MEMORY:
220 return "I40E_ERR_NO_MEMORY";
221 case I40E_ERR_BAD_PTR:
222 return "I40E_ERR_BAD_PTR";
223 case I40E_ERR_RING_FULL:
224 return "I40E_ERR_RING_FULL";
225 case I40E_ERR_INVALID_PD_ID:
226 return "I40E_ERR_INVALID_PD_ID";
227 case I40E_ERR_INVALID_QP_ID:
228 return "I40E_ERR_INVALID_QP_ID";
229 case I40E_ERR_INVALID_CQ_ID:
230 return "I40E_ERR_INVALID_CQ_ID";
231 case I40E_ERR_INVALID_CEQ_ID:
232 return "I40E_ERR_INVALID_CEQ_ID";
233 case I40E_ERR_INVALID_AEQ_ID:
234 return "I40E_ERR_INVALID_AEQ_ID";
235 case I40E_ERR_INVALID_SIZE:
236 return "I40E_ERR_INVALID_SIZE";
237 case I40E_ERR_INVALID_ARP_INDEX:
238 return "I40E_ERR_INVALID_ARP_INDEX";
239 case I40E_ERR_INVALID_FPM_FUNC_ID:
240 return "I40E_ERR_INVALID_FPM_FUNC_ID";
241 case I40E_ERR_QP_INVALID_MSG_SIZE:
242 return "I40E_ERR_QP_INVALID_MSG_SIZE";
243 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
244 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
245 case I40E_ERR_INVALID_FRAG_COUNT:
246 return "I40E_ERR_INVALID_FRAG_COUNT";
247 case I40E_ERR_QUEUE_EMPTY:
248 return "I40E_ERR_QUEUE_EMPTY";
249 case I40E_ERR_INVALID_ALIGNMENT:
250 return "I40E_ERR_INVALID_ALIGNMENT";
251 case I40E_ERR_FLUSHED_QUEUE:
252 return "I40E_ERR_FLUSHED_QUEUE";
253 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
254 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
255 case I40E_ERR_INVALID_IMM_DATA_SIZE:
256 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
257 case I40E_ERR_TIMEOUT:
258 return "I40E_ERR_TIMEOUT";
259 case I40E_ERR_OPCODE_MISMATCH:
260 return "I40E_ERR_OPCODE_MISMATCH";
261 case I40E_ERR_CQP_COMPL_ERROR:
262 return "I40E_ERR_CQP_COMPL_ERROR";
263 case I40E_ERR_INVALID_VF_ID:
264 return "I40E_ERR_INVALID_VF_ID";
265 case I40E_ERR_INVALID_HMCFN_ID:
266 return "I40E_ERR_INVALID_HMCFN_ID";
267 case I40E_ERR_BACKING_PAGE_ERROR:
268 return "I40E_ERR_BACKING_PAGE_ERROR";
269 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
270 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
271 case I40E_ERR_INVALID_PBLE_INDEX:
272 return "I40E_ERR_INVALID_PBLE_INDEX";
273 case I40E_ERR_INVALID_SD_INDEX:
274 return "I40E_ERR_INVALID_SD_INDEX";
275 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
276 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
277 case I40E_ERR_INVALID_SD_TYPE:
278 return "I40E_ERR_INVALID_SD_TYPE";
279 case I40E_ERR_MEMCPY_FAILED:
280 return "I40E_ERR_MEMCPY_FAILED";
281 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
282 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
283 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
284 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
285 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
286 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
287 case I40E_ERR_SRQ_ENABLED:
288 return "I40E_ERR_SRQ_ENABLED";
289 case I40E_ERR_ADMIN_QUEUE_ERROR:
290 return "I40E_ERR_ADMIN_QUEUE_ERROR";
291 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
292 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
293 case I40E_ERR_BUF_TOO_SHORT:
294 return "I40E_ERR_BUF_TOO_SHORT";
295 case I40E_ERR_ADMIN_QUEUE_FULL:
296 return "I40E_ERR_ADMIN_QUEUE_FULL";
297 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
298 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
299 case I40E_ERR_BAD_IWARP_CQE:
300 return "I40E_ERR_BAD_IWARP_CQE";
301 case I40E_ERR_NVM_BLANK_MODE:
302 return "I40E_ERR_NVM_BLANK_MODE";
303 case I40E_ERR_NOT_IMPLEMENTED:
304 return "I40E_ERR_NOT_IMPLEMENTED";
305 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
306 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
307 case I40E_ERR_DIAG_TEST_FAILED:
308 return "I40E_ERR_DIAG_TEST_FAILED";
309 case I40E_ERR_NOT_READY:
310 return "I40E_ERR_NOT_READY";
311 case I40E_NOT_SUPPORTED:
312 return "I40E_NOT_SUPPORTED";
313 case I40E_ERR_FIRMWARE_API_VERSION:
314 return "I40E_ERR_FIRMWARE_API_VERSION";
317 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
321 #endif /* I40E_NDIS_SUPPORT */
324 * @hw: debug mask related to admin queue
326 * @desc: pointer to admin queue descriptor
327 * @buffer: pointer to command buffer
328 * @buf_len: max length of buffer
330 * Dumps debug log about adminq command with descriptor contents.
332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
333 void *buffer, u16 buf_len)
335 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
336 u16 len = LE16_TO_CPU(aq_desc->datalen);
337 u8 *buf = (u8 *)buffer;
340 if ((!(mask & hw->debug_mask)) || (desc == NULL))
344 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
345 LE16_TO_CPU(aq_desc->opcode),
346 LE16_TO_CPU(aq_desc->flags),
347 LE16_TO_CPU(aq_desc->datalen),
348 LE16_TO_CPU(aq_desc->retval));
349 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
350 LE32_TO_CPU(aq_desc->cookie_high),
351 LE32_TO_CPU(aq_desc->cookie_low));
352 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->params.internal.param0),
354 LE32_TO_CPU(aq_desc->params.internal.param1));
355 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
356 LE32_TO_CPU(aq_desc->params.external.addr_high),
357 LE32_TO_CPU(aq_desc->params.external.addr_low));
359 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
360 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
363 /* write the full 16-byte chunks */
364 for (i = 0; i < (len - 16); i += 16)
366 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
367 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
368 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
369 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
370 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
371 /* the most we could have left is 16 bytes, pad with zeros */
376 memset(d_buf, 0, sizeof(d_buf));
377 for (j = 0; i < len; j++, i++)
380 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
381 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
382 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
383 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
384 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
390 * i40e_check_asq_alive
391 * @hw: pointer to the hw struct
393 * Returns true if Queue is enabled else false.
395 bool i40e_check_asq_alive(struct i40e_hw *hw)
401 return !!(rd32(hw, hw->aq.asq.len) &
402 I40E_PF_ATQLEN_ATQENABLE_MASK);
404 return !!(rd32(hw, hw->aq.asq.len) &
405 I40E_PF_ATQLEN_ATQENABLE_MASK);
406 #endif /* INTEGRATED_VF */
407 #endif /* PF_DRIVER */
411 return !!(rd32(hw, hw->aq.asq.len) &
412 I40E_VF_ATQLEN1_ATQENABLE_MASK);
414 return !!(rd32(hw, hw->aq.asq.len) &
415 I40E_VF_ATQLEN1_ATQENABLE_MASK);
416 #endif /* INTEGRATED_VF */
417 #endif /* VF_DRIVER */
422 * i40e_aq_queue_shutdown
423 * @hw: pointer to the hw struct
424 * @unloading: is the driver unloading itself
426 * Tell the Firmware that we're shutting down the AdminQ and whether
427 * or not the driver is unloading as well.
429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
432 struct i40e_aq_desc desc;
433 struct i40e_aqc_queue_shutdown *cmd =
434 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
435 enum i40e_status_code status;
437 i40e_fill_default_direct_cmd_desc(&desc,
438 i40e_aqc_opc_queue_shutdown);
441 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
442 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
449 * i40e_aq_get_set_rss_lut
450 * @hw: pointer to the hardware structure
451 * @vsi_id: vsi fw index
452 * @pf_lut: for PF table set true, for VSI table set false
453 * @lut: pointer to the lut buffer provided by the caller
454 * @lut_size: size of the lut buffer
455 * @set: set true to set the table, false to get the table
457 * Internal function to get or set RSS look up table
459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
460 u16 vsi_id, bool pf_lut,
461 u8 *lut, u16 lut_size,
464 enum i40e_status_code status;
465 struct i40e_aq_desc desc;
466 struct i40e_aqc_get_set_rss_lut *cmd_resp =
467 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
470 i40e_fill_default_direct_cmd_desc(&desc,
471 i40e_aqc_opc_set_rss_lut);
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_get_rss_lut);
476 /* Indirect command */
477 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
478 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
481 CPU_TO_LE16((u16)((vsi_id <<
482 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
483 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
484 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
487 cmd_resp->flags |= CPU_TO_LE16((u16)
488 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
489 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
490 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
492 cmd_resp->flags |= CPU_TO_LE16((u16)
493 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
495 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
497 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
503 * i40e_aq_get_rss_lut
504 * @hw: pointer to the hardware structure
505 * @vsi_id: vsi fw index
506 * @pf_lut: for PF table set true, for VSI table set false
507 * @lut: pointer to the lut buffer provided by the caller
508 * @lut_size: size of the lut buffer
510 * get the RSS lookup table, PF or VSI type
512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
513 bool pf_lut, u8 *lut, u16 lut_size)
515 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
520 * i40e_aq_set_rss_lut
521 * @hw: pointer to the hardware structure
522 * @vsi_id: vsi fw index
523 * @pf_lut: for PF table set true, for VSI table set false
524 * @lut: pointer to the lut buffer provided by the caller
525 * @lut_size: size of the lut buffer
527 * set the RSS lookup table, PF or VSI type
529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
530 bool pf_lut, u8 *lut, u16 lut_size)
532 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
536 * i40e_aq_get_set_rss_key
537 * @hw: pointer to the hw struct
538 * @vsi_id: vsi fw index
539 * @key: pointer to key info struct
540 * @set: set true to set the key, false to get the key
542 * get the RSS key per VSI
544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
546 struct i40e_aqc_get_set_rss_key_data *key,
549 enum i40e_status_code status;
550 struct i40e_aq_desc desc;
551 struct i40e_aqc_get_set_rss_key *cmd_resp =
552 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
553 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
556 i40e_fill_default_direct_cmd_desc(&desc,
557 i40e_aqc_opc_set_rss_key);
559 i40e_fill_default_direct_cmd_desc(&desc,
560 i40e_aqc_opc_get_rss_key);
562 /* Indirect command */
563 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
564 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
567 CPU_TO_LE16((u16)((vsi_id <<
568 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
569 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
570 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
572 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
578 * i40e_aq_get_rss_key
579 * @hw: pointer to the hw struct
580 * @vsi_id: vsi fw index
581 * @key: pointer to key info struct
584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
586 struct i40e_aqc_get_set_rss_key_data *key)
588 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
592 * i40e_aq_set_rss_key
593 * @hw: pointer to the hw struct
594 * @vsi_id: vsi fw index
595 * @key: pointer to key info struct
597 * set the RSS key per VSI
599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
601 struct i40e_aqc_get_set_rss_key_data *key)
603 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
605 #endif /* X722_SUPPORT */
607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
608 * hardware to a bit-field that can be used by SW to more easily determine the
611 * Macros are used to shorten the table lines and make this table human
614 * We store the PTYPE in the top byte of the bit field - this is just so that
615 * we can check that the table doesn't have a row missing, as the index into
616 * the table should be the PTYPE.
620 * IF NOT i40e_ptype_lookup[ptype].known
623 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
624 * Use the rest of the fields to look at the tunnels, inner protocols, etc
626 * Use the enum i40e_rx_l2_ptype to decode the packet type
630 /* macro to make the table lines short */
631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
634 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
635 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
636 I40E_RX_PTYPE_##OUTER_FRAG, \
637 I40E_RX_PTYPE_TUNNEL_##T, \
638 I40E_RX_PTYPE_TUNNEL_END_##TE, \
639 I40E_RX_PTYPE_##TEF, \
640 I40E_RX_PTYPE_INNER_PROT_##I, \
641 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
644 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
646 /* shorter macros makes the table fit but are terse */
647 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
648 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
649 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
653 /* L2 Packet types */
654 I40E_PTT_UNUSED_ENTRY(0),
655 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
656 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
657 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
658 I40E_PTT_UNUSED_ENTRY(4),
659 I40E_PTT_UNUSED_ENTRY(5),
660 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(8),
663 I40E_PTT_UNUSED_ENTRY(9),
664 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
666 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
668 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 /* Non Tunneled IPv4 */
678 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
680 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
681 I40E_PTT_UNUSED_ENTRY(25),
682 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
683 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
684 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
687 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
688 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
689 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
690 I40E_PTT_UNUSED_ENTRY(32),
691 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
692 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
693 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
696 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
697 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
698 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
699 I40E_PTT_UNUSED_ENTRY(39),
700 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
701 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
702 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
704 /* IPv4 --> GRE/NAT */
705 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
707 /* IPv4 --> GRE/NAT --> IPv4 */
708 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
709 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
710 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
711 I40E_PTT_UNUSED_ENTRY(47),
712 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
713 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
714 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
716 /* IPv4 --> GRE/NAT --> IPv6 */
717 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
718 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
719 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
720 I40E_PTT_UNUSED_ENTRY(54),
721 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
722 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
723 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
725 /* IPv4 --> GRE/NAT --> MAC */
726 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
728 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
729 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
730 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
731 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
732 I40E_PTT_UNUSED_ENTRY(62),
733 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
734 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
735 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
737 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
738 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
739 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
740 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
741 I40E_PTT_UNUSED_ENTRY(69),
742 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
743 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
744 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
746 /* IPv4 --> GRE/NAT --> MAC/VLAN */
747 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
749 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
750 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
751 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
752 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
753 I40E_PTT_UNUSED_ENTRY(77),
754 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
755 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
756 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
758 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
759 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
760 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
761 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
762 I40E_PTT_UNUSED_ENTRY(84),
763 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
764 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
765 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
767 /* Non Tunneled IPv6 */
768 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
769 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
770 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
771 I40E_PTT_UNUSED_ENTRY(91),
772 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
773 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
774 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
777 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
778 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
779 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
780 I40E_PTT_UNUSED_ENTRY(98),
781 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
782 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
783 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
786 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
787 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
788 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
789 I40E_PTT_UNUSED_ENTRY(105),
790 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
791 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
792 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
794 /* IPv6 --> GRE/NAT */
795 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
797 /* IPv6 --> GRE/NAT -> IPv4 */
798 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
799 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
800 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
801 I40E_PTT_UNUSED_ENTRY(113),
802 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
803 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
804 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
806 /* IPv6 --> GRE/NAT -> IPv6 */
807 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
808 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
809 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
810 I40E_PTT_UNUSED_ENTRY(120),
811 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
812 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
813 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
815 /* IPv6 --> GRE/NAT -> MAC */
816 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
818 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
819 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
820 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
821 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
822 I40E_PTT_UNUSED_ENTRY(128),
823 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
824 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
825 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
827 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
828 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
829 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
830 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
831 I40E_PTT_UNUSED_ENTRY(135),
832 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
833 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
834 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
836 /* IPv6 --> GRE/NAT -> MAC/VLAN */
837 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
839 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
840 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
841 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
842 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
843 I40E_PTT_UNUSED_ENTRY(143),
844 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
845 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
846 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
848 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
849 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
850 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
851 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
852 I40E_PTT_UNUSED_ENTRY(150),
853 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
854 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
855 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
858 I40E_PTT_UNUSED_ENTRY(154),
859 I40E_PTT_UNUSED_ENTRY(155),
860 I40E_PTT_UNUSED_ENTRY(156),
861 I40E_PTT_UNUSED_ENTRY(157),
862 I40E_PTT_UNUSED_ENTRY(158),
863 I40E_PTT_UNUSED_ENTRY(159),
865 I40E_PTT_UNUSED_ENTRY(160),
866 I40E_PTT_UNUSED_ENTRY(161),
867 I40E_PTT_UNUSED_ENTRY(162),
868 I40E_PTT_UNUSED_ENTRY(163),
869 I40E_PTT_UNUSED_ENTRY(164),
870 I40E_PTT_UNUSED_ENTRY(165),
871 I40E_PTT_UNUSED_ENTRY(166),
872 I40E_PTT_UNUSED_ENTRY(167),
873 I40E_PTT_UNUSED_ENTRY(168),
874 I40E_PTT_UNUSED_ENTRY(169),
876 I40E_PTT_UNUSED_ENTRY(170),
877 I40E_PTT_UNUSED_ENTRY(171),
878 I40E_PTT_UNUSED_ENTRY(172),
879 I40E_PTT_UNUSED_ENTRY(173),
880 I40E_PTT_UNUSED_ENTRY(174),
881 I40E_PTT_UNUSED_ENTRY(175),
882 I40E_PTT_UNUSED_ENTRY(176),
883 I40E_PTT_UNUSED_ENTRY(177),
884 I40E_PTT_UNUSED_ENTRY(178),
885 I40E_PTT_UNUSED_ENTRY(179),
887 I40E_PTT_UNUSED_ENTRY(180),
888 I40E_PTT_UNUSED_ENTRY(181),
889 I40E_PTT_UNUSED_ENTRY(182),
890 I40E_PTT_UNUSED_ENTRY(183),
891 I40E_PTT_UNUSED_ENTRY(184),
892 I40E_PTT_UNUSED_ENTRY(185),
893 I40E_PTT_UNUSED_ENTRY(186),
894 I40E_PTT_UNUSED_ENTRY(187),
895 I40E_PTT_UNUSED_ENTRY(188),
896 I40E_PTT_UNUSED_ENTRY(189),
898 I40E_PTT_UNUSED_ENTRY(190),
899 I40E_PTT_UNUSED_ENTRY(191),
900 I40E_PTT_UNUSED_ENTRY(192),
901 I40E_PTT_UNUSED_ENTRY(193),
902 I40E_PTT_UNUSED_ENTRY(194),
903 I40E_PTT_UNUSED_ENTRY(195),
904 I40E_PTT_UNUSED_ENTRY(196),
905 I40E_PTT_UNUSED_ENTRY(197),
906 I40E_PTT_UNUSED_ENTRY(198),
907 I40E_PTT_UNUSED_ENTRY(199),
909 I40E_PTT_UNUSED_ENTRY(200),
910 I40E_PTT_UNUSED_ENTRY(201),
911 I40E_PTT_UNUSED_ENTRY(202),
912 I40E_PTT_UNUSED_ENTRY(203),
913 I40E_PTT_UNUSED_ENTRY(204),
914 I40E_PTT_UNUSED_ENTRY(205),
915 I40E_PTT_UNUSED_ENTRY(206),
916 I40E_PTT_UNUSED_ENTRY(207),
917 I40E_PTT_UNUSED_ENTRY(208),
918 I40E_PTT_UNUSED_ENTRY(209),
920 I40E_PTT_UNUSED_ENTRY(210),
921 I40E_PTT_UNUSED_ENTRY(211),
922 I40E_PTT_UNUSED_ENTRY(212),
923 I40E_PTT_UNUSED_ENTRY(213),
924 I40E_PTT_UNUSED_ENTRY(214),
925 I40E_PTT_UNUSED_ENTRY(215),
926 I40E_PTT_UNUSED_ENTRY(216),
927 I40E_PTT_UNUSED_ENTRY(217),
928 I40E_PTT_UNUSED_ENTRY(218),
929 I40E_PTT_UNUSED_ENTRY(219),
931 I40E_PTT_UNUSED_ENTRY(220),
932 I40E_PTT_UNUSED_ENTRY(221),
933 I40E_PTT_UNUSED_ENTRY(222),
934 I40E_PTT_UNUSED_ENTRY(223),
935 I40E_PTT_UNUSED_ENTRY(224),
936 I40E_PTT_UNUSED_ENTRY(225),
937 I40E_PTT_UNUSED_ENTRY(226),
938 I40E_PTT_UNUSED_ENTRY(227),
939 I40E_PTT_UNUSED_ENTRY(228),
940 I40E_PTT_UNUSED_ENTRY(229),
942 I40E_PTT_UNUSED_ENTRY(230),
943 I40E_PTT_UNUSED_ENTRY(231),
944 I40E_PTT_UNUSED_ENTRY(232),
945 I40E_PTT_UNUSED_ENTRY(233),
946 I40E_PTT_UNUSED_ENTRY(234),
947 I40E_PTT_UNUSED_ENTRY(235),
948 I40E_PTT_UNUSED_ENTRY(236),
949 I40E_PTT_UNUSED_ENTRY(237),
950 I40E_PTT_UNUSED_ENTRY(238),
951 I40E_PTT_UNUSED_ENTRY(239),
953 I40E_PTT_UNUSED_ENTRY(240),
954 I40E_PTT_UNUSED_ENTRY(241),
955 I40E_PTT_UNUSED_ENTRY(242),
956 I40E_PTT_UNUSED_ENTRY(243),
957 I40E_PTT_UNUSED_ENTRY(244),
958 I40E_PTT_UNUSED_ENTRY(245),
959 I40E_PTT_UNUSED_ENTRY(246),
960 I40E_PTT_UNUSED_ENTRY(247),
961 I40E_PTT_UNUSED_ENTRY(248),
962 I40E_PTT_UNUSED_ENTRY(249),
964 I40E_PTT_UNUSED_ENTRY(250),
965 I40E_PTT_UNUSED_ENTRY(251),
966 I40E_PTT_UNUSED_ENTRY(252),
967 I40E_PTT_UNUSED_ENTRY(253),
968 I40E_PTT_UNUSED_ENTRY(254),
969 I40E_PTT_UNUSED_ENTRY(255)
974 * i40e_validate_mac_addr - Validate unicast MAC address
975 * @mac_addr: pointer to MAC address
977 * Tests a MAC address to ensure it is a valid Individual Address
979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
981 enum i40e_status_code status = I40E_SUCCESS;
983 DEBUGFUNC("i40e_validate_mac_addr");
985 /* Broadcast addresses ARE multicast addresses
986 * Make sure it is not a multicast address
987 * Reject the zero address
989 if (I40E_IS_MULTICAST(mac_addr) ||
990 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
991 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
992 status = I40E_ERR_INVALID_MAC_ADDR;
999 * i40e_init_shared_code - Initialize the shared code
1000 * @hw: pointer to hardware structure
1002 * This assigns the MAC type and PHY code and inits the NVM.
1003 * Does not touch the hardware. This function must be called prior to any
1004 * other function in the shared code. The i40e_hw structure should be
1005 * memset to 0 prior to calling this function. The following fields in
1006 * hw structure should be filled in prior to calling this function:
1007 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008 * subsystem_vendor_id, and revision_id
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1012 enum i40e_status_code status = I40E_SUCCESS;
1013 u32 port, ari, func_rid;
1015 DEBUGFUNC("i40e_init_shared_code");
1017 i40e_set_mac_type(hw);
1019 switch (hw->mac.type) {
1020 case I40E_MAC_XL710:
1026 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1029 hw->phy.get_link_info = true;
1031 /* Determine port number and PF number*/
1032 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034 hw->port = (u8)port;
1035 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1039 hw->pf_id = (u8)(func_rid & 0xff);
1041 hw->pf_id = (u8)(func_rid & 0x7);
1044 if (hw->mac.type == I40E_MAC_X722)
1045 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1048 status = i40e_init_nvm(hw);
1053 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054 * @hw: pointer to the hw struct
1055 * @flags: a return indicator of what addresses were added to the addr store
1056 * @addrs: the requestor's mac addr store
1057 * @cmd_details: pointer to command details structure or NULL
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1061 struct i40e_aqc_mac_address_read_data *addrs,
1062 struct i40e_asq_cmd_details *cmd_details)
1064 struct i40e_aq_desc desc;
1065 struct i40e_aqc_mac_address_read *cmd_data =
1066 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067 enum i40e_status_code status;
1069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1072 status = i40e_asq_send_command(hw, &desc, addrs,
1073 sizeof(*addrs), cmd_details);
1074 *flags = LE16_TO_CPU(cmd_data->command_flags);
1080 * i40e_aq_mac_address_write - Change the MAC addresses
1081 * @hw: pointer to the hw struct
1082 * @flags: indicates which MAC to be written
1083 * @mac_addr: address to write
1084 * @cmd_details: pointer to command details structure or NULL
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087 u16 flags, u8 *mac_addr,
1088 struct i40e_asq_cmd_details *cmd_details)
1090 struct i40e_aq_desc desc;
1091 struct i40e_aqc_mac_address_write *cmd_data =
1092 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093 enum i40e_status_code status;
1095 i40e_fill_default_direct_cmd_desc(&desc,
1096 i40e_aqc_opc_mac_address_write);
1097 cmd_data->command_flags = CPU_TO_LE16(flags);
1098 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100 ((u32)mac_addr[3] << 16) |
1101 ((u32)mac_addr[4] << 8) |
1104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1110 * i40e_get_mac_addr - get MAC address
1111 * @hw: pointer to the HW structure
1112 * @mac_addr: pointer to MAC address
1114 * Reads the adapter's MAC address from register
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1118 struct i40e_aqc_mac_address_read_data addrs;
1119 enum i40e_status_code status;
1122 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1124 if (flags & I40E_AQC_LAN_ADDR_VALID)
1125 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1131 * i40e_get_port_mac_addr - get Port MAC address
1132 * @hw: pointer to the HW structure
1133 * @mac_addr: pointer to Port MAC address
1135 * Reads the adapter's Port MAC address
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1139 struct i40e_aqc_mac_address_read_data addrs;
1140 enum i40e_status_code status;
1143 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1147 if (flags & I40E_AQC_PORT_ADDR_VALID)
1148 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1150 status = I40E_ERR_INVALID_MAC_ADDR;
1156 * i40e_pre_tx_queue_cfg - pre tx queue configure
1157 * @hw: pointer to the HW structure
1158 * @queue: target pf queue index
1159 * @enable: state change request
1161 * Handles hw requirement to indicate intention to enable
1162 * or disable target queue.
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1166 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1170 if (abs_queue_idx >= 128) {
1171 reg_block = abs_queue_idx / 128;
1172 abs_queue_idx %= 128;
1175 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1180 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1182 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1184 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1188 * i40e_read_pba_string - Reads part number string from EEPROM
1189 * @hw: pointer to hardware structure
1190 * @pba_num: stores the part number string from the EEPROM
1191 * @pba_num_size: part number string buffer length
1193 * Reads the part number string from the EEPROM.
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1198 enum i40e_status_code status = I40E_SUCCESS;
1204 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1210 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211 if (status != I40E_SUCCESS) {
1212 DEBUGOUT("Failed to read PBA Block pointer.\n");
1216 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217 if (status != I40E_SUCCESS) {
1218 DEBUGOUT("Failed to read PBA Block size.\n");
1222 /* Subtract one to get PBA word count (PBA Size word is included in
1226 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227 DEBUGOUT("Buffer to small for PBA data.\n");
1228 return I40E_ERR_PARAM;
1231 for (i = 0; i < pba_size; i++) {
1232 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233 if (status != I40E_SUCCESS) {
1234 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1238 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1241 pba_num[(pba_size * 2)] = '\0';
1247 * i40e_get_media_type - Gets media type
1248 * @hw: pointer to the hardware structure
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1252 enum i40e_media_type media;
1254 switch (hw->phy.link_info.phy_type) {
1255 case I40E_PHY_TYPE_10GBASE_SR:
1256 case I40E_PHY_TYPE_10GBASE_LR:
1257 case I40E_PHY_TYPE_1000BASE_SX:
1258 case I40E_PHY_TYPE_1000BASE_LX:
1259 case I40E_PHY_TYPE_40GBASE_SR4:
1260 case I40E_PHY_TYPE_40GBASE_LR4:
1261 media = I40E_MEDIA_TYPE_FIBER;
1263 case I40E_PHY_TYPE_100BASE_TX:
1264 case I40E_PHY_TYPE_1000BASE_T:
1265 case I40E_PHY_TYPE_10GBASE_T:
1266 media = I40E_MEDIA_TYPE_BASET;
1268 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270 case I40E_PHY_TYPE_10GBASE_CR1:
1271 case I40E_PHY_TYPE_40GBASE_CR4:
1272 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273 case I40E_PHY_TYPE_40GBASE_AOC:
1274 case I40E_PHY_TYPE_10GBASE_AOC:
1275 media = I40E_MEDIA_TYPE_DA;
1277 case I40E_PHY_TYPE_1000BASE_KX:
1278 case I40E_PHY_TYPE_10GBASE_KX4:
1279 case I40E_PHY_TYPE_10GBASE_KR:
1280 case I40E_PHY_TYPE_40GBASE_KR4:
1281 case I40E_PHY_TYPE_20GBASE_KR2:
1282 media = I40E_MEDIA_TYPE_BACKPLANE;
1284 case I40E_PHY_TYPE_SGMII:
1285 case I40E_PHY_TYPE_XAUI:
1286 case I40E_PHY_TYPE_XFI:
1287 case I40E_PHY_TYPE_XLAUI:
1288 case I40E_PHY_TYPE_XLPPI:
1290 media = I40E_MEDIA_TYPE_UNKNOWN;
1297 #define I40E_PF_RESET_WAIT_COUNT 200
1299 * i40e_pf_reset - Reset the PF
1300 * @hw: pointer to the hardware structure
1302 * Assuming someone else has triggered a global reset,
1303 * assure the global reset is complete and then reset the PF
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1312 /* Poll for Global Reset steady state in case of recent GRST.
1313 * The grst delay value is in 100ms units, and we'll wait a
1314 * couple counts longer to be sure we don't just miss the end.
1316 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319 #ifdef I40E_ESS_SUPPORT
1320 /* It can take upto 15 secs for GRST steady state */
1321 grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1323 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1324 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1327 i40e_msec_delay(100);
1329 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330 DEBUGOUT("Global reset polling failed to complete.\n");
1331 return I40E_ERR_RESET_FAILED;
1334 /* Now Wait for the FW to be ready */
1335 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336 reg = rd32(hw, I40E_GLNVM_ULD);
1337 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1344 i40e_msec_delay(10);
1346 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348 DEBUGOUT("wait for FW Reset complete timedout\n");
1349 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350 return I40E_ERR_RESET_FAILED;
1353 /* If there was a Global Reset in progress when we got here,
1354 * we don't need to do the PF Reset
1357 reg = rd32(hw, I40E_PFGEN_CTRL);
1358 wr32(hw, I40E_PFGEN_CTRL,
1359 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361 reg = rd32(hw, I40E_PFGEN_CTRL);
1362 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1366 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367 DEBUGOUT("PF reset polling failed to complete.\n");
1368 return I40E_ERR_RESET_FAILED;
1372 i40e_clear_pxe_mode(hw);
1375 return I40E_SUCCESS;
1379 * i40e_clear_hw - clear out any left over hw state
1380 * @hw: pointer to the hw struct
1382 * Clear queues and interrupts, typically called at init time,
1383 * but after the capabilities have been found so we know how many
1384 * queues and msix vectors have been allocated.
1386 void i40e_clear_hw(struct i40e_hw *hw)
1388 u32 num_queues, base_queue;
1396 /* get number of interrupts, queues, and vfs */
1397 val = rd32(hw, I40E_GLPCI_CNF2);
1398 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1403 val = rd32(hw, I40E_PFLAN_QALLOC);
1404 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409 num_queues = (j - base_queue) + 1;
1413 val = rd32(hw, I40E_PF_VT_PFALLOC);
1414 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419 num_vfs = (j - i) + 1;
1423 /* stop all the interrupts */
1424 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426 for (i = 0; i < num_pf_int - 2; i++)
1427 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1429 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431 wr32(hw, I40E_PFINT_LNKLST0, val);
1432 for (i = 0; i < num_pf_int - 2; i++)
1433 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435 for (i = 0; i < num_vfs; i++)
1436 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437 for (i = 0; i < num_vf_int - 2; i++)
1438 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1440 /* warn the HW of the coming Tx disables */
1441 for (i = 0; i < num_queues; i++) {
1442 u32 abs_queue_idx = base_queue + i;
1445 if (abs_queue_idx >= 128) {
1446 reg_block = abs_queue_idx / 128;
1447 abs_queue_idx %= 128;
1450 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1455 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1457 i40e_usec_delay(400);
1459 /* stop all the queues */
1460 for (i = 0; i < num_queues; i++) {
1461 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462 wr32(hw, I40E_QTX_ENA(i), 0);
1463 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464 wr32(hw, I40E_QRX_ENA(i), 0);
1467 /* short wait for all queue disables to settle */
1468 i40e_usec_delay(50);
1472 * i40e_clear_pxe_mode - clear pxe operations mode
1473 * @hw: pointer to the hw struct
1475 * Make sure all PXE mode settings are cleared, including things
1476 * like descriptor fetch/write-back mode.
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1480 if (i40e_check_asq_alive(hw))
1481 i40e_aq_clear_pxe_mode(hw, NULL);
1485 * i40e_led_is_mine - helper to find matching led
1486 * @hw: pointer to the hw struct
1487 * @idx: index into GPIO registers
1489 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1496 if (!hw->func_caps.led[idx])
1499 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1503 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504 * if it is not our port then ignore
1506 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1520 * i40e_led_get - return current on/off mode
1521 * @hw: pointer to the hw struct
1523 * The value returned is the 'mode' field as defined in the
1524 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525 * values are variations of possible behaviors relating to
1526 * blink, link, and wire.
1528 u32 i40e_led_get(struct i40e_hw *hw)
1530 u32 current_mode = 0;
1534 /* as per the documentation GPIO 22-29 are the LED
1535 * GPIO pins named LED0..LED7
1537 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538 u32 gpio_val = i40e_led_is_mine(hw, i);
1543 /* ignore gpio LED src mode entries related to the activity LEDs */
1544 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546 switch (current_mode) {
1547 case I40E_COMBINED_ACTIVITY:
1548 case I40E_FILTER_ACTIVITY:
1549 case I40E_MAC_ACTIVITY:
1555 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1564 * i40e_led_set - set new on/off mode
1565 * @hw: pointer to the hw struct
1566 * @mode: 0=off, 0xf=on (else see manual for mode details)
1567 * @blink: true if the LED should blink when on, false if steady
1569 * if this function is used to turn on the blink it should
1570 * be used to disable the blink when restoring the original state.
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1574 u32 current_mode = 0;
1577 if (mode & 0xfffffff0)
1578 DEBUGOUT1("invalid mode passed in %X\n", mode);
1580 /* as per the documentation GPIO 22-29 are the LED
1581 * GPIO pins named LED0..LED7
1583 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584 u32 gpio_val = i40e_led_is_mine(hw, i);
1589 /* ignore gpio LED src mode entries related to the activity LEDs */
1590 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592 switch (current_mode) {
1593 case I40E_COMBINED_ACTIVITY:
1594 case I40E_FILTER_ACTIVITY:
1595 case I40E_MAC_ACTIVITY:
1601 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602 /* this & is a bit of paranoia, but serves as a range check */
1603 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1606 if (mode == I40E_LINK_ACTIVITY)
1610 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1612 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1614 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1619 /* Admin command wrappers */
1622 * i40e_aq_get_phy_capabilities
1623 * @hw: pointer to the hw struct
1624 * @abilities: structure for PHY capabilities to be filled
1625 * @qualified_modules: report Qualified Modules
1626 * @report_init: report init capabilities (active are default)
1627 * @cmd_details: pointer to command details structure or NULL
1629 * Returns the various PHY abilities supported on the Port.
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632 bool qualified_modules, bool report_init,
1633 struct i40e_aq_get_phy_abilities_resp *abilities,
1634 struct i40e_asq_cmd_details *cmd_details)
1636 struct i40e_aq_desc desc;
1637 enum i40e_status_code status;
1638 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1641 return I40E_ERR_PARAM;
1643 i40e_fill_default_direct_cmd_desc(&desc,
1644 i40e_aqc_opc_get_phy_abilities);
1646 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647 if (abilities_size > I40E_AQ_LARGE_BUF)
1648 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1650 if (qualified_modules)
1651 desc.params.external.param0 |=
1652 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1655 desc.params.external.param0 |=
1656 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1658 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1661 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662 status = I40E_ERR_UNKNOWN_PHY;
1665 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1671 * i40e_aq_set_phy_config
1672 * @hw: pointer to the hw struct
1673 * @config: structure with PHY configuration to be set
1674 * @cmd_details: pointer to command details structure or NULL
1676 * Set the various PHY configuration parameters
1677 * supported on the Port.One or more of the Set PHY config parameters may be
1678 * ignored in an MFP mode as the PF may not have the privilege to set some
1679 * of the PHY Config parameters. This status will be indicated by the
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683 struct i40e_aq_set_phy_config *config,
1684 struct i40e_asq_cmd_details *cmd_details)
1686 struct i40e_aq_desc desc;
1687 struct i40e_aq_set_phy_config *cmd =
1688 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689 enum i40e_status_code status;
1692 return I40E_ERR_PARAM;
1694 i40e_fill_default_direct_cmd_desc(&desc,
1695 i40e_aqc_opc_set_phy_config);
1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1706 * @hw: pointer to the hw struct
1708 * Set the requested flow control mode using set_phy_config.
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711 bool atomic_restart)
1713 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714 struct i40e_aq_get_phy_abilities_resp abilities;
1715 struct i40e_aq_set_phy_config config;
1716 enum i40e_status_code status;
1717 u8 pause_mask = 0x0;
1723 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1726 case I40E_FC_RX_PAUSE:
1727 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1729 case I40E_FC_TX_PAUSE:
1730 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1736 /* Get the current phy config */
1737 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1740 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1744 memset(&config, 0, sizeof(config));
1745 /* clear the old pause settings */
1746 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748 /* set the new abilities */
1749 config.abilities |= pause_mask;
1750 /* If the abilities have changed, then set the new config */
1751 if (config.abilities != abilities.abilities) {
1752 /* Auto restart link so settings take effect */
1754 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755 /* Copy over all the old settings */
1756 config.phy_type = abilities.phy_type;
1757 config.link_speed = abilities.link_speed;
1758 config.eee_capability = abilities.eee_capability;
1759 config.eeer = abilities.eeer_val;
1760 config.low_power_ctrl = abilities.d3_lpan;
1761 status = i40e_aq_set_phy_config(hw, &config, NULL);
1764 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1766 /* Update the link info */
1767 status = i40e_update_link_info(hw);
1769 /* Wait a little bit (on 40G cards it sometimes takes a really
1770 * long time for link to come back from the atomic reset)
1773 i40e_msec_delay(1000);
1774 status = i40e_update_link_info(hw);
1777 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1783 * i40e_aq_set_mac_config
1784 * @hw: pointer to the hw struct
1785 * @max_frame_size: Maximum Frame Size to be supported by the port
1786 * @crc_en: Tell HW to append a CRC to outgoing frames
1787 * @pacing: Pacing configurations
1788 * @cmd_details: pointer to command details structure or NULL
1790 * Configure MAC settings for frame size, jumbo frame support and the
1791 * addition of a CRC by the hardware.
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1795 bool crc_en, u16 pacing,
1796 struct i40e_asq_cmd_details *cmd_details)
1798 struct i40e_aq_desc desc;
1799 struct i40e_aq_set_mac_config *cmd =
1800 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801 enum i40e_status_code status;
1803 if (max_frame_size == 0)
1804 return I40E_ERR_PARAM;
1806 i40e_fill_default_direct_cmd_desc(&desc,
1807 i40e_aqc_opc_set_mac_config);
1809 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810 cmd->params = ((u8)pacing & 0x0F) << 3;
1812 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1820 * i40e_aq_clear_pxe_mode
1821 * @hw: pointer to the hw struct
1822 * @cmd_details: pointer to command details structure or NULL
1824 * Tell the firmware that the driver is taking over from PXE
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827 struct i40e_asq_cmd_details *cmd_details)
1829 enum i40e_status_code status;
1830 struct i40e_aq_desc desc;
1831 struct i40e_aqc_clear_pxe *cmd =
1832 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1834 i40e_fill_default_direct_cmd_desc(&desc,
1835 i40e_aqc_opc_clear_pxe_mode);
1839 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1841 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1847 * i40e_aq_set_link_restart_an
1848 * @hw: pointer to the hw struct
1849 * @enable_link: if true: enable link, if false: disable link
1850 * @cmd_details: pointer to command details structure or NULL
1852 * Sets up the link and restarts the Auto-Negotiation over the link.
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1857 struct i40e_aq_desc desc;
1858 struct i40e_aqc_set_link_restart_an *cmd =
1859 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860 enum i40e_status_code status;
1862 i40e_fill_default_direct_cmd_desc(&desc,
1863 i40e_aqc_opc_set_link_restart_an);
1865 cmd->command = I40E_AQ_PHY_RESTART_AN;
1867 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1869 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1877 * i40e_aq_get_link_info
1878 * @hw: pointer to the hw struct
1879 * @enable_lse: enable/disable LinkStatusEvent reporting
1880 * @link: pointer to link status structure - optional
1881 * @cmd_details: pointer to command details structure or NULL
1883 * Returns the link status of the adapter.
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886 bool enable_lse, struct i40e_link_status *link,
1887 struct i40e_asq_cmd_details *cmd_details)
1889 struct i40e_aq_desc desc;
1890 struct i40e_aqc_get_link_status *resp =
1891 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893 enum i40e_status_code status;
1894 bool tx_pause, rx_pause;
1897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1900 command_flags = I40E_AQ_LSE_ENABLE;
1902 command_flags = I40E_AQ_LSE_DISABLE;
1903 resp->command_flags = CPU_TO_LE16(command_flags);
1905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907 if (status != I40E_SUCCESS)
1908 goto aq_get_link_info_exit;
1910 /* save off old link status information */
1911 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1914 /* update link status */
1915 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916 hw->phy.media_type = i40e_get_media_type(hw);
1917 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918 hw_link_info->link_info = resp->link_info;
1919 hw_link_info->an_info = resp->an_info;
1920 hw_link_info->ext_info = resp->ext_info;
1921 hw_link_info->loopback = resp->loopback;
1922 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1925 /* update fc info */
1926 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928 if (tx_pause & rx_pause)
1929 hw->fc.current_mode = I40E_FC_FULL;
1931 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1933 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1935 hw->fc.current_mode = I40E_FC_NONE;
1937 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938 hw_link_info->crc_enable = true;
1940 hw_link_info->crc_enable = false;
1942 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943 hw_link_info->lse_enable = true;
1945 hw_link_info->lse_enable = false;
1947 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1951 /* save link status information */
1953 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954 I40E_NONDMA_TO_NONDMA);
1956 /* flag cleared so helper functions don't call AQ again */
1957 hw->phy.get_link_info = false;
1959 aq_get_link_info_exit:
1964 * i40e_aq_set_phy_int_mask
1965 * @hw: pointer to the hw struct
1966 * @mask: interrupt mask to be set
1967 * @cmd_details: pointer to command details structure or NULL
1969 * Set link interrupt mask.
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1973 struct i40e_asq_cmd_details *cmd_details)
1975 struct i40e_aq_desc desc;
1976 struct i40e_aqc_set_phy_int_mask *cmd =
1977 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978 enum i40e_status_code status;
1980 i40e_fill_default_direct_cmd_desc(&desc,
1981 i40e_aqc_opc_set_phy_int_mask);
1983 cmd->event_mask = CPU_TO_LE16(mask);
1985 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1991 * i40e_aq_get_local_advt_reg
1992 * @hw: pointer to the hw struct
1993 * @advt_reg: local AN advertisement register value
1994 * @cmd_details: pointer to command details structure or NULL
1996 * Get the Local AN advertisement register value.
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2000 struct i40e_asq_cmd_details *cmd_details)
2002 struct i40e_aq_desc desc;
2003 struct i40e_aqc_an_advt_reg *resp =
2004 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005 enum i40e_status_code status;
2007 i40e_fill_default_direct_cmd_desc(&desc,
2008 i40e_aqc_opc_get_local_advt_reg);
2010 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2012 if (status != I40E_SUCCESS)
2013 goto aq_get_local_advt_reg_exit;
2015 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2018 aq_get_local_advt_reg_exit:
2023 * i40e_aq_set_local_advt_reg
2024 * @hw: pointer to the hw struct
2025 * @advt_reg: local AN advertisement register value
2026 * @cmd_details: pointer to command details structure or NULL
2028 * Get the Local AN advertisement register value.
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2032 struct i40e_asq_cmd_details *cmd_details)
2034 struct i40e_aq_desc desc;
2035 struct i40e_aqc_an_advt_reg *cmd =
2036 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037 enum i40e_status_code status;
2039 i40e_fill_default_direct_cmd_desc(&desc,
2040 i40e_aqc_opc_get_local_advt_reg);
2042 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2051 * i40e_aq_get_partner_advt
2052 * @hw: pointer to the hw struct
2053 * @advt_reg: AN partner advertisement register value
2054 * @cmd_details: pointer to command details structure or NULL
2056 * Get the link partner AN advertisement register value.
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2060 struct i40e_asq_cmd_details *cmd_details)
2062 struct i40e_aq_desc desc;
2063 struct i40e_aqc_an_advt_reg *resp =
2064 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065 enum i40e_status_code status;
2067 i40e_fill_default_direct_cmd_desc(&desc,
2068 i40e_aqc_opc_get_partner_advt);
2070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2072 if (status != I40E_SUCCESS)
2073 goto aq_get_partner_advt_exit;
2075 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2078 aq_get_partner_advt_exit:
2083 * i40e_aq_set_lb_modes
2084 * @hw: pointer to the hw struct
2085 * @lb_modes: loopback mode to be set
2086 * @cmd_details: pointer to command details structure or NULL
2088 * Sets loopback modes.
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2092 struct i40e_asq_cmd_details *cmd_details)
2094 struct i40e_aq_desc desc;
2095 struct i40e_aqc_set_lb_mode *cmd =
2096 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097 enum i40e_status_code status;
2099 i40e_fill_default_direct_cmd_desc(&desc,
2100 i40e_aqc_opc_set_lb_modes);
2102 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2110 * i40e_aq_set_phy_debug
2111 * @hw: pointer to the hw struct
2112 * @cmd_flags: debug command flags
2113 * @cmd_details: pointer to command details structure or NULL
2115 * Reset the external PHY.
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118 struct i40e_asq_cmd_details *cmd_details)
2120 struct i40e_aq_desc desc;
2121 struct i40e_aqc_set_phy_debug *cmd =
2122 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123 enum i40e_status_code status;
2125 i40e_fill_default_direct_cmd_desc(&desc,
2126 i40e_aqc_opc_set_phy_debug);
2128 cmd->command_flags = cmd_flags;
2130 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2137 * @hw: pointer to the hw struct
2138 * @vsi_ctx: pointer to a vsi context struct
2139 * @cmd_details: pointer to command details structure or NULL
2141 * Add a VSI context to the hardware.
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144 struct i40e_vsi_context *vsi_ctx,
2145 struct i40e_asq_cmd_details *cmd_details)
2147 struct i40e_aq_desc desc;
2148 struct i40e_aqc_add_get_update_vsi *cmd =
2149 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150 struct i40e_aqc_add_get_update_vsi_completion *resp =
2151 (struct i40e_aqc_add_get_update_vsi_completion *)
2153 enum i40e_status_code status;
2155 i40e_fill_default_direct_cmd_desc(&desc,
2156 i40e_aqc_opc_add_vsi);
2158 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159 cmd->connection_type = vsi_ctx->connection_type;
2160 cmd->vf_id = vsi_ctx->vf_num;
2161 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2163 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2165 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166 sizeof(vsi_ctx->info), cmd_details);
2168 if (status != I40E_SUCCESS)
2169 goto aq_add_vsi_exit;
2171 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2181 * i40e_aq_set_default_vsi
2182 * @hw: pointer to the hw struct
2184 * @cmd_details: pointer to command details structure or NULL
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2188 struct i40e_asq_cmd_details *cmd_details)
2190 struct i40e_aq_desc desc;
2191 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2194 enum i40e_status_code status;
2196 i40e_fill_default_direct_cmd_desc(&desc,
2197 i40e_aqc_opc_set_vsi_promiscuous_modes);
2199 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201 cmd->seid = CPU_TO_LE16(seid);
2203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209 * i40e_aq_set_vsi_unicast_promiscuous
2210 * @hw: pointer to the hw struct
2212 * @set: set unicast promiscuous enable/disable
2213 * @cmd_details: pointer to command details structure or NULL
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2217 struct i40e_asq_cmd_details *cmd_details)
2219 struct i40e_aq_desc desc;
2220 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222 enum i40e_status_code status;
2225 i40e_fill_default_direct_cmd_desc(&desc,
2226 i40e_aqc_opc_set_vsi_promiscuous_modes);
2229 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2231 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2233 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2235 cmd->seid = CPU_TO_LE16(seid);
2236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2242 * i40e_aq_set_vsi_multicast_promiscuous
2243 * @hw: pointer to the hw struct
2245 * @set: set multicast promiscuous enable/disable
2246 * @cmd_details: pointer to command details structure or NULL
2248 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2249 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2251 struct i40e_aq_desc desc;
2252 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2253 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2254 enum i40e_status_code status;
2257 i40e_fill_default_direct_cmd_desc(&desc,
2258 i40e_aqc_opc_set_vsi_promiscuous_modes);
2261 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2263 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2265 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2267 cmd->seid = CPU_TO_LE16(seid);
2268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2274 * i40e_aq_set_vsi_mc_promisc_on_vlan
2275 * @hw: pointer to the hw struct
2277 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2278 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2279 * @cmd_details: pointer to command details structure or NULL
2281 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2282 u16 seid, bool enable, u16 vid,
2283 struct i40e_asq_cmd_details *cmd_details)
2285 struct i40e_aq_desc desc;
2286 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288 enum i40e_status_code status;
2291 i40e_fill_default_direct_cmd_desc(&desc,
2292 i40e_aqc_opc_set_vsi_promiscuous_modes);
2295 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2297 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2298 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2299 cmd->seid = CPU_TO_LE16(seid);
2300 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2302 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2308 * i40e_aq_set_vsi_uc_promisc_on_vlan
2309 * @hw: pointer to the hw struct
2311 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2312 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2313 * @cmd_details: pointer to command details structure or NULL
2315 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2316 u16 seid, bool enable, u16 vid,
2317 struct i40e_asq_cmd_details *cmd_details)
2319 struct i40e_aq_desc desc;
2320 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2321 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2322 enum i40e_status_code status;
2325 i40e_fill_default_direct_cmd_desc(&desc,
2326 i40e_aqc_opc_set_vsi_promiscuous_modes);
2329 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2331 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2332 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2333 cmd->seid = CPU_TO_LE16(seid);
2334 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2336 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342 * i40e_aq_set_vsi_broadcast
2343 * @hw: pointer to the hw struct
2345 * @set_filter: true to set filter, false to clear filter
2346 * @cmd_details: pointer to command details structure or NULL
2348 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2350 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2351 u16 seid, bool set_filter,
2352 struct i40e_asq_cmd_details *cmd_details)
2354 struct i40e_aq_desc desc;
2355 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357 enum i40e_status_code status;
2359 i40e_fill_default_direct_cmd_desc(&desc,
2360 i40e_aqc_opc_set_vsi_promiscuous_modes);
2363 cmd->promiscuous_flags
2364 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2366 cmd->promiscuous_flags
2367 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2369 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2370 cmd->seid = CPU_TO_LE16(seid);
2371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2377 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2378 * @hw: pointer to the hw struct
2380 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2381 * @cmd_details: pointer to command details structure or NULL
2383 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2384 u16 seid, bool enable,
2385 struct i40e_asq_cmd_details *cmd_details)
2387 struct i40e_aq_desc desc;
2388 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2389 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2390 enum i40e_status_code status;
2393 i40e_fill_default_direct_cmd_desc(&desc,
2394 i40e_aqc_opc_set_vsi_promiscuous_modes);
2396 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2398 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2399 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2400 cmd->seid = CPU_TO_LE16(seid);
2402 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2408 * i40e_get_vsi_params - get VSI configuration info
2409 * @hw: pointer to the hw struct
2410 * @vsi_ctx: pointer to a vsi context struct
2411 * @cmd_details: pointer to command details structure or NULL
2413 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2414 struct i40e_vsi_context *vsi_ctx,
2415 struct i40e_asq_cmd_details *cmd_details)
2417 struct i40e_aq_desc desc;
2418 struct i40e_aqc_add_get_update_vsi *cmd =
2419 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2420 struct i40e_aqc_add_get_update_vsi_completion *resp =
2421 (struct i40e_aqc_add_get_update_vsi_completion *)
2423 enum i40e_status_code status;
2425 UNREFERENCED_1PARAMETER(cmd_details);
2426 i40e_fill_default_direct_cmd_desc(&desc,
2427 i40e_aqc_opc_get_vsi_parameters);
2429 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2431 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2433 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2434 sizeof(vsi_ctx->info), NULL);
2436 if (status != I40E_SUCCESS)
2437 goto aq_get_vsi_params_exit;
2439 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2440 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2441 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2442 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2444 aq_get_vsi_params_exit:
2449 * i40e_aq_update_vsi_params
2450 * @hw: pointer to the hw struct
2451 * @vsi_ctx: pointer to a vsi context struct
2452 * @cmd_details: pointer to command details structure or NULL
2454 * Update a VSI context.
2456 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2457 struct i40e_vsi_context *vsi_ctx,
2458 struct i40e_asq_cmd_details *cmd_details)
2460 struct i40e_aq_desc desc;
2461 struct i40e_aqc_add_get_update_vsi *cmd =
2462 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2463 enum i40e_status_code status;
2465 i40e_fill_default_direct_cmd_desc(&desc,
2466 i40e_aqc_opc_update_vsi_parameters);
2467 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2469 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2471 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2472 sizeof(vsi_ctx->info), cmd_details);
2478 * i40e_aq_get_switch_config
2479 * @hw: pointer to the hardware structure
2480 * @buf: pointer to the result buffer
2481 * @buf_size: length of input buffer
2482 * @start_seid: seid to start for the report, 0 == beginning
2483 * @cmd_details: pointer to command details structure or NULL
2485 * Fill the buf with switch configuration returned from AdminQ command
2487 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2488 struct i40e_aqc_get_switch_config_resp *buf,
2489 u16 buf_size, u16 *start_seid,
2490 struct i40e_asq_cmd_details *cmd_details)
2492 struct i40e_aq_desc desc;
2493 struct i40e_aqc_switch_seid *scfg =
2494 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2495 enum i40e_status_code status;
2497 i40e_fill_default_direct_cmd_desc(&desc,
2498 i40e_aqc_opc_get_switch_config);
2499 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2500 if (buf_size > I40E_AQ_LARGE_BUF)
2501 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2502 scfg->seid = CPU_TO_LE16(*start_seid);
2504 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2505 *start_seid = LE16_TO_CPU(scfg->seid);
2511 * i40e_aq_set_switch_config
2512 * @hw: pointer to the hardware structure
2513 * @flags: bit flag values to set
2514 * @valid_flags: which bit flags to set
2515 * @cmd_details: pointer to command details structure or NULL
2517 * Set switch configuration bits
2519 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2520 u16 flags, u16 valid_flags,
2521 struct i40e_asq_cmd_details *cmd_details)
2523 struct i40e_aq_desc desc;
2524 struct i40e_aqc_set_switch_config *scfg =
2525 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2526 enum i40e_status_code status;
2528 i40e_fill_default_direct_cmd_desc(&desc,
2529 i40e_aqc_opc_set_switch_config);
2530 scfg->flags = CPU_TO_LE16(flags);
2531 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2533 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2539 * i40e_aq_get_firmware_version
2540 * @hw: pointer to the hw struct
2541 * @fw_major_version: firmware major version
2542 * @fw_minor_version: firmware minor version
2543 * @fw_build: firmware build number
2544 * @api_major_version: major queue version
2545 * @api_minor_version: minor queue version
2546 * @cmd_details: pointer to command details structure or NULL
2548 * Get the firmware version from the admin queue commands
2550 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2551 u16 *fw_major_version, u16 *fw_minor_version,
2553 u16 *api_major_version, u16 *api_minor_version,
2554 struct i40e_asq_cmd_details *cmd_details)
2556 struct i40e_aq_desc desc;
2557 struct i40e_aqc_get_version *resp =
2558 (struct i40e_aqc_get_version *)&desc.params.raw;
2559 enum i40e_status_code status;
2561 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2565 if (status == I40E_SUCCESS) {
2566 if (fw_major_version != NULL)
2567 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2568 if (fw_minor_version != NULL)
2569 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2570 if (fw_build != NULL)
2571 *fw_build = LE32_TO_CPU(resp->fw_build);
2572 if (api_major_version != NULL)
2573 *api_major_version = LE16_TO_CPU(resp->api_major);
2574 if (api_minor_version != NULL)
2575 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2577 /* A workaround to fix the API version in SW */
2578 if (api_major_version && api_minor_version &&
2579 fw_major_version && fw_minor_version &&
2580 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2581 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2582 (*fw_major_version > 4)))
2583 *api_minor_version = 2;
2590 * i40e_aq_send_driver_version
2591 * @hw: pointer to the hw struct
2592 * @dv: driver's major, minor version
2593 * @cmd_details: pointer to command details structure or NULL
2595 * Send the driver version to the firmware
2597 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2598 struct i40e_driver_version *dv,
2599 struct i40e_asq_cmd_details *cmd_details)
2601 struct i40e_aq_desc desc;
2602 struct i40e_aqc_driver_version *cmd =
2603 (struct i40e_aqc_driver_version *)&desc.params.raw;
2604 enum i40e_status_code status;
2608 return I40E_ERR_PARAM;
2610 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2612 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2613 cmd->driver_major_ver = dv->major_version;
2614 cmd->driver_minor_ver = dv->minor_version;
2615 cmd->driver_build_ver = dv->build_version;
2616 cmd->driver_subbuild_ver = dv->subbuild_version;
2619 while (len < sizeof(dv->driver_string) &&
2620 (dv->driver_string[len] < 0x80) &&
2621 dv->driver_string[len])
2623 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2630 * i40e_get_link_status - get status of the HW network link
2631 * @hw: pointer to the hw struct
2632 * @link_up: pointer to bool (true/false = linkup/linkdown)
2634 * Variable link_up true if link is up, false if link is down.
2635 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2637 * Side effect: LinkStatusEvent reporting becomes enabled
2639 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2641 enum i40e_status_code status = I40E_SUCCESS;
2643 if (hw->phy.get_link_info) {
2644 status = i40e_update_link_info(hw);
2646 if (status != I40E_SUCCESS)
2647 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2651 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2657 * i40e_updatelink_status - update status of the HW network link
2658 * @hw: pointer to the hw struct
2660 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2662 struct i40e_aq_get_phy_abilities_resp abilities;
2663 enum i40e_status_code status = I40E_SUCCESS;
2665 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2669 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2670 status = i40e_aq_get_phy_capabilities(hw, false, false,
2675 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2676 sizeof(hw->phy.link_info.module_type));
2683 * i40e_get_link_speed
2684 * @hw: pointer to the hw struct
2686 * Returns the link speed of the adapter.
2688 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2690 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2691 enum i40e_status_code status = I40E_SUCCESS;
2693 if (hw->phy.get_link_info) {
2694 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2696 if (status != I40E_SUCCESS)
2697 goto i40e_link_speed_exit;
2700 speed = hw->phy.link_info.link_speed;
2702 i40e_link_speed_exit:
2707 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2708 * @hw: pointer to the hw struct
2709 * @uplink_seid: the MAC or other gizmo SEID
2710 * @downlink_seid: the VSI SEID
2711 * @enabled_tc: bitmap of TCs to be enabled
2712 * @default_port: true for default port VSI, false for control port
2713 * @veb_seid: pointer to where to put the resulting VEB SEID
2714 * @enable_stats: true to turn on VEB stats
2715 * @cmd_details: pointer to command details structure or NULL
2717 * This asks the FW to add a VEB between the uplink and downlink
2718 * elements. If the uplink SEID is 0, this will be a floating VEB.
2720 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2721 u16 downlink_seid, u8 enabled_tc,
2722 bool default_port, u16 *veb_seid,
2724 struct i40e_asq_cmd_details *cmd_details)
2726 struct i40e_aq_desc desc;
2727 struct i40e_aqc_add_veb *cmd =
2728 (struct i40e_aqc_add_veb *)&desc.params.raw;
2729 struct i40e_aqc_add_veb_completion *resp =
2730 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2731 enum i40e_status_code status;
2734 /* SEIDs need to either both be set or both be 0 for floating VEB */
2735 if (!!uplink_seid != !!downlink_seid)
2736 return I40E_ERR_PARAM;
2738 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2740 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2741 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2742 cmd->enable_tcs = enabled_tc;
2744 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2746 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2748 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2750 /* reverse logic here: set the bitflag to disable the stats */
2752 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2754 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2756 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2758 if (!status && veb_seid)
2759 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2765 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2766 * @hw: pointer to the hw struct
2767 * @veb_seid: the SEID of the VEB to query
2768 * @switch_id: the uplink switch id
2769 * @floating: set to true if the VEB is floating
2770 * @statistic_index: index of the stats counter block for this VEB
2771 * @vebs_used: number of VEB's used by function
2772 * @vebs_free: total VEB's not reserved by any function
2773 * @cmd_details: pointer to command details structure or NULL
2775 * This retrieves the parameters for a particular VEB, specified by
2776 * uplink_seid, and returns them to the caller.
2778 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2779 u16 veb_seid, u16 *switch_id,
2780 bool *floating, u16 *statistic_index,
2781 u16 *vebs_used, u16 *vebs_free,
2782 struct i40e_asq_cmd_details *cmd_details)
2784 struct i40e_aq_desc desc;
2785 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2786 (struct i40e_aqc_get_veb_parameters_completion *)
2788 enum i40e_status_code status;
2791 return I40E_ERR_PARAM;
2793 i40e_fill_default_direct_cmd_desc(&desc,
2794 i40e_aqc_opc_get_veb_parameters);
2795 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2797 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2802 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2803 if (statistic_index)
2804 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2806 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2808 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2810 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2811 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2822 * i40e_aq_add_macvlan
2823 * @hw: pointer to the hw struct
2824 * @seid: VSI for the mac address
2825 * @mv_list: list of macvlans to be added
2826 * @count: length of the list
2827 * @cmd_details: pointer to command details structure or NULL
2829 * Add MAC/VLAN addresses to the HW filtering
2831 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2832 struct i40e_aqc_add_macvlan_element_data *mv_list,
2833 u16 count, struct i40e_asq_cmd_details *cmd_details)
2835 struct i40e_aq_desc desc;
2836 struct i40e_aqc_macvlan *cmd =
2837 (struct i40e_aqc_macvlan *)&desc.params.raw;
2838 enum i40e_status_code status;
2842 if (count == 0 || !mv_list || !hw)
2843 return I40E_ERR_PARAM;
2845 buf_size = count * sizeof(*mv_list);
2847 /* prep the rest of the request */
2848 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2849 cmd->num_addresses = CPU_TO_LE16(count);
2850 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2854 for (i = 0; i < count; i++)
2855 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2857 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2859 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2860 if (buf_size > I40E_AQ_LARGE_BUF)
2861 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2863 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2870 * i40e_aq_remove_macvlan
2871 * @hw: pointer to the hw struct
2872 * @seid: VSI for the mac address
2873 * @mv_list: list of macvlans to be removed
2874 * @count: length of the list
2875 * @cmd_details: pointer to command details structure or NULL
2877 * Remove MAC/VLAN addresses from the HW filtering
2879 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2880 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2881 u16 count, struct i40e_asq_cmd_details *cmd_details)
2883 struct i40e_aq_desc desc;
2884 struct i40e_aqc_macvlan *cmd =
2885 (struct i40e_aqc_macvlan *)&desc.params.raw;
2886 enum i40e_status_code status;
2889 if (count == 0 || !mv_list || !hw)
2890 return I40E_ERR_PARAM;
2892 buf_size = count * sizeof(*mv_list);
2894 /* prep the rest of the request */
2895 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2896 cmd->num_addresses = CPU_TO_LE16(count);
2897 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2901 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2902 if (buf_size > I40E_AQ_LARGE_BUF)
2903 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2905 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2912 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2913 * @hw: pointer to the hw struct
2914 * @opcode: AQ opcode for add or delete mirror rule
2915 * @sw_seid: Switch SEID (to which rule refers)
2916 * @rule_type: Rule Type (ingress/egress/VLAN)
2917 * @id: Destination VSI SEID or Rule ID
2918 * @count: length of the list
2919 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2920 * @cmd_details: pointer to command details structure or NULL
2921 * @rule_id: Rule ID returned from FW
2922 * @rule_used: Number of rules used in internal switch
2923 * @rule_free: Number of rules free in internal switch
2925 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2926 * VEBs/VEPA elements only
2928 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2929 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2930 u16 count, __le16 *mr_list,
2931 struct i40e_asq_cmd_details *cmd_details,
2932 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2934 struct i40e_aq_desc desc;
2935 struct i40e_aqc_add_delete_mirror_rule *cmd =
2936 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2937 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2938 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2939 enum i40e_status_code status;
2942 buf_size = count * sizeof(*mr_list);
2944 /* prep the rest of the request */
2945 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2946 cmd->seid = CPU_TO_LE16(sw_seid);
2947 cmd->rule_type = CPU_TO_LE16(rule_type &
2948 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2949 cmd->num_entries = CPU_TO_LE16(count);
2950 /* Dest VSI for add, rule_id for delete */
2951 cmd->destination = CPU_TO_LE16(id);
2953 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2955 if (buf_size > I40E_AQ_LARGE_BUF)
2956 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2959 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2961 if (status == I40E_SUCCESS ||
2962 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2964 *rule_id = LE16_TO_CPU(resp->rule_id);
2966 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2968 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2974 * i40e_aq_add_mirrorrule - add a mirror rule
2975 * @hw: pointer to the hw struct
2976 * @sw_seid: Switch SEID (to which rule refers)
2977 * @rule_type: Rule Type (ingress/egress/VLAN)
2978 * @dest_vsi: SEID of VSI to which packets will be mirrored
2979 * @count: length of the list
2980 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2981 * @cmd_details: pointer to command details structure or NULL
2982 * @rule_id: Rule ID returned from FW
2983 * @rule_used: Number of rules used in internal switch
2984 * @rule_free: Number of rules free in internal switch
2986 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2988 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2989 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2990 struct i40e_asq_cmd_details *cmd_details,
2991 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2993 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2994 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2995 if (count == 0 || !mr_list)
2996 return I40E_ERR_PARAM;
2999 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3000 rule_type, dest_vsi, count, mr_list,
3001 cmd_details, rule_id, rules_used, rules_free);
3005 * i40e_aq_delete_mirrorrule - delete a mirror rule
3006 * @hw: pointer to the hw struct
3007 * @sw_seid: Switch SEID (to which rule refers)
3008 * @rule_type: Rule Type (ingress/egress/VLAN)
3009 * @count: length of the list
3010 * @rule_id: Rule ID that is returned in the receive desc as part of
3012 * @mr_list: list of mirrored VLAN IDs to be removed
3013 * @cmd_details: pointer to command details structure or NULL
3014 * @rule_used: Number of rules used in internal switch
3015 * @rule_free: Number of rules free in internal switch
3017 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3019 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3020 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3021 struct i40e_asq_cmd_details *cmd_details,
3022 u16 *rules_used, u16 *rules_free)
3024 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3025 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3027 return I40E_ERR_PARAM;
3029 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3030 * mirroring. For other rule_type, count and rule_type should
3033 if (count == 0 || !mr_list)
3034 return I40E_ERR_PARAM;
3037 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3038 rule_type, rule_id, count, mr_list,
3039 cmd_details, NULL, rules_used, rules_free);
3043 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3044 * @hw: pointer to the hw struct
3045 * @seid: VSI for the vlan filters
3046 * @v_list: list of vlan filters to be added
3047 * @count: length of the list
3048 * @cmd_details: pointer to command details structure or NULL
3050 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3051 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3052 u8 count, struct i40e_asq_cmd_details *cmd_details)
3054 struct i40e_aq_desc desc;
3055 struct i40e_aqc_macvlan *cmd =
3056 (struct i40e_aqc_macvlan *)&desc.params.raw;
3057 enum i40e_status_code status;
3060 if (count == 0 || !v_list || !hw)
3061 return I40E_ERR_PARAM;
3063 buf_size = count * sizeof(*v_list);
3065 /* prep the rest of the request */
3066 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3067 cmd->num_addresses = CPU_TO_LE16(count);
3068 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3072 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3073 if (buf_size > I40E_AQ_LARGE_BUF)
3074 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3076 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3083 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3084 * @hw: pointer to the hw struct
3085 * @seid: VSI for the vlan filters
3086 * @v_list: list of macvlans to be removed
3087 * @count: length of the list
3088 * @cmd_details: pointer to command details structure or NULL
3090 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3091 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3092 u8 count, struct i40e_asq_cmd_details *cmd_details)
3094 struct i40e_aq_desc desc;
3095 struct i40e_aqc_macvlan *cmd =
3096 (struct i40e_aqc_macvlan *)&desc.params.raw;
3097 enum i40e_status_code status;
3100 if (count == 0 || !v_list || !hw)
3101 return I40E_ERR_PARAM;
3103 buf_size = count * sizeof(*v_list);
3105 /* prep the rest of the request */
3106 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3107 cmd->num_addresses = CPU_TO_LE16(count);
3108 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3112 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3113 if (buf_size > I40E_AQ_LARGE_BUF)
3114 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3116 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3123 * i40e_aq_send_msg_to_vf
3124 * @hw: pointer to the hardware structure
3125 * @vfid: vf id to send msg
3126 * @v_opcode: opcodes for VF-PF communication
3127 * @v_retval: return error code
3128 * @msg: pointer to the msg buffer
3129 * @msglen: msg length
3130 * @cmd_details: pointer to command details
3134 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3135 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3136 struct i40e_asq_cmd_details *cmd_details)
3138 struct i40e_aq_desc desc;
3139 struct i40e_aqc_pf_vf_message *cmd =
3140 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3141 enum i40e_status_code status;
3143 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3144 cmd->id = CPU_TO_LE32(vfid);
3145 desc.cookie_high = CPU_TO_LE32(v_opcode);
3146 desc.cookie_low = CPU_TO_LE32(v_retval);
3147 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3149 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3151 if (msglen > I40E_AQ_LARGE_BUF)
3152 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3153 desc.datalen = CPU_TO_LE16(msglen);
3155 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3161 * i40e_aq_debug_read_register
3162 * @hw: pointer to the hw struct
3163 * @reg_addr: register address
3164 * @reg_val: register value
3165 * @cmd_details: pointer to command details structure or NULL
3167 * Read the register using the admin queue commands
3169 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3170 u32 reg_addr, u64 *reg_val,
3171 struct i40e_asq_cmd_details *cmd_details)
3173 struct i40e_aq_desc desc;
3174 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3175 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3176 enum i40e_status_code status;
3178 if (reg_val == NULL)
3179 return I40E_ERR_PARAM;
3181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3183 cmd_resp->address = CPU_TO_LE32(reg_addr);
3185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3187 if (status == I40E_SUCCESS) {
3188 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3189 (u64)LE32_TO_CPU(cmd_resp->value_low);
3196 * i40e_aq_debug_write_register
3197 * @hw: pointer to the hw struct
3198 * @reg_addr: register address
3199 * @reg_val: register value
3200 * @cmd_details: pointer to command details structure or NULL
3202 * Write to a register using the admin queue commands
3204 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3205 u32 reg_addr, u64 reg_val,
3206 struct i40e_asq_cmd_details *cmd_details)
3208 struct i40e_aq_desc desc;
3209 struct i40e_aqc_debug_reg_read_write *cmd =
3210 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3211 enum i40e_status_code status;
3213 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3215 cmd->address = CPU_TO_LE32(reg_addr);
3216 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3217 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3225 * i40e_aq_get_hmc_resource_profile
3226 * @hw: pointer to the hw struct
3227 * @profile: type of profile the HMC is to be set as
3228 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3229 * @cmd_details: pointer to command details structure or NULL
3231 * query the HMC profile of the device.
3233 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3234 enum i40e_aq_hmc_profile *profile,
3235 u8 *pe_vf_enabled_count,
3236 struct i40e_asq_cmd_details *cmd_details)
3238 struct i40e_aq_desc desc;
3239 struct i40e_aq_get_set_hmc_resource_profile *resp =
3240 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3241 enum i40e_status_code status;
3243 i40e_fill_default_direct_cmd_desc(&desc,
3244 i40e_aqc_opc_query_hmc_resource_profile);
3245 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3247 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3248 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3249 *pe_vf_enabled_count = resp->pe_vf_enabled &
3250 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3256 * i40e_aq_set_hmc_resource_profile
3257 * @hw: pointer to the hw struct
3258 * @profile: type of profile the HMC is to be set as
3259 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3260 * @cmd_details: pointer to command details structure or NULL
3262 * set the HMC profile of the device.
3264 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3265 enum i40e_aq_hmc_profile profile,
3266 u8 pe_vf_enabled_count,
3267 struct i40e_asq_cmd_details *cmd_details)
3269 struct i40e_aq_desc desc;
3270 struct i40e_aq_get_set_hmc_resource_profile *cmd =
3271 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3272 enum i40e_status_code status;
3274 i40e_fill_default_direct_cmd_desc(&desc,
3275 i40e_aqc_opc_set_hmc_resource_profile);
3277 cmd->pm_profile = (u8)profile;
3278 cmd->pe_vf_enabled = pe_vf_enabled_count;
3280 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3286 * i40e_aq_request_resource
3287 * @hw: pointer to the hw struct
3288 * @resource: resource id
3289 * @access: access type
3290 * @sdp_number: resource number
3291 * @timeout: the maximum time in ms that the driver may hold the resource
3292 * @cmd_details: pointer to command details structure or NULL
3294 * requests common resource using the admin queue commands
3296 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3297 enum i40e_aq_resources_ids resource,
3298 enum i40e_aq_resource_access_type access,
3299 u8 sdp_number, u64 *timeout,
3300 struct i40e_asq_cmd_details *cmd_details)
3302 struct i40e_aq_desc desc;
3303 struct i40e_aqc_request_resource *cmd_resp =
3304 (struct i40e_aqc_request_resource *)&desc.params.raw;
3305 enum i40e_status_code status;
3307 DEBUGFUNC("i40e_aq_request_resource");
3309 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3311 cmd_resp->resource_id = CPU_TO_LE16(resource);
3312 cmd_resp->access_type = CPU_TO_LE16(access);
3313 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3315 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3316 /* The completion specifies the maximum time in ms that the driver
3317 * may hold the resource in the Timeout field.
3318 * If the resource is held by someone else, the command completes with
3319 * busy return value and the timeout field indicates the maximum time
3320 * the current owner of the resource has to free it.
3322 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3323 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3329 * i40e_aq_release_resource
3330 * @hw: pointer to the hw struct
3331 * @resource: resource id
3332 * @sdp_number: resource number
3333 * @cmd_details: pointer to command details structure or NULL
3335 * release common resource using the admin queue commands
3337 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3338 enum i40e_aq_resources_ids resource,
3340 struct i40e_asq_cmd_details *cmd_details)
3342 struct i40e_aq_desc desc;
3343 struct i40e_aqc_request_resource *cmd =
3344 (struct i40e_aqc_request_resource *)&desc.params.raw;
3345 enum i40e_status_code status;
3347 DEBUGFUNC("i40e_aq_release_resource");
3349 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3351 cmd->resource_id = CPU_TO_LE16(resource);
3352 cmd->resource_number = CPU_TO_LE32(sdp_number);
3354 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3361 * @hw: pointer to the hw struct
3362 * @module_pointer: module pointer location in words from the NVM beginning
3363 * @offset: byte offset from the module beginning
3364 * @length: length of the section to be read (in bytes from the offset)
3365 * @data: command buffer (size [bytes] = length)
3366 * @last_command: tells if this is the last command in a series
3367 * @cmd_details: pointer to command details structure or NULL
3369 * Read the NVM using the admin queue commands
3371 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3372 u32 offset, u16 length, void *data,
3374 struct i40e_asq_cmd_details *cmd_details)
3376 struct i40e_aq_desc desc;
3377 struct i40e_aqc_nvm_update *cmd =
3378 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3379 enum i40e_status_code status;
3381 DEBUGFUNC("i40e_aq_read_nvm");
3383 /* In offset the highest byte must be zeroed. */
3384 if (offset & 0xFF000000) {
3385 status = I40E_ERR_PARAM;
3386 goto i40e_aq_read_nvm_exit;
3389 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3391 /* If this is the last command in a series, set the proper flag. */
3393 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3394 cmd->module_pointer = module_pointer;
3395 cmd->offset = CPU_TO_LE32(offset);
3396 cmd->length = CPU_TO_LE16(length);
3398 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3399 if (length > I40E_AQ_LARGE_BUF)
3400 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3402 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3404 i40e_aq_read_nvm_exit:
3409 * i40e_aq_read_nvm_config - read an nvm config block
3410 * @hw: pointer to the hw struct
3411 * @cmd_flags: NVM access admin command bits
3412 * @field_id: field or feature id
3413 * @data: buffer for result
3414 * @buf_size: buffer size
3415 * @element_count: pointer to count of elements read by FW
3416 * @cmd_details: pointer to command details structure or NULL
3418 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3419 u8 cmd_flags, u32 field_id, void *data,
3420 u16 buf_size, u16 *element_count,
3421 struct i40e_asq_cmd_details *cmd_details)
3423 struct i40e_aq_desc desc;
3424 struct i40e_aqc_nvm_config_read *cmd =
3425 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3426 enum i40e_status_code status;
3428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3429 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3430 if (buf_size > I40E_AQ_LARGE_BUF)
3431 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3433 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3434 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3435 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3436 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3438 cmd->element_id_msw = 0;
3440 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3442 if (!status && element_count)
3443 *element_count = LE16_TO_CPU(cmd->element_count);
3449 * i40e_aq_write_nvm_config - write an nvm config block
3450 * @hw: pointer to the hw struct
3451 * @cmd_flags: NVM access admin command bits
3452 * @data: buffer for result
3453 * @buf_size: buffer size
3454 * @element_count: count of elements to be written
3455 * @cmd_details: pointer to command details structure or NULL
3457 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3458 u8 cmd_flags, void *data, u16 buf_size,
3460 struct i40e_asq_cmd_details *cmd_details)
3462 struct i40e_aq_desc desc;
3463 struct i40e_aqc_nvm_config_write *cmd =
3464 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3465 enum i40e_status_code status;
3467 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3468 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3469 if (buf_size > I40E_AQ_LARGE_BUF)
3470 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3472 cmd->element_count = CPU_TO_LE16(element_count);
3473 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3474 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3480 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3481 * @hw: pointer to the hw struct
3482 * @cmd_details: pointer to command details structure or NULL
3484 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3485 void *buff, u16 buff_size,
3486 struct i40e_asq_cmd_details *cmd_details)
3488 struct i40e_aq_desc desc;
3489 enum i40e_status_code status;
3491 UNREFERENCED_2PARAMETER(buff, buff_size);
3493 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3494 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3495 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3496 status = I40E_ERR_NOT_IMPLEMENTED;
3503 * @hw: pointer to the hw struct
3504 * @module_pointer: module pointer location in words from the NVM beginning
3505 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3506 * @length: length of the section to be erased (expressed in 4 KB)
3507 * @last_command: tells if this is the last command in a series
3508 * @cmd_details: pointer to command details structure or NULL
3510 * Erase the NVM sector using the admin queue commands
3512 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3513 u32 offset, u16 length, bool last_command,
3514 struct i40e_asq_cmd_details *cmd_details)
3516 struct i40e_aq_desc desc;
3517 struct i40e_aqc_nvm_update *cmd =
3518 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3519 enum i40e_status_code status;
3521 DEBUGFUNC("i40e_aq_erase_nvm");
3523 /* In offset the highest byte must be zeroed. */
3524 if (offset & 0xFF000000) {
3525 status = I40E_ERR_PARAM;
3526 goto i40e_aq_erase_nvm_exit;
3529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3531 /* If this is the last command in a series, set the proper flag. */
3533 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3534 cmd->module_pointer = module_pointer;
3535 cmd->offset = CPU_TO_LE32(offset);
3536 cmd->length = CPU_TO_LE16(length);
3538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3540 i40e_aq_erase_nvm_exit:
3545 * i40e_parse_discover_capabilities
3546 * @hw: pointer to the hw struct
3547 * @buff: pointer to a buffer containing device/function capability records
3548 * @cap_count: number of capability records in the list
3549 * @list_type_opc: type of capabilities list to parse
3551 * Parse the device/function capabilities list.
3553 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3555 enum i40e_admin_queue_opc list_type_opc)
3557 struct i40e_aqc_list_capabilities_element_resp *cap;
3558 u32 valid_functions, num_functions;
3559 u32 number, logical_id, phys_id;
3560 struct i40e_hw_capabilities *p;
3565 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3567 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3568 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3569 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3570 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3574 for (i = 0; i < cap_count; i++, cap++) {
3575 id = LE16_TO_CPU(cap->id);
3576 number = LE32_TO_CPU(cap->number);
3577 logical_id = LE32_TO_CPU(cap->logical_id);
3578 phys_id = LE32_TO_CPU(cap->phys_id);
3579 major_rev = cap->major_rev;
3582 case I40E_AQ_CAP_ID_SWITCH_MODE:
3583 p->switch_mode = number;
3584 i40e_debug(hw, I40E_DEBUG_INIT,
3585 "HW Capability: Switch mode = %d\n",
3588 case I40E_AQ_CAP_ID_MNG_MODE:
3589 p->management_mode = number;
3590 i40e_debug(hw, I40E_DEBUG_INIT,
3591 "HW Capability: Management Mode = %d\n",
3592 p->management_mode);
3594 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3595 p->npar_enable = number;
3596 i40e_debug(hw, I40E_DEBUG_INIT,
3597 "HW Capability: NPAR enable = %d\n",
3600 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3602 i40e_debug(hw, I40E_DEBUG_INIT,
3603 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3605 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3606 p->valid_functions = number;
3607 i40e_debug(hw, I40E_DEBUG_INIT,
3608 "HW Capability: Valid Functions = %d\n",
3609 p->valid_functions);
3611 case I40E_AQ_CAP_ID_SRIOV:
3613 p->sr_iov_1_1 = true;
3614 i40e_debug(hw, I40E_DEBUG_INIT,
3615 "HW Capability: SR-IOV = %d\n",
3618 case I40E_AQ_CAP_ID_VF:
3619 p->num_vfs = number;
3620 p->vf_base_id = logical_id;
3621 i40e_debug(hw, I40E_DEBUG_INIT,
3622 "HW Capability: VF count = %d\n",
3624 i40e_debug(hw, I40E_DEBUG_INIT,
3625 "HW Capability: VF base_id = %d\n",
3628 case I40E_AQ_CAP_ID_VMDQ:
3631 i40e_debug(hw, I40E_DEBUG_INIT,
3632 "HW Capability: VMDQ = %d\n", p->vmdq);
3634 case I40E_AQ_CAP_ID_8021QBG:
3636 p->evb_802_1_qbg = true;
3637 i40e_debug(hw, I40E_DEBUG_INIT,
3638 "HW Capability: 802.1Qbg = %d\n", number);
3640 case I40E_AQ_CAP_ID_8021QBR:
3642 p->evb_802_1_qbh = true;
3643 i40e_debug(hw, I40E_DEBUG_INIT,
3644 "HW Capability: 802.1Qbh = %d\n", number);
3646 case I40E_AQ_CAP_ID_VSI:
3647 p->num_vsis = number;
3648 i40e_debug(hw, I40E_DEBUG_INIT,
3649 "HW Capability: VSI count = %d\n",
3652 case I40E_AQ_CAP_ID_DCB:
3655 p->enabled_tcmap = logical_id;
3658 i40e_debug(hw, I40E_DEBUG_INIT,
3659 "HW Capability: DCB = %d\n", p->dcb);
3660 i40e_debug(hw, I40E_DEBUG_INIT,
3661 "HW Capability: TC Mapping = %d\n",
3663 i40e_debug(hw, I40E_DEBUG_INIT,
3664 "HW Capability: TC Max = %d\n", p->maxtc);
3666 case I40E_AQ_CAP_ID_FCOE:
3669 i40e_debug(hw, I40E_DEBUG_INIT,
3670 "HW Capability: FCOE = %d\n", p->fcoe);
3672 case I40E_AQ_CAP_ID_ISCSI:
3675 i40e_debug(hw, I40E_DEBUG_INIT,
3676 "HW Capability: iSCSI = %d\n", p->iscsi);
3678 case I40E_AQ_CAP_ID_RSS:
3680 p->rss_table_size = number;
3681 p->rss_table_entry_width = logical_id;
3682 i40e_debug(hw, I40E_DEBUG_INIT,
3683 "HW Capability: RSS = %d\n", p->rss);
3684 i40e_debug(hw, I40E_DEBUG_INIT,
3685 "HW Capability: RSS table size = %d\n",
3687 i40e_debug(hw, I40E_DEBUG_INIT,
3688 "HW Capability: RSS table width = %d\n",
3689 p->rss_table_entry_width);
3691 case I40E_AQ_CAP_ID_RXQ:
3692 p->num_rx_qp = number;
3693 p->base_queue = phys_id;
3694 i40e_debug(hw, I40E_DEBUG_INIT,
3695 "HW Capability: Rx QP = %d\n", number);
3696 i40e_debug(hw, I40E_DEBUG_INIT,
3697 "HW Capability: base_queue = %d\n",
3700 case I40E_AQ_CAP_ID_TXQ:
3701 p->num_tx_qp = number;
3702 p->base_queue = phys_id;
3703 i40e_debug(hw, I40E_DEBUG_INIT,
3704 "HW Capability: Tx QP = %d\n", number);
3705 i40e_debug(hw, I40E_DEBUG_INIT,
3706 "HW Capability: base_queue = %d\n",
3709 case I40E_AQ_CAP_ID_MSIX:
3710 p->num_msix_vectors = number;
3711 i40e_debug(hw, I40E_DEBUG_INIT,
3712 "HW Capability: MSIX vector count = %d\n",
3713 p->num_msix_vectors_vf);
3715 case I40E_AQ_CAP_ID_VF_MSIX:
3716 p->num_msix_vectors_vf = number;
3717 i40e_debug(hw, I40E_DEBUG_INIT,
3718 "HW Capability: MSIX VF vector count = %d\n",
3719 p->num_msix_vectors_vf);
3721 case I40E_AQ_CAP_ID_FLEX10:
3722 if (major_rev == 1) {
3724 p->flex10_enable = true;
3725 p->flex10_capable = true;
3728 /* Capability revision >= 2 */
3730 p->flex10_enable = true;
3732 p->flex10_capable = true;
3734 p->flex10_mode = logical_id;
3735 p->flex10_status = phys_id;
3736 i40e_debug(hw, I40E_DEBUG_INIT,
3737 "HW Capability: Flex10 mode = %d\n",
3739 i40e_debug(hw, I40E_DEBUG_INIT,
3740 "HW Capability: Flex10 status = %d\n",
3743 case I40E_AQ_CAP_ID_CEM:
3746 i40e_debug(hw, I40E_DEBUG_INIT,
3747 "HW Capability: CEM = %d\n", p->mgmt_cem);
3749 case I40E_AQ_CAP_ID_IWARP:
3752 i40e_debug(hw, I40E_DEBUG_INIT,
3753 "HW Capability: iWARP = %d\n", p->iwarp);
3755 case I40E_AQ_CAP_ID_LED:
3756 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3757 p->led[phys_id] = true;
3758 i40e_debug(hw, I40E_DEBUG_INIT,
3759 "HW Capability: LED - PIN %d\n", phys_id);
3761 case I40E_AQ_CAP_ID_SDP:
3762 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3763 p->sdp[phys_id] = true;
3764 i40e_debug(hw, I40E_DEBUG_INIT,
3765 "HW Capability: SDP - PIN %d\n", phys_id);
3767 case I40E_AQ_CAP_ID_MDIO:
3769 p->mdio_port_num = phys_id;
3770 p->mdio_port_mode = logical_id;
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: MDIO port number = %d\n",
3775 i40e_debug(hw, I40E_DEBUG_INIT,
3776 "HW Capability: MDIO port mode = %d\n",
3779 case I40E_AQ_CAP_ID_1588:
3781 p->ieee_1588 = true;
3782 i40e_debug(hw, I40E_DEBUG_INIT,
3783 "HW Capability: IEEE 1588 = %d\n",
3786 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3788 p->fd_filters_guaranteed = number;
3789 p->fd_filters_best_effort = logical_id;
3790 i40e_debug(hw, I40E_DEBUG_INIT,
3791 "HW Capability: Flow Director = 1\n");
3792 i40e_debug(hw, I40E_DEBUG_INIT,
3793 "HW Capability: Guaranteed FD filters = %d\n",
3794 p->fd_filters_guaranteed);
3796 case I40E_AQ_CAP_ID_WSR_PROT:
3797 p->wr_csr_prot = (u64)number;
3798 p->wr_csr_prot |= (u64)logical_id << 32;
3799 i40e_debug(hw, I40E_DEBUG_INIT,
3800 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3801 (p->wr_csr_prot & 0xffff));
3804 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3805 hw->num_wol_proxy_filters = (u16)number;
3806 hw->wol_proxy_vsi_seid = (u16)logical_id;
3807 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3808 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3809 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3811 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3812 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3813 p->proxy_support = p->proxy_support;
3814 i40e_debug(hw, I40E_DEBUG_INIT,
3815 "HW Capability: WOL proxy filters = %d\n",
3816 hw->num_wol_proxy_filters);
3825 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3827 #ifdef I40E_FCOE_ENA
3828 /* Software override ensuring FCoE is disabled if npar or mfp
3829 * mode because it is not supported in these modes.
3831 if (p->npar_enable || p->flex10_enable)
3834 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3838 /* count the enabled ports (aka the "not disabled" ports) */
3840 for (i = 0; i < 4; i++) {
3841 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3844 /* use AQ read to get the physical register offset instead
3845 * of the port relative offset
3847 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3848 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3852 valid_functions = p->valid_functions;
3854 while (valid_functions) {
3855 if (valid_functions & 1)
3857 valid_functions >>= 1;
3860 /* partition id is 1-based, and functions are evenly spread
3861 * across the ports as partitions
3863 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3864 hw->num_partitions = num_functions / hw->num_ports;
3866 /* additional HW specific goodies that might
3867 * someday be HW version specific
3869 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3873 * i40e_aq_discover_capabilities
3874 * @hw: pointer to the hw struct
3875 * @buff: a virtual buffer to hold the capabilities
3876 * @buff_size: Size of the virtual buffer
3877 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3878 * @list_type_opc: capabilities type to discover - pass in the command opcode
3879 * @cmd_details: pointer to command details structure or NULL
3881 * Get the device capabilities descriptions from the firmware
3883 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3884 void *buff, u16 buff_size, u16 *data_size,
3885 enum i40e_admin_queue_opc list_type_opc,
3886 struct i40e_asq_cmd_details *cmd_details)
3888 struct i40e_aqc_list_capabilites *cmd;
3889 struct i40e_aq_desc desc;
3890 enum i40e_status_code status = I40E_SUCCESS;
3892 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3894 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3895 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3896 status = I40E_ERR_PARAM;
3900 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3902 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3903 if (buff_size > I40E_AQ_LARGE_BUF)
3904 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3906 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3907 *data_size = LE16_TO_CPU(desc.datalen);
3912 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3920 * i40e_aq_update_nvm
3921 * @hw: pointer to the hw struct
3922 * @module_pointer: module pointer location in words from the NVM beginning
3923 * @offset: byte offset from the module beginning
3924 * @length: length of the section to be written (in bytes from the offset)
3925 * @data: command buffer (size [bytes] = length)
3926 * @last_command: tells if this is the last command in a series
3927 * @cmd_details: pointer to command details structure or NULL
3929 * Update the NVM using the admin queue commands
3931 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3932 u32 offset, u16 length, void *data,
3934 struct i40e_asq_cmd_details *cmd_details)
3936 struct i40e_aq_desc desc;
3937 struct i40e_aqc_nvm_update *cmd =
3938 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3939 enum i40e_status_code status;
3941 DEBUGFUNC("i40e_aq_update_nvm");
3943 /* In offset the highest byte must be zeroed. */
3944 if (offset & 0xFF000000) {
3945 status = I40E_ERR_PARAM;
3946 goto i40e_aq_update_nvm_exit;
3949 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3951 /* If this is the last command in a series, set the proper flag. */
3953 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3954 cmd->module_pointer = module_pointer;
3955 cmd->offset = CPU_TO_LE32(offset);
3956 cmd->length = CPU_TO_LE16(length);
3958 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3959 if (length > I40E_AQ_LARGE_BUF)
3960 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3962 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3964 i40e_aq_update_nvm_exit:
3969 * i40e_aq_get_lldp_mib
3970 * @hw: pointer to the hw struct
3971 * @bridge_type: type of bridge requested
3972 * @mib_type: Local, Remote or both Local and Remote MIBs
3973 * @buff: pointer to a user supplied buffer to store the MIB block
3974 * @buff_size: size of the buffer (in bytes)
3975 * @local_len : length of the returned Local LLDP MIB
3976 * @remote_len: length of the returned Remote LLDP MIB
3977 * @cmd_details: pointer to command details structure or NULL
3979 * Requests the complete LLDP MIB (entire packet).
3981 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3982 u8 mib_type, void *buff, u16 buff_size,
3983 u16 *local_len, u16 *remote_len,
3984 struct i40e_asq_cmd_details *cmd_details)
3986 struct i40e_aq_desc desc;
3987 struct i40e_aqc_lldp_get_mib *cmd =
3988 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3989 struct i40e_aqc_lldp_get_mib *resp =
3990 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3991 enum i40e_status_code status;
3993 if (buff_size == 0 || !buff)
3994 return I40E_ERR_PARAM;
3996 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3997 /* Indirect Command */
3998 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4000 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4001 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4002 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4004 desc.datalen = CPU_TO_LE16(buff_size);
4006 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4007 if (buff_size > I40E_AQ_LARGE_BUF)
4008 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4010 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4012 if (local_len != NULL)
4013 *local_len = LE16_TO_CPU(resp->local_len);
4014 if (remote_len != NULL)
4015 *remote_len = LE16_TO_CPU(resp->remote_len);
4022 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4023 * @hw: pointer to the hw struct
4024 * @mib_type: Local, Remote or both Local and Remote MIBs
4025 * @buff: pointer to a user supplied buffer to store the MIB block
4026 * @buff_size: size of the buffer (in bytes)
4027 * @cmd_details: pointer to command details structure or NULL
4031 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4032 u8 mib_type, void *buff, u16 buff_size,
4033 struct i40e_asq_cmd_details *cmd_details)
4035 struct i40e_aq_desc desc;
4036 struct i40e_aqc_lldp_set_local_mib *cmd =
4037 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4038 enum i40e_status_code status;
4040 if (buff_size == 0 || !buff)
4041 return I40E_ERR_PARAM;
4043 i40e_fill_default_direct_cmd_desc(&desc,
4044 i40e_aqc_opc_lldp_set_local_mib);
4045 /* Indirect Command */
4046 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4047 if (buff_size > I40E_AQ_LARGE_BUF)
4048 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4049 desc.datalen = CPU_TO_LE16(buff_size);
4051 cmd->type = mib_type;
4052 cmd->length = CPU_TO_LE16(buff_size);
4053 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4054 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4056 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4061 * i40e_aq_cfg_lldp_mib_change_event
4062 * @hw: pointer to the hw struct
4063 * @enable_update: Enable or Disable event posting
4064 * @cmd_details: pointer to command details structure or NULL
4066 * Enable or Disable posting of an event on ARQ when LLDP MIB
4067 * associated with the interface changes
4069 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4071 struct i40e_asq_cmd_details *cmd_details)
4073 struct i40e_aq_desc desc;
4074 struct i40e_aqc_lldp_update_mib *cmd =
4075 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4076 enum i40e_status_code status;
4078 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4081 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4083 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4089 * i40e_aq_add_lldp_tlv
4090 * @hw: pointer to the hw struct
4091 * @bridge_type: type of bridge
4092 * @buff: buffer with TLV to add
4093 * @buff_size: length of the buffer
4094 * @tlv_len: length of the TLV to be added
4095 * @mib_len: length of the LLDP MIB returned in response
4096 * @cmd_details: pointer to command details structure or NULL
4098 * Add the specified TLV to LLDP Local MIB for the given bridge type,
4099 * it is responsibility of the caller to make sure that the TLV is not
4100 * already present in the LLDPDU.
4101 * In return firmware will write the complete LLDP MIB with the newly
4102 * added TLV in the response buffer.
4104 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4105 void *buff, u16 buff_size, u16 tlv_len,
4107 struct i40e_asq_cmd_details *cmd_details)
4109 struct i40e_aq_desc desc;
4110 struct i40e_aqc_lldp_add_tlv *cmd =
4111 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4112 enum i40e_status_code status;
4114 if (buff_size == 0 || !buff || tlv_len == 0)
4115 return I40E_ERR_PARAM;
4117 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4119 /* Indirect Command */
4120 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4121 if (buff_size > I40E_AQ_LARGE_BUF)
4122 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4123 desc.datalen = CPU_TO_LE16(buff_size);
4125 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4126 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4127 cmd->len = CPU_TO_LE16(tlv_len);
4129 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4131 if (mib_len != NULL)
4132 *mib_len = LE16_TO_CPU(desc.datalen);
4139 * i40e_aq_update_lldp_tlv
4140 * @hw: pointer to the hw struct
4141 * @bridge_type: type of bridge
4142 * @buff: buffer with TLV to update
4143 * @buff_size: size of the buffer holding original and updated TLVs
4144 * @old_len: Length of the Original TLV
4145 * @new_len: Length of the Updated TLV
4146 * @offset: offset of the updated TLV in the buff
4147 * @mib_len: length of the returned LLDP MIB
4148 * @cmd_details: pointer to command details structure or NULL
4150 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4151 * Firmware will place the complete LLDP MIB in response buffer with the
4154 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4155 u8 bridge_type, void *buff, u16 buff_size,
4156 u16 old_len, u16 new_len, u16 offset,
4158 struct i40e_asq_cmd_details *cmd_details)
4160 struct i40e_aq_desc desc;
4161 struct i40e_aqc_lldp_update_tlv *cmd =
4162 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4163 enum i40e_status_code status;
4165 if (buff_size == 0 || !buff || offset == 0 ||
4166 old_len == 0 || new_len == 0)
4167 return I40E_ERR_PARAM;
4169 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4171 /* Indirect Command */
4172 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4173 if (buff_size > I40E_AQ_LARGE_BUF)
4174 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4175 desc.datalen = CPU_TO_LE16(buff_size);
4177 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4178 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4179 cmd->old_len = CPU_TO_LE16(old_len);
4180 cmd->new_offset = CPU_TO_LE16(offset);
4181 cmd->new_len = CPU_TO_LE16(new_len);
4183 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4185 if (mib_len != NULL)
4186 *mib_len = LE16_TO_CPU(desc.datalen);
4193 * i40e_aq_delete_lldp_tlv
4194 * @hw: pointer to the hw struct
4195 * @bridge_type: type of bridge
4196 * @buff: pointer to a user supplied buffer that has the TLV
4197 * @buff_size: length of the buffer
4198 * @tlv_len: length of the TLV to be deleted
4199 * @mib_len: length of the returned LLDP MIB
4200 * @cmd_details: pointer to command details structure or NULL
4202 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4203 * The firmware places the entire LLDP MIB in the response buffer.
4205 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4206 u8 bridge_type, void *buff, u16 buff_size,
4207 u16 tlv_len, u16 *mib_len,
4208 struct i40e_asq_cmd_details *cmd_details)
4210 struct i40e_aq_desc desc;
4211 struct i40e_aqc_lldp_add_tlv *cmd =
4212 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4213 enum i40e_status_code status;
4215 if (buff_size == 0 || !buff)
4216 return I40E_ERR_PARAM;
4218 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4220 /* Indirect Command */
4221 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4222 if (buff_size > I40E_AQ_LARGE_BUF)
4223 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4224 desc.datalen = CPU_TO_LE16(buff_size);
4225 cmd->len = CPU_TO_LE16(tlv_len);
4226 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4227 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4229 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4231 if (mib_len != NULL)
4232 *mib_len = LE16_TO_CPU(desc.datalen);
4240 * @hw: pointer to the hw struct
4241 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4242 * @cmd_details: pointer to command details structure or NULL
4244 * Stop or Shutdown the embedded LLDP Agent
4246 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4247 struct i40e_asq_cmd_details *cmd_details)
4249 struct i40e_aq_desc desc;
4250 struct i40e_aqc_lldp_stop *cmd =
4251 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4252 enum i40e_status_code status;
4254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4257 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4259 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4265 * i40e_aq_start_lldp
4266 * @hw: pointer to the hw struct
4267 * @cmd_details: pointer to command details structure or NULL
4269 * Start the embedded LLDP Agent on all ports.
4271 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4272 struct i40e_asq_cmd_details *cmd_details)
4274 struct i40e_aq_desc desc;
4275 struct i40e_aqc_lldp_start *cmd =
4276 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4277 enum i40e_status_code status;
4279 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4281 cmd->command = I40E_AQ_LLDP_AGENT_START;
4283 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4289 * i40e_aq_get_cee_dcb_config
4290 * @hw: pointer to the hw struct
4291 * @buff: response buffer that stores CEE operational configuration
4292 * @buff_size: size of the buffer passed
4293 * @cmd_details: pointer to command details structure or NULL
4295 * Get CEE DCBX mode operational configuration from firmware
4297 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4298 void *buff, u16 buff_size,
4299 struct i40e_asq_cmd_details *cmd_details)
4301 struct i40e_aq_desc desc;
4302 enum i40e_status_code status;
4304 if (buff_size == 0 || !buff)
4305 return I40E_ERR_PARAM;
4307 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4309 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4310 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4317 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4318 * @hw: pointer to the hw struct
4319 * @start_agent: True if DCBx Agent needs to be Started
4320 * False if DCBx Agent needs to be Stopped
4321 * @cmd_details: pointer to command details structure or NULL
4323 * Start/Stop the embedded dcbx Agent
4325 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4327 struct i40e_asq_cmd_details *cmd_details)
4329 struct i40e_aq_desc desc;
4330 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4331 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4333 enum i40e_status_code status;
4335 i40e_fill_default_direct_cmd_desc(&desc,
4336 i40e_aqc_opc_lldp_stop_start_spec_agent);
4339 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4347 * i40e_aq_add_udp_tunnel
4348 * @hw: pointer to the hw struct
4349 * @udp_port: the UDP port to add
4350 * @header_len: length of the tunneling header length in DWords
4351 * @protocol_index: protocol index type
4352 * @filter_index: pointer to filter index
4353 * @cmd_details: pointer to command details structure or NULL
4355 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4356 u16 udp_port, u8 protocol_index,
4358 struct i40e_asq_cmd_details *cmd_details)
4360 struct i40e_aq_desc desc;
4361 struct i40e_aqc_add_udp_tunnel *cmd =
4362 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4363 struct i40e_aqc_del_udp_tunnel_completion *resp =
4364 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4365 enum i40e_status_code status;
4367 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4369 cmd->udp_port = CPU_TO_LE16(udp_port);
4370 cmd->protocol_type = protocol_index;
4372 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4374 if (!status && filter_index)
4375 *filter_index = resp->index;
4381 * i40e_aq_del_udp_tunnel
4382 * @hw: pointer to the hw struct
4383 * @index: filter index
4384 * @cmd_details: pointer to command details structure or NULL
4386 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4387 struct i40e_asq_cmd_details *cmd_details)
4389 struct i40e_aq_desc desc;
4390 struct i40e_aqc_remove_udp_tunnel *cmd =
4391 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4392 enum i40e_status_code status;
4394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4398 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4404 * i40e_aq_get_switch_resource_alloc (0x0204)
4405 * @hw: pointer to the hw struct
4406 * @num_entries: pointer to u8 to store the number of resource entries returned
4407 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4408 * to store the resource information for all resource types. Each
4409 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4410 * @count: size, in bytes, of the buffer provided
4411 * @cmd_details: pointer to command details structure or NULL
4413 * Query the resources allocated to a function.
4415 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4417 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4419 struct i40e_asq_cmd_details *cmd_details)
4421 struct i40e_aq_desc desc;
4422 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4423 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4424 enum i40e_status_code status;
4425 u16 length = count * sizeof(*buf);
4427 i40e_fill_default_direct_cmd_desc(&desc,
4428 i40e_aqc_opc_get_switch_resource_alloc);
4430 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4431 if (length > I40E_AQ_LARGE_BUF)
4432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4434 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4436 if (!status && num_entries)
4437 *num_entries = cmd_resp->num_entries;
4443 * i40e_aq_delete_element - Delete switch element
4444 * @hw: pointer to the hw struct
4445 * @seid: the SEID to delete from the switch
4446 * @cmd_details: pointer to command details structure or NULL
4448 * This deletes a switch element from the switch.
4450 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4451 struct i40e_asq_cmd_details *cmd_details)
4453 struct i40e_aq_desc desc;
4454 struct i40e_aqc_switch_seid *cmd =
4455 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4456 enum i40e_status_code status;
4459 return I40E_ERR_PARAM;
4461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4463 cmd->seid = CPU_TO_LE16(seid);
4465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4471 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4472 * @hw: pointer to the hw struct
4473 * @flags: component flags
4474 * @mac_seid: uplink seid (MAC SEID)
4475 * @vsi_seid: connected vsi seid
4476 * @ret_seid: seid of create pv component
4478 * This instantiates an i40e port virtualizer with specified flags.
4479 * Depending on specified flags the port virtualizer can act as a
4480 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4482 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4483 u16 mac_seid, u16 vsi_seid,
4486 struct i40e_aq_desc desc;
4487 struct i40e_aqc_add_update_pv *cmd =
4488 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4489 struct i40e_aqc_add_update_pv_completion *resp =
4490 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4491 enum i40e_status_code status;
4494 return I40E_ERR_PARAM;
4496 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4497 cmd->command_flags = CPU_TO_LE16(flags);
4498 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4499 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4501 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4502 if (!status && ret_seid)
4503 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4509 * i40e_aq_add_tag - Add an S/E-tag
4510 * @hw: pointer to the hw struct
4511 * @direct_to_queue: should s-tag direct flow to a specific queue
4512 * @vsi_seid: VSI SEID to use this tag
4513 * @tag: value of the tag
4514 * @queue_num: queue number, only valid is direct_to_queue is true
4515 * @tags_used: return value, number of tags in use by this PF
4516 * @tags_free: return value, number of unallocated tags
4517 * @cmd_details: pointer to command details structure or NULL
4519 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4520 * the number of tags allocated by the PF, and the number of unallocated
4523 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4524 u16 vsi_seid, u16 tag, u16 queue_num,
4525 u16 *tags_used, u16 *tags_free,
4526 struct i40e_asq_cmd_details *cmd_details)
4528 struct i40e_aq_desc desc;
4529 struct i40e_aqc_add_tag *cmd =
4530 (struct i40e_aqc_add_tag *)&desc.params.raw;
4531 struct i40e_aqc_add_remove_tag_completion *resp =
4532 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4533 enum i40e_status_code status;
4536 return I40E_ERR_PARAM;
4538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4540 cmd->seid = CPU_TO_LE16(vsi_seid);
4541 cmd->tag = CPU_TO_LE16(tag);
4542 if (direct_to_queue) {
4543 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4544 cmd->queue_number = CPU_TO_LE16(queue_num);
4547 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4550 if (tags_used != NULL)
4551 *tags_used = LE16_TO_CPU(resp->tags_used);
4552 if (tags_free != NULL)
4553 *tags_free = LE16_TO_CPU(resp->tags_free);
4560 * i40e_aq_remove_tag - Remove an S- or E-tag
4561 * @hw: pointer to the hw struct
4562 * @vsi_seid: VSI SEID this tag is associated with
4563 * @tag: value of the S-tag to delete
4564 * @tags_used: return value, number of tags in use by this PF
4565 * @tags_free: return value, number of unallocated tags
4566 * @cmd_details: pointer to command details structure or NULL
4568 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4569 * the number of tags allocated by the PF, and the number of unallocated
4572 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4573 u16 tag, u16 *tags_used, u16 *tags_free,
4574 struct i40e_asq_cmd_details *cmd_details)
4576 struct i40e_aq_desc desc;
4577 struct i40e_aqc_remove_tag *cmd =
4578 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4579 struct i40e_aqc_add_remove_tag_completion *resp =
4580 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4581 enum i40e_status_code status;
4584 return I40E_ERR_PARAM;
4586 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4588 cmd->seid = CPU_TO_LE16(vsi_seid);
4589 cmd->tag = CPU_TO_LE16(tag);
4591 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4594 if (tags_used != NULL)
4595 *tags_used = LE16_TO_CPU(resp->tags_used);
4596 if (tags_free != NULL)
4597 *tags_free = LE16_TO_CPU(resp->tags_free);
4604 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4605 * @hw: pointer to the hw struct
4606 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4607 * @etag: value of E-tag to add
4608 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4609 * @buf: address of indirect buffer
4610 * @tags_used: return value, number of E-tags in use by this port
4611 * @tags_free: return value, number of unallocated M-tags
4612 * @cmd_details: pointer to command details structure or NULL
4614 * This associates a multicast E-tag to a port virtualizer. It will return
4615 * the number of tags allocated by the PF, and the number of unallocated
4618 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4619 * num_tags_in_buf long.
4621 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4622 u16 etag, u8 num_tags_in_buf, void *buf,
4623 u16 *tags_used, u16 *tags_free,
4624 struct i40e_asq_cmd_details *cmd_details)
4626 struct i40e_aq_desc desc;
4627 struct i40e_aqc_add_remove_mcast_etag *cmd =
4628 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4629 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4630 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4631 enum i40e_status_code status;
4632 u16 length = sizeof(u16) * num_tags_in_buf;
4634 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4635 return I40E_ERR_PARAM;
4637 i40e_fill_default_direct_cmd_desc(&desc,
4638 i40e_aqc_opc_add_multicast_etag);
4640 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4641 cmd->etag = CPU_TO_LE16(etag);
4642 cmd->num_unicast_etags = num_tags_in_buf;
4644 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4645 if (length > I40E_AQ_LARGE_BUF)
4646 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4648 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4651 if (tags_used != NULL)
4652 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4653 if (tags_free != NULL)
4654 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4661 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4662 * @hw: pointer to the hw struct
4663 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4664 * @etag: value of the E-tag to remove
4665 * @tags_used: return value, number of tags in use by this port
4666 * @tags_free: return value, number of unallocated tags
4667 * @cmd_details: pointer to command details structure or NULL
4669 * This deletes an E-tag from the port virtualizer. It will return
4670 * the number of tags allocated by the port, and the number of unallocated
4673 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4674 u16 etag, u16 *tags_used, u16 *tags_free,
4675 struct i40e_asq_cmd_details *cmd_details)
4677 struct i40e_aq_desc desc;
4678 struct i40e_aqc_add_remove_mcast_etag *cmd =
4679 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4680 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4681 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4682 enum i40e_status_code status;
4686 return I40E_ERR_PARAM;
4688 i40e_fill_default_direct_cmd_desc(&desc,
4689 i40e_aqc_opc_remove_multicast_etag);
4691 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4692 cmd->etag = CPU_TO_LE16(etag);
4694 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4697 if (tags_used != NULL)
4698 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4699 if (tags_free != NULL)
4700 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4707 * i40e_aq_update_tag - Update an S/E-tag
4708 * @hw: pointer to the hw struct
4709 * @vsi_seid: VSI SEID using this S-tag
4710 * @old_tag: old tag value
4711 * @new_tag: new tag value
4712 * @tags_used: return value, number of tags in use by this PF
4713 * @tags_free: return value, number of unallocated tags
4714 * @cmd_details: pointer to command details structure or NULL
4716 * This updates the value of the tag currently attached to this VSI
4717 * in the switch complex. It will return the number of tags allocated
4718 * by the PF, and the number of unallocated tags available.
4720 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4721 u16 old_tag, u16 new_tag, u16 *tags_used,
4723 struct i40e_asq_cmd_details *cmd_details)
4725 struct i40e_aq_desc desc;
4726 struct i40e_aqc_update_tag *cmd =
4727 (struct i40e_aqc_update_tag *)&desc.params.raw;
4728 struct i40e_aqc_update_tag_completion *resp =
4729 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4730 enum i40e_status_code status;
4733 return I40E_ERR_PARAM;
4735 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4737 cmd->seid = CPU_TO_LE16(vsi_seid);
4738 cmd->old_tag = CPU_TO_LE16(old_tag);
4739 cmd->new_tag = CPU_TO_LE16(new_tag);
4741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4744 if (tags_used != NULL)
4745 *tags_used = LE16_TO_CPU(resp->tags_used);
4746 if (tags_free != NULL)
4747 *tags_free = LE16_TO_CPU(resp->tags_free);
4754 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4755 * @hw: pointer to the hw struct
4756 * @tcmap: TC map for request/release any ignore PFC condition
4757 * @request: request or release ignore PFC condition
4758 * @tcmap_ret: return TCs for which PFC is currently ignored
4759 * @cmd_details: pointer to command details structure or NULL
4761 * This sends out request/release to ignore PFC condition for a TC.
4762 * It will return the TCs for which PFC is currently ignored.
4764 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4765 bool request, u8 *tcmap_ret,
4766 struct i40e_asq_cmd_details *cmd_details)
4768 struct i40e_aq_desc desc;
4769 struct i40e_aqc_pfc_ignore *cmd_resp =
4770 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4771 enum i40e_status_code status;
4773 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4776 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4778 cmd_resp->tc_bitmap = tcmap;
4780 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4783 if (tcmap_ret != NULL)
4784 *tcmap_ret = cmd_resp->tc_bitmap;
4791 * i40e_aq_dcb_updated - DCB Updated Command
4792 * @hw: pointer to the hw struct
4793 * @cmd_details: pointer to command details structure or NULL
4795 * When LLDP is handled in PF this command is used by the PF
4796 * to notify EMP that a DCB setting is modified.
4797 * When LLDP is handled in EMP this command is used by the PF
4798 * to notify EMP whenever one of the following parameters get
4800 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4801 * - PCIRTT in PRTDCB_GENC.PCIRTT
4802 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4803 * EMP will return when the shared RPB settings have been
4804 * recomputed and modified. The retval field in the descriptor
4805 * will be set to 0 when RPB is modified.
4807 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4808 struct i40e_asq_cmd_details *cmd_details)
4810 struct i40e_aq_desc desc;
4811 enum i40e_status_code status;
4813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4821 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4822 * @hw: pointer to the hw struct
4823 * @seid: defines the SEID of the switch for which the stats are requested
4824 * @vlan_id: the VLAN ID for which the statistics are requested
4825 * @stat_index: index of the statistics counters block assigned to this VLAN
4826 * @cmd_details: pointer to command details structure or NULL
4828 * XL710 supports 128 smonVlanStats counters.This command is used to
4829 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4832 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4833 u16 vlan_id, u16 *stat_index,
4834 struct i40e_asq_cmd_details *cmd_details)
4836 struct i40e_aq_desc desc;
4837 struct i40e_aqc_add_remove_statistics *cmd_resp =
4838 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4839 enum i40e_status_code status;
4841 if ((seid == 0) || (stat_index == NULL))
4842 return I40E_ERR_PARAM;
4844 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4846 cmd_resp->seid = CPU_TO_LE16(seid);
4847 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4849 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4851 if (!status && stat_index)
4852 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4858 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4859 * @hw: pointer to the hw struct
4860 * @seid: defines the SEID of the switch for which the stats are requested
4861 * @vlan_id: the VLAN ID for which the statistics are requested
4862 * @stat_index: index of the statistics counters block assigned to this VLAN
4863 * @cmd_details: pointer to command details structure or NULL
4865 * XL710 supports 128 smonVlanStats counters.This command is used to
4866 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4869 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4870 u16 vlan_id, u16 stat_index,
4871 struct i40e_asq_cmd_details *cmd_details)
4873 struct i40e_aq_desc desc;
4874 struct i40e_aqc_add_remove_statistics *cmd =
4875 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4876 enum i40e_status_code status;
4879 return I40E_ERR_PARAM;
4881 i40e_fill_default_direct_cmd_desc(&desc,
4882 i40e_aqc_opc_remove_statistics);
4884 cmd->seid = CPU_TO_LE16(seid);
4885 cmd->vlan = CPU_TO_LE16(vlan_id);
4886 cmd->stat_index = CPU_TO_LE16(stat_index);
4888 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4894 * i40e_aq_set_port_parameters - set physical port parameters.
4895 * @hw: pointer to the hw struct
4896 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4897 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4898 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4899 * @double_vlan: if set double VLAN is enabled
4900 * @cmd_details: pointer to command details structure or NULL
4902 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4903 u16 bad_frame_vsi, bool save_bad_pac,
4904 bool pad_short_pac, bool double_vlan,
4905 struct i40e_asq_cmd_details *cmd_details)
4907 struct i40e_aqc_set_port_parameters *cmd;
4908 enum i40e_status_code status;
4909 struct i40e_aq_desc desc;
4910 u16 command_flags = 0;
4912 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4914 i40e_fill_default_direct_cmd_desc(&desc,
4915 i40e_aqc_opc_set_port_parameters);
4917 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4919 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4921 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4923 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4924 cmd->command_flags = CPU_TO_LE16(command_flags);
4926 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4932 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4933 * @hw: pointer to the hw struct
4934 * @seid: seid for the physical port/switching component/vsi
4935 * @buff: Indirect buffer to hold data parameters and response
4936 * @buff_size: Indirect buffer size
4937 * @opcode: Tx scheduler AQ command opcode
4938 * @cmd_details: pointer to command details structure or NULL
4940 * Generic command handler for Tx scheduler AQ commands
4942 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4943 void *buff, u16 buff_size,
4944 enum i40e_admin_queue_opc opcode,
4945 struct i40e_asq_cmd_details *cmd_details)
4947 struct i40e_aq_desc desc;
4948 struct i40e_aqc_tx_sched_ind *cmd =
4949 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4950 enum i40e_status_code status;
4951 bool cmd_param_flag = false;
4954 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4955 case i40e_aqc_opc_configure_vsi_tc_bw:
4956 case i40e_aqc_opc_enable_switching_comp_ets:
4957 case i40e_aqc_opc_modify_switching_comp_ets:
4958 case i40e_aqc_opc_disable_switching_comp_ets:
4959 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4960 case i40e_aqc_opc_configure_switching_comp_bw_config:
4961 cmd_param_flag = true;
4963 case i40e_aqc_opc_query_vsi_bw_config:
4964 case i40e_aqc_opc_query_vsi_ets_sla_config:
4965 case i40e_aqc_opc_query_switching_comp_ets_config:
4966 case i40e_aqc_opc_query_port_ets_config:
4967 case i40e_aqc_opc_query_switching_comp_bw_config:
4968 cmd_param_flag = false;
4971 return I40E_ERR_PARAM;
4974 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4976 /* Indirect command */
4977 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4979 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4980 if (buff_size > I40E_AQ_LARGE_BUF)
4981 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4983 desc.datalen = CPU_TO_LE16(buff_size);
4985 cmd->vsi_seid = CPU_TO_LE16(seid);
4987 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4993 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4994 * @hw: pointer to the hw struct
4996 * @credit: BW limit credits (0 = disabled)
4997 * @max_credit: Max BW limit credits
4998 * @cmd_details: pointer to command details structure or NULL
5000 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5001 u16 seid, u16 credit, u8 max_credit,
5002 struct i40e_asq_cmd_details *cmd_details)
5004 struct i40e_aq_desc desc;
5005 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5006 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5007 enum i40e_status_code status;
5009 i40e_fill_default_direct_cmd_desc(&desc,
5010 i40e_aqc_opc_configure_vsi_bw_limit);
5012 cmd->vsi_seid = CPU_TO_LE16(seid);
5013 cmd->credit = CPU_TO_LE16(credit);
5014 cmd->max_credit = max_credit;
5016 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5022 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5023 * @hw: pointer to the hw struct
5024 * @seid: switching component seid
5025 * @credit: BW limit credits (0 = disabled)
5026 * @max_bw: Max BW limit credits
5027 * @cmd_details: pointer to command details structure or NULL
5029 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5030 u16 seid, u16 credit, u8 max_bw,
5031 struct i40e_asq_cmd_details *cmd_details)
5033 struct i40e_aq_desc desc;
5034 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5035 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5036 enum i40e_status_code status;
5038 i40e_fill_default_direct_cmd_desc(&desc,
5039 i40e_aqc_opc_configure_switching_comp_bw_limit);
5041 cmd->seid = CPU_TO_LE16(seid);
5042 cmd->credit = CPU_TO_LE16(credit);
5043 cmd->max_bw = max_bw;
5045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5051 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5052 * @hw: pointer to the hw struct
5054 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5055 * @cmd_details: pointer to command details structure or NULL
5057 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5059 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5060 struct i40e_asq_cmd_details *cmd_details)
5062 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5063 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5068 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5069 * @hw: pointer to the hw struct
5071 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5072 * @cmd_details: pointer to command details structure or NULL
5074 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5076 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5077 struct i40e_asq_cmd_details *cmd_details)
5079 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5080 i40e_aqc_opc_configure_vsi_tc_bw,
5085 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5086 * @hw: pointer to the hw struct
5087 * @seid: seid of the switching component connected to Physical Port
5088 * @ets_data: Buffer holding ETS parameters
5089 * @cmd_details: pointer to command details structure or NULL
5091 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5093 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5094 enum i40e_admin_queue_opc opcode,
5095 struct i40e_asq_cmd_details *cmd_details)
5097 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5098 sizeof(*ets_data), opcode, cmd_details);
5102 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5103 * @hw: pointer to the hw struct
5104 * @seid: seid of the switching component
5105 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5106 * @cmd_details: pointer to command details structure or NULL
5108 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5110 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5111 struct i40e_asq_cmd_details *cmd_details)
5113 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5114 i40e_aqc_opc_configure_switching_comp_bw_config,
5119 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5120 * @hw: pointer to the hw struct
5121 * @seid: seid of the switching component
5122 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5123 * @cmd_details: pointer to command details structure or NULL
5125 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5126 struct i40e_hw *hw, u16 seid,
5127 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5128 struct i40e_asq_cmd_details *cmd_details)
5130 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5131 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5136 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5137 * @hw: pointer to the hw struct
5138 * @seid: seid of the VSI
5139 * @bw_data: Buffer to hold VSI BW configuration
5140 * @cmd_details: pointer to command details structure or NULL
5142 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5144 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5145 struct i40e_asq_cmd_details *cmd_details)
5147 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5148 i40e_aqc_opc_query_vsi_bw_config,
5153 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5154 * @hw: pointer to the hw struct
5155 * @seid: seid of the VSI
5156 * @bw_data: Buffer to hold VSI BW configuration per TC
5157 * @cmd_details: pointer to command details structure or NULL
5159 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5161 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5162 struct i40e_asq_cmd_details *cmd_details)
5164 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5165 i40e_aqc_opc_query_vsi_ets_sla_config,
5170 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5171 * @hw: pointer to the hw struct
5172 * @seid: seid of the switching component
5173 * @bw_data: Buffer to hold switching component's per TC BW config
5174 * @cmd_details: pointer to command details structure or NULL
5176 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5178 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5179 struct i40e_asq_cmd_details *cmd_details)
5181 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5182 i40e_aqc_opc_query_switching_comp_ets_config,
5187 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5188 * @hw: pointer to the hw struct
5189 * @seid: seid of the VSI or switching component connected to Physical Port
5190 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5191 * @cmd_details: pointer to command details structure or NULL
5193 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5195 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5196 struct i40e_asq_cmd_details *cmd_details)
5198 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5199 i40e_aqc_opc_query_port_ets_config,
5204 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5205 * @hw: pointer to the hw struct
5206 * @seid: seid of the switching component
5207 * @bw_data: Buffer to hold switching component's BW configuration
5208 * @cmd_details: pointer to command details structure or NULL
5210 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5212 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5213 struct i40e_asq_cmd_details *cmd_details)
5215 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5216 i40e_aqc_opc_query_switching_comp_bw_config,
5221 * i40e_validate_filter_settings
5222 * @hw: pointer to the hardware structure
5223 * @settings: Filter control settings
5225 * Check and validate the filter control settings passed.
5226 * The function checks for the valid filter/context sizes being
5227 * passed for FCoE and PE.
5229 * Returns I40E_SUCCESS if the values passed are valid and within
5230 * range else returns an error.
5232 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5233 struct i40e_filter_control_settings *settings)
5235 u32 fcoe_cntx_size, fcoe_filt_size;
5236 u32 pe_cntx_size, pe_filt_size;
5241 /* Validate FCoE settings passed */
5242 switch (settings->fcoe_filt_num) {
5243 case I40E_HASH_FILTER_SIZE_1K:
5244 case I40E_HASH_FILTER_SIZE_2K:
5245 case I40E_HASH_FILTER_SIZE_4K:
5246 case I40E_HASH_FILTER_SIZE_8K:
5247 case I40E_HASH_FILTER_SIZE_16K:
5248 case I40E_HASH_FILTER_SIZE_32K:
5249 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5250 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5253 return I40E_ERR_PARAM;
5256 switch (settings->fcoe_cntx_num) {
5257 case I40E_DMA_CNTX_SIZE_512:
5258 case I40E_DMA_CNTX_SIZE_1K:
5259 case I40E_DMA_CNTX_SIZE_2K:
5260 case I40E_DMA_CNTX_SIZE_4K:
5261 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5262 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5265 return I40E_ERR_PARAM;
5268 /* Validate PE settings passed */
5269 switch (settings->pe_filt_num) {
5270 case I40E_HASH_FILTER_SIZE_1K:
5271 case I40E_HASH_FILTER_SIZE_2K:
5272 case I40E_HASH_FILTER_SIZE_4K:
5273 case I40E_HASH_FILTER_SIZE_8K:
5274 case I40E_HASH_FILTER_SIZE_16K:
5275 case I40E_HASH_FILTER_SIZE_32K:
5276 case I40E_HASH_FILTER_SIZE_64K:
5277 case I40E_HASH_FILTER_SIZE_128K:
5278 case I40E_HASH_FILTER_SIZE_256K:
5279 case I40E_HASH_FILTER_SIZE_512K:
5280 case I40E_HASH_FILTER_SIZE_1M:
5281 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5282 pe_filt_size <<= (u32)settings->pe_filt_num;
5285 return I40E_ERR_PARAM;
5288 switch (settings->pe_cntx_num) {
5289 case I40E_DMA_CNTX_SIZE_512:
5290 case I40E_DMA_CNTX_SIZE_1K:
5291 case I40E_DMA_CNTX_SIZE_2K:
5292 case I40E_DMA_CNTX_SIZE_4K:
5293 case I40E_DMA_CNTX_SIZE_8K:
5294 case I40E_DMA_CNTX_SIZE_16K:
5295 case I40E_DMA_CNTX_SIZE_32K:
5296 case I40E_DMA_CNTX_SIZE_64K:
5297 case I40E_DMA_CNTX_SIZE_128K:
5298 case I40E_DMA_CNTX_SIZE_256K:
5299 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5300 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5303 return I40E_ERR_PARAM;
5306 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5307 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5308 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5309 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5310 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5311 return I40E_ERR_INVALID_SIZE;
5313 return I40E_SUCCESS;
5317 * i40e_set_filter_control
5318 * @hw: pointer to the hardware structure
5319 * @settings: Filter control settings
5321 * Set the Queue Filters for PE/FCoE and enable filters required
5322 * for a single PF. It is expected that these settings are programmed
5323 * at the driver initialization time.
5325 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5326 struct i40e_filter_control_settings *settings)
5328 enum i40e_status_code ret = I40E_SUCCESS;
5329 u32 hash_lut_size = 0;
5333 return I40E_ERR_PARAM;
5335 /* Validate the input settings */
5336 ret = i40e_validate_filter_settings(hw, settings);
5340 /* Read the PF Queue Filter control register */
5341 val = rd32(hw, I40E_PFQF_CTL_0);
5343 /* Program required PE hash buckets for the PF */
5344 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5345 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5346 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5347 /* Program required PE contexts for the PF */
5348 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5349 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5350 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5352 /* Program required FCoE hash buckets for the PF */
5353 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5354 val |= ((u32)settings->fcoe_filt_num <<
5355 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5356 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5357 /* Program required FCoE DDP contexts for the PF */
5358 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5359 val |= ((u32)settings->fcoe_cntx_num <<
5360 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5361 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5363 /* Program Hash LUT size for the PF */
5364 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5365 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5367 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5368 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5370 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5371 if (settings->enable_fdir)
5372 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5373 if (settings->enable_ethtype)
5374 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5375 if (settings->enable_macvlan)
5376 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5378 wr32(hw, I40E_PFQF_CTL_0, val);
5380 return I40E_SUCCESS;
5384 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5385 * @hw: pointer to the hw struct
5386 * @mac_addr: MAC address to use in the filter
5387 * @ethtype: Ethertype to use in the filter
5388 * @flags: Flags that needs to be applied to the filter
5389 * @vsi_seid: seid of the control VSI
5390 * @queue: VSI queue number to send the packet to
5391 * @is_add: Add control packet filter if True else remove
5392 * @stats: Structure to hold information on control filter counts
5393 * @cmd_details: pointer to command details structure or NULL
5395 * This command will Add or Remove control packet filter for a control VSI.
5396 * In return it will update the total number of perfect filter count in
5399 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5400 u8 *mac_addr, u16 ethtype, u16 flags,
5401 u16 vsi_seid, u16 queue, bool is_add,
5402 struct i40e_control_filter_stats *stats,
5403 struct i40e_asq_cmd_details *cmd_details)
5405 struct i40e_aq_desc desc;
5406 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5407 (struct i40e_aqc_add_remove_control_packet_filter *)
5409 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5410 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5412 enum i40e_status_code status;
5415 return I40E_ERR_PARAM;
5418 i40e_fill_default_direct_cmd_desc(&desc,
5419 i40e_aqc_opc_add_control_packet_filter);
5420 cmd->queue = CPU_TO_LE16(queue);
5422 i40e_fill_default_direct_cmd_desc(&desc,
5423 i40e_aqc_opc_remove_control_packet_filter);
5427 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5428 I40E_NONDMA_TO_NONDMA);
5430 cmd->etype = CPU_TO_LE16(ethtype);
5431 cmd->flags = CPU_TO_LE16(flags);
5432 cmd->seid = CPU_TO_LE16(vsi_seid);
5434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5436 if (!status && stats) {
5437 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5438 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5439 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5440 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5447 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5448 * @hw: pointer to the hw struct
5449 * @seid: VSI seid to add ethertype filter from
5451 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5452 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5455 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5456 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5457 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5458 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5459 enum i40e_status_code status;
5461 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5462 seid, 0, true, NULL,
5465 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5469 * i40e_aq_add_cloud_filters
5470 * @hw: pointer to the hardware structure
5471 * @seid: VSI seid to add cloud filters from
5472 * @filters: Buffer which contains the filters to be added
5473 * @filter_count: number of filters contained in the buffer
5475 * Set the cloud filters for a given VSI. The contents of the
5476 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5477 * in by the caller of the function.
5480 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5482 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5485 struct i40e_aq_desc desc;
5486 struct i40e_aqc_add_remove_cloud_filters *cmd =
5487 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5489 enum i40e_status_code status;
5491 i40e_fill_default_direct_cmd_desc(&desc,
5492 i40e_aqc_opc_add_cloud_filters);
5494 buff_len = filter_count * sizeof(*filters);
5495 desc.datalen = CPU_TO_LE16(buff_len);
5496 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5497 cmd->num_filters = filter_count;
5498 cmd->seid = CPU_TO_LE16(seid);
5500 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5506 * i40e_aq_remove_cloud_filters
5507 * @hw: pointer to the hardware structure
5508 * @seid: VSI seid to remove cloud filters from
5509 * @filters: Buffer which contains the filters to be removed
5510 * @filter_count: number of filters contained in the buffer
5512 * Remove the cloud filters for a given VSI. The contents of the
5513 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5514 * in by the caller of the function.
5517 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5519 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5522 struct i40e_aq_desc desc;
5523 struct i40e_aqc_add_remove_cloud_filters *cmd =
5524 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5525 enum i40e_status_code status;
5528 i40e_fill_default_direct_cmd_desc(&desc,
5529 i40e_aqc_opc_remove_cloud_filters);
5531 buff_len = filter_count * sizeof(*filters);
5532 desc.datalen = CPU_TO_LE16(buff_len);
5533 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5534 cmd->num_filters = filter_count;
5535 cmd->seid = CPU_TO_LE16(seid);
5537 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5543 * i40e_aq_alternate_write
5544 * @hw: pointer to the hardware structure
5545 * @reg_addr0: address of first dword to be read
5546 * @reg_val0: value to be written under 'reg_addr0'
5547 * @reg_addr1: address of second dword to be read
5548 * @reg_val1: value to be written under 'reg_addr1'
5550 * Write one or two dwords to alternate structure. Fields are indicated
5551 * by 'reg_addr0' and 'reg_addr1' register numbers.
5554 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5555 u32 reg_addr0, u32 reg_val0,
5556 u32 reg_addr1, u32 reg_val1)
5558 struct i40e_aq_desc desc;
5559 struct i40e_aqc_alternate_write *cmd_resp =
5560 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5561 enum i40e_status_code status;
5563 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5564 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5565 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5566 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5567 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5569 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5575 * i40e_aq_alternate_write_indirect
5576 * @hw: pointer to the hardware structure
5577 * @addr: address of a first register to be modified
5578 * @dw_count: number of alternate structure fields to write
5579 * @buffer: pointer to the command buffer
5581 * Write 'dw_count' dwords from 'buffer' to alternate structure
5582 * starting at 'addr'.
5585 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5586 u32 addr, u32 dw_count, void *buffer)
5588 struct i40e_aq_desc desc;
5589 struct i40e_aqc_alternate_ind_write *cmd_resp =
5590 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5591 enum i40e_status_code status;
5594 return I40E_ERR_PARAM;
5596 /* Indirect command */
5597 i40e_fill_default_direct_cmd_desc(&desc,
5598 i40e_aqc_opc_alternate_write_indirect);
5600 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5601 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5602 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5603 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5605 cmd_resp->address = CPU_TO_LE32(addr);
5606 cmd_resp->length = CPU_TO_LE32(dw_count);
5608 status = i40e_asq_send_command(hw, &desc, buffer,
5609 I40E_LO_DWORD(4*dw_count), NULL);
5615 * i40e_aq_alternate_read
5616 * @hw: pointer to the hardware structure
5617 * @reg_addr0: address of first dword to be read
5618 * @reg_val0: pointer for data read from 'reg_addr0'
5619 * @reg_addr1: address of second dword to be read
5620 * @reg_val1: pointer for data read from 'reg_addr1'
5622 * Read one or two dwords from alternate structure. Fields are indicated
5623 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5624 * is not passed then only register at 'reg_addr0' is read.
5627 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5628 u32 reg_addr0, u32 *reg_val0,
5629 u32 reg_addr1, u32 *reg_val1)
5631 struct i40e_aq_desc desc;
5632 struct i40e_aqc_alternate_write *cmd_resp =
5633 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5634 enum i40e_status_code status;
5636 if (reg_val0 == NULL)
5637 return I40E_ERR_PARAM;
5639 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5640 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5641 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5643 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5645 if (status == I40E_SUCCESS) {
5646 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5648 if (reg_val1 != NULL)
5649 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5656 * i40e_aq_alternate_read_indirect
5657 * @hw: pointer to the hardware structure
5658 * @addr: address of the alternate structure field
5659 * @dw_count: number of alternate structure fields to read
5660 * @buffer: pointer to the command buffer
5662 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5663 * place them in 'buffer'. The buffer should be allocated by caller.
5666 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5667 u32 addr, u32 dw_count, void *buffer)
5669 struct i40e_aq_desc desc;
5670 struct i40e_aqc_alternate_ind_write *cmd_resp =
5671 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5672 enum i40e_status_code status;
5675 return I40E_ERR_PARAM;
5677 /* Indirect command */
5678 i40e_fill_default_direct_cmd_desc(&desc,
5679 i40e_aqc_opc_alternate_read_indirect);
5681 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5682 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5683 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5684 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5686 cmd_resp->address = CPU_TO_LE32(addr);
5687 cmd_resp->length = CPU_TO_LE32(dw_count);
5689 status = i40e_asq_send_command(hw, &desc, buffer,
5690 I40E_LO_DWORD(4*dw_count), NULL);
5696 * i40e_aq_alternate_clear
5697 * @hw: pointer to the HW structure.
5699 * Clear the alternate structures of the port from which the function
5703 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5705 struct i40e_aq_desc desc;
5706 enum i40e_status_code status;
5708 i40e_fill_default_direct_cmd_desc(&desc,
5709 i40e_aqc_opc_alternate_clear_port);
5711 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5717 * i40e_aq_alternate_write_done
5718 * @hw: pointer to the HW structure.
5719 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5720 * @reset_needed: indicates the SW should trigger GLOBAL reset
5722 * Indicates to the FW that alternate structures have been changed.
5725 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5726 u8 bios_mode, bool *reset_needed)
5728 struct i40e_aq_desc desc;
5729 struct i40e_aqc_alternate_write_done *cmd =
5730 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5731 enum i40e_status_code status;
5733 if (reset_needed == NULL)
5734 return I40E_ERR_PARAM;
5736 i40e_fill_default_direct_cmd_desc(&desc,
5737 i40e_aqc_opc_alternate_write_done);
5739 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5741 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5742 if (!status && reset_needed)
5743 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5744 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5750 * i40e_aq_set_oem_mode
5751 * @hw: pointer to the HW structure.
5752 * @oem_mode: the OEM mode to be used
5754 * Sets the device to a specific operating mode. Currently the only supported
5755 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5758 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5761 struct i40e_aq_desc desc;
5762 struct i40e_aqc_alternate_write_done *cmd =
5763 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5764 enum i40e_status_code status;
5766 i40e_fill_default_direct_cmd_desc(&desc,
5767 i40e_aqc_opc_alternate_set_mode);
5769 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5771 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5777 * i40e_aq_resume_port_tx
5778 * @hw: pointer to the hardware structure
5779 * @cmd_details: pointer to command details structure or NULL
5781 * Resume port's Tx traffic
5783 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5784 struct i40e_asq_cmd_details *cmd_details)
5786 struct i40e_aq_desc desc;
5787 enum i40e_status_code status;
5789 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5791 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5797 * i40e_set_pci_config_data - store PCI bus info
5798 * @hw: pointer to hardware structure
5799 * @link_status: the link status word from PCI config space
5801 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5803 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5805 hw->bus.type = i40e_bus_type_pci_express;
5807 switch (link_status & I40E_PCI_LINK_WIDTH) {
5808 case I40E_PCI_LINK_WIDTH_1:
5809 hw->bus.width = i40e_bus_width_pcie_x1;
5811 case I40E_PCI_LINK_WIDTH_2:
5812 hw->bus.width = i40e_bus_width_pcie_x2;
5814 case I40E_PCI_LINK_WIDTH_4:
5815 hw->bus.width = i40e_bus_width_pcie_x4;
5817 case I40E_PCI_LINK_WIDTH_8:
5818 hw->bus.width = i40e_bus_width_pcie_x8;
5821 hw->bus.width = i40e_bus_width_unknown;
5825 switch (link_status & I40E_PCI_LINK_SPEED) {
5826 case I40E_PCI_LINK_SPEED_2500:
5827 hw->bus.speed = i40e_bus_speed_2500;
5829 case I40E_PCI_LINK_SPEED_5000:
5830 hw->bus.speed = i40e_bus_speed_5000;
5832 case I40E_PCI_LINK_SPEED_8000:
5833 hw->bus.speed = i40e_bus_speed_8000;
5836 hw->bus.speed = i40e_bus_speed_unknown;
5842 * i40e_aq_debug_dump
5843 * @hw: pointer to the hardware structure
5844 * @cluster_id: specific cluster to dump
5845 * @table_id: table id within cluster
5846 * @start_index: index of line in the block to read
5847 * @buff_size: dump buffer size
5848 * @buff: dump buffer
5849 * @ret_buff_size: actual buffer size returned
5850 * @ret_next_table: next block to read
5851 * @ret_next_index: next index to read
5853 * Dump internal FW/HW data for debug purposes.
5856 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5857 u8 table_id, u32 start_index, u16 buff_size,
5858 void *buff, u16 *ret_buff_size,
5859 u8 *ret_next_table, u32 *ret_next_index,
5860 struct i40e_asq_cmd_details *cmd_details)
5862 struct i40e_aq_desc desc;
5863 struct i40e_aqc_debug_dump_internals *cmd =
5864 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5865 struct i40e_aqc_debug_dump_internals *resp =
5866 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5867 enum i40e_status_code status;
5869 if (buff_size == 0 || !buff)
5870 return I40E_ERR_PARAM;
5872 i40e_fill_default_direct_cmd_desc(&desc,
5873 i40e_aqc_opc_debug_dump_internals);
5874 /* Indirect Command */
5875 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5876 if (buff_size > I40E_AQ_LARGE_BUF)
5877 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5879 cmd->cluster_id = cluster_id;
5880 cmd->table_id = table_id;
5881 cmd->idx = CPU_TO_LE32(start_index);
5883 desc.datalen = CPU_TO_LE16(buff_size);
5885 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5887 if (ret_buff_size != NULL)
5888 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5889 if (ret_next_table != NULL)
5890 *ret_next_table = resp->table_id;
5891 if (ret_next_index != NULL)
5892 *ret_next_index = LE32_TO_CPU(resp->idx);
5899 * i40e_read_bw_from_alt_ram
5900 * @hw: pointer to the hardware structure
5901 * @max_bw: pointer for max_bw read
5902 * @min_bw: pointer for min_bw read
5903 * @min_valid: pointer for bool that is true if min_bw is a valid value
5904 * @max_valid: pointer for bool that is true if max_bw is a valid value
5906 * Read bw from the alternate ram for the given pf
5908 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5909 u32 *max_bw, u32 *min_bw,
5910 bool *min_valid, bool *max_valid)
5912 enum i40e_status_code status;
5913 u32 max_bw_addr, min_bw_addr;
5915 /* Calculate the address of the min/max bw registers */
5916 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5917 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5918 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5919 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5920 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5921 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5923 /* Read the bandwidths from alt ram */
5924 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5925 min_bw_addr, min_bw);
5927 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5932 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5941 * i40e_aq_configure_partition_bw
5942 * @hw: pointer to the hardware structure
5943 * @bw_data: Buffer holding valid pfs and bw limits
5944 * @cmd_details: pointer to command details
5946 * Configure partitions guaranteed/max bw
5948 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5949 struct i40e_aqc_configure_partition_bw_data *bw_data,
5950 struct i40e_asq_cmd_details *cmd_details)
5952 enum i40e_status_code status;
5953 struct i40e_aq_desc desc;
5954 u16 bwd_size = sizeof(*bw_data);
5956 i40e_fill_default_direct_cmd_desc(&desc,
5957 i40e_aqc_opc_configure_partition_bw);
5959 /* Indirect command */
5960 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5961 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5963 if (bwd_size > I40E_AQ_LARGE_BUF)
5964 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5966 desc.datalen = CPU_TO_LE16(bwd_size);
5968 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5974 * i40e_read_phy_register
5975 * @hw: pointer to the HW structure
5976 * @page: registers page number
5977 * @reg: register address in the page
5978 * @phy_adr: PHY address on MDIO interface
5979 * @value: PHY register value
5981 * Reads specified PHY register value
5983 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5984 u8 page, u16 reg, u8 phy_addr,
5987 enum i40e_status_code status = I40E_ERR_TIMEOUT;
5990 u8 port_num = (u8)hw->func_caps.mdio_port_num;
5992 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
5993 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5994 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5995 (I40E_MDIO_OPCODE_ADDRESS) |
5996 (I40E_MDIO_STCODE) |
5997 (I40E_GLGEN_MSCA_MDICMD_MASK) |
5998 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
5999 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6001 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6002 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6003 status = I40E_SUCCESS;
6006 i40e_usec_delay(10);
6011 i40e_debug(hw, I40E_DEBUG_PHY,
6012 "PHY: Can't write command to external PHY.\n");
6016 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6017 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6018 (I40E_MDIO_OPCODE_READ) |
6019 (I40E_MDIO_STCODE) |
6020 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6021 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6022 status = I40E_ERR_TIMEOUT;
6024 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6026 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6027 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6028 status = I40E_SUCCESS;
6031 i40e_usec_delay(10);
6036 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6037 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6038 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6040 i40e_debug(hw, I40E_DEBUG_PHY,
6041 "PHY: Can't read register value from external PHY.\n");
6049 * i40e_write_phy_register
6050 * @hw: pointer to the HW structure
6051 * @page: registers page number
6052 * @reg: register address in the page
6053 * @phy_adr: PHY address on MDIO interface
6054 * @value: PHY register value
6056 * Writes value to specified PHY register
6058 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6059 u8 page, u16 reg, u8 phy_addr,
6062 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6065 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6067 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6068 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6069 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6070 (I40E_MDIO_OPCODE_ADDRESS) |
6071 (I40E_MDIO_STCODE) |
6072 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6073 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6074 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6076 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6077 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6078 status = I40E_SUCCESS;
6081 i40e_usec_delay(10);
6085 i40e_debug(hw, I40E_DEBUG_PHY,
6086 "PHY: Can't write command to external PHY.\n");
6090 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6091 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6093 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6094 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6095 (I40E_MDIO_OPCODE_WRITE) |
6096 (I40E_MDIO_STCODE) |
6097 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6098 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6099 status = I40E_ERR_TIMEOUT;
6101 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6103 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6104 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6105 status = I40E_SUCCESS;
6108 i40e_usec_delay(10);
6117 * i40e_get_phy_address
6118 * @hw: pointer to the HW structure
6119 * @dev_num: PHY port num that address we want
6120 * @phy_addr: Returned PHY address
6122 * Gets PHY address for current port
6124 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6126 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6127 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6129 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6133 * i40e_blink_phy_led
6134 * @hw: pointer to the HW structure
6135 * @time: time how long led will blinks in secs
6136 * @interval: gap between LED on and off in msecs
6138 * Blinks PHY link LED
6140 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6141 u32 time, u32 interval)
6143 enum i40e_status_code status = I40E_SUCCESS;
6148 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6152 i = rd32(hw, I40E_PFGEN_PORTNUM);
6153 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6154 phy_addr = i40e_get_phy_address(hw, port_num);
6156 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6158 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6159 led_addr, phy_addr, &led_reg);
6161 goto phy_blinking_end;
6163 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6165 status = i40e_write_phy_register(hw,
6166 I40E_PHY_COM_REG_PAGE,
6170 goto phy_blinking_end;
6175 if (time > 0 && interval > 0) {
6176 for (i = 0; i < time * 1000; i += interval) {
6177 status = i40e_read_phy_register(hw,
6178 I40E_PHY_COM_REG_PAGE,
6182 goto restore_config;
6183 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6186 led_reg = I40E_PHY_LED_MANUAL_ON;
6187 status = i40e_write_phy_register(hw,
6188 I40E_PHY_COM_REG_PAGE,
6192 goto restore_config;
6193 i40e_msec_delay(interval);
6198 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6206 * i40e_led_get_phy - return current on/off mode
6207 * @hw: pointer to the hw struct
6208 * @led_addr: address of led register to use
6209 * @val: original value of register to use
6212 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6215 enum i40e_status_code status = I40E_SUCCESS;
6223 temp_addr = I40E_PHY_LED_PROV_REG_1;
6224 i = rd32(hw, I40E_PFGEN_PORTNUM);
6225 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6226 phy_addr = i40e_get_phy_address(hw, port_num);
6228 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6230 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6231 temp_addr, phy_addr, ®_val);
6235 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6236 *led_addr = temp_addr;
6245 * @hw: pointer to the HW structure
6246 * @on: true or false
6247 * @mode: original val plus bit for set or ignore
6248 * Set led's on or off when controlled by the PHY
6251 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6252 u16 led_addr, u32 mode)
6254 enum i40e_status_code status = I40E_SUCCESS;
6261 i = rd32(hw, I40E_PFGEN_PORTNUM);
6262 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6263 phy_addr = i40e_get_phy_address(hw, port_num);
6265 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6266 phy_addr, &led_reg);
6270 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6272 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6273 led_addr, phy_addr, led_reg);
6277 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6278 led_addr, phy_addr, &led_reg);
6280 goto restore_config;
6282 led_reg = I40E_PHY_LED_MANUAL_ON;
6285 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6286 led_addr, phy_addr, led_reg);
6288 goto restore_config;
6289 if (mode & I40E_PHY_LED_MODE_ORIG) {
6290 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6291 status = i40e_write_phy_register(hw,
6292 I40E_PHY_COM_REG_PAGE,
6293 led_addr, phy_addr, led_ctl);
6297 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6301 #endif /* PF_DRIVER */
6305 * i40e_aq_send_msg_to_pf
6306 * @hw: pointer to the hardware structure
6307 * @v_opcode: opcodes for VF-PF communication
6308 * @v_retval: return error code
6309 * @msg: pointer to the msg buffer
6310 * @msglen: msg length
6311 * @cmd_details: pointer to command details
6313 * Send message to PF driver using admin queue. By default, this message
6314 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6315 * completion before returning.
6317 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6318 enum i40e_virtchnl_ops v_opcode,
6319 enum i40e_status_code v_retval,
6320 u8 *msg, u16 msglen,
6321 struct i40e_asq_cmd_details *cmd_details)
6323 struct i40e_aq_desc desc;
6324 struct i40e_asq_cmd_details details;
6325 enum i40e_status_code status;
6327 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6328 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6329 desc.cookie_high = CPU_TO_LE32(v_opcode);
6330 desc.cookie_low = CPU_TO_LE32(v_retval);
6332 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6333 | I40E_AQ_FLAG_RD));
6334 if (msglen > I40E_AQ_LARGE_BUF)
6335 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6336 desc.datalen = CPU_TO_LE16(msglen);
6339 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6340 details.async = true;
6341 cmd_details = &details;
6343 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6344 msglen, cmd_details);
6349 * i40e_vf_parse_hw_config
6350 * @hw: pointer to the hardware structure
6351 * @msg: pointer to the virtual channel VF resource structure
6353 * Given a VF resource message from the PF, populate the hw struct
6354 * with appropriate information.
6356 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6357 struct i40e_virtchnl_vf_resource *msg)
6359 struct i40e_virtchnl_vsi_resource *vsi_res;
6362 vsi_res = &msg->vsi_res[0];
6364 hw->dev_caps.num_vsis = msg->num_vsis;
6365 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6366 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6367 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6368 hw->dev_caps.dcb = msg->vf_offload_flags &
6369 I40E_VIRTCHNL_VF_OFFLOAD_L2;
6370 hw->dev_caps.fcoe = (msg->vf_offload_flags &
6371 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6372 hw->dev_caps.iwarp = (msg->vf_offload_flags &
6373 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6374 for (i = 0; i < msg->num_vsis; i++) {
6375 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6376 i40e_memcpy(hw->mac.perm_addr,
6377 vsi_res->default_mac_addr,
6378 I40E_ETH_LENGTH_OF_ADDRESS,
6379 I40E_NONDMA_TO_NONDMA);
6380 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6381 I40E_ETH_LENGTH_OF_ADDRESS,
6382 I40E_NONDMA_TO_NONDMA);
6390 * @hw: pointer to the hardware structure
6392 * Send a VF_RESET message to the PF. Does not wait for response from PF
6393 * as none will be forthcoming. Immediately after calling this function,
6394 * the admin queue should be shut down and (optionally) reinitialized.
6396 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6398 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6399 I40E_SUCCESS, NULL, 0, NULL);
6401 #endif /* VF_DRIVER */
6405 * i40e_aq_set_arp_proxy_config
6406 * @hw: pointer to the HW structure
6407 * @proxy_config - pointer to proxy config command table struct
6408 * @cmd_details: pointer to command details
6410 * Set ARP offload parameters from pre-populated
6411 * i40e_aqc_arp_proxy_data struct
6413 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6414 struct i40e_aqc_arp_proxy_data *proxy_config,
6415 struct i40e_asq_cmd_details *cmd_details)
6417 struct i40e_aq_desc desc;
6418 enum i40e_status_code status;
6421 return I40E_ERR_PARAM;
6423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6425 desc.params.external.addr_high =
6426 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6427 desc.params.external.addr_low =
6428 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6430 status = i40e_asq_send_command(hw, &desc, proxy_config,
6431 sizeof(struct i40e_aqc_arp_proxy_data),
6438 * i40e_aq_opc_set_ns_proxy_table_entry
6439 * @hw: pointer to the HW structure
6440 * @ns_proxy_table_entry: pointer to NS table entry command struct
6441 * @cmd_details: pointer to command details
6443 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6444 * from pre-populated i40e_aqc_ns_proxy_data struct
6446 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6447 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6448 struct i40e_asq_cmd_details *cmd_details)
6450 struct i40e_aq_desc desc;
6451 enum i40e_status_code status;
6453 if (!ns_proxy_table_entry)
6454 return I40E_ERR_PARAM;
6456 i40e_fill_default_direct_cmd_desc(&desc,
6457 i40e_aqc_opc_set_ns_proxy_table_entry);
6459 desc.params.external.addr_high =
6460 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6461 desc.params.external.addr_low =
6462 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6464 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6465 sizeof(struct i40e_aqc_ns_proxy_data),
6472 * i40e_aq_set_clear_wol_filter
6473 * @hw: pointer to the hw struct
6474 * @filter_index: index of filter to modify (0-7)
6475 * @filter: buffer containing filter to be set
6476 * @set_filter: true to set filter, false to clear filter
6477 * @no_wol_tco: if true, pass through packets cannot cause wake-up
6478 * if false, pass through packets may cause wake-up
6479 * @filter_valid: true if filter action is valid
6480 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6481 * @cmd_details: pointer to command details structure or NULL
6483 * Set or clear WoL filter for port attached to the PF
6485 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6487 struct i40e_aqc_set_wol_filter_data *filter,
6488 bool set_filter, bool no_wol_tco,
6489 bool filter_valid, bool no_wol_tco_valid,
6490 struct i40e_asq_cmd_details *cmd_details)
6492 struct i40e_aq_desc desc;
6493 struct i40e_aqc_set_wol_filter *cmd =
6494 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6495 enum i40e_status_code status;
6497 u16 valid_flags = 0;
6500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6502 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6503 return I40E_ERR_PARAM;
6504 cmd->filter_index = CPU_TO_LE16(filter_index);
6508 return I40E_ERR_PARAM;
6509 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6510 buff_len = sizeof(*filter);
6513 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6514 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6517 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6518 if (no_wol_tco_valid)
6519 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6520 cmd->valid_flags = CPU_TO_LE16(valid_flags);
6522 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6523 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6525 status = i40e_asq_send_command(hw, &desc, filter,
6526 buff_len, cmd_details);
6532 * i40e_aq_get_wake_event_reason
6533 * @hw: pointer to the hw struct
6534 * @wake_reason: return value, index of matching filter
6535 * @cmd_details: pointer to command details structure or NULL
6537 * Get information for the reason of a Wake Up event
6539 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6541 struct i40e_asq_cmd_details *cmd_details)
6543 struct i40e_aq_desc desc;
6544 struct i40e_aqc_get_wake_reason_completion *resp =
6545 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6546 enum i40e_status_code status;
6548 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6552 if (status == I40E_SUCCESS)
6553 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6558 #endif /* X722_SUPPORT */