1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_prototype.h"
36 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
38 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
40 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
41 u16 *words, u16 *data);
42 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
43 u16 *words, u16 *data);
44 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
45 u32 offset, u16 words, void *data,
49 * i40e_init_nvm_ops - Initialize NVM function pointers
50 * @hw: pointer to the HW structure
52 * Setup the function pointers and the NVM info structure. Should be called
53 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
54 * Please notice that the NVM term is used here (& in all methods covered
55 * in this file) as an equivalent of the FLASH part mapped into the SR.
56 * We are accessing FLASH always thru the Shadow RAM.
58 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
60 struct i40e_nvm_info *nvm = &hw->nvm;
61 enum i40e_status_code ret_code = I40E_SUCCESS;
65 DEBUGFUNC("i40e_init_nvm");
67 /* The SR size is stored regardless of the nvm programming mode
68 * as the blank mode may be used in the factory line.
70 gens = rd32(hw, I40E_GLNVM_GENS);
71 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
72 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
73 /* Switching to words (sr_size contains power of 2KB) */
74 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
76 /* Check if we are in the normal or blank NVM programming mode */
77 fla = rd32(hw, I40E_GLNVM_FLA);
78 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
80 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
81 nvm->blank_nvm_mode = false;
82 } else { /* Blank programming mode */
83 nvm->blank_nvm_mode = true;
84 ret_code = I40E_ERR_NVM_BLANK_MODE;
85 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
92 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
93 * @hw: pointer to the HW structure
94 * @access: NVM access type (read or write)
96 * This function will request NVM ownership for reading
97 * via the proper Admin Command.
99 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
100 enum i40e_aq_resource_access_type access)
102 enum i40e_status_code ret_code = I40E_SUCCESS;
106 DEBUGFUNC("i40e_acquire_nvm");
108 if (hw->nvm.blank_nvm_mode)
109 goto i40e_i40e_acquire_nvm_exit;
111 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
112 0, &time_left, NULL);
113 /* Reading the Global Device Timer */
114 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
116 /* Store the timeout */
117 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
120 i40e_debug(hw, I40E_DEBUG_NVM,
121 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
122 access, time_left, ret_code, hw->aq.asq_last_status);
124 if (ret_code && time_left) {
125 /* Poll until the current NVM owner timeouts */
126 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
127 while ((gtime < timeout) && time_left) {
129 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
130 ret_code = i40e_aq_request_resource(hw,
131 I40E_NVM_RESOURCE_ID,
132 access, 0, &time_left,
134 if (ret_code == I40E_SUCCESS) {
135 hw->nvm.hw_semaphore_timeout =
136 I40E_MS_TO_GTIME(time_left) + gtime;
140 if (ret_code != I40E_SUCCESS) {
141 hw->nvm.hw_semaphore_timeout = 0;
142 i40e_debug(hw, I40E_DEBUG_NVM,
143 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
144 time_left, ret_code, hw->aq.asq_last_status);
148 i40e_i40e_acquire_nvm_exit:
153 * i40e_release_nvm - Generic request for releasing the NVM ownership
154 * @hw: pointer to the HW structure
156 * This function will release NVM resource via the proper Admin Command.
158 void i40e_release_nvm(struct i40e_hw *hw)
160 enum i40e_status_code ret_code = I40E_SUCCESS;
163 DEBUGFUNC("i40e_release_nvm");
165 if (hw->nvm.blank_nvm_mode)
168 ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
170 /* there are some rare cases when trying to release the resource
171 * results in an admin Q timeout, so handle them correctly
173 while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
174 (total_delay < hw->aq.asq_cmd_timeout)) {
176 ret_code = i40e_aq_release_resource(hw,
177 I40E_NVM_RESOURCE_ID, 0, NULL);
183 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
184 * @hw: pointer to the HW structure
186 * Polls the SRCTL Shadow RAM register done bit.
188 static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
190 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
193 DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
195 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
196 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
197 srctl = rd32(hw, I40E_GLNVM_SRCTL);
198 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
199 ret_code = I40E_SUCCESS;
204 if (ret_code == I40E_ERR_TIMEOUT)
205 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
210 * i40e_read_nvm_word - Reads Shadow RAM
211 * @hw: pointer to the HW structure
212 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
213 * @data: word read from the Shadow RAM
215 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
217 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
220 return i40e_read_nvm_word_srctl(hw, offset, data);
224 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
225 * @hw: pointer to the HW structure
226 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
227 * @data: word read from the Shadow RAM
229 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
231 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
234 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
237 DEBUGFUNC("i40e_read_nvm_word_srctl");
239 if (offset >= hw->nvm.sr_size) {
240 i40e_debug(hw, I40E_DEBUG_NVM,
241 "NVM read error: Offset %d beyond Shadow RAM limit %d\n",
242 offset, hw->nvm.sr_size);
243 ret_code = I40E_ERR_PARAM;
247 /* Poll the done bit first */
248 ret_code = i40e_poll_sr_srctl_done_bit(hw);
249 if (ret_code == I40E_SUCCESS) {
250 /* Write the address and start reading */
251 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
252 BIT(I40E_GLNVM_SRCTL_START_SHIFT);
253 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
255 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
256 ret_code = i40e_poll_sr_srctl_done_bit(hw);
257 if (ret_code == I40E_SUCCESS) {
258 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
259 *data = (u16)((sr_reg &
260 I40E_GLNVM_SRDATA_RDDATA_MASK)
261 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
264 if (ret_code != I40E_SUCCESS)
265 i40e_debug(hw, I40E_DEBUG_NVM,
266 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
274 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
275 * @hw: pointer to the HW structure
276 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
277 * @data: word read from the Shadow RAM
279 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
281 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
284 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
286 DEBUGFUNC("i40e_read_nvm_word_aq");
288 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
289 *data = LE16_TO_CPU(*(__le16 *)data);
295 * i40e_read_nvm_buffer - Reads Shadow RAM buffer
296 * @hw: pointer to the HW structure
297 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
298 * @words: (in) number of words to read; (out) number of words actually read
299 * @data: words read from the Shadow RAM
301 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
302 * method. The buffer read is preceded by the NVM ownership take
303 * and followed by the release.
305 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
306 u16 *words, u16 *data)
308 return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
312 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
313 * @hw: pointer to the HW structure
314 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
315 * @words: (in) number of words to read; (out) number of words actually read
316 * @data: words read from the Shadow RAM
318 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
319 * method. The buffer read is preceded by the NVM ownership take
320 * and followed by the release.
322 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
323 u16 *words, u16 *data)
325 enum i40e_status_code ret_code = I40E_SUCCESS;
328 DEBUGFUNC("i40e_read_nvm_buffer_srctl");
330 /* Loop thru the selected region */
331 for (word = 0; word < *words; word++) {
332 index = offset + word;
333 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
334 if (ret_code != I40E_SUCCESS)
338 /* Update the number of words read from the Shadow RAM */
345 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
346 * @hw: pointer to the HW structure
347 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
348 * @words: (in) number of words to read; (out) number of words actually read
349 * @data: words read from the Shadow RAM
351 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
352 * method. The buffer read is preceded by the NVM ownership take
353 * and followed by the release.
355 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
356 u16 *words, u16 *data)
358 enum i40e_status_code ret_code;
359 u16 read_size = *words;
360 bool last_cmd = false;
364 DEBUGFUNC("i40e_read_nvm_buffer_aq");
367 /* Calculate number of bytes we should read in this step.
368 * FVL AQ do not allow to read more than one page at a time or
369 * to cross page boundaries.
371 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
372 read_size = min(*words,
373 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
374 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
376 read_size = min((*words - words_read),
377 I40E_SR_SECTOR_SIZE_IN_WORDS);
379 /* Check if this is last command, if so set proper flag */
380 if ((words_read + read_size) >= *words)
383 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
384 data + words_read, last_cmd);
385 if (ret_code != I40E_SUCCESS)
386 goto read_nvm_buffer_aq_exit;
388 /* Increment counter for words already read and move offset to
391 words_read += read_size;
393 } while (words_read < *words);
395 for (i = 0; i < *words; i++)
396 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
398 read_nvm_buffer_aq_exit:
404 * i40e_read_nvm_aq - Read Shadow RAM.
405 * @hw: pointer to the HW structure.
406 * @module_pointer: module pointer location in words from the NVM beginning
407 * @offset: offset in words from module start
408 * @words: number of words to write
409 * @data: buffer with words to write to the Shadow RAM
410 * @last_command: tells the AdminQ that this is the last command
412 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
414 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
415 u32 offset, u16 words, void *data,
418 enum i40e_status_code ret_code = I40E_ERR_NVM;
419 struct i40e_asq_cmd_details cmd_details;
421 DEBUGFUNC("i40e_read_nvm_aq");
423 memset(&cmd_details, 0, sizeof(cmd_details));
424 cmd_details.wb_desc = &hw->nvm_wb_desc;
426 /* Here we are checking the SR limit only for the flat memory model.
427 * We cannot do it for the module-based model, as we did not acquire
428 * the NVM resource yet (we cannot get the module pointer value).
429 * Firmware will check the module-based model.
431 if ((offset + words) > hw->nvm.sr_size)
432 i40e_debug(hw, I40E_DEBUG_NVM,
433 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
434 (offset + words), hw->nvm.sr_size);
435 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
436 /* We can write only up to 4KB (one sector), in one AQ write */
437 i40e_debug(hw, I40E_DEBUG_NVM,
438 "NVM write fail error: tried to write %d words, limit is %d.\n",
439 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
440 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
441 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
442 /* A single write cannot spread over two sectors */
443 i40e_debug(hw, I40E_DEBUG_NVM,
444 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
447 ret_code = i40e_aq_read_nvm(hw, module_pointer,
448 2 * offset, /*bytes*/
450 data, last_command, &cmd_details);
456 * i40e_write_nvm_aq - Writes Shadow RAM.
457 * @hw: pointer to the HW structure.
458 * @module_pointer: module pointer location in words from the NVM beginning
459 * @offset: offset in words from module start
460 * @words: number of words to write
461 * @data: buffer with words to write to the Shadow RAM
462 * @last_command: tells the AdminQ that this is the last command
464 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
466 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
467 u32 offset, u16 words, void *data,
470 enum i40e_status_code ret_code = I40E_ERR_NVM;
471 struct i40e_asq_cmd_details cmd_details;
473 DEBUGFUNC("i40e_write_nvm_aq");
475 memset(&cmd_details, 0, sizeof(cmd_details));
476 cmd_details.wb_desc = &hw->nvm_wb_desc;
478 /* Here we are checking the SR limit only for the flat memory model.
479 * We cannot do it for the module-based model, as we did not acquire
480 * the NVM resource yet (we cannot get the module pointer value).
481 * Firmware will check the module-based model.
483 if ((offset + words) > hw->nvm.sr_size)
484 DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
485 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
486 /* We can write only up to 4KB (one sector), in one AQ write */
487 DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
488 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
489 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
490 /* A single write cannot spread over two sectors */
491 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
493 ret_code = i40e_aq_update_nvm(hw, module_pointer,
494 2 * offset, /*bytes*/
496 data, last_command, &cmd_details);
502 * i40e_write_nvm_word - Writes Shadow RAM word
503 * @hw: pointer to the HW structure
504 * @offset: offset of the Shadow RAM word to write
505 * @data: word to write to the Shadow RAM
507 * Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
508 * NVM ownership have to be acquired and released (on ARQ completion event
509 * reception) by caller. To commit SR to NVM update checksum function
512 enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
515 DEBUGFUNC("i40e_write_nvm_word");
517 *((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));
519 /* Value 0x00 below means that we treat SR as a flat mem */
520 return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);
524 * i40e_write_nvm_buffer - Writes Shadow RAM buffer
525 * @hw: pointer to the HW structure
526 * @module_pointer: module pointer location in words from the NVM beginning
527 * @offset: offset of the Shadow RAM buffer to write
528 * @words: number of words to write
529 * @data: words to write to the Shadow RAM
531 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
532 * NVM ownership must be acquired before calling this function and released
533 * on ARQ completion event reception by caller. To commit SR to NVM update
534 * checksum function should be called.
536 enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,
537 u8 module_pointer, u32 offset,
538 u16 words, void *data)
540 __le16 *le_word_ptr = (__le16 *)data;
541 u16 *word_ptr = (u16 *)data;
544 DEBUGFUNC("i40e_write_nvm_buffer");
546 for (i = 0; i < words; i++)
547 le_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);
549 /* Here we will only write one buffer as the size of the modules
550 * mirrored in the Shadow RAM is always less than 4K.
552 return i40e_write_nvm_aq(hw, module_pointer, offset, words,
557 * i40e_calc_nvm_checksum - Calculates and returns the checksum
558 * @hw: pointer to hardware structure
559 * @checksum: pointer to the checksum
561 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
562 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
563 * is customer specific and unknown. Therefore, this function skips all maximum
564 * possible size of VPD (1kB).
566 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
568 enum i40e_status_code ret_code = I40E_SUCCESS;
569 struct i40e_virt_mem vmem;
570 u16 pcie_alt_module = 0;
571 u16 checksum_local = 0;
576 DEBUGFUNC("i40e_calc_nvm_checksum");
578 ret_code = i40e_allocate_virt_mem(hw, &vmem,
579 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
581 goto i40e_calc_nvm_checksum_exit;
582 data = (u16 *)vmem.va;
584 /* read pointer to VPD area */
585 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
586 if (ret_code != I40E_SUCCESS) {
587 ret_code = I40E_ERR_NVM_CHECKSUM;
588 goto i40e_calc_nvm_checksum_exit;
591 /* read pointer to PCIe Alt Auto-load module */
592 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
594 if (ret_code != I40E_SUCCESS) {
595 ret_code = I40E_ERR_NVM_CHECKSUM;
596 goto i40e_calc_nvm_checksum_exit;
599 /* Calculate SW checksum that covers the whole 64kB shadow RAM
600 * except the VPD and PCIe ALT Auto-load modules
602 for (i = 0; i < hw->nvm.sr_size; i++) {
604 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
605 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
607 ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
608 if (ret_code != I40E_SUCCESS) {
609 ret_code = I40E_ERR_NVM_CHECKSUM;
610 goto i40e_calc_nvm_checksum_exit;
614 /* Skip Checksum word */
615 if (i == I40E_SR_SW_CHECKSUM_WORD)
617 /* Skip VPD module (convert byte size to word count) */
618 if ((i >= (u32)vpd_module) &&
619 (i < ((u32)vpd_module +
620 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
623 /* Skip PCIe ALT module (convert byte size to word count) */
624 if ((i >= (u32)pcie_alt_module) &&
625 (i < ((u32)pcie_alt_module +
626 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
630 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
633 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
635 i40e_calc_nvm_checksum_exit:
636 i40e_free_virt_mem(hw, &vmem);
641 * i40e_update_nvm_checksum - Updates the NVM checksum
642 * @hw: pointer to hardware structure
644 * NVM ownership must be acquired before calling this function and released
645 * on ARQ completion event reception by caller.
646 * This function will commit SR to NVM.
648 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
650 enum i40e_status_code ret_code = I40E_SUCCESS;
654 DEBUGFUNC("i40e_update_nvm_checksum");
656 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
657 le_sum = CPU_TO_LE16(checksum);
658 if (ret_code == I40E_SUCCESS)
659 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
666 * i40e_validate_nvm_checksum - Validate EEPROM checksum
667 * @hw: pointer to hardware structure
668 * @checksum: calculated checksum
670 * Performs checksum calculation and validates the NVM SW checksum. If the
671 * caller does not need checksum, the value can be NULL.
673 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
676 enum i40e_status_code ret_code = I40E_SUCCESS;
678 u16 checksum_local = 0;
680 DEBUGFUNC("i40e_validate_nvm_checksum");
682 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
683 if (ret_code != I40E_SUCCESS)
684 goto i40e_validate_nvm_checksum_exit;
686 /* Do not use i40e_read_nvm_word() because we do not want to take
687 * the synchronization semaphores twice here.
689 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
691 /* Verify read checksum from EEPROM is the same as
692 * calculated checksum
694 if (checksum_local != checksum_sr)
695 ret_code = I40E_ERR_NVM_CHECKSUM;
697 /* If the user cares, return the calculated checksum */
699 *checksum = checksum_local;
701 i40e_validate_nvm_checksum_exit:
705 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
706 struct i40e_nvm_access *cmd,
707 u8 *bytes, int *perrno);
708 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
709 struct i40e_nvm_access *cmd,
710 u8 *bytes, int *perrno);
711 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
712 struct i40e_nvm_access *cmd,
713 u8 *bytes, int *perrno);
714 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
715 struct i40e_nvm_access *cmd,
717 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
718 struct i40e_nvm_access *cmd,
720 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
721 struct i40e_nvm_access *cmd,
722 u8 *bytes, int *perrno);
723 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
724 struct i40e_nvm_access *cmd,
725 u8 *bytes, int *perrno);
726 STATIC enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
727 struct i40e_nvm_access *cmd,
728 u8 *bytes, int *perrno);
729 STATIC enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
730 struct i40e_nvm_access *cmd,
731 u8 *bytes, int *perrno);
732 STATIC INLINE u8 i40e_nvmupd_get_module(u32 val)
734 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
736 STATIC INLINE u8 i40e_nvmupd_get_transaction(u32 val)
738 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
741 STATIC const char *i40e_nvm_update_state_str[] = {
742 "I40E_NVMUPD_INVALID",
743 "I40E_NVMUPD_READ_CON",
744 "I40E_NVMUPD_READ_SNT",
745 "I40E_NVMUPD_READ_LCB",
746 "I40E_NVMUPD_READ_SA",
747 "I40E_NVMUPD_WRITE_ERA",
748 "I40E_NVMUPD_WRITE_CON",
749 "I40E_NVMUPD_WRITE_SNT",
750 "I40E_NVMUPD_WRITE_LCB",
751 "I40E_NVMUPD_WRITE_SA",
752 "I40E_NVMUPD_CSUM_CON",
753 "I40E_NVMUPD_CSUM_SA",
754 "I40E_NVMUPD_CSUM_LCB",
755 "I40E_NVMUPD_STATUS",
756 "I40E_NVMUPD_EXEC_AQ",
757 "I40E_NVMUPD_GET_AQ_RESULT",
761 * i40e_nvmupd_command - Process an NVM update command
762 * @hw: pointer to hardware structure
763 * @cmd: pointer to nvm update command
764 * @bytes: pointer to the data buffer
765 * @perrno: pointer to return error code
767 * Dispatches command depending on what update state is current
769 enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
770 struct i40e_nvm_access *cmd,
771 u8 *bytes, int *perrno)
773 enum i40e_status_code status;
774 enum i40e_nvmupd_cmd upd_cmd;
776 DEBUGFUNC("i40e_nvmupd_command");
781 /* early check for status command and debug msgs */
782 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
784 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n",
785 i40e_nvm_update_state_str[upd_cmd],
787 hw->aq.nvm_release_on_done);
789 if (upd_cmd == I40E_NVMUPD_INVALID) {
791 i40e_debug(hw, I40E_DEBUG_NVM,
792 "i40e_nvmupd_validate_command returns %d errno %d\n",
796 /* a status request returns immediately rather than
797 * going into the state machine
799 if (upd_cmd == I40E_NVMUPD_STATUS) {
800 bytes[0] = hw->nvmupd_state;
804 switch (hw->nvmupd_state) {
805 case I40E_NVMUPD_STATE_INIT:
806 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
809 case I40E_NVMUPD_STATE_READING:
810 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
813 case I40E_NVMUPD_STATE_WRITING:
814 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
817 case I40E_NVMUPD_STATE_INIT_WAIT:
818 case I40E_NVMUPD_STATE_WRITE_WAIT:
819 status = I40E_ERR_NOT_READY;
824 /* invalid state, should never happen */
825 i40e_debug(hw, I40E_DEBUG_NVM,
826 "NVMUPD: no such state %d\n", hw->nvmupd_state);
827 status = I40E_NOT_SUPPORTED;
835 * i40e_nvmupd_state_init - Handle NVM update state Init
836 * @hw: pointer to hardware structure
837 * @cmd: pointer to nvm update command buffer
838 * @bytes: pointer to the data buffer
839 * @perrno: pointer to return error code
841 * Process legitimate commands of the Init state and conditionally set next
842 * state. Reject all other commands.
844 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
845 struct i40e_nvm_access *cmd,
846 u8 *bytes, int *perrno)
848 enum i40e_status_code status = I40E_SUCCESS;
849 enum i40e_nvmupd_cmd upd_cmd;
851 DEBUGFUNC("i40e_nvmupd_state_init");
853 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
856 case I40E_NVMUPD_READ_SA:
857 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
859 *perrno = i40e_aq_rc_to_posix(status,
860 hw->aq.asq_last_status);
862 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
863 i40e_release_nvm(hw);
867 case I40E_NVMUPD_READ_SNT:
868 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
870 *perrno = i40e_aq_rc_to_posix(status,
871 hw->aq.asq_last_status);
873 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
875 i40e_release_nvm(hw);
877 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
881 case I40E_NVMUPD_WRITE_ERA:
882 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
884 *perrno = i40e_aq_rc_to_posix(status,
885 hw->aq.asq_last_status);
887 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
889 i40e_release_nvm(hw);
891 hw->aq.nvm_release_on_done = true;
892 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
897 case I40E_NVMUPD_WRITE_SA:
898 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
900 *perrno = i40e_aq_rc_to_posix(status,
901 hw->aq.asq_last_status);
903 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
905 i40e_release_nvm(hw);
907 hw->aq.nvm_release_on_done = true;
908 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
913 case I40E_NVMUPD_WRITE_SNT:
914 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
916 *perrno = i40e_aq_rc_to_posix(status,
917 hw->aq.asq_last_status);
919 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
921 i40e_release_nvm(hw);
923 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
927 case I40E_NVMUPD_CSUM_SA:
928 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
930 *perrno = i40e_aq_rc_to_posix(status,
931 hw->aq.asq_last_status);
933 status = i40e_update_nvm_checksum(hw);
935 *perrno = hw->aq.asq_last_status ?
936 i40e_aq_rc_to_posix(status,
937 hw->aq.asq_last_status) :
939 i40e_release_nvm(hw);
941 hw->aq.nvm_release_on_done = true;
942 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
947 case I40E_NVMUPD_EXEC_AQ:
948 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
951 case I40E_NVMUPD_GET_AQ_RESULT:
952 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
956 i40e_debug(hw, I40E_DEBUG_NVM,
957 "NVMUPD: bad cmd %s in init state\n",
958 i40e_nvm_update_state_str[upd_cmd]);
959 status = I40E_ERR_NVM;
967 * i40e_nvmupd_state_reading - Handle NVM update state Reading
968 * @hw: pointer to hardware structure
969 * @cmd: pointer to nvm update command buffer
970 * @bytes: pointer to the data buffer
971 * @perrno: pointer to return error code
973 * NVM ownership is already held. Process legitimate commands and set any
974 * change in state; reject all other commands.
976 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
977 struct i40e_nvm_access *cmd,
978 u8 *bytes, int *perrno)
980 enum i40e_status_code status = I40E_SUCCESS;
981 enum i40e_nvmupd_cmd upd_cmd;
983 DEBUGFUNC("i40e_nvmupd_state_reading");
985 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
988 case I40E_NVMUPD_READ_SA:
989 case I40E_NVMUPD_READ_CON:
990 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
993 case I40E_NVMUPD_READ_LCB:
994 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
995 i40e_release_nvm(hw);
996 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1000 i40e_debug(hw, I40E_DEBUG_NVM,
1001 "NVMUPD: bad cmd %s in reading state.\n",
1002 i40e_nvm_update_state_str[upd_cmd]);
1003 status = I40E_NOT_SUPPORTED;
1011 * i40e_nvmupd_state_writing - Handle NVM update state Writing
1012 * @hw: pointer to hardware structure
1013 * @cmd: pointer to nvm update command buffer
1014 * @bytes: pointer to the data buffer
1015 * @perrno: pointer to return error code
1017 * NVM ownership is already held. Process legitimate commands and set any
1018 * change in state; reject all other commands
1020 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
1021 struct i40e_nvm_access *cmd,
1022 u8 *bytes, int *perrno)
1024 enum i40e_status_code status = I40E_SUCCESS;
1025 enum i40e_nvmupd_cmd upd_cmd;
1026 bool retry_attempt = false;
1028 DEBUGFUNC("i40e_nvmupd_state_writing");
1030 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1034 case I40E_NVMUPD_WRITE_CON:
1035 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1037 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1040 case I40E_NVMUPD_WRITE_LCB:
1041 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1043 *perrno = hw->aq.asq_last_status ?
1044 i40e_aq_rc_to_posix(status,
1045 hw->aq.asq_last_status) :
1047 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1049 hw->aq.nvm_release_on_done = true;
1050 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1054 case I40E_NVMUPD_CSUM_CON:
1055 status = i40e_update_nvm_checksum(hw);
1057 *perrno = hw->aq.asq_last_status ?
1058 i40e_aq_rc_to_posix(status,
1059 hw->aq.asq_last_status) :
1061 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1063 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1067 case I40E_NVMUPD_CSUM_LCB:
1068 status = i40e_update_nvm_checksum(hw);
1070 *perrno = hw->aq.asq_last_status ?
1071 i40e_aq_rc_to_posix(status,
1072 hw->aq.asq_last_status) :
1074 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1076 hw->aq.nvm_release_on_done = true;
1077 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1082 i40e_debug(hw, I40E_DEBUG_NVM,
1083 "NVMUPD: bad cmd %s in writing state.\n",
1084 i40e_nvm_update_state_str[upd_cmd]);
1085 status = I40E_NOT_SUPPORTED;
1090 /* In some circumstances, a multi-write transaction takes longer
1091 * than the default 3 minute timeout on the write semaphore. If
1092 * the write failed with an EBUSY status, this is likely the problem,
1093 * so here we try to reacquire the semaphore then retry the write.
1094 * We only do one retry, then give up.
1096 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1098 enum i40e_status_code old_status = status;
1099 u32 old_asq_status = hw->aq.asq_last_status;
1102 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1103 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1104 i40e_debug(hw, I40E_DEBUG_ALL,
1105 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1106 gtime, hw->nvm.hw_semaphore_timeout);
1107 i40e_release_nvm(hw);
1108 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1110 i40e_debug(hw, I40E_DEBUG_ALL,
1111 "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1112 hw->aq.asq_last_status);
1113 status = old_status;
1114 hw->aq.asq_last_status = old_asq_status;
1116 retry_attempt = true;
1126 * i40e_nvmupd_validate_command - Validate given command
1127 * @hw: pointer to hardware structure
1128 * @cmd: pointer to nvm update command buffer
1129 * @perrno: pointer to return error code
1131 * Return one of the valid command types or I40E_NVMUPD_INVALID
1133 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1134 struct i40e_nvm_access *cmd,
1137 enum i40e_nvmupd_cmd upd_cmd;
1138 u8 module, transaction;
1140 DEBUGFUNC("i40e_nvmupd_validate_command\n");
1142 /* anything that doesn't match a recognized case is an error */
1143 upd_cmd = I40E_NVMUPD_INVALID;
1145 transaction = i40e_nvmupd_get_transaction(cmd->config);
1146 module = i40e_nvmupd_get_module(cmd->config);
1148 /* limits on data size */
1149 if ((cmd->data_size < 1) ||
1150 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1151 i40e_debug(hw, I40E_DEBUG_NVM,
1152 "i40e_nvmupd_validate_command data_size %d\n",
1155 return I40E_NVMUPD_INVALID;
1158 switch (cmd->command) {
1160 switch (transaction) {
1162 upd_cmd = I40E_NVMUPD_READ_CON;
1165 upd_cmd = I40E_NVMUPD_READ_SNT;
1168 upd_cmd = I40E_NVMUPD_READ_LCB;
1171 upd_cmd = I40E_NVMUPD_READ_SA;
1175 upd_cmd = I40E_NVMUPD_STATUS;
1176 else if (module == 0)
1177 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1182 case I40E_NVM_WRITE:
1183 switch (transaction) {
1185 upd_cmd = I40E_NVMUPD_WRITE_CON;
1188 upd_cmd = I40E_NVMUPD_WRITE_SNT;
1191 upd_cmd = I40E_NVMUPD_WRITE_LCB;
1194 upd_cmd = I40E_NVMUPD_WRITE_SA;
1197 upd_cmd = I40E_NVMUPD_WRITE_ERA;
1200 upd_cmd = I40E_NVMUPD_CSUM_CON;
1202 case (I40E_NVM_CSUM|I40E_NVM_SA):
1203 upd_cmd = I40E_NVMUPD_CSUM_SA;
1205 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1206 upd_cmd = I40E_NVMUPD_CSUM_LCB;
1210 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1220 * i40e_nvmupd_exec_aq - Run an AQ command
1221 * @hw: pointer to hardware structure
1222 * @cmd: pointer to nvm update command buffer
1223 * @bytes: pointer to the data buffer
1224 * @perrno: pointer to return error code
1226 * cmd structure contains identifiers and data buffer
1228 STATIC enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1229 struct i40e_nvm_access *cmd,
1230 u8 *bytes, int *perrno)
1232 struct i40e_asq_cmd_details cmd_details;
1233 enum i40e_status_code status;
1234 struct i40e_aq_desc *aq_desc;
1240 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1241 memset(&cmd_details, 0, sizeof(cmd_details));
1242 cmd_details.wb_desc = &hw->nvm_wb_desc;
1244 aq_desc_len = sizeof(struct i40e_aq_desc);
1245 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1247 /* get the aq descriptor */
1248 if (cmd->data_size < aq_desc_len) {
1249 i40e_debug(hw, I40E_DEBUG_NVM,
1250 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1251 cmd->data_size, aq_desc_len);
1253 return I40E_ERR_PARAM;
1255 aq_desc = (struct i40e_aq_desc *)bytes;
1257 /* if data buffer needed, make sure it's ready */
1258 aq_data_len = cmd->data_size - aq_desc_len;
1259 buff_size = max(aq_data_len, (u32)LE16_TO_CPU(aq_desc->datalen));
1261 if (!hw->nvm_buff.va) {
1262 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1263 hw->aq.asq_buf_size);
1265 i40e_debug(hw, I40E_DEBUG_NVM,
1266 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1270 if (hw->nvm_buff.va) {
1271 buff = hw->nvm_buff.va;
1272 memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1276 /* and away we go! */
1277 status = i40e_asq_send_command(hw, aq_desc, buff,
1278 buff_size, &cmd_details);
1280 i40e_debug(hw, I40E_DEBUG_NVM,
1281 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1282 i40e_stat_str(hw, status),
1283 i40e_aq_str(hw, hw->aq.asq_last_status));
1284 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1291 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1292 * @hw: pointer to hardware structure
1293 * @cmd: pointer to nvm update command buffer
1294 * @bytes: pointer to the data buffer
1295 * @perrno: pointer to return error code
1297 * cmd structure contains identifiers and data buffer
1299 STATIC enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1300 struct i40e_nvm_access *cmd,
1301 u8 *bytes, int *perrno)
1308 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1310 aq_desc_len = sizeof(struct i40e_aq_desc);
1311 aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_wb_desc.datalen);
1313 /* check offset range */
1314 if (cmd->offset > aq_total_len) {
1315 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1316 __func__, cmd->offset, aq_total_len);
1318 return I40E_ERR_PARAM;
1321 /* check copylength range */
1322 if (cmd->data_size > (aq_total_len - cmd->offset)) {
1323 int new_len = aq_total_len - cmd->offset;
1325 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1326 __func__, cmd->data_size, new_len);
1327 cmd->data_size = new_len;
1330 remainder = cmd->data_size;
1331 if (cmd->offset < aq_desc_len) {
1332 u32 len = aq_desc_len - cmd->offset;
1334 len = min(len, cmd->data_size);
1335 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1336 __func__, cmd->offset, cmd->offset + len);
1338 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1339 memcpy(bytes, buff, len);
1343 buff = hw->nvm_buff.va;
1345 buff = (u8 *)hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1348 if (remainder > 0) {
1349 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1351 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1352 __func__, start_byte, start_byte + remainder);
1353 memcpy(bytes, buff, remainder);
1356 return I40E_SUCCESS;
1360 * i40e_nvmupd_nvm_read - Read NVM
1361 * @hw: pointer to hardware structure
1362 * @cmd: pointer to nvm update command buffer
1363 * @bytes: pointer to the data buffer
1364 * @perrno: pointer to return error code
1366 * cmd structure contains identifiers and data buffer
1368 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1369 struct i40e_nvm_access *cmd,
1370 u8 *bytes, int *perrno)
1372 struct i40e_asq_cmd_details cmd_details;
1373 enum i40e_status_code status;
1374 u8 module, transaction;
1377 transaction = i40e_nvmupd_get_transaction(cmd->config);
1378 module = i40e_nvmupd_get_module(cmd->config);
1379 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1381 memset(&cmd_details, 0, sizeof(cmd_details));
1382 cmd_details.wb_desc = &hw->nvm_wb_desc;
1384 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1385 bytes, last, &cmd_details);
1387 i40e_debug(hw, I40E_DEBUG_NVM,
1388 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
1389 module, cmd->offset, cmd->data_size);
1390 i40e_debug(hw, I40E_DEBUG_NVM,
1391 "i40e_nvmupd_nvm_read status %d aq %d\n",
1392 status, hw->aq.asq_last_status);
1393 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1400 * i40e_nvmupd_nvm_erase - Erase an NVM module
1401 * @hw: pointer to hardware structure
1402 * @cmd: pointer to nvm update command buffer
1403 * @perrno: pointer to return error code
1405 * module, offset, data_size and data are in cmd structure
1407 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1408 struct i40e_nvm_access *cmd,
1411 enum i40e_status_code status = I40E_SUCCESS;
1412 struct i40e_asq_cmd_details cmd_details;
1413 u8 module, transaction;
1416 transaction = i40e_nvmupd_get_transaction(cmd->config);
1417 module = i40e_nvmupd_get_module(cmd->config);
1418 last = (transaction & I40E_NVM_LCB);
1420 memset(&cmd_details, 0, sizeof(cmd_details));
1421 cmd_details.wb_desc = &hw->nvm_wb_desc;
1423 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1424 last, &cmd_details);
1426 i40e_debug(hw, I40E_DEBUG_NVM,
1427 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
1428 module, cmd->offset, cmd->data_size);
1429 i40e_debug(hw, I40E_DEBUG_NVM,
1430 "i40e_nvmupd_nvm_erase status %d aq %d\n",
1431 status, hw->aq.asq_last_status);
1432 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1439 * i40e_nvmupd_nvm_write - Write NVM
1440 * @hw: pointer to hardware structure
1441 * @cmd: pointer to nvm update command buffer
1442 * @bytes: pointer to the data buffer
1443 * @perrno: pointer to return error code
1445 * module, offset, data_size and data are in cmd structure
1447 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1448 struct i40e_nvm_access *cmd,
1449 u8 *bytes, int *perrno)
1451 enum i40e_status_code status = I40E_SUCCESS;
1452 struct i40e_asq_cmd_details cmd_details;
1453 u8 module, transaction;
1456 transaction = i40e_nvmupd_get_transaction(cmd->config);
1457 module = i40e_nvmupd_get_module(cmd->config);
1458 last = (transaction & I40E_NVM_LCB);
1460 memset(&cmd_details, 0, sizeof(cmd_details));
1461 cmd_details.wb_desc = &hw->nvm_wb_desc;
1463 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1464 (u16)cmd->data_size, bytes, last,
1467 i40e_debug(hw, I40E_DEBUG_NVM,
1468 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1469 module, cmd->offset, cmd->data_size);
1470 i40e_debug(hw, I40E_DEBUG_NVM,
1471 "i40e_nvmupd_nvm_write status %d aq %d\n",
1472 status, hw->aq.asq_last_status);
1473 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);