1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_prototype.h"
36 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
38 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
40 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
41 u16 *words, u16 *data);
42 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
43 u16 *words, u16 *data);
44 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
45 u32 offset, u16 words, void *data,
49 * i40e_init_nvm_ops - Initialize NVM function pointers
50 * @hw: pointer to the HW structure
52 * Setup the function pointers and the NVM info structure. Should be called
53 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
54 * Please notice that the NVM term is used here (& in all methods covered
55 * in this file) as an equivalent of the FLASH part mapped into the SR.
56 * We are accessing FLASH always through the Shadow RAM.
58 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
60 struct i40e_nvm_info *nvm = &hw->nvm;
61 enum i40e_status_code ret_code = I40E_SUCCESS;
65 DEBUGFUNC("i40e_init_nvm");
67 /* The SR size is stored regardless of the nvm programming mode
68 * as the blank mode may be used in the factory line.
70 gens = rd32(hw, I40E_GLNVM_GENS);
71 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
72 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
73 /* Switching to words (sr_size contains power of 2KB) */
74 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
76 /* Check if we are in the normal or blank NVM programming mode */
77 fla = rd32(hw, I40E_GLNVM_FLA);
78 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
80 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
81 nvm->blank_nvm_mode = false;
82 } else { /* Blank programming mode */
83 nvm->blank_nvm_mode = true;
84 ret_code = I40E_ERR_NVM_BLANK_MODE;
85 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
92 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
93 * @hw: pointer to the HW structure
94 * @access: NVM access type (read or write)
96 * This function will request NVM ownership for reading
97 * via the proper Admin Command.
99 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
100 enum i40e_aq_resource_access_type access)
102 enum i40e_status_code ret_code = I40E_SUCCESS;
106 DEBUGFUNC("i40e_acquire_nvm");
108 if (hw->nvm.blank_nvm_mode)
109 goto i40e_i40e_acquire_nvm_exit;
111 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
112 0, &time_left, NULL);
113 /* Reading the Global Device Timer */
114 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
116 /* Store the timeout */
117 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
120 i40e_debug(hw, I40E_DEBUG_NVM,
121 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
122 access, time_left, ret_code, hw->aq.asq_last_status);
124 if (ret_code && time_left) {
125 /* Poll until the current NVM owner timeouts */
126 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
127 while ((gtime < timeout) && time_left) {
129 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
130 ret_code = i40e_aq_request_resource(hw,
131 I40E_NVM_RESOURCE_ID,
132 access, 0, &time_left,
134 if (ret_code == I40E_SUCCESS) {
135 hw->nvm.hw_semaphore_timeout =
136 I40E_MS_TO_GTIME(time_left) + gtime;
140 if (ret_code != I40E_SUCCESS) {
141 hw->nvm.hw_semaphore_timeout = 0;
142 i40e_debug(hw, I40E_DEBUG_NVM,
143 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
144 time_left, ret_code, hw->aq.asq_last_status);
148 i40e_i40e_acquire_nvm_exit:
153 * i40e_release_nvm - Generic request for releasing the NVM ownership
154 * @hw: pointer to the HW structure
156 * This function will release NVM resource via the proper Admin Command.
158 void i40e_release_nvm(struct i40e_hw *hw)
160 enum i40e_status_code ret_code = I40E_SUCCESS;
163 DEBUGFUNC("i40e_release_nvm");
165 if (hw->nvm.blank_nvm_mode)
168 ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
170 /* there are some rare cases when trying to release the resource
171 * results in an admin Q timeout, so handle them correctly
173 while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
174 (total_delay < hw->aq.asq_cmd_timeout)) {
176 ret_code = i40e_aq_release_resource(hw,
177 I40E_NVM_RESOURCE_ID, 0, NULL);
183 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
184 * @hw: pointer to the HW structure
186 * Polls the SRCTL Shadow RAM register done bit.
188 static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
190 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
193 DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
195 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
196 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
197 srctl = rd32(hw, I40E_GLNVM_SRCTL);
198 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
199 ret_code = I40E_SUCCESS;
204 if (ret_code == I40E_ERR_TIMEOUT)
205 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
210 * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
211 * @hw: pointer to the HW structure
212 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
213 * @data: word read from the Shadow RAM
215 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
217 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
220 enum i40e_status_code ret_code = I40E_SUCCESS;
222 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
224 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
225 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
227 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
229 i40e_release_nvm(hw);
235 * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking
236 * @hw: pointer to the HW structure
237 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
238 * @data: word read from the Shadow RAM
240 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
242 enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw,
246 enum i40e_status_code ret_code = I40E_SUCCESS;
248 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
249 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
251 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
256 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
257 * @hw: pointer to the HW structure
258 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
259 * @data: word read from the Shadow RAM
261 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
263 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
266 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
269 DEBUGFUNC("i40e_read_nvm_word_srctl");
271 if (offset >= hw->nvm.sr_size) {
272 i40e_debug(hw, I40E_DEBUG_NVM,
273 "NVM read error: Offset %d beyond Shadow RAM limit %d\n",
274 offset, hw->nvm.sr_size);
275 ret_code = I40E_ERR_PARAM;
279 /* Poll the done bit first */
280 ret_code = i40e_poll_sr_srctl_done_bit(hw);
281 if (ret_code == I40E_SUCCESS) {
282 /* Write the address and start reading */
283 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
284 BIT(I40E_GLNVM_SRCTL_START_SHIFT);
285 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
287 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
288 ret_code = i40e_poll_sr_srctl_done_bit(hw);
289 if (ret_code == I40E_SUCCESS) {
290 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
291 *data = (u16)((sr_reg &
292 I40E_GLNVM_SRDATA_RDDATA_MASK)
293 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
296 if (ret_code != I40E_SUCCESS)
297 i40e_debug(hw, I40E_DEBUG_NVM,
298 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
306 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
307 * @hw: pointer to the HW structure
308 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
309 * @data: word read from the Shadow RAM
311 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
313 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
316 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
318 DEBUGFUNC("i40e_read_nvm_word_aq");
320 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
321 *data = LE16_TO_CPU(*(__le16 *)data);
327 * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
328 * @hw: pointer to the HW structure
329 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
330 * @words: (in) number of words to read; (out) number of words actually read
331 * @data: words read from the Shadow RAM
333 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
334 * method. The buffer read is preceded by the NVM ownership take
335 * and followed by the release.
337 enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw,
339 u16 *words, u16 *data)
341 enum i40e_status_code ret_code = I40E_SUCCESS;
343 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
344 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data);
346 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
351 * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acuire lock if necessary
352 * @hw: pointer to the HW structure
353 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
354 * @words: (in) number of words to read; (out) number of words actually read
355 * @data: words read from the Shadow RAM
357 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
358 * method. The buffer read is preceded by the NVM ownership take
359 * and followed by the release.
361 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
362 u16 *words, u16 *data)
364 enum i40e_status_code ret_code = I40E_SUCCESS;
366 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
367 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
369 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
371 i40e_release_nvm(hw);
374 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
380 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
381 * @hw: pointer to the HW structure
382 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
383 * @words: (in) number of words to read; (out) number of words actually read
384 * @data: words read from the Shadow RAM
386 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
387 * method. The buffer read is preceded by the NVM ownership take
388 * and followed by the release.
390 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
391 u16 *words, u16 *data)
393 enum i40e_status_code ret_code = I40E_SUCCESS;
396 DEBUGFUNC("i40e_read_nvm_buffer_srctl");
398 /* Loop through the selected region */
399 for (word = 0; word < *words; word++) {
400 index = offset + word;
401 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
402 if (ret_code != I40E_SUCCESS)
406 /* Update the number of words read from the Shadow RAM */
413 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
414 * @hw: pointer to the HW structure
415 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
416 * @words: (in) number of words to read; (out) number of words actually read
417 * @data: words read from the Shadow RAM
419 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
420 * method. The buffer read is preceded by the NVM ownership take
421 * and followed by the release.
423 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
424 u16 *words, u16 *data)
426 enum i40e_status_code ret_code;
427 u16 read_size = *words;
428 bool last_cmd = false;
432 DEBUGFUNC("i40e_read_nvm_buffer_aq");
435 /* Calculate number of bytes we should read in this step.
436 * FVL AQ do not allow to read more than one page at a time or
437 * to cross page boundaries.
439 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
440 read_size = min(*words,
441 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
442 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
444 read_size = min((*words - words_read),
445 I40E_SR_SECTOR_SIZE_IN_WORDS);
447 /* Check if this is last command, if so set proper flag */
448 if ((words_read + read_size) >= *words)
451 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
452 data + words_read, last_cmd);
453 if (ret_code != I40E_SUCCESS)
454 goto read_nvm_buffer_aq_exit;
456 /* Increment counter for words already read and move offset to
459 words_read += read_size;
461 } while (words_read < *words);
463 for (i = 0; i < *words; i++)
464 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
466 read_nvm_buffer_aq_exit:
472 * i40e_read_nvm_aq - Read Shadow RAM.
473 * @hw: pointer to the HW structure.
474 * @module_pointer: module pointer location in words from the NVM beginning
475 * @offset: offset in words from module start
476 * @words: number of words to write
477 * @data: buffer with words to write to the Shadow RAM
478 * @last_command: tells the AdminQ that this is the last command
480 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
482 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
483 u32 offset, u16 words, void *data,
486 enum i40e_status_code ret_code = I40E_ERR_NVM;
487 struct i40e_asq_cmd_details cmd_details;
489 DEBUGFUNC("i40e_read_nvm_aq");
491 memset(&cmd_details, 0, sizeof(cmd_details));
492 cmd_details.wb_desc = &hw->nvm_wb_desc;
494 /* Here we are checking the SR limit only for the flat memory model.
495 * We cannot do it for the module-based model, as we did not acquire
496 * the NVM resource yet (we cannot get the module pointer value).
497 * Firmware will check the module-based model.
499 if ((offset + words) > hw->nvm.sr_size)
500 i40e_debug(hw, I40E_DEBUG_NVM,
501 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
502 (offset + words), hw->nvm.sr_size);
503 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
504 /* We can write only up to 4KB (one sector), in one AQ write */
505 i40e_debug(hw, I40E_DEBUG_NVM,
506 "NVM write fail error: tried to write %d words, limit is %d.\n",
507 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
508 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
509 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
510 /* A single write cannot spread over two sectors */
511 i40e_debug(hw, I40E_DEBUG_NVM,
512 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
515 ret_code = i40e_aq_read_nvm(hw, module_pointer,
516 2 * offset, /*bytes*/
518 data, last_command, &cmd_details);
524 * i40e_write_nvm_aq - Writes Shadow RAM.
525 * @hw: pointer to the HW structure.
526 * @module_pointer: module pointer location in words from the NVM beginning
527 * @offset: offset in words from module start
528 * @words: number of words to write
529 * @data: buffer with words to write to the Shadow RAM
530 * @last_command: tells the AdminQ that this is the last command
532 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
534 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
535 u32 offset, u16 words, void *data,
538 enum i40e_status_code ret_code = I40E_ERR_NVM;
539 struct i40e_asq_cmd_details cmd_details;
541 DEBUGFUNC("i40e_write_nvm_aq");
543 memset(&cmd_details, 0, sizeof(cmd_details));
544 cmd_details.wb_desc = &hw->nvm_wb_desc;
546 /* Here we are checking the SR limit only for the flat memory model.
547 * We cannot do it for the module-based model, as we did not acquire
548 * the NVM resource yet (we cannot get the module pointer value).
549 * Firmware will check the module-based model.
551 if ((offset + words) > hw->nvm.sr_size)
552 DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
553 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
554 /* We can write only up to 4KB (one sector), in one AQ write */
555 DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
556 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
557 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
558 /* A single write cannot spread over two sectors */
559 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
561 ret_code = i40e_aq_update_nvm(hw, module_pointer,
562 2 * offset, /*bytes*/
564 data, last_command, &cmd_details);
570 * __i40e_write_nvm_word - Writes Shadow RAM word
571 * @hw: pointer to the HW structure
572 * @offset: offset of the Shadow RAM word to write
573 * @data: word to write to the Shadow RAM
575 * Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
576 * NVM ownership have to be acquired and released (on ARQ completion event
577 * reception) by caller. To commit SR to NVM update checksum function
580 enum i40e_status_code __i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
583 DEBUGFUNC("i40e_write_nvm_word");
585 *((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));
587 /* Value 0x00 below means that we treat SR as a flat mem */
588 return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);
592 * __i40e_write_nvm_buffer - Writes Shadow RAM buffer
593 * @hw: pointer to the HW structure
594 * @module_pointer: module pointer location in words from the NVM beginning
595 * @offset: offset of the Shadow RAM buffer to write
596 * @words: number of words to write
597 * @data: words to write to the Shadow RAM
599 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
600 * NVM ownership must be acquired before calling this function and released
601 * on ARQ completion event reception by caller. To commit SR to NVM update
602 * checksum function should be called.
604 enum i40e_status_code __i40e_write_nvm_buffer(struct i40e_hw *hw,
605 u8 module_pointer, u32 offset,
606 u16 words, void *data)
608 __le16 *le_word_ptr = (__le16 *)data;
609 u16 *word_ptr = (u16 *)data;
612 DEBUGFUNC("i40e_write_nvm_buffer");
614 for (i = 0; i < words; i++)
615 le_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);
617 /* Here we will only write one buffer as the size of the modules
618 * mirrored in the Shadow RAM is always less than 4K.
620 return i40e_write_nvm_aq(hw, module_pointer, offset, words,
625 * i40e_calc_nvm_checksum - Calculates and returns the checksum
626 * @hw: pointer to hardware structure
627 * @checksum: pointer to the checksum
629 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
630 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
631 * is customer specific and unknown. Therefore, this function skips all maximum
632 * possible size of VPD (1kB).
634 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
636 enum i40e_status_code ret_code = I40E_SUCCESS;
637 struct i40e_virt_mem vmem;
638 u16 pcie_alt_module = 0;
639 u16 checksum_local = 0;
644 DEBUGFUNC("i40e_calc_nvm_checksum");
646 ret_code = i40e_allocate_virt_mem(hw, &vmem,
647 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
649 goto i40e_calc_nvm_checksum_exit;
650 data = (u16 *)vmem.va;
652 /* read pointer to VPD area */
653 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR,
655 if (ret_code != I40E_SUCCESS) {
656 ret_code = I40E_ERR_NVM_CHECKSUM;
657 goto i40e_calc_nvm_checksum_exit;
660 /* read pointer to PCIe Alt Auto-load module */
661 ret_code = __i40e_read_nvm_word(hw,
662 I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
664 if (ret_code != I40E_SUCCESS) {
665 ret_code = I40E_ERR_NVM_CHECKSUM;
666 goto i40e_calc_nvm_checksum_exit;
669 /* Calculate SW checksum that covers the whole 64kB shadow RAM
670 * except the VPD and PCIe ALT Auto-load modules
672 for (i = 0; i < hw->nvm.sr_size; i++) {
674 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
675 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
677 ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
678 if (ret_code != I40E_SUCCESS) {
679 ret_code = I40E_ERR_NVM_CHECKSUM;
680 goto i40e_calc_nvm_checksum_exit;
684 /* Skip Checksum word */
685 if (i == I40E_SR_SW_CHECKSUM_WORD)
687 /* Skip VPD module (convert byte size to word count) */
688 if ((i >= (u32)vpd_module) &&
689 (i < ((u32)vpd_module +
690 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
693 /* Skip PCIe ALT module (convert byte size to word count) */
694 if ((i >= (u32)pcie_alt_module) &&
695 (i < ((u32)pcie_alt_module +
696 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
700 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
703 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
705 i40e_calc_nvm_checksum_exit:
706 i40e_free_virt_mem(hw, &vmem);
711 * i40e_update_nvm_checksum - Updates the NVM checksum
712 * @hw: pointer to hardware structure
714 * NVM ownership must be acquired before calling this function and released
715 * on ARQ completion event reception by caller.
716 * This function will commit SR to NVM.
718 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
720 enum i40e_status_code ret_code = I40E_SUCCESS;
724 DEBUGFUNC("i40e_update_nvm_checksum");
726 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
727 le_sum = CPU_TO_LE16(checksum);
728 if (ret_code == I40E_SUCCESS)
729 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
736 * i40e_validate_nvm_checksum - Validate EEPROM checksum
737 * @hw: pointer to hardware structure
738 * @checksum: calculated checksum
740 * Performs checksum calculation and validates the NVM SW checksum. If the
741 * caller does not need checksum, the value can be NULL.
743 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
746 enum i40e_status_code ret_code = I40E_SUCCESS;
748 u16 checksum_local = 0;
750 DEBUGFUNC("i40e_validate_nvm_checksum");
752 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
753 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
755 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
756 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
757 i40e_release_nvm(hw);
758 if (ret_code != I40E_SUCCESS)
759 goto i40e_validate_nvm_checksum_exit;
761 goto i40e_validate_nvm_checksum_exit;
764 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
766 /* Verify read checksum from EEPROM is the same as
767 * calculated checksum
769 if (checksum_local != checksum_sr)
770 ret_code = I40E_ERR_NVM_CHECKSUM;
772 /* If the user cares, return the calculated checksum */
774 *checksum = checksum_local;
776 i40e_validate_nvm_checksum_exit:
780 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
781 struct i40e_nvm_access *cmd,
782 u8 *bytes, int *perrno);
783 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
784 struct i40e_nvm_access *cmd,
785 u8 *bytes, int *perrno);
786 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
787 struct i40e_nvm_access *cmd,
788 u8 *bytes, int *perrno);
789 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
790 struct i40e_nvm_access *cmd,
792 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
793 struct i40e_nvm_access *cmd,
795 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
796 struct i40e_nvm_access *cmd,
797 u8 *bytes, int *perrno);
798 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
799 struct i40e_nvm_access *cmd,
800 u8 *bytes, int *perrno);
801 STATIC enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
802 struct i40e_nvm_access *cmd,
803 u8 *bytes, int *perrno);
804 STATIC enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
805 struct i40e_nvm_access *cmd,
806 u8 *bytes, int *perrno);
807 STATIC INLINE u8 i40e_nvmupd_get_module(u32 val)
809 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
811 STATIC INLINE u8 i40e_nvmupd_get_transaction(u32 val)
813 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
816 STATIC const char *i40e_nvm_update_state_str[] = {
817 "I40E_NVMUPD_INVALID",
818 "I40E_NVMUPD_READ_CON",
819 "I40E_NVMUPD_READ_SNT",
820 "I40E_NVMUPD_READ_LCB",
821 "I40E_NVMUPD_READ_SA",
822 "I40E_NVMUPD_WRITE_ERA",
823 "I40E_NVMUPD_WRITE_CON",
824 "I40E_NVMUPD_WRITE_SNT",
825 "I40E_NVMUPD_WRITE_LCB",
826 "I40E_NVMUPD_WRITE_SA",
827 "I40E_NVMUPD_CSUM_CON",
828 "I40E_NVMUPD_CSUM_SA",
829 "I40E_NVMUPD_CSUM_LCB",
830 "I40E_NVMUPD_STATUS",
831 "I40E_NVMUPD_EXEC_AQ",
832 "I40E_NVMUPD_GET_AQ_RESULT",
836 * i40e_nvmupd_command - Process an NVM update command
837 * @hw: pointer to hardware structure
838 * @cmd: pointer to nvm update command
839 * @bytes: pointer to the data buffer
840 * @perrno: pointer to return error code
842 * Dispatches command depending on what update state is current
844 enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
845 struct i40e_nvm_access *cmd,
846 u8 *bytes, int *perrno)
848 enum i40e_status_code status;
849 enum i40e_nvmupd_cmd upd_cmd;
851 DEBUGFUNC("i40e_nvmupd_command");
856 /* early check for status command and debug msgs */
857 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
859 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
860 i40e_nvm_update_state_str[upd_cmd],
862 hw->nvm_release_on_done, hw->nvm_wait_opcode,
863 cmd->command, cmd->config, cmd->offset, cmd->data_size);
865 if (upd_cmd == I40E_NVMUPD_INVALID) {
867 i40e_debug(hw, I40E_DEBUG_NVM,
868 "i40e_nvmupd_validate_command returns %d errno %d\n",
872 /* a status request returns immediately rather than
873 * going into the state machine
875 if (upd_cmd == I40E_NVMUPD_STATUS) {
876 if (!cmd->data_size) {
878 return I40E_ERR_BUF_TOO_SHORT;
881 bytes[0] = hw->nvmupd_state;
883 if (cmd->data_size >= 4) {
885 *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
888 /* Clear error status on read */
889 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
890 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
895 /* Clear status even it is not read and log */
896 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
897 i40e_debug(hw, I40E_DEBUG_NVM,
898 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
899 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
902 /* Acquire lock to prevent race condition where adminq_task
903 * can execute after i40e_nvmupd_nvm_read/write but before state
904 * variables (nvm_wait_opcode, nvm_release_on_done) are updated
906 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
907 switch (hw->nvmupd_state) {
908 case I40E_NVMUPD_STATE_INIT:
909 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
912 case I40E_NVMUPD_STATE_READING:
913 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
916 case I40E_NVMUPD_STATE_WRITING:
917 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
920 case I40E_NVMUPD_STATE_INIT_WAIT:
921 case I40E_NVMUPD_STATE_WRITE_WAIT:
922 /* if we need to stop waiting for an event, clear
923 * the wait info and return before doing anything else
925 if (cmd->offset == 0xffff) {
926 i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode);
930 status = I40E_ERR_NOT_READY;
935 /* invalid state, should never happen */
936 i40e_debug(hw, I40E_DEBUG_NVM,
937 "NVMUPD: no such state %d\n", hw->nvmupd_state);
938 status = I40E_NOT_SUPPORTED;
942 i40e_release_spinlock(&hw->aq.arq_spinlock);
947 * i40e_nvmupd_state_init - Handle NVM update state Init
948 * @hw: pointer to hardware structure
949 * @cmd: pointer to nvm update command buffer
950 * @bytes: pointer to the data buffer
951 * @perrno: pointer to return error code
953 * Process legitimate commands of the Init state and conditionally set next
954 * state. Reject all other commands.
956 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
957 struct i40e_nvm_access *cmd,
958 u8 *bytes, int *perrno)
960 enum i40e_status_code status = I40E_SUCCESS;
961 enum i40e_nvmupd_cmd upd_cmd;
963 DEBUGFUNC("i40e_nvmupd_state_init");
965 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
968 case I40E_NVMUPD_READ_SA:
969 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
971 *perrno = i40e_aq_rc_to_posix(status,
972 hw->aq.asq_last_status);
974 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
975 i40e_release_nvm(hw);
979 case I40E_NVMUPD_READ_SNT:
980 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
982 *perrno = i40e_aq_rc_to_posix(status,
983 hw->aq.asq_last_status);
985 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
987 i40e_release_nvm(hw);
989 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
993 case I40E_NVMUPD_WRITE_ERA:
994 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
996 *perrno = i40e_aq_rc_to_posix(status,
997 hw->aq.asq_last_status);
999 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
1001 i40e_release_nvm(hw);
1003 hw->nvm_release_on_done = true;
1004 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
1005 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1010 case I40E_NVMUPD_WRITE_SA:
1011 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1013 *perrno = i40e_aq_rc_to_posix(status,
1014 hw->aq.asq_last_status);
1016 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1018 i40e_release_nvm(hw);
1020 hw->nvm_release_on_done = true;
1021 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1022 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1027 case I40E_NVMUPD_WRITE_SNT:
1028 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1030 *perrno = i40e_aq_rc_to_posix(status,
1031 hw->aq.asq_last_status);
1033 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1035 i40e_release_nvm(hw);
1037 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1038 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1043 case I40E_NVMUPD_CSUM_SA:
1044 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1046 *perrno = i40e_aq_rc_to_posix(status,
1047 hw->aq.asq_last_status);
1049 status = i40e_update_nvm_checksum(hw);
1051 *perrno = hw->aq.asq_last_status ?
1052 i40e_aq_rc_to_posix(status,
1053 hw->aq.asq_last_status) :
1055 i40e_release_nvm(hw);
1057 hw->nvm_release_on_done = true;
1058 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1059 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1064 case I40E_NVMUPD_EXEC_AQ:
1065 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
1068 case I40E_NVMUPD_GET_AQ_RESULT:
1069 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
1073 i40e_debug(hw, I40E_DEBUG_NVM,
1074 "NVMUPD: bad cmd %s in init state\n",
1075 i40e_nvm_update_state_str[upd_cmd]);
1076 status = I40E_ERR_NVM;
1084 * i40e_nvmupd_state_reading - Handle NVM update state Reading
1085 * @hw: pointer to hardware structure
1086 * @cmd: pointer to nvm update command buffer
1087 * @bytes: pointer to the data buffer
1088 * @perrno: pointer to return error code
1090 * NVM ownership is already held. Process legitimate commands and set any
1091 * change in state; reject all other commands.
1093 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
1094 struct i40e_nvm_access *cmd,
1095 u8 *bytes, int *perrno)
1097 enum i40e_status_code status = I40E_SUCCESS;
1098 enum i40e_nvmupd_cmd upd_cmd;
1100 DEBUGFUNC("i40e_nvmupd_state_reading");
1102 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1105 case I40E_NVMUPD_READ_SA:
1106 case I40E_NVMUPD_READ_CON:
1107 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
1110 case I40E_NVMUPD_READ_LCB:
1111 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
1112 i40e_release_nvm(hw);
1113 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1117 i40e_debug(hw, I40E_DEBUG_NVM,
1118 "NVMUPD: bad cmd %s in reading state.\n",
1119 i40e_nvm_update_state_str[upd_cmd]);
1120 status = I40E_NOT_SUPPORTED;
1128 * i40e_nvmupd_state_writing - Handle NVM update state Writing
1129 * @hw: pointer to hardware structure
1130 * @cmd: pointer to nvm update command buffer
1131 * @bytes: pointer to the data buffer
1132 * @perrno: pointer to return error code
1134 * NVM ownership is already held. Process legitimate commands and set any
1135 * change in state; reject all other commands
1137 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
1138 struct i40e_nvm_access *cmd,
1139 u8 *bytes, int *perrno)
1141 enum i40e_status_code status = I40E_SUCCESS;
1142 enum i40e_nvmupd_cmd upd_cmd;
1143 bool retry_attempt = false;
1145 DEBUGFUNC("i40e_nvmupd_state_writing");
1147 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1151 case I40E_NVMUPD_WRITE_CON:
1152 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1154 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1155 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1159 case I40E_NVMUPD_WRITE_LCB:
1160 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1162 *perrno = hw->aq.asq_last_status ?
1163 i40e_aq_rc_to_posix(status,
1164 hw->aq.asq_last_status) :
1166 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1168 hw->nvm_release_on_done = true;
1169 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1170 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1174 case I40E_NVMUPD_CSUM_CON:
1175 /* Assumes the caller has acquired the nvm */
1176 status = i40e_update_nvm_checksum(hw);
1178 *perrno = hw->aq.asq_last_status ?
1179 i40e_aq_rc_to_posix(status,
1180 hw->aq.asq_last_status) :
1182 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1184 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1185 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1189 case I40E_NVMUPD_CSUM_LCB:
1190 /* Assumes the caller has acquired the nvm */
1191 status = i40e_update_nvm_checksum(hw);
1193 *perrno = hw->aq.asq_last_status ?
1194 i40e_aq_rc_to_posix(status,
1195 hw->aq.asq_last_status) :
1197 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1199 hw->nvm_release_on_done = true;
1200 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1201 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1206 i40e_debug(hw, I40E_DEBUG_NVM,
1207 "NVMUPD: bad cmd %s in writing state.\n",
1208 i40e_nvm_update_state_str[upd_cmd]);
1209 status = I40E_NOT_SUPPORTED;
1214 /* In some circumstances, a multi-write transaction takes longer
1215 * than the default 3 minute timeout on the write semaphore. If
1216 * the write failed with an EBUSY status, this is likely the problem,
1217 * so here we try to reacquire the semaphore then retry the write.
1218 * We only do one retry, then give up.
1220 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1222 enum i40e_status_code old_status = status;
1223 u32 old_asq_status = hw->aq.asq_last_status;
1226 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1227 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1228 i40e_debug(hw, I40E_DEBUG_ALL,
1229 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1230 gtime, hw->nvm.hw_semaphore_timeout);
1231 i40e_release_nvm(hw);
1232 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1234 i40e_debug(hw, I40E_DEBUG_ALL,
1235 "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1236 hw->aq.asq_last_status);
1237 status = old_status;
1238 hw->aq.asq_last_status = old_asq_status;
1240 retry_attempt = true;
1250 * i40e_nvmupd_check_wait_event - handle NVM update operation events
1251 * @hw: pointer to the hardware structure
1252 * @opcode: the event that just happened
1254 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
1256 if (opcode == hw->nvm_wait_opcode) {
1258 i40e_debug(hw, I40E_DEBUG_NVM,
1259 "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
1260 if (hw->nvm_release_on_done) {
1261 i40e_release_nvm(hw);
1262 hw->nvm_release_on_done = false;
1264 hw->nvm_wait_opcode = 0;
1266 if (hw->aq.arq_last_status) {
1267 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
1271 switch (hw->nvmupd_state) {
1272 case I40E_NVMUPD_STATE_INIT_WAIT:
1273 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1276 case I40E_NVMUPD_STATE_WRITE_WAIT:
1277 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1287 * i40e_nvmupd_validate_command - Validate given command
1288 * @hw: pointer to hardware structure
1289 * @cmd: pointer to nvm update command buffer
1290 * @perrno: pointer to return error code
1292 * Return one of the valid command types or I40E_NVMUPD_INVALID
1294 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1295 struct i40e_nvm_access *cmd,
1298 enum i40e_nvmupd_cmd upd_cmd;
1299 u8 module, transaction;
1301 DEBUGFUNC("i40e_nvmupd_validate_command\n");
1303 /* anything that doesn't match a recognized case is an error */
1304 upd_cmd = I40E_NVMUPD_INVALID;
1306 transaction = i40e_nvmupd_get_transaction(cmd->config);
1307 module = i40e_nvmupd_get_module(cmd->config);
1309 /* limits on data size */
1310 if ((cmd->data_size < 1) ||
1311 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1312 i40e_debug(hw, I40E_DEBUG_NVM,
1313 "i40e_nvmupd_validate_command data_size %d\n",
1316 return I40E_NVMUPD_INVALID;
1319 switch (cmd->command) {
1321 switch (transaction) {
1323 upd_cmd = I40E_NVMUPD_READ_CON;
1326 upd_cmd = I40E_NVMUPD_READ_SNT;
1329 upd_cmd = I40E_NVMUPD_READ_LCB;
1332 upd_cmd = I40E_NVMUPD_READ_SA;
1336 upd_cmd = I40E_NVMUPD_STATUS;
1337 else if (module == 0)
1338 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1343 case I40E_NVM_WRITE:
1344 switch (transaction) {
1346 upd_cmd = I40E_NVMUPD_WRITE_CON;
1349 upd_cmd = I40E_NVMUPD_WRITE_SNT;
1352 upd_cmd = I40E_NVMUPD_WRITE_LCB;
1355 upd_cmd = I40E_NVMUPD_WRITE_SA;
1358 upd_cmd = I40E_NVMUPD_WRITE_ERA;
1361 upd_cmd = I40E_NVMUPD_CSUM_CON;
1363 case (I40E_NVM_CSUM|I40E_NVM_SA):
1364 upd_cmd = I40E_NVMUPD_CSUM_SA;
1366 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1367 upd_cmd = I40E_NVMUPD_CSUM_LCB;
1371 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1381 * i40e_nvmupd_exec_aq - Run an AQ command
1382 * @hw: pointer to hardware structure
1383 * @cmd: pointer to nvm update command buffer
1384 * @bytes: pointer to the data buffer
1385 * @perrno: pointer to return error code
1387 * cmd structure contains identifiers and data buffer
1389 STATIC enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1390 struct i40e_nvm_access *cmd,
1391 u8 *bytes, int *perrno)
1393 struct i40e_asq_cmd_details cmd_details;
1394 enum i40e_status_code status;
1395 struct i40e_aq_desc *aq_desc;
1401 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1402 memset(&cmd_details, 0, sizeof(cmd_details));
1403 cmd_details.wb_desc = &hw->nvm_wb_desc;
1405 aq_desc_len = sizeof(struct i40e_aq_desc);
1406 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1408 /* get the aq descriptor */
1409 if (cmd->data_size < aq_desc_len) {
1410 i40e_debug(hw, I40E_DEBUG_NVM,
1411 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1412 cmd->data_size, aq_desc_len);
1414 return I40E_ERR_PARAM;
1416 aq_desc = (struct i40e_aq_desc *)bytes;
1418 /* if data buffer needed, make sure it's ready */
1419 aq_data_len = cmd->data_size - aq_desc_len;
1420 buff_size = max(aq_data_len, (u32)LE16_TO_CPU(aq_desc->datalen));
1422 if (!hw->nvm_buff.va) {
1423 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1424 hw->aq.asq_buf_size);
1426 i40e_debug(hw, I40E_DEBUG_NVM,
1427 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1431 if (hw->nvm_buff.va) {
1432 buff = hw->nvm_buff.va;
1433 i40e_memcpy(buff, &bytes[aq_desc_len], aq_data_len,
1434 I40E_NONDMA_TO_NONDMA);
1438 /* and away we go! */
1439 status = i40e_asq_send_command(hw, aq_desc, buff,
1440 buff_size, &cmd_details);
1442 i40e_debug(hw, I40E_DEBUG_NVM,
1443 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1444 i40e_stat_str(hw, status),
1445 i40e_aq_str(hw, hw->aq.asq_last_status));
1446 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1449 /* should we wait for a followup event? */
1451 hw->nvm_wait_opcode = cmd->offset;
1452 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1459 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1460 * @hw: pointer to hardware structure
1461 * @cmd: pointer to nvm update command buffer
1462 * @bytes: pointer to the data buffer
1463 * @perrno: pointer to return error code
1465 * cmd structure contains identifiers and data buffer
1467 STATIC enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1468 struct i40e_nvm_access *cmd,
1469 u8 *bytes, int *perrno)
1476 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1478 aq_desc_len = sizeof(struct i40e_aq_desc);
1479 aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_wb_desc.datalen);
1481 /* check offset range */
1482 if (cmd->offset > aq_total_len) {
1483 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1484 __func__, cmd->offset, aq_total_len);
1486 return I40E_ERR_PARAM;
1489 /* check copylength range */
1490 if (cmd->data_size > (aq_total_len - cmd->offset)) {
1491 int new_len = aq_total_len - cmd->offset;
1493 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1494 __func__, cmd->data_size, new_len);
1495 cmd->data_size = new_len;
1498 remainder = cmd->data_size;
1499 if (cmd->offset < aq_desc_len) {
1500 u32 len = aq_desc_len - cmd->offset;
1502 len = min(len, cmd->data_size);
1503 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1504 __func__, cmd->offset, cmd->offset + len);
1506 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1507 i40e_memcpy(bytes, buff, len, I40E_NONDMA_TO_NONDMA);
1511 buff = hw->nvm_buff.va;
1513 buff = (u8 *)hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1516 if (remainder > 0) {
1517 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1519 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1520 __func__, start_byte, start_byte + remainder);
1521 i40e_memcpy(bytes, buff, remainder, I40E_NONDMA_TO_NONDMA);
1524 return I40E_SUCCESS;
1528 * i40e_nvmupd_nvm_read - Read NVM
1529 * @hw: pointer to hardware structure
1530 * @cmd: pointer to nvm update command buffer
1531 * @bytes: pointer to the data buffer
1532 * @perrno: pointer to return error code
1534 * cmd structure contains identifiers and data buffer
1536 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1537 struct i40e_nvm_access *cmd,
1538 u8 *bytes, int *perrno)
1540 struct i40e_asq_cmd_details cmd_details;
1541 enum i40e_status_code status;
1542 u8 module, transaction;
1545 transaction = i40e_nvmupd_get_transaction(cmd->config);
1546 module = i40e_nvmupd_get_module(cmd->config);
1547 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1549 memset(&cmd_details, 0, sizeof(cmd_details));
1550 cmd_details.wb_desc = &hw->nvm_wb_desc;
1552 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1553 bytes, last, &cmd_details);
1555 i40e_debug(hw, I40E_DEBUG_NVM,
1556 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
1557 module, cmd->offset, cmd->data_size);
1558 i40e_debug(hw, I40E_DEBUG_NVM,
1559 "i40e_nvmupd_nvm_read status %d aq %d\n",
1560 status, hw->aq.asq_last_status);
1561 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1568 * i40e_nvmupd_nvm_erase - Erase an NVM module
1569 * @hw: pointer to hardware structure
1570 * @cmd: pointer to nvm update command buffer
1571 * @perrno: pointer to return error code
1573 * module, offset, data_size and data are in cmd structure
1575 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1576 struct i40e_nvm_access *cmd,
1579 enum i40e_status_code status = I40E_SUCCESS;
1580 struct i40e_asq_cmd_details cmd_details;
1581 u8 module, transaction;
1584 transaction = i40e_nvmupd_get_transaction(cmd->config);
1585 module = i40e_nvmupd_get_module(cmd->config);
1586 last = (transaction & I40E_NVM_LCB);
1588 memset(&cmd_details, 0, sizeof(cmd_details));
1589 cmd_details.wb_desc = &hw->nvm_wb_desc;
1591 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1592 last, &cmd_details);
1594 i40e_debug(hw, I40E_DEBUG_NVM,
1595 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
1596 module, cmd->offset, cmd->data_size);
1597 i40e_debug(hw, I40E_DEBUG_NVM,
1598 "i40e_nvmupd_nvm_erase status %d aq %d\n",
1599 status, hw->aq.asq_last_status);
1600 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1607 * i40e_nvmupd_nvm_write - Write NVM
1608 * @hw: pointer to hardware structure
1609 * @cmd: pointer to nvm update command buffer
1610 * @bytes: pointer to the data buffer
1611 * @perrno: pointer to return error code
1613 * module, offset, data_size and data are in cmd structure
1615 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1616 struct i40e_nvm_access *cmd,
1617 u8 *bytes, int *perrno)
1619 enum i40e_status_code status = I40E_SUCCESS;
1620 struct i40e_asq_cmd_details cmd_details;
1621 u8 module, transaction;
1624 transaction = i40e_nvmupd_get_transaction(cmd->config);
1625 module = i40e_nvmupd_get_module(cmd->config);
1626 last = (transaction & I40E_NVM_LCB);
1628 memset(&cmd_details, 0, sizeof(cmd_details));
1629 cmd_details.wb_desc = &hw->nvm_wb_desc;
1631 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1632 (u16)cmd->data_size, bytes, last,
1635 i40e_debug(hw, I40E_DEBUG_NVM,
1636 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1637 module, cmd->offset, cmd->data_size);
1638 i40e_debug(hw, I40E_DEBUG_NVM,
1639 "i40e_nvmupd_nvm_write status %d aq %d\n",
1640 status, hw->aq.asq_last_status);
1641 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);