1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_prototype.h"
36 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
38 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
40 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
41 u16 *words, u16 *data);
42 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
43 u16 *words, u16 *data);
44 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
45 u32 offset, u16 words, void *data,
49 * i40e_init_nvm_ops - Initialize NVM function pointers
50 * @hw: pointer to the HW structure
52 * Setup the function pointers and the NVM info structure. Should be called
53 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
54 * Please notice that the NVM term is used here (& in all methods covered
55 * in this file) as an equivalent of the FLASH part mapped into the SR.
56 * We are accessing FLASH always thru the Shadow RAM.
58 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
60 struct i40e_nvm_info *nvm = &hw->nvm;
61 enum i40e_status_code ret_code = I40E_SUCCESS;
65 DEBUGFUNC("i40e_init_nvm");
67 /* The SR size is stored regardless of the nvm programming mode
68 * as the blank mode may be used in the factory line.
70 gens = rd32(hw, I40E_GLNVM_GENS);
71 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
72 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
73 /* Switching to words (sr_size contains power of 2KB) */
74 nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
76 /* Check if we are in the normal or blank NVM programming mode */
77 fla = rd32(hw, I40E_GLNVM_FLA);
78 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
80 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
81 nvm->blank_nvm_mode = false;
82 } else { /* Blank programming mode */
83 nvm->blank_nvm_mode = true;
84 ret_code = I40E_ERR_NVM_BLANK_MODE;
85 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
92 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
93 * @hw: pointer to the HW structure
94 * @access: NVM access type (read or write)
96 * This function will request NVM ownership for reading
97 * via the proper Admin Command.
99 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
100 enum i40e_aq_resource_access_type access)
102 enum i40e_status_code ret_code = I40E_SUCCESS;
106 DEBUGFUNC("i40e_acquire_nvm");
108 if (hw->nvm.blank_nvm_mode)
109 goto i40e_i40e_acquire_nvm_exit;
111 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
112 0, &time_left, NULL);
113 /* Reading the Global Device Timer */
114 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
116 /* Store the timeout */
117 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
120 i40e_debug(hw, I40E_DEBUG_NVM,
121 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
122 access, time_left, ret_code, hw->aq.asq_last_status);
124 if (ret_code && time_left) {
125 /* Poll until the current NVM owner timeouts */
126 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
127 while ((gtime < timeout) && time_left) {
129 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
130 ret_code = i40e_aq_request_resource(hw,
131 I40E_NVM_RESOURCE_ID,
132 access, 0, &time_left,
134 if (ret_code == I40E_SUCCESS) {
135 hw->nvm.hw_semaphore_timeout =
136 I40E_MS_TO_GTIME(time_left) + gtime;
140 if (ret_code != I40E_SUCCESS) {
141 hw->nvm.hw_semaphore_timeout = 0;
142 i40e_debug(hw, I40E_DEBUG_NVM,
143 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
144 time_left, ret_code, hw->aq.asq_last_status);
148 i40e_i40e_acquire_nvm_exit:
153 * i40e_release_nvm - Generic request for releasing the NVM ownership
154 * @hw: pointer to the HW structure
156 * This function will release NVM resource via the proper Admin Command.
158 void i40e_release_nvm(struct i40e_hw *hw)
160 DEBUGFUNC("i40e_release_nvm");
162 if (!hw->nvm.blank_nvm_mode)
163 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
167 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
168 * @hw: pointer to the HW structure
170 * Polls the SRCTL Shadow RAM register done bit.
172 static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
174 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
177 DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
179 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
180 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
181 srctl = rd32(hw, I40E_GLNVM_SRCTL);
182 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
183 ret_code = I40E_SUCCESS;
188 if (ret_code == I40E_ERR_TIMEOUT)
189 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
194 * i40e_read_nvm_word - Reads Shadow RAM
195 * @hw: pointer to the HW structure
196 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
197 * @data: word read from the Shadow RAM
199 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
201 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
204 return i40e_read_nvm_word_srctl(hw, offset, data);
208 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
209 * @hw: pointer to the HW structure
210 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
211 * @data: word read from the Shadow RAM
213 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
215 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
218 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
221 DEBUGFUNC("i40e_read_nvm_word_srctl");
223 if (offset >= hw->nvm.sr_size) {
224 i40e_debug(hw, I40E_DEBUG_NVM,
225 "NVM read error: Offset %d beyond Shadow RAM limit %d\n",
226 offset, hw->nvm.sr_size);
227 ret_code = I40E_ERR_PARAM;
231 /* Poll the done bit first */
232 ret_code = i40e_poll_sr_srctl_done_bit(hw);
233 if (ret_code == I40E_SUCCESS) {
234 /* Write the address and start reading */
235 sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
236 (1 << I40E_GLNVM_SRCTL_START_SHIFT);
237 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
239 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
240 ret_code = i40e_poll_sr_srctl_done_bit(hw);
241 if (ret_code == I40E_SUCCESS) {
242 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
243 *data = (u16)((sr_reg &
244 I40E_GLNVM_SRDATA_RDDATA_MASK)
245 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
248 if (ret_code != I40E_SUCCESS)
249 i40e_debug(hw, I40E_DEBUG_NVM,
250 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
258 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
259 * @hw: pointer to the HW structure
260 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
261 * @data: word read from the Shadow RAM
263 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
265 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
268 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
270 DEBUGFUNC("i40e_read_nvm_word_aq");
272 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
273 *data = LE16_TO_CPU(*(__le16 *)data);
279 * i40e_read_nvm_buffer - Reads Shadow RAM buffer
280 * @hw: pointer to the HW structure
281 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
282 * @words: (in) number of words to read; (out) number of words actually read
283 * @data: words read from the Shadow RAM
285 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
286 * method. The buffer read is preceded by the NVM ownership take
287 * and followed by the release.
289 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
290 u16 *words, u16 *data)
292 return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
296 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
297 * @hw: pointer to the HW structure
298 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
299 * @words: (in) number of words to read; (out) number of words actually read
300 * @data: words read from the Shadow RAM
302 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
303 * method. The buffer read is preceded by the NVM ownership take
304 * and followed by the release.
306 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
307 u16 *words, u16 *data)
309 enum i40e_status_code ret_code = I40E_SUCCESS;
312 DEBUGFUNC("i40e_read_nvm_buffer_srctl");
314 /* Loop thru the selected region */
315 for (word = 0; word < *words; word++) {
316 index = offset + word;
317 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
318 if (ret_code != I40E_SUCCESS)
322 /* Update the number of words read from the Shadow RAM */
329 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
330 * @hw: pointer to the HW structure
331 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
332 * @words: (in) number of words to read; (out) number of words actually read
333 * @data: words read from the Shadow RAM
335 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
336 * method. The buffer read is preceded by the NVM ownership take
337 * and followed by the release.
339 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
340 u16 *words, u16 *data)
342 enum i40e_status_code ret_code;
343 u16 read_size = *words;
344 bool last_cmd = false;
348 DEBUGFUNC("i40e_read_nvm_buffer_aq");
351 /* Calculate number of bytes we should read in this step.
352 * FVL AQ do not allow to read more than one page at a time or
353 * to cross page boundaries.
355 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
356 read_size = min(*words,
357 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
358 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
360 read_size = min((*words - words_read),
361 I40E_SR_SECTOR_SIZE_IN_WORDS);
363 /* Check if this is last command, if so set proper flag */
364 if ((words_read + read_size) >= *words)
367 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
368 data + words_read, last_cmd);
369 if (ret_code != I40E_SUCCESS)
370 goto read_nvm_buffer_aq_exit;
372 /* Increment counter for words already read and move offset to
375 words_read += read_size;
377 } while (words_read < *words);
379 for (i = 0; i < *words; i++)
380 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
382 read_nvm_buffer_aq_exit:
388 * i40e_read_nvm_aq - Read Shadow RAM.
389 * @hw: pointer to the HW structure.
390 * @module_pointer: module pointer location in words from the NVM beginning
391 * @offset: offset in words from module start
392 * @words: number of words to write
393 * @data: buffer with words to write to the Shadow RAM
394 * @last_command: tells the AdminQ that this is the last command
396 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
398 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
399 u32 offset, u16 words, void *data,
402 enum i40e_status_code ret_code = I40E_ERR_NVM;
404 DEBUGFUNC("i40e_read_nvm_aq");
406 /* Here we are checking the SR limit only for the flat memory model.
407 * We cannot do it for the module-based model, as we did not acquire
408 * the NVM resource yet (we cannot get the module pointer value).
409 * Firmware will check the module-based model.
411 if ((offset + words) > hw->nvm.sr_size)
412 i40e_debug(hw, I40E_DEBUG_NVM,
413 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
414 (offset + words), hw->nvm.sr_size);
415 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
416 /* We can write only up to 4KB (one sector), in one AQ write */
417 i40e_debug(hw, I40E_DEBUG_NVM,
418 "NVM write fail error: tried to write %d words, limit is %d.\n",
419 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
420 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
421 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
422 /* A single write cannot spread over two sectors */
423 i40e_debug(hw, I40E_DEBUG_NVM,
424 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
427 ret_code = i40e_aq_read_nvm(hw, module_pointer,
428 2 * offset, /*bytes*/
430 data, last_command, NULL);
436 * i40e_write_nvm_aq - Writes Shadow RAM.
437 * @hw: pointer to the HW structure.
438 * @module_pointer: module pointer location in words from the NVM beginning
439 * @offset: offset in words from module start
440 * @words: number of words to write
441 * @data: buffer with words to write to the Shadow RAM
442 * @last_command: tells the AdminQ that this is the last command
444 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
446 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
447 u32 offset, u16 words, void *data,
450 enum i40e_status_code ret_code = I40E_ERR_NVM;
452 DEBUGFUNC("i40e_write_nvm_aq");
454 /* Here we are checking the SR limit only for the flat memory model.
455 * We cannot do it for the module-based model, as we did not acquire
456 * the NVM resource yet (we cannot get the module pointer value).
457 * Firmware will check the module-based model.
459 if ((offset + words) > hw->nvm.sr_size)
460 DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
461 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
462 /* We can write only up to 4KB (one sector), in one AQ write */
463 DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
464 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
465 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
466 /* A single write cannot spread over two sectors */
467 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
469 ret_code = i40e_aq_update_nvm(hw, module_pointer,
470 2 * offset, /*bytes*/
472 data, last_command, NULL);
478 * i40e_write_nvm_word - Writes Shadow RAM word
479 * @hw: pointer to the HW structure
480 * @offset: offset of the Shadow RAM word to write
481 * @data: word to write to the Shadow RAM
483 * Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
484 * NVM ownership have to be acquired and released (on ARQ completion event
485 * reception) by caller. To commit SR to NVM update checksum function
488 enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
491 DEBUGFUNC("i40e_write_nvm_word");
493 *((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));
495 /* Value 0x00 below means that we treat SR as a flat mem */
496 return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);
500 * i40e_write_nvm_buffer - Writes Shadow RAM buffer
501 * @hw: pointer to the HW structure
502 * @module_pointer: module pointer location in words from the NVM beginning
503 * @offset: offset of the Shadow RAM buffer to write
504 * @words: number of words to write
505 * @data: words to write to the Shadow RAM
507 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
508 * NVM ownership must be acquired before calling this function and released
509 * on ARQ completion event reception by caller. To commit SR to NVM update
510 * checksum function should be called.
512 enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,
513 u8 module_pointer, u32 offset,
514 u16 words, void *data)
516 __le16 *le_word_ptr = (__le16 *)data;
517 u16 *word_ptr = (u16 *)data;
520 DEBUGFUNC("i40e_write_nvm_buffer");
522 for (i = 0; i < words; i++)
523 le_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);
525 /* Here we will only write one buffer as the size of the modules
526 * mirrored in the Shadow RAM is always less than 4K.
528 return i40e_write_nvm_aq(hw, module_pointer, offset, words,
533 * i40e_calc_nvm_checksum - Calculates and returns the checksum
534 * @hw: pointer to hardware structure
535 * @checksum: pointer to the checksum
537 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
538 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
539 * is customer specific and unknown. Therefore, this function skips all maximum
540 * possible size of VPD (1kB).
542 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
544 enum i40e_status_code ret_code = I40E_SUCCESS;
545 struct i40e_virt_mem vmem;
546 u16 pcie_alt_module = 0;
547 u16 checksum_local = 0;
552 DEBUGFUNC("i40e_calc_nvm_checksum");
554 ret_code = i40e_allocate_virt_mem(hw, &vmem,
555 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
557 goto i40e_calc_nvm_checksum_exit;
558 data = (u16 *)vmem.va;
560 /* read pointer to VPD area */
561 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
562 if (ret_code != I40E_SUCCESS) {
563 ret_code = I40E_ERR_NVM_CHECKSUM;
564 goto i40e_calc_nvm_checksum_exit;
567 /* read pointer to PCIe Alt Auto-load module */
568 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
570 if (ret_code != I40E_SUCCESS) {
571 ret_code = I40E_ERR_NVM_CHECKSUM;
572 goto i40e_calc_nvm_checksum_exit;
575 /* Calculate SW checksum that covers the whole 64kB shadow RAM
576 * except the VPD and PCIe ALT Auto-load modules
578 for (i = 0; i < hw->nvm.sr_size; i++) {
580 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
581 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
582 ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
583 if (ret_code != I40E_SUCCESS) {
584 ret_code = I40E_ERR_NVM_CHECKSUM;
585 goto i40e_calc_nvm_checksum_exit;
589 /* Skip Checksum word */
590 if (i == I40E_SR_SW_CHECKSUM_WORD)
592 /* Skip VPD module (convert byte size to word count) */
593 if ((i >= (u32)vpd_module) &&
594 (i < ((u32)vpd_module +
595 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
598 /* Skip PCIe ALT module (convert byte size to word count) */
599 if ((i >= (u32)pcie_alt_module) &&
600 (i < ((u32)pcie_alt_module +
601 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
605 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
608 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
610 i40e_calc_nvm_checksum_exit:
611 i40e_free_virt_mem(hw, &vmem);
616 * i40e_update_nvm_checksum - Updates the NVM checksum
617 * @hw: pointer to hardware structure
619 * NVM ownership must be acquired before calling this function and released
620 * on ARQ completion event reception by caller.
621 * This function will commit SR to NVM.
623 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
625 enum i40e_status_code ret_code = I40E_SUCCESS;
628 DEBUGFUNC("i40e_update_nvm_checksum");
630 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
631 if (ret_code == I40E_SUCCESS)
632 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
639 * i40e_validate_nvm_checksum - Validate EEPROM checksum
640 * @hw: pointer to hardware structure
641 * @checksum: calculated checksum
643 * Performs checksum calculation and validates the NVM SW checksum. If the
644 * caller does not need checksum, the value can be NULL.
646 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
649 enum i40e_status_code ret_code = I40E_SUCCESS;
651 u16 checksum_local = 0;
653 DEBUGFUNC("i40e_validate_nvm_checksum");
655 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
656 if (ret_code != I40E_SUCCESS)
657 goto i40e_validate_nvm_checksum_exit;
659 /* Do not use i40e_read_nvm_word() because we do not want to take
660 * the synchronization semaphores twice here.
662 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
664 /* Verify read checksum from EEPROM is the same as
665 * calculated checksum
667 if (checksum_local != checksum_sr)
668 ret_code = I40E_ERR_NVM_CHECKSUM;
670 /* If the user cares, return the calculated checksum */
672 *checksum = checksum_local;
674 i40e_validate_nvm_checksum_exit:
678 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
679 struct i40e_nvm_access *cmd,
680 u8 *bytes, int *perrno);
681 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
682 struct i40e_nvm_access *cmd,
683 u8 *bytes, int *perrno);
684 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
685 struct i40e_nvm_access *cmd,
686 u8 *bytes, int *perrno);
687 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
688 struct i40e_nvm_access *cmd,
690 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
691 struct i40e_nvm_access *cmd,
693 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
694 struct i40e_nvm_access *cmd,
695 u8 *bytes, int *perrno);
696 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
697 struct i40e_nvm_access *cmd,
698 u8 *bytes, int *perrno);
699 STATIC inline u8 i40e_nvmupd_get_module(u32 val)
701 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
703 STATIC inline u8 i40e_nvmupd_get_transaction(u32 val)
705 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
708 STATIC const char *i40e_nvm_update_state_str[] = {
709 "I40E_NVMUPD_INVALID",
710 "I40E_NVMUPD_READ_CON",
711 "I40E_NVMUPD_READ_SNT",
712 "I40E_NVMUPD_READ_LCB",
713 "I40E_NVMUPD_READ_SA",
714 "I40E_NVMUPD_WRITE_ERA",
715 "I40E_NVMUPD_WRITE_CON",
716 "I40E_NVMUPD_WRITE_SNT",
717 "I40E_NVMUPD_WRITE_LCB",
718 "I40E_NVMUPD_WRITE_SA",
719 "I40E_NVMUPD_CSUM_CON",
720 "I40E_NVMUPD_CSUM_SA",
721 "I40E_NVMUPD_CSUM_LCB",
725 * i40e_nvmupd_command - Process an NVM update command
726 * @hw: pointer to hardware structure
727 * @cmd: pointer to nvm update command
728 * @bytes: pointer to the data buffer
729 * @perrno: pointer to return error code
731 * Dispatches command depending on what update state is current
733 enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
734 struct i40e_nvm_access *cmd,
735 u8 *bytes, int *perrno)
737 enum i40e_status_code status;
739 DEBUGFUNC("i40e_nvmupd_command");
744 switch (hw->nvmupd_state) {
745 case I40E_NVMUPD_STATE_INIT:
746 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
749 case I40E_NVMUPD_STATE_READING:
750 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
753 case I40E_NVMUPD_STATE_WRITING:
754 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
758 /* invalid state, should never happen */
759 i40e_debug(hw, I40E_DEBUG_NVM,
760 "NVMUPD: no such state %d\n", hw->nvmupd_state);
761 status = I40E_NOT_SUPPORTED;
769 * i40e_nvmupd_state_init - Handle NVM update state Init
770 * @hw: pointer to hardware structure
771 * @cmd: pointer to nvm update command buffer
772 * @bytes: pointer to the data buffer
773 * @perrno: pointer to return error code
775 * Process legitimate commands of the Init state and conditionally set next
776 * state. Reject all other commands.
778 STATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,
779 struct i40e_nvm_access *cmd,
780 u8 *bytes, int *perrno)
782 enum i40e_status_code status = I40E_SUCCESS;
783 enum i40e_nvmupd_cmd upd_cmd;
785 DEBUGFUNC("i40e_nvmupd_state_init");
787 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
790 case I40E_NVMUPD_READ_SA:
791 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
793 *perrno = i40e_aq_rc_to_posix(status,
794 hw->aq.asq_last_status);
796 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
797 i40e_release_nvm(hw);
801 case I40E_NVMUPD_READ_SNT:
802 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
804 *perrno = i40e_aq_rc_to_posix(status,
805 hw->aq.asq_last_status);
807 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
809 i40e_release_nvm(hw);
811 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
815 case I40E_NVMUPD_WRITE_ERA:
816 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
818 *perrno = i40e_aq_rc_to_posix(status,
819 hw->aq.asq_last_status);
821 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
823 i40e_release_nvm(hw);
825 hw->aq.nvm_release_on_done = true;
829 case I40E_NVMUPD_WRITE_SA:
830 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
832 *perrno = i40e_aq_rc_to_posix(status,
833 hw->aq.asq_last_status);
835 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
837 i40e_release_nvm(hw);
839 hw->aq.nvm_release_on_done = true;
843 case I40E_NVMUPD_WRITE_SNT:
844 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
846 *perrno = i40e_aq_rc_to_posix(status,
847 hw->aq.asq_last_status);
849 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
851 i40e_release_nvm(hw);
853 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
857 case I40E_NVMUPD_CSUM_SA:
858 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
860 *perrno = i40e_aq_rc_to_posix(status,
861 hw->aq.asq_last_status);
863 status = i40e_update_nvm_checksum(hw);
865 *perrno = hw->aq.asq_last_status ?
866 i40e_aq_rc_to_posix(status,
867 hw->aq.asq_last_status) :
869 i40e_release_nvm(hw);
871 hw->aq.nvm_release_on_done = true;
877 i40e_debug(hw, I40E_DEBUG_NVM,
878 "NVMUPD: bad cmd %s in init state\n",
879 i40e_nvm_update_state_str[upd_cmd]);
880 status = I40E_ERR_NVM;
888 * i40e_nvmupd_state_reading - Handle NVM update state Reading
889 * @hw: pointer to hardware structure
890 * @cmd: pointer to nvm update command buffer
891 * @bytes: pointer to the data buffer
892 * @perrno: pointer to return error code
894 * NVM ownership is already held. Process legitimate commands and set any
895 * change in state; reject all other commands.
897 STATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,
898 struct i40e_nvm_access *cmd,
899 u8 *bytes, int *perrno)
901 enum i40e_status_code status;
902 enum i40e_nvmupd_cmd upd_cmd;
904 DEBUGFUNC("i40e_nvmupd_state_reading");
906 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
909 case I40E_NVMUPD_READ_SA:
910 case I40E_NVMUPD_READ_CON:
911 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
914 case I40E_NVMUPD_READ_LCB:
915 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
916 i40e_release_nvm(hw);
917 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
921 i40e_debug(hw, I40E_DEBUG_NVM,
922 "NVMUPD: bad cmd %s in reading state.\n",
923 i40e_nvm_update_state_str[upd_cmd]);
924 status = I40E_NOT_SUPPORTED;
932 * i40e_nvmupd_state_writing - Handle NVM update state Writing
933 * @hw: pointer to hardware structure
934 * @cmd: pointer to nvm update command buffer
935 * @bytes: pointer to the data buffer
936 * @perrno: pointer to return error code
938 * NVM ownership is already held. Process legitimate commands and set any
939 * change in state; reject all other commands
941 STATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,
942 struct i40e_nvm_access *cmd,
943 u8 *bytes, int *perrno)
945 enum i40e_status_code status;
946 enum i40e_nvmupd_cmd upd_cmd;
947 bool retry_attempt = false;
949 DEBUGFUNC("i40e_nvmupd_state_writing");
951 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
955 case I40E_NVMUPD_WRITE_CON:
956 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
959 case I40E_NVMUPD_WRITE_LCB:
960 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
962 hw->aq.nvm_release_on_done = true;
963 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
966 case I40E_NVMUPD_CSUM_CON:
967 status = i40e_update_nvm_checksum(hw);
969 *perrno = hw->aq.asq_last_status ?
970 i40e_aq_rc_to_posix(status,
971 hw->aq.asq_last_status) :
973 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
977 case I40E_NVMUPD_CSUM_LCB:
978 status = i40e_update_nvm_checksum(hw);
980 *perrno = hw->aq.asq_last_status ?
981 i40e_aq_rc_to_posix(status,
982 hw->aq.asq_last_status) :
985 hw->aq.nvm_release_on_done = true;
986 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
990 i40e_debug(hw, I40E_DEBUG_NVM,
991 "NVMUPD: bad cmd %s in writing state.\n",
992 i40e_nvm_update_state_str[upd_cmd]);
993 status = I40E_NOT_SUPPORTED;
998 /* In some circumstances, a multi-write transaction takes longer
999 * than the default 3 minute timeout on the write semaphore. If
1000 * the write failed with an EBUSY status, this is likely the problem,
1001 * so here we try to reacquire the semaphore then retry the write.
1002 * We only do one retry, then give up.
1004 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1006 enum i40e_status_code old_status = status;
1007 u32 old_asq_status = hw->aq.asq_last_status;
1010 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1011 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1012 i40e_debug(hw, I40E_DEBUG_ALL,
1013 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1014 gtime, hw->nvm.hw_semaphore_timeout);
1015 i40e_release_nvm(hw);
1016 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1018 i40e_debug(hw, I40E_DEBUG_ALL,
1019 "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1020 hw->aq.asq_last_status);
1021 status = old_status;
1022 hw->aq.asq_last_status = old_asq_status;
1024 retry_attempt = true;
1034 * i40e_nvmupd_validate_command - Validate given command
1035 * @hw: pointer to hardware structure
1036 * @cmd: pointer to nvm update command buffer
1037 * @perrno: pointer to return error code
1039 * Return one of the valid command types or I40E_NVMUPD_INVALID
1041 STATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1042 struct i40e_nvm_access *cmd,
1045 enum i40e_nvmupd_cmd upd_cmd;
1046 u8 transaction, module;
1048 DEBUGFUNC("i40e_nvmupd_validate_command\n");
1050 /* anything that doesn't match a recognized case is an error */
1051 upd_cmd = I40E_NVMUPD_INVALID;
1053 transaction = i40e_nvmupd_get_transaction(cmd->config);
1054 module = i40e_nvmupd_get_module(cmd->config);
1056 /* limits on data size */
1057 if ((cmd->data_size < 1) ||
1058 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1059 i40e_debug(hw, I40E_DEBUG_NVM,
1060 "i40e_nvmupd_validate_command data_size %d\n",
1063 return I40E_NVMUPD_INVALID;
1066 switch (cmd->command) {
1068 switch (transaction) {
1070 upd_cmd = I40E_NVMUPD_READ_CON;
1073 upd_cmd = I40E_NVMUPD_READ_SNT;
1076 upd_cmd = I40E_NVMUPD_READ_LCB;
1079 upd_cmd = I40E_NVMUPD_READ_SA;
1084 case I40E_NVM_WRITE:
1085 switch (transaction) {
1087 upd_cmd = I40E_NVMUPD_WRITE_CON;
1090 upd_cmd = I40E_NVMUPD_WRITE_SNT;
1093 upd_cmd = I40E_NVMUPD_WRITE_LCB;
1096 upd_cmd = I40E_NVMUPD_WRITE_SA;
1099 upd_cmd = I40E_NVMUPD_WRITE_ERA;
1102 upd_cmd = I40E_NVMUPD_CSUM_CON;
1104 case (I40E_NVM_CSUM|I40E_NVM_SA):
1105 upd_cmd = I40E_NVMUPD_CSUM_SA;
1107 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1108 upd_cmd = I40E_NVMUPD_CSUM_LCB;
1113 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n",
1114 i40e_nvm_update_state_str[upd_cmd],
1116 hw->aq.nvm_release_on_done);
1118 if (upd_cmd == I40E_NVMUPD_INVALID) {
1120 i40e_debug(hw, I40E_DEBUG_NVM,
1121 "i40e_nvmupd_validate_command returns %d perrno %d\n",
1128 * i40e_nvmupd_nvm_read - Read NVM
1129 * @hw: pointer to hardware structure
1130 * @cmd: pointer to nvm update command buffer
1131 * @bytes: pointer to the data buffer
1132 * @perrno: pointer to return error code
1134 * cmd structure contains identifiers and data buffer
1136 STATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1137 struct i40e_nvm_access *cmd,
1138 u8 *bytes, int *perrno)
1140 enum i40e_status_code status;
1141 u8 module, transaction;
1144 transaction = i40e_nvmupd_get_transaction(cmd->config);
1145 module = i40e_nvmupd_get_module(cmd->config);
1146 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1148 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1151 i40e_debug(hw, I40E_DEBUG_NVM,
1152 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
1153 module, cmd->offset, cmd->data_size);
1154 i40e_debug(hw, I40E_DEBUG_NVM,
1155 "i40e_nvmupd_nvm_read status %d aq %d\n",
1156 status, hw->aq.asq_last_status);
1157 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1164 * i40e_nvmupd_nvm_erase - Erase an NVM module
1165 * @hw: pointer to hardware structure
1166 * @cmd: pointer to nvm update command buffer
1167 * @perrno: pointer to return error code
1169 * module, offset, data_size and data are in cmd structure
1171 STATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1172 struct i40e_nvm_access *cmd,
1175 enum i40e_status_code status = I40E_SUCCESS;
1176 u8 module, transaction;
1179 transaction = i40e_nvmupd_get_transaction(cmd->config);
1180 module = i40e_nvmupd_get_module(cmd->config);
1181 last = (transaction & I40E_NVM_LCB);
1182 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1185 i40e_debug(hw, I40E_DEBUG_NVM,
1186 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
1187 module, cmd->offset, cmd->data_size);
1188 i40e_debug(hw, I40E_DEBUG_NVM,
1189 "i40e_nvmupd_nvm_erase status %d aq %d\n",
1190 status, hw->aq.asq_last_status);
1191 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1198 * i40e_nvmupd_nvm_write - Write NVM
1199 * @hw: pointer to hardware structure
1200 * @cmd: pointer to nvm update command buffer
1201 * @bytes: pointer to the data buffer
1202 * @perrno: pointer to return error code
1204 * module, offset, data_size and data are in cmd structure
1206 STATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1207 struct i40e_nvm_access *cmd,
1208 u8 *bytes, int *perrno)
1210 enum i40e_status_code status = I40E_SUCCESS;
1211 u8 module, transaction;
1214 transaction = i40e_nvmupd_get_transaction(cmd->config);
1215 module = i40e_nvmupd_get_module(cmd->config);
1216 last = (transaction & I40E_NVM_LCB);
1218 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1219 (u16)cmd->data_size, bytes, last, NULL);
1221 i40e_debug(hw, I40E_DEBUG_NVM,
1222 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1223 module, cmd->offset, cmd->data_size);
1224 i40e_debug(hw, I40E_DEBUG_NVM,
1225 "i40e_nvmupd_nvm_write status %d aq %d\n",
1226 status, hw->aq.asq_last_status);
1227 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);