1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
14 #include <rte_common.h>
15 #include <rte_memcpy.h>
16 #include <rte_byteorder.h>
17 #include <rte_cycles.h>
18 #include <rte_spinlock.h>
22 #include "../i40e_logs.h"
23 #include "i40e_status.h"
35 typedef enum i40e_status_code i40e_status;
37 #define hw_dbg(hw, S, A...) do {} while (0)
38 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
39 #define lower_32_bits(n) ((u32)(n))
40 #define low_16_bits(x) ((x) & 0xFFFF)
41 #define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)
44 #define ETH_ADDR_LEN 6
48 #define __le16 uint16_t
51 #define __le32 uint32_t
54 #define __le64 uint64_t
57 #define __be16 uint16_t
60 #define __be32 uint32_t
63 #define __be64 uint64_t
71 /* Avoid macro redefinition warning on Windows */
72 #ifdef RTE_EXEC_ENV_WINDOWS
80 #define min(a,b) RTE_MIN(a,b)
81 #define max(a,b) RTE_MAX(a,b)
83 #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
85 #define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S)
86 #define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)
88 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
89 #define DEBUGOUT2 DEBUGOUT1
90 #define DEBUGOUT3 DEBUGOUT2
91 #define DEBUGOUT6 DEBUGOUT3
92 #define DEBUGOUT7 DEBUGOUT6
94 #define i40e_debug(h, m, s, ...) \
96 if (((m) & (h)->debug_mask)) \
97 PMD_DRV_LOG_RAW(DEBUG, "i40e %02x.%x " s, \
98 (h)->bus.device, (h)->bus.func, \
102 /* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()
103 * are required for reading/writing below registers, as reading/writing it
104 * directly may not function correctly if the device is under heavy small
105 * packet traffic. Note that those interfaces are available from FVL5 and not
106 * suitable before the AdminQ is ready during initialization.
119 * I40E_VSIQF_TCREGION
128 * I40E_GLQF_HASH_INSET
133 * I40E_PRTQF_FD_INSET
134 * I40E_PRTQF_FD_FLXINSET
138 #define I40E_PCI_REG(reg) rte_read32(reg)
139 #define I40E_PCI_REG_ADDR(a, reg) \
140 ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
141 static inline uint32_t i40e_read_addr(volatile void *addr)
143 return rte_le_to_cpu_32(I40E_PCI_REG(addr));
146 #define I40E_PCI_REG64(reg) rte_read64(reg)
147 #define I40E_PCI_REG64_ADDR(a, reg) \
148 ((volatile uint64_t *)((char *)(a)->hw_addr + (reg)))
149 static inline uint64_t i40e_read64_addr(volatile void *addr)
151 return rte_le_to_cpu_64(I40E_PCI_REG64(addr));
154 #define I40E_PCI_REG_WRITE(reg, value) \
155 rte_write32((rte_cpu_to_le_32(value)), reg)
156 #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \
157 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
159 #define I40E_PCI_REG_WC_WRITE(reg, value) \
160 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
161 #define I40E_PCI_REG_WC_WRITE_RELAXED(reg, value) \
162 rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
164 #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
165 #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)
167 #define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))
168 #define I40E_WRITE_REG(hw, reg, value) \
169 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))
171 #define I40E_READ_REG64(hw, reg) i40e_read64_addr(I40E_PCI_REG64_ADDR((hw), (reg)))
173 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))
174 #define wr32(a, reg, value) \
175 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))
176 #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)))
178 #define ARRAY_SIZE(arr) RTE_DIM(arr)
180 /* memory allocation tracking */
181 struct i40e_dma_mem {
188 #define i40e_allocate_dma_mem(h, m, unused, s, a) \
189 i40e_allocate_dma_mem_d(h, m, s, a)
190 #define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m)
192 struct i40e_virt_mem {
197 #define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s)
198 #define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m)
200 #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
201 #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
202 #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
203 #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
204 #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
205 #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
207 #define cpu_to_le16(o) rte_cpu_to_le_16(o)
208 #define cpu_to_le32(s) rte_cpu_to_le_32(s)
209 #define cpu_to_le64(h) rte_cpu_to_le_64(h)
210 #define le16_to_cpu(a) rte_le_to_cpu_16(a)
211 #define le32_to_cpu(c) rte_le_to_cpu_32(c)
212 #define le64_to_cpu(k) rte_le_to_cpu_64(k)
215 struct i40e_spinlock {
216 rte_spinlock_t spinlock;
219 #define i40e_init_spinlock(_sp) i40e_init_spinlock_d(_sp)
220 #define i40e_acquire_spinlock(_sp) i40e_acquire_spinlock_d(_sp)
221 #define i40e_release_spinlock(_sp) i40e_release_spinlock_d(_sp)
222 #define i40e_destroy_spinlock(_sp) i40e_destroy_spinlock_d(_sp)
224 #define I40E_NTOHS(a) rte_be_to_cpu_16(a)
225 #define I40E_NTOHL(a) rte_be_to_cpu_32(a)
226 #define I40E_HTONS(a) rte_cpu_to_be_16(a)
227 #define I40E_HTONL(a) rte_cpu_to_be_32(a)
229 #define i40e_memset(a, b, c, d) memset((a), (b), (c))
230 #define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
232 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
233 #define DELAY(x) rte_delay_us_sleep(x)
234 #define i40e_usec_delay(x) DELAY(x)
235 #define i40e_msec_delay(x) DELAY(1000 * (x))
236 #define udelay(x) DELAY(x)
237 #define msleep(x) DELAY(1000*(x))
238 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
240 #endif /* _I40E_OSDEP_H_ */