1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
14 #include <rte_common.h>
15 #include <rte_memcpy.h>
16 #include <rte_byteorder.h>
17 #include <rte_cycles.h>
18 #include <rte_spinlock.h>
22 #include "../i40e_logs.h"
34 typedef enum i40e_status_code i40e_status;
36 #define hw_dbg(hw, S, A...) do {} while (0)
37 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
38 #define lower_32_bits(n) ((u32)(n))
39 #define low_16_bits(x) ((x) & 0xFFFF)
40 #define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)
43 #define ETH_ADDR_LEN 6
47 #define __le16 uint16_t
50 #define __le32 uint32_t
53 #define __le64 uint64_t
56 #define __be16 uint16_t
59 #define __be32 uint32_t
62 #define __be64 uint64_t
70 #define min(a,b) RTE_MIN(a,b)
71 #define max(a,b) RTE_MAX(a,b)
73 #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
75 #define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S)
76 #define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)
78 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
79 #define DEBUGOUT2 DEBUGOUT1
80 #define DEBUGOUT3 DEBUGOUT2
81 #define DEBUGOUT6 DEBUGOUT3
82 #define DEBUGOUT7 DEBUGOUT6
84 #define i40e_debug(h, m, s, ...) \
86 if (((m) & (h)->debug_mask)) \
87 PMD_DRV_LOG_RAW(DEBUG, "i40e %02x.%x " s, \
88 (h)->bus.device, (h)->bus.func, \
92 /* AQ commands based interfaces of i40e_read_rx_ctl() and i40e_write_rx_ctl()
93 * are required for reading/writing below registers, as reading/writing it
94 * directly may not function correctly if the device is under heavy small
95 * packet traffic. Note that those interfaces are available from FVL5 and not
96 * suitable before the AdminQ is ready during initialization.
109 * I40E_VSIQF_TCREGION
118 * I40E_GLQF_HASH_INSET
123 * I40E_PRTQF_FD_INSET
124 * I40E_PRTQF_FD_FLXINSET
128 #define I40E_PCI_REG(reg) rte_read32(reg)
129 #define I40E_PCI_REG_ADDR(a, reg) \
130 ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
131 static inline uint32_t i40e_read_addr(volatile void *addr)
133 return rte_le_to_cpu_32(I40E_PCI_REG(addr));
136 #define I40E_PCI_REG_WRITE(reg, value) \
137 rte_write32((rte_cpu_to_le_32(value)), reg)
138 #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \
139 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
141 #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
142 #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)
144 #define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))
145 #define I40E_WRITE_REG(hw, reg, value) \
146 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))
148 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))
149 #define wr32(a, reg, value) \
150 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))
151 #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)))
153 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
155 /* memory allocation tracking */
156 struct i40e_dma_mem {
161 } __attribute__((packed));
163 #define i40e_allocate_dma_mem(h, m, unused, s, a) \
164 i40e_allocate_dma_mem_d(h, m, s, a)
165 #define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m)
167 struct i40e_virt_mem {
170 } __attribute__((packed));
172 #define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s)
173 #define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m)
175 #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
176 #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
177 #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
178 #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
179 #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
180 #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
182 #define cpu_to_le16(o) rte_cpu_to_le_16(o)
183 #define cpu_to_le32(s) rte_cpu_to_le_32(s)
184 #define cpu_to_le64(h) rte_cpu_to_le_64(h)
185 #define le16_to_cpu(a) rte_le_to_cpu_16(a)
186 #define le32_to_cpu(c) rte_le_to_cpu_32(c)
187 #define le64_to_cpu(k) rte_le_to_cpu_64(k)
190 struct i40e_spinlock {
191 rte_spinlock_t spinlock;
194 #define i40e_init_spinlock(_sp) i40e_init_spinlock_d(_sp)
195 #define i40e_acquire_spinlock(_sp) i40e_acquire_spinlock_d(_sp)
196 #define i40e_release_spinlock(_sp) i40e_release_spinlock_d(_sp)
197 #define i40e_destroy_spinlock(_sp) i40e_destroy_spinlock_d(_sp)
199 #define I40E_NTOHS(a) rte_be_to_cpu_16(a)
200 #define I40E_NTOHL(a) rte_be_to_cpu_32(a)
201 #define I40E_HTONS(a) rte_cpu_to_be_16(a)
202 #define I40E_HTONL(a) rte_cpu_to_be_32(a)
204 #define i40e_memset(a, b, c, d) memset((a), (b), (c))
205 #define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
207 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
208 #define DELAY(x) rte_delay_us_sleep(x)
209 #define i40e_usec_delay(x) DELAY(x)
210 #define i40e_msec_delay(x) DELAY(1000 * (x))
211 #define udelay(x) DELAY(x)
212 #define msleep(x) DELAY(1000*(x))
213 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
215 #endif /* _I40E_OSDEP_H_ */