drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 161                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166
 167 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 168                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 170                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 172                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 174                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 176                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 177
 178 #define I40E_PHY_COM_REG_PAGE                   0x1E
 179 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 180 #define I40E_PHY_LED_MANUAL_ON                  0x100
 181 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 182 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 183 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 184
 185 /* Memory types */
 186 enum i40e_memset_type {
 187         I40E_NONDMA_MEM = 0,
 188         I40E_DMA_MEM
 189 };
 190
 191 /* Memcpy types */
 192 enum i40e_memcpy_type {
 193         I40E_NONDMA_TO_NONDMA = 0,
 194         I40E_NONDMA_TO_DMA,
 195         I40E_DMA_TO_DMA,
 196         I40E_DMA_TO_NONDMA
 197 };
 198
 199 #ifdef X722_SUPPORT
 200 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 201 #endif
 202 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 203
 204
 205 /* These are structs for managing the hardware information and the operations.
 206  * The structures of function pointers are filled out at init time when we
 207  * know for sure exactly which hardware we're working with.  This gives us the
 208  * flexibility of using the same main driver code but adapting to slightly
 209  * different hardware needs as new parts are developed.  For this architecture,
 210  * the Firmware and AdminQ are intended to insulate the driver from most of the
 211  * future changes, but these structures will also do part of the job.
 212  */
 213 enum i40e_mac_type {
 214         I40E_MAC_UNKNOWN = 0,
 215         I40E_MAC_X710,
 216         I40E_MAC_XL710,
 217         I40E_MAC_VF,
 218 #ifdef X722_SUPPORT
 219         I40E_MAC_X722,
 220         I40E_MAC_X722_VF,
 221 #endif
 222         I40E_MAC_GENERIC,
 223 };
 224
 225 enum i40e_media_type {
 226         I40E_MEDIA_TYPE_UNKNOWN = 0,
 227         I40E_MEDIA_TYPE_FIBER,
 228         I40E_MEDIA_TYPE_BASET,
 229         I40E_MEDIA_TYPE_BACKPLANE,
 230         I40E_MEDIA_TYPE_CX4,
 231         I40E_MEDIA_TYPE_DA,
 232         I40E_MEDIA_TYPE_VIRTUAL
 233 };
 234
 235 enum i40e_fc_mode {
 236         I40E_FC_NONE = 0,
 237         I40E_FC_RX_PAUSE,
 238         I40E_FC_TX_PAUSE,
 239         I40E_FC_FULL,
 240         I40E_FC_PFC,
 241         I40E_FC_DEFAULT
 242 };
 243
 244 enum i40e_set_fc_aq_failures {
 245         I40E_SET_FC_AQ_FAIL_NONE = 0,
 246         I40E_SET_FC_AQ_FAIL_GET = 1,
 247         I40E_SET_FC_AQ_FAIL_SET = 2,
 248         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 249         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 250 };
 251
 252 enum i40e_vsi_type {
 253         I40E_VSI_MAIN   = 0,
 254         I40E_VSI_VMDQ1  = 1,
 255         I40E_VSI_VMDQ2  = 2,
 256         I40E_VSI_CTRL   = 3,
 257         I40E_VSI_FCOE   = 4,
 258         I40E_VSI_MIRROR = 5,
 259         I40E_VSI_SRIOV  = 6,
 260         I40E_VSI_FDIR   = 7,
 261         I40E_VSI_TYPE_UNKNOWN
 262 };
 263
 264 enum i40e_queue_type {
 265         I40E_QUEUE_TYPE_RX = 0,
 266         I40E_QUEUE_TYPE_TX,
 267         I40E_QUEUE_TYPE_PE_CEQ,
 268         I40E_QUEUE_TYPE_UNKNOWN
 269 };
 270
 271 struct i40e_link_status {
 272         enum i40e_aq_phy_type phy_type;
 273         enum i40e_aq_link_speed link_speed;
 274         u8 link_info;
 275         u8 an_info;
 276         u8 ext_info;
 277         u8 loopback;
 278         /* is Link Status Event notification to SW enabled */
 279         bool lse_enable;
 280         u16 max_frame_size;
 281         bool crc_enable;
 282         u8 pacing;
 283         u8 requested_speeds;
 284         u8 module_type[3];
 285         /* 1st byte: module identifier */
 286 #define I40E_MODULE_TYPE_SFP            0x03
 287 #define I40E_MODULE_TYPE_QSFP           0x0D
 288         /* 2nd byte: ethernet compliance codes for 10/40G */
 289 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 290 #define I40E_MODULE_TYPE_40G_LR4        0x02
 291 #define I40E_MODULE_TYPE_40G_SR4        0x04
 292 #define I40E_MODULE_TYPE_40G_CR4        0x08
 293 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 294 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 295 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 296 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 297         /* 3rd byte: ethernet compliance codes for 1G */
 298 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 299 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 300 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 301 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 302 };
 303
 304 struct i40e_phy_info {
 305         struct i40e_link_status link_info;
 306         struct i40e_link_status link_info_old;
 307         bool get_link_info;
 308         enum i40e_media_type media_type;
 309         /* all the phy types the NVM is capable of */
 310         u64 phy_types;
 311 };
 312
 313 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 314 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 317 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 318 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 319 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 320 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 321 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 322 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 323 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 325 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 326 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 327 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 328 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 330 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 331 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 332 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 333 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 334 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 335 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 336 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 337 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 338 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 339 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 340                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 341 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 342 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)
 343 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)
 344 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)
 345 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)
 346 #define I40E_HW_CAP_MAX_GPIO                    30
 347 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 348 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 349
 350 #ifdef X722_SUPPORT
 351 enum i40e_acpi_programming_method {
 352         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 353         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 354 };
 355
 356 #define I40E_WOL_SUPPORT_MASK                   1
 357 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 358 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 359
 360 #endif
 361 /* Capabilities of a PF or a VF or the whole device */
 362 struct i40e_hw_capabilities {
 363         u32  switch_mode;
 364 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 365 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 366 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 367
 368         u32  management_mode;
 369         u32  mng_protocols_over_mctp;
 370 #define I40E_MNG_PROTOCOL_PLDM          0x2
 371 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 372 #define I40E_MNG_PROTOCOL_NCSI          0x8
 373         u32  npar_enable;
 374         u32  os2bmc;
 375         u32  valid_functions;
 376         bool sr_iov_1_1;
 377         bool vmdq;
 378         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 379         bool evb_802_1_qbh; /* Bridge Port Extension */
 380         bool dcb;
 381         bool fcoe;
 382         bool iscsi; /* Indicates iSCSI enabled */
 383         bool flex10_enable;
 384         bool flex10_capable;
 385         u32  flex10_mode;
 386 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 387 #define I40E_FLEX10_MODE_DCC            0x1
 388 #define I40E_FLEX10_MODE_DCI            0x2
 389
 390         u32 flex10_status;
 391 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 392 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 393
 394         bool sec_rev_disabled;
 395         bool update_disabled;
 396 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 397 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 398
 399         bool mgmt_cem;
 400         bool ieee_1588;
 401         bool iwarp;
 402         bool fd;
 403         u32 fd_filters_guaranteed;
 404         u32 fd_filters_best_effort;
 405         bool rss;
 406         u32 rss_table_size;
 407         u32 rss_table_entry_width;
 408         bool led[I40E_HW_CAP_MAX_GPIO];
 409         bool sdp[I40E_HW_CAP_MAX_GPIO];
 410         u32 nvm_image_type;
 411         u32 num_flow_director_filters;
 412         u32 num_vfs;
 413         u32 vf_base_id;
 414         u32 num_vsis;
 415         u32 num_rx_qp;
 416         u32 num_tx_qp;
 417         u32 base_queue;
 418         u32 num_msix_vectors;
 419         u32 num_msix_vectors_vf;
 420         u32 led_pin_num;
 421         u32 sdp_pin_num;
 422         u32 mdio_port_num;
 423         u32 mdio_port_mode;
 424         u8 rx_buf_chain_len;
 425         u32 enabled_tcmap;
 426         u32 maxtc;
 427         u64 wr_csr_prot;
 428 #ifdef X722_SUPPORT
 429         bool apm_wol_support;
 430         enum i40e_acpi_programming_method acpi_prog_method;
 431         bool proxy_support;
 432 #endif
 433 };
 434
 435 struct i40e_mac_info {
 436         enum i40e_mac_type type;
 437         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 438         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 439         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 440         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 441         u16 max_fcoeq;
 442 };
 443
 444 enum i40e_aq_resources_ids {
 445         I40E_NVM_RESOURCE_ID = 1
 446 };
 447
 448 enum i40e_aq_resource_access_type {
 449         I40E_RESOURCE_READ = 1,
 450         I40E_RESOURCE_WRITE
 451 };
 452
 453 struct i40e_nvm_info {
 454         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 455         u32 timeout;              /* [ms] */
 456         u16 sr_size;              /* Shadow RAM size in words */
 457         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 458         u16 version;              /* NVM package version */
 459         u32 eetrack;              /* NVM data version */
 460         u32 oem_ver;              /* OEM version info */
 461 };
 462
 463 /* definitions used in NVM update support */
 464
 465 enum i40e_nvmupd_cmd {
 466         I40E_NVMUPD_INVALID,
 467         I40E_NVMUPD_READ_CON,
 468         I40E_NVMUPD_READ_SNT,
 469         I40E_NVMUPD_READ_LCB,
 470         I40E_NVMUPD_READ_SA,
 471         I40E_NVMUPD_WRITE_ERA,
 472         I40E_NVMUPD_WRITE_CON,
 473         I40E_NVMUPD_WRITE_SNT,
 474         I40E_NVMUPD_WRITE_LCB,
 475         I40E_NVMUPD_WRITE_SA,
 476         I40E_NVMUPD_CSUM_CON,
 477         I40E_NVMUPD_CSUM_SA,
 478         I40E_NVMUPD_CSUM_LCB,
 479         I40E_NVMUPD_STATUS,
 480         I40E_NVMUPD_EXEC_AQ,
 481         I40E_NVMUPD_GET_AQ_RESULT,
 482 };
 483
 484 enum i40e_nvmupd_state {
 485         I40E_NVMUPD_STATE_INIT,
 486         I40E_NVMUPD_STATE_READING,
 487         I40E_NVMUPD_STATE_WRITING,
 488         I40E_NVMUPD_STATE_INIT_WAIT,
 489         I40E_NVMUPD_STATE_WRITE_WAIT,
 490 };
 491
 492 /* nvm_access definition and its masks/shifts need to be accessible to
 493  * application, core driver, and shared code.  Where is the right file?
 494  */
 495 #define I40E_NVM_READ   0xB
 496 #define I40E_NVM_WRITE  0xC
 497
 498 #define I40E_NVM_MOD_PNT_MASK 0xFF
 499
 500 #define I40E_NVM_TRANS_SHIFT    8
 501 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 502 #define I40E_NVM_CON            0x0
 503 #define I40E_NVM_SNT            0x1
 504 #define I40E_NVM_LCB            0x2
 505 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 506 #define I40E_NVM_ERA            0x4
 507 #define I40E_NVM_CSUM           0x8
 508 #define I40E_NVM_EXEC           0xf
 509
 510 #define I40E_NVM_ADAPT_SHIFT    16
 511 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 512
 513 #define I40E_NVMUPD_MAX_DATA    4096
 514 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 515
 516 struct i40e_nvm_access {
 517         u32 command;
 518         u32 config;
 519         u32 offset;     /* in bytes */
 520         u32 data_size;  /* in bytes */
 521         u8 data[1];
 522 };
 523
 524 /* PCI bus types */
 525 enum i40e_bus_type {
 526         i40e_bus_type_unknown = 0,
 527         i40e_bus_type_pci,
 528         i40e_bus_type_pcix,
 529         i40e_bus_type_pci_express,
 530         i40e_bus_type_reserved
 531 };
 532
 533 /* PCI bus speeds */
 534 enum i40e_bus_speed {
 535         i40e_bus_speed_unknown  = 0,
 536         i40e_bus_speed_33       = 33,
 537         i40e_bus_speed_66       = 66,
 538         i40e_bus_speed_100      = 100,
 539         i40e_bus_speed_120      = 120,
 540         i40e_bus_speed_133      = 133,
 541         i40e_bus_speed_2500     = 2500,
 542         i40e_bus_speed_5000     = 5000,
 543         i40e_bus_speed_8000     = 8000,
 544         i40e_bus_speed_reserved
 545 };
 546
 547 /* PCI bus widths */
 548 enum i40e_bus_width {
 549         i40e_bus_width_unknown  = 0,
 550         i40e_bus_width_pcie_x1  = 1,
 551         i40e_bus_width_pcie_x2  = 2,
 552         i40e_bus_width_pcie_x4  = 4,
 553         i40e_bus_width_pcie_x8  = 8,
 554         i40e_bus_width_32       = 32,
 555         i40e_bus_width_64       = 64,
 556         i40e_bus_width_reserved
 557 };
 558
 559 /* Bus parameters */
 560 struct i40e_bus_info {
 561         enum i40e_bus_speed speed;
 562         enum i40e_bus_width width;
 563         enum i40e_bus_type type;
 564
 565         u16 func;
 566         u16 device;
 567         u16 lan_id;
 568         u16 bus_id;
 569 };
 570
 571 /* Flow control (FC) parameters */
 572 struct i40e_fc_info {
 573         enum i40e_fc_mode current_mode; /* FC mode in effect */
 574         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 575 };
 576
 577 #define I40E_MAX_TRAFFIC_CLASS          8
 578 #define I40E_MAX_USER_PRIORITY          8
 579 #define I40E_DCBX_MAX_APPS              32
 580 #define I40E_LLDPDU_SIZE                1500
 581 #define I40E_TLV_STATUS_OPER            0x1
 582 #define I40E_TLV_STATUS_SYNC            0x2
 583 #define I40E_TLV_STATUS_ERR             0x4
 584 #define I40E_CEE_OPER_MAX_APPS          3
 585 #define I40E_APP_PROTOID_FCOE           0x8906
 586 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 587 #define I40E_APP_PROTOID_FIP            0x8914
 588 #define I40E_APP_SEL_ETHTYPE            0x1
 589 #define I40E_APP_SEL_TCPIP              0x2
 590 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 591 #define I40E_CEE_APP_SEL_TCPIP          0x1
 592
 593 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 594 struct i40e_dcb_ets_config {
 595         u8 willing;
 596         u8 cbs;
 597         u8 maxtcs;
 598         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 599         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 600         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 601 };
 602
 603 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 604 struct i40e_dcb_pfc_config {
 605         u8 willing;
 606         u8 mbc;
 607         u8 pfccap;
 608         u8 pfcenable;
 609 };
 610
 611 /* CEE or IEEE 802.1Qaz Application Priority data */
 612 struct i40e_dcb_app_priority_table {
 613         u8  priority;
 614         u8  selector;
 615         u16 protocolid;
 616 };
 617
 618 struct i40e_dcbx_config {
 619         u8  dcbx_mode;
 620 #define I40E_DCBX_MODE_CEE      0x1
 621 #define I40E_DCBX_MODE_IEEE     0x2
 622         u8  app_mode;
 623 #define I40E_DCBX_APPS_NON_WILLING      0x1
 624         u32 numapps;
 625         u32 tlv_status; /* CEE mode TLV status */
 626         struct i40e_dcb_ets_config etscfg;
 627         struct i40e_dcb_ets_config etsrec;
 628         struct i40e_dcb_pfc_config pfc;
 629         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 630 };
 631
 632 /* Port hardware description */
 633 struct i40e_hw {
 634         u8 *hw_addr;
 635         void *back;
 636
 637         /* subsystem structs */
 638         struct i40e_phy_info phy;
 639         struct i40e_mac_info mac;
 640         struct i40e_bus_info bus;
 641         struct i40e_nvm_info nvm;
 642         struct i40e_fc_info fc;
 643
 644         /* pci info */
 645         u16 device_id;
 646         u16 vendor_id;
 647         u16 subsystem_device_id;
 648         u16 subsystem_vendor_id;
 649         u8 revision_id;
 650         u8 port;
 651         bool adapter_stopped;
 652
 653         /* capabilities for entire device and PCI func */
 654         struct i40e_hw_capabilities dev_caps;
 655         struct i40e_hw_capabilities func_caps;
 656
 657         /* Flow Director shared filter space */
 658         u16 fdir_shared_filter_count;
 659
 660         /* device profile info */
 661         u8  pf_id;
 662         u16 main_vsi_seid;
 663
 664         /* for multi-function MACs */
 665         u16 partition_id;
 666         u16 num_partitions;
 667         u16 num_ports;
 668
 669         /* Closest numa node to the device */
 670         u16 numa_node;
 671
 672         /* Admin Queue info */
 673         struct i40e_adminq_info aq;
 674
 675         /* state of nvm update process */
 676         enum i40e_nvmupd_state nvmupd_state;
 677         struct i40e_aq_desc nvm_wb_desc;
 678         struct i40e_virt_mem nvm_buff;
 679         bool nvm_release_on_done;
 680         u16 nvm_wait_opcode;
 681
 682         /* HMC info */
 683         struct i40e_hmc_info hmc; /* HMC info struct */
 684
 685         /* LLDP/DCBX Status */
 686         u16 dcbx_status;
 687
 688         /* DCBX info */
 689         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 690         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 691         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 692
 693 #ifdef X722_SUPPORT
 694         /* WoL and proxy support */
 695         u16 num_wol_proxy_filters;
 696         u16 wol_proxy_vsi_seid;
 697
 698 #endif
 699 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 700         u64 flags;
 701
 702         /* debug mask */
 703         u32 debug_mask;
 704 #ifndef I40E_NDIS_SUPPORT
 705         char err_str[16];
 706 #endif /* I40E_NDIS_SUPPORT */
 707 };
 708
 709 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 710 {
 711 #ifdef X722_SUPPORT
 712         return (hw->mac.type == I40E_MAC_VF ||
 713                 hw->mac.type == I40E_MAC_X722_VF);
 714 #else
 715         return hw->mac.type == I40E_MAC_VF;
 716 #endif
 717 }
 718
 719 struct i40e_driver_version {
 720         u8 major_version;
 721         u8 minor_version;
 722         u8 build_version;
 723         u8 subbuild_version;
 724         u8 driver_string[32];
 725 };
 726
 727 /* RX Descriptors */
 728 union i40e_16byte_rx_desc {
 729         struct {
 730                 __le64 pkt_addr; /* Packet buffer address */
 731                 __le64 hdr_addr; /* Header buffer address */
 732         } read;
 733         struct {
 734                 struct {
 735                         struct {
 736                                 union {
 737                                         __le16 mirroring_status;
 738                                         __le16 fcoe_ctx_id;
 739                                 } mirr_fcoe;
 740                                 __le16 l2tag1;
 741                         } lo_dword;
 742                         union {
 743                                 __le32 rss; /* RSS Hash */
 744                                 __le32 fd_id; /* Flow director filter id */
 745                                 __le32 fcoe_param; /* FCoE DDP Context id */
 746                         } hi_dword;
 747                 } qword0;
 748                 struct {
 749                         /* ext status/error/pktype/length */
 750                         __le64 status_error_len;
 751                 } qword1;
 752         } wb;  /* writeback */
 753 };
 754
 755 union i40e_32byte_rx_desc {
 756         struct {
 757                 __le64  pkt_addr; /* Packet buffer address */
 758                 __le64  hdr_addr; /* Header buffer address */
 759                         /* bit 0 of hdr_buffer_addr is DD bit */
 760                 __le64  rsvd1;
 761                 __le64  rsvd2;
 762         } read;
 763         struct {
 764                 struct {
 765                         struct {
 766                                 union {
 767                                         __le16 mirroring_status;
 768                                         __le16 fcoe_ctx_id;
 769                                 } mirr_fcoe;
 770                                 __le16 l2tag1;
 771                         } lo_dword;
 772                         union {
 773                                 __le32 rss; /* RSS Hash */
 774                                 __le32 fcoe_param; /* FCoE DDP Context id */
 775                                 /* Flow director filter id in case of
 776                                  * Programming status desc WB
 777                                  */
 778                                 __le32 fd_id;
 779                         } hi_dword;
 780                 } qword0;
 781                 struct {
 782                         /* status/error/pktype/length */
 783                         __le64 status_error_len;
 784                 } qword1;
 785                 struct {
 786                         __le16 ext_status; /* extended status */
 787                         __le16 rsvd;
 788                         __le16 l2tag2_1;
 789                         __le16 l2tag2_2;
 790                 } qword2;
 791                 struct {
 792                         union {
 793                                 __le32 flex_bytes_lo;
 794                                 __le32 pe_status;
 795                         } lo_dword;
 796                         union {
 797                                 __le32 flex_bytes_hi;
 798                                 __le32 fd_id;
 799                         } hi_dword;
 800                 } qword3;
 801         } wb;  /* writeback */
 802 };
 803
 804 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 805 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 806                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 807 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 808 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 809                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 810
 811 enum i40e_rx_desc_status_bits {
 812         /* Note: These are predefined bit offsets */
 813         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 814         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 815         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 816         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 817         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 818         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 819         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 820 #ifdef X722_SUPPORT
 821         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 822 #else
 823         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 824 #endif
 825
 826         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 827         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 828         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 829         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 830         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 831         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 832 #ifdef X722_SUPPORT
 833         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 834 #else
 835         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 836 #endif
 837         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 838 };
 839
 840 #define I40E_RXD_QW1_STATUS_SHIFT       0
 841 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 842                                          I40E_RXD_QW1_STATUS_SHIFT)
 843
 844 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 845 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 846                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 847
 848 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 849 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 850
 851 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 852 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 853                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 854
 855 enum i40e_rx_desc_fltstat_values {
 856         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 857         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 858         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 859         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 860 };
 861
 862 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 863 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 864 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 865 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 866
 867 #define I40E_RXD_QW1_ERROR_SHIFT        19
 868 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 869
 870 enum i40e_rx_desc_error_bits {
 871         /* Note: These are predefined bit offsets */
 872         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 873         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 874         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 875         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 876         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 877         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 878         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 879         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 880         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 881 };
 882
 883 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 884         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 885         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 886         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 887         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 888         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 889 };
 890
 891 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 892 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 893
 894 /* Packet type non-ip values */
 895 enum i40e_rx_l2_ptype {
 896         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 897         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 898         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 899         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 900         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 901         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 902         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 903         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 904         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 905         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 906         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 907         I40E_RX_PTYPE_L2_ARP                            = 11,
 908         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 909         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 910         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 911         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 912         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 913         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 914         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 915         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 916         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 917         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 918         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 919         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 920         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 921         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 922 };
 923
 924 struct i40e_rx_ptype_decoded {
 925         u32 ptype:8;
 926         u32 known:1;
 927         u32 outer_ip:1;
 928         u32 outer_ip_ver:1;
 929         u32 outer_frag:1;
 930         u32 tunnel_type:3;
 931         u32 tunnel_end_prot:2;
 932         u32 tunnel_end_frag:1;
 933         u32 inner_prot:4;
 934         u32 payload_layer:3;
 935 };
 936
 937 enum i40e_rx_ptype_outer_ip {
 938         I40E_RX_PTYPE_OUTER_L2  = 0,
 939         I40E_RX_PTYPE_OUTER_IP  = 1
 940 };
 941
 942 enum i40e_rx_ptype_outer_ip_ver {
 943         I40E_RX_PTYPE_OUTER_NONE        = 0,
 944         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 945         I40E_RX_PTYPE_OUTER_IPV6        = 1
 946 };
 947
 948 enum i40e_rx_ptype_outer_fragmented {
 949         I40E_RX_PTYPE_NOT_FRAG  = 0,
 950         I40E_RX_PTYPE_FRAG      = 1
 951 };
 952
 953 enum i40e_rx_ptype_tunnel_type {
 954         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 955         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 956         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 957         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 958         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 959 };
 960
 961 enum i40e_rx_ptype_tunnel_end_prot {
 962         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 963         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 964         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 965 };
 966
 967 enum i40e_rx_ptype_inner_prot {
 968         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 969         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 970         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 971         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 972         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 973         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 974 };
 975
 976 enum i40e_rx_ptype_payload_layer {
 977         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 978         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 979         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 980         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 981 };
 982
 983 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 984 #define I40E_RX_PTYPE_SHIFT             56
 985
 986 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 987 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 988                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 989
 990 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 991 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 992                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 993
 994 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 995 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 996
 997 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 998 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 999
1000 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1001 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1002                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1003
1004 enum i40e_rx_desc_ext_status_bits {
1005         /* Note: These are predefined bit offsets */
1006         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1007         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1008         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1009         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1010         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1011         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1012         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1013 };
1014
1015 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1016 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1017
1018 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1019 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1020
1021 enum i40e_rx_desc_pe_status_bits {
1022         /* Note: These are predefined bit offsets */
1023         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1024         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1025         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1026         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1027         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1028         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1029         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1030         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1031         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1032 };
1033
1034 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1035 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1036
1037 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1038 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1039                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1040
1041 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1042 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1043                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1044
1045 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1046 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1047                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1048
1049 enum i40e_rx_prog_status_desc_status_bits {
1050         /* Note: These are predefined bit offsets */
1051         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1052         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1053 };
1054
1055 enum i40e_rx_prog_status_desc_prog_id_masks {
1056         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1057         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1058         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1059 };
1060
1061 enum i40e_rx_prog_status_desc_error_bits {
1062         /* Note: These are predefined bit offsets */
1063         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1064         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1065         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1066         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1067 };
1068
1069 #define I40E_TWO_BIT_MASK       0x3
1070 #define I40E_THREE_BIT_MASK     0x7
1071 #define I40E_FOUR_BIT_MASK      0xF
1072 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1073
1074 /* TX Descriptor */
1075 struct i40e_tx_desc {
1076         __le64 buffer_addr; /* Address of descriptor's data buf */
1077         __le64 cmd_type_offset_bsz;
1078 };
1079
1080 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1081 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1082
1083 enum i40e_tx_desc_dtype_value {
1084         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1085         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1086         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1087         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1088         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1089         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1090         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1091         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1092         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1093         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1094 };
1095
1096 #define I40E_TXD_QW1_CMD_SHIFT  4
1097 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1098
1099 enum i40e_tx_desc_cmd_bits {
1100         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1101         I40E_TX_DESC_CMD_RS                     = 0x0002,
1102         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1103         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1104         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1105         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1106         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1107         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1108         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1109         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1110         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1111         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1112         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1113         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1114         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1115         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1116         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1117         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1118 };
1119
1120 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1121 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1122                                          I40E_TXD_QW1_OFFSET_SHIFT)
1123
1124 enum i40e_tx_desc_length_fields {
1125         /* Note: These are predefined bit offsets */
1126         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1127         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1128         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1129 };
1130
1131 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1132 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1133 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1134 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1135
1136 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1137 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1138                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1139
1140 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1141 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1142
1143 /* Context descriptors */
1144 struct i40e_tx_context_desc {
1145         __le32 tunneling_params;
1146         __le16 l2tag2;
1147         __le16 rsvd;
1148         __le64 type_cmd_tso_mss;
1149 };
1150
1151 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1152 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1153
1154 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1155 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1156
1157 enum i40e_tx_ctx_desc_cmd_bits {
1158         I40E_TX_CTX_DESC_TSO            = 0x01,
1159         I40E_TX_CTX_DESC_TSYN           = 0x02,
1160         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1161         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1162         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1163         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1164         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1165         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1166         I40E_TX_CTX_DESC_SWPE           = 0x40
1167 };
1168
1169 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1170 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1171                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1172
1173 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1174 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1175                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1176
1177 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1178 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1179
1180 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1181 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1182                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1183
1184 enum i40e_tx_ctx_desc_eipt_offload {
1185         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1186         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1187         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1188         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1189 };
1190
1191 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1192 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1193                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1194
1195 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1196 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1197
1198 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1199 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1200
1201 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1202 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1203
1204 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1205
1206 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1207 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1208                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1209
1210 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1211 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1212                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1213
1214 #ifdef X722_SUPPORT
1215 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1216 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1217 #endif
1218 struct i40e_nop_desc {
1219         __le64 rsvd;
1220         __le64 dtype_cmd;
1221 };
1222
1223 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1224 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1225
1226 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1227 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1228
1229 enum i40e_tx_nop_desc_cmd_bits {
1230         /* Note: These are predefined bit offsets */
1231         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1232         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1233         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1234 };
1235
1236 struct i40e_filter_program_desc {
1237         __le32 qindex_flex_ptype_vsi;
1238         __le32 rsvd;
1239         __le32 dtype_cmd_cntindex;
1240         __le32 fd_id;
1241 };
1242 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1243 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1244                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1245 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1246 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1247                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1248 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1249 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1250                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1251
1252 /* Packet Classifier Types for filters */
1253 enum i40e_filter_pctype {
1254 #ifdef X722_SUPPORT
1255         /* Note: Values 0-28 are reserved for future use.
1256          * Value 29, 30, 32 are not supported on XL710 and X710.
1257          */
1258         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1259         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1260 #else
1261         /* Note: Values 0-30 are reserved for future use */
1262 #endif
1263         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1264 #ifdef X722_SUPPORT
1265         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1266 #else
1267         /* Note: Value 32 is reserved for future use */
1268 #endif
1269         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1270         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1271         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1272         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1273 #ifdef X722_SUPPORT
1274         /* Note: Values 37-38 are reserved for future use.
1275          * Value 39, 40, 42 are not supported on XL710 and X710.
1276          */
1277         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1278         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1279 #else
1280         /* Note: Values 37-40 are reserved for future use */
1281 #endif
1282         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1283 #ifdef X722_SUPPORT
1284         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1285 #endif
1286         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1287         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1288         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1289         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1290         /* Note: Value 47 is reserved for future use */
1291         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1292         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1293         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1294         /* Note: Values 51-62 are reserved for future use */
1295         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1296 };
1297
1298 enum i40e_filter_program_desc_dest {
1299         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1300         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1301         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1302 };
1303
1304 enum i40e_filter_program_desc_fd_status {
1305         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1306         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1307         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1308         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1309 };
1310
1311 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1312 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1313                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1314
1315 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1316 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1317
1318 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1319 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1320                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1321
1322 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1323 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1324
1325 enum i40e_filter_program_desc_pcmd {
1326         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1327         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1328 };
1329
1330 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1331 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1332
1333 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1334 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1335
1336 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1337                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1338 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1339                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1340 #ifdef X722_SUPPORT
1341
1342 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1343                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1344 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1345 #endif
1346
1347 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1348 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1349                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1350
1351 enum i40e_filter_type {
1352         I40E_FLOW_DIRECTOR_FLTR = 0,
1353         I40E_PE_QUAD_HASH_FLTR = 1,
1354         I40E_ETHERTYPE_FLTR,
1355         I40E_FCOE_CTX_FLTR,
1356         I40E_MAC_VLAN_FLTR,
1357         I40E_HASH_FLTR
1358 };
1359
1360 struct i40e_vsi_context {
1361         u16 seid;
1362         u16 uplink_seid;
1363         u16 vsi_number;
1364         u16 vsis_allocated;
1365         u16 vsis_unallocated;
1366         u16 flags;
1367         u8 pf_num;
1368         u8 vf_num;
1369         u8 connection_type;
1370         struct i40e_aqc_vsi_properties_data info;
1371 };
1372
1373 struct i40e_veb_context {
1374         u16 seid;
1375         u16 uplink_seid;
1376         u16 veb_number;
1377         u16 vebs_allocated;
1378         u16 vebs_unallocated;
1379         u16 flags;
1380         struct i40e_aqc_get_veb_parameters_completion info;
1381 };
1382
1383 /* Statistics collected by each port, VSI, VEB, and S-channel */
1384 struct i40e_eth_stats {
1385         u64 rx_bytes;                   /* gorc */
1386         u64 rx_unicast;                 /* uprc */
1387         u64 rx_multicast;               /* mprc */
1388         u64 rx_broadcast;               /* bprc */
1389         u64 rx_discards;                /* rdpc */
1390         u64 rx_unknown_protocol;        /* rupp */
1391         u64 tx_bytes;                   /* gotc */
1392         u64 tx_unicast;                 /* uptc */
1393         u64 tx_multicast;               /* mptc */
1394         u64 tx_broadcast;               /* bptc */
1395         u64 tx_discards;                /* tdpc */
1396         u64 tx_errors;                  /* tepc */
1397 };
1398
1399 /* Statistics collected per VEB per TC */
1400 struct i40e_veb_tc_stats {
1401         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1402         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1403         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1404         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1405 };
1406
1407 /* Statistics collected per function for FCoE */
1408 struct i40e_fcoe_stats {
1409         u64 rx_fcoe_packets;            /* fcoeprc */
1410         u64 rx_fcoe_dwords;             /* focedwrc */
1411         u64 rx_fcoe_dropped;            /* fcoerpdc */
1412         u64 tx_fcoe_packets;            /* fcoeptc */
1413         u64 tx_fcoe_dwords;             /* focedwtc */
1414         u64 fcoe_bad_fccrc;             /* fcoecrc */
1415         u64 fcoe_last_error;            /* fcoelast */
1416         u64 fcoe_ddp_count;             /* fcoeddpc */
1417 };
1418
1419 /* offset to per function FCoE statistics block */
1420 #define I40E_FCOE_VF_STAT_OFFSET        0
1421 #define I40E_FCOE_PF_STAT_OFFSET        128
1422 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1423
1424 /* Statistics collected by the MAC */
1425 struct i40e_hw_port_stats {
1426         /* eth stats collected by the port */
1427         struct i40e_eth_stats eth;
1428
1429         /* additional port specific stats */
1430         u64 tx_dropped_link_down;       /* tdold */
1431         u64 crc_errors;                 /* crcerrs */
1432         u64 illegal_bytes;              /* illerrc */
1433         u64 error_bytes;                /* errbc */
1434         u64 mac_local_faults;           /* mlfc */
1435         u64 mac_remote_faults;          /* mrfc */
1436         u64 rx_length_errors;           /* rlec */
1437         u64 link_xon_rx;                /* lxonrxc */
1438         u64 link_xoff_rx;               /* lxoffrxc */
1439         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1440         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1441         u64 link_xon_tx;                /* lxontxc */
1442         u64 link_xoff_tx;               /* lxofftxc */
1443         u64 priority_xon_tx[8];         /* pxontxc[8] */
1444         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1445         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1446         u64 rx_size_64;                 /* prc64 */
1447         u64 rx_size_127;                /* prc127 */
1448         u64 rx_size_255;                /* prc255 */
1449         u64 rx_size_511;                /* prc511 */
1450         u64 rx_size_1023;               /* prc1023 */
1451         u64 rx_size_1522;               /* prc1522 */
1452         u64 rx_size_big;                /* prc9522 */
1453         u64 rx_undersize;               /* ruc */
1454         u64 rx_fragments;               /* rfc */
1455         u64 rx_oversize;                /* roc */
1456         u64 rx_jabber;                  /* rjc */
1457         u64 tx_size_64;                 /* ptc64 */
1458         u64 tx_size_127;                /* ptc127 */
1459         u64 tx_size_255;                /* ptc255 */
1460         u64 tx_size_511;                /* ptc511 */
1461         u64 tx_size_1023;               /* ptc1023 */
1462         u64 tx_size_1522;               /* ptc1522 */
1463         u64 tx_size_big;                /* ptc9522 */
1464         u64 mac_short_packet_dropped;   /* mspdc */
1465         u64 checksum_error;             /* xec */
1466         /* flow director stats */
1467         u64 fd_atr_match;
1468         u64 fd_sb_match;
1469         u64 fd_atr_tunnel_match;
1470         u32 fd_atr_status;
1471         u32 fd_sb_status;
1472         /* EEE LPI */
1473         u32 tx_lpi_status;
1474         u32 rx_lpi_status;
1475         u64 tx_lpi_count;               /* etlpic */
1476         u64 rx_lpi_count;               /* erlpic */
1477 };
1478
1479 /* Checksum and Shadow RAM pointers */
1480 #define I40E_SR_NVM_CONTROL_WORD                0x00
1481 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1482 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1483 #define I40E_SR_OPTION_ROM_PTR                  0x05
1484 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1485 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1486 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1487 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1488 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1489 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1490 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1491 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1492 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1493 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1494 #define I40E_SR_PBA_FLAGS                       0x15
1495 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1496 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1497 #define I40E_NVM_OEM_VER_OFF                    0x83
1498 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1499 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1500 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1501 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1502 #define I40E_SR_NVM_MAP_VERSION                 0x29
1503 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1504 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1505 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1506 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1507 #define I40E_SR_VPD_PTR                         0x2F
1508 #define I40E_SR_PXE_SETUP_PTR                   0x30
1509 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1510 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1511 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1512 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1513 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1514 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1515 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1516 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1517 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1518 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1519 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1520 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1521 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1522 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1523 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1524 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1525 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1526 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1527
1528 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1529 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1530 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1531 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1532 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1533
1534 /* Shadow RAM related */
1535 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1536 #define I40E_SR_BUF_ALIGNMENT           4096
1537 #define I40E_SR_WORDS_IN_1KB            512
1538 /* Checksum should be calculated such that after adding all the words,
1539  * including the checksum word itself, the sum should be 0xBABA.
1540  */
1541 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1542
1543 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1544
1545 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1546
1547 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1548         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1549         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1550         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1551         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1552         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1553         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1554         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1555         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1556         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1557         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1558         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1559         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1560         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1561 };
1562
1563 /* FCoE DIF/DIX Context descriptor */
1564 struct i40e_fcoe_difdix_context_desc {
1565         __le64 flags_buff0_buff1_ref;
1566         __le64 difapp_msk_bias;
1567 };
1568
1569 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1570 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1571                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1572
1573 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1574         /* 2 BITS */
1575         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1576         /* 1 BIT  */
1577         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1578         /* 1 BIT  */
1579         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1580         /* 2 BITS */
1581         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1582         /* 2 BITS */
1583         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1584         /* 2 BITS */
1585         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1586         /* 2 BITS */
1587         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1588         /* 2 BITS */
1589         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1590         /* 2 BITS */
1591         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1592         /* 2 BITS */
1593         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1594         /* 2 BITS */
1595         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1596         /* 1 BIT  */
1597         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1598         /* 1 BIT  */
1599         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1600         /* 2 BITS */
1601         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1602         /* 2 BITS */
1603         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1604         /* 2 BITS */
1605         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1606         /* 2 BITS */
1607         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1608         /* 1 BIT  */
1609         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1610         /* 1 BIT  */
1611         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1612         /* 1 BIT */
1613         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1614         /* 1 BIT */
1615         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1616 };
1617
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1619 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1620                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1621
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1623 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1624                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1625
1626 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1627 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1628                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1629
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1631 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1632                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1633
1634 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1635 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1636                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1637
1638 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1639 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1640                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1641
1642 /* FCoE DIF/DIX Buffers descriptor */
1643 struct i40e_fcoe_difdix_buffers_desc {
1644         __le64 buff_addr0;
1645         __le64 buff_addr1;
1646 };
1647
1648 /* FCoE DDP Context descriptor */
1649 struct i40e_fcoe_ddp_context_desc {
1650         __le64 rsvd;
1651         __le64 type_cmd_foff_lsize;
1652 };
1653
1654 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1655 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1656                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1657
1658 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1659 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1660                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1661
1662 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1663         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1664         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1665         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1666         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1667         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1668         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1669 };
1670
1671 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1672 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1673                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1674
1675 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1676 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1677                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1678
1679 /* FCoE DDP/DWO Queue Context descriptor */
1680 struct i40e_fcoe_queue_context_desc {
1681         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1682         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1683 };
1684
1685 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1686 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1687                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1688
1689 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1690 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1691                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1692
1693 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1694 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1695                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1696
1697 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1698 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1699                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1700
1701 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1702         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1703         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1704 };
1705
1706 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1707 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1708                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1709
1710 /* FCoE DDP/DWO Filter Context descriptor */
1711 struct i40e_fcoe_filter_context_desc {
1712         __le32 param;
1713         __le16 seqn;
1714
1715         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1716         __le16 rsvd_dmaindx;
1717
1718         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1719         __le64 flags_rsvd_lanq;
1720 };
1721
1722 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1723 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1724                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1725
1726 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1727         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1728         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1729         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1730         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1731         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1732         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1733 };
1734
1735 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1736 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1737                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1738
1739 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1740 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1741                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1742
1743 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1744 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1745                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1746
1747 enum i40e_switch_element_types {
1748         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1749         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1750         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1751         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1752         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1753         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1754         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1755         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1756         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1757 };
1758
1759 /* Supported EtherType filters */
1760 enum i40e_ether_type_index {
1761         I40E_ETHER_TYPE_1588            = 0,
1762         I40E_ETHER_TYPE_FIP             = 1,
1763         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1764         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1765         I40E_ETHER_TYPE_LLDP            = 4,
1766         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1767         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1768         I40E_ETHER_TYPE_QCN_CNM         = 7,
1769         I40E_ETHER_TYPE_8021X           = 8,
1770         I40E_ETHER_TYPE_ARP             = 9,
1771         I40E_ETHER_TYPE_RSV1            = 10,
1772         I40E_ETHER_TYPE_RSV2            = 11,
1773 };
1774
1775 /* Filter context base size is 1K */
1776 #define I40E_HASH_FILTER_BASE_SIZE      1024
1777 /* Supported Hash filter values */
1778 enum i40e_hash_filter_size {
1779         I40E_HASH_FILTER_SIZE_1K        = 0,
1780         I40E_HASH_FILTER_SIZE_2K        = 1,
1781         I40E_HASH_FILTER_SIZE_4K        = 2,
1782         I40E_HASH_FILTER_SIZE_8K        = 3,
1783         I40E_HASH_FILTER_SIZE_16K       = 4,
1784         I40E_HASH_FILTER_SIZE_32K       = 5,
1785         I40E_HASH_FILTER_SIZE_64K       = 6,
1786         I40E_HASH_FILTER_SIZE_128K      = 7,
1787         I40E_HASH_FILTER_SIZE_256K      = 8,
1788         I40E_HASH_FILTER_SIZE_512K      = 9,
1789         I40E_HASH_FILTER_SIZE_1M        = 10,
1790 };
1791
1792 /* DMA context base size is 0.5K */
1793 #define I40E_DMA_CNTX_BASE_SIZE         512
1794 /* Supported DMA context values */
1795 enum i40e_dma_cntx_size {
1796         I40E_DMA_CNTX_SIZE_512          = 0,
1797         I40E_DMA_CNTX_SIZE_1K           = 1,
1798         I40E_DMA_CNTX_SIZE_2K           = 2,
1799         I40E_DMA_CNTX_SIZE_4K           = 3,
1800         I40E_DMA_CNTX_SIZE_8K           = 4,
1801         I40E_DMA_CNTX_SIZE_16K          = 5,
1802         I40E_DMA_CNTX_SIZE_32K          = 6,
1803         I40E_DMA_CNTX_SIZE_64K          = 7,
1804         I40E_DMA_CNTX_SIZE_128K         = 8,
1805         I40E_DMA_CNTX_SIZE_256K         = 9,
1806 };
1807
1808 /* Supported Hash look up table (LUT) sizes */
1809 enum i40e_hash_lut_size {
1810         I40E_HASH_LUT_SIZE_128          = 0,
1811         I40E_HASH_LUT_SIZE_512          = 1,
1812 };
1813
1814 /* Structure to hold a per PF filter control settings */
1815 struct i40e_filter_control_settings {
1816         /* number of PE Quad Hash filter buckets */
1817         enum i40e_hash_filter_size pe_filt_num;
1818         /* number of PE Quad Hash contexts */
1819         enum i40e_dma_cntx_size pe_cntx_num;
1820         /* number of FCoE filter buckets */
1821         enum i40e_hash_filter_size fcoe_filt_num;
1822         /* number of FCoE DDP contexts */
1823         enum i40e_dma_cntx_size fcoe_cntx_num;
1824         /* size of the Hash LUT */
1825         enum i40e_hash_lut_size hash_lut_size;
1826         /* enable FDIR filters for PF and its VFs */
1827         bool enable_fdir;
1828         /* enable Ethertype filters for PF and its VFs */
1829         bool enable_ethtype;
1830         /* enable MAC/VLAN filters for PF and its VFs */
1831         bool enable_macvlan;
1832 };
1833
1834 /* Structure to hold device level control filter counts */
1835 struct i40e_control_filter_stats {
1836         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1837         u16 etype_used;       /* Used perfect EtherType filters */
1838         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1839         u16 etype_free;       /* Un-used perfect EtherType filters */
1840 };
1841
1842 enum i40e_reset_type {
1843         I40E_RESET_POR          = 0,
1844         I40E_RESET_CORER        = 1,
1845         I40E_RESET_GLOBR        = 2,
1846         I40E_RESET_EMPR         = 3,
1847 };
1848
1849 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1850 #define I40E_NVM_LLDP_CFG_PTR           0xD
1851 struct i40e_lldp_variables {
1852         u16 length;
1853         u16 adminstatus;
1854         u16 msgfasttx;
1855         u16 msgtxinterval;
1856         u16 txparams;
1857         u16 timers;
1858         u16 crc8;
1859 };
1860
1861 /* Offsets into Alternate Ram */
1862 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1863 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1864 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1865 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1866 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1867 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1868
1869 /* Alternate Ram Bandwidth Masks */
1870 #define I40E_ALT_BW_VALUE_MASK          0xFF
1871 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1872 #define I40E_ALT_BW_VALID_MASK          0x80000000
1873
1874 /* RSS Hash Table Size */
1875 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1876
1877 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1878 #define I40E_L3_SRC_SHIFT               47
1879 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1880 #define I40E_L3_V6_SRC_SHIFT            43
1881 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1882 #define I40E_L3_DST_SHIFT               35
1883 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1884 #define I40E_L3_V6_DST_SHIFT            35
1885 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1886 #define I40E_L4_SRC_SHIFT               34
1887 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1888 #define I40E_L4_DST_SHIFT               33
1889 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1890 #define I40E_VERIFY_TAG_SHIFT           31
1891 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1892
1893 #define I40E_FLEX_50_SHIFT              13
1894 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1895 #define I40E_FLEX_51_SHIFT              12
1896 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1897 #define I40E_FLEX_52_SHIFT              11
1898 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1899 #define I40E_FLEX_53_SHIFT              10
1900 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1901 #define I40E_FLEX_54_SHIFT              9
1902 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1903 #define I40E_FLEX_55_SHIFT              8
1904 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1905 #define I40E_FLEX_56_SHIFT              7
1906 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1907 #define I40E_FLEX_57_SHIFT              6
1908 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1909 #endif /* _I40E_TYPE_H_ */