1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
53 /* I40E_MASK is a macro used on 32 bit registers */
54 #define I40E_MASK(mask, shift) (mask << shift)
57 #define I40E_MAX_PF 16
58 #define I40E_MAX_PF_VSI 64
59 #define I40E_MAX_PF_QP 128
60 #define I40E_MAX_VSI_QP 16
61 #define I40E_MAX_VF_VSI 3
62 #define I40E_MAX_CHAINED_RX_BUFFERS 5
63 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
65 /* something less than 1 minute */
66 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
68 /* Max default timeout in ms, */
69 #define I40E_MAX_NVM_TIMEOUT 18000
71 /* Check whether address is multicast. */
72 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
74 /* Check whether an address is broadcast. */
75 #define I40E_IS_BROADCAST(address) \
76 ((((u8 *)(address))[0] == ((u8)0xff)) && \
77 (((u8 *)(address))[1] == ((u8)0xff)))
79 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
80 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
82 /* forward declaration */
84 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
86 #define I40E_ETH_LENGTH_OF_ADDRESS 6
87 /* Data type manipulation macros. */
88 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
89 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
91 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
92 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
94 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
95 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
97 /* Number of Transmit Descriptors must be a multiple of 8. */
98 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
99 /* Number of Receive Descriptors must be a multiple of 32 if
100 * the number of descriptors is greater than 32.
102 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
104 #define I40E_DESC_UNUSED(R) \
105 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
106 (R)->next_to_clean - (R)->next_to_use - 1)
108 /* bitfields for Tx queue mapping in QTX_CTL */
109 #define I40E_QTX_CTL_VF_QUEUE 0x0
110 #define I40E_QTX_CTL_VM_QUEUE 0x1
111 #define I40E_QTX_CTL_PF_QUEUE 0x2
113 /* debug masks - set these bits in hw->debug_mask to control output */
114 enum i40e_debug_mask {
115 I40E_DEBUG_INIT = 0x00000001,
116 I40E_DEBUG_RELEASE = 0x00000002,
118 I40E_DEBUG_LINK = 0x00000010,
119 I40E_DEBUG_PHY = 0x00000020,
120 I40E_DEBUG_HMC = 0x00000040,
121 I40E_DEBUG_NVM = 0x00000080,
122 I40E_DEBUG_LAN = 0x00000100,
123 I40E_DEBUG_FLOW = 0x00000200,
124 I40E_DEBUG_DCB = 0x00000400,
125 I40E_DEBUG_DIAG = 0x00000800,
126 I40E_DEBUG_FD = 0x00001000,
128 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
129 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
130 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
131 I40E_DEBUG_AQ_COMMAND = 0x06000000,
132 I40E_DEBUG_AQ = 0x0F000000,
134 I40E_DEBUG_USER = 0xF0000000,
136 I40E_DEBUG_ALL = 0xFFFFFFFF
140 #define I40E_PCI_LINK_STATUS 0xB2
141 #define I40E_PCI_LINK_WIDTH 0x3F0
142 #define I40E_PCI_LINK_WIDTH_1 0x10
143 #define I40E_PCI_LINK_WIDTH_2 0x20
144 #define I40E_PCI_LINK_WIDTH_4 0x40
145 #define I40E_PCI_LINK_WIDTH_8 0x80
146 #define I40E_PCI_LINK_SPEED 0xF
147 #define I40E_PCI_LINK_SPEED_2500 0x1
148 #define I40E_PCI_LINK_SPEED_5000 0x2
149 #define I40E_PCI_LINK_SPEED_8000 0x3
152 enum i40e_memset_type {
158 enum i40e_memcpy_type {
159 I40E_NONDMA_TO_NONDMA = 0,
165 /* These are structs for managing the hardware information and the operations.
166 * The structures of function pointers are filled out at init time when we
167 * know for sure exactly which hardware we're working with. This gives us the
168 * flexibility of using the same main driver code but adapting to slightly
169 * different hardware needs as new parts are developed. For this architecture,
170 * the Firmware and AdminQ are intended to insulate the driver from most of the
171 * future changes, but these structures will also do part of the job.
174 I40E_MAC_UNKNOWN = 0,
181 enum i40e_media_type {
182 I40E_MEDIA_TYPE_UNKNOWN = 0,
183 I40E_MEDIA_TYPE_FIBER,
184 I40E_MEDIA_TYPE_BASET,
185 I40E_MEDIA_TYPE_BACKPLANE,
188 I40E_MEDIA_TYPE_VIRTUAL
200 enum i40e_set_fc_aq_failures {
201 I40E_SET_FC_AQ_FAIL_NONE = 0,
202 I40E_SET_FC_AQ_FAIL_GET = 1,
203 I40E_SET_FC_AQ_FAIL_SET = 2,
204 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
205 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
217 I40E_VSI_TYPE_UNKNOWN
220 enum i40e_queue_type {
221 I40E_QUEUE_TYPE_RX = 0,
223 I40E_QUEUE_TYPE_PE_CEQ,
224 I40E_QUEUE_TYPE_UNKNOWN
227 struct i40e_link_status {
228 enum i40e_aq_phy_type phy_type;
229 enum i40e_aq_link_speed link_speed;
234 /* is Link Status Event notification to SW enabled */
242 struct i40e_phy_info {
243 struct i40e_link_status link_info;
244 struct i40e_link_status link_info_old;
245 u32 autoneg_advertised;
249 enum i40e_media_type media_type;
252 #define I40E_HW_CAP_MAX_GPIO 30
253 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
254 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
256 /* Capabilities of a PF or a VF or the whole device */
257 struct i40e_hw_capabilities {
259 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
260 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
261 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
269 bool evb_802_1_qbg; /* Edge Virtual Bridging */
270 bool evb_802_1_qbh; /* Bridge Port Extension */
273 bool iscsi; /* Indicates iSCSI enabled */
279 u32 fd_filters_guaranteed;
280 u32 fd_filters_best_effort;
283 u32 rss_table_entry_width;
284 bool led[I40E_HW_CAP_MAX_GPIO];
285 bool sdp[I40E_HW_CAP_MAX_GPIO];
287 u32 num_flow_director_filters;
294 u32 num_msix_vectors;
295 u32 num_msix_vectors_vf;
305 struct i40e_mac_info {
306 enum i40e_mac_type type;
307 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
308 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
309 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
310 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
314 enum i40e_aq_resources_ids {
315 I40E_NVM_RESOURCE_ID = 1
318 enum i40e_aq_resource_access_type {
319 I40E_RESOURCE_READ = 1,
323 struct i40e_nvm_info {
324 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
325 u32 timeout; /* [ms] */
326 u16 sr_size; /* Shadow RAM size in words */
327 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
328 u16 version; /* NVM package version */
329 u32 eetrack; /* NVM data version */
332 /* definitions used in NVM update support */
334 enum i40e_nvmupd_cmd {
336 I40E_NVMUPD_READ_CON,
337 I40E_NVMUPD_READ_SNT,
338 I40E_NVMUPD_READ_LCB,
340 I40E_NVMUPD_WRITE_ERA,
341 I40E_NVMUPD_WRITE_CON,
342 I40E_NVMUPD_WRITE_SNT,
343 I40E_NVMUPD_WRITE_LCB,
344 I40E_NVMUPD_WRITE_SA,
345 I40E_NVMUPD_CSUM_CON,
347 I40E_NVMUPD_CSUM_LCB,
350 enum i40e_nvmupd_state {
351 I40E_NVMUPD_STATE_INIT,
352 I40E_NVMUPD_STATE_READING,
353 I40E_NVMUPD_STATE_WRITING
356 /* nvm_access definition and its masks/shifts need to be accessible to
357 * application, core driver, and shared code. Where is the right file?
359 #define I40E_NVM_READ 0xB
360 #define I40E_NVM_WRITE 0xC
362 #define I40E_NVM_MOD_PNT_MASK 0xFF
364 #define I40E_NVM_TRANS_SHIFT 8
365 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
366 #define I40E_NVM_CON 0x0
367 #define I40E_NVM_SNT 0x1
368 #define I40E_NVM_LCB 0x2
369 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
370 #define I40E_NVM_ERA 0x4
371 #define I40E_NVM_CSUM 0x8
373 #define I40E_NVM_ADAPT_SHIFT 16
374 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
376 #define I40E_NVMUPD_MAX_DATA 4096
377 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
379 struct i40e_nvm_access {
382 u32 offset; /* in bytes */
383 u32 data_size; /* in bytes */
389 i40e_bus_type_unknown = 0,
392 i40e_bus_type_pci_express,
393 i40e_bus_type_reserved
397 enum i40e_bus_speed {
398 i40e_bus_speed_unknown = 0,
399 i40e_bus_speed_33 = 33,
400 i40e_bus_speed_66 = 66,
401 i40e_bus_speed_100 = 100,
402 i40e_bus_speed_120 = 120,
403 i40e_bus_speed_133 = 133,
404 i40e_bus_speed_2500 = 2500,
405 i40e_bus_speed_5000 = 5000,
406 i40e_bus_speed_8000 = 8000,
407 i40e_bus_speed_reserved
411 enum i40e_bus_width {
412 i40e_bus_width_unknown = 0,
413 i40e_bus_width_pcie_x1 = 1,
414 i40e_bus_width_pcie_x2 = 2,
415 i40e_bus_width_pcie_x4 = 4,
416 i40e_bus_width_pcie_x8 = 8,
417 i40e_bus_width_32 = 32,
418 i40e_bus_width_64 = 64,
419 i40e_bus_width_reserved
423 struct i40e_bus_info {
424 enum i40e_bus_speed speed;
425 enum i40e_bus_width width;
426 enum i40e_bus_type type;
433 /* Flow control (FC) parameters */
434 struct i40e_fc_info {
435 enum i40e_fc_mode current_mode; /* FC mode in effect */
436 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
439 #define I40E_MAX_TRAFFIC_CLASS 8
440 #define I40E_MAX_USER_PRIORITY 8
441 #define I40E_DCBX_MAX_APPS 32
442 #define I40E_LLDPDU_SIZE 1500
443 #define I40E_TLV_STATUS_OPER 0x1
444 #define I40E_TLV_STATUS_SYNC 0x2
445 #define I40E_TLV_STATUS_ERR 0x4
446 #define I40E_CEE_OPER_MAX_APPS 3
447 #define I40E_APP_PROTOID_FCOE 0x8906
448 #define I40E_APP_PROTOID_ISCSI 0x0cbc
449 #define I40E_APP_PROTOID_FIP 0x8914
450 #define I40E_APP_SEL_ETHTYPE 0x1
451 #define I40E_APP_SEL_TCPIP 0x2
453 /* CEE or IEEE 802.1Qaz ETS Configuration data */
454 struct i40e_dcb_ets_config {
458 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
459 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
460 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
463 /* CEE or IEEE 802.1Qaz PFC Configuration data */
464 struct i40e_dcb_pfc_config {
471 /* CEE or IEEE 802.1Qaz Application Priority data */
472 struct i40e_dcb_app_priority_table {
478 struct i40e_dcbx_config {
480 #define I40E_DCBX_MODE_CEE 0x1
481 #define I40E_DCBX_MODE_IEEE 0x2
483 struct i40e_dcb_ets_config etscfg;
484 struct i40e_dcb_ets_config etsrec;
485 struct i40e_dcb_pfc_config pfc;
486 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
489 /* Port hardware description */
494 /* subsystem structs */
495 struct i40e_phy_info phy;
496 struct i40e_mac_info mac;
497 struct i40e_bus_info bus;
498 struct i40e_nvm_info nvm;
499 struct i40e_fc_info fc;
504 u16 subsystem_device_id;
505 u16 subsystem_vendor_id;
508 bool adapter_stopped;
510 /* capabilities for entire device and PCI func */
511 struct i40e_hw_capabilities dev_caps;
512 struct i40e_hw_capabilities func_caps;
514 /* Flow Director shared filter space */
515 u16 fdir_shared_filter_count;
517 /* device profile info */
521 /* for multi-function MACs */
526 /* Closest numa node to the device */
529 /* Admin Queue info */
530 struct i40e_adminq_info aq;
532 /* state of nvm update process */
533 enum i40e_nvmupd_state nvmupd_state;
536 struct i40e_hmc_info hmc; /* HMC info struct */
538 /* LLDP/DCBX Status */
542 struct i40e_dcbx_config local_dcbx_config;
543 struct i40e_dcbx_config remote_dcbx_config;
549 static inline bool i40e_is_vf(struct i40e_hw *hw)
551 return hw->mac.type == I40E_MAC_VF;
554 struct i40e_driver_version {
559 u8 driver_string[32];
563 union i40e_16byte_rx_desc {
565 __le64 pkt_addr; /* Packet buffer address */
566 __le64 hdr_addr; /* Header buffer address */
572 __le16 mirroring_status;
578 __le32 rss; /* RSS Hash */
579 __le32 fd_id; /* Flow director filter id */
580 __le32 fcoe_param; /* FCoE DDP Context id */
584 /* ext status/error/pktype/length */
585 __le64 status_error_len;
587 } wb; /* writeback */
590 union i40e_32byte_rx_desc {
592 __le64 pkt_addr; /* Packet buffer address */
593 __le64 hdr_addr; /* Header buffer address */
594 /* bit 0 of hdr_buffer_addr is DD bit */
602 __le16 mirroring_status;
608 __le32 rss; /* RSS Hash */
609 __le32 fcoe_param; /* FCoE DDP Context id */
610 /* Flow director filter id in case of
611 * Programming status desc WB
617 /* status/error/pktype/length */
618 __le64 status_error_len;
621 __le16 ext_status; /* extended status */
628 __le32 flex_bytes_lo;
632 __le32 flex_bytes_hi;
636 } wb; /* writeback */
639 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
640 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
641 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
642 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
643 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
644 I40E_RXD_QW0_FCOEINDX_SHIFT)
646 enum i40e_rx_desc_status_bits {
647 /* Note: These are predefined bit offsets */
648 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
649 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
650 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
651 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
652 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
653 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
654 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
655 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
657 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
658 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
659 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
660 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
661 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
662 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
663 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
664 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
667 #define I40E_RXD_QW1_STATUS_SHIFT 0
668 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
669 I40E_RXD_QW1_STATUS_SHIFT)
671 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
672 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
673 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
675 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
676 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
677 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
679 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
680 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
681 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
683 enum i40e_rx_desc_fltstat_values {
684 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
685 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
686 I40E_RX_DESC_FLTSTAT_RSV = 2,
687 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
690 #define I40E_RXD_PACKET_TYPE_UNICAST 0
691 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
692 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
693 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
695 #define I40E_RXD_QW1_ERROR_SHIFT 19
696 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
698 enum i40e_rx_desc_error_bits {
699 /* Note: These are predefined bit offsets */
700 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
701 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
702 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
703 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
704 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
705 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
706 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
707 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
708 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
711 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
712 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
713 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
714 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
715 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
716 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
719 #define I40E_RXD_QW1_PTYPE_SHIFT 30
720 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
722 /* Packet type non-ip values */
723 enum i40e_rx_l2_ptype {
724 I40E_RX_PTYPE_L2_RESERVED = 0,
725 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
726 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
727 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
728 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
729 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
730 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
731 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
732 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
733 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
734 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
735 I40E_RX_PTYPE_L2_ARP = 11,
736 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
737 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
738 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
739 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
740 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
741 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
742 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
743 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
744 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
745 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
746 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
747 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
748 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
749 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
752 struct i40e_rx_ptype_decoded {
759 u32 tunnel_end_prot:2;
760 u32 tunnel_end_frag:1;
765 enum i40e_rx_ptype_outer_ip {
766 I40E_RX_PTYPE_OUTER_L2 = 0,
767 I40E_RX_PTYPE_OUTER_IP = 1
770 enum i40e_rx_ptype_outer_ip_ver {
771 I40E_RX_PTYPE_OUTER_NONE = 0,
772 I40E_RX_PTYPE_OUTER_IPV4 = 0,
773 I40E_RX_PTYPE_OUTER_IPV6 = 1
776 enum i40e_rx_ptype_outer_fragmented {
777 I40E_RX_PTYPE_NOT_FRAG = 0,
778 I40E_RX_PTYPE_FRAG = 1
781 enum i40e_rx_ptype_tunnel_type {
782 I40E_RX_PTYPE_TUNNEL_NONE = 0,
783 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
784 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
785 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
786 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
789 enum i40e_rx_ptype_tunnel_end_prot {
790 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
791 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
792 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
795 enum i40e_rx_ptype_inner_prot {
796 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
797 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
798 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
799 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
800 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
801 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
804 enum i40e_rx_ptype_payload_layer {
805 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
806 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
807 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
808 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
811 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
812 #define I40E_RX_PTYPE_SHIFT 56
814 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
815 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
816 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
818 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
819 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
820 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
822 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
823 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
824 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
826 #define I40E_RXD_QW1_NEXTP_SHIFT 38
827 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
829 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
830 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
831 I40E_RXD_QW2_EXT_STATUS_SHIFT)
833 enum i40e_rx_desc_ext_status_bits {
834 /* Note: These are predefined bit offsets */
835 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
836 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
837 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
838 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
839 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
840 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
841 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
844 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
845 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
847 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
848 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
850 enum i40e_rx_desc_pe_status_bits {
851 /* Note: These are predefined bit offsets */
852 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
853 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
854 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
855 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
856 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
857 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
858 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
859 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
860 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
863 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
864 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
866 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
867 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
868 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
870 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
871 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
872 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
874 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
875 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
876 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
878 enum i40e_rx_prog_status_desc_status_bits {
879 /* Note: These are predefined bit offsets */
880 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
881 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
884 enum i40e_rx_prog_status_desc_prog_id_masks {
885 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
886 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
887 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
890 enum i40e_rx_prog_status_desc_error_bits {
891 /* Note: These are predefined bit offsets */
892 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
893 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
894 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
895 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
898 #define I40E_TWO_BIT_MASK 0x3
899 #define I40E_THREE_BIT_MASK 0x7
900 #define I40E_FOUR_BIT_MASK 0xF
901 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
904 struct i40e_tx_desc {
905 __le64 buffer_addr; /* Address of descriptor's data buf */
906 __le64 cmd_type_offset_bsz;
909 #define I40E_TXD_QW1_DTYPE_SHIFT 0
910 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
912 enum i40e_tx_desc_dtype_value {
913 I40E_TX_DESC_DTYPE_DATA = 0x0,
914 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
915 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
916 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
917 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
918 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
919 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
920 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
921 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
922 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
925 #define I40E_TXD_QW1_CMD_SHIFT 4
926 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
928 enum i40e_tx_desc_cmd_bits {
929 I40E_TX_DESC_CMD_EOP = 0x0001,
930 I40E_TX_DESC_CMD_RS = 0x0002,
931 I40E_TX_DESC_CMD_ICRC = 0x0004,
932 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
933 I40E_TX_DESC_CMD_DUMMY = 0x0010,
934 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
935 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
936 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
937 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
938 I40E_TX_DESC_CMD_FCOET = 0x0080,
939 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
940 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
941 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
942 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
943 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
944 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
945 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
946 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
949 #define I40E_TXD_QW1_OFFSET_SHIFT 16
950 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
951 I40E_TXD_QW1_OFFSET_SHIFT)
953 enum i40e_tx_desc_length_fields {
954 /* Note: These are predefined bit offsets */
955 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
956 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
957 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
960 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
961 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
962 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
963 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
965 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
966 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
967 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
969 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
970 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
972 /* Context descriptors */
973 struct i40e_tx_context_desc {
974 __le32 tunneling_params;
977 __le64 type_cmd_tso_mss;
980 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
981 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
983 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
984 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
986 enum i40e_tx_ctx_desc_cmd_bits {
987 I40E_TX_CTX_DESC_TSO = 0x01,
988 I40E_TX_CTX_DESC_TSYN = 0x02,
989 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
990 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
991 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
992 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
993 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
994 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
995 I40E_TX_CTX_DESC_SWPE = 0x40
998 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
999 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1000 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1002 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1003 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1004 I40E_TXD_CTX_QW1_MSS_SHIFT)
1006 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1007 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1009 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1010 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1011 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1013 enum i40e_tx_ctx_desc_eipt_offload {
1014 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1015 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1016 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1017 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1020 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1021 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1022 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1024 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1025 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1027 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1028 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1030 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1031 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1032 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1034 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1036 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1037 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1038 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1040 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1041 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1042 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1044 struct i40e_nop_desc {
1049 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1050 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1052 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1053 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1055 enum i40e_tx_nop_desc_cmd_bits {
1056 /* Note: These are predefined bit offsets */
1057 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1058 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1059 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1062 struct i40e_filter_program_desc {
1063 __le32 qindex_flex_ptype_vsi;
1065 __le32 dtype_cmd_cntindex;
1068 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1069 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1070 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1071 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1072 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1073 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1074 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1075 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1076 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1078 /* Packet Classifier Types for filters */
1079 enum i40e_filter_pctype {
1080 /* Note: Values 0-30 are reserved for future use */
1081 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1082 /* Note: Value 32 is reserved for future use */
1083 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1084 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1085 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1086 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1087 /* Note: Values 37-40 are reserved for future use */
1088 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1089 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1090 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1091 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1092 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1093 /* Note: Value 47 is reserved for future use */
1094 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1095 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1096 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1097 /* Note: Values 51-62 are reserved for future use */
1098 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1101 enum i40e_filter_program_desc_dest {
1102 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1103 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1104 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1107 enum i40e_filter_program_desc_fd_status {
1108 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1109 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1110 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1111 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1114 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1115 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1118 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1119 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1121 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1122 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1123 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1125 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1126 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1128 enum i40e_filter_program_desc_pcmd {
1129 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1130 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1133 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1134 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1136 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1137 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1138 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1140 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1141 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1142 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1143 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1145 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1146 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1147 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1149 enum i40e_filter_type {
1150 I40E_FLOW_DIRECTOR_FLTR = 0,
1151 I40E_PE_QUAD_HASH_FLTR = 1,
1152 I40E_ETHERTYPE_FLTR,
1158 struct i40e_vsi_context {
1163 u16 vsis_unallocated;
1168 struct i40e_aqc_vsi_properties_data info;
1171 struct i40e_veb_context {
1176 u16 vebs_unallocated;
1178 struct i40e_aqc_get_veb_parameters_completion info;
1181 /* Statistics collected by each port, VSI, VEB, and S-channel */
1182 struct i40e_eth_stats {
1183 u64 rx_bytes; /* gorc */
1184 u64 rx_unicast; /* uprc */
1185 u64 rx_multicast; /* mprc */
1186 u64 rx_broadcast; /* bprc */
1187 u64 rx_discards; /* rdpc */
1188 u64 rx_unknown_protocol; /* rupp */
1189 u64 tx_bytes; /* gotc */
1190 u64 tx_unicast; /* uptc */
1191 u64 tx_multicast; /* mptc */
1192 u64 tx_broadcast; /* bptc */
1193 u64 tx_discards; /* tdpc */
1194 u64 tx_errors; /* tepc */
1197 /* Statistics collected per VEB per TC */
1198 struct i40e_veb_tc_stats {
1199 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1200 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1201 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1202 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1205 /* Statistics collected by the MAC */
1206 struct i40e_hw_port_stats {
1207 /* eth stats collected by the port */
1208 struct i40e_eth_stats eth;
1210 /* additional port specific stats */
1211 u64 tx_dropped_link_down; /* tdold */
1212 u64 crc_errors; /* crcerrs */
1213 u64 illegal_bytes; /* illerrc */
1214 u64 error_bytes; /* errbc */
1215 u64 mac_local_faults; /* mlfc */
1216 u64 mac_remote_faults; /* mrfc */
1217 u64 rx_length_errors; /* rlec */
1218 u64 link_xon_rx; /* lxonrxc */
1219 u64 link_xoff_rx; /* lxoffrxc */
1220 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1221 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1222 u64 link_xon_tx; /* lxontxc */
1223 u64 link_xoff_tx; /* lxofftxc */
1224 u64 priority_xon_tx[8]; /* pxontxc[8] */
1225 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1226 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1227 u64 rx_size_64; /* prc64 */
1228 u64 rx_size_127; /* prc127 */
1229 u64 rx_size_255; /* prc255 */
1230 u64 rx_size_511; /* prc511 */
1231 u64 rx_size_1023; /* prc1023 */
1232 u64 rx_size_1522; /* prc1522 */
1233 u64 rx_size_big; /* prc9522 */
1234 u64 rx_undersize; /* ruc */
1235 u64 rx_fragments; /* rfc */
1236 u64 rx_oversize; /* roc */
1237 u64 rx_jabber; /* rjc */
1238 u64 tx_size_64; /* ptc64 */
1239 u64 tx_size_127; /* ptc127 */
1240 u64 tx_size_255; /* ptc255 */
1241 u64 tx_size_511; /* ptc511 */
1242 u64 tx_size_1023; /* ptc1023 */
1243 u64 tx_size_1522; /* ptc1522 */
1244 u64 tx_size_big; /* ptc9522 */
1245 u64 mac_short_packet_dropped; /* mspdc */
1246 u64 checksum_error; /* xec */
1247 /* flow director stats */
1253 u64 tx_lpi_count; /* etlpic */
1254 u64 rx_lpi_count; /* erlpic */
1257 /* Checksum and Shadow RAM pointers */
1258 #define I40E_SR_NVM_CONTROL_WORD 0x00
1259 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1260 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1261 #define I40E_SR_OPTION_ROM_PTR 0x05
1262 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1263 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1264 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1265 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1266 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1267 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1268 #define I40E_SR_PE_IMAGE_PTR 0x0C
1269 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1270 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1271 #define I40E_SR_EMP_MODULE_PTR 0x0F
1272 #define I40E_SR_PBA_FLAGS 0x15
1273 #define I40E_SR_PBA_BLOCK_PTR 0x16
1274 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1275 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1276 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1277 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1278 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1279 #define I40E_SR_NVM_MAP_VERSION 0x29
1280 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1281 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1282 #define I40E_SR_NVM_EETRACK_LO 0x2D
1283 #define I40E_SR_NVM_EETRACK_HI 0x2E
1284 #define I40E_SR_VPD_PTR 0x2F
1285 #define I40E_SR_PXE_SETUP_PTR 0x30
1286 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1287 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1288 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1289 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1290 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1291 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1292 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1293 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1294 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1295 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1296 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1297 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1298 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1299 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1300 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1301 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1302 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1303 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1305 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1306 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1307 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1308 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1309 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1311 /* Shadow RAM related */
1312 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1313 #define I40E_SR_BUF_ALIGNMENT 4096
1314 #define I40E_SR_WORDS_IN_1KB 512
1315 /* Checksum should be calculated such that after adding all the words,
1316 * including the checksum word itself, the sum should be 0xBABA.
1318 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1320 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1322 enum i40e_switch_element_types {
1323 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1324 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1325 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1326 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1327 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1328 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1329 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1330 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1331 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1334 /* Supported EtherType filters */
1335 enum i40e_ether_type_index {
1336 I40E_ETHER_TYPE_1588 = 0,
1337 I40E_ETHER_TYPE_FIP = 1,
1338 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1339 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1340 I40E_ETHER_TYPE_LLDP = 4,
1341 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1342 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1343 I40E_ETHER_TYPE_QCN_CNM = 7,
1344 I40E_ETHER_TYPE_8021X = 8,
1345 I40E_ETHER_TYPE_ARP = 9,
1346 I40E_ETHER_TYPE_RSV1 = 10,
1347 I40E_ETHER_TYPE_RSV2 = 11,
1350 /* Filter context base size is 1K */
1351 #define I40E_HASH_FILTER_BASE_SIZE 1024
1352 /* Supported Hash filter values */
1353 enum i40e_hash_filter_size {
1354 I40E_HASH_FILTER_SIZE_1K = 0,
1355 I40E_HASH_FILTER_SIZE_2K = 1,
1356 I40E_HASH_FILTER_SIZE_4K = 2,
1357 I40E_HASH_FILTER_SIZE_8K = 3,
1358 I40E_HASH_FILTER_SIZE_16K = 4,
1359 I40E_HASH_FILTER_SIZE_32K = 5,
1360 I40E_HASH_FILTER_SIZE_64K = 6,
1361 I40E_HASH_FILTER_SIZE_128K = 7,
1362 I40E_HASH_FILTER_SIZE_256K = 8,
1363 I40E_HASH_FILTER_SIZE_512K = 9,
1364 I40E_HASH_FILTER_SIZE_1M = 10,
1367 /* DMA context base size is 0.5K */
1368 #define I40E_DMA_CNTX_BASE_SIZE 512
1369 /* Supported DMA context values */
1370 enum i40e_dma_cntx_size {
1371 I40E_DMA_CNTX_SIZE_512 = 0,
1372 I40E_DMA_CNTX_SIZE_1K = 1,
1373 I40E_DMA_CNTX_SIZE_2K = 2,
1374 I40E_DMA_CNTX_SIZE_4K = 3,
1375 I40E_DMA_CNTX_SIZE_8K = 4,
1376 I40E_DMA_CNTX_SIZE_16K = 5,
1377 I40E_DMA_CNTX_SIZE_32K = 6,
1378 I40E_DMA_CNTX_SIZE_64K = 7,
1379 I40E_DMA_CNTX_SIZE_128K = 8,
1380 I40E_DMA_CNTX_SIZE_256K = 9,
1383 /* Supported Hash look up table (LUT) sizes */
1384 enum i40e_hash_lut_size {
1385 I40E_HASH_LUT_SIZE_128 = 0,
1386 I40E_HASH_LUT_SIZE_512 = 1,
1389 /* Structure to hold a per PF filter control settings */
1390 struct i40e_filter_control_settings {
1391 /* number of PE Quad Hash filter buckets */
1392 enum i40e_hash_filter_size pe_filt_num;
1393 /* number of PE Quad Hash contexts */
1394 enum i40e_dma_cntx_size pe_cntx_num;
1395 /* number of FCoE filter buckets */
1396 enum i40e_hash_filter_size fcoe_filt_num;
1397 /* number of FCoE DDP contexts */
1398 enum i40e_dma_cntx_size fcoe_cntx_num;
1399 /* size of the Hash LUT */
1400 enum i40e_hash_lut_size hash_lut_size;
1401 /* enable FDIR filters for PF and its VFs */
1403 /* enable Ethertype filters for PF and its VFs */
1404 bool enable_ethtype;
1405 /* enable MAC/VLAN filters for PF and its VFs */
1406 bool enable_macvlan;
1409 /* Structure to hold device level control filter counts */
1410 struct i40e_control_filter_stats {
1411 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1412 u16 etype_used; /* Used perfect EtherType filters */
1413 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1414 u16 etype_free; /* Un-used perfect EtherType filters */
1417 enum i40e_reset_type {
1419 I40E_RESET_CORER = 1,
1420 I40E_RESET_GLOBR = 2,
1421 I40E_RESET_EMPR = 3,
1424 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1425 #define I40E_NVM_LLDP_CFG_PTR 0xD
1426 struct i40e_lldp_variables {
1436 /* Offsets into Alternate Ram */
1437 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1438 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1439 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1440 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1441 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1442 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1444 /* Alternate Ram Bandwidth Masks */
1445 #define I40E_ALT_BW_VALUE_MASK 0xFF
1446 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1447 #define I40E_ALT_BW_VALID_MASK 0x80000000
1449 /* RSS Hash Table Size */
1450 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1451 #endif /* _I40E_TYPE_H_ */