1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
161 enum i40e_memset_type {
167 enum i40e_memcpy_type {
168 I40E_NONDMA_TO_NONDMA = 0,
176 #define I40E_FW_API_VERSION_MINOR_X722 0x0003
178 #define I40E_FW_API_VERSION_MINOR_X710 0x0004
181 /* These are structs for managing the hardware information and the operations.
182 * The structures of function pointers are filled out at init time when we
183 * know for sure exactly which hardware we're working with. This gives us the
184 * flexibility of using the same main driver code but adapting to slightly
185 * different hardware needs as new parts are developed. For this architecture,
186 * the Firmware and AdminQ are intended to insulate the driver from most of the
187 * future changes, but these structures will also do part of the job.
190 I40E_MAC_UNKNOWN = 0,
197 enum i40e_media_type {
198 I40E_MEDIA_TYPE_UNKNOWN = 0,
199 I40E_MEDIA_TYPE_FIBER,
200 I40E_MEDIA_TYPE_BASET,
201 I40E_MEDIA_TYPE_BACKPLANE,
204 I40E_MEDIA_TYPE_VIRTUAL
216 enum i40e_set_fc_aq_failures {
217 I40E_SET_FC_AQ_FAIL_NONE = 0,
218 I40E_SET_FC_AQ_FAIL_GET = 1,
219 I40E_SET_FC_AQ_FAIL_SET = 2,
220 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
221 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
233 I40E_VSI_TYPE_UNKNOWN
236 enum i40e_queue_type {
237 I40E_QUEUE_TYPE_RX = 0,
239 I40E_QUEUE_TYPE_PE_CEQ,
240 I40E_QUEUE_TYPE_UNKNOWN
243 struct i40e_link_status {
244 enum i40e_aq_phy_type phy_type;
245 enum i40e_aq_link_speed link_speed;
250 /* is Link Status Event notification to SW enabled */
257 /* 1st byte: module identifier */
258 #define I40E_MODULE_TYPE_SFP 0x03
259 #define I40E_MODULE_TYPE_QSFP 0x0D
260 /* 2nd byte: ethernet compliance codes for 10/40G */
261 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
262 #define I40E_MODULE_TYPE_40G_LR4 0x02
263 #define I40E_MODULE_TYPE_40G_SR4 0x04
264 #define I40E_MODULE_TYPE_40G_CR4 0x08
265 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
266 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
267 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
268 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
269 /* 3rd byte: ethernet compliance codes for 1G */
270 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
271 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
272 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
273 #define I40E_MODULE_TYPE_1000BASE_T 0x08
276 enum i40e_aq_capabilities_phy_type {
277 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
278 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
279 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
280 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
281 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
282 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
283 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
284 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
285 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
286 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
287 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
288 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
289 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
290 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
291 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
292 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
293 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
294 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
295 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
296 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
297 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
298 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
299 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
300 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
301 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
302 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
303 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
304 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
307 struct i40e_phy_info {
308 struct i40e_link_status link_info;
309 struct i40e_link_status link_info_old;
311 enum i40e_media_type media_type;
312 /* all the phy types the NVM is capable of */
316 #define I40E_HW_CAP_MAX_GPIO 30
317 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
318 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
320 /* Capabilities of a PF or a VF or the whole device */
321 struct i40e_hw_capabilities {
323 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
324 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
325 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
333 bool evb_802_1_qbg; /* Edge Virtual Bridging */
334 bool evb_802_1_qbh; /* Bridge Port Extension */
337 bool iscsi; /* Indicates iSCSI enabled */
343 u32 fd_filters_guaranteed;
344 u32 fd_filters_best_effort;
347 u32 rss_table_entry_width;
348 bool led[I40E_HW_CAP_MAX_GPIO];
349 bool sdp[I40E_HW_CAP_MAX_GPIO];
351 u32 num_flow_director_filters;
358 u32 num_msix_vectors;
359 u32 num_msix_vectors_vf;
369 struct i40e_mac_info {
370 enum i40e_mac_type type;
371 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
372 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
373 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
374 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
378 enum i40e_aq_resources_ids {
379 I40E_NVM_RESOURCE_ID = 1
382 enum i40e_aq_resource_access_type {
383 I40E_RESOURCE_READ = 1,
387 struct i40e_nvm_info {
388 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
389 u32 timeout; /* [ms] */
390 u16 sr_size; /* Shadow RAM size in words */
391 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
392 u16 version; /* NVM package version */
393 u32 eetrack; /* NVM data version */
394 u32 oem_ver; /* OEM version info */
397 /* definitions used in NVM update support */
399 enum i40e_nvmupd_cmd {
401 I40E_NVMUPD_READ_CON,
402 I40E_NVMUPD_READ_SNT,
403 I40E_NVMUPD_READ_LCB,
405 I40E_NVMUPD_WRITE_ERA,
406 I40E_NVMUPD_WRITE_CON,
407 I40E_NVMUPD_WRITE_SNT,
408 I40E_NVMUPD_WRITE_LCB,
409 I40E_NVMUPD_WRITE_SA,
410 I40E_NVMUPD_CSUM_CON,
412 I40E_NVMUPD_CSUM_LCB,
415 I40E_NVMUPD_GET_AQ_RESULT,
418 enum i40e_nvmupd_state {
419 I40E_NVMUPD_STATE_INIT,
420 I40E_NVMUPD_STATE_READING,
421 I40E_NVMUPD_STATE_WRITING,
422 I40E_NVMUPD_STATE_INIT_WAIT,
423 I40E_NVMUPD_STATE_WRITE_WAIT,
426 /* nvm_access definition and its masks/shifts need to be accessible to
427 * application, core driver, and shared code. Where is the right file?
429 #define I40E_NVM_READ 0xB
430 #define I40E_NVM_WRITE 0xC
432 #define I40E_NVM_MOD_PNT_MASK 0xFF
434 #define I40E_NVM_TRANS_SHIFT 8
435 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
436 #define I40E_NVM_CON 0x0
437 #define I40E_NVM_SNT 0x1
438 #define I40E_NVM_LCB 0x2
439 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
440 #define I40E_NVM_ERA 0x4
441 #define I40E_NVM_CSUM 0x8
442 #define I40E_NVM_EXEC 0xf
444 #define I40E_NVM_ADAPT_SHIFT 16
445 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
447 #define I40E_NVMUPD_MAX_DATA 4096
448 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
450 struct i40e_nvm_access {
453 u32 offset; /* in bytes */
454 u32 data_size; /* in bytes */
460 i40e_bus_type_unknown = 0,
463 i40e_bus_type_pci_express,
464 i40e_bus_type_reserved
468 enum i40e_bus_speed {
469 i40e_bus_speed_unknown = 0,
470 i40e_bus_speed_33 = 33,
471 i40e_bus_speed_66 = 66,
472 i40e_bus_speed_100 = 100,
473 i40e_bus_speed_120 = 120,
474 i40e_bus_speed_133 = 133,
475 i40e_bus_speed_2500 = 2500,
476 i40e_bus_speed_5000 = 5000,
477 i40e_bus_speed_8000 = 8000,
478 i40e_bus_speed_reserved
482 enum i40e_bus_width {
483 i40e_bus_width_unknown = 0,
484 i40e_bus_width_pcie_x1 = 1,
485 i40e_bus_width_pcie_x2 = 2,
486 i40e_bus_width_pcie_x4 = 4,
487 i40e_bus_width_pcie_x8 = 8,
488 i40e_bus_width_32 = 32,
489 i40e_bus_width_64 = 64,
490 i40e_bus_width_reserved
494 struct i40e_bus_info {
495 enum i40e_bus_speed speed;
496 enum i40e_bus_width width;
497 enum i40e_bus_type type;
504 /* Flow control (FC) parameters */
505 struct i40e_fc_info {
506 enum i40e_fc_mode current_mode; /* FC mode in effect */
507 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
510 #define I40E_MAX_TRAFFIC_CLASS 8
511 #define I40E_MAX_USER_PRIORITY 8
512 #define I40E_DCBX_MAX_APPS 32
513 #define I40E_LLDPDU_SIZE 1500
514 #define I40E_TLV_STATUS_OPER 0x1
515 #define I40E_TLV_STATUS_SYNC 0x2
516 #define I40E_TLV_STATUS_ERR 0x4
517 #define I40E_CEE_OPER_MAX_APPS 3
518 #define I40E_APP_PROTOID_FCOE 0x8906
519 #define I40E_APP_PROTOID_ISCSI 0x0cbc
520 #define I40E_APP_PROTOID_FIP 0x8914
521 #define I40E_APP_SEL_ETHTYPE 0x1
522 #define I40E_APP_SEL_TCPIP 0x2
523 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
524 #define I40E_CEE_APP_SEL_TCPIP 0x1
526 /* CEE or IEEE 802.1Qaz ETS Configuration data */
527 struct i40e_dcb_ets_config {
531 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
532 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
533 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
536 /* CEE or IEEE 802.1Qaz PFC Configuration data */
537 struct i40e_dcb_pfc_config {
544 /* CEE or IEEE 802.1Qaz Application Priority data */
545 struct i40e_dcb_app_priority_table {
551 struct i40e_dcbx_config {
553 #define I40E_DCBX_MODE_CEE 0x1
554 #define I40E_DCBX_MODE_IEEE 0x2
556 #define I40E_DCBX_APPS_NON_WILLING 0x1
558 u32 tlv_status; /* CEE mode TLV status */
559 struct i40e_dcb_ets_config etscfg;
560 struct i40e_dcb_ets_config etsrec;
561 struct i40e_dcb_pfc_config pfc;
562 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
565 /* Port hardware description */
570 /* subsystem structs */
571 struct i40e_phy_info phy;
572 struct i40e_mac_info mac;
573 struct i40e_bus_info bus;
574 struct i40e_nvm_info nvm;
575 struct i40e_fc_info fc;
580 u16 subsystem_device_id;
581 u16 subsystem_vendor_id;
584 bool adapter_stopped;
586 /* capabilities for entire device and PCI func */
587 struct i40e_hw_capabilities dev_caps;
588 struct i40e_hw_capabilities func_caps;
590 /* Flow Director shared filter space */
591 u16 fdir_shared_filter_count;
593 /* device profile info */
597 /* for multi-function MACs */
602 /* Closest numa node to the device */
605 /* Admin Queue info */
606 struct i40e_adminq_info aq;
608 /* state of nvm update process */
609 enum i40e_nvmupd_state nvmupd_state;
610 struct i40e_aq_desc nvm_wb_desc;
611 struct i40e_virt_mem nvm_buff;
614 struct i40e_hmc_info hmc; /* HMC info struct */
616 /* LLDP/DCBX Status */
620 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
621 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
622 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
626 #ifndef I40E_NDIS_SUPPORT
628 #endif /* I40E_NDIS_SUPPORT */
631 static inline bool i40e_is_vf(struct i40e_hw *hw)
633 return hw->mac.type == I40E_MAC_VF;
636 struct i40e_driver_version {
641 u8 driver_string[32];
645 union i40e_16byte_rx_desc {
647 __le64 pkt_addr; /* Packet buffer address */
648 __le64 hdr_addr; /* Header buffer address */
654 __le16 mirroring_status;
660 __le32 rss; /* RSS Hash */
661 __le32 fd_id; /* Flow director filter id */
662 __le32 fcoe_param; /* FCoE DDP Context id */
666 /* ext status/error/pktype/length */
667 __le64 status_error_len;
669 } wb; /* writeback */
672 union i40e_32byte_rx_desc {
674 __le64 pkt_addr; /* Packet buffer address */
675 __le64 hdr_addr; /* Header buffer address */
676 /* bit 0 of hdr_buffer_addr is DD bit */
684 __le16 mirroring_status;
690 __le32 rss; /* RSS Hash */
691 __le32 fcoe_param; /* FCoE DDP Context id */
692 /* Flow director filter id in case of
693 * Programming status desc WB
699 /* status/error/pktype/length */
700 __le64 status_error_len;
703 __le16 ext_status; /* extended status */
710 __le32 flex_bytes_lo;
714 __le32 flex_bytes_hi;
718 } wb; /* writeback */
721 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
722 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
723 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
724 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
725 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
726 I40E_RXD_QW0_FCOEINDX_SHIFT)
728 enum i40e_rx_desc_status_bits {
729 /* Note: These are predefined bit offsets */
730 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
731 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
732 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
733 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
734 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
735 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
736 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
737 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
739 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
740 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
741 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
742 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
743 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
744 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
745 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
746 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
749 #define I40E_RXD_QW1_STATUS_SHIFT 0
750 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
751 I40E_RXD_QW1_STATUS_SHIFT)
753 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
754 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
755 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
757 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
758 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
760 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
761 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
762 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
764 enum i40e_rx_desc_fltstat_values {
765 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
766 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
767 I40E_RX_DESC_FLTSTAT_RSV = 2,
768 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
771 #define I40E_RXD_PACKET_TYPE_UNICAST 0
772 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
773 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
774 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
776 #define I40E_RXD_QW1_ERROR_SHIFT 19
777 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
779 enum i40e_rx_desc_error_bits {
780 /* Note: These are predefined bit offsets */
781 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
782 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
783 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
784 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
785 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
786 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
787 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
788 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
789 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
792 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
793 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
794 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
795 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
796 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
797 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
800 #define I40E_RXD_QW1_PTYPE_SHIFT 30
801 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
803 /* Packet type non-ip values */
804 enum i40e_rx_l2_ptype {
805 I40E_RX_PTYPE_L2_RESERVED = 0,
806 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
807 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
808 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
809 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
810 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
811 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
812 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
813 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
814 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
815 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
816 I40E_RX_PTYPE_L2_ARP = 11,
817 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
818 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
819 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
820 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
821 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
822 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
823 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
824 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
825 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
826 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
827 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
828 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
829 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
830 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
833 struct i40e_rx_ptype_decoded {
840 u32 tunnel_end_prot:2;
841 u32 tunnel_end_frag:1;
846 enum i40e_rx_ptype_outer_ip {
847 I40E_RX_PTYPE_OUTER_L2 = 0,
848 I40E_RX_PTYPE_OUTER_IP = 1
851 enum i40e_rx_ptype_outer_ip_ver {
852 I40E_RX_PTYPE_OUTER_NONE = 0,
853 I40E_RX_PTYPE_OUTER_IPV4 = 0,
854 I40E_RX_PTYPE_OUTER_IPV6 = 1
857 enum i40e_rx_ptype_outer_fragmented {
858 I40E_RX_PTYPE_NOT_FRAG = 0,
859 I40E_RX_PTYPE_FRAG = 1
862 enum i40e_rx_ptype_tunnel_type {
863 I40E_RX_PTYPE_TUNNEL_NONE = 0,
864 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
865 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
866 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
867 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
870 enum i40e_rx_ptype_tunnel_end_prot {
871 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
872 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
873 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
876 enum i40e_rx_ptype_inner_prot {
877 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
878 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
879 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
880 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
881 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
882 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
885 enum i40e_rx_ptype_payload_layer {
886 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
887 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
888 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
889 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
892 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
893 #define I40E_RX_PTYPE_SHIFT 56
895 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
896 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
897 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
899 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
900 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
901 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
903 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
904 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
906 #define I40E_RXD_QW1_NEXTP_SHIFT 38
907 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
909 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
910 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
911 I40E_RXD_QW2_EXT_STATUS_SHIFT)
913 enum i40e_rx_desc_ext_status_bits {
914 /* Note: These are predefined bit offsets */
915 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
916 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
917 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
918 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
919 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
920 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
921 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
924 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
925 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
927 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
928 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
930 enum i40e_rx_desc_pe_status_bits {
931 /* Note: These are predefined bit offsets */
932 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
933 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
934 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
935 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
936 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
937 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
938 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
939 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
940 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
943 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
944 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
946 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
947 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
948 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
950 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
951 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
952 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
954 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
955 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
956 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
958 enum i40e_rx_prog_status_desc_status_bits {
959 /* Note: These are predefined bit offsets */
960 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
961 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
964 enum i40e_rx_prog_status_desc_prog_id_masks {
965 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
966 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
967 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
970 enum i40e_rx_prog_status_desc_error_bits {
971 /* Note: These are predefined bit offsets */
972 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
973 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
974 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
975 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
978 #define I40E_TWO_BIT_MASK 0x3
979 #define I40E_THREE_BIT_MASK 0x7
980 #define I40E_FOUR_BIT_MASK 0xF
981 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
984 struct i40e_tx_desc {
985 __le64 buffer_addr; /* Address of descriptor's data buf */
986 __le64 cmd_type_offset_bsz;
989 #define I40E_TXD_QW1_DTYPE_SHIFT 0
990 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
992 enum i40e_tx_desc_dtype_value {
993 I40E_TX_DESC_DTYPE_DATA = 0x0,
994 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
995 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
996 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
997 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
998 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
999 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1000 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1001 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1002 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1005 #define I40E_TXD_QW1_CMD_SHIFT 4
1006 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1008 enum i40e_tx_desc_cmd_bits {
1009 I40E_TX_DESC_CMD_EOP = 0x0001,
1010 I40E_TX_DESC_CMD_RS = 0x0002,
1011 I40E_TX_DESC_CMD_ICRC = 0x0004,
1012 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1013 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1014 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1015 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1016 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1017 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1018 I40E_TX_DESC_CMD_FCOET = 0x0080,
1019 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1020 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1021 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1022 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1023 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1024 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1025 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1026 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1029 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1030 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1031 I40E_TXD_QW1_OFFSET_SHIFT)
1033 enum i40e_tx_desc_length_fields {
1034 /* Note: These are predefined bit offsets */
1035 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1036 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1037 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1040 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1041 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1042 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1043 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1045 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1046 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1047 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1049 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1050 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1052 /* Context descriptors */
1053 struct i40e_tx_context_desc {
1054 __le32 tunneling_params;
1057 __le64 type_cmd_tso_mss;
1060 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1061 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1063 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1064 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1066 enum i40e_tx_ctx_desc_cmd_bits {
1067 I40E_TX_CTX_DESC_TSO = 0x01,
1068 I40E_TX_CTX_DESC_TSYN = 0x02,
1069 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1070 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1071 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1072 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1073 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1074 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1075 I40E_TX_CTX_DESC_SWPE = 0x40
1078 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1079 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1080 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1082 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1083 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1084 I40E_TXD_CTX_QW1_MSS_SHIFT)
1086 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1087 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1089 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1090 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1091 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1093 enum i40e_tx_ctx_desc_eipt_offload {
1094 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1095 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1096 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1097 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1100 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1101 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1102 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1104 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1105 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1107 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1108 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1110 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1111 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1113 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1115 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1116 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1117 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1119 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1120 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1121 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1123 struct i40e_nop_desc {
1128 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1129 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1131 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1132 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1134 enum i40e_tx_nop_desc_cmd_bits {
1135 /* Note: These are predefined bit offsets */
1136 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1137 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1138 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1141 struct i40e_filter_program_desc {
1142 __le32 qindex_flex_ptype_vsi;
1144 __le32 dtype_cmd_cntindex;
1147 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1148 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1149 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1150 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1151 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1152 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1153 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1154 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1155 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1157 /* Packet Classifier Types for filters */
1158 enum i40e_filter_pctype {
1159 /* Note: Values 0-30 are reserved for future use */
1160 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1161 /* Note: Value 32 is reserved for future use */
1162 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1163 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1164 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1165 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1166 /* Note: Values 37-40 are reserved for future use */
1167 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1168 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1169 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1170 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1171 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1172 /* Note: Value 47 is reserved for future use */
1173 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1174 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1175 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1176 /* Note: Values 51-62 are reserved for future use */
1177 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1180 enum i40e_filter_program_desc_dest {
1181 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1182 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1183 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1186 enum i40e_filter_program_desc_fd_status {
1187 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1188 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1189 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1190 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1193 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1194 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1195 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1197 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1198 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1200 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1201 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1202 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1204 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1205 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1207 enum i40e_filter_program_desc_pcmd {
1208 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1209 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1212 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1213 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1215 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1216 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1218 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1219 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1220 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1221 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1223 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1224 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1225 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1227 enum i40e_filter_type {
1228 I40E_FLOW_DIRECTOR_FLTR = 0,
1229 I40E_PE_QUAD_HASH_FLTR = 1,
1230 I40E_ETHERTYPE_FLTR,
1236 struct i40e_vsi_context {
1241 u16 vsis_unallocated;
1246 struct i40e_aqc_vsi_properties_data info;
1249 struct i40e_veb_context {
1254 u16 vebs_unallocated;
1256 struct i40e_aqc_get_veb_parameters_completion info;
1259 /* Statistics collected by each port, VSI, VEB, and S-channel */
1260 struct i40e_eth_stats {
1261 u64 rx_bytes; /* gorc */
1262 u64 rx_unicast; /* uprc */
1263 u64 rx_multicast; /* mprc */
1264 u64 rx_broadcast; /* bprc */
1265 u64 rx_discards; /* rdpc */
1266 u64 rx_unknown_protocol; /* rupp */
1267 u64 tx_bytes; /* gotc */
1268 u64 tx_unicast; /* uptc */
1269 u64 tx_multicast; /* mptc */
1270 u64 tx_broadcast; /* bptc */
1271 u64 tx_discards; /* tdpc */
1272 u64 tx_errors; /* tepc */
1275 /* Statistics collected per VEB per TC */
1276 struct i40e_veb_tc_stats {
1277 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1278 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1279 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1280 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1283 /* Statistics collected by the MAC */
1284 struct i40e_hw_port_stats {
1285 /* eth stats collected by the port */
1286 struct i40e_eth_stats eth;
1288 /* additional port specific stats */
1289 u64 tx_dropped_link_down; /* tdold */
1290 u64 crc_errors; /* crcerrs */
1291 u64 illegal_bytes; /* illerrc */
1292 u64 error_bytes; /* errbc */
1293 u64 mac_local_faults; /* mlfc */
1294 u64 mac_remote_faults; /* mrfc */
1295 u64 rx_length_errors; /* rlec */
1296 u64 link_xon_rx; /* lxonrxc */
1297 u64 link_xoff_rx; /* lxoffrxc */
1298 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1299 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1300 u64 link_xon_tx; /* lxontxc */
1301 u64 link_xoff_tx; /* lxofftxc */
1302 u64 priority_xon_tx[8]; /* pxontxc[8] */
1303 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1304 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1305 u64 rx_size_64; /* prc64 */
1306 u64 rx_size_127; /* prc127 */
1307 u64 rx_size_255; /* prc255 */
1308 u64 rx_size_511; /* prc511 */
1309 u64 rx_size_1023; /* prc1023 */
1310 u64 rx_size_1522; /* prc1522 */
1311 u64 rx_size_big; /* prc9522 */
1312 u64 rx_undersize; /* ruc */
1313 u64 rx_fragments; /* rfc */
1314 u64 rx_oversize; /* roc */
1315 u64 rx_jabber; /* rjc */
1316 u64 tx_size_64; /* ptc64 */
1317 u64 tx_size_127; /* ptc127 */
1318 u64 tx_size_255; /* ptc255 */
1319 u64 tx_size_511; /* ptc511 */
1320 u64 tx_size_1023; /* ptc1023 */
1321 u64 tx_size_1522; /* ptc1522 */
1322 u64 tx_size_big; /* ptc9522 */
1323 u64 mac_short_packet_dropped; /* mspdc */
1324 u64 checksum_error; /* xec */
1325 /* flow director stats */
1331 u64 tx_lpi_count; /* etlpic */
1332 u64 rx_lpi_count; /* erlpic */
1335 /* Checksum and Shadow RAM pointers */
1336 #define I40E_SR_NVM_CONTROL_WORD 0x00
1337 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1338 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1339 #define I40E_SR_OPTION_ROM_PTR 0x05
1340 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1341 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1342 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1343 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1344 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1345 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1346 #define I40E_SR_PE_IMAGE_PTR 0x0C
1347 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1348 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1349 #define I40E_SR_EMP_MODULE_PTR 0x0F
1350 #define I40E_SR_PBA_FLAGS 0x15
1351 #define I40E_SR_PBA_BLOCK_PTR 0x16
1352 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1353 #define I40E_NVM_OEM_VER_OFF 0x83
1354 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1355 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1356 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1357 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1358 #define I40E_SR_NVM_MAP_VERSION 0x29
1359 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1360 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1361 #define I40E_SR_NVM_EETRACK_LO 0x2D
1362 #define I40E_SR_NVM_EETRACK_HI 0x2E
1363 #define I40E_SR_VPD_PTR 0x2F
1364 #define I40E_SR_PXE_SETUP_PTR 0x30
1365 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1366 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1367 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1368 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1369 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1370 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1371 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1372 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1373 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1374 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1375 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1376 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1377 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1378 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1379 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1380 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1381 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1382 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1384 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1385 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1386 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1387 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1388 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1390 /* Shadow RAM related */
1391 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1392 #define I40E_SR_BUF_ALIGNMENT 4096
1393 #define I40E_SR_WORDS_IN_1KB 512
1394 /* Checksum should be calculated such that after adding all the words,
1395 * including the checksum word itself, the sum should be 0xBABA.
1397 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1399 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1401 enum i40e_switch_element_types {
1402 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1403 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1404 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1405 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1406 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1407 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1408 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1409 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1410 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1413 /* Supported EtherType filters */
1414 enum i40e_ether_type_index {
1415 I40E_ETHER_TYPE_1588 = 0,
1416 I40E_ETHER_TYPE_FIP = 1,
1417 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1418 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1419 I40E_ETHER_TYPE_LLDP = 4,
1420 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1421 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1422 I40E_ETHER_TYPE_QCN_CNM = 7,
1423 I40E_ETHER_TYPE_8021X = 8,
1424 I40E_ETHER_TYPE_ARP = 9,
1425 I40E_ETHER_TYPE_RSV1 = 10,
1426 I40E_ETHER_TYPE_RSV2 = 11,
1429 /* Filter context base size is 1K */
1430 #define I40E_HASH_FILTER_BASE_SIZE 1024
1431 /* Supported Hash filter values */
1432 enum i40e_hash_filter_size {
1433 I40E_HASH_FILTER_SIZE_1K = 0,
1434 I40E_HASH_FILTER_SIZE_2K = 1,
1435 I40E_HASH_FILTER_SIZE_4K = 2,
1436 I40E_HASH_FILTER_SIZE_8K = 3,
1437 I40E_HASH_FILTER_SIZE_16K = 4,
1438 I40E_HASH_FILTER_SIZE_32K = 5,
1439 I40E_HASH_FILTER_SIZE_64K = 6,
1440 I40E_HASH_FILTER_SIZE_128K = 7,
1441 I40E_HASH_FILTER_SIZE_256K = 8,
1442 I40E_HASH_FILTER_SIZE_512K = 9,
1443 I40E_HASH_FILTER_SIZE_1M = 10,
1446 /* DMA context base size is 0.5K */
1447 #define I40E_DMA_CNTX_BASE_SIZE 512
1448 /* Supported DMA context values */
1449 enum i40e_dma_cntx_size {
1450 I40E_DMA_CNTX_SIZE_512 = 0,
1451 I40E_DMA_CNTX_SIZE_1K = 1,
1452 I40E_DMA_CNTX_SIZE_2K = 2,
1453 I40E_DMA_CNTX_SIZE_4K = 3,
1454 I40E_DMA_CNTX_SIZE_8K = 4,
1455 I40E_DMA_CNTX_SIZE_16K = 5,
1456 I40E_DMA_CNTX_SIZE_32K = 6,
1457 I40E_DMA_CNTX_SIZE_64K = 7,
1458 I40E_DMA_CNTX_SIZE_128K = 8,
1459 I40E_DMA_CNTX_SIZE_256K = 9,
1462 /* Supported Hash look up table (LUT) sizes */
1463 enum i40e_hash_lut_size {
1464 I40E_HASH_LUT_SIZE_128 = 0,
1465 I40E_HASH_LUT_SIZE_512 = 1,
1468 /* Structure to hold a per PF filter control settings */
1469 struct i40e_filter_control_settings {
1470 /* number of PE Quad Hash filter buckets */
1471 enum i40e_hash_filter_size pe_filt_num;
1472 /* number of PE Quad Hash contexts */
1473 enum i40e_dma_cntx_size pe_cntx_num;
1474 /* number of FCoE filter buckets */
1475 enum i40e_hash_filter_size fcoe_filt_num;
1476 /* number of FCoE DDP contexts */
1477 enum i40e_dma_cntx_size fcoe_cntx_num;
1478 /* size of the Hash LUT */
1479 enum i40e_hash_lut_size hash_lut_size;
1480 /* enable FDIR filters for PF and its VFs */
1482 /* enable Ethertype filters for PF and its VFs */
1483 bool enable_ethtype;
1484 /* enable MAC/VLAN filters for PF and its VFs */
1485 bool enable_macvlan;
1488 /* Structure to hold device level control filter counts */
1489 struct i40e_control_filter_stats {
1490 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1491 u16 etype_used; /* Used perfect EtherType filters */
1492 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1493 u16 etype_free; /* Un-used perfect EtherType filters */
1496 enum i40e_reset_type {
1498 I40E_RESET_CORER = 1,
1499 I40E_RESET_GLOBR = 2,
1500 I40E_RESET_EMPR = 3,
1503 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1504 #define I40E_NVM_LLDP_CFG_PTR 0xD
1505 struct i40e_lldp_variables {
1515 /* Offsets into Alternate Ram */
1516 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1517 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1518 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1519 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1520 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1521 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1523 /* Alternate Ram Bandwidth Masks */
1524 #define I40E_ALT_BW_VALUE_MASK 0xFF
1525 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1526 #define I40E_ALT_BW_VALID_MASK 0x80000000
1528 /* RSS Hash Table Size */
1529 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1530 #endif /* _I40E_TYPE_H_ */