1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
161 enum i40e_memset_type {
167 enum i40e_memcpy_type {
168 I40E_NONDMA_TO_NONDMA = 0,
176 #define I40E_FW_API_VERSION_MINOR_X722 0x0003
178 #define I40E_FW_API_VERSION_MINOR_X710 0x0004
181 /* These are structs for managing the hardware information and the operations.
182 * The structures of function pointers are filled out at init time when we
183 * know for sure exactly which hardware we're working with. This gives us the
184 * flexibility of using the same main driver code but adapting to slightly
185 * different hardware needs as new parts are developed. For this architecture,
186 * the Firmware and AdminQ are intended to insulate the driver from most of the
187 * future changes, but these structures will also do part of the job.
190 I40E_MAC_UNKNOWN = 0,
197 enum i40e_media_type {
198 I40E_MEDIA_TYPE_UNKNOWN = 0,
199 I40E_MEDIA_TYPE_FIBER,
200 I40E_MEDIA_TYPE_BASET,
201 I40E_MEDIA_TYPE_BACKPLANE,
204 I40E_MEDIA_TYPE_VIRTUAL
216 enum i40e_set_fc_aq_failures {
217 I40E_SET_FC_AQ_FAIL_NONE = 0,
218 I40E_SET_FC_AQ_FAIL_GET = 1,
219 I40E_SET_FC_AQ_FAIL_SET = 2,
220 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
221 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
233 I40E_VSI_TYPE_UNKNOWN
236 enum i40e_queue_type {
237 I40E_QUEUE_TYPE_RX = 0,
239 I40E_QUEUE_TYPE_PE_CEQ,
240 I40E_QUEUE_TYPE_UNKNOWN
243 struct i40e_link_status {
244 enum i40e_aq_phy_type phy_type;
245 enum i40e_aq_link_speed link_speed;
250 /* is Link Status Event notification to SW enabled */
257 /* 1st byte: module identifier */
258 #define I40E_MODULE_TYPE_SFP 0x03
259 #define I40E_MODULE_TYPE_QSFP 0x0D
260 /* 2nd byte: ethernet compliance codes for 10/40G */
261 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
262 #define I40E_MODULE_TYPE_40G_LR4 0x02
263 #define I40E_MODULE_TYPE_40G_SR4 0x04
264 #define I40E_MODULE_TYPE_40G_CR4 0x08
265 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
266 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
267 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
268 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
269 /* 3rd byte: ethernet compliance codes for 1G */
270 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
271 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
272 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
273 #define I40E_MODULE_TYPE_1000BASE_T 0x08
276 enum i40e_aq_capabilities_phy_type {
277 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
278 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
279 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
280 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
281 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
282 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
283 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
284 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
285 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
286 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
287 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
288 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
289 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
290 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
291 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
292 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
293 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
294 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
295 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
296 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
297 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
298 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
299 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
300 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
301 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
302 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
303 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
304 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
307 struct i40e_phy_info {
308 struct i40e_link_status link_info;
309 struct i40e_link_status link_info_old;
311 enum i40e_media_type media_type;
312 /* all the phy types the NVM is capable of */
316 #define I40E_HW_CAP_MAX_GPIO 30
317 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
318 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
320 /* Capabilities of a PF or a VF or the whole device */
321 struct i40e_hw_capabilities {
323 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
324 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
325 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
333 bool evb_802_1_qbg; /* Edge Virtual Bridging */
334 bool evb_802_1_qbh; /* Bridge Port Extension */
337 bool iscsi; /* Indicates iSCSI enabled */
341 #define I40E_FLEX10_MODE_UNKNOWN 0x0
342 #define I40E_FLEX10_MODE_DCC 0x1
343 #define I40E_FLEX10_MODE_DCI 0x2
346 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
347 #define I40E_FLEX10_STATUS_VC_MODE 0x2
353 u32 fd_filters_guaranteed;
354 u32 fd_filters_best_effort;
357 u32 rss_table_entry_width;
358 bool led[I40E_HW_CAP_MAX_GPIO];
359 bool sdp[I40E_HW_CAP_MAX_GPIO];
361 u32 num_flow_director_filters;
368 u32 num_msix_vectors;
369 u32 num_msix_vectors_vf;
379 struct i40e_mac_info {
380 enum i40e_mac_type type;
381 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
382 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
383 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
384 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
388 enum i40e_aq_resources_ids {
389 I40E_NVM_RESOURCE_ID = 1
392 enum i40e_aq_resource_access_type {
393 I40E_RESOURCE_READ = 1,
397 struct i40e_nvm_info {
398 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
399 u32 timeout; /* [ms] */
400 u16 sr_size; /* Shadow RAM size in words */
401 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
402 u16 version; /* NVM package version */
403 u32 eetrack; /* NVM data version */
404 u32 oem_ver; /* OEM version info */
407 /* definitions used in NVM update support */
409 enum i40e_nvmupd_cmd {
411 I40E_NVMUPD_READ_CON,
412 I40E_NVMUPD_READ_SNT,
413 I40E_NVMUPD_READ_LCB,
415 I40E_NVMUPD_WRITE_ERA,
416 I40E_NVMUPD_WRITE_CON,
417 I40E_NVMUPD_WRITE_SNT,
418 I40E_NVMUPD_WRITE_LCB,
419 I40E_NVMUPD_WRITE_SA,
420 I40E_NVMUPD_CSUM_CON,
422 I40E_NVMUPD_CSUM_LCB,
425 I40E_NVMUPD_GET_AQ_RESULT,
428 enum i40e_nvmupd_state {
429 I40E_NVMUPD_STATE_INIT,
430 I40E_NVMUPD_STATE_READING,
431 I40E_NVMUPD_STATE_WRITING,
432 I40E_NVMUPD_STATE_INIT_WAIT,
433 I40E_NVMUPD_STATE_WRITE_WAIT,
436 /* nvm_access definition and its masks/shifts need to be accessible to
437 * application, core driver, and shared code. Where is the right file?
439 #define I40E_NVM_READ 0xB
440 #define I40E_NVM_WRITE 0xC
442 #define I40E_NVM_MOD_PNT_MASK 0xFF
444 #define I40E_NVM_TRANS_SHIFT 8
445 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
446 #define I40E_NVM_CON 0x0
447 #define I40E_NVM_SNT 0x1
448 #define I40E_NVM_LCB 0x2
449 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
450 #define I40E_NVM_ERA 0x4
451 #define I40E_NVM_CSUM 0x8
452 #define I40E_NVM_EXEC 0xf
454 #define I40E_NVM_ADAPT_SHIFT 16
455 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
457 #define I40E_NVMUPD_MAX_DATA 4096
458 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
460 struct i40e_nvm_access {
463 u32 offset; /* in bytes */
464 u32 data_size; /* in bytes */
470 i40e_bus_type_unknown = 0,
473 i40e_bus_type_pci_express,
474 i40e_bus_type_reserved
478 enum i40e_bus_speed {
479 i40e_bus_speed_unknown = 0,
480 i40e_bus_speed_33 = 33,
481 i40e_bus_speed_66 = 66,
482 i40e_bus_speed_100 = 100,
483 i40e_bus_speed_120 = 120,
484 i40e_bus_speed_133 = 133,
485 i40e_bus_speed_2500 = 2500,
486 i40e_bus_speed_5000 = 5000,
487 i40e_bus_speed_8000 = 8000,
488 i40e_bus_speed_reserved
492 enum i40e_bus_width {
493 i40e_bus_width_unknown = 0,
494 i40e_bus_width_pcie_x1 = 1,
495 i40e_bus_width_pcie_x2 = 2,
496 i40e_bus_width_pcie_x4 = 4,
497 i40e_bus_width_pcie_x8 = 8,
498 i40e_bus_width_32 = 32,
499 i40e_bus_width_64 = 64,
500 i40e_bus_width_reserved
504 struct i40e_bus_info {
505 enum i40e_bus_speed speed;
506 enum i40e_bus_width width;
507 enum i40e_bus_type type;
514 /* Flow control (FC) parameters */
515 struct i40e_fc_info {
516 enum i40e_fc_mode current_mode; /* FC mode in effect */
517 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
520 #define I40E_MAX_TRAFFIC_CLASS 8
521 #define I40E_MAX_USER_PRIORITY 8
522 #define I40E_DCBX_MAX_APPS 32
523 #define I40E_LLDPDU_SIZE 1500
524 #define I40E_TLV_STATUS_OPER 0x1
525 #define I40E_TLV_STATUS_SYNC 0x2
526 #define I40E_TLV_STATUS_ERR 0x4
527 #define I40E_CEE_OPER_MAX_APPS 3
528 #define I40E_APP_PROTOID_FCOE 0x8906
529 #define I40E_APP_PROTOID_ISCSI 0x0cbc
530 #define I40E_APP_PROTOID_FIP 0x8914
531 #define I40E_APP_SEL_ETHTYPE 0x1
532 #define I40E_APP_SEL_TCPIP 0x2
533 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
534 #define I40E_CEE_APP_SEL_TCPIP 0x1
536 /* CEE or IEEE 802.1Qaz ETS Configuration data */
537 struct i40e_dcb_ets_config {
541 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
542 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
543 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
546 /* CEE or IEEE 802.1Qaz PFC Configuration data */
547 struct i40e_dcb_pfc_config {
554 /* CEE or IEEE 802.1Qaz Application Priority data */
555 struct i40e_dcb_app_priority_table {
561 struct i40e_dcbx_config {
563 #define I40E_DCBX_MODE_CEE 0x1
564 #define I40E_DCBX_MODE_IEEE 0x2
566 #define I40E_DCBX_APPS_NON_WILLING 0x1
568 u32 tlv_status; /* CEE mode TLV status */
569 struct i40e_dcb_ets_config etscfg;
570 struct i40e_dcb_ets_config etsrec;
571 struct i40e_dcb_pfc_config pfc;
572 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
575 /* Port hardware description */
580 /* subsystem structs */
581 struct i40e_phy_info phy;
582 struct i40e_mac_info mac;
583 struct i40e_bus_info bus;
584 struct i40e_nvm_info nvm;
585 struct i40e_fc_info fc;
590 u16 subsystem_device_id;
591 u16 subsystem_vendor_id;
594 bool adapter_stopped;
596 /* capabilities for entire device and PCI func */
597 struct i40e_hw_capabilities dev_caps;
598 struct i40e_hw_capabilities func_caps;
600 /* Flow Director shared filter space */
601 u16 fdir_shared_filter_count;
603 /* device profile info */
607 /* for multi-function MACs */
612 /* Closest numa node to the device */
615 /* Admin Queue info */
616 struct i40e_adminq_info aq;
618 /* state of nvm update process */
619 enum i40e_nvmupd_state nvmupd_state;
620 struct i40e_aq_desc nvm_wb_desc;
621 struct i40e_virt_mem nvm_buff;
624 struct i40e_hmc_info hmc; /* HMC info struct */
626 /* LLDP/DCBX Status */
630 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
631 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
632 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
636 #ifndef I40E_NDIS_SUPPORT
638 #endif /* I40E_NDIS_SUPPORT */
641 static inline bool i40e_is_vf(struct i40e_hw *hw)
643 return hw->mac.type == I40E_MAC_VF;
646 struct i40e_driver_version {
651 u8 driver_string[32];
655 union i40e_16byte_rx_desc {
657 __le64 pkt_addr; /* Packet buffer address */
658 __le64 hdr_addr; /* Header buffer address */
664 __le16 mirroring_status;
670 __le32 rss; /* RSS Hash */
671 __le32 fd_id; /* Flow director filter id */
672 __le32 fcoe_param; /* FCoE DDP Context id */
676 /* ext status/error/pktype/length */
677 __le64 status_error_len;
679 } wb; /* writeback */
682 union i40e_32byte_rx_desc {
684 __le64 pkt_addr; /* Packet buffer address */
685 __le64 hdr_addr; /* Header buffer address */
686 /* bit 0 of hdr_buffer_addr is DD bit */
694 __le16 mirroring_status;
700 __le32 rss; /* RSS Hash */
701 __le32 fcoe_param; /* FCoE DDP Context id */
702 /* Flow director filter id in case of
703 * Programming status desc WB
709 /* status/error/pktype/length */
710 __le64 status_error_len;
713 __le16 ext_status; /* extended status */
720 __le32 flex_bytes_lo;
724 __le32 flex_bytes_hi;
728 } wb; /* writeback */
731 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
732 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
733 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
734 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
735 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
736 I40E_RXD_QW0_FCOEINDX_SHIFT)
738 enum i40e_rx_desc_status_bits {
739 /* Note: These are predefined bit offsets */
740 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
741 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
742 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
743 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
744 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
745 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
746 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
747 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
749 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
750 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
751 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
752 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
753 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
754 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
755 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
756 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
759 #define I40E_RXD_QW1_STATUS_SHIFT 0
760 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
761 I40E_RXD_QW1_STATUS_SHIFT)
763 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
764 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
765 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
767 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
768 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
770 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
771 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
772 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
774 enum i40e_rx_desc_fltstat_values {
775 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
776 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
777 I40E_RX_DESC_FLTSTAT_RSV = 2,
778 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
781 #define I40E_RXD_PACKET_TYPE_UNICAST 0
782 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
783 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
784 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
786 #define I40E_RXD_QW1_ERROR_SHIFT 19
787 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
789 enum i40e_rx_desc_error_bits {
790 /* Note: These are predefined bit offsets */
791 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
792 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
793 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
794 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
795 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
796 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
797 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
798 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
799 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
802 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
803 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
804 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
805 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
806 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
807 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
810 #define I40E_RXD_QW1_PTYPE_SHIFT 30
811 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
813 /* Packet type non-ip values */
814 enum i40e_rx_l2_ptype {
815 I40E_RX_PTYPE_L2_RESERVED = 0,
816 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
817 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
818 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
819 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
820 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
821 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
822 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
823 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
824 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
825 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
826 I40E_RX_PTYPE_L2_ARP = 11,
827 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
828 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
829 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
830 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
831 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
832 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
833 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
834 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
835 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
836 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
837 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
838 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
839 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
840 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
843 struct i40e_rx_ptype_decoded {
850 u32 tunnel_end_prot:2;
851 u32 tunnel_end_frag:1;
856 enum i40e_rx_ptype_outer_ip {
857 I40E_RX_PTYPE_OUTER_L2 = 0,
858 I40E_RX_PTYPE_OUTER_IP = 1
861 enum i40e_rx_ptype_outer_ip_ver {
862 I40E_RX_PTYPE_OUTER_NONE = 0,
863 I40E_RX_PTYPE_OUTER_IPV4 = 0,
864 I40E_RX_PTYPE_OUTER_IPV6 = 1
867 enum i40e_rx_ptype_outer_fragmented {
868 I40E_RX_PTYPE_NOT_FRAG = 0,
869 I40E_RX_PTYPE_FRAG = 1
872 enum i40e_rx_ptype_tunnel_type {
873 I40E_RX_PTYPE_TUNNEL_NONE = 0,
874 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
875 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
876 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
877 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
880 enum i40e_rx_ptype_tunnel_end_prot {
881 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
882 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
883 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
886 enum i40e_rx_ptype_inner_prot {
887 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
888 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
889 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
890 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
891 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
892 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
895 enum i40e_rx_ptype_payload_layer {
896 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
897 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
898 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
899 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
902 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
903 #define I40E_RX_PTYPE_SHIFT 56
905 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
906 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
907 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
909 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
910 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
911 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
913 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
914 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
916 #define I40E_RXD_QW1_NEXTP_SHIFT 38
917 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
919 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
920 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
921 I40E_RXD_QW2_EXT_STATUS_SHIFT)
923 enum i40e_rx_desc_ext_status_bits {
924 /* Note: These are predefined bit offsets */
925 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
926 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
927 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
928 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
929 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
930 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
931 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
934 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
935 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
937 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
938 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
940 enum i40e_rx_desc_pe_status_bits {
941 /* Note: These are predefined bit offsets */
942 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
943 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
944 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
945 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
946 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
947 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
948 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
949 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
950 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
953 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
954 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
956 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
957 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
958 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
960 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
961 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
962 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
964 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
965 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
966 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
968 enum i40e_rx_prog_status_desc_status_bits {
969 /* Note: These are predefined bit offsets */
970 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
971 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
974 enum i40e_rx_prog_status_desc_prog_id_masks {
975 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
976 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
977 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
980 enum i40e_rx_prog_status_desc_error_bits {
981 /* Note: These are predefined bit offsets */
982 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
983 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
984 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
985 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
988 #define I40E_TWO_BIT_MASK 0x3
989 #define I40E_THREE_BIT_MASK 0x7
990 #define I40E_FOUR_BIT_MASK 0xF
991 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
994 struct i40e_tx_desc {
995 __le64 buffer_addr; /* Address of descriptor's data buf */
996 __le64 cmd_type_offset_bsz;
999 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1000 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1002 enum i40e_tx_desc_dtype_value {
1003 I40E_TX_DESC_DTYPE_DATA = 0x0,
1004 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1005 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1006 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1007 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1008 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1009 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1010 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1011 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1012 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1015 #define I40E_TXD_QW1_CMD_SHIFT 4
1016 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1018 enum i40e_tx_desc_cmd_bits {
1019 I40E_TX_DESC_CMD_EOP = 0x0001,
1020 I40E_TX_DESC_CMD_RS = 0x0002,
1021 I40E_TX_DESC_CMD_ICRC = 0x0004,
1022 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1023 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1024 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1025 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1026 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1027 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1028 I40E_TX_DESC_CMD_FCOET = 0x0080,
1029 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1030 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1031 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1032 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1033 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1034 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1035 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1036 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1039 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1040 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1041 I40E_TXD_QW1_OFFSET_SHIFT)
1043 enum i40e_tx_desc_length_fields {
1044 /* Note: These are predefined bit offsets */
1045 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1046 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1047 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1050 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1051 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1052 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1053 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1055 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1056 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1057 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1059 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1060 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1062 /* Context descriptors */
1063 struct i40e_tx_context_desc {
1064 __le32 tunneling_params;
1067 __le64 type_cmd_tso_mss;
1070 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1071 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1073 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1074 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1076 enum i40e_tx_ctx_desc_cmd_bits {
1077 I40E_TX_CTX_DESC_TSO = 0x01,
1078 I40E_TX_CTX_DESC_TSYN = 0x02,
1079 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1080 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1081 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1082 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1083 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1084 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1085 I40E_TX_CTX_DESC_SWPE = 0x40
1088 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1089 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1090 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1092 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1093 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1094 I40E_TXD_CTX_QW1_MSS_SHIFT)
1096 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1097 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1099 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1100 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1101 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1103 enum i40e_tx_ctx_desc_eipt_offload {
1104 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1105 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1106 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1107 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1110 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1111 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1112 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1114 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1115 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1117 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1118 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1120 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1121 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1123 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1125 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1126 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1127 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1129 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1130 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1131 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1133 struct i40e_nop_desc {
1138 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1139 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1141 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1142 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1144 enum i40e_tx_nop_desc_cmd_bits {
1145 /* Note: These are predefined bit offsets */
1146 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1147 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1148 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1151 struct i40e_filter_program_desc {
1152 __le32 qindex_flex_ptype_vsi;
1154 __le32 dtype_cmd_cntindex;
1157 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1158 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1159 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1160 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1161 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1162 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1163 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1164 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1165 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1167 /* Packet Classifier Types for filters */
1168 enum i40e_filter_pctype {
1169 /* Note: Values 0-30 are reserved for future use */
1170 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1171 /* Note: Value 32 is reserved for future use */
1172 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1173 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1174 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1175 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1176 /* Note: Values 37-40 are reserved for future use */
1177 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1178 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1179 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1180 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1181 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1182 /* Note: Value 47 is reserved for future use */
1183 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1184 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1185 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1186 /* Note: Values 51-62 are reserved for future use */
1187 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1190 enum i40e_filter_program_desc_dest {
1191 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1192 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1193 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1196 enum i40e_filter_program_desc_fd_status {
1197 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1198 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1199 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1200 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1203 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1204 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1205 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1207 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1208 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1210 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1211 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1212 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1214 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1215 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1217 enum i40e_filter_program_desc_pcmd {
1218 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1219 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1222 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1223 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1225 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1226 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1228 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1229 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1230 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1231 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1233 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1234 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1235 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1237 enum i40e_filter_type {
1238 I40E_FLOW_DIRECTOR_FLTR = 0,
1239 I40E_PE_QUAD_HASH_FLTR = 1,
1240 I40E_ETHERTYPE_FLTR,
1246 struct i40e_vsi_context {
1251 u16 vsis_unallocated;
1256 struct i40e_aqc_vsi_properties_data info;
1259 struct i40e_veb_context {
1264 u16 vebs_unallocated;
1266 struct i40e_aqc_get_veb_parameters_completion info;
1269 /* Statistics collected by each port, VSI, VEB, and S-channel */
1270 struct i40e_eth_stats {
1271 u64 rx_bytes; /* gorc */
1272 u64 rx_unicast; /* uprc */
1273 u64 rx_multicast; /* mprc */
1274 u64 rx_broadcast; /* bprc */
1275 u64 rx_discards; /* rdpc */
1276 u64 rx_unknown_protocol; /* rupp */
1277 u64 tx_bytes; /* gotc */
1278 u64 tx_unicast; /* uptc */
1279 u64 tx_multicast; /* mptc */
1280 u64 tx_broadcast; /* bptc */
1281 u64 tx_discards; /* tdpc */
1282 u64 tx_errors; /* tepc */
1285 /* Statistics collected per VEB per TC */
1286 struct i40e_veb_tc_stats {
1287 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1288 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1289 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1290 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1293 /* Statistics collected by the MAC */
1294 struct i40e_hw_port_stats {
1295 /* eth stats collected by the port */
1296 struct i40e_eth_stats eth;
1298 /* additional port specific stats */
1299 u64 tx_dropped_link_down; /* tdold */
1300 u64 crc_errors; /* crcerrs */
1301 u64 illegal_bytes; /* illerrc */
1302 u64 error_bytes; /* errbc */
1303 u64 mac_local_faults; /* mlfc */
1304 u64 mac_remote_faults; /* mrfc */
1305 u64 rx_length_errors; /* rlec */
1306 u64 link_xon_rx; /* lxonrxc */
1307 u64 link_xoff_rx; /* lxoffrxc */
1308 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1309 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1310 u64 link_xon_tx; /* lxontxc */
1311 u64 link_xoff_tx; /* lxofftxc */
1312 u64 priority_xon_tx[8]; /* pxontxc[8] */
1313 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1314 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1315 u64 rx_size_64; /* prc64 */
1316 u64 rx_size_127; /* prc127 */
1317 u64 rx_size_255; /* prc255 */
1318 u64 rx_size_511; /* prc511 */
1319 u64 rx_size_1023; /* prc1023 */
1320 u64 rx_size_1522; /* prc1522 */
1321 u64 rx_size_big; /* prc9522 */
1322 u64 rx_undersize; /* ruc */
1323 u64 rx_fragments; /* rfc */
1324 u64 rx_oversize; /* roc */
1325 u64 rx_jabber; /* rjc */
1326 u64 tx_size_64; /* ptc64 */
1327 u64 tx_size_127; /* ptc127 */
1328 u64 tx_size_255; /* ptc255 */
1329 u64 tx_size_511; /* ptc511 */
1330 u64 tx_size_1023; /* ptc1023 */
1331 u64 tx_size_1522; /* ptc1522 */
1332 u64 tx_size_big; /* ptc9522 */
1333 u64 mac_short_packet_dropped; /* mspdc */
1334 u64 checksum_error; /* xec */
1335 /* flow director stats */
1341 u64 tx_lpi_count; /* etlpic */
1342 u64 rx_lpi_count; /* erlpic */
1345 /* Checksum and Shadow RAM pointers */
1346 #define I40E_SR_NVM_CONTROL_WORD 0x00
1347 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1348 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1349 #define I40E_SR_OPTION_ROM_PTR 0x05
1350 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1351 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1352 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1353 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1354 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1355 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1356 #define I40E_SR_PE_IMAGE_PTR 0x0C
1357 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1358 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1359 #define I40E_SR_EMP_MODULE_PTR 0x0F
1360 #define I40E_SR_PBA_FLAGS 0x15
1361 #define I40E_SR_PBA_BLOCK_PTR 0x16
1362 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1363 #define I40E_NVM_OEM_VER_OFF 0x83
1364 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1365 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1366 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1367 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1368 #define I40E_SR_NVM_MAP_VERSION 0x29
1369 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1370 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1371 #define I40E_SR_NVM_EETRACK_LO 0x2D
1372 #define I40E_SR_NVM_EETRACK_HI 0x2E
1373 #define I40E_SR_VPD_PTR 0x2F
1374 #define I40E_SR_PXE_SETUP_PTR 0x30
1375 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1376 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1377 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1378 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1379 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1380 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1381 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1382 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1383 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1384 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1385 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1386 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1387 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1388 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1389 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1390 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1391 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1392 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1394 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1395 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1396 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1397 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1398 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1400 /* Shadow RAM related */
1401 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1402 #define I40E_SR_BUF_ALIGNMENT 4096
1403 #define I40E_SR_WORDS_IN_1KB 512
1404 /* Checksum should be calculated such that after adding all the words,
1405 * including the checksum word itself, the sum should be 0xBABA.
1407 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1409 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1411 enum i40e_switch_element_types {
1412 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1413 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1414 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1415 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1416 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1417 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1418 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1419 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1420 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1423 /* Supported EtherType filters */
1424 enum i40e_ether_type_index {
1425 I40E_ETHER_TYPE_1588 = 0,
1426 I40E_ETHER_TYPE_FIP = 1,
1427 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1428 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1429 I40E_ETHER_TYPE_LLDP = 4,
1430 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1431 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1432 I40E_ETHER_TYPE_QCN_CNM = 7,
1433 I40E_ETHER_TYPE_8021X = 8,
1434 I40E_ETHER_TYPE_ARP = 9,
1435 I40E_ETHER_TYPE_RSV1 = 10,
1436 I40E_ETHER_TYPE_RSV2 = 11,
1439 /* Filter context base size is 1K */
1440 #define I40E_HASH_FILTER_BASE_SIZE 1024
1441 /* Supported Hash filter values */
1442 enum i40e_hash_filter_size {
1443 I40E_HASH_FILTER_SIZE_1K = 0,
1444 I40E_HASH_FILTER_SIZE_2K = 1,
1445 I40E_HASH_FILTER_SIZE_4K = 2,
1446 I40E_HASH_FILTER_SIZE_8K = 3,
1447 I40E_HASH_FILTER_SIZE_16K = 4,
1448 I40E_HASH_FILTER_SIZE_32K = 5,
1449 I40E_HASH_FILTER_SIZE_64K = 6,
1450 I40E_HASH_FILTER_SIZE_128K = 7,
1451 I40E_HASH_FILTER_SIZE_256K = 8,
1452 I40E_HASH_FILTER_SIZE_512K = 9,
1453 I40E_HASH_FILTER_SIZE_1M = 10,
1456 /* DMA context base size is 0.5K */
1457 #define I40E_DMA_CNTX_BASE_SIZE 512
1458 /* Supported DMA context values */
1459 enum i40e_dma_cntx_size {
1460 I40E_DMA_CNTX_SIZE_512 = 0,
1461 I40E_DMA_CNTX_SIZE_1K = 1,
1462 I40E_DMA_CNTX_SIZE_2K = 2,
1463 I40E_DMA_CNTX_SIZE_4K = 3,
1464 I40E_DMA_CNTX_SIZE_8K = 4,
1465 I40E_DMA_CNTX_SIZE_16K = 5,
1466 I40E_DMA_CNTX_SIZE_32K = 6,
1467 I40E_DMA_CNTX_SIZE_64K = 7,
1468 I40E_DMA_CNTX_SIZE_128K = 8,
1469 I40E_DMA_CNTX_SIZE_256K = 9,
1472 /* Supported Hash look up table (LUT) sizes */
1473 enum i40e_hash_lut_size {
1474 I40E_HASH_LUT_SIZE_128 = 0,
1475 I40E_HASH_LUT_SIZE_512 = 1,
1478 /* Structure to hold a per PF filter control settings */
1479 struct i40e_filter_control_settings {
1480 /* number of PE Quad Hash filter buckets */
1481 enum i40e_hash_filter_size pe_filt_num;
1482 /* number of PE Quad Hash contexts */
1483 enum i40e_dma_cntx_size pe_cntx_num;
1484 /* number of FCoE filter buckets */
1485 enum i40e_hash_filter_size fcoe_filt_num;
1486 /* number of FCoE DDP contexts */
1487 enum i40e_dma_cntx_size fcoe_cntx_num;
1488 /* size of the Hash LUT */
1489 enum i40e_hash_lut_size hash_lut_size;
1490 /* enable FDIR filters for PF and its VFs */
1492 /* enable Ethertype filters for PF and its VFs */
1493 bool enable_ethtype;
1494 /* enable MAC/VLAN filters for PF and its VFs */
1495 bool enable_macvlan;
1498 /* Structure to hold device level control filter counts */
1499 struct i40e_control_filter_stats {
1500 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1501 u16 etype_used; /* Used perfect EtherType filters */
1502 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1503 u16 etype_free; /* Un-used perfect EtherType filters */
1506 enum i40e_reset_type {
1508 I40E_RESET_CORER = 1,
1509 I40E_RESET_GLOBR = 2,
1510 I40E_RESET_EMPR = 3,
1513 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1514 #define I40E_NVM_LLDP_CFG_PTR 0xD
1515 struct i40e_lldp_variables {
1525 /* Offsets into Alternate Ram */
1526 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1527 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1528 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1529 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1530 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1531 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1533 /* Alternate Ram Bandwidth Masks */
1534 #define I40E_ALT_BW_VALUE_MASK 0xFF
1535 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1536 #define I40E_ALT_BW_VALID_MASK 0x80000000
1538 /* RSS Hash Table Size */
1539 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1540 #endif /* _I40E_TYPE_H_ */