drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 161                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166
 167 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 168                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 170                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 172                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 174                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 176                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 177
 178 #define I40E_PHY_COM_REG_PAGE                   0x1E
 179 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 180 #define I40E_PHY_LED_MANUAL_ON                  0x100
 181 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 182 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 183 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 184
 185 /* Memory types */
 186 enum i40e_memset_type {
 187         I40E_NONDMA_MEM = 0,
 188         I40E_DMA_MEM
 189 };
 190
 191 /* Memcpy types */
 192 enum i40e_memcpy_type {
 193         I40E_NONDMA_TO_NONDMA = 0,
 194         I40E_NONDMA_TO_DMA,
 195         I40E_DMA_TO_DMA,
 196         I40E_DMA_TO_NONDMA
 197 };
 198
 199 #ifdef X722_SUPPORT
 200 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 201 #endif
 202 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 203
 204
 205 /* These are structs for managing the hardware information and the operations.
 206  * The structures of function pointers are filled out at init time when we
 207  * know for sure exactly which hardware we're working with.  This gives us the
 208  * flexibility of using the same main driver code but adapting to slightly
 209  * different hardware needs as new parts are developed.  For this architecture,
 210  * the Firmware and AdminQ are intended to insulate the driver from most of the
 211  * future changes, but these structures will also do part of the job.
 212  */
 213 enum i40e_mac_type {
 214         I40E_MAC_UNKNOWN = 0,
 215         I40E_MAC_XL710,
 216         I40E_MAC_VF,
 217 #ifdef X722_SUPPORT
 218         I40E_MAC_X722,
 219         I40E_MAC_X722_VF,
 220 #endif
 221         I40E_MAC_GENERIC,
 222 };
 223
 224 enum i40e_media_type {
 225         I40E_MEDIA_TYPE_UNKNOWN = 0,
 226         I40E_MEDIA_TYPE_FIBER,
 227         I40E_MEDIA_TYPE_BASET,
 228         I40E_MEDIA_TYPE_BACKPLANE,
 229         I40E_MEDIA_TYPE_CX4,
 230         I40E_MEDIA_TYPE_DA,
 231         I40E_MEDIA_TYPE_VIRTUAL
 232 };
 233
 234 enum i40e_fc_mode {
 235         I40E_FC_NONE = 0,
 236         I40E_FC_RX_PAUSE,
 237         I40E_FC_TX_PAUSE,
 238         I40E_FC_FULL,
 239         I40E_FC_PFC,
 240         I40E_FC_DEFAULT
 241 };
 242
 243 enum i40e_set_fc_aq_failures {
 244         I40E_SET_FC_AQ_FAIL_NONE = 0,
 245         I40E_SET_FC_AQ_FAIL_GET = 1,
 246         I40E_SET_FC_AQ_FAIL_SET = 2,
 247         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 248         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 249 };
 250
 251 enum i40e_vsi_type {
 252         I40E_VSI_MAIN   = 0,
 253         I40E_VSI_VMDQ1  = 1,
 254         I40E_VSI_VMDQ2  = 2,
 255         I40E_VSI_CTRL   = 3,
 256         I40E_VSI_FCOE   = 4,
 257         I40E_VSI_MIRROR = 5,
 258         I40E_VSI_SRIOV  = 6,
 259         I40E_VSI_FDIR   = 7,
 260         I40E_VSI_TYPE_UNKNOWN
 261 };
 262
 263 enum i40e_queue_type {
 264         I40E_QUEUE_TYPE_RX = 0,
 265         I40E_QUEUE_TYPE_TX,
 266         I40E_QUEUE_TYPE_PE_CEQ,
 267         I40E_QUEUE_TYPE_UNKNOWN
 268 };
 269
 270 struct i40e_link_status {
 271         enum i40e_aq_phy_type phy_type;
 272         enum i40e_aq_link_speed link_speed;
 273         u8 link_info;
 274         u8 an_info;
 275         u8 fec_info;
 276         u8 ext_info;
 277         u8 loopback;
 278         /* is Link Status Event notification to SW enabled */
 279         bool lse_enable;
 280         u16 max_frame_size;
 281         bool crc_enable;
 282         u8 pacing;
 283         u8 requested_speeds;
 284         u8 module_type[3];
 285         /* 1st byte: module identifier */
 286 #define I40E_MODULE_TYPE_SFP            0x03
 287 #define I40E_MODULE_TYPE_QSFP           0x0D
 288         /* 2nd byte: ethernet compliance codes for 10/40G */
 289 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 290 #define I40E_MODULE_TYPE_40G_LR4        0x02
 291 #define I40E_MODULE_TYPE_40G_SR4        0x04
 292 #define I40E_MODULE_TYPE_40G_CR4        0x08
 293 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 294 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 295 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 296 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 297         /* 3rd byte: ethernet compliance codes for 1G */
 298 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 299 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 300 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 301 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 302 };
 303
 304 struct i40e_phy_info {
 305         struct i40e_link_status link_info;
 306         struct i40e_link_status link_info_old;
 307         bool get_link_info;
 308         enum i40e_media_type media_type;
 309         /* all the phy types the NVM is capable of */
 310         u64 phy_types;
 311 };
 312
 313 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 314 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 317 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 318 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 319 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 320 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 321 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 322 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 323 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 325 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 326 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 327 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 328 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 330 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 331 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 332 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 333 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 334 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 335 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 336 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 337 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 338 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 339 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 340                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 341 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 342 /*
 343  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 344  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 345  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 346  * a shift is needed to adjust for this with values larger than 31. The
 347  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 348  */
 349 #define I40E_PHY_TYPE_OFFSET 1
 350 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 351                                              I40E_PHY_TYPE_OFFSET)
 352 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 353                                              I40E_PHY_TYPE_OFFSET)
 354 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 355                                              I40E_PHY_TYPE_OFFSET)
 356 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 357                                              I40E_PHY_TYPE_OFFSET)
 358 #define I40E_HW_CAP_MAX_GPIO                    30
 359 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 360 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 361
 362 #ifdef X722_SUPPORT
 363 enum i40e_acpi_programming_method {
 364         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 365         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 366 };
 367
 368 #define I40E_WOL_SUPPORT_MASK                   0x1
 369 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 370 #define I40E_PROXY_SUPPORT_MASK                 0x4
 371
 372 #endif
 373 /* Capabilities of a PF or a VF or the whole device */
 374 struct i40e_hw_capabilities {
 375         u32  switch_mode;
 376 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 377 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 378 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 379
 380         u32  management_mode;
 381         u32  mng_protocols_over_mctp;
 382 #define I40E_MNG_PROTOCOL_PLDM          0x2
 383 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 384 #define I40E_MNG_PROTOCOL_NCSI          0x8
 385         u32  npar_enable;
 386         u32  os2bmc;
 387         u32  valid_functions;
 388         bool sr_iov_1_1;
 389         bool vmdq;
 390         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 391         bool evb_802_1_qbh; /* Bridge Port Extension */
 392         bool dcb;
 393         bool fcoe;
 394         bool iscsi; /* Indicates iSCSI enabled */
 395         bool flex10_enable;
 396         bool flex10_capable;
 397         u32  flex10_mode;
 398 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 399 #define I40E_FLEX10_MODE_DCC            0x1
 400 #define I40E_FLEX10_MODE_DCI            0x2
 401
 402         u32 flex10_status;
 403 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 404 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 405
 406         bool sec_rev_disabled;
 407         bool update_disabled;
 408 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 409 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 410
 411         bool mgmt_cem;
 412         bool ieee_1588;
 413         bool iwarp;
 414         bool fd;
 415         u32 fd_filters_guaranteed;
 416         u32 fd_filters_best_effort;
 417         bool rss;
 418         u32 rss_table_size;
 419         u32 rss_table_entry_width;
 420         bool led[I40E_HW_CAP_MAX_GPIO];
 421         bool sdp[I40E_HW_CAP_MAX_GPIO];
 422         u32 nvm_image_type;
 423         u32 num_flow_director_filters;
 424         u32 num_vfs;
 425         u32 vf_base_id;
 426         u32 num_vsis;
 427         u32 num_rx_qp;
 428         u32 num_tx_qp;
 429         u32 base_queue;
 430         u32 num_msix_vectors;
 431         u32 num_msix_vectors_vf;
 432         u32 led_pin_num;
 433         u32 sdp_pin_num;
 434         u32 mdio_port_num;
 435         u32 mdio_port_mode;
 436         u8 rx_buf_chain_len;
 437         u32 enabled_tcmap;
 438         u32 maxtc;
 439         u64 wr_csr_prot;
 440 #ifdef X722_SUPPORT
 441         bool apm_wol_support;
 442         enum i40e_acpi_programming_method acpi_prog_method;
 443         bool proxy_support;
 444 #endif
 445 };
 446
 447 struct i40e_mac_info {
 448         enum i40e_mac_type type;
 449         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 450         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 451         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 452         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 453         u16 max_fcoeq;
 454 };
 455
 456 enum i40e_aq_resources_ids {
 457         I40E_NVM_RESOURCE_ID = 1
 458 };
 459
 460 enum i40e_aq_resource_access_type {
 461         I40E_RESOURCE_READ = 1,
 462         I40E_RESOURCE_WRITE
 463 };
 464
 465 struct i40e_nvm_info {
 466         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 467         u32 timeout;              /* [ms] */
 468         u16 sr_size;              /* Shadow RAM size in words */
 469         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 470         u16 version;              /* NVM package version */
 471         u32 eetrack;              /* NVM data version */
 472         u32 oem_ver;              /* OEM version info */
 473 };
 474
 475 /* definitions used in NVM update support */
 476
 477 enum i40e_nvmupd_cmd {
 478         I40E_NVMUPD_INVALID,
 479         I40E_NVMUPD_READ_CON,
 480         I40E_NVMUPD_READ_SNT,
 481         I40E_NVMUPD_READ_LCB,
 482         I40E_NVMUPD_READ_SA,
 483         I40E_NVMUPD_WRITE_ERA,
 484         I40E_NVMUPD_WRITE_CON,
 485         I40E_NVMUPD_WRITE_SNT,
 486         I40E_NVMUPD_WRITE_LCB,
 487         I40E_NVMUPD_WRITE_SA,
 488         I40E_NVMUPD_CSUM_CON,
 489         I40E_NVMUPD_CSUM_SA,
 490         I40E_NVMUPD_CSUM_LCB,
 491         I40E_NVMUPD_STATUS,
 492         I40E_NVMUPD_EXEC_AQ,
 493         I40E_NVMUPD_GET_AQ_RESULT,
 494 };
 495
 496 enum i40e_nvmupd_state {
 497         I40E_NVMUPD_STATE_INIT,
 498         I40E_NVMUPD_STATE_READING,
 499         I40E_NVMUPD_STATE_WRITING,
 500         I40E_NVMUPD_STATE_INIT_WAIT,
 501         I40E_NVMUPD_STATE_WRITE_WAIT,
 502 };
 503
 504 /* nvm_access definition and its masks/shifts need to be accessible to
 505  * application, core driver, and shared code.  Where is the right file?
 506  */
 507 #define I40E_NVM_READ   0xB
 508 #define I40E_NVM_WRITE  0xC
 509
 510 #define I40E_NVM_MOD_PNT_MASK 0xFF
 511
 512 #define I40E_NVM_TRANS_SHIFT    8
 513 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 514 #define I40E_NVM_CON            0x0
 515 #define I40E_NVM_SNT            0x1
 516 #define I40E_NVM_LCB            0x2
 517 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 518 #define I40E_NVM_ERA            0x4
 519 #define I40E_NVM_CSUM           0x8
 520 #define I40E_NVM_EXEC           0xf
 521
 522 #define I40E_NVM_ADAPT_SHIFT    16
 523 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 524
 525 #define I40E_NVMUPD_MAX_DATA    4096
 526 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 527
 528 struct i40e_nvm_access {
 529         u32 command;
 530         u32 config;
 531         u32 offset;     /* in bytes */
 532         u32 data_size;  /* in bytes */
 533         u8 data[1];
 534 };
 535
 536 /* PCI bus types */
 537 enum i40e_bus_type {
 538         i40e_bus_type_unknown = 0,
 539         i40e_bus_type_pci,
 540         i40e_bus_type_pcix,
 541         i40e_bus_type_pci_express,
 542         i40e_bus_type_reserved
 543 };
 544
 545 /* PCI bus speeds */
 546 enum i40e_bus_speed {
 547         i40e_bus_speed_unknown  = 0,
 548         i40e_bus_speed_33       = 33,
 549         i40e_bus_speed_66       = 66,
 550         i40e_bus_speed_100      = 100,
 551         i40e_bus_speed_120      = 120,
 552         i40e_bus_speed_133      = 133,
 553         i40e_bus_speed_2500     = 2500,
 554         i40e_bus_speed_5000     = 5000,
 555         i40e_bus_speed_8000     = 8000,
 556         i40e_bus_speed_reserved
 557 };
 558
 559 /* PCI bus widths */
 560 enum i40e_bus_width {
 561         i40e_bus_width_unknown  = 0,
 562         i40e_bus_width_pcie_x1  = 1,
 563         i40e_bus_width_pcie_x2  = 2,
 564         i40e_bus_width_pcie_x4  = 4,
 565         i40e_bus_width_pcie_x8  = 8,
 566         i40e_bus_width_32       = 32,
 567         i40e_bus_width_64       = 64,
 568         i40e_bus_width_reserved
 569 };
 570
 571 /* Bus parameters */
 572 struct i40e_bus_info {
 573         enum i40e_bus_speed speed;
 574         enum i40e_bus_width width;
 575         enum i40e_bus_type type;
 576
 577         u16 func;
 578         u16 device;
 579         u16 lan_id;
 580         u16 bus_id;
 581 };
 582
 583 /* Flow control (FC) parameters */
 584 struct i40e_fc_info {
 585         enum i40e_fc_mode current_mode; /* FC mode in effect */
 586         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 587 };
 588
 589 #define I40E_MAX_TRAFFIC_CLASS          8
 590 #define I40E_MAX_USER_PRIORITY          8
 591 #define I40E_DCBX_MAX_APPS              32
 592 #define I40E_LLDPDU_SIZE                1500
 593 #define I40E_TLV_STATUS_OPER            0x1
 594 #define I40E_TLV_STATUS_SYNC            0x2
 595 #define I40E_TLV_STATUS_ERR             0x4
 596 #define I40E_CEE_OPER_MAX_APPS          3
 597 #define I40E_APP_PROTOID_FCOE           0x8906
 598 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 599 #define I40E_APP_PROTOID_FIP            0x8914
 600 #define I40E_APP_SEL_ETHTYPE            0x1
 601 #define I40E_APP_SEL_TCPIP              0x2
 602 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 603 #define I40E_CEE_APP_SEL_TCPIP          0x1
 604
 605 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 606 struct i40e_dcb_ets_config {
 607         u8 willing;
 608         u8 cbs;
 609         u8 maxtcs;
 610         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 611         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 612         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 613 };
 614
 615 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 616 struct i40e_dcb_pfc_config {
 617         u8 willing;
 618         u8 mbc;
 619         u8 pfccap;
 620         u8 pfcenable;
 621 };
 622
 623 /* CEE or IEEE 802.1Qaz Application Priority data */
 624 struct i40e_dcb_app_priority_table {
 625         u8  priority;
 626         u8  selector;
 627         u16 protocolid;
 628 };
 629
 630 struct i40e_dcbx_config {
 631         u8  dcbx_mode;
 632 #define I40E_DCBX_MODE_CEE      0x1
 633 #define I40E_DCBX_MODE_IEEE     0x2
 634         u8  app_mode;
 635 #define I40E_DCBX_APPS_NON_WILLING      0x1
 636         u32 numapps;
 637         u32 tlv_status; /* CEE mode TLV status */
 638         struct i40e_dcb_ets_config etscfg;
 639         struct i40e_dcb_ets_config etsrec;
 640         struct i40e_dcb_pfc_config pfc;
 641         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 642 };
 643
 644 /* Port hardware description */
 645 struct i40e_hw {
 646         u8 *hw_addr;
 647         void *back;
 648
 649         /* subsystem structs */
 650         struct i40e_phy_info phy;
 651         struct i40e_mac_info mac;
 652         struct i40e_bus_info bus;
 653         struct i40e_nvm_info nvm;
 654         struct i40e_fc_info fc;
 655
 656         /* pci info */
 657         u16 device_id;
 658         u16 vendor_id;
 659         u16 subsystem_device_id;
 660         u16 subsystem_vendor_id;
 661         u8 revision_id;
 662         u8 port;
 663         bool adapter_stopped;
 664
 665         /* capabilities for entire device and PCI func */
 666         struct i40e_hw_capabilities dev_caps;
 667         struct i40e_hw_capabilities func_caps;
 668
 669         /* Flow Director shared filter space */
 670         u16 fdir_shared_filter_count;
 671
 672         /* device profile info */
 673         u8  pf_id;
 674         u16 main_vsi_seid;
 675
 676         /* for multi-function MACs */
 677         u16 partition_id;
 678         u16 num_partitions;
 679         u16 num_ports;
 680
 681         /* Closest numa node to the device */
 682         u16 numa_node;
 683
 684         /* Admin Queue info */
 685         struct i40e_adminq_info aq;
 686
 687         /* state of nvm update process */
 688         enum i40e_nvmupd_state nvmupd_state;
 689         struct i40e_aq_desc nvm_wb_desc;
 690         struct i40e_virt_mem nvm_buff;
 691         bool nvm_release_on_done;
 692         u16 nvm_wait_opcode;
 693
 694         /* HMC info */
 695         struct i40e_hmc_info hmc; /* HMC info struct */
 696
 697         /* LLDP/DCBX Status */
 698         u16 dcbx_status;
 699
 700         /* DCBX info */
 701         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 702         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 703         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 704
 705 #ifdef X722_SUPPORT
 706         /* WoL and proxy support */
 707         u16 num_wol_proxy_filters;
 708         u16 wol_proxy_vsi_seid;
 709
 710 #endif
 711 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 712         u64 flags;
 713
 714         /* debug mask */
 715         u32 debug_mask;
 716 #ifndef I40E_NDIS_SUPPORT
 717         char err_str[16];
 718 #endif /* I40E_NDIS_SUPPORT */
 719 };
 720
 721 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 722 {
 723 #ifdef X722_SUPPORT
 724         return (hw->mac.type == I40E_MAC_VF ||
 725                 hw->mac.type == I40E_MAC_X722_VF);
 726 #else
 727         return hw->mac.type == I40E_MAC_VF;
 728 #endif
 729 }
 730
 731 struct i40e_driver_version {
 732         u8 major_version;
 733         u8 minor_version;
 734         u8 build_version;
 735         u8 subbuild_version;
 736         u8 driver_string[32];
 737 };
 738
 739 /* RX Descriptors */
 740 union i40e_16byte_rx_desc {
 741         struct {
 742                 __le64 pkt_addr; /* Packet buffer address */
 743                 __le64 hdr_addr; /* Header buffer address */
 744         } read;
 745         struct {
 746                 struct {
 747                         struct {
 748                                 union {
 749                                         __le16 mirroring_status;
 750                                         __le16 fcoe_ctx_id;
 751                                 } mirr_fcoe;
 752                                 __le16 l2tag1;
 753                         } lo_dword;
 754                         union {
 755                                 __le32 rss; /* RSS Hash */
 756                                 __le32 fd_id; /* Flow director filter id */
 757                                 __le32 fcoe_param; /* FCoE DDP Context id */
 758                         } hi_dword;
 759                 } qword0;
 760                 struct {
 761                         /* ext status/error/pktype/length */
 762                         __le64 status_error_len;
 763                 } qword1;
 764         } wb;  /* writeback */
 765 };
 766
 767 union i40e_32byte_rx_desc {
 768         struct {
 769                 __le64  pkt_addr; /* Packet buffer address */
 770                 __le64  hdr_addr; /* Header buffer address */
 771                         /* bit 0 of hdr_buffer_addr is DD bit */
 772                 __le64  rsvd1;
 773                 __le64  rsvd2;
 774         } read;
 775         struct {
 776                 struct {
 777                         struct {
 778                                 union {
 779                                         __le16 mirroring_status;
 780                                         __le16 fcoe_ctx_id;
 781                                 } mirr_fcoe;
 782                                 __le16 l2tag1;
 783                         } lo_dword;
 784                         union {
 785                                 __le32 rss; /* RSS Hash */
 786                                 __le32 fcoe_param; /* FCoE DDP Context id */
 787                                 /* Flow director filter id in case of
 788                                  * Programming status desc WB
 789                                  */
 790                                 __le32 fd_id;
 791                         } hi_dword;
 792                 } qword0;
 793                 struct {
 794                         /* status/error/pktype/length */
 795                         __le64 status_error_len;
 796                 } qword1;
 797                 struct {
 798                         __le16 ext_status; /* extended status */
 799                         __le16 rsvd;
 800                         __le16 l2tag2_1;
 801                         __le16 l2tag2_2;
 802                 } qword2;
 803                 struct {
 804                         union {
 805                                 __le32 flex_bytes_lo;
 806                                 __le32 pe_status;
 807                         } lo_dword;
 808                         union {
 809                                 __le32 flex_bytes_hi;
 810                                 __le32 fd_id;
 811                         } hi_dword;
 812                 } qword3;
 813         } wb;  /* writeback */
 814 };
 815
 816 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 817 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 818                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 819 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 820 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 821                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 822
 823 enum i40e_rx_desc_status_bits {
 824         /* Note: These are predefined bit offsets */
 825         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 826         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 827         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 828         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 829         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 830         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 831         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 832 #ifdef X722_SUPPORT
 833         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 834 #else
 835         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 836 #endif
 837
 838         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 839         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 840         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 841         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 842         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 843         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 844 #ifdef X722_SUPPORT
 845         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 846 #else
 847         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 848 #endif
 849         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 850 };
 851
 852 #define I40E_RXD_QW1_STATUS_SHIFT       0
 853 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 854                                          I40E_RXD_QW1_STATUS_SHIFT)
 855
 856 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 857 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 858                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 859
 860 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 861 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 862
 863 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 864 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 865                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 866
 867 enum i40e_rx_desc_fltstat_values {
 868         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 869         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 870         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 871         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 872 };
 873
 874 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 875 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 876 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 877 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 878
 879 #define I40E_RXD_QW1_ERROR_SHIFT        19
 880 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 881
 882 enum i40e_rx_desc_error_bits {
 883         /* Note: These are predefined bit offsets */
 884         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 885         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 886         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 887         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 888         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 889         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 890         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 891         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 892         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 893 };
 894
 895 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 896         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 897         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 898         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 899         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 900         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 901 };
 902
 903 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 904 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 905
 906 /* Packet type non-ip values */
 907 enum i40e_rx_l2_ptype {
 908         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 909         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 910         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 911         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 912         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 913         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 914         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 915         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 916         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 917         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 918         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 919         I40E_RX_PTYPE_L2_ARP                            = 11,
 920         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 921         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 922         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 923         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 924         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 925         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 926         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 927         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 928         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 929         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 930         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 931         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 932         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 933         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 934 };
 935
 936 struct i40e_rx_ptype_decoded {
 937         u32 ptype:8;
 938         u32 known:1;
 939         u32 outer_ip:1;
 940         u32 outer_ip_ver:1;
 941         u32 outer_frag:1;
 942         u32 tunnel_type:3;
 943         u32 tunnel_end_prot:2;
 944         u32 tunnel_end_frag:1;
 945         u32 inner_prot:4;
 946         u32 payload_layer:3;
 947 };
 948
 949 enum i40e_rx_ptype_outer_ip {
 950         I40E_RX_PTYPE_OUTER_L2  = 0,
 951         I40E_RX_PTYPE_OUTER_IP  = 1
 952 };
 953
 954 enum i40e_rx_ptype_outer_ip_ver {
 955         I40E_RX_PTYPE_OUTER_NONE        = 0,
 956         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 957         I40E_RX_PTYPE_OUTER_IPV6        = 1
 958 };
 959
 960 enum i40e_rx_ptype_outer_fragmented {
 961         I40E_RX_PTYPE_NOT_FRAG  = 0,
 962         I40E_RX_PTYPE_FRAG      = 1
 963 };
 964
 965 enum i40e_rx_ptype_tunnel_type {
 966         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 967         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 968         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 969         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 970         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 971 };
 972
 973 enum i40e_rx_ptype_tunnel_end_prot {
 974         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 975         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 976         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 977 };
 978
 979 enum i40e_rx_ptype_inner_prot {
 980         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 981         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 982         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 983         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 984         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 985         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 986 };
 987
 988 enum i40e_rx_ptype_payload_layer {
 989         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 990         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 991         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 992         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 993 };
 994
 995 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 996 #define I40E_RX_PTYPE_SHIFT             56
 997
 998 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 999 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1000                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1001
1002 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
1003 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1004                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1005
1006 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1007 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1008
1009 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1010 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1011
1012 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1013 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1014                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1015
1016 enum i40e_rx_desc_ext_status_bits {
1017         /* Note: These are predefined bit offsets */
1018         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1019         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1020         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1021         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1022         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1023         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1024         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1025 };
1026
1027 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1028 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1029
1030 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1031 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1032
1033 enum i40e_rx_desc_pe_status_bits {
1034         /* Note: These are predefined bit offsets */
1035         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1036         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1037         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1038         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1039         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1040         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1041         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1042         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1043         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1044 };
1045
1046 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1047 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1048
1049 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1050 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1051                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1052
1053 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1054 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1055                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1056
1057 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1058 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1059                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1060
1061 enum i40e_rx_prog_status_desc_status_bits {
1062         /* Note: These are predefined bit offsets */
1063         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1064         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1065 };
1066
1067 enum i40e_rx_prog_status_desc_prog_id_masks {
1068         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1069         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1070         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1071 };
1072
1073 enum i40e_rx_prog_status_desc_error_bits {
1074         /* Note: These are predefined bit offsets */
1075         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1076         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1077         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1078         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1079 };
1080
1081 #define I40E_TWO_BIT_MASK       0x3
1082 #define I40E_THREE_BIT_MASK     0x7
1083 #define I40E_FOUR_BIT_MASK      0xF
1084 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1085
1086 /* TX Descriptor */
1087 struct i40e_tx_desc {
1088         __le64 buffer_addr; /* Address of descriptor's data buf */
1089         __le64 cmd_type_offset_bsz;
1090 };
1091
1092 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1093 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1094
1095 enum i40e_tx_desc_dtype_value {
1096         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1097         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1098         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1099         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1100         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1101         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1102         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1103         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1104         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1105         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1106 };
1107
1108 #define I40E_TXD_QW1_CMD_SHIFT  4
1109 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1110
1111 enum i40e_tx_desc_cmd_bits {
1112         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1113         I40E_TX_DESC_CMD_RS                     = 0x0002,
1114         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1115         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1116         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1117         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1118         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1119         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1120         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1121         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1122         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1123         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1124         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1125         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1126         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1127         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1128         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1129         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1130 };
1131
1132 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1133 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1134                                          I40E_TXD_QW1_OFFSET_SHIFT)
1135
1136 enum i40e_tx_desc_length_fields {
1137         /* Note: These are predefined bit offsets */
1138         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1139         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1140         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1141 };
1142
1143 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1144 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1145 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1146 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1147
1148 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1149 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1150                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1151
1152 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1153 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1154
1155 /* Context descriptors */
1156 struct i40e_tx_context_desc {
1157         __le32 tunneling_params;
1158         __le16 l2tag2;
1159         __le16 rsvd;
1160         __le64 type_cmd_tso_mss;
1161 };
1162
1163 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1164 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1165
1166 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1167 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1168
1169 enum i40e_tx_ctx_desc_cmd_bits {
1170         I40E_TX_CTX_DESC_TSO            = 0x01,
1171         I40E_TX_CTX_DESC_TSYN           = 0x02,
1172         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1173         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1174         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1175         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1176         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1177         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1178         I40E_TX_CTX_DESC_SWPE           = 0x40
1179 };
1180
1181 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1182 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1183                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1184
1185 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1186 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1187                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1188
1189 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1190 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1191
1192 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1193 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1194                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1195
1196 enum i40e_tx_ctx_desc_eipt_offload {
1197         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1198         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1199         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1200         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1201 };
1202
1203 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1204 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1205                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1206
1207 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1208 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1209
1210 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1211 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1212
1213 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1214 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1215
1216 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1217
1218 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1219 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1220                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1221
1222 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1223 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1224                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1225
1226 #ifdef X722_SUPPORT
1227 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1228 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1229 #endif
1230 struct i40e_nop_desc {
1231         __le64 rsvd;
1232         __le64 dtype_cmd;
1233 };
1234
1235 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1236 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1237
1238 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1239 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1240
1241 enum i40e_tx_nop_desc_cmd_bits {
1242         /* Note: These are predefined bit offsets */
1243         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1244         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1245         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1246 };
1247
1248 struct i40e_filter_program_desc {
1249         __le32 qindex_flex_ptype_vsi;
1250         __le32 rsvd;
1251         __le32 dtype_cmd_cntindex;
1252         __le32 fd_id;
1253 };
1254 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1255 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1256                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1257 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1258 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1259                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1260 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1261 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1262                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1263
1264 /* Packet Classifier Types for filters */
1265 enum i40e_filter_pctype {
1266 #ifdef X722_SUPPORT
1267         /* Note: Values 0-28 are reserved for future use.
1268          * Value 29, 30, 32 are not supported on XL710 and X710.
1269          */
1270         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1271         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1272 #else
1273         /* Note: Values 0-30 are reserved for future use */
1274 #endif
1275         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1276 #ifdef X722_SUPPORT
1277         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1278 #else
1279         /* Note: Value 32 is reserved for future use */
1280 #endif
1281         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1282         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1283         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1284         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1285 #ifdef X722_SUPPORT
1286         /* Note: Values 37-38 are reserved for future use.
1287          * Value 39, 40, 42 are not supported on XL710 and X710.
1288          */
1289         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1290         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1291 #else
1292         /* Note: Values 37-40 are reserved for future use */
1293 #endif
1294         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1295 #ifdef X722_SUPPORT
1296         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1297 #endif
1298         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1299         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1300         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1301         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1302         /* Note: Value 47 is reserved for future use */
1303         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1304         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1305         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1306         /* Note: Values 51-62 are reserved for future use */
1307         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1308 };
1309
1310 enum i40e_filter_program_desc_dest {
1311         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1312         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1313         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1314 };
1315
1316 enum i40e_filter_program_desc_fd_status {
1317         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1318         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1319         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1320         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1321 };
1322
1323 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1324 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1325                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1326
1327 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1328 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1329
1330 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1331 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1332                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1333
1334 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1335 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1336
1337 enum i40e_filter_program_desc_pcmd {
1338         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1339         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1340 };
1341
1342 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1343 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1344
1345 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1346 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1347
1348 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1349                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1350 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1351                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1352 #ifdef X722_SUPPORT
1353
1354 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1355                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1356 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1357 #endif
1358
1359 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1360 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1361                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1362
1363 enum i40e_filter_type {
1364         I40E_FLOW_DIRECTOR_FLTR = 0,
1365         I40E_PE_QUAD_HASH_FLTR = 1,
1366         I40E_ETHERTYPE_FLTR,
1367         I40E_FCOE_CTX_FLTR,
1368         I40E_MAC_VLAN_FLTR,
1369         I40E_HASH_FLTR
1370 };
1371
1372 struct i40e_vsi_context {
1373         u16 seid;
1374         u16 uplink_seid;
1375         u16 vsi_number;
1376         u16 vsis_allocated;
1377         u16 vsis_unallocated;
1378         u16 flags;
1379         u8 pf_num;
1380         u8 vf_num;
1381         u8 connection_type;
1382         struct i40e_aqc_vsi_properties_data info;
1383 };
1384
1385 struct i40e_veb_context {
1386         u16 seid;
1387         u16 uplink_seid;
1388         u16 veb_number;
1389         u16 vebs_allocated;
1390         u16 vebs_unallocated;
1391         u16 flags;
1392         struct i40e_aqc_get_veb_parameters_completion info;
1393 };
1394
1395 /* Statistics collected by each port, VSI, VEB, and S-channel */
1396 struct i40e_eth_stats {
1397         u64 rx_bytes;                   /* gorc */
1398         u64 rx_unicast;                 /* uprc */
1399         u64 rx_multicast;               /* mprc */
1400         u64 rx_broadcast;               /* bprc */
1401         u64 rx_discards;                /* rdpc */
1402         u64 rx_unknown_protocol;        /* rupp */
1403         u64 tx_bytes;                   /* gotc */
1404         u64 tx_unicast;                 /* uptc */
1405         u64 tx_multicast;               /* mptc */
1406         u64 tx_broadcast;               /* bptc */
1407         u64 tx_discards;                /* tdpc */
1408         u64 tx_errors;                  /* tepc */
1409 };
1410
1411 /* Statistics collected per VEB per TC */
1412 struct i40e_veb_tc_stats {
1413         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1414         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1415         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1416         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1417 };
1418
1419 /* Statistics collected per function for FCoE */
1420 struct i40e_fcoe_stats {
1421         u64 rx_fcoe_packets;            /* fcoeprc */
1422         u64 rx_fcoe_dwords;             /* focedwrc */
1423         u64 rx_fcoe_dropped;            /* fcoerpdc */
1424         u64 tx_fcoe_packets;            /* fcoeptc */
1425         u64 tx_fcoe_dwords;             /* focedwtc */
1426         u64 fcoe_bad_fccrc;             /* fcoecrc */
1427         u64 fcoe_last_error;            /* fcoelast */
1428         u64 fcoe_ddp_count;             /* fcoeddpc */
1429 };
1430
1431 /* offset to per function FCoE statistics block */
1432 #define I40E_FCOE_VF_STAT_OFFSET        0
1433 #define I40E_FCOE_PF_STAT_OFFSET        128
1434 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1435
1436 /* Statistics collected by the MAC */
1437 struct i40e_hw_port_stats {
1438         /* eth stats collected by the port */
1439         struct i40e_eth_stats eth;
1440
1441         /* additional port specific stats */
1442         u64 tx_dropped_link_down;       /* tdold */
1443         u64 crc_errors;                 /* crcerrs */
1444         u64 illegal_bytes;              /* illerrc */
1445         u64 error_bytes;                /* errbc */
1446         u64 mac_local_faults;           /* mlfc */
1447         u64 mac_remote_faults;          /* mrfc */
1448         u64 rx_length_errors;           /* rlec */
1449         u64 link_xon_rx;                /* lxonrxc */
1450         u64 link_xoff_rx;               /* lxoffrxc */
1451         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1452         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1453         u64 link_xon_tx;                /* lxontxc */
1454         u64 link_xoff_tx;               /* lxofftxc */
1455         u64 priority_xon_tx[8];         /* pxontxc[8] */
1456         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1457         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1458         u64 rx_size_64;                 /* prc64 */
1459         u64 rx_size_127;                /* prc127 */
1460         u64 rx_size_255;                /* prc255 */
1461         u64 rx_size_511;                /* prc511 */
1462         u64 rx_size_1023;               /* prc1023 */
1463         u64 rx_size_1522;               /* prc1522 */
1464         u64 rx_size_big;                /* prc9522 */
1465         u64 rx_undersize;               /* ruc */
1466         u64 rx_fragments;               /* rfc */
1467         u64 rx_oversize;                /* roc */
1468         u64 rx_jabber;                  /* rjc */
1469         u64 tx_size_64;                 /* ptc64 */
1470         u64 tx_size_127;                /* ptc127 */
1471         u64 tx_size_255;                /* ptc255 */
1472         u64 tx_size_511;                /* ptc511 */
1473         u64 tx_size_1023;               /* ptc1023 */
1474         u64 tx_size_1522;               /* ptc1522 */
1475         u64 tx_size_big;                /* ptc9522 */
1476         u64 mac_short_packet_dropped;   /* mspdc */
1477         u64 checksum_error;             /* xec */
1478         /* flow director stats */
1479         u64 fd_atr_match;
1480         u64 fd_sb_match;
1481         u64 fd_atr_tunnel_match;
1482         u32 fd_atr_status;
1483         u32 fd_sb_status;
1484         /* EEE LPI */
1485         u32 tx_lpi_status;
1486         u32 rx_lpi_status;
1487         u64 tx_lpi_count;               /* etlpic */
1488         u64 rx_lpi_count;               /* erlpic */
1489 };
1490
1491 /* Checksum and Shadow RAM pointers */
1492 #define I40E_SR_NVM_CONTROL_WORD                0x00
1493 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1494 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1495 #define I40E_SR_OPTION_ROM_PTR                  0x05
1496 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1497 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1498 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1499 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1500 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1501 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1502 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1503 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1504 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1505 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1506 #define I40E_SR_PBA_FLAGS                       0x15
1507 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1508 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1509 #define I40E_NVM_OEM_VER_OFF                    0x83
1510 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1511 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1512 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1513 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1514 #define I40E_SR_NVM_MAP_VERSION                 0x29
1515 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1516 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1517 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1518 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1519 #define I40E_SR_VPD_PTR                         0x2F
1520 #define I40E_SR_PXE_SETUP_PTR                   0x30
1521 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1522 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1523 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1524 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1525 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1526 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1527 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1528 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1529 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1530 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1531 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1532 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1533 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1534 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1535 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1536 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1537 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1538 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1539
1540 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1541 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1542 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1543 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1544 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1545
1546 /* Shadow RAM related */
1547 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1548 #define I40E_SR_BUF_ALIGNMENT           4096
1549 #define I40E_SR_WORDS_IN_1KB            512
1550 /* Checksum should be calculated such that after adding all the words,
1551  * including the checksum word itself, the sum should be 0xBABA.
1552  */
1553 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1554
1555 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1556
1557 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1558
1559 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1560         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1561         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1562         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1563         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1564         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1565         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1566         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1567         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1568         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1569         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1570         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1571         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1572         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1573 };
1574
1575 /* FCoE DIF/DIX Context descriptor */
1576 struct i40e_fcoe_difdix_context_desc {
1577         __le64 flags_buff0_buff1_ref;
1578         __le64 difapp_msk_bias;
1579 };
1580
1581 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1582 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1583                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1584
1585 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1586         /* 2 BITS */
1587         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1588         /* 1 BIT  */
1589         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1590         /* 1 BIT  */
1591         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1592         /* 2 BITS */
1593         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1594         /* 2 BITS */
1595         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1596         /* 2 BITS */
1597         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1598         /* 2 BITS */
1599         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1600         /* 2 BITS */
1601         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1602         /* 2 BITS */
1603         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1604         /* 2 BITS */
1605         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1606         /* 2 BITS */
1607         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1608         /* 1 BIT  */
1609         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1610         /* 1 BIT  */
1611         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1612         /* 2 BITS */
1613         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1614         /* 2 BITS */
1615         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1616         /* 2 BITS */
1617         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1618         /* 2 BITS */
1619         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1620         /* 1 BIT  */
1621         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1622         /* 1 BIT  */
1623         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1624         /* 1 BIT */
1625         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1626         /* 1 BIT */
1627         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1628 };
1629
1630 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1631 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1632                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1633
1634 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1635 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1636                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1637
1638 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1639 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1640                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1641
1642 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1643 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1644                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1645
1646 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1647 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1648                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1649
1650 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1651 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1652                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1653
1654 /* FCoE DIF/DIX Buffers descriptor */
1655 struct i40e_fcoe_difdix_buffers_desc {
1656         __le64 buff_addr0;
1657         __le64 buff_addr1;
1658 };
1659
1660 /* FCoE DDP Context descriptor */
1661 struct i40e_fcoe_ddp_context_desc {
1662         __le64 rsvd;
1663         __le64 type_cmd_foff_lsize;
1664 };
1665
1666 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1667 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1668                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1669
1670 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1671 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1672                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1673
1674 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1675         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1676         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1677         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1678         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1679         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1680         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1681 };
1682
1683 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1684 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1685                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1686
1687 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1688 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1689                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1690
1691 /* FCoE DDP/DWO Queue Context descriptor */
1692 struct i40e_fcoe_queue_context_desc {
1693         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1694         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1695 };
1696
1697 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1698 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1699                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1700
1701 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1702 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1703                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1704
1705 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1706 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1707                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1708
1709 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1710 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1711                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1712
1713 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1714         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1715         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1716 };
1717
1718 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1719 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1720                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1721
1722 /* FCoE DDP/DWO Filter Context descriptor */
1723 struct i40e_fcoe_filter_context_desc {
1724         __le32 param;
1725         __le16 seqn;
1726
1727         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1728         __le16 rsvd_dmaindx;
1729
1730         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1731         __le64 flags_rsvd_lanq;
1732 };
1733
1734 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1735 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1736                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1737
1738 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1739         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1740         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1741         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1742         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1743         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1744         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1745 };
1746
1747 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1748 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1749                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1750
1751 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1752 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1753                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1754
1755 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1756 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1757                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1758
1759 enum i40e_switch_element_types {
1760         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1761         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1762         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1763         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1764         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1765         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1766         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1767         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1768         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1769 };
1770
1771 /* Supported EtherType filters */
1772 enum i40e_ether_type_index {
1773         I40E_ETHER_TYPE_1588            = 0,
1774         I40E_ETHER_TYPE_FIP             = 1,
1775         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1776         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1777         I40E_ETHER_TYPE_LLDP            = 4,
1778         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1779         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1780         I40E_ETHER_TYPE_QCN_CNM         = 7,
1781         I40E_ETHER_TYPE_8021X           = 8,
1782         I40E_ETHER_TYPE_ARP             = 9,
1783         I40E_ETHER_TYPE_RSV1            = 10,
1784         I40E_ETHER_TYPE_RSV2            = 11,
1785 };
1786
1787 /* Filter context base size is 1K */
1788 #define I40E_HASH_FILTER_BASE_SIZE      1024
1789 /* Supported Hash filter values */
1790 enum i40e_hash_filter_size {
1791         I40E_HASH_FILTER_SIZE_1K        = 0,
1792         I40E_HASH_FILTER_SIZE_2K        = 1,
1793         I40E_HASH_FILTER_SIZE_4K        = 2,
1794         I40E_HASH_FILTER_SIZE_8K        = 3,
1795         I40E_HASH_FILTER_SIZE_16K       = 4,
1796         I40E_HASH_FILTER_SIZE_32K       = 5,
1797         I40E_HASH_FILTER_SIZE_64K       = 6,
1798         I40E_HASH_FILTER_SIZE_128K      = 7,
1799         I40E_HASH_FILTER_SIZE_256K      = 8,
1800         I40E_HASH_FILTER_SIZE_512K      = 9,
1801         I40E_HASH_FILTER_SIZE_1M        = 10,
1802 };
1803
1804 /* DMA context base size is 0.5K */
1805 #define I40E_DMA_CNTX_BASE_SIZE         512
1806 /* Supported DMA context values */
1807 enum i40e_dma_cntx_size {
1808         I40E_DMA_CNTX_SIZE_512          = 0,
1809         I40E_DMA_CNTX_SIZE_1K           = 1,
1810         I40E_DMA_CNTX_SIZE_2K           = 2,
1811         I40E_DMA_CNTX_SIZE_4K           = 3,
1812         I40E_DMA_CNTX_SIZE_8K           = 4,
1813         I40E_DMA_CNTX_SIZE_16K          = 5,
1814         I40E_DMA_CNTX_SIZE_32K          = 6,
1815         I40E_DMA_CNTX_SIZE_64K          = 7,
1816         I40E_DMA_CNTX_SIZE_128K         = 8,
1817         I40E_DMA_CNTX_SIZE_256K         = 9,
1818 };
1819
1820 /* Supported Hash look up table (LUT) sizes */
1821 enum i40e_hash_lut_size {
1822         I40E_HASH_LUT_SIZE_128          = 0,
1823         I40E_HASH_LUT_SIZE_512          = 1,
1824 };
1825
1826 /* Structure to hold a per PF filter control settings */
1827 struct i40e_filter_control_settings {
1828         /* number of PE Quad Hash filter buckets */
1829         enum i40e_hash_filter_size pe_filt_num;
1830         /* number of PE Quad Hash contexts */
1831         enum i40e_dma_cntx_size pe_cntx_num;
1832         /* number of FCoE filter buckets */
1833         enum i40e_hash_filter_size fcoe_filt_num;
1834         /* number of FCoE DDP contexts */
1835         enum i40e_dma_cntx_size fcoe_cntx_num;
1836         /* size of the Hash LUT */
1837         enum i40e_hash_lut_size hash_lut_size;
1838         /* enable FDIR filters for PF and its VFs */
1839         bool enable_fdir;
1840         /* enable Ethertype filters for PF and its VFs */
1841         bool enable_ethtype;
1842         /* enable MAC/VLAN filters for PF and its VFs */
1843         bool enable_macvlan;
1844 };
1845
1846 /* Structure to hold device level control filter counts */
1847 struct i40e_control_filter_stats {
1848         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1849         u16 etype_used;       /* Used perfect EtherType filters */
1850         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1851         u16 etype_free;       /* Un-used perfect EtherType filters */
1852 };
1853
1854 enum i40e_reset_type {
1855         I40E_RESET_POR          = 0,
1856         I40E_RESET_CORER        = 1,
1857         I40E_RESET_GLOBR        = 2,
1858         I40E_RESET_EMPR         = 3,
1859 };
1860
1861 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1862 #define I40E_NVM_LLDP_CFG_PTR           0xD
1863 struct i40e_lldp_variables {
1864         u16 length;
1865         u16 adminstatus;
1866         u16 msgfasttx;
1867         u16 msgtxinterval;
1868         u16 txparams;
1869         u16 timers;
1870         u16 crc8;
1871 };
1872
1873 /* Offsets into Alternate Ram */
1874 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1875 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1876 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1877 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1878 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1879 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1880
1881 /* Alternate Ram Bandwidth Masks */
1882 #define I40E_ALT_BW_VALUE_MASK          0xFF
1883 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1884 #define I40E_ALT_BW_VALID_MASK          0x80000000
1885
1886 /* RSS Hash Table Size */
1887 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1888
1889 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1890 #define I40E_L3_SRC_SHIFT               47
1891 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1892 #define I40E_L3_V6_SRC_SHIFT            43
1893 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1894 #define I40E_L3_DST_SHIFT               35
1895 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1896 #define I40E_L3_V6_DST_SHIFT            35
1897 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1898 #define I40E_L4_SRC_SHIFT               34
1899 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1900 #define I40E_L4_DST_SHIFT               33
1901 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1902 #define I40E_VERIFY_TAG_SHIFT           31
1903 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1904
1905 #define I40E_FLEX_50_SHIFT              13
1906 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1907 #define I40E_FLEX_51_SHIFT              12
1908 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1909 #define I40E_FLEX_52_SHIFT              11
1910 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1911 #define I40E_FLEX_53_SHIFT              10
1912 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1913 #define I40E_FLEX_54_SHIFT              9
1914 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1915 #define I40E_FLEX_55_SHIFT              8
1916 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1917 #define I40E_FLEX_56_SHIFT              7
1918 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1919 #define I40E_FLEX_57_SHIFT              6
1920 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1921 #endif /* _I40E_TYPE_H_ */