drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_STCODE                0
 161 #define I40E_MDIO_OPCODE_ADDRESS        0
 162 #define I40E_MDIO_OPCODE_WRITE          I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_OPCODE_READ_INC_ADDR  I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166 #define I40E_MDIO_OPCODE_READ           I40E_MASK(3, \
 167                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 168
 169 #define I40E_PHY_COM_REG_PAGE                   0x1E
 170 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 171 #define I40E_PHY_LED_MANUAL_ON                  0x100
 172 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 173 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 174 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 175
 176 /* Memory types */
 177 enum i40e_memset_type {
 178         I40E_NONDMA_MEM = 0,
 179         I40E_DMA_MEM
 180 };
 181
 182 /* Memcpy types */
 183 enum i40e_memcpy_type {
 184         I40E_NONDMA_TO_NONDMA = 0,
 185         I40E_NONDMA_TO_DMA,
 186         I40E_DMA_TO_DMA,
 187         I40E_DMA_TO_NONDMA
 188 };
 189
 190 #ifdef X722_SUPPORT
 191 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 192 #endif
 193 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 194
 195
 196 /* These are structs for managing the hardware information and the operations.
 197  * The structures of function pointers are filled out at init time when we
 198  * know for sure exactly which hardware we're working with.  This gives us the
 199  * flexibility of using the same main driver code but adapting to slightly
 200  * different hardware needs as new parts are developed.  For this architecture,
 201  * the Firmware and AdminQ are intended to insulate the driver from most of the
 202  * future changes, but these structures will also do part of the job.
 203  */
 204 enum i40e_mac_type {
 205         I40E_MAC_UNKNOWN = 0,
 206         I40E_MAC_X710,
 207         I40E_MAC_XL710,
 208         I40E_MAC_VF,
 209 #ifdef X722_SUPPORT
 210         I40E_MAC_X722,
 211         I40E_MAC_X722_VF,
 212 #endif
 213         I40E_MAC_GENERIC,
 214 };
 215
 216 enum i40e_media_type {
 217         I40E_MEDIA_TYPE_UNKNOWN = 0,
 218         I40E_MEDIA_TYPE_FIBER,
 219         I40E_MEDIA_TYPE_BASET,
 220         I40E_MEDIA_TYPE_BACKPLANE,
 221         I40E_MEDIA_TYPE_CX4,
 222         I40E_MEDIA_TYPE_DA,
 223         I40E_MEDIA_TYPE_VIRTUAL
 224 };
 225
 226 enum i40e_fc_mode {
 227         I40E_FC_NONE = 0,
 228         I40E_FC_RX_PAUSE,
 229         I40E_FC_TX_PAUSE,
 230         I40E_FC_FULL,
 231         I40E_FC_PFC,
 232         I40E_FC_DEFAULT
 233 };
 234
 235 enum i40e_set_fc_aq_failures {
 236         I40E_SET_FC_AQ_FAIL_NONE = 0,
 237         I40E_SET_FC_AQ_FAIL_GET = 1,
 238         I40E_SET_FC_AQ_FAIL_SET = 2,
 239         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 240         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 241 };
 242
 243 enum i40e_vsi_type {
 244         I40E_VSI_MAIN   = 0,
 245         I40E_VSI_VMDQ1  = 1,
 246         I40E_VSI_VMDQ2  = 2,
 247         I40E_VSI_CTRL   = 3,
 248         I40E_VSI_FCOE   = 4,
 249         I40E_VSI_MIRROR = 5,
 250         I40E_VSI_SRIOV  = 6,
 251         I40E_VSI_FDIR   = 7,
 252         I40E_VSI_TYPE_UNKNOWN
 253 };
 254
 255 enum i40e_queue_type {
 256         I40E_QUEUE_TYPE_RX = 0,
 257         I40E_QUEUE_TYPE_TX,
 258         I40E_QUEUE_TYPE_PE_CEQ,
 259         I40E_QUEUE_TYPE_UNKNOWN
 260 };
 261
 262 struct i40e_link_status {
 263         enum i40e_aq_phy_type phy_type;
 264         enum i40e_aq_link_speed link_speed;
 265         u8 link_info;
 266         u8 an_info;
 267         u8 ext_info;
 268         u8 loopback;
 269         /* is Link Status Event notification to SW enabled */
 270         bool lse_enable;
 271         u16 max_frame_size;
 272         bool crc_enable;
 273         u8 pacing;
 274         u8 requested_speeds;
 275         u8 module_type[3];
 276         /* 1st byte: module identifier */
 277 #define I40E_MODULE_TYPE_SFP            0x03
 278 #define I40E_MODULE_TYPE_QSFP           0x0D
 279         /* 2nd byte: ethernet compliance codes for 10/40G */
 280 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 281 #define I40E_MODULE_TYPE_40G_LR4        0x02
 282 #define I40E_MODULE_TYPE_40G_SR4        0x04
 283 #define I40E_MODULE_TYPE_40G_CR4        0x08
 284 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 285 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 286 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 287 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 288         /* 3rd byte: ethernet compliance codes for 1G */
 289 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 290 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 291 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 292 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 293 };
 294
 295 struct i40e_phy_info {
 296         struct i40e_link_status link_info;
 297         struct i40e_link_status link_info_old;
 298         bool get_link_info;
 299         enum i40e_media_type media_type;
 300         /* all the phy types the NVM is capable of */
 301         u32 phy_types;
 302 };
 303
 304 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 305 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 306 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 307 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 308 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 309 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 310 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 311 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 312 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 313 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 314 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 317 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 318 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 319 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 320 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 321 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 322 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 323 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 325 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 326 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 327 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 328 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 329 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 330 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 331                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 332 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 333 #define I40E_HW_CAP_MAX_GPIO                    30
 334 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 335 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 336
 337 #ifdef X722_SUPPORT
 338 enum i40e_acpi_programming_method {
 339         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 340         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 341 };
 342
 343 #define I40E_WOL_SUPPORT_MASK                   1
 344 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 345 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 346
 347 #endif
 348 /* Capabilities of a PF or a VF or the whole device */
 349 struct i40e_hw_capabilities {
 350         u32  switch_mode;
 351 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 352 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 353 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 354
 355         u32  management_mode;
 356         u32  npar_enable;
 357         u32  os2bmc;
 358         u32  valid_functions;
 359         bool sr_iov_1_1;
 360         bool vmdq;
 361         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 362         bool evb_802_1_qbh; /* Bridge Port Extension */
 363         bool dcb;
 364         bool fcoe;
 365         bool iscsi; /* Indicates iSCSI enabled */
 366         bool flex10_enable;
 367         bool flex10_capable;
 368         u32  flex10_mode;
 369 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 370 #define I40E_FLEX10_MODE_DCC            0x1
 371 #define I40E_FLEX10_MODE_DCI            0x2
 372
 373         u32 flex10_status;
 374 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 375 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 376
 377         bool sec_rev_disabled;
 378         bool update_disabled;
 379 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 380 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 381
 382         bool mgmt_cem;
 383         bool ieee_1588;
 384         bool iwarp;
 385         bool fd;
 386         u32 fd_filters_guaranteed;
 387         u32 fd_filters_best_effort;
 388         bool rss;
 389         u32 rss_table_size;
 390         u32 rss_table_entry_width;
 391         bool led[I40E_HW_CAP_MAX_GPIO];
 392         bool sdp[I40E_HW_CAP_MAX_GPIO];
 393         u32 nvm_image_type;
 394         u32 num_flow_director_filters;
 395         u32 num_vfs;
 396         u32 vf_base_id;
 397         u32 num_vsis;
 398         u32 num_rx_qp;
 399         u32 num_tx_qp;
 400         u32 base_queue;
 401         u32 num_msix_vectors;
 402         u32 num_msix_vectors_vf;
 403         u32 led_pin_num;
 404         u32 sdp_pin_num;
 405         u32 mdio_port_num;
 406         u32 mdio_port_mode;
 407         u8 rx_buf_chain_len;
 408         u32 enabled_tcmap;
 409         u32 maxtc;
 410         u64 wr_csr_prot;
 411 #ifdef X722_SUPPORT
 412         bool apm_wol_support;
 413         enum i40e_acpi_programming_method acpi_prog_method;
 414         bool proxy_support;
 415 #endif
 416 };
 417
 418 struct i40e_mac_info {
 419         enum i40e_mac_type type;
 420         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 421         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 422         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 423         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 424         u16 max_fcoeq;
 425 };
 426
 427 enum i40e_aq_resources_ids {
 428         I40E_NVM_RESOURCE_ID = 1
 429 };
 430
 431 enum i40e_aq_resource_access_type {
 432         I40E_RESOURCE_READ = 1,
 433         I40E_RESOURCE_WRITE
 434 };
 435
 436 struct i40e_nvm_info {
 437         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 438         u32 timeout;              /* [ms] */
 439         u16 sr_size;              /* Shadow RAM size in words */
 440         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 441         u16 version;              /* NVM package version */
 442         u32 eetrack;              /* NVM data version */
 443         u32 oem_ver;              /* OEM version info */
 444 };
 445
 446 /* definitions used in NVM update support */
 447
 448 enum i40e_nvmupd_cmd {
 449         I40E_NVMUPD_INVALID,
 450         I40E_NVMUPD_READ_CON,
 451         I40E_NVMUPD_READ_SNT,
 452         I40E_NVMUPD_READ_LCB,
 453         I40E_NVMUPD_READ_SA,
 454         I40E_NVMUPD_WRITE_ERA,
 455         I40E_NVMUPD_WRITE_CON,
 456         I40E_NVMUPD_WRITE_SNT,
 457         I40E_NVMUPD_WRITE_LCB,
 458         I40E_NVMUPD_WRITE_SA,
 459         I40E_NVMUPD_CSUM_CON,
 460         I40E_NVMUPD_CSUM_SA,
 461         I40E_NVMUPD_CSUM_LCB,
 462         I40E_NVMUPD_STATUS,
 463         I40E_NVMUPD_EXEC_AQ,
 464         I40E_NVMUPD_GET_AQ_RESULT,
 465 };
 466
 467 enum i40e_nvmupd_state {
 468         I40E_NVMUPD_STATE_INIT,
 469         I40E_NVMUPD_STATE_READING,
 470         I40E_NVMUPD_STATE_WRITING,
 471         I40E_NVMUPD_STATE_INIT_WAIT,
 472         I40E_NVMUPD_STATE_WRITE_WAIT,
 473 };
 474
 475 /* nvm_access definition and its masks/shifts need to be accessible to
 476  * application, core driver, and shared code.  Where is the right file?
 477  */
 478 #define I40E_NVM_READ   0xB
 479 #define I40E_NVM_WRITE  0xC
 480
 481 #define I40E_NVM_MOD_PNT_MASK 0xFF
 482
 483 #define I40E_NVM_TRANS_SHIFT    8
 484 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 485 #define I40E_NVM_CON            0x0
 486 #define I40E_NVM_SNT            0x1
 487 #define I40E_NVM_LCB            0x2
 488 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 489 #define I40E_NVM_ERA            0x4
 490 #define I40E_NVM_CSUM           0x8
 491 #define I40E_NVM_EXEC           0xf
 492
 493 #define I40E_NVM_ADAPT_SHIFT    16
 494 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 495
 496 #define I40E_NVMUPD_MAX_DATA    4096
 497 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 498
 499 struct i40e_nvm_access {
 500         u32 command;
 501         u32 config;
 502         u32 offset;     /* in bytes */
 503         u32 data_size;  /* in bytes */
 504         u8 data[1];
 505 };
 506
 507 /* PCI bus types */
 508 enum i40e_bus_type {
 509         i40e_bus_type_unknown = 0,
 510         i40e_bus_type_pci,
 511         i40e_bus_type_pcix,
 512         i40e_bus_type_pci_express,
 513         i40e_bus_type_reserved
 514 };
 515
 516 /* PCI bus speeds */
 517 enum i40e_bus_speed {
 518         i40e_bus_speed_unknown  = 0,
 519         i40e_bus_speed_33       = 33,
 520         i40e_bus_speed_66       = 66,
 521         i40e_bus_speed_100      = 100,
 522         i40e_bus_speed_120      = 120,
 523         i40e_bus_speed_133      = 133,
 524         i40e_bus_speed_2500     = 2500,
 525         i40e_bus_speed_5000     = 5000,
 526         i40e_bus_speed_8000     = 8000,
 527         i40e_bus_speed_reserved
 528 };
 529
 530 /* PCI bus widths */
 531 enum i40e_bus_width {
 532         i40e_bus_width_unknown  = 0,
 533         i40e_bus_width_pcie_x1  = 1,
 534         i40e_bus_width_pcie_x2  = 2,
 535         i40e_bus_width_pcie_x4  = 4,
 536         i40e_bus_width_pcie_x8  = 8,
 537         i40e_bus_width_32       = 32,
 538         i40e_bus_width_64       = 64,
 539         i40e_bus_width_reserved
 540 };
 541
 542 /* Bus parameters */
 543 struct i40e_bus_info {
 544         enum i40e_bus_speed speed;
 545         enum i40e_bus_width width;
 546         enum i40e_bus_type type;
 547
 548         u16 func;
 549         u16 device;
 550         u16 lan_id;
 551 };
 552
 553 /* Flow control (FC) parameters */
 554 struct i40e_fc_info {
 555         enum i40e_fc_mode current_mode; /* FC mode in effect */
 556         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 557 };
 558
 559 #define I40E_MAX_TRAFFIC_CLASS          8
 560 #define I40E_MAX_USER_PRIORITY          8
 561 #define I40E_DCBX_MAX_APPS              32
 562 #define I40E_LLDPDU_SIZE                1500
 563 #define I40E_TLV_STATUS_OPER            0x1
 564 #define I40E_TLV_STATUS_SYNC            0x2
 565 #define I40E_TLV_STATUS_ERR             0x4
 566 #define I40E_CEE_OPER_MAX_APPS          3
 567 #define I40E_APP_PROTOID_FCOE           0x8906
 568 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 569 #define I40E_APP_PROTOID_FIP            0x8914
 570 #define I40E_APP_SEL_ETHTYPE            0x1
 571 #define I40E_APP_SEL_TCPIP              0x2
 572 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 573 #define I40E_CEE_APP_SEL_TCPIP          0x1
 574
 575 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 576 struct i40e_dcb_ets_config {
 577         u8 willing;
 578         u8 cbs;
 579         u8 maxtcs;
 580         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 581         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 582         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 583 };
 584
 585 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 586 struct i40e_dcb_pfc_config {
 587         u8 willing;
 588         u8 mbc;
 589         u8 pfccap;
 590         u8 pfcenable;
 591 };
 592
 593 /* CEE or IEEE 802.1Qaz Application Priority data */
 594 struct i40e_dcb_app_priority_table {
 595         u8  priority;
 596         u8  selector;
 597         u16 protocolid;
 598 };
 599
 600 struct i40e_dcbx_config {
 601         u8  dcbx_mode;
 602 #define I40E_DCBX_MODE_CEE      0x1
 603 #define I40E_DCBX_MODE_IEEE     0x2
 604         u8  app_mode;
 605 #define I40E_DCBX_APPS_NON_WILLING      0x1
 606         u32 numapps;
 607         u32 tlv_status; /* CEE mode TLV status */
 608         struct i40e_dcb_ets_config etscfg;
 609         struct i40e_dcb_ets_config etsrec;
 610         struct i40e_dcb_pfc_config pfc;
 611         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 612 };
 613
 614 /* Port hardware description */
 615 struct i40e_hw {
 616         u8 *hw_addr;
 617         void *back;
 618
 619         /* subsystem structs */
 620         struct i40e_phy_info phy;
 621         struct i40e_mac_info mac;
 622         struct i40e_bus_info bus;
 623         struct i40e_nvm_info nvm;
 624         struct i40e_fc_info fc;
 625
 626         /* pci info */
 627         u16 device_id;
 628         u16 vendor_id;
 629         u16 subsystem_device_id;
 630         u16 subsystem_vendor_id;
 631         u8 revision_id;
 632         u8 port;
 633         bool adapter_stopped;
 634
 635         /* capabilities for entire device and PCI func */
 636         struct i40e_hw_capabilities dev_caps;
 637         struct i40e_hw_capabilities func_caps;
 638
 639         /* Flow Director shared filter space */
 640         u16 fdir_shared_filter_count;
 641
 642         /* device profile info */
 643         u8  pf_id;
 644         u16 main_vsi_seid;
 645
 646         /* for multi-function MACs */
 647         u16 partition_id;
 648         u16 num_partitions;
 649         u16 num_ports;
 650
 651         /* Closest numa node to the device */
 652         u16 numa_node;
 653
 654         /* Admin Queue info */
 655         struct i40e_adminq_info aq;
 656
 657         /* state of nvm update process */
 658         enum i40e_nvmupd_state nvmupd_state;
 659         struct i40e_aq_desc nvm_wb_desc;
 660         struct i40e_virt_mem nvm_buff;
 661         bool nvm_release_on_done;
 662         u16 nvm_wait_opcode;
 663
 664         /* HMC info */
 665         struct i40e_hmc_info hmc; /* HMC info struct */
 666
 667         /* LLDP/DCBX Status */
 668         u16 dcbx_status;
 669
 670         /* DCBX info */
 671         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 672         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 673         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 674
 675 #ifdef X722_SUPPORT
 676         /* WoL and proxy support */
 677         u16 num_wol_proxy_filters;
 678         u16 wol_proxy_vsi_seid;
 679
 680 #endif
 681 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 682         u64 flags;
 683
 684         /* debug mask */
 685         u32 debug_mask;
 686 #ifndef I40E_NDIS_SUPPORT
 687         char err_str[16];
 688 #endif /* I40E_NDIS_SUPPORT */
 689 };
 690
 691 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 692 {
 693 #ifdef X722_SUPPORT
 694         return (hw->mac.type == I40E_MAC_VF ||
 695                 hw->mac.type == I40E_MAC_X722_VF);
 696 #else
 697         return hw->mac.type == I40E_MAC_VF;
 698 #endif
 699 }
 700
 701 struct i40e_driver_version {
 702         u8 major_version;
 703         u8 minor_version;
 704         u8 build_version;
 705         u8 subbuild_version;
 706         u8 driver_string[32];
 707 };
 708
 709 /* RX Descriptors */
 710 union i40e_16byte_rx_desc {
 711         struct {
 712                 __le64 pkt_addr; /* Packet buffer address */
 713                 __le64 hdr_addr; /* Header buffer address */
 714         } read;
 715         struct {
 716                 struct {
 717                         struct {
 718                                 union {
 719                                         __le16 mirroring_status;
 720                                         __le16 fcoe_ctx_id;
 721                                 } mirr_fcoe;
 722                                 __le16 l2tag1;
 723                         } lo_dword;
 724                         union {
 725                                 __le32 rss; /* RSS Hash */
 726                                 __le32 fd_id; /* Flow director filter id */
 727                                 __le32 fcoe_param; /* FCoE DDP Context id */
 728                         } hi_dword;
 729                 } qword0;
 730                 struct {
 731                         /* ext status/error/pktype/length */
 732                         __le64 status_error_len;
 733                 } qword1;
 734         } wb;  /* writeback */
 735 };
 736
 737 union i40e_32byte_rx_desc {
 738         struct {
 739                 __le64  pkt_addr; /* Packet buffer address */
 740                 __le64  hdr_addr; /* Header buffer address */
 741                         /* bit 0 of hdr_buffer_addr is DD bit */
 742                 __le64  rsvd1;
 743                 __le64  rsvd2;
 744         } read;
 745         struct {
 746                 struct {
 747                         struct {
 748                                 union {
 749                                         __le16 mirroring_status;
 750                                         __le16 fcoe_ctx_id;
 751                                 } mirr_fcoe;
 752                                 __le16 l2tag1;
 753                         } lo_dword;
 754                         union {
 755                                 __le32 rss; /* RSS Hash */
 756                                 __le32 fcoe_param; /* FCoE DDP Context id */
 757                                 /* Flow director filter id in case of
 758                                  * Programming status desc WB
 759                                  */
 760                                 __le32 fd_id;
 761                         } hi_dword;
 762                 } qword0;
 763                 struct {
 764                         /* status/error/pktype/length */
 765                         __le64 status_error_len;
 766                 } qword1;
 767                 struct {
 768                         __le16 ext_status; /* extended status */
 769                         __le16 rsvd;
 770                         __le16 l2tag2_1;
 771                         __le16 l2tag2_2;
 772                 } qword2;
 773                 struct {
 774                         union {
 775                                 __le32 flex_bytes_lo;
 776                                 __le32 pe_status;
 777                         } lo_dword;
 778                         union {
 779                                 __le32 flex_bytes_hi;
 780                                 __le32 fd_id;
 781                         } hi_dword;
 782                 } qword3;
 783         } wb;  /* writeback */
 784 };
 785
 786 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 787 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 788                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 789 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 790 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 791                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 792
 793 enum i40e_rx_desc_status_bits {
 794         /* Note: These are predefined bit offsets */
 795         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 796         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 797         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 798         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 799         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 800         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 801         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 802 #ifdef X722_SUPPORT
 803         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 804 #else
 805         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 806 #endif
 807
 808         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 809         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 810         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 811         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 812         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 813         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 814 #ifdef X722_SUPPORT
 815         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 816 #else
 817         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 818 #endif
 819         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 820 };
 821
 822 #define I40E_RXD_QW1_STATUS_SHIFT       0
 823 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 824                                          I40E_RXD_QW1_STATUS_SHIFT)
 825
 826 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 827 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 828                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 829
 830 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 831 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 832
 833 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 834 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 835                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 836
 837 enum i40e_rx_desc_fltstat_values {
 838         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 839         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 840         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 841         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 842 };
 843
 844 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 845 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 846 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 847 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 848
 849 #define I40E_RXD_QW1_ERROR_SHIFT        19
 850 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 851
 852 enum i40e_rx_desc_error_bits {
 853         /* Note: These are predefined bit offsets */
 854         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 855         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 856         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 857         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 858         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 859         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 860         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 861         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 862         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 863 };
 864
 865 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 866         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 867         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 868         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 869         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 870         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 871 };
 872
 873 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 874 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 875
 876 /* Packet type non-ip values */
 877 enum i40e_rx_l2_ptype {
 878         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 879         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 880         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 881         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 882         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 883         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 884         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 885         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 886         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 887         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 888         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 889         I40E_RX_PTYPE_L2_ARP                            = 11,
 890         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 891         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 892         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 893         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 894         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 895         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 896         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 897         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 898         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 899         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 900         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 901         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 902         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 903         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 904 };
 905
 906 struct i40e_rx_ptype_decoded {
 907         u32 ptype:8;
 908         u32 known:1;
 909         u32 outer_ip:1;
 910         u32 outer_ip_ver:1;
 911         u32 outer_frag:1;
 912         u32 tunnel_type:3;
 913         u32 tunnel_end_prot:2;
 914         u32 tunnel_end_frag:1;
 915         u32 inner_prot:4;
 916         u32 payload_layer:3;
 917 };
 918
 919 enum i40e_rx_ptype_outer_ip {
 920         I40E_RX_PTYPE_OUTER_L2  = 0,
 921         I40E_RX_PTYPE_OUTER_IP  = 1
 922 };
 923
 924 enum i40e_rx_ptype_outer_ip_ver {
 925         I40E_RX_PTYPE_OUTER_NONE        = 0,
 926         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 927         I40E_RX_PTYPE_OUTER_IPV6        = 1
 928 };
 929
 930 enum i40e_rx_ptype_outer_fragmented {
 931         I40E_RX_PTYPE_NOT_FRAG  = 0,
 932         I40E_RX_PTYPE_FRAG      = 1
 933 };
 934
 935 enum i40e_rx_ptype_tunnel_type {
 936         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 937         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 938         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 939         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 940         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 941 };
 942
 943 enum i40e_rx_ptype_tunnel_end_prot {
 944         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 945         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 946         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 947 };
 948
 949 enum i40e_rx_ptype_inner_prot {
 950         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 951         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 952         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 953         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 954         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 955         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 956 };
 957
 958 enum i40e_rx_ptype_payload_layer {
 959         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 960         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 961         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 962         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 963 };
 964
 965 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 966 #define I40E_RX_PTYPE_SHIFT             56
 967
 968 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 969 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 970                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 971
 972 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 973 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 974                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 975
 976 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 977 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 978
 979 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 980 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 981
 982 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 983 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 984                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 985
 986 enum i40e_rx_desc_ext_status_bits {
 987         /* Note: These are predefined bit offsets */
 988         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 989         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 990         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 991         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 992         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 993         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 994         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 995 };
 996
 997 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 998 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 999
1000 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1001 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1002
1003 enum i40e_rx_desc_pe_status_bits {
1004         /* Note: These are predefined bit offsets */
1005         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1006         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1007         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1008         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1009         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1010         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1011         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1012         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1013         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1014 };
1015
1016 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1017 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1018
1019 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1020 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1021                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1022
1023 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1024 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1025                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1026
1027 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1028 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1029                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1030
1031 enum i40e_rx_prog_status_desc_status_bits {
1032         /* Note: These are predefined bit offsets */
1033         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1034         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1035 };
1036
1037 enum i40e_rx_prog_status_desc_prog_id_masks {
1038         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1039         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1040         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1041 };
1042
1043 enum i40e_rx_prog_status_desc_error_bits {
1044         /* Note: These are predefined bit offsets */
1045         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1046         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1047         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1048         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1049 };
1050
1051 #define I40E_TWO_BIT_MASK       0x3
1052 #define I40E_THREE_BIT_MASK     0x7
1053 #define I40E_FOUR_BIT_MASK      0xF
1054 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1055
1056 /* TX Descriptor */
1057 struct i40e_tx_desc {
1058         __le64 buffer_addr; /* Address of descriptor's data buf */
1059         __le64 cmd_type_offset_bsz;
1060 };
1061
1062 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1063 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1064
1065 enum i40e_tx_desc_dtype_value {
1066         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1067         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1068         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1069         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1070         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1071         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1072         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1073         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1074         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1075         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1076 };
1077
1078 #define I40E_TXD_QW1_CMD_SHIFT  4
1079 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1080
1081 enum i40e_tx_desc_cmd_bits {
1082         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1083         I40E_TX_DESC_CMD_RS                     = 0x0002,
1084         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1085         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1086         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1087         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1088         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1089         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1090         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1091         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1092         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1093         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1094         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1095         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1096         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1097         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1098         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1099         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1100 };
1101
1102 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1103 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1104                                          I40E_TXD_QW1_OFFSET_SHIFT)
1105
1106 enum i40e_tx_desc_length_fields {
1107         /* Note: These are predefined bit offsets */
1108         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1109         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1110         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1111 };
1112
1113 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1114 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1115 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1116 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1117
1118 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1119 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1120                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1121
1122 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1123 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1124
1125 /* Context descriptors */
1126 struct i40e_tx_context_desc {
1127         __le32 tunneling_params;
1128         __le16 l2tag2;
1129         __le16 rsvd;
1130         __le64 type_cmd_tso_mss;
1131 };
1132
1133 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1134 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1135
1136 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1137 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1138
1139 enum i40e_tx_ctx_desc_cmd_bits {
1140         I40E_TX_CTX_DESC_TSO            = 0x01,
1141         I40E_TX_CTX_DESC_TSYN           = 0x02,
1142         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1143         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1144         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1145         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1146         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1147         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1148         I40E_TX_CTX_DESC_SWPE           = 0x40
1149 };
1150
1151 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1152 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1153                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1154
1155 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1156 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1157                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1158
1159 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1160 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1161
1162 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1163 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1164                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1165
1166 enum i40e_tx_ctx_desc_eipt_offload {
1167         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1168         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1169         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1170         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1171 };
1172
1173 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1174 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1175                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1176
1177 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1178 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1179
1180 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1181 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1182
1183 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1184 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1185
1186 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1187
1188 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1189 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1190                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1191
1192 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1193 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1194                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1195
1196 #ifdef X722_SUPPORT
1197 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1198 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1199 #endif
1200 struct i40e_nop_desc {
1201         __le64 rsvd;
1202         __le64 dtype_cmd;
1203 };
1204
1205 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1206 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1207
1208 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1209 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1210
1211 enum i40e_tx_nop_desc_cmd_bits {
1212         /* Note: These are predefined bit offsets */
1213         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1214         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1215         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1216 };
1217
1218 struct i40e_filter_program_desc {
1219         __le32 qindex_flex_ptype_vsi;
1220         __le32 rsvd;
1221         __le32 dtype_cmd_cntindex;
1222         __le32 fd_id;
1223 };
1224 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1225 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1226                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1227 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1228 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1229                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1230 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1231 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1232                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1233
1234 /* Packet Classifier Types for filters */
1235 enum i40e_filter_pctype {
1236 #ifdef X722_SUPPORT
1237         /* Note: Values 0-28 are reserved for future use.
1238          * Value 29, 30, 32 are not supported on XL710 and X710.
1239          */
1240         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1241         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1242 #else
1243         /* Note: Values 0-30 are reserved for future use */
1244 #endif
1245         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1246 #ifdef X722_SUPPORT
1247         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1248 #else
1249         /* Note: Value 32 is reserved for future use */
1250 #endif
1251         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1252         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1253         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1254         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1255 #ifdef X722_SUPPORT
1256         /* Note: Values 37-38 are reserved for future use.
1257          * Value 39, 40, 42 are not supported on XL710 and X710.
1258          */
1259         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1260         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1261 #else
1262         /* Note: Values 37-40 are reserved for future use */
1263 #endif
1264         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1265 #ifdef X722_SUPPORT
1266         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1267 #endif
1268         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1269         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1270         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1271         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1272         /* Note: Value 47 is reserved for future use */
1273         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1274         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1275         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1276         /* Note: Values 51-62 are reserved for future use */
1277         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1278 };
1279
1280 enum i40e_filter_program_desc_dest {
1281         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1282         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1283         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1284 };
1285
1286 enum i40e_filter_program_desc_fd_status {
1287         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1288         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1289         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1290         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1291 };
1292
1293 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1294 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1295                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1296
1297 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1298 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1299
1300 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1301 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1302                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1303
1304 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1305 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1306
1307 enum i40e_filter_program_desc_pcmd {
1308         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1309         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1310 };
1311
1312 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1313 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1314
1315 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1316 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1317
1318 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1319                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1320 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1321                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1322 #ifdef X722_SUPPORT
1323
1324 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1325                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1326 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1327 #endif
1328
1329 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1330 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1331                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1332
1333 enum i40e_filter_type {
1334         I40E_FLOW_DIRECTOR_FLTR = 0,
1335         I40E_PE_QUAD_HASH_FLTR = 1,
1336         I40E_ETHERTYPE_FLTR,
1337         I40E_FCOE_CTX_FLTR,
1338         I40E_MAC_VLAN_FLTR,
1339         I40E_HASH_FLTR
1340 };
1341
1342 struct i40e_vsi_context {
1343         u16 seid;
1344         u16 uplink_seid;
1345         u16 vsi_number;
1346         u16 vsis_allocated;
1347         u16 vsis_unallocated;
1348         u16 flags;
1349         u8 pf_num;
1350         u8 vf_num;
1351         u8 connection_type;
1352         struct i40e_aqc_vsi_properties_data info;
1353 };
1354
1355 struct i40e_veb_context {
1356         u16 seid;
1357         u16 uplink_seid;
1358         u16 veb_number;
1359         u16 vebs_allocated;
1360         u16 vebs_unallocated;
1361         u16 flags;
1362         struct i40e_aqc_get_veb_parameters_completion info;
1363 };
1364
1365 /* Statistics collected by each port, VSI, VEB, and S-channel */
1366 struct i40e_eth_stats {
1367         u64 rx_bytes;                   /* gorc */
1368         u64 rx_unicast;                 /* uprc */
1369         u64 rx_multicast;               /* mprc */
1370         u64 rx_broadcast;               /* bprc */
1371         u64 rx_discards;                /* rdpc */
1372         u64 rx_unknown_protocol;        /* rupp */
1373         u64 tx_bytes;                   /* gotc */
1374         u64 tx_unicast;                 /* uptc */
1375         u64 tx_multicast;               /* mptc */
1376         u64 tx_broadcast;               /* bptc */
1377         u64 tx_discards;                /* tdpc */
1378         u64 tx_errors;                  /* tepc */
1379 };
1380
1381 /* Statistics collected per VEB per TC */
1382 struct i40e_veb_tc_stats {
1383         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1384         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1385         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1386         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1387 };
1388
1389 /* Statistics collected by the MAC */
1390 struct i40e_hw_port_stats {
1391         /* eth stats collected by the port */
1392         struct i40e_eth_stats eth;
1393
1394         /* additional port specific stats */
1395         u64 tx_dropped_link_down;       /* tdold */
1396         u64 crc_errors;                 /* crcerrs */
1397         u64 illegal_bytes;              /* illerrc */
1398         u64 error_bytes;                /* errbc */
1399         u64 mac_local_faults;           /* mlfc */
1400         u64 mac_remote_faults;          /* mrfc */
1401         u64 rx_length_errors;           /* rlec */
1402         u64 link_xon_rx;                /* lxonrxc */
1403         u64 link_xoff_rx;               /* lxoffrxc */
1404         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1405         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1406         u64 link_xon_tx;                /* lxontxc */
1407         u64 link_xoff_tx;               /* lxofftxc */
1408         u64 priority_xon_tx[8];         /* pxontxc[8] */
1409         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1410         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1411         u64 rx_size_64;                 /* prc64 */
1412         u64 rx_size_127;                /* prc127 */
1413         u64 rx_size_255;                /* prc255 */
1414         u64 rx_size_511;                /* prc511 */
1415         u64 rx_size_1023;               /* prc1023 */
1416         u64 rx_size_1522;               /* prc1522 */
1417         u64 rx_size_big;                /* prc9522 */
1418         u64 rx_undersize;               /* ruc */
1419         u64 rx_fragments;               /* rfc */
1420         u64 rx_oversize;                /* roc */
1421         u64 rx_jabber;                  /* rjc */
1422         u64 tx_size_64;                 /* ptc64 */
1423         u64 tx_size_127;                /* ptc127 */
1424         u64 tx_size_255;                /* ptc255 */
1425         u64 tx_size_511;                /* ptc511 */
1426         u64 tx_size_1023;               /* ptc1023 */
1427         u64 tx_size_1522;               /* ptc1522 */
1428         u64 tx_size_big;                /* ptc9522 */
1429         u64 mac_short_packet_dropped;   /* mspdc */
1430         u64 checksum_error;             /* xec */
1431         /* flow director stats */
1432         u64 fd_atr_match;
1433         u64 fd_sb_match;
1434         u64 fd_atr_tunnel_match;
1435         u32 fd_atr_status;
1436         u32 fd_sb_status;
1437         /* EEE LPI */
1438         u32 tx_lpi_status;
1439         u32 rx_lpi_status;
1440         u64 tx_lpi_count;               /* etlpic */
1441         u64 rx_lpi_count;               /* erlpic */
1442 };
1443
1444 /* Checksum and Shadow RAM pointers */
1445 #define I40E_SR_NVM_CONTROL_WORD                0x00
1446 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1447 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1448 #define I40E_SR_OPTION_ROM_PTR                  0x05
1449 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1450 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1451 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1452 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1453 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1454 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1455 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1456 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1457 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1458 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1459 #define I40E_SR_PBA_FLAGS                       0x15
1460 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1461 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1462 #define I40E_NVM_OEM_VER_OFF                    0x83
1463 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1464 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1465 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1466 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1467 #define I40E_SR_NVM_MAP_VERSION                 0x29
1468 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1469 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1470 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1471 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1472 #define I40E_SR_VPD_PTR                         0x2F
1473 #define I40E_SR_PXE_SETUP_PTR                   0x30
1474 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1475 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1476 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1477 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1478 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1479 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1480 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1481 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1482 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1483 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1484 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1485 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1486 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1487 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1488 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1489 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1490 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1491 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1492
1493 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1494 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1495 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1496 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1497 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1498
1499 /* Shadow RAM related */
1500 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1501 #define I40E_SR_BUF_ALIGNMENT           4096
1502 #define I40E_SR_WORDS_IN_1KB            512
1503 /* Checksum should be calculated such that after adding all the words,
1504  * including the checksum word itself, the sum should be 0xBABA.
1505  */
1506 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1507
1508 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1509
1510 enum i40e_switch_element_types {
1511         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1512         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1513         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1514         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1515         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1516         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1517         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1518         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1519         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1520 };
1521
1522 /* Supported EtherType filters */
1523 enum i40e_ether_type_index {
1524         I40E_ETHER_TYPE_1588            = 0,
1525         I40E_ETHER_TYPE_FIP             = 1,
1526         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1527         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1528         I40E_ETHER_TYPE_LLDP            = 4,
1529         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1530         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1531         I40E_ETHER_TYPE_QCN_CNM         = 7,
1532         I40E_ETHER_TYPE_8021X           = 8,
1533         I40E_ETHER_TYPE_ARP             = 9,
1534         I40E_ETHER_TYPE_RSV1            = 10,
1535         I40E_ETHER_TYPE_RSV2            = 11,
1536 };
1537
1538 /* Filter context base size is 1K */
1539 #define I40E_HASH_FILTER_BASE_SIZE      1024
1540 /* Supported Hash filter values */
1541 enum i40e_hash_filter_size {
1542         I40E_HASH_FILTER_SIZE_1K        = 0,
1543         I40E_HASH_FILTER_SIZE_2K        = 1,
1544         I40E_HASH_FILTER_SIZE_4K        = 2,
1545         I40E_HASH_FILTER_SIZE_8K        = 3,
1546         I40E_HASH_FILTER_SIZE_16K       = 4,
1547         I40E_HASH_FILTER_SIZE_32K       = 5,
1548         I40E_HASH_FILTER_SIZE_64K       = 6,
1549         I40E_HASH_FILTER_SIZE_128K      = 7,
1550         I40E_HASH_FILTER_SIZE_256K      = 8,
1551         I40E_HASH_FILTER_SIZE_512K      = 9,
1552         I40E_HASH_FILTER_SIZE_1M        = 10,
1553 };
1554
1555 /* DMA context base size is 0.5K */
1556 #define I40E_DMA_CNTX_BASE_SIZE         512
1557 /* Supported DMA context values */
1558 enum i40e_dma_cntx_size {
1559         I40E_DMA_CNTX_SIZE_512          = 0,
1560         I40E_DMA_CNTX_SIZE_1K           = 1,
1561         I40E_DMA_CNTX_SIZE_2K           = 2,
1562         I40E_DMA_CNTX_SIZE_4K           = 3,
1563         I40E_DMA_CNTX_SIZE_8K           = 4,
1564         I40E_DMA_CNTX_SIZE_16K          = 5,
1565         I40E_DMA_CNTX_SIZE_32K          = 6,
1566         I40E_DMA_CNTX_SIZE_64K          = 7,
1567         I40E_DMA_CNTX_SIZE_128K         = 8,
1568         I40E_DMA_CNTX_SIZE_256K         = 9,
1569 };
1570
1571 /* Supported Hash look up table (LUT) sizes */
1572 enum i40e_hash_lut_size {
1573         I40E_HASH_LUT_SIZE_128          = 0,
1574         I40E_HASH_LUT_SIZE_512          = 1,
1575 };
1576
1577 /* Structure to hold a per PF filter control settings */
1578 struct i40e_filter_control_settings {
1579         /* number of PE Quad Hash filter buckets */
1580         enum i40e_hash_filter_size pe_filt_num;
1581         /* number of PE Quad Hash contexts */
1582         enum i40e_dma_cntx_size pe_cntx_num;
1583         /* number of FCoE filter buckets */
1584         enum i40e_hash_filter_size fcoe_filt_num;
1585         /* number of FCoE DDP contexts */
1586         enum i40e_dma_cntx_size fcoe_cntx_num;
1587         /* size of the Hash LUT */
1588         enum i40e_hash_lut_size hash_lut_size;
1589         /* enable FDIR filters for PF and its VFs */
1590         bool enable_fdir;
1591         /* enable Ethertype filters for PF and its VFs */
1592         bool enable_ethtype;
1593         /* enable MAC/VLAN filters for PF and its VFs */
1594         bool enable_macvlan;
1595 };
1596
1597 /* Structure to hold device level control filter counts */
1598 struct i40e_control_filter_stats {
1599         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1600         u16 etype_used;       /* Used perfect EtherType filters */
1601         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1602         u16 etype_free;       /* Un-used perfect EtherType filters */
1603 };
1604
1605 enum i40e_reset_type {
1606         I40E_RESET_POR          = 0,
1607         I40E_RESET_CORER        = 1,
1608         I40E_RESET_GLOBR        = 2,
1609         I40E_RESET_EMPR         = 3,
1610 };
1611
1612 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1613 #define I40E_NVM_LLDP_CFG_PTR           0xD
1614 struct i40e_lldp_variables {
1615         u16 length;
1616         u16 adminstatus;
1617         u16 msgfasttx;
1618         u16 msgtxinterval;
1619         u16 txparams;
1620         u16 timers;
1621         u16 crc8;
1622 };
1623
1624 /* Offsets into Alternate Ram */
1625 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1626 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1627 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1628 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1629 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1630 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1631
1632 /* Alternate Ram Bandwidth Masks */
1633 #define I40E_ALT_BW_VALUE_MASK          0xFF
1634 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1635 #define I40E_ALT_BW_VALID_MASK          0x80000000
1636
1637 /* RSS Hash Table Size */
1638 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1639
1640 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1641 #define I40E_L3_SRC_SHIFT               47
1642 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1643 #define I40E_L3_V6_SRC_SHIFT            43
1644 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1645 #define I40E_L3_DST_SHIFT               35
1646 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1647 #define I40E_L3_V6_DST_SHIFT            35
1648 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1649 #define I40E_L4_SRC_SHIFT               34
1650 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1651 #define I40E_L4_DST_SHIFT               33
1652 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1653 #define I40E_VERIFY_TAG_SHIFT           31
1654 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1655
1656 #define I40E_FLEX_50_SHIFT              13
1657 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1658 #define I40E_FLEX_51_SHIFT              12
1659 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1660 #define I40E_FLEX_52_SHIFT              11
1661 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1662 #define I40E_FLEX_53_SHIFT              10
1663 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1664 #define I40E_FLEX_54_SHIFT              9
1665 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1666 #define I40E_FLEX_55_SHIFT              8
1667 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1668 #define I40E_FLEX_56_SHIFT              7
1669 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1670 #define I40E_FLEX_57_SHIFT              6
1671 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1672 #endif /* _I40E_TYPE_H_ */