1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
98 /* Data type manipulation macros. */
99 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
100 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
102 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
103 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
105 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
106 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
108 /* Number of Transmit Descriptors must be a multiple of 8. */
109 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
110 /* Number of Receive Descriptors must be a multiple of 32 if
111 * the number of descriptors is greater than 32.
113 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
115 #define I40E_DESC_UNUSED(R) \
116 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
117 (R)->next_to_clean - (R)->next_to_use - 1)
119 /* bitfields for Tx queue mapping in QTX_CTL */
120 #define I40E_QTX_CTL_VF_QUEUE 0x0
121 #define I40E_QTX_CTL_VM_QUEUE 0x1
122 #define I40E_QTX_CTL_PF_QUEUE 0x2
124 /* debug masks - set these bits in hw->debug_mask to control output */
125 enum i40e_debug_mask {
126 I40E_DEBUG_INIT = 0x00000001,
127 I40E_DEBUG_RELEASE = 0x00000002,
129 I40E_DEBUG_LINK = 0x00000010,
130 I40E_DEBUG_PHY = 0x00000020,
131 I40E_DEBUG_HMC = 0x00000040,
132 I40E_DEBUG_NVM = 0x00000080,
133 I40E_DEBUG_LAN = 0x00000100,
134 I40E_DEBUG_FLOW = 0x00000200,
135 I40E_DEBUG_DCB = 0x00000400,
136 I40E_DEBUG_DIAG = 0x00000800,
137 I40E_DEBUG_FD = 0x00001000,
138 I40E_DEBUG_PACKAGE = 0x00002000,
140 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
141 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
142 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
143 I40E_DEBUG_AQ_COMMAND = 0x06000000,
144 I40E_DEBUG_AQ = 0x0F000000,
146 I40E_DEBUG_USER = 0xF0000000,
148 I40E_DEBUG_ALL = 0xFFFFFFFF
152 #define I40E_PCI_LINK_STATUS 0xB2
153 #define I40E_PCI_LINK_WIDTH 0x3F0
154 #define I40E_PCI_LINK_WIDTH_1 0x10
155 #define I40E_PCI_LINK_WIDTH_2 0x20
156 #define I40E_PCI_LINK_WIDTH_4 0x40
157 #define I40E_PCI_LINK_WIDTH_8 0x80
158 #define I40E_PCI_LINK_SPEED 0xF
159 #define I40E_PCI_LINK_SPEED_2500 0x1
160 #define I40E_PCI_LINK_SPEED_5000 0x2
161 #define I40E_PCI_LINK_SPEED_8000 0x3
163 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
164 I40E_GLGEN_MSCA_STCODE_SHIFT)
165 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
166 I40E_GLGEN_MSCA_OPCODE_SHIFT)
167 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
168 I40E_GLGEN_MSCA_OPCODE_SHIFT)
170 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
171 I40E_GLGEN_MSCA_STCODE_SHIFT)
172 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
173 I40E_GLGEN_MSCA_OPCODE_SHIFT)
174 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
175 I40E_GLGEN_MSCA_OPCODE_SHIFT)
176 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
177 I40E_GLGEN_MSCA_OPCODE_SHIFT)
178 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
179 I40E_GLGEN_MSCA_OPCODE_SHIFT)
181 #define I40E_PHY_COM_REG_PAGE 0x1E
182 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
183 #define I40E_PHY_LED_MANUAL_ON 0x100
184 #define I40E_PHY_LED_PROV_REG_1 0xC430
185 #define I40E_PHY_LED_MODE_MASK 0xFFFF
186 #define I40E_PHY_LED_MODE_ORIG 0x80000000
189 enum i40e_memset_type {
195 enum i40e_memcpy_type {
196 I40E_NONDMA_TO_NONDMA = 0,
202 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
203 #define I40E_FW_API_VERSION_MINOR_X710 0x0005
206 /* These are structs for managing the hardware information and the operations.
207 * The structures of function pointers are filled out at init time when we
208 * know for sure exactly which hardware we're working with. This gives us the
209 * flexibility of using the same main driver code but adapting to slightly
210 * different hardware needs as new parts are developed. For this architecture,
211 * the Firmware and AdminQ are intended to insulate the driver from most of the
212 * future changes, but these structures will also do part of the job.
215 I40E_MAC_UNKNOWN = 0,
223 enum i40e_media_type {
224 I40E_MEDIA_TYPE_UNKNOWN = 0,
225 I40E_MEDIA_TYPE_FIBER,
226 I40E_MEDIA_TYPE_BASET,
227 I40E_MEDIA_TYPE_BACKPLANE,
230 I40E_MEDIA_TYPE_VIRTUAL
242 enum i40e_set_fc_aq_failures {
243 I40E_SET_FC_AQ_FAIL_NONE = 0,
244 I40E_SET_FC_AQ_FAIL_GET = 1,
245 I40E_SET_FC_AQ_FAIL_SET = 2,
246 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
247 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
259 I40E_VSI_TYPE_UNKNOWN
262 enum i40e_queue_type {
263 I40E_QUEUE_TYPE_RX = 0,
265 I40E_QUEUE_TYPE_PE_CEQ,
266 I40E_QUEUE_TYPE_UNKNOWN
269 struct i40e_link_status {
270 enum i40e_aq_phy_type phy_type;
271 enum i40e_aq_link_speed link_speed;
277 /* is Link Status Event notification to SW enabled */
284 /* 1st byte: module identifier */
285 #define I40E_MODULE_TYPE_SFP 0x03
286 #define I40E_MODULE_TYPE_QSFP 0x0D
287 /* 2nd byte: ethernet compliance codes for 10/40G */
288 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
289 #define I40E_MODULE_TYPE_40G_LR4 0x02
290 #define I40E_MODULE_TYPE_40G_SR4 0x04
291 #define I40E_MODULE_TYPE_40G_CR4 0x08
292 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
293 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
294 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
295 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
296 /* 3rd byte: ethernet compliance codes for 1G */
297 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
298 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
299 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
300 #define I40E_MODULE_TYPE_1000BASE_T 0x08
303 struct i40e_phy_info {
304 struct i40e_link_status link_info;
305 struct i40e_link_status link_info_old;
307 enum i40e_media_type media_type;
308 /* all the phy types the NVM is capable of */
312 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
313 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
314 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
315 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
316 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
317 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
318 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
319 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
320 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
321 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
323 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
324 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
325 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
326 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
327 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
328 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
329 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
330 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
331 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
332 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
333 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
334 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
335 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
336 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
337 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
338 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
339 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
340 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
342 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
343 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
344 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
345 * a shift is needed to adjust for this with values larger than 31. The
346 * only affected values are I40E_PHY_TYPE_25GBASE_*.
348 #define I40E_PHY_TYPE_OFFSET 1
349 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
350 I40E_PHY_TYPE_OFFSET)
351 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
352 I40E_PHY_TYPE_OFFSET)
353 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
354 I40E_PHY_TYPE_OFFSET)
355 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
356 I40E_PHY_TYPE_OFFSET)
357 #define I40E_HW_CAP_MAX_GPIO 30
358 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
359 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
361 enum i40e_acpi_programming_method {
362 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
363 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
366 #define I40E_WOL_SUPPORT_MASK 0x1
367 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
368 #define I40E_PROXY_SUPPORT_MASK 0x4
370 /* Capabilities of a PF or a VF or the whole device */
371 struct i40e_hw_capabilities {
373 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
374 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
375 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
378 u32 mng_protocols_over_mctp;
379 #define I40E_MNG_PROTOCOL_PLDM 0x2
380 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
381 #define I40E_MNG_PROTOCOL_NCSI 0x8
387 bool evb_802_1_qbg; /* Edge Virtual Bridging */
388 bool evb_802_1_qbh; /* Bridge Port Extension */
391 bool iscsi; /* Indicates iSCSI enabled */
395 #define I40E_FLEX10_MODE_UNKNOWN 0x0
396 #define I40E_FLEX10_MODE_DCC 0x1
397 #define I40E_FLEX10_MODE_DCI 0x2
400 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
401 #define I40E_FLEX10_STATUS_VC_MODE 0x2
403 bool sec_rev_disabled;
404 bool update_disabled;
405 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
406 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
412 u32 fd_filters_guaranteed;
413 u32 fd_filters_best_effort;
416 u32 rss_table_entry_width;
417 bool led[I40E_HW_CAP_MAX_GPIO];
418 bool sdp[I40E_HW_CAP_MAX_GPIO];
420 u32 num_flow_director_filters;
427 u32 num_msix_vectors;
428 u32 num_msix_vectors_vf;
437 bool apm_wol_support;
438 enum i40e_acpi_programming_method acpi_prog_method;
442 struct i40e_mac_info {
443 enum i40e_mac_type type;
445 u8 perm_addr[ETH_ALEN];
446 u8 san_addr[ETH_ALEN];
447 u8 port_addr[ETH_ALEN];
451 enum i40e_aq_resources_ids {
452 I40E_NVM_RESOURCE_ID = 1
455 enum i40e_aq_resource_access_type {
456 I40E_RESOURCE_READ = 1,
460 struct i40e_nvm_info {
461 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
462 u32 timeout; /* [ms] */
463 u16 sr_size; /* Shadow RAM size in words */
464 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
465 u16 version; /* NVM package version */
466 u32 eetrack; /* NVM data version */
467 u32 oem_ver; /* OEM version info */
470 /* definitions used in NVM update support */
472 enum i40e_nvmupd_cmd {
474 I40E_NVMUPD_READ_CON,
475 I40E_NVMUPD_READ_SNT,
476 I40E_NVMUPD_READ_LCB,
478 I40E_NVMUPD_WRITE_ERA,
479 I40E_NVMUPD_WRITE_CON,
480 I40E_NVMUPD_WRITE_SNT,
481 I40E_NVMUPD_WRITE_LCB,
482 I40E_NVMUPD_WRITE_SA,
483 I40E_NVMUPD_CSUM_CON,
485 I40E_NVMUPD_CSUM_LCB,
488 I40E_NVMUPD_GET_AQ_RESULT,
491 enum i40e_nvmupd_state {
492 I40E_NVMUPD_STATE_INIT,
493 I40E_NVMUPD_STATE_READING,
494 I40E_NVMUPD_STATE_WRITING,
495 I40E_NVMUPD_STATE_INIT_WAIT,
496 I40E_NVMUPD_STATE_WRITE_WAIT,
497 I40E_NVMUPD_STATE_ERROR
500 /* nvm_access definition and its masks/shifts need to be accessible to
501 * application, core driver, and shared code. Where is the right file?
503 #define I40E_NVM_READ 0xB
504 #define I40E_NVM_WRITE 0xC
506 #define I40E_NVM_MOD_PNT_MASK 0xFF
508 #define I40E_NVM_TRANS_SHIFT 8
509 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
510 #define I40E_NVM_CON 0x0
511 #define I40E_NVM_SNT 0x1
512 #define I40E_NVM_LCB 0x2
513 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
514 #define I40E_NVM_ERA 0x4
515 #define I40E_NVM_CSUM 0x8
516 #define I40E_NVM_EXEC 0xf
518 #define I40E_NVM_ADAPT_SHIFT 16
519 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
521 #define I40E_NVMUPD_MAX_DATA 4096
522 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
524 struct i40e_nvm_access {
527 u32 offset; /* in bytes */
528 u32 data_size; /* in bytes */
534 i40e_bus_type_unknown = 0,
537 i40e_bus_type_pci_express,
538 i40e_bus_type_reserved
542 enum i40e_bus_speed {
543 i40e_bus_speed_unknown = 0,
544 i40e_bus_speed_33 = 33,
545 i40e_bus_speed_66 = 66,
546 i40e_bus_speed_100 = 100,
547 i40e_bus_speed_120 = 120,
548 i40e_bus_speed_133 = 133,
549 i40e_bus_speed_2500 = 2500,
550 i40e_bus_speed_5000 = 5000,
551 i40e_bus_speed_8000 = 8000,
552 i40e_bus_speed_reserved
556 enum i40e_bus_width {
557 i40e_bus_width_unknown = 0,
558 i40e_bus_width_pcie_x1 = 1,
559 i40e_bus_width_pcie_x2 = 2,
560 i40e_bus_width_pcie_x4 = 4,
561 i40e_bus_width_pcie_x8 = 8,
562 i40e_bus_width_32 = 32,
563 i40e_bus_width_64 = 64,
564 i40e_bus_width_reserved
568 struct i40e_bus_info {
569 enum i40e_bus_speed speed;
570 enum i40e_bus_width width;
571 enum i40e_bus_type type;
579 /* Flow control (FC) parameters */
580 struct i40e_fc_info {
581 enum i40e_fc_mode current_mode; /* FC mode in effect */
582 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
585 #define I40E_MAX_TRAFFIC_CLASS 8
586 #define I40E_MAX_USER_PRIORITY 8
587 #define I40E_DCBX_MAX_APPS 32
588 #define I40E_LLDPDU_SIZE 1500
589 #define I40E_TLV_STATUS_OPER 0x1
590 #define I40E_TLV_STATUS_SYNC 0x2
591 #define I40E_TLV_STATUS_ERR 0x4
592 #define I40E_CEE_OPER_MAX_APPS 3
593 #define I40E_APP_PROTOID_FCOE 0x8906
594 #define I40E_APP_PROTOID_ISCSI 0x0cbc
595 #define I40E_APP_PROTOID_FIP 0x8914
596 #define I40E_APP_SEL_ETHTYPE 0x1
597 #define I40E_APP_SEL_TCPIP 0x2
598 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
599 #define I40E_CEE_APP_SEL_TCPIP 0x1
601 /* CEE or IEEE 802.1Qaz ETS Configuration data */
602 struct i40e_dcb_ets_config {
606 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
607 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
608 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
611 /* CEE or IEEE 802.1Qaz PFC Configuration data */
612 struct i40e_dcb_pfc_config {
619 /* CEE or IEEE 802.1Qaz Application Priority data */
620 struct i40e_dcb_app_priority_table {
626 struct i40e_dcbx_config {
628 #define I40E_DCBX_MODE_CEE 0x1
629 #define I40E_DCBX_MODE_IEEE 0x2
631 #define I40E_DCBX_APPS_NON_WILLING 0x1
633 u32 tlv_status; /* CEE mode TLV status */
634 struct i40e_dcb_ets_config etscfg;
635 struct i40e_dcb_ets_config etsrec;
636 struct i40e_dcb_pfc_config pfc;
637 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
640 /* Port hardware description */
645 /* subsystem structs */
646 struct i40e_phy_info phy;
647 struct i40e_mac_info mac;
648 struct i40e_bus_info bus;
649 struct i40e_nvm_info nvm;
650 struct i40e_fc_info fc;
655 u16 subsystem_device_id;
656 u16 subsystem_vendor_id;
659 bool adapter_stopped;
661 /* capabilities for entire device and PCI func */
662 struct i40e_hw_capabilities dev_caps;
663 struct i40e_hw_capabilities func_caps;
665 /* Flow Director shared filter space */
666 u16 fdir_shared_filter_count;
668 /* device profile info */
672 /* for multi-function MACs */
677 /* Closest numa node to the device */
680 /* Admin Queue info */
681 struct i40e_adminq_info aq;
683 /* state of nvm update process */
684 enum i40e_nvmupd_state nvmupd_state;
685 struct i40e_aq_desc nvm_wb_desc;
686 struct i40e_virt_mem nvm_buff;
687 bool nvm_release_on_done;
691 struct i40e_hmc_info hmc; /* HMC info struct */
693 /* LLDP/DCBX Status */
697 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
698 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
699 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
701 /* WoL and proxy support */
702 u16 num_wol_proxy_filters;
703 u16 wol_proxy_vsi_seid;
705 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
713 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
715 return (hw->mac.type == I40E_MAC_VF ||
716 hw->mac.type == I40E_MAC_X722_VF);
719 struct i40e_driver_version {
724 u8 driver_string[32];
728 union i40e_16byte_rx_desc {
730 __le64 pkt_addr; /* Packet buffer address */
731 __le64 hdr_addr; /* Header buffer address */
737 __le16 mirroring_status;
743 __le32 rss; /* RSS Hash */
744 __le32 fd_id; /* Flow director filter id */
745 __le32 fcoe_param; /* FCoE DDP Context id */
749 /* ext status/error/pktype/length */
750 __le64 status_error_len;
752 } wb; /* writeback */
755 union i40e_32byte_rx_desc {
757 __le64 pkt_addr; /* Packet buffer address */
758 __le64 hdr_addr; /* Header buffer address */
759 /* bit 0 of hdr_buffer_addr is DD bit */
767 __le16 mirroring_status;
773 __le32 rss; /* RSS Hash */
774 __le32 fcoe_param; /* FCoE DDP Context id */
775 /* Flow director filter id in case of
776 * Programming status desc WB
782 /* status/error/pktype/length */
783 __le64 status_error_len;
786 __le16 ext_status; /* extended status */
793 __le32 flex_bytes_lo;
797 __le32 flex_bytes_hi;
801 } wb; /* writeback */
804 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
805 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
806 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
807 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
808 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
809 I40E_RXD_QW0_FCOEINDX_SHIFT)
811 enum i40e_rx_desc_status_bits {
812 /* Note: These are predefined bit offsets */
813 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
814 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
815 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
816 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
817 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
818 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
819 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
820 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
822 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
823 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
824 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
825 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
826 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
827 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
828 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
829 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
832 #define I40E_RXD_QW1_STATUS_SHIFT 0
833 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
834 I40E_RXD_QW1_STATUS_SHIFT)
836 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
837 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
838 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
840 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
841 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
843 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
844 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
845 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
847 enum i40e_rx_desc_fltstat_values {
848 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
849 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
850 I40E_RX_DESC_FLTSTAT_RSV = 2,
851 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
854 #define I40E_RXD_PACKET_TYPE_UNICAST 0
855 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
856 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
857 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
859 #define I40E_RXD_QW1_ERROR_SHIFT 19
860 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
862 enum i40e_rx_desc_error_bits {
863 /* Note: These are predefined bit offsets */
864 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
865 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
866 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
867 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
868 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
869 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
870 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
871 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
872 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
875 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
876 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
877 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
878 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
879 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
880 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
883 #define I40E_RXD_QW1_PTYPE_SHIFT 30
884 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
886 /* Packet type non-ip values */
887 enum i40e_rx_l2_ptype {
888 I40E_RX_PTYPE_L2_RESERVED = 0,
889 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
890 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
891 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
892 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
893 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
894 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
895 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
896 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
897 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
898 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
899 I40E_RX_PTYPE_L2_ARP = 11,
900 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
901 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
902 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
903 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
904 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
905 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
906 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
907 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
908 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
909 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
910 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
911 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
912 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
913 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
916 struct i40e_rx_ptype_decoded {
923 u32 tunnel_end_prot:2;
924 u32 tunnel_end_frag:1;
929 enum i40e_rx_ptype_outer_ip {
930 I40E_RX_PTYPE_OUTER_L2 = 0,
931 I40E_RX_PTYPE_OUTER_IP = 1
934 enum i40e_rx_ptype_outer_ip_ver {
935 I40E_RX_PTYPE_OUTER_NONE = 0,
936 I40E_RX_PTYPE_OUTER_IPV4 = 0,
937 I40E_RX_PTYPE_OUTER_IPV6 = 1
940 enum i40e_rx_ptype_outer_fragmented {
941 I40E_RX_PTYPE_NOT_FRAG = 0,
942 I40E_RX_PTYPE_FRAG = 1
945 enum i40e_rx_ptype_tunnel_type {
946 I40E_RX_PTYPE_TUNNEL_NONE = 0,
947 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
948 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
949 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
950 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
953 enum i40e_rx_ptype_tunnel_end_prot {
954 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
955 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
956 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
959 enum i40e_rx_ptype_inner_prot {
960 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
961 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
962 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
963 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
964 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
965 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
968 enum i40e_rx_ptype_payload_layer {
969 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
970 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
971 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
972 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
975 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
976 #define I40E_RX_PTYPE_SHIFT 56
978 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
979 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
980 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
982 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
983 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
984 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
986 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
987 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
989 #define I40E_RXD_QW1_NEXTP_SHIFT 38
990 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
992 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
993 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
994 I40E_RXD_QW2_EXT_STATUS_SHIFT)
996 enum i40e_rx_desc_ext_status_bits {
997 /* Note: These are predefined bit offsets */
998 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
999 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1000 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1001 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1002 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1003 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1004 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1007 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1008 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1010 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1011 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1013 enum i40e_rx_desc_pe_status_bits {
1014 /* Note: These are predefined bit offsets */
1015 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1016 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1017 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1018 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1019 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1020 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1021 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1022 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1023 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1026 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1027 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1029 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1030 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1031 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1033 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1034 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1035 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1037 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1038 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1039 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1041 enum i40e_rx_prog_status_desc_status_bits {
1042 /* Note: These are predefined bit offsets */
1043 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1044 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1047 enum i40e_rx_prog_status_desc_prog_id_masks {
1048 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1049 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1050 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1053 enum i40e_rx_prog_status_desc_error_bits {
1054 /* Note: These are predefined bit offsets */
1055 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1056 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1057 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1058 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1061 #define I40E_TWO_BIT_MASK 0x3
1062 #define I40E_THREE_BIT_MASK 0x7
1063 #define I40E_FOUR_BIT_MASK 0xF
1064 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1067 struct i40e_tx_desc {
1068 __le64 buffer_addr; /* Address of descriptor's data buf */
1069 __le64 cmd_type_offset_bsz;
1072 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1073 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1075 enum i40e_tx_desc_dtype_value {
1076 I40E_TX_DESC_DTYPE_DATA = 0x0,
1077 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1078 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1079 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1080 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1081 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1082 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1083 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1084 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1085 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1088 #define I40E_TXD_QW1_CMD_SHIFT 4
1089 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1091 enum i40e_tx_desc_cmd_bits {
1092 I40E_TX_DESC_CMD_EOP = 0x0001,
1093 I40E_TX_DESC_CMD_RS = 0x0002,
1094 I40E_TX_DESC_CMD_ICRC = 0x0004,
1095 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1096 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1097 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1098 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1099 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1100 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1101 I40E_TX_DESC_CMD_FCOET = 0x0080,
1102 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1103 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1104 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1105 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1106 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1107 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1108 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1109 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1112 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1113 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1114 I40E_TXD_QW1_OFFSET_SHIFT)
1116 enum i40e_tx_desc_length_fields {
1117 /* Note: These are predefined bit offsets */
1118 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1119 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1120 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1123 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1124 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1125 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1126 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1128 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1129 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1130 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1132 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1133 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1135 /* Context descriptors */
1136 struct i40e_tx_context_desc {
1137 __le32 tunneling_params;
1140 __le64 type_cmd_tso_mss;
1143 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1144 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1146 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1147 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1149 enum i40e_tx_ctx_desc_cmd_bits {
1150 I40E_TX_CTX_DESC_TSO = 0x01,
1151 I40E_TX_CTX_DESC_TSYN = 0x02,
1152 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1153 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1154 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1155 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1156 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1157 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1158 I40E_TX_CTX_DESC_SWPE = 0x40
1161 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1162 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1163 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1165 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1166 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1167 I40E_TXD_CTX_QW1_MSS_SHIFT)
1169 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1170 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1172 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1173 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1174 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1176 enum i40e_tx_ctx_desc_eipt_offload {
1177 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1178 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1179 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1180 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1183 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1184 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1185 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1187 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1188 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1190 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1191 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1193 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1194 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1196 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1198 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1199 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1200 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1202 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1203 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1204 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1206 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1207 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1208 struct i40e_nop_desc {
1213 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1214 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1216 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1217 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1219 enum i40e_tx_nop_desc_cmd_bits {
1220 /* Note: These are predefined bit offsets */
1221 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1222 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1223 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1226 struct i40e_filter_program_desc {
1227 __le32 qindex_flex_ptype_vsi;
1229 __le32 dtype_cmd_cntindex;
1232 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1233 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1234 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1235 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1236 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1237 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1238 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1239 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1240 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1242 /* Packet Classifier Types for filters */
1243 enum i40e_filter_pctype {
1244 /* Note: Values 0-28 are reserved for future use.
1245 * Value 29, 30, 32 are not supported on XL710 and X710.
1247 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1248 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1249 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1250 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1251 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1252 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1253 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1254 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1255 /* Note: Values 37-38 are reserved for future use.
1256 * Value 39, 40, 42 are not supported on XL710 and X710.
1258 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1259 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1260 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1261 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1262 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1263 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1264 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1265 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1266 /* Note: Value 47 is reserved for future use */
1267 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1268 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1269 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1270 /* Note: Values 51-62 are reserved for future use */
1271 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1274 enum i40e_filter_program_desc_dest {
1275 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1276 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1277 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1280 enum i40e_filter_program_desc_fd_status {
1281 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1282 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1283 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1284 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1287 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1288 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1289 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1291 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1292 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1294 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1295 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1296 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1298 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1299 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1301 enum i40e_filter_program_desc_pcmd {
1302 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1303 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1306 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1307 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1309 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1310 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1312 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1313 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1314 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1315 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1317 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1318 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1319 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1321 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1322 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1323 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1325 enum i40e_filter_type {
1326 I40E_FLOW_DIRECTOR_FLTR = 0,
1327 I40E_PE_QUAD_HASH_FLTR = 1,
1328 I40E_ETHERTYPE_FLTR,
1334 struct i40e_vsi_context {
1339 u16 vsis_unallocated;
1344 struct i40e_aqc_vsi_properties_data info;
1347 struct i40e_veb_context {
1352 u16 vebs_unallocated;
1354 struct i40e_aqc_get_veb_parameters_completion info;
1357 /* Statistics collected by each port, VSI, VEB, and S-channel */
1358 struct i40e_eth_stats {
1359 u64 rx_bytes; /* gorc */
1360 u64 rx_unicast; /* uprc */
1361 u64 rx_multicast; /* mprc */
1362 u64 rx_broadcast; /* bprc */
1363 u64 rx_discards; /* rdpc */
1364 u64 rx_unknown_protocol; /* rupp */
1365 u64 tx_bytes; /* gotc */
1366 u64 tx_unicast; /* uptc */
1367 u64 tx_multicast; /* mptc */
1368 u64 tx_broadcast; /* bptc */
1369 u64 tx_discards; /* tdpc */
1370 u64 tx_errors; /* tepc */
1373 /* Statistics collected per VEB per TC */
1374 struct i40e_veb_tc_stats {
1375 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1376 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1377 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1378 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1381 /* Statistics collected per function for FCoE */
1382 struct i40e_fcoe_stats {
1383 u64 rx_fcoe_packets; /* fcoeprc */
1384 u64 rx_fcoe_dwords; /* focedwrc */
1385 u64 rx_fcoe_dropped; /* fcoerpdc */
1386 u64 tx_fcoe_packets; /* fcoeptc */
1387 u64 tx_fcoe_dwords; /* focedwtc */
1388 u64 fcoe_bad_fccrc; /* fcoecrc */
1389 u64 fcoe_last_error; /* fcoelast */
1390 u64 fcoe_ddp_count; /* fcoeddpc */
1393 /* offset to per function FCoE statistics block */
1394 #define I40E_FCOE_VF_STAT_OFFSET 0
1395 #define I40E_FCOE_PF_STAT_OFFSET 128
1396 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1398 /* Statistics collected by the MAC */
1399 struct i40e_hw_port_stats {
1400 /* eth stats collected by the port */
1401 struct i40e_eth_stats eth;
1403 /* additional port specific stats */
1404 u64 tx_dropped_link_down; /* tdold */
1405 u64 crc_errors; /* crcerrs */
1406 u64 illegal_bytes; /* illerrc */
1407 u64 error_bytes; /* errbc */
1408 u64 mac_local_faults; /* mlfc */
1409 u64 mac_remote_faults; /* mrfc */
1410 u64 rx_length_errors; /* rlec */
1411 u64 link_xon_rx; /* lxonrxc */
1412 u64 link_xoff_rx; /* lxoffrxc */
1413 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1414 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1415 u64 link_xon_tx; /* lxontxc */
1416 u64 link_xoff_tx; /* lxofftxc */
1417 u64 priority_xon_tx[8]; /* pxontxc[8] */
1418 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1419 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1420 u64 rx_size_64; /* prc64 */
1421 u64 rx_size_127; /* prc127 */
1422 u64 rx_size_255; /* prc255 */
1423 u64 rx_size_511; /* prc511 */
1424 u64 rx_size_1023; /* prc1023 */
1425 u64 rx_size_1522; /* prc1522 */
1426 u64 rx_size_big; /* prc9522 */
1427 u64 rx_undersize; /* ruc */
1428 u64 rx_fragments; /* rfc */
1429 u64 rx_oversize; /* roc */
1430 u64 rx_jabber; /* rjc */
1431 u64 tx_size_64; /* ptc64 */
1432 u64 tx_size_127; /* ptc127 */
1433 u64 tx_size_255; /* ptc255 */
1434 u64 tx_size_511; /* ptc511 */
1435 u64 tx_size_1023; /* ptc1023 */
1436 u64 tx_size_1522; /* ptc1522 */
1437 u64 tx_size_big; /* ptc9522 */
1438 u64 mac_short_packet_dropped; /* mspdc */
1439 u64 checksum_error; /* xec */
1440 /* flow director stats */
1443 u64 fd_atr_tunnel_match;
1449 u64 tx_lpi_count; /* etlpic */
1450 u64 rx_lpi_count; /* erlpic */
1453 /* Checksum and Shadow RAM pointers */
1454 #define I40E_SR_NVM_CONTROL_WORD 0x00
1455 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1456 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1457 #define I40E_SR_OPTION_ROM_PTR 0x05
1458 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1459 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1460 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1461 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1462 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1463 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1464 #define I40E_SR_PE_IMAGE_PTR 0x0C
1465 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1466 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1467 #define I40E_SR_EMP_MODULE_PTR 0x0F
1468 #define I40E_SR_PBA_FLAGS 0x15
1469 #define I40E_SR_PBA_BLOCK_PTR 0x16
1470 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1471 #define I40E_NVM_OEM_VER_OFF 0x83
1472 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1473 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1474 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1475 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1476 #define I40E_SR_NVM_MAP_VERSION 0x29
1477 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1478 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1479 #define I40E_SR_NVM_EETRACK_LO 0x2D
1480 #define I40E_SR_NVM_EETRACK_HI 0x2E
1481 #define I40E_SR_VPD_PTR 0x2F
1482 #define I40E_SR_PXE_SETUP_PTR 0x30
1483 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1484 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1485 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1486 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1487 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1488 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1489 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1490 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1491 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1492 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1493 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1494 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1495 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1496 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1497 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1498 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1499 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1500 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1501 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1503 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1504 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1505 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1506 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1507 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1509 /* Shadow RAM related */
1510 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1511 #define I40E_SR_BUF_ALIGNMENT 4096
1512 #define I40E_SR_WORDS_IN_1KB 512
1513 /* Checksum should be calculated such that after adding all the words,
1514 * including the checksum word itself, the sum should be 0xBABA.
1516 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1518 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1520 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1522 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1523 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1524 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1525 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1526 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1527 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1528 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1529 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1530 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1531 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1532 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1533 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1534 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1535 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1538 /* FCoE DIF/DIX Context descriptor */
1539 struct i40e_fcoe_difdix_context_desc {
1540 __le64 flags_buff0_buff1_ref;
1541 __le64 difapp_msk_bias;
1544 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1545 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1546 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1548 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1550 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1552 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1554 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1556 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1558 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1560 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1562 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1564 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1566 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1568 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1570 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1572 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1574 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1576 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1578 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1580 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1582 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1584 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1586 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1588 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1590 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1593 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1594 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1595 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1597 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1598 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1599 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1601 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1602 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1603 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1605 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1606 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1607 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1609 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1610 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1611 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1613 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1614 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1615 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1617 /* FCoE DIF/DIX Buffers descriptor */
1618 struct i40e_fcoe_difdix_buffers_desc {
1623 /* FCoE DDP Context descriptor */
1624 struct i40e_fcoe_ddp_context_desc {
1626 __le64 type_cmd_foff_lsize;
1629 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1630 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1631 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1633 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1634 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1635 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1637 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1638 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1639 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1640 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1641 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1642 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1643 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1646 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1647 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1648 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1650 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1651 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1652 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1654 /* FCoE DDP/DWO Queue Context descriptor */
1655 struct i40e_fcoe_queue_context_desc {
1656 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1657 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1660 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1661 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1662 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1664 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1665 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1666 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1668 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1669 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1670 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1672 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1673 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1674 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1676 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1677 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1678 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1681 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1682 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1683 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1685 /* FCoE DDP/DWO Filter Context descriptor */
1686 struct i40e_fcoe_filter_context_desc {
1690 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1691 __le16 rsvd_dmaindx;
1693 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1694 __le64 flags_rsvd_lanq;
1697 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1698 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1699 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1701 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1702 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1703 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1704 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1705 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1706 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1707 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1710 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1711 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1712 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1714 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1715 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1716 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1718 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1719 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1720 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1722 enum i40e_switch_element_types {
1723 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1724 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1725 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1726 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1727 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1728 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1729 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1730 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1731 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1734 /* Supported EtherType filters */
1735 enum i40e_ether_type_index {
1736 I40E_ETHER_TYPE_1588 = 0,
1737 I40E_ETHER_TYPE_FIP = 1,
1738 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1739 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1740 I40E_ETHER_TYPE_LLDP = 4,
1741 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1742 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1743 I40E_ETHER_TYPE_QCN_CNM = 7,
1744 I40E_ETHER_TYPE_8021X = 8,
1745 I40E_ETHER_TYPE_ARP = 9,
1746 I40E_ETHER_TYPE_RSV1 = 10,
1747 I40E_ETHER_TYPE_RSV2 = 11,
1750 /* Filter context base size is 1K */
1751 #define I40E_HASH_FILTER_BASE_SIZE 1024
1752 /* Supported Hash filter values */
1753 enum i40e_hash_filter_size {
1754 I40E_HASH_FILTER_SIZE_1K = 0,
1755 I40E_HASH_FILTER_SIZE_2K = 1,
1756 I40E_HASH_FILTER_SIZE_4K = 2,
1757 I40E_HASH_FILTER_SIZE_8K = 3,
1758 I40E_HASH_FILTER_SIZE_16K = 4,
1759 I40E_HASH_FILTER_SIZE_32K = 5,
1760 I40E_HASH_FILTER_SIZE_64K = 6,
1761 I40E_HASH_FILTER_SIZE_128K = 7,
1762 I40E_HASH_FILTER_SIZE_256K = 8,
1763 I40E_HASH_FILTER_SIZE_512K = 9,
1764 I40E_HASH_FILTER_SIZE_1M = 10,
1767 /* DMA context base size is 0.5K */
1768 #define I40E_DMA_CNTX_BASE_SIZE 512
1769 /* Supported DMA context values */
1770 enum i40e_dma_cntx_size {
1771 I40E_DMA_CNTX_SIZE_512 = 0,
1772 I40E_DMA_CNTX_SIZE_1K = 1,
1773 I40E_DMA_CNTX_SIZE_2K = 2,
1774 I40E_DMA_CNTX_SIZE_4K = 3,
1775 I40E_DMA_CNTX_SIZE_8K = 4,
1776 I40E_DMA_CNTX_SIZE_16K = 5,
1777 I40E_DMA_CNTX_SIZE_32K = 6,
1778 I40E_DMA_CNTX_SIZE_64K = 7,
1779 I40E_DMA_CNTX_SIZE_128K = 8,
1780 I40E_DMA_CNTX_SIZE_256K = 9,
1783 /* Supported Hash look up table (LUT) sizes */
1784 enum i40e_hash_lut_size {
1785 I40E_HASH_LUT_SIZE_128 = 0,
1786 I40E_HASH_LUT_SIZE_512 = 1,
1789 /* Structure to hold a per PF filter control settings */
1790 struct i40e_filter_control_settings {
1791 /* number of PE Quad Hash filter buckets */
1792 enum i40e_hash_filter_size pe_filt_num;
1793 /* number of PE Quad Hash contexts */
1794 enum i40e_dma_cntx_size pe_cntx_num;
1795 /* number of FCoE filter buckets */
1796 enum i40e_hash_filter_size fcoe_filt_num;
1797 /* number of FCoE DDP contexts */
1798 enum i40e_dma_cntx_size fcoe_cntx_num;
1799 /* size of the Hash LUT */
1800 enum i40e_hash_lut_size hash_lut_size;
1801 /* enable FDIR filters for PF and its VFs */
1803 /* enable Ethertype filters for PF and its VFs */
1804 bool enable_ethtype;
1805 /* enable MAC/VLAN filters for PF and its VFs */
1806 bool enable_macvlan;
1809 /* Structure to hold device level control filter counts */
1810 struct i40e_control_filter_stats {
1811 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1812 u16 etype_used; /* Used perfect EtherType filters */
1813 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1814 u16 etype_free; /* Un-used perfect EtherType filters */
1817 enum i40e_reset_type {
1819 I40E_RESET_CORER = 1,
1820 I40E_RESET_GLOBR = 2,
1821 I40E_RESET_EMPR = 3,
1824 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1825 #define I40E_NVM_LLDP_CFG_PTR 0xD
1826 struct i40e_lldp_variables {
1836 /* Offsets into Alternate Ram */
1837 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1838 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1839 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1840 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1841 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1842 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1844 /* Alternate Ram Bandwidth Masks */
1845 #define I40E_ALT_BW_VALUE_MASK 0xFF
1846 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1847 #define I40E_ALT_BW_VALID_MASK 0x80000000
1849 /* RSS Hash Table Size */
1850 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1852 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1853 #define I40E_L3_SRC_SHIFT 47
1854 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1855 #define I40E_L3_V6_SRC_SHIFT 43
1856 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1857 #define I40E_L3_DST_SHIFT 35
1858 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1859 #define I40E_L3_V6_DST_SHIFT 35
1860 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1861 #define I40E_L4_SRC_SHIFT 34
1862 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1863 #define I40E_L4_DST_SHIFT 33
1864 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1865 #define I40E_VERIFY_TAG_SHIFT 31
1866 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1868 #define I40E_FLEX_50_SHIFT 13
1869 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1870 #define I40E_FLEX_51_SHIFT 12
1871 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1872 #define I40E_FLEX_52_SHIFT 11
1873 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1874 #define I40E_FLEX_53_SHIFT 10
1875 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1876 #define I40E_FLEX_54_SHIFT 9
1877 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1878 #define I40E_FLEX_55_SHIFT 8
1879 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1880 #define I40E_FLEX_56_SHIFT 7
1881 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1882 #define I40E_FLEX_57_SHIFT 6
1883 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1885 /* Version format for Dynamic Device Personalization(DDP) */
1886 struct i40e_ddp_version {
1893 #define I40E_DDP_NAME_SIZE 32
1895 /* Package header */
1896 struct i40e_package_header {
1897 struct i40e_ddp_version version;
1899 u32 segment_offset[1];
1902 /* Generic segment header */
1903 struct i40e_generic_seg_header {
1904 #define SEGMENT_TYPE_METADATA 0x00000001
1905 #define SEGMENT_TYPE_NOTES 0x00000002
1906 #define SEGMENT_TYPE_I40E 0x00000011
1907 #define SEGMENT_TYPE_X722 0x00000012
1909 struct i40e_ddp_version version;
1911 char name[I40E_DDP_NAME_SIZE];
1914 struct i40e_metadata_segment {
1915 struct i40e_generic_seg_header header;
1916 struct i40e_ddp_version version;
1918 char name[I40E_DDP_NAME_SIZE];
1921 struct i40e_device_id_entry {
1923 u32 sub_vendor_dev_id;
1926 struct i40e_profile_segment {
1927 struct i40e_generic_seg_header header;
1928 struct i40e_ddp_version version;
1929 char name[I40E_DDP_NAME_SIZE];
1930 u32 device_table_count;
1931 struct i40e_device_id_entry device_table[1];
1934 struct i40e_section_table {
1936 u32 section_offset[1];
1939 struct i40e_profile_section_header {
1943 #define SECTION_TYPE_INFO 0x00000010
1944 #define SECTION_TYPE_MMIO 0x00000800
1945 #define SECTION_TYPE_AQ 0x00000801
1946 #define SECTION_TYPE_NOTE 0x80000000
1947 #define SECTION_TYPE_NAME 0x80000001
1954 struct i40e_profile_info {
1956 struct i40e_ddp_version version;
1958 #define I40E_DDP_ADD_TRACKID 0x01
1959 #define I40E_DDP_REMOVE_TRACKID 0x02
1961 u8 name[I40E_DDP_NAME_SIZE];
1963 #endif /* _I40E_TYPE_H_ */