1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
160 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
161 I40E_GLGEN_MSCA_STCODE_SHIFT)
162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
163 I40E_GLGEN_MSCA_OPCODE_SHIFT)
164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
165 I40E_GLGEN_MSCA_OPCODE_SHIFT)
167 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
168 I40E_GLGEN_MSCA_STCODE_SHIFT)
169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
170 I40E_GLGEN_MSCA_OPCODE_SHIFT)
171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
172 I40E_GLGEN_MSCA_OPCODE_SHIFT)
173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
174 I40E_GLGEN_MSCA_OPCODE_SHIFT)
175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
176 I40E_GLGEN_MSCA_OPCODE_SHIFT)
178 #define I40E_PHY_COM_REG_PAGE 0x1E
179 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
180 #define I40E_PHY_LED_MANUAL_ON 0x100
181 #define I40E_PHY_LED_PROV_REG_1 0xC430
182 #define I40E_PHY_LED_MODE_MASK 0xFFFF
183 #define I40E_PHY_LED_MODE_ORIG 0x80000000
186 enum i40e_memset_type {
192 enum i40e_memcpy_type {
193 I40E_NONDMA_TO_NONDMA = 0,
200 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
202 #define I40E_FW_API_VERSION_MINOR_X710 0x0005
205 /* These are structs for managing the hardware information and the operations.
206 * The structures of function pointers are filled out at init time when we
207 * know for sure exactly which hardware we're working with. This gives us the
208 * flexibility of using the same main driver code but adapting to slightly
209 * different hardware needs as new parts are developed. For this architecture,
210 * the Firmware and AdminQ are intended to insulate the driver from most of the
211 * future changes, but these structures will also do part of the job.
214 I40E_MAC_UNKNOWN = 0,
225 enum i40e_media_type {
226 I40E_MEDIA_TYPE_UNKNOWN = 0,
227 I40E_MEDIA_TYPE_FIBER,
228 I40E_MEDIA_TYPE_BASET,
229 I40E_MEDIA_TYPE_BACKPLANE,
232 I40E_MEDIA_TYPE_VIRTUAL
244 enum i40e_set_fc_aq_failures {
245 I40E_SET_FC_AQ_FAIL_NONE = 0,
246 I40E_SET_FC_AQ_FAIL_GET = 1,
247 I40E_SET_FC_AQ_FAIL_SET = 2,
248 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
249 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
261 I40E_VSI_TYPE_UNKNOWN
264 enum i40e_queue_type {
265 I40E_QUEUE_TYPE_RX = 0,
267 I40E_QUEUE_TYPE_PE_CEQ,
268 I40E_QUEUE_TYPE_UNKNOWN
271 struct i40e_link_status {
272 enum i40e_aq_phy_type phy_type;
273 enum i40e_aq_link_speed link_speed;
278 /* is Link Status Event notification to SW enabled */
285 /* 1st byte: module identifier */
286 #define I40E_MODULE_TYPE_SFP 0x03
287 #define I40E_MODULE_TYPE_QSFP 0x0D
288 /* 2nd byte: ethernet compliance codes for 10/40G */
289 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
290 #define I40E_MODULE_TYPE_40G_LR4 0x02
291 #define I40E_MODULE_TYPE_40G_SR4 0x04
292 #define I40E_MODULE_TYPE_40G_CR4 0x08
293 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
294 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
295 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
296 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
297 /* 3rd byte: ethernet compliance codes for 1G */
298 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
299 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
300 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
301 #define I40E_MODULE_TYPE_1000BASE_T 0x08
304 struct i40e_phy_info {
305 struct i40e_link_status link_info;
306 struct i40e_link_status link_info_old;
308 enum i40e_media_type media_type;
309 /* all the phy types the NVM is capable of */
313 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
314 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
315 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
316 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
317 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
318 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
319 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
320 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
321 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
322 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
323 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
325 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
326 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
327 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
328 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
329 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
330 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
331 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
332 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
333 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
334 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
335 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
336 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
337 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
338 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
339 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
340 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
341 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
342 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)
343 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)
344 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)
345 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)
346 #define I40E_HW_CAP_MAX_GPIO 30
347 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
348 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
351 enum i40e_acpi_programming_method {
352 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
353 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
356 #define I40E_WOL_SUPPORT_MASK 1
357 #define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1)
358 #define I40E_PROXY_SUPPORT_MASK (1 << 2)
361 /* Capabilities of a PF or a VF or the whole device */
362 struct i40e_hw_capabilities {
364 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
365 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
366 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
374 bool evb_802_1_qbg; /* Edge Virtual Bridging */
375 bool evb_802_1_qbh; /* Bridge Port Extension */
378 bool iscsi; /* Indicates iSCSI enabled */
382 #define I40E_FLEX10_MODE_UNKNOWN 0x0
383 #define I40E_FLEX10_MODE_DCC 0x1
384 #define I40E_FLEX10_MODE_DCI 0x2
387 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
388 #define I40E_FLEX10_STATUS_VC_MODE 0x2
390 bool sec_rev_disabled;
391 bool update_disabled;
392 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
393 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
399 u32 fd_filters_guaranteed;
400 u32 fd_filters_best_effort;
403 u32 rss_table_entry_width;
404 bool led[I40E_HW_CAP_MAX_GPIO];
405 bool sdp[I40E_HW_CAP_MAX_GPIO];
407 u32 num_flow_director_filters;
414 u32 num_msix_vectors;
415 u32 num_msix_vectors_vf;
425 bool apm_wol_support;
426 enum i40e_acpi_programming_method acpi_prog_method;
431 struct i40e_mac_info {
432 enum i40e_mac_type type;
433 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
434 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
435 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
436 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
440 enum i40e_aq_resources_ids {
441 I40E_NVM_RESOURCE_ID = 1
444 enum i40e_aq_resource_access_type {
445 I40E_RESOURCE_READ = 1,
449 struct i40e_nvm_info {
450 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
451 u32 timeout; /* [ms] */
452 u16 sr_size; /* Shadow RAM size in words */
453 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
454 u16 version; /* NVM package version */
455 u32 eetrack; /* NVM data version */
456 u32 oem_ver; /* OEM version info */
459 /* definitions used in NVM update support */
461 enum i40e_nvmupd_cmd {
463 I40E_NVMUPD_READ_CON,
464 I40E_NVMUPD_READ_SNT,
465 I40E_NVMUPD_READ_LCB,
467 I40E_NVMUPD_WRITE_ERA,
468 I40E_NVMUPD_WRITE_CON,
469 I40E_NVMUPD_WRITE_SNT,
470 I40E_NVMUPD_WRITE_LCB,
471 I40E_NVMUPD_WRITE_SA,
472 I40E_NVMUPD_CSUM_CON,
474 I40E_NVMUPD_CSUM_LCB,
477 I40E_NVMUPD_GET_AQ_RESULT,
480 enum i40e_nvmupd_state {
481 I40E_NVMUPD_STATE_INIT,
482 I40E_NVMUPD_STATE_READING,
483 I40E_NVMUPD_STATE_WRITING,
484 I40E_NVMUPD_STATE_INIT_WAIT,
485 I40E_NVMUPD_STATE_WRITE_WAIT,
488 /* nvm_access definition and its masks/shifts need to be accessible to
489 * application, core driver, and shared code. Where is the right file?
491 #define I40E_NVM_READ 0xB
492 #define I40E_NVM_WRITE 0xC
494 #define I40E_NVM_MOD_PNT_MASK 0xFF
496 #define I40E_NVM_TRANS_SHIFT 8
497 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
498 #define I40E_NVM_CON 0x0
499 #define I40E_NVM_SNT 0x1
500 #define I40E_NVM_LCB 0x2
501 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
502 #define I40E_NVM_ERA 0x4
503 #define I40E_NVM_CSUM 0x8
504 #define I40E_NVM_EXEC 0xf
506 #define I40E_NVM_ADAPT_SHIFT 16
507 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
509 #define I40E_NVMUPD_MAX_DATA 4096
510 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
512 struct i40e_nvm_access {
515 u32 offset; /* in bytes */
516 u32 data_size; /* in bytes */
522 i40e_bus_type_unknown = 0,
525 i40e_bus_type_pci_express,
526 i40e_bus_type_reserved
530 enum i40e_bus_speed {
531 i40e_bus_speed_unknown = 0,
532 i40e_bus_speed_33 = 33,
533 i40e_bus_speed_66 = 66,
534 i40e_bus_speed_100 = 100,
535 i40e_bus_speed_120 = 120,
536 i40e_bus_speed_133 = 133,
537 i40e_bus_speed_2500 = 2500,
538 i40e_bus_speed_5000 = 5000,
539 i40e_bus_speed_8000 = 8000,
540 i40e_bus_speed_reserved
544 enum i40e_bus_width {
545 i40e_bus_width_unknown = 0,
546 i40e_bus_width_pcie_x1 = 1,
547 i40e_bus_width_pcie_x2 = 2,
548 i40e_bus_width_pcie_x4 = 4,
549 i40e_bus_width_pcie_x8 = 8,
550 i40e_bus_width_32 = 32,
551 i40e_bus_width_64 = 64,
552 i40e_bus_width_reserved
556 struct i40e_bus_info {
557 enum i40e_bus_speed speed;
558 enum i40e_bus_width width;
559 enum i40e_bus_type type;
567 /* Flow control (FC) parameters */
568 struct i40e_fc_info {
569 enum i40e_fc_mode current_mode; /* FC mode in effect */
570 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
573 #define I40E_MAX_TRAFFIC_CLASS 8
574 #define I40E_MAX_USER_PRIORITY 8
575 #define I40E_DCBX_MAX_APPS 32
576 #define I40E_LLDPDU_SIZE 1500
577 #define I40E_TLV_STATUS_OPER 0x1
578 #define I40E_TLV_STATUS_SYNC 0x2
579 #define I40E_TLV_STATUS_ERR 0x4
580 #define I40E_CEE_OPER_MAX_APPS 3
581 #define I40E_APP_PROTOID_FCOE 0x8906
582 #define I40E_APP_PROTOID_ISCSI 0x0cbc
583 #define I40E_APP_PROTOID_FIP 0x8914
584 #define I40E_APP_SEL_ETHTYPE 0x1
585 #define I40E_APP_SEL_TCPIP 0x2
586 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
587 #define I40E_CEE_APP_SEL_TCPIP 0x1
589 /* CEE or IEEE 802.1Qaz ETS Configuration data */
590 struct i40e_dcb_ets_config {
594 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
595 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
596 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
599 /* CEE or IEEE 802.1Qaz PFC Configuration data */
600 struct i40e_dcb_pfc_config {
607 /* CEE or IEEE 802.1Qaz Application Priority data */
608 struct i40e_dcb_app_priority_table {
614 struct i40e_dcbx_config {
616 #define I40E_DCBX_MODE_CEE 0x1
617 #define I40E_DCBX_MODE_IEEE 0x2
619 #define I40E_DCBX_APPS_NON_WILLING 0x1
621 u32 tlv_status; /* CEE mode TLV status */
622 struct i40e_dcb_ets_config etscfg;
623 struct i40e_dcb_ets_config etsrec;
624 struct i40e_dcb_pfc_config pfc;
625 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
628 /* Port hardware description */
633 /* subsystem structs */
634 struct i40e_phy_info phy;
635 struct i40e_mac_info mac;
636 struct i40e_bus_info bus;
637 struct i40e_nvm_info nvm;
638 struct i40e_fc_info fc;
643 u16 subsystem_device_id;
644 u16 subsystem_vendor_id;
647 bool adapter_stopped;
649 /* capabilities for entire device and PCI func */
650 struct i40e_hw_capabilities dev_caps;
651 struct i40e_hw_capabilities func_caps;
653 /* Flow Director shared filter space */
654 u16 fdir_shared_filter_count;
656 /* device profile info */
660 /* for multi-function MACs */
665 /* Closest numa node to the device */
668 /* Admin Queue info */
669 struct i40e_adminq_info aq;
671 /* state of nvm update process */
672 enum i40e_nvmupd_state nvmupd_state;
673 struct i40e_aq_desc nvm_wb_desc;
674 struct i40e_virt_mem nvm_buff;
675 bool nvm_release_on_done;
679 struct i40e_hmc_info hmc; /* HMC info struct */
681 /* LLDP/DCBX Status */
685 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
686 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
687 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
690 /* WoL and proxy support */
691 u16 num_wol_proxy_filters;
692 u16 wol_proxy_vsi_seid;
695 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
700 #ifndef I40E_NDIS_SUPPORT
702 #endif /* I40E_NDIS_SUPPORT */
705 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
708 return (hw->mac.type == I40E_MAC_VF ||
709 hw->mac.type == I40E_MAC_X722_VF);
711 return hw->mac.type == I40E_MAC_VF;
715 struct i40e_driver_version {
720 u8 driver_string[32];
724 union i40e_16byte_rx_desc {
726 __le64 pkt_addr; /* Packet buffer address */
727 __le64 hdr_addr; /* Header buffer address */
733 __le16 mirroring_status;
739 __le32 rss; /* RSS Hash */
740 __le32 fd_id; /* Flow director filter id */
741 __le32 fcoe_param; /* FCoE DDP Context id */
745 /* ext status/error/pktype/length */
746 __le64 status_error_len;
748 } wb; /* writeback */
751 union i40e_32byte_rx_desc {
753 __le64 pkt_addr; /* Packet buffer address */
754 __le64 hdr_addr; /* Header buffer address */
755 /* bit 0 of hdr_buffer_addr is DD bit */
763 __le16 mirroring_status;
769 __le32 rss; /* RSS Hash */
770 __le32 fcoe_param; /* FCoE DDP Context id */
771 /* Flow director filter id in case of
772 * Programming status desc WB
778 /* status/error/pktype/length */
779 __le64 status_error_len;
782 __le16 ext_status; /* extended status */
789 __le32 flex_bytes_lo;
793 __le32 flex_bytes_hi;
797 } wb; /* writeback */
800 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
801 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
802 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
803 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
804 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
805 I40E_RXD_QW0_FCOEINDX_SHIFT)
807 enum i40e_rx_desc_status_bits {
808 /* Note: These are predefined bit offsets */
809 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
810 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
811 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
812 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
813 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
814 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
815 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
817 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
819 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
822 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
823 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
824 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
825 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
826 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
827 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
829 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
831 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
833 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
836 #define I40E_RXD_QW1_STATUS_SHIFT 0
837 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
838 I40E_RXD_QW1_STATUS_SHIFT)
840 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
841 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
842 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
844 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
845 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
847 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
848 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
849 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
851 enum i40e_rx_desc_fltstat_values {
852 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
853 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
854 I40E_RX_DESC_FLTSTAT_RSV = 2,
855 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
858 #define I40E_RXD_PACKET_TYPE_UNICAST 0
859 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
860 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
861 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
863 #define I40E_RXD_QW1_ERROR_SHIFT 19
864 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
866 enum i40e_rx_desc_error_bits {
867 /* Note: These are predefined bit offsets */
868 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
869 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
870 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
871 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
872 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
873 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
874 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
875 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
876 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
879 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
880 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
881 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
882 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
883 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
884 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
887 #define I40E_RXD_QW1_PTYPE_SHIFT 30
888 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
890 /* Packet type non-ip values */
891 enum i40e_rx_l2_ptype {
892 I40E_RX_PTYPE_L2_RESERVED = 0,
893 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
894 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
895 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
896 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
897 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
898 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
899 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
900 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
901 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
902 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
903 I40E_RX_PTYPE_L2_ARP = 11,
904 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
905 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
906 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
907 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
908 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
909 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
910 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
911 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
912 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
913 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
914 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
915 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
916 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
917 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
920 struct i40e_rx_ptype_decoded {
927 u32 tunnel_end_prot:2;
928 u32 tunnel_end_frag:1;
933 enum i40e_rx_ptype_outer_ip {
934 I40E_RX_PTYPE_OUTER_L2 = 0,
935 I40E_RX_PTYPE_OUTER_IP = 1
938 enum i40e_rx_ptype_outer_ip_ver {
939 I40E_RX_PTYPE_OUTER_NONE = 0,
940 I40E_RX_PTYPE_OUTER_IPV4 = 0,
941 I40E_RX_PTYPE_OUTER_IPV6 = 1
944 enum i40e_rx_ptype_outer_fragmented {
945 I40E_RX_PTYPE_NOT_FRAG = 0,
946 I40E_RX_PTYPE_FRAG = 1
949 enum i40e_rx_ptype_tunnel_type {
950 I40E_RX_PTYPE_TUNNEL_NONE = 0,
951 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
952 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
953 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
954 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
957 enum i40e_rx_ptype_tunnel_end_prot {
958 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
959 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
960 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
963 enum i40e_rx_ptype_inner_prot {
964 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
965 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
966 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
967 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
968 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
969 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
972 enum i40e_rx_ptype_payload_layer {
973 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
974 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
975 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
976 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
979 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
980 #define I40E_RX_PTYPE_SHIFT 56
982 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
983 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
984 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
986 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
987 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
988 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
990 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
991 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
993 #define I40E_RXD_QW1_NEXTP_SHIFT 38
994 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
996 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
997 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
998 I40E_RXD_QW2_EXT_STATUS_SHIFT)
1000 enum i40e_rx_desc_ext_status_bits {
1001 /* Note: These are predefined bit offsets */
1002 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
1003 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1004 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1005 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1006 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1007 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1008 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1011 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1012 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1014 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1015 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1017 enum i40e_rx_desc_pe_status_bits {
1018 /* Note: These are predefined bit offsets */
1019 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1020 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1021 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1022 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1023 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1024 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1025 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1026 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1027 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1030 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1031 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1033 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1034 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1035 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1037 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1038 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1039 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1041 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1042 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1043 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1045 enum i40e_rx_prog_status_desc_status_bits {
1046 /* Note: These are predefined bit offsets */
1047 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1048 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1051 enum i40e_rx_prog_status_desc_prog_id_masks {
1052 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1053 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1054 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1057 enum i40e_rx_prog_status_desc_error_bits {
1058 /* Note: These are predefined bit offsets */
1059 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1060 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1061 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1062 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1065 #define I40E_TWO_BIT_MASK 0x3
1066 #define I40E_THREE_BIT_MASK 0x7
1067 #define I40E_FOUR_BIT_MASK 0xF
1068 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1071 struct i40e_tx_desc {
1072 __le64 buffer_addr; /* Address of descriptor's data buf */
1073 __le64 cmd_type_offset_bsz;
1076 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1077 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1079 enum i40e_tx_desc_dtype_value {
1080 I40E_TX_DESC_DTYPE_DATA = 0x0,
1081 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1082 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1083 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1084 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1085 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1086 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1087 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1088 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1089 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1092 #define I40E_TXD_QW1_CMD_SHIFT 4
1093 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1095 enum i40e_tx_desc_cmd_bits {
1096 I40E_TX_DESC_CMD_EOP = 0x0001,
1097 I40E_TX_DESC_CMD_RS = 0x0002,
1098 I40E_TX_DESC_CMD_ICRC = 0x0004,
1099 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1100 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1101 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1102 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1103 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1104 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1105 I40E_TX_DESC_CMD_FCOET = 0x0080,
1106 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1107 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1108 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1109 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1110 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1111 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1112 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1113 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1116 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1117 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1118 I40E_TXD_QW1_OFFSET_SHIFT)
1120 enum i40e_tx_desc_length_fields {
1121 /* Note: These are predefined bit offsets */
1122 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1123 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1124 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1127 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1128 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1129 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1130 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1132 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1133 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1134 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1136 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1137 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1139 /* Context descriptors */
1140 struct i40e_tx_context_desc {
1141 __le32 tunneling_params;
1144 __le64 type_cmd_tso_mss;
1147 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1148 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1150 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1151 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1153 enum i40e_tx_ctx_desc_cmd_bits {
1154 I40E_TX_CTX_DESC_TSO = 0x01,
1155 I40E_TX_CTX_DESC_TSYN = 0x02,
1156 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1157 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1158 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1159 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1160 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1161 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1162 I40E_TX_CTX_DESC_SWPE = 0x40
1165 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1166 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1167 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1169 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1170 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1171 I40E_TXD_CTX_QW1_MSS_SHIFT)
1173 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1174 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1176 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1177 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1178 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1180 enum i40e_tx_ctx_desc_eipt_offload {
1181 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1182 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1183 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1184 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1187 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1188 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1189 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1191 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1192 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1194 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1195 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1197 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1198 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1200 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1202 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1203 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1204 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1206 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1207 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1208 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1211 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1212 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1214 struct i40e_nop_desc {
1219 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1220 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1222 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1223 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1225 enum i40e_tx_nop_desc_cmd_bits {
1226 /* Note: These are predefined bit offsets */
1227 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1228 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1229 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1232 struct i40e_filter_program_desc {
1233 __le32 qindex_flex_ptype_vsi;
1235 __le32 dtype_cmd_cntindex;
1238 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1239 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1240 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1241 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1242 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1243 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1244 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1245 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1246 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1248 /* Packet Classifier Types for filters */
1249 enum i40e_filter_pctype {
1251 /* Note: Values 0-28 are reserved for future use.
1252 * Value 29, 30, 32 are not supported on XL710 and X710.
1254 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1255 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1257 /* Note: Values 0-30 are reserved for future use */
1259 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1261 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1263 /* Note: Value 32 is reserved for future use */
1265 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1266 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1267 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1268 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1270 /* Note: Values 37-38 are reserved for future use.
1271 * Value 39, 40, 42 are not supported on XL710 and X710.
1273 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1274 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1276 /* Note: Values 37-40 are reserved for future use */
1278 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1280 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1282 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1283 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1284 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1285 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1286 /* Note: Value 47 is reserved for future use */
1287 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1288 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1289 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1290 /* Note: Values 51-62 are reserved for future use */
1291 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1294 enum i40e_filter_program_desc_dest {
1295 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1296 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1297 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1300 enum i40e_filter_program_desc_fd_status {
1301 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1302 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1303 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1304 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1307 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1308 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1309 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1311 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1312 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1314 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1315 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1316 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1318 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1319 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1321 enum i40e_filter_program_desc_pcmd {
1322 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1323 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1326 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1327 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1329 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1330 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1332 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1333 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1334 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1335 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1338 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1339 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1340 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1343 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1344 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1345 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1347 enum i40e_filter_type {
1348 I40E_FLOW_DIRECTOR_FLTR = 0,
1349 I40E_PE_QUAD_HASH_FLTR = 1,
1350 I40E_ETHERTYPE_FLTR,
1356 struct i40e_vsi_context {
1361 u16 vsis_unallocated;
1366 struct i40e_aqc_vsi_properties_data info;
1369 struct i40e_veb_context {
1374 u16 vebs_unallocated;
1376 struct i40e_aqc_get_veb_parameters_completion info;
1379 /* Statistics collected by each port, VSI, VEB, and S-channel */
1380 struct i40e_eth_stats {
1381 u64 rx_bytes; /* gorc */
1382 u64 rx_unicast; /* uprc */
1383 u64 rx_multicast; /* mprc */
1384 u64 rx_broadcast; /* bprc */
1385 u64 rx_discards; /* rdpc */
1386 u64 rx_unknown_protocol; /* rupp */
1387 u64 tx_bytes; /* gotc */
1388 u64 tx_unicast; /* uptc */
1389 u64 tx_multicast; /* mptc */
1390 u64 tx_broadcast; /* bptc */
1391 u64 tx_discards; /* tdpc */
1392 u64 tx_errors; /* tepc */
1395 /* Statistics collected per VEB per TC */
1396 struct i40e_veb_tc_stats {
1397 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1398 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1399 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1400 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1403 /* Statistics collected per function for FCoE */
1404 struct i40e_fcoe_stats {
1405 u64 rx_fcoe_packets; /* fcoeprc */
1406 u64 rx_fcoe_dwords; /* focedwrc */
1407 u64 rx_fcoe_dropped; /* fcoerpdc */
1408 u64 tx_fcoe_packets; /* fcoeptc */
1409 u64 tx_fcoe_dwords; /* focedwtc */
1410 u64 fcoe_bad_fccrc; /* fcoecrc */
1411 u64 fcoe_last_error; /* fcoelast */
1412 u64 fcoe_ddp_count; /* fcoeddpc */
1415 /* offset to per function FCoE statistics block */
1416 #define I40E_FCOE_VF_STAT_OFFSET 0
1417 #define I40E_FCOE_PF_STAT_OFFSET 128
1418 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1420 /* Statistics collected by the MAC */
1421 struct i40e_hw_port_stats {
1422 /* eth stats collected by the port */
1423 struct i40e_eth_stats eth;
1425 /* additional port specific stats */
1426 u64 tx_dropped_link_down; /* tdold */
1427 u64 crc_errors; /* crcerrs */
1428 u64 illegal_bytes; /* illerrc */
1429 u64 error_bytes; /* errbc */
1430 u64 mac_local_faults; /* mlfc */
1431 u64 mac_remote_faults; /* mrfc */
1432 u64 rx_length_errors; /* rlec */
1433 u64 link_xon_rx; /* lxonrxc */
1434 u64 link_xoff_rx; /* lxoffrxc */
1435 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1436 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1437 u64 link_xon_tx; /* lxontxc */
1438 u64 link_xoff_tx; /* lxofftxc */
1439 u64 priority_xon_tx[8]; /* pxontxc[8] */
1440 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1441 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1442 u64 rx_size_64; /* prc64 */
1443 u64 rx_size_127; /* prc127 */
1444 u64 rx_size_255; /* prc255 */
1445 u64 rx_size_511; /* prc511 */
1446 u64 rx_size_1023; /* prc1023 */
1447 u64 rx_size_1522; /* prc1522 */
1448 u64 rx_size_big; /* prc9522 */
1449 u64 rx_undersize; /* ruc */
1450 u64 rx_fragments; /* rfc */
1451 u64 rx_oversize; /* roc */
1452 u64 rx_jabber; /* rjc */
1453 u64 tx_size_64; /* ptc64 */
1454 u64 tx_size_127; /* ptc127 */
1455 u64 tx_size_255; /* ptc255 */
1456 u64 tx_size_511; /* ptc511 */
1457 u64 tx_size_1023; /* ptc1023 */
1458 u64 tx_size_1522; /* ptc1522 */
1459 u64 tx_size_big; /* ptc9522 */
1460 u64 mac_short_packet_dropped; /* mspdc */
1461 u64 checksum_error; /* xec */
1462 /* flow director stats */
1465 u64 fd_atr_tunnel_match;
1471 u64 tx_lpi_count; /* etlpic */
1472 u64 rx_lpi_count; /* erlpic */
1475 /* Checksum and Shadow RAM pointers */
1476 #define I40E_SR_NVM_CONTROL_WORD 0x00
1477 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1478 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1479 #define I40E_SR_OPTION_ROM_PTR 0x05
1480 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1481 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1482 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1483 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1484 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1485 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1486 #define I40E_SR_PE_IMAGE_PTR 0x0C
1487 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1488 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1489 #define I40E_SR_EMP_MODULE_PTR 0x0F
1490 #define I40E_SR_PBA_FLAGS 0x15
1491 #define I40E_SR_PBA_BLOCK_PTR 0x16
1492 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1493 #define I40E_NVM_OEM_VER_OFF 0x83
1494 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1495 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1496 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1497 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1498 #define I40E_SR_NVM_MAP_VERSION 0x29
1499 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1500 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1501 #define I40E_SR_NVM_EETRACK_LO 0x2D
1502 #define I40E_SR_NVM_EETRACK_HI 0x2E
1503 #define I40E_SR_VPD_PTR 0x2F
1504 #define I40E_SR_PXE_SETUP_PTR 0x30
1505 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1506 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1507 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1508 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1509 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1510 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1511 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1512 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1513 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1514 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1515 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1516 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1517 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1518 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1519 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1520 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1521 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1522 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1524 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1525 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1526 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1527 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1528 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1530 /* Shadow RAM related */
1531 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1532 #define I40E_SR_BUF_ALIGNMENT 4096
1533 #define I40E_SR_WORDS_IN_1KB 512
1534 /* Checksum should be calculated such that after adding all the words,
1535 * including the checksum word itself, the sum should be 0xBABA.
1537 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1539 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1541 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1543 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1544 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1545 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1546 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1547 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1548 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1549 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1550 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1551 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1552 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1553 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1554 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1555 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1556 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1559 /* FCoE DIF/DIX Context descriptor */
1560 struct i40e_fcoe_difdix_context_desc {
1561 __le64 flags_buff0_buff1_ref;
1562 __le64 difapp_msk_bias;
1565 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1566 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1567 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1569 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1571 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1573 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1575 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1577 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1579 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1581 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1583 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1585 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1587 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1589 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1591 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1593 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1595 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1597 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1599 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1601 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1603 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1605 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1607 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1609 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1611 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1614 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1615 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1616 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1619 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1620 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1623 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1624 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1626 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1627 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1628 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1631 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1632 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1634 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1635 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1636 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1638 /* FCoE DIF/DIX Buffers descriptor */
1639 struct i40e_fcoe_difdix_buffers_desc {
1644 /* FCoE DDP Context descriptor */
1645 struct i40e_fcoe_ddp_context_desc {
1647 __le64 type_cmd_foff_lsize;
1650 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1651 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1652 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1654 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1655 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1656 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1658 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1659 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1660 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1661 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1662 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1663 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1664 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1667 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1668 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1669 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1671 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1672 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1673 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1675 /* FCoE DDP/DWO Queue Context descriptor */
1676 struct i40e_fcoe_queue_context_desc {
1677 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1678 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1681 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1682 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1683 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1685 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1686 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1687 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1689 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1690 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1691 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1693 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1694 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1695 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1697 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1698 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1699 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1702 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1703 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1704 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1706 /* FCoE DDP/DWO Filter Context descriptor */
1707 struct i40e_fcoe_filter_context_desc {
1711 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1712 __le16 rsvd_dmaindx;
1714 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1715 __le64 flags_rsvd_lanq;
1718 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1719 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1720 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1722 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1723 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1724 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1725 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1726 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1727 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1728 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1731 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1732 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1733 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1735 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1736 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1737 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1739 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1740 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1741 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1743 enum i40e_switch_element_types {
1744 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1745 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1746 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1747 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1748 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1749 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1750 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1751 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1752 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1755 /* Supported EtherType filters */
1756 enum i40e_ether_type_index {
1757 I40E_ETHER_TYPE_1588 = 0,
1758 I40E_ETHER_TYPE_FIP = 1,
1759 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1760 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1761 I40E_ETHER_TYPE_LLDP = 4,
1762 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1763 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1764 I40E_ETHER_TYPE_QCN_CNM = 7,
1765 I40E_ETHER_TYPE_8021X = 8,
1766 I40E_ETHER_TYPE_ARP = 9,
1767 I40E_ETHER_TYPE_RSV1 = 10,
1768 I40E_ETHER_TYPE_RSV2 = 11,
1771 /* Filter context base size is 1K */
1772 #define I40E_HASH_FILTER_BASE_SIZE 1024
1773 /* Supported Hash filter values */
1774 enum i40e_hash_filter_size {
1775 I40E_HASH_FILTER_SIZE_1K = 0,
1776 I40E_HASH_FILTER_SIZE_2K = 1,
1777 I40E_HASH_FILTER_SIZE_4K = 2,
1778 I40E_HASH_FILTER_SIZE_8K = 3,
1779 I40E_HASH_FILTER_SIZE_16K = 4,
1780 I40E_HASH_FILTER_SIZE_32K = 5,
1781 I40E_HASH_FILTER_SIZE_64K = 6,
1782 I40E_HASH_FILTER_SIZE_128K = 7,
1783 I40E_HASH_FILTER_SIZE_256K = 8,
1784 I40E_HASH_FILTER_SIZE_512K = 9,
1785 I40E_HASH_FILTER_SIZE_1M = 10,
1788 /* DMA context base size is 0.5K */
1789 #define I40E_DMA_CNTX_BASE_SIZE 512
1790 /* Supported DMA context values */
1791 enum i40e_dma_cntx_size {
1792 I40E_DMA_CNTX_SIZE_512 = 0,
1793 I40E_DMA_CNTX_SIZE_1K = 1,
1794 I40E_DMA_CNTX_SIZE_2K = 2,
1795 I40E_DMA_CNTX_SIZE_4K = 3,
1796 I40E_DMA_CNTX_SIZE_8K = 4,
1797 I40E_DMA_CNTX_SIZE_16K = 5,
1798 I40E_DMA_CNTX_SIZE_32K = 6,
1799 I40E_DMA_CNTX_SIZE_64K = 7,
1800 I40E_DMA_CNTX_SIZE_128K = 8,
1801 I40E_DMA_CNTX_SIZE_256K = 9,
1804 /* Supported Hash look up table (LUT) sizes */
1805 enum i40e_hash_lut_size {
1806 I40E_HASH_LUT_SIZE_128 = 0,
1807 I40E_HASH_LUT_SIZE_512 = 1,
1810 /* Structure to hold a per PF filter control settings */
1811 struct i40e_filter_control_settings {
1812 /* number of PE Quad Hash filter buckets */
1813 enum i40e_hash_filter_size pe_filt_num;
1814 /* number of PE Quad Hash contexts */
1815 enum i40e_dma_cntx_size pe_cntx_num;
1816 /* number of FCoE filter buckets */
1817 enum i40e_hash_filter_size fcoe_filt_num;
1818 /* number of FCoE DDP contexts */
1819 enum i40e_dma_cntx_size fcoe_cntx_num;
1820 /* size of the Hash LUT */
1821 enum i40e_hash_lut_size hash_lut_size;
1822 /* enable FDIR filters for PF and its VFs */
1824 /* enable Ethertype filters for PF and its VFs */
1825 bool enable_ethtype;
1826 /* enable MAC/VLAN filters for PF and its VFs */
1827 bool enable_macvlan;
1830 /* Structure to hold device level control filter counts */
1831 struct i40e_control_filter_stats {
1832 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1833 u16 etype_used; /* Used perfect EtherType filters */
1834 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1835 u16 etype_free; /* Un-used perfect EtherType filters */
1838 enum i40e_reset_type {
1840 I40E_RESET_CORER = 1,
1841 I40E_RESET_GLOBR = 2,
1842 I40E_RESET_EMPR = 3,
1845 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1846 #define I40E_NVM_LLDP_CFG_PTR 0xD
1847 struct i40e_lldp_variables {
1857 /* Offsets into Alternate Ram */
1858 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1859 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1860 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1861 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1862 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1863 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1865 /* Alternate Ram Bandwidth Masks */
1866 #define I40E_ALT_BW_VALUE_MASK 0xFF
1867 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1868 #define I40E_ALT_BW_VALID_MASK 0x80000000
1870 /* RSS Hash Table Size */
1871 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1873 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1874 #define I40E_L3_SRC_SHIFT 47
1875 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1876 #define I40E_L3_V6_SRC_SHIFT 43
1877 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1878 #define I40E_L3_DST_SHIFT 35
1879 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1880 #define I40E_L3_V6_DST_SHIFT 35
1881 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1882 #define I40E_L4_SRC_SHIFT 34
1883 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1884 #define I40E_L4_DST_SHIFT 33
1885 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1886 #define I40E_VERIFY_TAG_SHIFT 31
1887 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1889 #define I40E_FLEX_50_SHIFT 13
1890 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1891 #define I40E_FLEX_51_SHIFT 12
1892 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1893 #define I40E_FLEX_52_SHIFT 11
1894 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1895 #define I40E_FLEX_53_SHIFT 10
1896 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1897 #define I40E_FLEX_54_SHIFT 9
1898 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1899 #define I40E_FLEX_55_SHIFT 8
1900 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1901 #define I40E_FLEX_56_SHIFT 7
1902 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1903 #define I40E_FLEX_57_SHIFT 6
1904 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1905 #endif /* _I40E_TYPE_H_ */