1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
160 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
161 I40E_GLGEN_MSCA_STCODE_SHIFT)
162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
163 I40E_GLGEN_MSCA_OPCODE_SHIFT)
164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
165 I40E_GLGEN_MSCA_OPCODE_SHIFT)
167 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
168 I40E_GLGEN_MSCA_STCODE_SHIFT)
169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
170 I40E_GLGEN_MSCA_OPCODE_SHIFT)
171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
172 I40E_GLGEN_MSCA_OPCODE_SHIFT)
173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
174 I40E_GLGEN_MSCA_OPCODE_SHIFT)
175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
176 I40E_GLGEN_MSCA_OPCODE_SHIFT)
178 #define I40E_PHY_COM_REG_PAGE 0x1E
179 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
180 #define I40E_PHY_LED_MANUAL_ON 0x100
181 #define I40E_PHY_LED_PROV_REG_1 0xC430
182 #define I40E_PHY_LED_MODE_MASK 0xFFFF
183 #define I40E_PHY_LED_MODE_ORIG 0x80000000
186 enum i40e_memset_type {
192 enum i40e_memcpy_type {
193 I40E_NONDMA_TO_NONDMA = 0,
199 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
200 #define I40E_FW_API_VERSION_MINOR_X710 0x0005
203 /* These are structs for managing the hardware information and the operations.
204 * The structures of function pointers are filled out at init time when we
205 * know for sure exactly which hardware we're working with. This gives us the
206 * flexibility of using the same main driver code but adapting to slightly
207 * different hardware needs as new parts are developed. For this architecture,
208 * the Firmware and AdminQ are intended to insulate the driver from most of the
209 * future changes, but these structures will also do part of the job.
212 I40E_MAC_UNKNOWN = 0,
220 enum i40e_media_type {
221 I40E_MEDIA_TYPE_UNKNOWN = 0,
222 I40E_MEDIA_TYPE_FIBER,
223 I40E_MEDIA_TYPE_BASET,
224 I40E_MEDIA_TYPE_BACKPLANE,
227 I40E_MEDIA_TYPE_VIRTUAL
239 enum i40e_set_fc_aq_failures {
240 I40E_SET_FC_AQ_FAIL_NONE = 0,
241 I40E_SET_FC_AQ_FAIL_GET = 1,
242 I40E_SET_FC_AQ_FAIL_SET = 2,
243 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
244 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
256 I40E_VSI_TYPE_UNKNOWN
259 enum i40e_queue_type {
260 I40E_QUEUE_TYPE_RX = 0,
262 I40E_QUEUE_TYPE_PE_CEQ,
263 I40E_QUEUE_TYPE_UNKNOWN
266 struct i40e_link_status {
267 enum i40e_aq_phy_type phy_type;
268 enum i40e_aq_link_speed link_speed;
274 /* is Link Status Event notification to SW enabled */
281 /* 1st byte: module identifier */
282 #define I40E_MODULE_TYPE_SFP 0x03
283 #define I40E_MODULE_TYPE_QSFP 0x0D
284 /* 2nd byte: ethernet compliance codes for 10/40G */
285 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
286 #define I40E_MODULE_TYPE_40G_LR4 0x02
287 #define I40E_MODULE_TYPE_40G_SR4 0x04
288 #define I40E_MODULE_TYPE_40G_CR4 0x08
289 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
290 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
291 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
292 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
293 /* 3rd byte: ethernet compliance codes for 1G */
294 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
295 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
296 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
297 #define I40E_MODULE_TYPE_1000BASE_T 0x08
300 struct i40e_phy_info {
301 struct i40e_link_status link_info;
302 struct i40e_link_status link_info_old;
304 enum i40e_media_type media_type;
305 /* all the phy types the NVM is capable of */
309 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
310 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
311 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
312 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
313 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
314 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
315 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
316 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
317 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
318 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
319 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
320 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
321 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
322 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
323 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
324 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
325 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
326 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
327 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
328 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
329 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
330 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
331 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
332 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
333 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
334 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
335 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
336 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
337 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
339 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
340 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
341 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
342 * a shift is needed to adjust for this with values larger than 31. The
343 * only affected values are I40E_PHY_TYPE_25GBASE_*.
345 #define I40E_PHY_TYPE_OFFSET 1
346 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
347 I40E_PHY_TYPE_OFFSET)
348 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
349 I40E_PHY_TYPE_OFFSET)
350 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
351 I40E_PHY_TYPE_OFFSET)
352 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
353 I40E_PHY_TYPE_OFFSET)
354 #define I40E_HW_CAP_MAX_GPIO 30
355 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
356 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
358 enum i40e_acpi_programming_method {
359 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
360 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
363 #define I40E_WOL_SUPPORT_MASK 0x1
364 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
365 #define I40E_PROXY_SUPPORT_MASK 0x4
367 /* Capabilities of a PF or a VF or the whole device */
368 struct i40e_hw_capabilities {
370 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
371 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
372 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
375 u32 mng_protocols_over_mctp;
376 #define I40E_MNG_PROTOCOL_PLDM 0x2
377 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
378 #define I40E_MNG_PROTOCOL_NCSI 0x8
384 bool evb_802_1_qbg; /* Edge Virtual Bridging */
385 bool evb_802_1_qbh; /* Bridge Port Extension */
388 bool iscsi; /* Indicates iSCSI enabled */
392 #define I40E_FLEX10_MODE_UNKNOWN 0x0
393 #define I40E_FLEX10_MODE_DCC 0x1
394 #define I40E_FLEX10_MODE_DCI 0x2
397 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
398 #define I40E_FLEX10_STATUS_VC_MODE 0x2
400 bool sec_rev_disabled;
401 bool update_disabled;
402 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
403 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
409 u32 fd_filters_guaranteed;
410 u32 fd_filters_best_effort;
413 u32 rss_table_entry_width;
414 bool led[I40E_HW_CAP_MAX_GPIO];
415 bool sdp[I40E_HW_CAP_MAX_GPIO];
417 u32 num_flow_director_filters;
424 u32 num_msix_vectors;
425 u32 num_msix_vectors_vf;
434 bool apm_wol_support;
435 enum i40e_acpi_programming_method acpi_prog_method;
439 struct i40e_mac_info {
440 enum i40e_mac_type type;
441 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
442 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
443 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
444 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
448 enum i40e_aq_resources_ids {
449 I40E_NVM_RESOURCE_ID = 1
452 enum i40e_aq_resource_access_type {
453 I40E_RESOURCE_READ = 1,
457 struct i40e_nvm_info {
458 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
459 u32 timeout; /* [ms] */
460 u16 sr_size; /* Shadow RAM size in words */
461 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
462 u16 version; /* NVM package version */
463 u32 eetrack; /* NVM data version */
464 u32 oem_ver; /* OEM version info */
467 /* definitions used in NVM update support */
469 enum i40e_nvmupd_cmd {
471 I40E_NVMUPD_READ_CON,
472 I40E_NVMUPD_READ_SNT,
473 I40E_NVMUPD_READ_LCB,
475 I40E_NVMUPD_WRITE_ERA,
476 I40E_NVMUPD_WRITE_CON,
477 I40E_NVMUPD_WRITE_SNT,
478 I40E_NVMUPD_WRITE_LCB,
479 I40E_NVMUPD_WRITE_SA,
480 I40E_NVMUPD_CSUM_CON,
482 I40E_NVMUPD_CSUM_LCB,
485 I40E_NVMUPD_GET_AQ_RESULT,
488 enum i40e_nvmupd_state {
489 I40E_NVMUPD_STATE_INIT,
490 I40E_NVMUPD_STATE_READING,
491 I40E_NVMUPD_STATE_WRITING,
492 I40E_NVMUPD_STATE_INIT_WAIT,
493 I40E_NVMUPD_STATE_WRITE_WAIT,
494 I40E_NVMUPD_STATE_ERROR
497 /* nvm_access definition and its masks/shifts need to be accessible to
498 * application, core driver, and shared code. Where is the right file?
500 #define I40E_NVM_READ 0xB
501 #define I40E_NVM_WRITE 0xC
503 #define I40E_NVM_MOD_PNT_MASK 0xFF
505 #define I40E_NVM_TRANS_SHIFT 8
506 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
507 #define I40E_NVM_CON 0x0
508 #define I40E_NVM_SNT 0x1
509 #define I40E_NVM_LCB 0x2
510 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
511 #define I40E_NVM_ERA 0x4
512 #define I40E_NVM_CSUM 0x8
513 #define I40E_NVM_EXEC 0xf
515 #define I40E_NVM_ADAPT_SHIFT 16
516 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
518 #define I40E_NVMUPD_MAX_DATA 4096
519 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
521 struct i40e_nvm_access {
524 u32 offset; /* in bytes */
525 u32 data_size; /* in bytes */
531 i40e_bus_type_unknown = 0,
534 i40e_bus_type_pci_express,
535 i40e_bus_type_reserved
539 enum i40e_bus_speed {
540 i40e_bus_speed_unknown = 0,
541 i40e_bus_speed_33 = 33,
542 i40e_bus_speed_66 = 66,
543 i40e_bus_speed_100 = 100,
544 i40e_bus_speed_120 = 120,
545 i40e_bus_speed_133 = 133,
546 i40e_bus_speed_2500 = 2500,
547 i40e_bus_speed_5000 = 5000,
548 i40e_bus_speed_8000 = 8000,
549 i40e_bus_speed_reserved
553 enum i40e_bus_width {
554 i40e_bus_width_unknown = 0,
555 i40e_bus_width_pcie_x1 = 1,
556 i40e_bus_width_pcie_x2 = 2,
557 i40e_bus_width_pcie_x4 = 4,
558 i40e_bus_width_pcie_x8 = 8,
559 i40e_bus_width_32 = 32,
560 i40e_bus_width_64 = 64,
561 i40e_bus_width_reserved
565 struct i40e_bus_info {
566 enum i40e_bus_speed speed;
567 enum i40e_bus_width width;
568 enum i40e_bus_type type;
576 /* Flow control (FC) parameters */
577 struct i40e_fc_info {
578 enum i40e_fc_mode current_mode; /* FC mode in effect */
579 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
582 #define I40E_MAX_TRAFFIC_CLASS 8
583 #define I40E_MAX_USER_PRIORITY 8
584 #define I40E_DCBX_MAX_APPS 32
585 #define I40E_LLDPDU_SIZE 1500
586 #define I40E_TLV_STATUS_OPER 0x1
587 #define I40E_TLV_STATUS_SYNC 0x2
588 #define I40E_TLV_STATUS_ERR 0x4
589 #define I40E_CEE_OPER_MAX_APPS 3
590 #define I40E_APP_PROTOID_FCOE 0x8906
591 #define I40E_APP_PROTOID_ISCSI 0x0cbc
592 #define I40E_APP_PROTOID_FIP 0x8914
593 #define I40E_APP_SEL_ETHTYPE 0x1
594 #define I40E_APP_SEL_TCPIP 0x2
595 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
596 #define I40E_CEE_APP_SEL_TCPIP 0x1
598 /* CEE or IEEE 802.1Qaz ETS Configuration data */
599 struct i40e_dcb_ets_config {
603 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
604 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
605 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
608 /* CEE or IEEE 802.1Qaz PFC Configuration data */
609 struct i40e_dcb_pfc_config {
616 /* CEE or IEEE 802.1Qaz Application Priority data */
617 struct i40e_dcb_app_priority_table {
623 struct i40e_dcbx_config {
625 #define I40E_DCBX_MODE_CEE 0x1
626 #define I40E_DCBX_MODE_IEEE 0x2
628 #define I40E_DCBX_APPS_NON_WILLING 0x1
630 u32 tlv_status; /* CEE mode TLV status */
631 struct i40e_dcb_ets_config etscfg;
632 struct i40e_dcb_ets_config etsrec;
633 struct i40e_dcb_pfc_config pfc;
634 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
637 /* Port hardware description */
642 /* subsystem structs */
643 struct i40e_phy_info phy;
644 struct i40e_mac_info mac;
645 struct i40e_bus_info bus;
646 struct i40e_nvm_info nvm;
647 struct i40e_fc_info fc;
652 u16 subsystem_device_id;
653 u16 subsystem_vendor_id;
656 bool adapter_stopped;
658 /* capabilities for entire device and PCI func */
659 struct i40e_hw_capabilities dev_caps;
660 struct i40e_hw_capabilities func_caps;
662 /* Flow Director shared filter space */
663 u16 fdir_shared_filter_count;
665 /* device profile info */
669 /* for multi-function MACs */
674 /* Closest numa node to the device */
677 /* Admin Queue info */
678 struct i40e_adminq_info aq;
680 /* state of nvm update process */
681 enum i40e_nvmupd_state nvmupd_state;
682 struct i40e_aq_desc nvm_wb_desc;
683 struct i40e_virt_mem nvm_buff;
684 bool nvm_release_on_done;
688 struct i40e_hmc_info hmc; /* HMC info struct */
690 /* LLDP/DCBX Status */
694 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
695 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
696 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
698 /* WoL and proxy support */
699 u16 num_wol_proxy_filters;
700 u16 wol_proxy_vsi_seid;
702 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
710 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
712 return (hw->mac.type == I40E_MAC_VF ||
713 hw->mac.type == I40E_MAC_X722_VF);
716 struct i40e_driver_version {
721 u8 driver_string[32];
725 union i40e_16byte_rx_desc {
727 __le64 pkt_addr; /* Packet buffer address */
728 __le64 hdr_addr; /* Header buffer address */
734 __le16 mirroring_status;
740 __le32 rss; /* RSS Hash */
741 __le32 fd_id; /* Flow director filter id */
742 __le32 fcoe_param; /* FCoE DDP Context id */
746 /* ext status/error/pktype/length */
747 __le64 status_error_len;
749 } wb; /* writeback */
752 union i40e_32byte_rx_desc {
754 __le64 pkt_addr; /* Packet buffer address */
755 __le64 hdr_addr; /* Header buffer address */
756 /* bit 0 of hdr_buffer_addr is DD bit */
764 __le16 mirroring_status;
770 __le32 rss; /* RSS Hash */
771 __le32 fcoe_param; /* FCoE DDP Context id */
772 /* Flow director filter id in case of
773 * Programming status desc WB
779 /* status/error/pktype/length */
780 __le64 status_error_len;
783 __le16 ext_status; /* extended status */
790 __le32 flex_bytes_lo;
794 __le32 flex_bytes_hi;
798 } wb; /* writeback */
801 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
802 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
803 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
804 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
805 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
806 I40E_RXD_QW0_FCOEINDX_SHIFT)
808 enum i40e_rx_desc_status_bits {
809 /* Note: These are predefined bit offsets */
810 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
811 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
812 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
813 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
814 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
815 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
816 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
817 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
819 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
820 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
821 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
822 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
823 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
824 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
825 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
826 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
829 #define I40E_RXD_QW1_STATUS_SHIFT 0
830 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
831 I40E_RXD_QW1_STATUS_SHIFT)
833 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
834 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
835 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
837 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
838 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
840 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
841 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
842 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
844 enum i40e_rx_desc_fltstat_values {
845 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
846 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
847 I40E_RX_DESC_FLTSTAT_RSV = 2,
848 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
851 #define I40E_RXD_PACKET_TYPE_UNICAST 0
852 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
853 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
854 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
856 #define I40E_RXD_QW1_ERROR_SHIFT 19
857 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
859 enum i40e_rx_desc_error_bits {
860 /* Note: These are predefined bit offsets */
861 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
862 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
863 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
864 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
865 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
866 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
867 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
868 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
869 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
872 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
873 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
874 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
875 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
876 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
877 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
880 #define I40E_RXD_QW1_PTYPE_SHIFT 30
881 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
883 /* Packet type non-ip values */
884 enum i40e_rx_l2_ptype {
885 I40E_RX_PTYPE_L2_RESERVED = 0,
886 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
887 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
888 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
889 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
890 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
891 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
892 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
893 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
894 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
895 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
896 I40E_RX_PTYPE_L2_ARP = 11,
897 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
898 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
899 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
900 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
901 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
902 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
903 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
904 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
905 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
906 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
907 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
908 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
909 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
910 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
913 struct i40e_rx_ptype_decoded {
920 u32 tunnel_end_prot:2;
921 u32 tunnel_end_frag:1;
926 enum i40e_rx_ptype_outer_ip {
927 I40E_RX_PTYPE_OUTER_L2 = 0,
928 I40E_RX_PTYPE_OUTER_IP = 1
931 enum i40e_rx_ptype_outer_ip_ver {
932 I40E_RX_PTYPE_OUTER_NONE = 0,
933 I40E_RX_PTYPE_OUTER_IPV4 = 0,
934 I40E_RX_PTYPE_OUTER_IPV6 = 1
937 enum i40e_rx_ptype_outer_fragmented {
938 I40E_RX_PTYPE_NOT_FRAG = 0,
939 I40E_RX_PTYPE_FRAG = 1
942 enum i40e_rx_ptype_tunnel_type {
943 I40E_RX_PTYPE_TUNNEL_NONE = 0,
944 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
945 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
946 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
947 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
950 enum i40e_rx_ptype_tunnel_end_prot {
951 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
952 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
953 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
956 enum i40e_rx_ptype_inner_prot {
957 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
958 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
959 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
960 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
961 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
962 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
965 enum i40e_rx_ptype_payload_layer {
966 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
967 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
968 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
969 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
972 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
973 #define I40E_RX_PTYPE_SHIFT 56
975 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
976 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
977 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
979 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
980 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
981 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
983 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
984 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
986 #define I40E_RXD_QW1_NEXTP_SHIFT 38
987 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
989 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
990 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
991 I40E_RXD_QW2_EXT_STATUS_SHIFT)
993 enum i40e_rx_desc_ext_status_bits {
994 /* Note: These are predefined bit offsets */
995 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
996 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
997 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
998 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
999 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1000 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1001 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1004 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1005 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1007 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1008 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1010 enum i40e_rx_desc_pe_status_bits {
1011 /* Note: These are predefined bit offsets */
1012 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1013 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1014 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1015 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1016 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1017 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1018 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1019 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1020 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1023 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1024 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1026 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1027 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1028 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1030 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1031 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1032 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1034 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1035 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1036 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1038 enum i40e_rx_prog_status_desc_status_bits {
1039 /* Note: These are predefined bit offsets */
1040 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1041 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1044 enum i40e_rx_prog_status_desc_prog_id_masks {
1045 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1046 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1047 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1050 enum i40e_rx_prog_status_desc_error_bits {
1051 /* Note: These are predefined bit offsets */
1052 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1053 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1054 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1055 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1058 #define I40E_TWO_BIT_MASK 0x3
1059 #define I40E_THREE_BIT_MASK 0x7
1060 #define I40E_FOUR_BIT_MASK 0xF
1061 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1064 struct i40e_tx_desc {
1065 __le64 buffer_addr; /* Address of descriptor's data buf */
1066 __le64 cmd_type_offset_bsz;
1069 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1070 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1072 enum i40e_tx_desc_dtype_value {
1073 I40E_TX_DESC_DTYPE_DATA = 0x0,
1074 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1075 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1076 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1077 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1078 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1079 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1080 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1081 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1082 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1085 #define I40E_TXD_QW1_CMD_SHIFT 4
1086 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1088 enum i40e_tx_desc_cmd_bits {
1089 I40E_TX_DESC_CMD_EOP = 0x0001,
1090 I40E_TX_DESC_CMD_RS = 0x0002,
1091 I40E_TX_DESC_CMD_ICRC = 0x0004,
1092 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1093 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1094 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1095 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1096 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1097 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1098 I40E_TX_DESC_CMD_FCOET = 0x0080,
1099 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1100 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1101 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1102 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1103 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1104 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1105 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1106 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1109 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1110 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1111 I40E_TXD_QW1_OFFSET_SHIFT)
1113 enum i40e_tx_desc_length_fields {
1114 /* Note: These are predefined bit offsets */
1115 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1116 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1117 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1120 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1121 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1122 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1123 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1125 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1126 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1127 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1129 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1130 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1132 /* Context descriptors */
1133 struct i40e_tx_context_desc {
1134 __le32 tunneling_params;
1137 __le64 type_cmd_tso_mss;
1140 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1141 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1143 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1144 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1146 enum i40e_tx_ctx_desc_cmd_bits {
1147 I40E_TX_CTX_DESC_TSO = 0x01,
1148 I40E_TX_CTX_DESC_TSYN = 0x02,
1149 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1150 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1151 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1152 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1153 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1154 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1155 I40E_TX_CTX_DESC_SWPE = 0x40
1158 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1159 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1160 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1162 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1163 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1164 I40E_TXD_CTX_QW1_MSS_SHIFT)
1166 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1167 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1169 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1170 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1171 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1173 enum i40e_tx_ctx_desc_eipt_offload {
1174 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1175 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1176 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1177 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1180 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1181 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1182 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1184 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1185 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1187 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1188 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1190 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1191 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1193 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1195 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1196 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1197 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1199 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1200 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1201 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1203 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1204 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1205 struct i40e_nop_desc {
1210 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1211 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1213 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1214 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1216 enum i40e_tx_nop_desc_cmd_bits {
1217 /* Note: These are predefined bit offsets */
1218 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1219 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1220 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1223 struct i40e_filter_program_desc {
1224 __le32 qindex_flex_ptype_vsi;
1226 __le32 dtype_cmd_cntindex;
1229 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1230 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1231 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1232 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1233 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1234 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1235 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1236 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1237 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1239 /* Packet Classifier Types for filters */
1240 enum i40e_filter_pctype {
1241 /* Note: Values 0-28 are reserved for future use.
1242 * Value 29, 30, 32 are not supported on XL710 and X710.
1244 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1245 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1246 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1247 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1248 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1249 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1250 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1251 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1252 /* Note: Values 37-38 are reserved for future use.
1253 * Value 39, 40, 42 are not supported on XL710 and X710.
1255 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1256 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1257 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1258 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1259 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1260 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1261 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1262 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1263 /* Note: Value 47 is reserved for future use */
1264 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1265 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1266 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1267 /* Note: Values 51-62 are reserved for future use */
1268 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1271 enum i40e_filter_program_desc_dest {
1272 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1273 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1274 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1277 enum i40e_filter_program_desc_fd_status {
1278 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1279 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1280 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1281 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1284 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1285 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1286 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1288 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1289 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1291 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1292 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1293 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1295 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1296 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1298 enum i40e_filter_program_desc_pcmd {
1299 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1300 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1303 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1304 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1306 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1307 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1309 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1310 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1311 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1312 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1314 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1315 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1316 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1318 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1319 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1320 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1322 enum i40e_filter_type {
1323 I40E_FLOW_DIRECTOR_FLTR = 0,
1324 I40E_PE_QUAD_HASH_FLTR = 1,
1325 I40E_ETHERTYPE_FLTR,
1331 struct i40e_vsi_context {
1336 u16 vsis_unallocated;
1341 struct i40e_aqc_vsi_properties_data info;
1344 struct i40e_veb_context {
1349 u16 vebs_unallocated;
1351 struct i40e_aqc_get_veb_parameters_completion info;
1354 /* Statistics collected by each port, VSI, VEB, and S-channel */
1355 struct i40e_eth_stats {
1356 u64 rx_bytes; /* gorc */
1357 u64 rx_unicast; /* uprc */
1358 u64 rx_multicast; /* mprc */
1359 u64 rx_broadcast; /* bprc */
1360 u64 rx_discards; /* rdpc */
1361 u64 rx_unknown_protocol; /* rupp */
1362 u64 tx_bytes; /* gotc */
1363 u64 tx_unicast; /* uptc */
1364 u64 tx_multicast; /* mptc */
1365 u64 tx_broadcast; /* bptc */
1366 u64 tx_discards; /* tdpc */
1367 u64 tx_errors; /* tepc */
1370 /* Statistics collected per VEB per TC */
1371 struct i40e_veb_tc_stats {
1372 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1373 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1374 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1375 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1378 /* Statistics collected per function for FCoE */
1379 struct i40e_fcoe_stats {
1380 u64 rx_fcoe_packets; /* fcoeprc */
1381 u64 rx_fcoe_dwords; /* focedwrc */
1382 u64 rx_fcoe_dropped; /* fcoerpdc */
1383 u64 tx_fcoe_packets; /* fcoeptc */
1384 u64 tx_fcoe_dwords; /* focedwtc */
1385 u64 fcoe_bad_fccrc; /* fcoecrc */
1386 u64 fcoe_last_error; /* fcoelast */
1387 u64 fcoe_ddp_count; /* fcoeddpc */
1390 /* offset to per function FCoE statistics block */
1391 #define I40E_FCOE_VF_STAT_OFFSET 0
1392 #define I40E_FCOE_PF_STAT_OFFSET 128
1393 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1395 /* Statistics collected by the MAC */
1396 struct i40e_hw_port_stats {
1397 /* eth stats collected by the port */
1398 struct i40e_eth_stats eth;
1400 /* additional port specific stats */
1401 u64 tx_dropped_link_down; /* tdold */
1402 u64 crc_errors; /* crcerrs */
1403 u64 illegal_bytes; /* illerrc */
1404 u64 error_bytes; /* errbc */
1405 u64 mac_local_faults; /* mlfc */
1406 u64 mac_remote_faults; /* mrfc */
1407 u64 rx_length_errors; /* rlec */
1408 u64 link_xon_rx; /* lxonrxc */
1409 u64 link_xoff_rx; /* lxoffrxc */
1410 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1411 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1412 u64 link_xon_tx; /* lxontxc */
1413 u64 link_xoff_tx; /* lxofftxc */
1414 u64 priority_xon_tx[8]; /* pxontxc[8] */
1415 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1416 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1417 u64 rx_size_64; /* prc64 */
1418 u64 rx_size_127; /* prc127 */
1419 u64 rx_size_255; /* prc255 */
1420 u64 rx_size_511; /* prc511 */
1421 u64 rx_size_1023; /* prc1023 */
1422 u64 rx_size_1522; /* prc1522 */
1423 u64 rx_size_big; /* prc9522 */
1424 u64 rx_undersize; /* ruc */
1425 u64 rx_fragments; /* rfc */
1426 u64 rx_oversize; /* roc */
1427 u64 rx_jabber; /* rjc */
1428 u64 tx_size_64; /* ptc64 */
1429 u64 tx_size_127; /* ptc127 */
1430 u64 tx_size_255; /* ptc255 */
1431 u64 tx_size_511; /* ptc511 */
1432 u64 tx_size_1023; /* ptc1023 */
1433 u64 tx_size_1522; /* ptc1522 */
1434 u64 tx_size_big; /* ptc9522 */
1435 u64 mac_short_packet_dropped; /* mspdc */
1436 u64 checksum_error; /* xec */
1437 /* flow director stats */
1440 u64 fd_atr_tunnel_match;
1446 u64 tx_lpi_count; /* etlpic */
1447 u64 rx_lpi_count; /* erlpic */
1450 /* Checksum and Shadow RAM pointers */
1451 #define I40E_SR_NVM_CONTROL_WORD 0x00
1452 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1453 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1454 #define I40E_SR_OPTION_ROM_PTR 0x05
1455 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1456 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1457 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1458 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1459 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1460 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1461 #define I40E_SR_PE_IMAGE_PTR 0x0C
1462 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1463 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1464 #define I40E_SR_EMP_MODULE_PTR 0x0F
1465 #define I40E_SR_PBA_FLAGS 0x15
1466 #define I40E_SR_PBA_BLOCK_PTR 0x16
1467 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1468 #define I40E_NVM_OEM_VER_OFF 0x83
1469 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1470 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1471 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1472 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1473 #define I40E_SR_NVM_MAP_VERSION 0x29
1474 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1475 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1476 #define I40E_SR_NVM_EETRACK_LO 0x2D
1477 #define I40E_SR_NVM_EETRACK_HI 0x2E
1478 #define I40E_SR_VPD_PTR 0x2F
1479 #define I40E_SR_PXE_SETUP_PTR 0x30
1480 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1481 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1482 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1483 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1484 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1485 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1486 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1487 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1488 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1489 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1490 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1491 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1492 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1493 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1494 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1495 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1496 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1497 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1498 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1500 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1501 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1502 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1503 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1504 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1506 /* Shadow RAM related */
1507 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1508 #define I40E_SR_BUF_ALIGNMENT 4096
1509 #define I40E_SR_WORDS_IN_1KB 512
1510 /* Checksum should be calculated such that after adding all the words,
1511 * including the checksum word itself, the sum should be 0xBABA.
1513 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1515 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1517 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1519 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1520 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1521 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1522 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1523 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1524 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1525 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1526 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1527 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1528 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1529 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1530 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1531 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1532 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1535 /* FCoE DIF/DIX Context descriptor */
1536 struct i40e_fcoe_difdix_context_desc {
1537 __le64 flags_buff0_buff1_ref;
1538 __le64 difapp_msk_bias;
1541 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1542 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1543 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1545 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1547 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1549 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1551 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1553 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1555 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1557 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1559 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1561 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1563 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1565 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1567 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1569 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1571 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1573 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1575 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1577 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1579 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1581 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1583 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1585 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1587 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1590 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1591 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1592 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1594 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1595 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1596 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1598 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1599 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1600 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1602 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1603 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1604 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1606 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1607 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1608 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1610 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1611 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1612 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1614 /* FCoE DIF/DIX Buffers descriptor */
1615 struct i40e_fcoe_difdix_buffers_desc {
1620 /* FCoE DDP Context descriptor */
1621 struct i40e_fcoe_ddp_context_desc {
1623 __le64 type_cmd_foff_lsize;
1626 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1627 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1628 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1630 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1631 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1632 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1634 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1635 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1636 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1637 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1638 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1639 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1640 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1643 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1644 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1645 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1647 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1648 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1649 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1651 /* FCoE DDP/DWO Queue Context descriptor */
1652 struct i40e_fcoe_queue_context_desc {
1653 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1654 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1657 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1658 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1659 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1661 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1662 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1663 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1665 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1666 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1667 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1669 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1670 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1671 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1673 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1674 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1675 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1678 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1679 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1680 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1682 /* FCoE DDP/DWO Filter Context descriptor */
1683 struct i40e_fcoe_filter_context_desc {
1687 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1688 __le16 rsvd_dmaindx;
1690 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1691 __le64 flags_rsvd_lanq;
1694 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1695 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1696 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1698 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1699 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1700 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1701 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1702 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1703 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1704 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1707 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1708 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1709 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1711 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1712 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1713 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1715 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1716 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1717 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1719 enum i40e_switch_element_types {
1720 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1721 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1722 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1723 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1724 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1725 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1726 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1727 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1728 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1731 /* Supported EtherType filters */
1732 enum i40e_ether_type_index {
1733 I40E_ETHER_TYPE_1588 = 0,
1734 I40E_ETHER_TYPE_FIP = 1,
1735 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1736 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1737 I40E_ETHER_TYPE_LLDP = 4,
1738 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1739 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1740 I40E_ETHER_TYPE_QCN_CNM = 7,
1741 I40E_ETHER_TYPE_8021X = 8,
1742 I40E_ETHER_TYPE_ARP = 9,
1743 I40E_ETHER_TYPE_RSV1 = 10,
1744 I40E_ETHER_TYPE_RSV2 = 11,
1747 /* Filter context base size is 1K */
1748 #define I40E_HASH_FILTER_BASE_SIZE 1024
1749 /* Supported Hash filter values */
1750 enum i40e_hash_filter_size {
1751 I40E_HASH_FILTER_SIZE_1K = 0,
1752 I40E_HASH_FILTER_SIZE_2K = 1,
1753 I40E_HASH_FILTER_SIZE_4K = 2,
1754 I40E_HASH_FILTER_SIZE_8K = 3,
1755 I40E_HASH_FILTER_SIZE_16K = 4,
1756 I40E_HASH_FILTER_SIZE_32K = 5,
1757 I40E_HASH_FILTER_SIZE_64K = 6,
1758 I40E_HASH_FILTER_SIZE_128K = 7,
1759 I40E_HASH_FILTER_SIZE_256K = 8,
1760 I40E_HASH_FILTER_SIZE_512K = 9,
1761 I40E_HASH_FILTER_SIZE_1M = 10,
1764 /* DMA context base size is 0.5K */
1765 #define I40E_DMA_CNTX_BASE_SIZE 512
1766 /* Supported DMA context values */
1767 enum i40e_dma_cntx_size {
1768 I40E_DMA_CNTX_SIZE_512 = 0,
1769 I40E_DMA_CNTX_SIZE_1K = 1,
1770 I40E_DMA_CNTX_SIZE_2K = 2,
1771 I40E_DMA_CNTX_SIZE_4K = 3,
1772 I40E_DMA_CNTX_SIZE_8K = 4,
1773 I40E_DMA_CNTX_SIZE_16K = 5,
1774 I40E_DMA_CNTX_SIZE_32K = 6,
1775 I40E_DMA_CNTX_SIZE_64K = 7,
1776 I40E_DMA_CNTX_SIZE_128K = 8,
1777 I40E_DMA_CNTX_SIZE_256K = 9,
1780 /* Supported Hash look up table (LUT) sizes */
1781 enum i40e_hash_lut_size {
1782 I40E_HASH_LUT_SIZE_128 = 0,
1783 I40E_HASH_LUT_SIZE_512 = 1,
1786 /* Structure to hold a per PF filter control settings */
1787 struct i40e_filter_control_settings {
1788 /* number of PE Quad Hash filter buckets */
1789 enum i40e_hash_filter_size pe_filt_num;
1790 /* number of PE Quad Hash contexts */
1791 enum i40e_dma_cntx_size pe_cntx_num;
1792 /* number of FCoE filter buckets */
1793 enum i40e_hash_filter_size fcoe_filt_num;
1794 /* number of FCoE DDP contexts */
1795 enum i40e_dma_cntx_size fcoe_cntx_num;
1796 /* size of the Hash LUT */
1797 enum i40e_hash_lut_size hash_lut_size;
1798 /* enable FDIR filters for PF and its VFs */
1800 /* enable Ethertype filters for PF and its VFs */
1801 bool enable_ethtype;
1802 /* enable MAC/VLAN filters for PF and its VFs */
1803 bool enable_macvlan;
1806 /* Structure to hold device level control filter counts */
1807 struct i40e_control_filter_stats {
1808 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1809 u16 etype_used; /* Used perfect EtherType filters */
1810 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1811 u16 etype_free; /* Un-used perfect EtherType filters */
1814 enum i40e_reset_type {
1816 I40E_RESET_CORER = 1,
1817 I40E_RESET_GLOBR = 2,
1818 I40E_RESET_EMPR = 3,
1821 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1822 #define I40E_NVM_LLDP_CFG_PTR 0xD
1823 struct i40e_lldp_variables {
1833 /* Offsets into Alternate Ram */
1834 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1835 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1836 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1837 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1838 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1839 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1841 /* Alternate Ram Bandwidth Masks */
1842 #define I40E_ALT_BW_VALUE_MASK 0xFF
1843 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1844 #define I40E_ALT_BW_VALID_MASK 0x80000000
1846 /* RSS Hash Table Size */
1847 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1849 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1850 #define I40E_L3_SRC_SHIFT 47
1851 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1852 #define I40E_L3_V6_SRC_SHIFT 43
1853 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1854 #define I40E_L3_DST_SHIFT 35
1855 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1856 #define I40E_L3_V6_DST_SHIFT 35
1857 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1858 #define I40E_L4_SRC_SHIFT 34
1859 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1860 #define I40E_L4_DST_SHIFT 33
1861 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1862 #define I40E_VERIFY_TAG_SHIFT 31
1863 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1865 #define I40E_FLEX_50_SHIFT 13
1866 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1867 #define I40E_FLEX_51_SHIFT 12
1868 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1869 #define I40E_FLEX_52_SHIFT 11
1870 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1871 #define I40E_FLEX_53_SHIFT 10
1872 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1873 #define I40E_FLEX_54_SHIFT 9
1874 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1875 #define I40E_FLEX_55_SHIFT 8
1876 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1877 #define I40E_FLEX_56_SHIFT 7
1878 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1879 #define I40E_FLEX_57_SHIFT 6
1880 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1881 #endif /* _I40E_TYPE_H_ */