1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
160 #define I40E_MDIO_STCODE 0
161 #define I40E_MDIO_OPCODE_ADDRESS 0
162 #define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \
163 I40E_GLGEN_MSCA_OPCODE_SHIFT)
164 #define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
165 I40E_GLGEN_MSCA_OPCODE_SHIFT)
166 #define I40E_MDIO_OPCODE_READ I40E_MASK(3, \
167 I40E_GLGEN_MSCA_OPCODE_SHIFT)
169 #define I40E_PHY_COM_REG_PAGE 0x1E
170 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
171 #define I40E_PHY_LED_MANUAL_ON 0x100
172 #define I40E_PHY_LED_PROV_REG_1 0xC430
173 #define I40E_PHY_LED_MODE_MASK 0xFFFF
174 #define I40E_PHY_LED_MODE_ORIG 0x80000000
177 enum i40e_memset_type {
183 enum i40e_memcpy_type {
184 I40E_NONDMA_TO_NONDMA = 0,
191 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
193 #define I40E_FW_API_VERSION_MINOR_X710 0x0005
196 /* These are structs for managing the hardware information and the operations.
197 * The structures of function pointers are filled out at init time when we
198 * know for sure exactly which hardware we're working with. This gives us the
199 * flexibility of using the same main driver code but adapting to slightly
200 * different hardware needs as new parts are developed. For this architecture,
201 * the Firmware and AdminQ are intended to insulate the driver from most of the
202 * future changes, but these structures will also do part of the job.
205 I40E_MAC_UNKNOWN = 0,
216 enum i40e_media_type {
217 I40E_MEDIA_TYPE_UNKNOWN = 0,
218 I40E_MEDIA_TYPE_FIBER,
219 I40E_MEDIA_TYPE_BASET,
220 I40E_MEDIA_TYPE_BACKPLANE,
223 I40E_MEDIA_TYPE_VIRTUAL
235 enum i40e_set_fc_aq_failures {
236 I40E_SET_FC_AQ_FAIL_NONE = 0,
237 I40E_SET_FC_AQ_FAIL_GET = 1,
238 I40E_SET_FC_AQ_FAIL_SET = 2,
239 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
240 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
252 I40E_VSI_TYPE_UNKNOWN
255 enum i40e_queue_type {
256 I40E_QUEUE_TYPE_RX = 0,
258 I40E_QUEUE_TYPE_PE_CEQ,
259 I40E_QUEUE_TYPE_UNKNOWN
262 struct i40e_link_status {
263 enum i40e_aq_phy_type phy_type;
264 enum i40e_aq_link_speed link_speed;
269 /* is Link Status Event notification to SW enabled */
276 /* 1st byte: module identifier */
277 #define I40E_MODULE_TYPE_SFP 0x03
278 #define I40E_MODULE_TYPE_QSFP 0x0D
279 /* 2nd byte: ethernet compliance codes for 10/40G */
280 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
281 #define I40E_MODULE_TYPE_40G_LR4 0x02
282 #define I40E_MODULE_TYPE_40G_SR4 0x04
283 #define I40E_MODULE_TYPE_40G_CR4 0x08
284 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
285 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
286 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
287 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
288 /* 3rd byte: ethernet compliance codes for 1G */
289 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
290 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
291 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
292 #define I40E_MODULE_TYPE_1000BASE_T 0x08
295 struct i40e_phy_info {
296 struct i40e_link_status link_info;
297 struct i40e_link_status link_info_old;
299 enum i40e_media_type media_type;
300 /* all the phy types the NVM is capable of */
304 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
305 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
306 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
307 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
308 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
309 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
310 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
311 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
312 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
313 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
314 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
315 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
316 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
317 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
318 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
319 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
320 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
321 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
322 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
323 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
325 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
326 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
327 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
328 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
329 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
330 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
331 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
332 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
333 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)
334 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)
335 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)
336 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)
337 #define I40E_HW_CAP_MAX_GPIO 30
338 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
339 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
342 enum i40e_acpi_programming_method {
343 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
344 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
347 #define I40E_WOL_SUPPORT_MASK 1
348 #define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1)
349 #define I40E_PROXY_SUPPORT_MASK (1 << 2)
352 /* Capabilities of a PF or a VF or the whole device */
353 struct i40e_hw_capabilities {
355 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
356 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
357 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
365 bool evb_802_1_qbg; /* Edge Virtual Bridging */
366 bool evb_802_1_qbh; /* Bridge Port Extension */
369 bool iscsi; /* Indicates iSCSI enabled */
373 #define I40E_FLEX10_MODE_UNKNOWN 0x0
374 #define I40E_FLEX10_MODE_DCC 0x1
375 #define I40E_FLEX10_MODE_DCI 0x2
378 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
379 #define I40E_FLEX10_STATUS_VC_MODE 0x2
381 bool sec_rev_disabled;
382 bool update_disabled;
383 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
384 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
390 u32 fd_filters_guaranteed;
391 u32 fd_filters_best_effort;
394 u32 rss_table_entry_width;
395 bool led[I40E_HW_CAP_MAX_GPIO];
396 bool sdp[I40E_HW_CAP_MAX_GPIO];
398 u32 num_flow_director_filters;
405 u32 num_msix_vectors;
406 u32 num_msix_vectors_vf;
416 bool apm_wol_support;
417 enum i40e_acpi_programming_method acpi_prog_method;
422 struct i40e_mac_info {
423 enum i40e_mac_type type;
424 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
425 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
426 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
427 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
431 enum i40e_aq_resources_ids {
432 I40E_NVM_RESOURCE_ID = 1
435 enum i40e_aq_resource_access_type {
436 I40E_RESOURCE_READ = 1,
440 struct i40e_nvm_info {
441 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
442 u32 timeout; /* [ms] */
443 u16 sr_size; /* Shadow RAM size in words */
444 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
445 u16 version; /* NVM package version */
446 u32 eetrack; /* NVM data version */
447 u32 oem_ver; /* OEM version info */
450 /* definitions used in NVM update support */
452 enum i40e_nvmupd_cmd {
454 I40E_NVMUPD_READ_CON,
455 I40E_NVMUPD_READ_SNT,
456 I40E_NVMUPD_READ_LCB,
458 I40E_NVMUPD_WRITE_ERA,
459 I40E_NVMUPD_WRITE_CON,
460 I40E_NVMUPD_WRITE_SNT,
461 I40E_NVMUPD_WRITE_LCB,
462 I40E_NVMUPD_WRITE_SA,
463 I40E_NVMUPD_CSUM_CON,
465 I40E_NVMUPD_CSUM_LCB,
468 I40E_NVMUPD_GET_AQ_RESULT,
471 enum i40e_nvmupd_state {
472 I40E_NVMUPD_STATE_INIT,
473 I40E_NVMUPD_STATE_READING,
474 I40E_NVMUPD_STATE_WRITING,
475 I40E_NVMUPD_STATE_INIT_WAIT,
476 I40E_NVMUPD_STATE_WRITE_WAIT,
479 /* nvm_access definition and its masks/shifts need to be accessible to
480 * application, core driver, and shared code. Where is the right file?
482 #define I40E_NVM_READ 0xB
483 #define I40E_NVM_WRITE 0xC
485 #define I40E_NVM_MOD_PNT_MASK 0xFF
487 #define I40E_NVM_TRANS_SHIFT 8
488 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
489 #define I40E_NVM_CON 0x0
490 #define I40E_NVM_SNT 0x1
491 #define I40E_NVM_LCB 0x2
492 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
493 #define I40E_NVM_ERA 0x4
494 #define I40E_NVM_CSUM 0x8
495 #define I40E_NVM_EXEC 0xf
497 #define I40E_NVM_ADAPT_SHIFT 16
498 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
500 #define I40E_NVMUPD_MAX_DATA 4096
501 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
503 struct i40e_nvm_access {
506 u32 offset; /* in bytes */
507 u32 data_size; /* in bytes */
513 i40e_bus_type_unknown = 0,
516 i40e_bus_type_pci_express,
517 i40e_bus_type_reserved
521 enum i40e_bus_speed {
522 i40e_bus_speed_unknown = 0,
523 i40e_bus_speed_33 = 33,
524 i40e_bus_speed_66 = 66,
525 i40e_bus_speed_100 = 100,
526 i40e_bus_speed_120 = 120,
527 i40e_bus_speed_133 = 133,
528 i40e_bus_speed_2500 = 2500,
529 i40e_bus_speed_5000 = 5000,
530 i40e_bus_speed_8000 = 8000,
531 i40e_bus_speed_reserved
535 enum i40e_bus_width {
536 i40e_bus_width_unknown = 0,
537 i40e_bus_width_pcie_x1 = 1,
538 i40e_bus_width_pcie_x2 = 2,
539 i40e_bus_width_pcie_x4 = 4,
540 i40e_bus_width_pcie_x8 = 8,
541 i40e_bus_width_32 = 32,
542 i40e_bus_width_64 = 64,
543 i40e_bus_width_reserved
547 struct i40e_bus_info {
548 enum i40e_bus_speed speed;
549 enum i40e_bus_width width;
550 enum i40e_bus_type type;
557 /* Flow control (FC) parameters */
558 struct i40e_fc_info {
559 enum i40e_fc_mode current_mode; /* FC mode in effect */
560 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
563 #define I40E_MAX_TRAFFIC_CLASS 8
564 #define I40E_MAX_USER_PRIORITY 8
565 #define I40E_DCBX_MAX_APPS 32
566 #define I40E_LLDPDU_SIZE 1500
567 #define I40E_TLV_STATUS_OPER 0x1
568 #define I40E_TLV_STATUS_SYNC 0x2
569 #define I40E_TLV_STATUS_ERR 0x4
570 #define I40E_CEE_OPER_MAX_APPS 3
571 #define I40E_APP_PROTOID_FCOE 0x8906
572 #define I40E_APP_PROTOID_ISCSI 0x0cbc
573 #define I40E_APP_PROTOID_FIP 0x8914
574 #define I40E_APP_SEL_ETHTYPE 0x1
575 #define I40E_APP_SEL_TCPIP 0x2
576 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
577 #define I40E_CEE_APP_SEL_TCPIP 0x1
579 /* CEE or IEEE 802.1Qaz ETS Configuration data */
580 struct i40e_dcb_ets_config {
584 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
585 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
586 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
589 /* CEE or IEEE 802.1Qaz PFC Configuration data */
590 struct i40e_dcb_pfc_config {
597 /* CEE or IEEE 802.1Qaz Application Priority data */
598 struct i40e_dcb_app_priority_table {
604 struct i40e_dcbx_config {
606 #define I40E_DCBX_MODE_CEE 0x1
607 #define I40E_DCBX_MODE_IEEE 0x2
609 #define I40E_DCBX_APPS_NON_WILLING 0x1
611 u32 tlv_status; /* CEE mode TLV status */
612 struct i40e_dcb_ets_config etscfg;
613 struct i40e_dcb_ets_config etsrec;
614 struct i40e_dcb_pfc_config pfc;
615 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
618 /* Port hardware description */
623 /* subsystem structs */
624 struct i40e_phy_info phy;
625 struct i40e_mac_info mac;
626 struct i40e_bus_info bus;
627 struct i40e_nvm_info nvm;
628 struct i40e_fc_info fc;
633 u16 subsystem_device_id;
634 u16 subsystem_vendor_id;
637 bool adapter_stopped;
639 /* capabilities for entire device and PCI func */
640 struct i40e_hw_capabilities dev_caps;
641 struct i40e_hw_capabilities func_caps;
643 /* Flow Director shared filter space */
644 u16 fdir_shared_filter_count;
646 /* device profile info */
650 /* for multi-function MACs */
655 /* Closest numa node to the device */
658 /* Admin Queue info */
659 struct i40e_adminq_info aq;
661 /* state of nvm update process */
662 enum i40e_nvmupd_state nvmupd_state;
663 struct i40e_aq_desc nvm_wb_desc;
664 struct i40e_virt_mem nvm_buff;
665 bool nvm_release_on_done;
669 struct i40e_hmc_info hmc; /* HMC info struct */
671 /* LLDP/DCBX Status */
675 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
676 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
677 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
680 /* WoL and proxy support */
681 u16 num_wol_proxy_filters;
682 u16 wol_proxy_vsi_seid;
685 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
690 #ifndef I40E_NDIS_SUPPORT
692 #endif /* I40E_NDIS_SUPPORT */
695 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
698 return (hw->mac.type == I40E_MAC_VF ||
699 hw->mac.type == I40E_MAC_X722_VF);
701 return hw->mac.type == I40E_MAC_VF;
705 struct i40e_driver_version {
710 u8 driver_string[32];
714 union i40e_16byte_rx_desc {
716 __le64 pkt_addr; /* Packet buffer address */
717 __le64 hdr_addr; /* Header buffer address */
723 __le16 mirroring_status;
729 __le32 rss; /* RSS Hash */
730 __le32 fd_id; /* Flow director filter id */
731 __le32 fcoe_param; /* FCoE DDP Context id */
735 /* ext status/error/pktype/length */
736 __le64 status_error_len;
738 } wb; /* writeback */
741 union i40e_32byte_rx_desc {
743 __le64 pkt_addr; /* Packet buffer address */
744 __le64 hdr_addr; /* Header buffer address */
745 /* bit 0 of hdr_buffer_addr is DD bit */
753 __le16 mirroring_status;
759 __le32 rss; /* RSS Hash */
760 __le32 fcoe_param; /* FCoE DDP Context id */
761 /* Flow director filter id in case of
762 * Programming status desc WB
768 /* status/error/pktype/length */
769 __le64 status_error_len;
772 __le16 ext_status; /* extended status */
779 __le32 flex_bytes_lo;
783 __le32 flex_bytes_hi;
787 } wb; /* writeback */
790 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
791 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
792 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
793 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
794 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
795 I40E_RXD_QW0_FCOEINDX_SHIFT)
797 enum i40e_rx_desc_status_bits {
798 /* Note: These are predefined bit offsets */
799 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
800 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
801 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
802 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
803 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
804 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
805 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
807 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
809 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
812 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
813 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
814 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
815 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
816 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
817 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
819 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
821 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
823 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
826 #define I40E_RXD_QW1_STATUS_SHIFT 0
827 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
828 I40E_RXD_QW1_STATUS_SHIFT)
830 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
831 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
832 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
834 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
835 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
837 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
838 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
839 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
841 enum i40e_rx_desc_fltstat_values {
842 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
843 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
844 I40E_RX_DESC_FLTSTAT_RSV = 2,
845 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
848 #define I40E_RXD_PACKET_TYPE_UNICAST 0
849 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
850 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
851 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
853 #define I40E_RXD_QW1_ERROR_SHIFT 19
854 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
856 enum i40e_rx_desc_error_bits {
857 /* Note: These are predefined bit offsets */
858 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
859 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
860 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
861 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
862 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
863 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
864 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
865 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
866 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
869 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
870 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
871 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
872 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
873 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
874 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
877 #define I40E_RXD_QW1_PTYPE_SHIFT 30
878 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
880 /* Packet type non-ip values */
881 enum i40e_rx_l2_ptype {
882 I40E_RX_PTYPE_L2_RESERVED = 0,
883 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
884 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
885 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
886 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
887 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
888 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
889 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
890 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
891 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
892 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
893 I40E_RX_PTYPE_L2_ARP = 11,
894 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
895 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
896 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
897 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
898 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
899 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
900 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
901 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
902 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
903 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
904 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
905 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
906 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
907 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
910 struct i40e_rx_ptype_decoded {
917 u32 tunnel_end_prot:2;
918 u32 tunnel_end_frag:1;
923 enum i40e_rx_ptype_outer_ip {
924 I40E_RX_PTYPE_OUTER_L2 = 0,
925 I40E_RX_PTYPE_OUTER_IP = 1
928 enum i40e_rx_ptype_outer_ip_ver {
929 I40E_RX_PTYPE_OUTER_NONE = 0,
930 I40E_RX_PTYPE_OUTER_IPV4 = 0,
931 I40E_RX_PTYPE_OUTER_IPV6 = 1
934 enum i40e_rx_ptype_outer_fragmented {
935 I40E_RX_PTYPE_NOT_FRAG = 0,
936 I40E_RX_PTYPE_FRAG = 1
939 enum i40e_rx_ptype_tunnel_type {
940 I40E_RX_PTYPE_TUNNEL_NONE = 0,
941 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
942 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
943 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
944 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
947 enum i40e_rx_ptype_tunnel_end_prot {
948 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
949 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
950 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
953 enum i40e_rx_ptype_inner_prot {
954 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
955 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
956 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
957 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
958 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
959 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
962 enum i40e_rx_ptype_payload_layer {
963 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
964 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
965 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
966 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
969 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
970 #define I40E_RX_PTYPE_SHIFT 56
972 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
973 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
974 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
976 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
977 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
978 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
980 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
981 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
983 #define I40E_RXD_QW1_NEXTP_SHIFT 38
984 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
986 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
987 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
988 I40E_RXD_QW2_EXT_STATUS_SHIFT)
990 enum i40e_rx_desc_ext_status_bits {
991 /* Note: These are predefined bit offsets */
992 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
993 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
994 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
995 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
996 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
997 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
998 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1001 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1002 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1004 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1005 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1007 enum i40e_rx_desc_pe_status_bits {
1008 /* Note: These are predefined bit offsets */
1009 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1010 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1011 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1012 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1013 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1014 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1015 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1016 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1017 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1020 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1021 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1023 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1024 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1025 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1027 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1028 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1029 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1031 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1032 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1033 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1035 enum i40e_rx_prog_status_desc_status_bits {
1036 /* Note: These are predefined bit offsets */
1037 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1038 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1041 enum i40e_rx_prog_status_desc_prog_id_masks {
1042 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1043 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1044 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1047 enum i40e_rx_prog_status_desc_error_bits {
1048 /* Note: These are predefined bit offsets */
1049 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1050 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1051 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1052 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1055 #define I40E_TWO_BIT_MASK 0x3
1056 #define I40E_THREE_BIT_MASK 0x7
1057 #define I40E_FOUR_BIT_MASK 0xF
1058 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1061 struct i40e_tx_desc {
1062 __le64 buffer_addr; /* Address of descriptor's data buf */
1063 __le64 cmd_type_offset_bsz;
1066 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1067 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1069 enum i40e_tx_desc_dtype_value {
1070 I40E_TX_DESC_DTYPE_DATA = 0x0,
1071 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1072 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1073 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1074 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1075 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1076 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1077 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1078 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1079 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1082 #define I40E_TXD_QW1_CMD_SHIFT 4
1083 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1085 enum i40e_tx_desc_cmd_bits {
1086 I40E_TX_DESC_CMD_EOP = 0x0001,
1087 I40E_TX_DESC_CMD_RS = 0x0002,
1088 I40E_TX_DESC_CMD_ICRC = 0x0004,
1089 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1090 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1091 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1092 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1093 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1094 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1095 I40E_TX_DESC_CMD_FCOET = 0x0080,
1096 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1097 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1098 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1099 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1100 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1101 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1102 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1103 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1106 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1107 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1108 I40E_TXD_QW1_OFFSET_SHIFT)
1110 enum i40e_tx_desc_length_fields {
1111 /* Note: These are predefined bit offsets */
1112 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1113 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1114 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1117 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1118 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1119 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1120 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1122 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1123 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1124 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1126 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1127 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1129 /* Context descriptors */
1130 struct i40e_tx_context_desc {
1131 __le32 tunneling_params;
1134 __le64 type_cmd_tso_mss;
1137 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1138 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1140 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1141 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1143 enum i40e_tx_ctx_desc_cmd_bits {
1144 I40E_TX_CTX_DESC_TSO = 0x01,
1145 I40E_TX_CTX_DESC_TSYN = 0x02,
1146 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1147 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1148 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1149 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1150 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1151 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1152 I40E_TX_CTX_DESC_SWPE = 0x40
1155 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1156 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1157 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1159 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1160 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1161 I40E_TXD_CTX_QW1_MSS_SHIFT)
1163 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1164 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1166 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1167 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1168 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1170 enum i40e_tx_ctx_desc_eipt_offload {
1171 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1172 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1173 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1174 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1177 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1178 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1179 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1181 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1182 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1184 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1185 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1187 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1188 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1190 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1192 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1193 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1194 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1196 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1197 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1198 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1201 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1202 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1204 struct i40e_nop_desc {
1209 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1210 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1212 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1213 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1215 enum i40e_tx_nop_desc_cmd_bits {
1216 /* Note: These are predefined bit offsets */
1217 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1218 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1219 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1222 struct i40e_filter_program_desc {
1223 __le32 qindex_flex_ptype_vsi;
1225 __le32 dtype_cmd_cntindex;
1228 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1229 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1230 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1231 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1232 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1233 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1234 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1235 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1236 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1238 /* Packet Classifier Types for filters */
1239 enum i40e_filter_pctype {
1241 /* Note: Values 0-28 are reserved for future use.
1242 * Value 29, 30, 32 are not supported on XL710 and X710.
1244 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1245 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1247 /* Note: Values 0-30 are reserved for future use */
1249 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1251 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1253 /* Note: Value 32 is reserved for future use */
1255 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1256 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1257 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1258 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1260 /* Note: Values 37-38 are reserved for future use.
1261 * Value 39, 40, 42 are not supported on XL710 and X710.
1263 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1264 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1266 /* Note: Values 37-40 are reserved for future use */
1268 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1270 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1272 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1273 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1274 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1275 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1276 /* Note: Value 47 is reserved for future use */
1277 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1278 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1279 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1280 /* Note: Values 51-62 are reserved for future use */
1281 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1284 enum i40e_filter_program_desc_dest {
1285 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1286 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1287 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1290 enum i40e_filter_program_desc_fd_status {
1291 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1292 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1293 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1294 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1297 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1298 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1299 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1301 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1302 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1304 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1305 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1306 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1308 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1309 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1311 enum i40e_filter_program_desc_pcmd {
1312 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1313 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1316 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1317 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1319 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1320 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1322 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1323 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1324 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1325 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1328 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1329 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1330 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1333 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1334 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1335 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1337 enum i40e_filter_type {
1338 I40E_FLOW_DIRECTOR_FLTR = 0,
1339 I40E_PE_QUAD_HASH_FLTR = 1,
1340 I40E_ETHERTYPE_FLTR,
1346 struct i40e_vsi_context {
1351 u16 vsis_unallocated;
1356 struct i40e_aqc_vsi_properties_data info;
1359 struct i40e_veb_context {
1364 u16 vebs_unallocated;
1366 struct i40e_aqc_get_veb_parameters_completion info;
1369 /* Statistics collected by each port, VSI, VEB, and S-channel */
1370 struct i40e_eth_stats {
1371 u64 rx_bytes; /* gorc */
1372 u64 rx_unicast; /* uprc */
1373 u64 rx_multicast; /* mprc */
1374 u64 rx_broadcast; /* bprc */
1375 u64 rx_discards; /* rdpc */
1376 u64 rx_unknown_protocol; /* rupp */
1377 u64 tx_bytes; /* gotc */
1378 u64 tx_unicast; /* uptc */
1379 u64 tx_multicast; /* mptc */
1380 u64 tx_broadcast; /* bptc */
1381 u64 tx_discards; /* tdpc */
1382 u64 tx_errors; /* tepc */
1385 /* Statistics collected per VEB per TC */
1386 struct i40e_veb_tc_stats {
1387 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1388 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1389 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1390 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1393 /* Statistics collected by the MAC */
1394 struct i40e_hw_port_stats {
1395 /* eth stats collected by the port */
1396 struct i40e_eth_stats eth;
1398 /* additional port specific stats */
1399 u64 tx_dropped_link_down; /* tdold */
1400 u64 crc_errors; /* crcerrs */
1401 u64 illegal_bytes; /* illerrc */
1402 u64 error_bytes; /* errbc */
1403 u64 mac_local_faults; /* mlfc */
1404 u64 mac_remote_faults; /* mrfc */
1405 u64 rx_length_errors; /* rlec */
1406 u64 link_xon_rx; /* lxonrxc */
1407 u64 link_xoff_rx; /* lxoffrxc */
1408 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1409 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1410 u64 link_xon_tx; /* lxontxc */
1411 u64 link_xoff_tx; /* lxofftxc */
1412 u64 priority_xon_tx[8]; /* pxontxc[8] */
1413 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1414 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1415 u64 rx_size_64; /* prc64 */
1416 u64 rx_size_127; /* prc127 */
1417 u64 rx_size_255; /* prc255 */
1418 u64 rx_size_511; /* prc511 */
1419 u64 rx_size_1023; /* prc1023 */
1420 u64 rx_size_1522; /* prc1522 */
1421 u64 rx_size_big; /* prc9522 */
1422 u64 rx_undersize; /* ruc */
1423 u64 rx_fragments; /* rfc */
1424 u64 rx_oversize; /* roc */
1425 u64 rx_jabber; /* rjc */
1426 u64 tx_size_64; /* ptc64 */
1427 u64 tx_size_127; /* ptc127 */
1428 u64 tx_size_255; /* ptc255 */
1429 u64 tx_size_511; /* ptc511 */
1430 u64 tx_size_1023; /* ptc1023 */
1431 u64 tx_size_1522; /* ptc1522 */
1432 u64 tx_size_big; /* ptc9522 */
1433 u64 mac_short_packet_dropped; /* mspdc */
1434 u64 checksum_error; /* xec */
1435 /* flow director stats */
1438 u64 fd_atr_tunnel_match;
1444 u64 tx_lpi_count; /* etlpic */
1445 u64 rx_lpi_count; /* erlpic */
1448 /* Checksum and Shadow RAM pointers */
1449 #define I40E_SR_NVM_CONTROL_WORD 0x00
1450 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1451 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1452 #define I40E_SR_OPTION_ROM_PTR 0x05
1453 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1454 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1455 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1456 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1457 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1458 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1459 #define I40E_SR_PE_IMAGE_PTR 0x0C
1460 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1461 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1462 #define I40E_SR_EMP_MODULE_PTR 0x0F
1463 #define I40E_SR_PBA_FLAGS 0x15
1464 #define I40E_SR_PBA_BLOCK_PTR 0x16
1465 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1466 #define I40E_NVM_OEM_VER_OFF 0x83
1467 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1468 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1469 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1470 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1471 #define I40E_SR_NVM_MAP_VERSION 0x29
1472 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1473 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1474 #define I40E_SR_NVM_EETRACK_LO 0x2D
1475 #define I40E_SR_NVM_EETRACK_HI 0x2E
1476 #define I40E_SR_VPD_PTR 0x2F
1477 #define I40E_SR_PXE_SETUP_PTR 0x30
1478 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1479 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1480 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1481 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1482 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1483 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1484 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1485 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1486 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1487 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1488 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1489 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1490 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1491 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1492 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1493 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1494 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1495 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1497 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1498 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1499 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1500 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1501 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1503 /* Shadow RAM related */
1504 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1505 #define I40E_SR_BUF_ALIGNMENT 4096
1506 #define I40E_SR_WORDS_IN_1KB 512
1507 /* Checksum should be calculated such that after adding all the words,
1508 * including the checksum word itself, the sum should be 0xBABA.
1510 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1512 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1514 enum i40e_switch_element_types {
1515 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1516 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1517 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1518 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1519 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1520 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1521 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1522 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1523 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1526 /* Supported EtherType filters */
1527 enum i40e_ether_type_index {
1528 I40E_ETHER_TYPE_1588 = 0,
1529 I40E_ETHER_TYPE_FIP = 1,
1530 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1531 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1532 I40E_ETHER_TYPE_LLDP = 4,
1533 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1534 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1535 I40E_ETHER_TYPE_QCN_CNM = 7,
1536 I40E_ETHER_TYPE_8021X = 8,
1537 I40E_ETHER_TYPE_ARP = 9,
1538 I40E_ETHER_TYPE_RSV1 = 10,
1539 I40E_ETHER_TYPE_RSV2 = 11,
1542 /* Filter context base size is 1K */
1543 #define I40E_HASH_FILTER_BASE_SIZE 1024
1544 /* Supported Hash filter values */
1545 enum i40e_hash_filter_size {
1546 I40E_HASH_FILTER_SIZE_1K = 0,
1547 I40E_HASH_FILTER_SIZE_2K = 1,
1548 I40E_HASH_FILTER_SIZE_4K = 2,
1549 I40E_HASH_FILTER_SIZE_8K = 3,
1550 I40E_HASH_FILTER_SIZE_16K = 4,
1551 I40E_HASH_FILTER_SIZE_32K = 5,
1552 I40E_HASH_FILTER_SIZE_64K = 6,
1553 I40E_HASH_FILTER_SIZE_128K = 7,
1554 I40E_HASH_FILTER_SIZE_256K = 8,
1555 I40E_HASH_FILTER_SIZE_512K = 9,
1556 I40E_HASH_FILTER_SIZE_1M = 10,
1559 /* DMA context base size is 0.5K */
1560 #define I40E_DMA_CNTX_BASE_SIZE 512
1561 /* Supported DMA context values */
1562 enum i40e_dma_cntx_size {
1563 I40E_DMA_CNTX_SIZE_512 = 0,
1564 I40E_DMA_CNTX_SIZE_1K = 1,
1565 I40E_DMA_CNTX_SIZE_2K = 2,
1566 I40E_DMA_CNTX_SIZE_4K = 3,
1567 I40E_DMA_CNTX_SIZE_8K = 4,
1568 I40E_DMA_CNTX_SIZE_16K = 5,
1569 I40E_DMA_CNTX_SIZE_32K = 6,
1570 I40E_DMA_CNTX_SIZE_64K = 7,
1571 I40E_DMA_CNTX_SIZE_128K = 8,
1572 I40E_DMA_CNTX_SIZE_256K = 9,
1575 /* Supported Hash look up table (LUT) sizes */
1576 enum i40e_hash_lut_size {
1577 I40E_HASH_LUT_SIZE_128 = 0,
1578 I40E_HASH_LUT_SIZE_512 = 1,
1581 /* Structure to hold a per PF filter control settings */
1582 struct i40e_filter_control_settings {
1583 /* number of PE Quad Hash filter buckets */
1584 enum i40e_hash_filter_size pe_filt_num;
1585 /* number of PE Quad Hash contexts */
1586 enum i40e_dma_cntx_size pe_cntx_num;
1587 /* number of FCoE filter buckets */
1588 enum i40e_hash_filter_size fcoe_filt_num;
1589 /* number of FCoE DDP contexts */
1590 enum i40e_dma_cntx_size fcoe_cntx_num;
1591 /* size of the Hash LUT */
1592 enum i40e_hash_lut_size hash_lut_size;
1593 /* enable FDIR filters for PF and its VFs */
1595 /* enable Ethertype filters for PF and its VFs */
1596 bool enable_ethtype;
1597 /* enable MAC/VLAN filters for PF and its VFs */
1598 bool enable_macvlan;
1601 /* Structure to hold device level control filter counts */
1602 struct i40e_control_filter_stats {
1603 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1604 u16 etype_used; /* Used perfect EtherType filters */
1605 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1606 u16 etype_free; /* Un-used perfect EtherType filters */
1609 enum i40e_reset_type {
1611 I40E_RESET_CORER = 1,
1612 I40E_RESET_GLOBR = 2,
1613 I40E_RESET_EMPR = 3,
1616 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1617 #define I40E_NVM_LLDP_CFG_PTR 0xD
1618 struct i40e_lldp_variables {
1628 /* Offsets into Alternate Ram */
1629 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1630 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1631 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1632 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1633 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1634 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1636 /* Alternate Ram Bandwidth Masks */
1637 #define I40E_ALT_BW_VALUE_MASK 0xFF
1638 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1639 #define I40E_ALT_BW_VALID_MASK 0x80000000
1641 /* RSS Hash Table Size */
1642 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1644 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1645 #define I40E_L3_SRC_SHIFT 47
1646 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1647 #define I40E_L3_V6_SRC_SHIFT 43
1648 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1649 #define I40E_L3_DST_SHIFT 35
1650 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1651 #define I40E_L3_V6_DST_SHIFT 35
1652 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1653 #define I40E_L4_SRC_SHIFT 34
1654 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1655 #define I40E_L4_DST_SHIFT 33
1656 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1657 #define I40E_VERIFY_TAG_SHIFT 31
1658 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1660 #define I40E_FLEX_50_SHIFT 13
1661 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1662 #define I40E_FLEX_51_SHIFT 12
1663 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1664 #define I40E_FLEX_52_SHIFT 11
1665 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1666 #define I40E_FLEX_53_SHIFT 10
1667 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1668 #define I40E_FLEX_54_SHIFT 9
1669 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1670 #define I40E_FLEX_55_SHIFT 8
1671 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1672 #define I40E_FLEX_56_SHIFT 7
1673 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1674 #define I40E_FLEX_57_SHIFT 6
1675 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1676 #endif /* _I40E_TYPE_H_ */