drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 161                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166
 167 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 168                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 170                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 172                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 174                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 176                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 177
 178 #define I40E_PHY_COM_REG_PAGE                   0x1E
 179 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 180 #define I40E_PHY_LED_MANUAL_ON                  0x100
 181 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 182 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 183 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 184
 185 /* Memory types */
 186 enum i40e_memset_type {
 187         I40E_NONDMA_MEM = 0,
 188         I40E_DMA_MEM
 189 };
 190
 191 /* Memcpy types */
 192 enum i40e_memcpy_type {
 193         I40E_NONDMA_TO_NONDMA = 0,
 194         I40E_NONDMA_TO_DMA,
 195         I40E_DMA_TO_DMA,
 196         I40E_DMA_TO_NONDMA
 197 };
 198
 199 #ifdef X722_SUPPORT
 200 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 201 #endif
 202 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 203
 204
 205 /* These are structs for managing the hardware information and the operations.
 206  * The structures of function pointers are filled out at init time when we
 207  * know for sure exactly which hardware we're working with.  This gives us the
 208  * flexibility of using the same main driver code but adapting to slightly
 209  * different hardware needs as new parts are developed.  For this architecture,
 210  * the Firmware and AdminQ are intended to insulate the driver from most of the
 211  * future changes, but these structures will also do part of the job.
 212  */
 213 enum i40e_mac_type {
 214         I40E_MAC_UNKNOWN = 0,
 215         I40E_MAC_XL710,
 216         I40E_MAC_VF,
 217 #ifdef X722_SUPPORT
 218         I40E_MAC_X722,
 219         I40E_MAC_X722_VF,
 220 #endif
 221         I40E_MAC_GENERIC,
 222 };
 223
 224 enum i40e_media_type {
 225         I40E_MEDIA_TYPE_UNKNOWN = 0,
 226         I40E_MEDIA_TYPE_FIBER,
 227         I40E_MEDIA_TYPE_BASET,
 228         I40E_MEDIA_TYPE_BACKPLANE,
 229         I40E_MEDIA_TYPE_CX4,
 230         I40E_MEDIA_TYPE_DA,
 231         I40E_MEDIA_TYPE_VIRTUAL
 232 };
 233
 234 enum i40e_fc_mode {
 235         I40E_FC_NONE = 0,
 236         I40E_FC_RX_PAUSE,
 237         I40E_FC_TX_PAUSE,
 238         I40E_FC_FULL,
 239         I40E_FC_PFC,
 240         I40E_FC_DEFAULT
 241 };
 242
 243 enum i40e_set_fc_aq_failures {
 244         I40E_SET_FC_AQ_FAIL_NONE = 0,
 245         I40E_SET_FC_AQ_FAIL_GET = 1,
 246         I40E_SET_FC_AQ_FAIL_SET = 2,
 247         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 248         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 249 };
 250
 251 enum i40e_vsi_type {
 252         I40E_VSI_MAIN   = 0,
 253         I40E_VSI_VMDQ1  = 1,
 254         I40E_VSI_VMDQ2  = 2,
 255         I40E_VSI_CTRL   = 3,
 256         I40E_VSI_FCOE   = 4,
 257         I40E_VSI_MIRROR = 5,
 258         I40E_VSI_SRIOV  = 6,
 259         I40E_VSI_FDIR   = 7,
 260         I40E_VSI_TYPE_UNKNOWN
 261 };
 262
 263 enum i40e_queue_type {
 264         I40E_QUEUE_TYPE_RX = 0,
 265         I40E_QUEUE_TYPE_TX,
 266         I40E_QUEUE_TYPE_PE_CEQ,
 267         I40E_QUEUE_TYPE_UNKNOWN
 268 };
 269
 270 struct i40e_link_status {
 271         enum i40e_aq_phy_type phy_type;
 272         enum i40e_aq_link_speed link_speed;
 273         u8 link_info;
 274         u8 an_info;
 275         u8 ext_info;
 276         u8 loopback;
 277         /* is Link Status Event notification to SW enabled */
 278         bool lse_enable;
 279         u16 max_frame_size;
 280         bool crc_enable;
 281         u8 pacing;
 282         u8 requested_speeds;
 283         u8 module_type[3];
 284         /* 1st byte: module identifier */
 285 #define I40E_MODULE_TYPE_SFP            0x03
 286 #define I40E_MODULE_TYPE_QSFP           0x0D
 287         /* 2nd byte: ethernet compliance codes for 10/40G */
 288 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 289 #define I40E_MODULE_TYPE_40G_LR4        0x02
 290 #define I40E_MODULE_TYPE_40G_SR4        0x04
 291 #define I40E_MODULE_TYPE_40G_CR4        0x08
 292 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 293 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 294 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 295 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 296         /* 3rd byte: ethernet compliance codes for 1G */
 297 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 298 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 299 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 300 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 301 };
 302
 303 struct i40e_phy_info {
 304         struct i40e_link_status link_info;
 305         struct i40e_link_status link_info_old;
 306         bool get_link_info;
 307         enum i40e_media_type media_type;
 308         /* all the phy types the NVM is capable of */
 309         u64 phy_types;
 310 };
 311
 312 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 313 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 314 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 316 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 317 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 318 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 319 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 320 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 321 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 323 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 325 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 326 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 327 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 328 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 330 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 331 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 332 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 333 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 334 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 335 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 336 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 337 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 338 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 339                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 340 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 341 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)
 342 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)
 343 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)
 344 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)
 345 #define I40E_HW_CAP_MAX_GPIO                    30
 346 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 347 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 348
 349 #ifdef X722_SUPPORT
 350 enum i40e_acpi_programming_method {
 351         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 352         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 353 };
 354
 355 #define I40E_WOL_SUPPORT_MASK                   1
 356 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 357 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 358
 359 #endif
 360 /* Capabilities of a PF or a VF or the whole device */
 361 struct i40e_hw_capabilities {
 362         u32  switch_mode;
 363 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 364 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 365 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 366
 367         u32  management_mode;
 368         u32  mng_protocols_over_mctp;
 369 #define I40E_MNG_PROTOCOL_PLDM          0x2
 370 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 371 #define I40E_MNG_PROTOCOL_NCSI          0x8
 372         u32  npar_enable;
 373         u32  os2bmc;
 374         u32  valid_functions;
 375         bool sr_iov_1_1;
 376         bool vmdq;
 377         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 378         bool evb_802_1_qbh; /* Bridge Port Extension */
 379         bool dcb;
 380         bool fcoe;
 381         bool iscsi; /* Indicates iSCSI enabled */
 382         bool flex10_enable;
 383         bool flex10_capable;
 384         u32  flex10_mode;
 385 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 386 #define I40E_FLEX10_MODE_DCC            0x1
 387 #define I40E_FLEX10_MODE_DCI            0x2
 388
 389         u32 flex10_status;
 390 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 391 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 392
 393         bool sec_rev_disabled;
 394         bool update_disabled;
 395 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 396 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 397
 398         bool mgmt_cem;
 399         bool ieee_1588;
 400         bool iwarp;
 401         bool fd;
 402         u32 fd_filters_guaranteed;
 403         u32 fd_filters_best_effort;
 404         bool rss;
 405         u32 rss_table_size;
 406         u32 rss_table_entry_width;
 407         bool led[I40E_HW_CAP_MAX_GPIO];
 408         bool sdp[I40E_HW_CAP_MAX_GPIO];
 409         u32 nvm_image_type;
 410         u32 num_flow_director_filters;
 411         u32 num_vfs;
 412         u32 vf_base_id;
 413         u32 num_vsis;
 414         u32 num_rx_qp;
 415         u32 num_tx_qp;
 416         u32 base_queue;
 417         u32 num_msix_vectors;
 418         u32 num_msix_vectors_vf;
 419         u32 led_pin_num;
 420         u32 sdp_pin_num;
 421         u32 mdio_port_num;
 422         u32 mdio_port_mode;
 423         u8 rx_buf_chain_len;
 424         u32 enabled_tcmap;
 425         u32 maxtc;
 426         u64 wr_csr_prot;
 427 #ifdef X722_SUPPORT
 428         bool apm_wol_support;
 429         enum i40e_acpi_programming_method acpi_prog_method;
 430         bool proxy_support;
 431 #endif
 432 };
 433
 434 struct i40e_mac_info {
 435         enum i40e_mac_type type;
 436         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 437         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 438         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 439         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 440         u16 max_fcoeq;
 441 };
 442
 443 enum i40e_aq_resources_ids {
 444         I40E_NVM_RESOURCE_ID = 1
 445 };
 446
 447 enum i40e_aq_resource_access_type {
 448         I40E_RESOURCE_READ = 1,
 449         I40E_RESOURCE_WRITE
 450 };
 451
 452 struct i40e_nvm_info {
 453         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 454         u32 timeout;              /* [ms] */
 455         u16 sr_size;              /* Shadow RAM size in words */
 456         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 457         u16 version;              /* NVM package version */
 458         u32 eetrack;              /* NVM data version */
 459         u32 oem_ver;              /* OEM version info */
 460 };
 461
 462 /* definitions used in NVM update support */
 463
 464 enum i40e_nvmupd_cmd {
 465         I40E_NVMUPD_INVALID,
 466         I40E_NVMUPD_READ_CON,
 467         I40E_NVMUPD_READ_SNT,
 468         I40E_NVMUPD_READ_LCB,
 469         I40E_NVMUPD_READ_SA,
 470         I40E_NVMUPD_WRITE_ERA,
 471         I40E_NVMUPD_WRITE_CON,
 472         I40E_NVMUPD_WRITE_SNT,
 473         I40E_NVMUPD_WRITE_LCB,
 474         I40E_NVMUPD_WRITE_SA,
 475         I40E_NVMUPD_CSUM_CON,
 476         I40E_NVMUPD_CSUM_SA,
 477         I40E_NVMUPD_CSUM_LCB,
 478         I40E_NVMUPD_STATUS,
 479         I40E_NVMUPD_EXEC_AQ,
 480         I40E_NVMUPD_GET_AQ_RESULT,
 481 };
 482
 483 enum i40e_nvmupd_state {
 484         I40E_NVMUPD_STATE_INIT,
 485         I40E_NVMUPD_STATE_READING,
 486         I40E_NVMUPD_STATE_WRITING,
 487         I40E_NVMUPD_STATE_INIT_WAIT,
 488         I40E_NVMUPD_STATE_WRITE_WAIT,
 489 };
 490
 491 /* nvm_access definition and its masks/shifts need to be accessible to
 492  * application, core driver, and shared code.  Where is the right file?
 493  */
 494 #define I40E_NVM_READ   0xB
 495 #define I40E_NVM_WRITE  0xC
 496
 497 #define I40E_NVM_MOD_PNT_MASK 0xFF
 498
 499 #define I40E_NVM_TRANS_SHIFT    8
 500 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 501 #define I40E_NVM_CON            0x0
 502 #define I40E_NVM_SNT            0x1
 503 #define I40E_NVM_LCB            0x2
 504 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 505 #define I40E_NVM_ERA            0x4
 506 #define I40E_NVM_CSUM           0x8
 507 #define I40E_NVM_EXEC           0xf
 508
 509 #define I40E_NVM_ADAPT_SHIFT    16
 510 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 511
 512 #define I40E_NVMUPD_MAX_DATA    4096
 513 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 514
 515 struct i40e_nvm_access {
 516         u32 command;
 517         u32 config;
 518         u32 offset;     /* in bytes */
 519         u32 data_size;  /* in bytes */
 520         u8 data[1];
 521 };
 522
 523 /* PCI bus types */
 524 enum i40e_bus_type {
 525         i40e_bus_type_unknown = 0,
 526         i40e_bus_type_pci,
 527         i40e_bus_type_pcix,
 528         i40e_bus_type_pci_express,
 529         i40e_bus_type_reserved
 530 };
 531
 532 /* PCI bus speeds */
 533 enum i40e_bus_speed {
 534         i40e_bus_speed_unknown  = 0,
 535         i40e_bus_speed_33       = 33,
 536         i40e_bus_speed_66       = 66,
 537         i40e_bus_speed_100      = 100,
 538         i40e_bus_speed_120      = 120,
 539         i40e_bus_speed_133      = 133,
 540         i40e_bus_speed_2500     = 2500,
 541         i40e_bus_speed_5000     = 5000,
 542         i40e_bus_speed_8000     = 8000,
 543         i40e_bus_speed_reserved
 544 };
 545
 546 /* PCI bus widths */
 547 enum i40e_bus_width {
 548         i40e_bus_width_unknown  = 0,
 549         i40e_bus_width_pcie_x1  = 1,
 550         i40e_bus_width_pcie_x2  = 2,
 551         i40e_bus_width_pcie_x4  = 4,
 552         i40e_bus_width_pcie_x8  = 8,
 553         i40e_bus_width_32       = 32,
 554         i40e_bus_width_64       = 64,
 555         i40e_bus_width_reserved
 556 };
 557
 558 /* Bus parameters */
 559 struct i40e_bus_info {
 560         enum i40e_bus_speed speed;
 561         enum i40e_bus_width width;
 562         enum i40e_bus_type type;
 563
 564         u16 func;
 565         u16 device;
 566         u16 lan_id;
 567         u16 bus_id;
 568 };
 569
 570 /* Flow control (FC) parameters */
 571 struct i40e_fc_info {
 572         enum i40e_fc_mode current_mode; /* FC mode in effect */
 573         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 574 };
 575
 576 #define I40E_MAX_TRAFFIC_CLASS          8
 577 #define I40E_MAX_USER_PRIORITY          8
 578 #define I40E_DCBX_MAX_APPS              32
 579 #define I40E_LLDPDU_SIZE                1500
 580 #define I40E_TLV_STATUS_OPER            0x1
 581 #define I40E_TLV_STATUS_SYNC            0x2
 582 #define I40E_TLV_STATUS_ERR             0x4
 583 #define I40E_CEE_OPER_MAX_APPS          3
 584 #define I40E_APP_PROTOID_FCOE           0x8906
 585 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 586 #define I40E_APP_PROTOID_FIP            0x8914
 587 #define I40E_APP_SEL_ETHTYPE            0x1
 588 #define I40E_APP_SEL_TCPIP              0x2
 589 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 590 #define I40E_CEE_APP_SEL_TCPIP          0x1
 591
 592 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 593 struct i40e_dcb_ets_config {
 594         u8 willing;
 595         u8 cbs;
 596         u8 maxtcs;
 597         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 598         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 599         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 600 };
 601
 602 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 603 struct i40e_dcb_pfc_config {
 604         u8 willing;
 605         u8 mbc;
 606         u8 pfccap;
 607         u8 pfcenable;
 608 };
 609
 610 /* CEE or IEEE 802.1Qaz Application Priority data */
 611 struct i40e_dcb_app_priority_table {
 612         u8  priority;
 613         u8  selector;
 614         u16 protocolid;
 615 };
 616
 617 struct i40e_dcbx_config {
 618         u8  dcbx_mode;
 619 #define I40E_DCBX_MODE_CEE      0x1
 620 #define I40E_DCBX_MODE_IEEE     0x2
 621         u8  app_mode;
 622 #define I40E_DCBX_APPS_NON_WILLING      0x1
 623         u32 numapps;
 624         u32 tlv_status; /* CEE mode TLV status */
 625         struct i40e_dcb_ets_config etscfg;
 626         struct i40e_dcb_ets_config etsrec;
 627         struct i40e_dcb_pfc_config pfc;
 628         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 629 };
 630
 631 /* Port hardware description */
 632 struct i40e_hw {
 633         u8 *hw_addr;
 634         void *back;
 635
 636         /* subsystem structs */
 637         struct i40e_phy_info phy;
 638         struct i40e_mac_info mac;
 639         struct i40e_bus_info bus;
 640         struct i40e_nvm_info nvm;
 641         struct i40e_fc_info fc;
 642
 643         /* pci info */
 644         u16 device_id;
 645         u16 vendor_id;
 646         u16 subsystem_device_id;
 647         u16 subsystem_vendor_id;
 648         u8 revision_id;
 649         u8 port;
 650         bool adapter_stopped;
 651
 652         /* capabilities for entire device and PCI func */
 653         struct i40e_hw_capabilities dev_caps;
 654         struct i40e_hw_capabilities func_caps;
 655
 656         /* Flow Director shared filter space */
 657         u16 fdir_shared_filter_count;
 658
 659         /* device profile info */
 660         u8  pf_id;
 661         u16 main_vsi_seid;
 662
 663         /* for multi-function MACs */
 664         u16 partition_id;
 665         u16 num_partitions;
 666         u16 num_ports;
 667
 668         /* Closest numa node to the device */
 669         u16 numa_node;
 670
 671         /* Admin Queue info */
 672         struct i40e_adminq_info aq;
 673
 674         /* state of nvm update process */
 675         enum i40e_nvmupd_state nvmupd_state;
 676         struct i40e_aq_desc nvm_wb_desc;
 677         struct i40e_virt_mem nvm_buff;
 678         bool nvm_release_on_done;
 679         u16 nvm_wait_opcode;
 680
 681         /* HMC info */
 682         struct i40e_hmc_info hmc; /* HMC info struct */
 683
 684         /* LLDP/DCBX Status */
 685         u16 dcbx_status;
 686
 687         /* DCBX info */
 688         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 689         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 690         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 691
 692 #ifdef X722_SUPPORT
 693         /* WoL and proxy support */
 694         u16 num_wol_proxy_filters;
 695         u16 wol_proxy_vsi_seid;
 696
 697 #endif
 698 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 699         u64 flags;
 700
 701         /* debug mask */
 702         u32 debug_mask;
 703 #ifndef I40E_NDIS_SUPPORT
 704         char err_str[16];
 705 #endif /* I40E_NDIS_SUPPORT */
 706 };
 707
 708 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 709 {
 710 #ifdef X722_SUPPORT
 711         return (hw->mac.type == I40E_MAC_VF ||
 712                 hw->mac.type == I40E_MAC_X722_VF);
 713 #else
 714         return hw->mac.type == I40E_MAC_VF;
 715 #endif
 716 }
 717
 718 struct i40e_driver_version {
 719         u8 major_version;
 720         u8 minor_version;
 721         u8 build_version;
 722         u8 subbuild_version;
 723         u8 driver_string[32];
 724 };
 725
 726 /* RX Descriptors */
 727 union i40e_16byte_rx_desc {
 728         struct {
 729                 __le64 pkt_addr; /* Packet buffer address */
 730                 __le64 hdr_addr; /* Header buffer address */
 731         } read;
 732         struct {
 733                 struct {
 734                         struct {
 735                                 union {
 736                                         __le16 mirroring_status;
 737                                         __le16 fcoe_ctx_id;
 738                                 } mirr_fcoe;
 739                                 __le16 l2tag1;
 740                         } lo_dword;
 741                         union {
 742                                 __le32 rss; /* RSS Hash */
 743                                 __le32 fd_id; /* Flow director filter id */
 744                                 __le32 fcoe_param; /* FCoE DDP Context id */
 745                         } hi_dword;
 746                 } qword0;
 747                 struct {
 748                         /* ext status/error/pktype/length */
 749                         __le64 status_error_len;
 750                 } qword1;
 751         } wb;  /* writeback */
 752 };
 753
 754 union i40e_32byte_rx_desc {
 755         struct {
 756                 __le64  pkt_addr; /* Packet buffer address */
 757                 __le64  hdr_addr; /* Header buffer address */
 758                         /* bit 0 of hdr_buffer_addr is DD bit */
 759                 __le64  rsvd1;
 760                 __le64  rsvd2;
 761         } read;
 762         struct {
 763                 struct {
 764                         struct {
 765                                 union {
 766                                         __le16 mirroring_status;
 767                                         __le16 fcoe_ctx_id;
 768                                 } mirr_fcoe;
 769                                 __le16 l2tag1;
 770                         } lo_dword;
 771                         union {
 772                                 __le32 rss; /* RSS Hash */
 773                                 __le32 fcoe_param; /* FCoE DDP Context id */
 774                                 /* Flow director filter id in case of
 775                                  * Programming status desc WB
 776                                  */
 777                                 __le32 fd_id;
 778                         } hi_dword;
 779                 } qword0;
 780                 struct {
 781                         /* status/error/pktype/length */
 782                         __le64 status_error_len;
 783                 } qword1;
 784                 struct {
 785                         __le16 ext_status; /* extended status */
 786                         __le16 rsvd;
 787                         __le16 l2tag2_1;
 788                         __le16 l2tag2_2;
 789                 } qword2;
 790                 struct {
 791                         union {
 792                                 __le32 flex_bytes_lo;
 793                                 __le32 pe_status;
 794                         } lo_dword;
 795                         union {
 796                                 __le32 flex_bytes_hi;
 797                                 __le32 fd_id;
 798                         } hi_dword;
 799                 } qword3;
 800         } wb;  /* writeback */
 801 };
 802
 803 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 804 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 805                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 806 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 807 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 808                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 809
 810 enum i40e_rx_desc_status_bits {
 811         /* Note: These are predefined bit offsets */
 812         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 813         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 814         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 815         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 816         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 817         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 818         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 819 #ifdef X722_SUPPORT
 820         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 821 #else
 822         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 823 #endif
 824
 825         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 826         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 827         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 828         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 829         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 830         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 831 #ifdef X722_SUPPORT
 832         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 833 #else
 834         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 835 #endif
 836         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 837 };
 838
 839 #define I40E_RXD_QW1_STATUS_SHIFT       0
 840 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 841                                          I40E_RXD_QW1_STATUS_SHIFT)
 842
 843 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 844 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 845                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 846
 847 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 848 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 849
 850 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 851 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 852                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 853
 854 enum i40e_rx_desc_fltstat_values {
 855         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 856         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 857         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 858         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 859 };
 860
 861 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 862 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 863 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 864 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 865
 866 #define I40E_RXD_QW1_ERROR_SHIFT        19
 867 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 868
 869 enum i40e_rx_desc_error_bits {
 870         /* Note: These are predefined bit offsets */
 871         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 872         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 873         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 874         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 875         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 876         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 877         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 878         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 879         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 880 };
 881
 882 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 883         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 884         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 885         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 886         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 887         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 888 };
 889
 890 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 891 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 892
 893 /* Packet type non-ip values */
 894 enum i40e_rx_l2_ptype {
 895         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 896         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 897         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 898         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 899         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 900         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 901         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 902         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 903         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 904         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 905         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 906         I40E_RX_PTYPE_L2_ARP                            = 11,
 907         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 908         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 909         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 910         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 911         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 912         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 913         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 914         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 915         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 916         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 917         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 918         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 919         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 920         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 921 };
 922
 923 struct i40e_rx_ptype_decoded {
 924         u32 ptype:8;
 925         u32 known:1;
 926         u32 outer_ip:1;
 927         u32 outer_ip_ver:1;
 928         u32 outer_frag:1;
 929         u32 tunnel_type:3;
 930         u32 tunnel_end_prot:2;
 931         u32 tunnel_end_frag:1;
 932         u32 inner_prot:4;
 933         u32 payload_layer:3;
 934 };
 935
 936 enum i40e_rx_ptype_outer_ip {
 937         I40E_RX_PTYPE_OUTER_L2  = 0,
 938         I40E_RX_PTYPE_OUTER_IP  = 1
 939 };
 940
 941 enum i40e_rx_ptype_outer_ip_ver {
 942         I40E_RX_PTYPE_OUTER_NONE        = 0,
 943         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 944         I40E_RX_PTYPE_OUTER_IPV6        = 1
 945 };
 946
 947 enum i40e_rx_ptype_outer_fragmented {
 948         I40E_RX_PTYPE_NOT_FRAG  = 0,
 949         I40E_RX_PTYPE_FRAG      = 1
 950 };
 951
 952 enum i40e_rx_ptype_tunnel_type {
 953         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 954         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 955         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 956         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 957         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 958 };
 959
 960 enum i40e_rx_ptype_tunnel_end_prot {
 961         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 962         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 963         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 964 };
 965
 966 enum i40e_rx_ptype_inner_prot {
 967         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 968         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 969         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 970         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 971         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 972         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 973 };
 974
 975 enum i40e_rx_ptype_payload_layer {
 976         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 977         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 978         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 979         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 980 };
 981
 982 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 983 #define I40E_RX_PTYPE_SHIFT             56
 984
 985 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 986 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 987                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 988
 989 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 990 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 991                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 992
 993 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 994 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 995
 996 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 997 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 998
 999 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1000 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1001                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1002
1003 enum i40e_rx_desc_ext_status_bits {
1004         /* Note: These are predefined bit offsets */
1005         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1006         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1007         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1008         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1009         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1010         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1011         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1012 };
1013
1014 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1015 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1016
1017 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1018 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1019
1020 enum i40e_rx_desc_pe_status_bits {
1021         /* Note: These are predefined bit offsets */
1022         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1023         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1024         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1025         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1026         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1027         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1028         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1029         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1030         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1031 };
1032
1033 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1034 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1035
1036 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1037 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1038                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1039
1040 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1041 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1042                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1043
1044 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1045 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1046                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1047
1048 enum i40e_rx_prog_status_desc_status_bits {
1049         /* Note: These are predefined bit offsets */
1050         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1051         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1052 };
1053
1054 enum i40e_rx_prog_status_desc_prog_id_masks {
1055         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1056         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1057         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1058 };
1059
1060 enum i40e_rx_prog_status_desc_error_bits {
1061         /* Note: These are predefined bit offsets */
1062         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1063         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1064         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1065         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1066 };
1067
1068 #define I40E_TWO_BIT_MASK       0x3
1069 #define I40E_THREE_BIT_MASK     0x7
1070 #define I40E_FOUR_BIT_MASK      0xF
1071 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1072
1073 /* TX Descriptor */
1074 struct i40e_tx_desc {
1075         __le64 buffer_addr; /* Address of descriptor's data buf */
1076         __le64 cmd_type_offset_bsz;
1077 };
1078
1079 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1080 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1081
1082 enum i40e_tx_desc_dtype_value {
1083         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1084         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1085         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1086         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1087         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1088         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1089         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1090         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1091         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1092         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1093 };
1094
1095 #define I40E_TXD_QW1_CMD_SHIFT  4
1096 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1097
1098 enum i40e_tx_desc_cmd_bits {
1099         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1100         I40E_TX_DESC_CMD_RS                     = 0x0002,
1101         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1102         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1103         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1104         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1105         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1106         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1107         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1108         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1109         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1110         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1111         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1112         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1113         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1114         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1115         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1116         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1117 };
1118
1119 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1120 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1121                                          I40E_TXD_QW1_OFFSET_SHIFT)
1122
1123 enum i40e_tx_desc_length_fields {
1124         /* Note: These are predefined bit offsets */
1125         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1126         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1127         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1128 };
1129
1130 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1131 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1132 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1133 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1134
1135 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1136 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1137                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1138
1139 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1140 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1141
1142 /* Context descriptors */
1143 struct i40e_tx_context_desc {
1144         __le32 tunneling_params;
1145         __le16 l2tag2;
1146         __le16 rsvd;
1147         __le64 type_cmd_tso_mss;
1148 };
1149
1150 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1151 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1152
1153 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1154 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1155
1156 enum i40e_tx_ctx_desc_cmd_bits {
1157         I40E_TX_CTX_DESC_TSO            = 0x01,
1158         I40E_TX_CTX_DESC_TSYN           = 0x02,
1159         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1160         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1161         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1162         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1163         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1164         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1165         I40E_TX_CTX_DESC_SWPE           = 0x40
1166 };
1167
1168 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1169 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1170                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1171
1172 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1173 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1174                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1175
1176 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1177 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1178
1179 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1180 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1181                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1182
1183 enum i40e_tx_ctx_desc_eipt_offload {
1184         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1185         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1186         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1187         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1188 };
1189
1190 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1191 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1192                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1193
1194 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1195 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1196
1197 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1198 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1199
1200 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1201 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1202
1203 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1204
1205 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1206 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1207                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1208
1209 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1210 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1211                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1212
1213 #ifdef X722_SUPPORT
1214 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1215 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1216 #endif
1217 struct i40e_nop_desc {
1218         __le64 rsvd;
1219         __le64 dtype_cmd;
1220 };
1221
1222 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1223 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1224
1225 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1226 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1227
1228 enum i40e_tx_nop_desc_cmd_bits {
1229         /* Note: These are predefined bit offsets */
1230         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1231         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1232         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1233 };
1234
1235 struct i40e_filter_program_desc {
1236         __le32 qindex_flex_ptype_vsi;
1237         __le32 rsvd;
1238         __le32 dtype_cmd_cntindex;
1239         __le32 fd_id;
1240 };
1241 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1242 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1243                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1244 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1245 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1246                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1247 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1248 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1249                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1250
1251 /* Packet Classifier Types for filters */
1252 enum i40e_filter_pctype {
1253 #ifdef X722_SUPPORT
1254         /* Note: Values 0-28 are reserved for future use.
1255          * Value 29, 30, 32 are not supported on XL710 and X710.
1256          */
1257         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1258         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1259 #else
1260         /* Note: Values 0-30 are reserved for future use */
1261 #endif
1262         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1263 #ifdef X722_SUPPORT
1264         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1265 #else
1266         /* Note: Value 32 is reserved for future use */
1267 #endif
1268         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1269         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1270         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1271         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1272 #ifdef X722_SUPPORT
1273         /* Note: Values 37-38 are reserved for future use.
1274          * Value 39, 40, 42 are not supported on XL710 and X710.
1275          */
1276         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1277         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1278 #else
1279         /* Note: Values 37-40 are reserved for future use */
1280 #endif
1281         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1282 #ifdef X722_SUPPORT
1283         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1284 #endif
1285         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1286         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1287         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1288         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1289         /* Note: Value 47 is reserved for future use */
1290         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1291         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1292         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1293         /* Note: Values 51-62 are reserved for future use */
1294         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1295 };
1296
1297 enum i40e_filter_program_desc_dest {
1298         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1299         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1300         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1301 };
1302
1303 enum i40e_filter_program_desc_fd_status {
1304         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1305         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1306         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1307         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1308 };
1309
1310 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1311 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1312                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1313
1314 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1315 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1316
1317 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1318 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1319                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1320
1321 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1322 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1323
1324 enum i40e_filter_program_desc_pcmd {
1325         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1326         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1327 };
1328
1329 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1330 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1331
1332 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1333 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1334
1335 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1336                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1337 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1338                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1339 #ifdef X722_SUPPORT
1340
1341 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1342                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1343 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1344 #endif
1345
1346 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1347 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1348                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1349
1350 enum i40e_filter_type {
1351         I40E_FLOW_DIRECTOR_FLTR = 0,
1352         I40E_PE_QUAD_HASH_FLTR = 1,
1353         I40E_ETHERTYPE_FLTR,
1354         I40E_FCOE_CTX_FLTR,
1355         I40E_MAC_VLAN_FLTR,
1356         I40E_HASH_FLTR
1357 };
1358
1359 struct i40e_vsi_context {
1360         u16 seid;
1361         u16 uplink_seid;
1362         u16 vsi_number;
1363         u16 vsis_allocated;
1364         u16 vsis_unallocated;
1365         u16 flags;
1366         u8 pf_num;
1367         u8 vf_num;
1368         u8 connection_type;
1369         struct i40e_aqc_vsi_properties_data info;
1370 };
1371
1372 struct i40e_veb_context {
1373         u16 seid;
1374         u16 uplink_seid;
1375         u16 veb_number;
1376         u16 vebs_allocated;
1377         u16 vebs_unallocated;
1378         u16 flags;
1379         struct i40e_aqc_get_veb_parameters_completion info;
1380 };
1381
1382 /* Statistics collected by each port, VSI, VEB, and S-channel */
1383 struct i40e_eth_stats {
1384         u64 rx_bytes;                   /* gorc */
1385         u64 rx_unicast;                 /* uprc */
1386         u64 rx_multicast;               /* mprc */
1387         u64 rx_broadcast;               /* bprc */
1388         u64 rx_discards;                /* rdpc */
1389         u64 rx_unknown_protocol;        /* rupp */
1390         u64 tx_bytes;                   /* gotc */
1391         u64 tx_unicast;                 /* uptc */
1392         u64 tx_multicast;               /* mptc */
1393         u64 tx_broadcast;               /* bptc */
1394         u64 tx_discards;                /* tdpc */
1395         u64 tx_errors;                  /* tepc */
1396 };
1397
1398 /* Statistics collected per VEB per TC */
1399 struct i40e_veb_tc_stats {
1400         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1401         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1402         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1403         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1404 };
1405
1406 /* Statistics collected per function for FCoE */
1407 struct i40e_fcoe_stats {
1408         u64 rx_fcoe_packets;            /* fcoeprc */
1409         u64 rx_fcoe_dwords;             /* focedwrc */
1410         u64 rx_fcoe_dropped;            /* fcoerpdc */
1411         u64 tx_fcoe_packets;            /* fcoeptc */
1412         u64 tx_fcoe_dwords;             /* focedwtc */
1413         u64 fcoe_bad_fccrc;             /* fcoecrc */
1414         u64 fcoe_last_error;            /* fcoelast */
1415         u64 fcoe_ddp_count;             /* fcoeddpc */
1416 };
1417
1418 /* offset to per function FCoE statistics block */
1419 #define I40E_FCOE_VF_STAT_OFFSET        0
1420 #define I40E_FCOE_PF_STAT_OFFSET        128
1421 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1422
1423 /* Statistics collected by the MAC */
1424 struct i40e_hw_port_stats {
1425         /* eth stats collected by the port */
1426         struct i40e_eth_stats eth;
1427
1428         /* additional port specific stats */
1429         u64 tx_dropped_link_down;       /* tdold */
1430         u64 crc_errors;                 /* crcerrs */
1431         u64 illegal_bytes;              /* illerrc */
1432         u64 error_bytes;                /* errbc */
1433         u64 mac_local_faults;           /* mlfc */
1434         u64 mac_remote_faults;          /* mrfc */
1435         u64 rx_length_errors;           /* rlec */
1436         u64 link_xon_rx;                /* lxonrxc */
1437         u64 link_xoff_rx;               /* lxoffrxc */
1438         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1439         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1440         u64 link_xon_tx;                /* lxontxc */
1441         u64 link_xoff_tx;               /* lxofftxc */
1442         u64 priority_xon_tx[8];         /* pxontxc[8] */
1443         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1444         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1445         u64 rx_size_64;                 /* prc64 */
1446         u64 rx_size_127;                /* prc127 */
1447         u64 rx_size_255;                /* prc255 */
1448         u64 rx_size_511;                /* prc511 */
1449         u64 rx_size_1023;               /* prc1023 */
1450         u64 rx_size_1522;               /* prc1522 */
1451         u64 rx_size_big;                /* prc9522 */
1452         u64 rx_undersize;               /* ruc */
1453         u64 rx_fragments;               /* rfc */
1454         u64 rx_oversize;                /* roc */
1455         u64 rx_jabber;                  /* rjc */
1456         u64 tx_size_64;                 /* ptc64 */
1457         u64 tx_size_127;                /* ptc127 */
1458         u64 tx_size_255;                /* ptc255 */
1459         u64 tx_size_511;                /* ptc511 */
1460         u64 tx_size_1023;               /* ptc1023 */
1461         u64 tx_size_1522;               /* ptc1522 */
1462         u64 tx_size_big;                /* ptc9522 */
1463         u64 mac_short_packet_dropped;   /* mspdc */
1464         u64 checksum_error;             /* xec */
1465         /* flow director stats */
1466         u64 fd_atr_match;
1467         u64 fd_sb_match;
1468         u64 fd_atr_tunnel_match;
1469         u32 fd_atr_status;
1470         u32 fd_sb_status;
1471         /* EEE LPI */
1472         u32 tx_lpi_status;
1473         u32 rx_lpi_status;
1474         u64 tx_lpi_count;               /* etlpic */
1475         u64 rx_lpi_count;               /* erlpic */
1476 };
1477
1478 /* Checksum and Shadow RAM pointers */
1479 #define I40E_SR_NVM_CONTROL_WORD                0x00
1480 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1481 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1482 #define I40E_SR_OPTION_ROM_PTR                  0x05
1483 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1484 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1485 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1486 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1487 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1488 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1489 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1490 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1491 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1492 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1493 #define I40E_SR_PBA_FLAGS                       0x15
1494 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1495 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1496 #define I40E_NVM_OEM_VER_OFF                    0x83
1497 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1498 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1499 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1500 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1501 #define I40E_SR_NVM_MAP_VERSION                 0x29
1502 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1503 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1504 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1505 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1506 #define I40E_SR_VPD_PTR                         0x2F
1507 #define I40E_SR_PXE_SETUP_PTR                   0x30
1508 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1509 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1510 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1511 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1512 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1513 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1514 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1515 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1516 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1517 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1518 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1519 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1520 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1521 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1522 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1523 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1524 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1525 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1526
1527 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1528 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1529 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1530 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1531 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1532
1533 /* Shadow RAM related */
1534 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1535 #define I40E_SR_BUF_ALIGNMENT           4096
1536 #define I40E_SR_WORDS_IN_1KB            512
1537 /* Checksum should be calculated such that after adding all the words,
1538  * including the checksum word itself, the sum should be 0xBABA.
1539  */
1540 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1541
1542 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1543
1544 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1545
1546 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1547         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1548         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1549         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1550         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1551         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1552         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1553         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1554         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1555         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1556         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1557         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1558         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1559         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1560 };
1561
1562 /* FCoE DIF/DIX Context descriptor */
1563 struct i40e_fcoe_difdix_context_desc {
1564         __le64 flags_buff0_buff1_ref;
1565         __le64 difapp_msk_bias;
1566 };
1567
1568 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1569 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1570                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1571
1572 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1573         /* 2 BITS */
1574         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1575         /* 1 BIT  */
1576         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1577         /* 1 BIT  */
1578         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1579         /* 2 BITS */
1580         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1581         /* 2 BITS */
1582         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1583         /* 2 BITS */
1584         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1585         /* 2 BITS */
1586         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1587         /* 2 BITS */
1588         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1589         /* 2 BITS */
1590         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1591         /* 2 BITS */
1592         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1593         /* 2 BITS */
1594         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1595         /* 1 BIT  */
1596         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1597         /* 1 BIT  */
1598         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1599         /* 2 BITS */
1600         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1601         /* 2 BITS */
1602         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1603         /* 2 BITS */
1604         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1605         /* 2 BITS */
1606         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1607         /* 1 BIT  */
1608         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1609         /* 1 BIT  */
1610         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1611         /* 1 BIT */
1612         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1613         /* 1 BIT */
1614         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1615 };
1616
1617 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1619                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1620
1621 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1623                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1624
1625 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1626 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1627                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1628
1629 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1631                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1632
1633 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1634 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1635                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1636
1637 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1638 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1639                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1640
1641 /* FCoE DIF/DIX Buffers descriptor */
1642 struct i40e_fcoe_difdix_buffers_desc {
1643         __le64 buff_addr0;
1644         __le64 buff_addr1;
1645 };
1646
1647 /* FCoE DDP Context descriptor */
1648 struct i40e_fcoe_ddp_context_desc {
1649         __le64 rsvd;
1650         __le64 type_cmd_foff_lsize;
1651 };
1652
1653 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1654 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1655                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1656
1657 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1658 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1659                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1660
1661 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1662         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1663         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1664         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1665         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1666         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1667         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1668 };
1669
1670 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1671 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1672                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1673
1674 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1675 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1676                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1677
1678 /* FCoE DDP/DWO Queue Context descriptor */
1679 struct i40e_fcoe_queue_context_desc {
1680         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1681         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1682 };
1683
1684 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1685 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1686                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1687
1688 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1689 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1690                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1691
1692 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1693 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1694                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1695
1696 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1697 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1698                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1699
1700 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1701         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1702         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1703 };
1704
1705 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1706 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1707                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1708
1709 /* FCoE DDP/DWO Filter Context descriptor */
1710 struct i40e_fcoe_filter_context_desc {
1711         __le32 param;
1712         __le16 seqn;
1713
1714         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1715         __le16 rsvd_dmaindx;
1716
1717         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1718         __le64 flags_rsvd_lanq;
1719 };
1720
1721 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1722 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1723                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1724
1725 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1726         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1727         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1728         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1729         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1730         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1731         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1732 };
1733
1734 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1735 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1736                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1737
1738 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1739 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1740                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1741
1742 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1743 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1744                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1745
1746 enum i40e_switch_element_types {
1747         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1748         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1749         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1750         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1751         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1752         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1753         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1754         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1755         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1756 };
1757
1758 /* Supported EtherType filters */
1759 enum i40e_ether_type_index {
1760         I40E_ETHER_TYPE_1588            = 0,
1761         I40E_ETHER_TYPE_FIP             = 1,
1762         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1763         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1764         I40E_ETHER_TYPE_LLDP            = 4,
1765         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1766         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1767         I40E_ETHER_TYPE_QCN_CNM         = 7,
1768         I40E_ETHER_TYPE_8021X           = 8,
1769         I40E_ETHER_TYPE_ARP             = 9,
1770         I40E_ETHER_TYPE_RSV1            = 10,
1771         I40E_ETHER_TYPE_RSV2            = 11,
1772 };
1773
1774 /* Filter context base size is 1K */
1775 #define I40E_HASH_FILTER_BASE_SIZE      1024
1776 /* Supported Hash filter values */
1777 enum i40e_hash_filter_size {
1778         I40E_HASH_FILTER_SIZE_1K        = 0,
1779         I40E_HASH_FILTER_SIZE_2K        = 1,
1780         I40E_HASH_FILTER_SIZE_4K        = 2,
1781         I40E_HASH_FILTER_SIZE_8K        = 3,
1782         I40E_HASH_FILTER_SIZE_16K       = 4,
1783         I40E_HASH_FILTER_SIZE_32K       = 5,
1784         I40E_HASH_FILTER_SIZE_64K       = 6,
1785         I40E_HASH_FILTER_SIZE_128K      = 7,
1786         I40E_HASH_FILTER_SIZE_256K      = 8,
1787         I40E_HASH_FILTER_SIZE_512K      = 9,
1788         I40E_HASH_FILTER_SIZE_1M        = 10,
1789 };
1790
1791 /* DMA context base size is 0.5K */
1792 #define I40E_DMA_CNTX_BASE_SIZE         512
1793 /* Supported DMA context values */
1794 enum i40e_dma_cntx_size {
1795         I40E_DMA_CNTX_SIZE_512          = 0,
1796         I40E_DMA_CNTX_SIZE_1K           = 1,
1797         I40E_DMA_CNTX_SIZE_2K           = 2,
1798         I40E_DMA_CNTX_SIZE_4K           = 3,
1799         I40E_DMA_CNTX_SIZE_8K           = 4,
1800         I40E_DMA_CNTX_SIZE_16K          = 5,
1801         I40E_DMA_CNTX_SIZE_32K          = 6,
1802         I40E_DMA_CNTX_SIZE_64K          = 7,
1803         I40E_DMA_CNTX_SIZE_128K         = 8,
1804         I40E_DMA_CNTX_SIZE_256K         = 9,
1805 };
1806
1807 /* Supported Hash look up table (LUT) sizes */
1808 enum i40e_hash_lut_size {
1809         I40E_HASH_LUT_SIZE_128          = 0,
1810         I40E_HASH_LUT_SIZE_512          = 1,
1811 };
1812
1813 /* Structure to hold a per PF filter control settings */
1814 struct i40e_filter_control_settings {
1815         /* number of PE Quad Hash filter buckets */
1816         enum i40e_hash_filter_size pe_filt_num;
1817         /* number of PE Quad Hash contexts */
1818         enum i40e_dma_cntx_size pe_cntx_num;
1819         /* number of FCoE filter buckets */
1820         enum i40e_hash_filter_size fcoe_filt_num;
1821         /* number of FCoE DDP contexts */
1822         enum i40e_dma_cntx_size fcoe_cntx_num;
1823         /* size of the Hash LUT */
1824         enum i40e_hash_lut_size hash_lut_size;
1825         /* enable FDIR filters for PF and its VFs */
1826         bool enable_fdir;
1827         /* enable Ethertype filters for PF and its VFs */
1828         bool enable_ethtype;
1829         /* enable MAC/VLAN filters for PF and its VFs */
1830         bool enable_macvlan;
1831 };
1832
1833 /* Structure to hold device level control filter counts */
1834 struct i40e_control_filter_stats {
1835         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1836         u16 etype_used;       /* Used perfect EtherType filters */
1837         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1838         u16 etype_free;       /* Un-used perfect EtherType filters */
1839 };
1840
1841 enum i40e_reset_type {
1842         I40E_RESET_POR          = 0,
1843         I40E_RESET_CORER        = 1,
1844         I40E_RESET_GLOBR        = 2,
1845         I40E_RESET_EMPR         = 3,
1846 };
1847
1848 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1849 #define I40E_NVM_LLDP_CFG_PTR           0xD
1850 struct i40e_lldp_variables {
1851         u16 length;
1852         u16 adminstatus;
1853         u16 msgfasttx;
1854         u16 msgtxinterval;
1855         u16 txparams;
1856         u16 timers;
1857         u16 crc8;
1858 };
1859
1860 /* Offsets into Alternate Ram */
1861 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1862 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1863 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1864 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1865 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1866 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1867
1868 /* Alternate Ram Bandwidth Masks */
1869 #define I40E_ALT_BW_VALUE_MASK          0xFF
1870 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1871 #define I40E_ALT_BW_VALID_MASK          0x80000000
1872
1873 /* RSS Hash Table Size */
1874 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1875
1876 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1877 #define I40E_L3_SRC_SHIFT               47
1878 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1879 #define I40E_L3_V6_SRC_SHIFT            43
1880 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1881 #define I40E_L3_DST_SHIFT               35
1882 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1883 #define I40E_L3_V6_DST_SHIFT            35
1884 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1885 #define I40E_L4_SRC_SHIFT               34
1886 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1887 #define I40E_L4_DST_SHIFT               33
1888 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1889 #define I40E_VERIFY_TAG_SHIFT           31
1890 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1891
1892 #define I40E_FLEX_50_SHIFT              13
1893 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1894 #define I40E_FLEX_51_SHIFT              12
1895 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1896 #define I40E_FLEX_52_SHIFT              11
1897 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1898 #define I40E_FLEX_53_SHIFT              10
1899 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1900 #define I40E_FLEX_54_SHIFT              9
1901 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1902 #define I40E_FLEX_55_SHIFT              8
1903 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1904 #define I40E_FLEX_56_SHIFT              7
1905 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1906 #define I40E_FLEX_57_SHIFT              6
1907 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1908 #endif /* _I40E_TYPE_H_ */