drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #ifndef ETH_ALEN
  96 #define ETH_ALEN        6
  97 #endif
  98 /* Data type manipulation macros. */
  99 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 100 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 101
 102 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 103 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 104
 105 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 106 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 107
 108 /* Number of Transmit Descriptors must be a multiple of 8. */
 109 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 110 /* Number of Receive Descriptors must be a multiple of 32 if
 111  * the number of descriptors is greater than 32.
 112  */
 113 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 114
 115 #define I40E_DESC_UNUSED(R)     \
 116         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 117         (R)->next_to_clean - (R)->next_to_use - 1)
 118
 119 /* bitfields for Tx queue mapping in QTX_CTL */
 120 #define I40E_QTX_CTL_VF_QUEUE   0x0
 121 #define I40E_QTX_CTL_VM_QUEUE   0x1
 122 #define I40E_QTX_CTL_PF_QUEUE   0x2
 123
 124 /* debug masks - set these bits in hw->debug_mask to control output */
 125 enum i40e_debug_mask {
 126         I40E_DEBUG_INIT                 = 0x00000001,
 127         I40E_DEBUG_RELEASE              = 0x00000002,
 128
 129         I40E_DEBUG_LINK                 = 0x00000010,
 130         I40E_DEBUG_PHY                  = 0x00000020,
 131         I40E_DEBUG_HMC                  = 0x00000040,
 132         I40E_DEBUG_NVM                  = 0x00000080,
 133         I40E_DEBUG_LAN                  = 0x00000100,
 134         I40E_DEBUG_FLOW                 = 0x00000200,
 135         I40E_DEBUG_DCB                  = 0x00000400,
 136         I40E_DEBUG_DIAG                 = 0x00000800,
 137         I40E_DEBUG_FD                   = 0x00001000,
 138         I40E_DEBUG_PACKAGE              = 0x00002000,
 139
 140         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 141         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 142         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 143         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 144         I40E_DEBUG_AQ                   = 0x0F000000,
 145
 146         I40E_DEBUG_USER                 = 0xF0000000,
 147
 148         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 149 };
 150
 151 /* PCI Bus Info */
 152 #define I40E_PCI_LINK_STATUS            0xB2
 153 #define I40E_PCI_LINK_WIDTH             0x3F0
 154 #define I40E_PCI_LINK_WIDTH_1           0x10
 155 #define I40E_PCI_LINK_WIDTH_2           0x20
 156 #define I40E_PCI_LINK_WIDTH_4           0x40
 157 #define I40E_PCI_LINK_WIDTH_8           0x80
 158 #define I40E_PCI_LINK_SPEED             0xF
 159 #define I40E_PCI_LINK_SPEED_2500        0x1
 160 #define I40E_PCI_LINK_SPEED_5000        0x2
 161 #define I40E_PCI_LINK_SPEED_8000        0x3
 162
 163 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 164                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 165 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 166                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 167 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 168                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 169
 170 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 171                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 172 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 173                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 174 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 175                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 176 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 177                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 178 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 179                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 180
 181 #define I40E_PHY_COM_REG_PAGE                   0x1E
 182 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 183 #define I40E_PHY_LED_MANUAL_ON                  0x100
 184 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 185 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 186 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 187
 188 /* Memory types */
 189 enum i40e_memset_type {
 190         I40E_NONDMA_MEM = 0,
 191         I40E_DMA_MEM
 192 };
 193
 194 /* Memcpy types */
 195 enum i40e_memcpy_type {
 196         I40E_NONDMA_TO_NONDMA = 0,
 197         I40E_NONDMA_TO_DMA,
 198         I40E_DMA_TO_DMA,
 199         I40E_DMA_TO_NONDMA
 200 };
 201
 202 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 203 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 204
 205
 206 /* These are structs for managing the hardware information and the operations.
 207  * The structures of function pointers are filled out at init time when we
 208  * know for sure exactly which hardware we're working with.  This gives us the
 209  * flexibility of using the same main driver code but adapting to slightly
 210  * different hardware needs as new parts are developed.  For this architecture,
 211  * the Firmware and AdminQ are intended to insulate the driver from most of the
 212  * future changes, but these structures will also do part of the job.
 213  */
 214 enum i40e_mac_type {
 215         I40E_MAC_UNKNOWN = 0,
 216         I40E_MAC_XL710,
 217         I40E_MAC_VF,
 218         I40E_MAC_X722,
 219         I40E_MAC_X722_VF,
 220         I40E_MAC_GENERIC,
 221 };
 222
 223 enum i40e_media_type {
 224         I40E_MEDIA_TYPE_UNKNOWN = 0,
 225         I40E_MEDIA_TYPE_FIBER,
 226         I40E_MEDIA_TYPE_BASET,
 227         I40E_MEDIA_TYPE_BACKPLANE,
 228         I40E_MEDIA_TYPE_CX4,
 229         I40E_MEDIA_TYPE_DA,
 230         I40E_MEDIA_TYPE_VIRTUAL
 231 };
 232
 233 enum i40e_fc_mode {
 234         I40E_FC_NONE = 0,
 235         I40E_FC_RX_PAUSE,
 236         I40E_FC_TX_PAUSE,
 237         I40E_FC_FULL,
 238         I40E_FC_PFC,
 239         I40E_FC_DEFAULT
 240 };
 241
 242 enum i40e_set_fc_aq_failures {
 243         I40E_SET_FC_AQ_FAIL_NONE = 0,
 244         I40E_SET_FC_AQ_FAIL_GET = 1,
 245         I40E_SET_FC_AQ_FAIL_SET = 2,
 246         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 247         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 248 };
 249
 250 enum i40e_vsi_type {
 251         I40E_VSI_MAIN   = 0,
 252         I40E_VSI_VMDQ1  = 1,
 253         I40E_VSI_VMDQ2  = 2,
 254         I40E_VSI_CTRL   = 3,
 255         I40E_VSI_FCOE   = 4,
 256         I40E_VSI_MIRROR = 5,
 257         I40E_VSI_SRIOV  = 6,
 258         I40E_VSI_FDIR   = 7,
 259         I40E_VSI_TYPE_UNKNOWN
 260 };
 261
 262 enum i40e_queue_type {
 263         I40E_QUEUE_TYPE_RX = 0,
 264         I40E_QUEUE_TYPE_TX,
 265         I40E_QUEUE_TYPE_PE_CEQ,
 266         I40E_QUEUE_TYPE_UNKNOWN
 267 };
 268
 269 struct i40e_link_status {
 270         enum i40e_aq_phy_type phy_type;
 271         enum i40e_aq_link_speed link_speed;
 272         u8 link_info;
 273         u8 an_info;
 274         u8 req_fec_info;
 275         u8 fec_info;
 276         u8 ext_info;
 277         u8 loopback;
 278         /* is Link Status Event notification to SW enabled */
 279         bool lse_enable;
 280         u16 max_frame_size;
 281         bool crc_enable;
 282         u8 pacing;
 283         u8 requested_speeds;
 284         u8 module_type[3];
 285         /* 1st byte: module identifier */
 286 #define I40E_MODULE_TYPE_SFP            0x03
 287 #define I40E_MODULE_TYPE_QSFP           0x0D
 288         /* 2nd byte: ethernet compliance codes for 10/40G */
 289 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 290 #define I40E_MODULE_TYPE_40G_LR4        0x02
 291 #define I40E_MODULE_TYPE_40G_SR4        0x04
 292 #define I40E_MODULE_TYPE_40G_CR4        0x08
 293 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 294 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 295 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 296 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 297         /* 3rd byte: ethernet compliance codes for 1G */
 298 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 299 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 300 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 301 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 302 };
 303
 304 struct i40e_phy_info {
 305         struct i40e_link_status link_info;
 306         struct i40e_link_status link_info_old;
 307         bool get_link_info;
 308         enum i40e_media_type media_type;
 309         /* all the phy types the NVM is capable of */
 310         u64 phy_types;
 311 };
 312
 313 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 314 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 317 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 318 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 319 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 320 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 321 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 322 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 323 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 325 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 326 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 327 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 328 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 330 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 331 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 332 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 333 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 334 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 335 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 336 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 337 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 338 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 339 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 340                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 341 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 342 /*
 343  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 344  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 345  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 346  * a shift is needed to adjust for this with values larger than 31. The
 347  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 348  */
 349 #define I40E_PHY_TYPE_OFFSET 1
 350 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 351                                              I40E_PHY_TYPE_OFFSET)
 352 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 353                                              I40E_PHY_TYPE_OFFSET)
 354 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 355                                              I40E_PHY_TYPE_OFFSET)
 356 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 357                                              I40E_PHY_TYPE_OFFSET)
 358 #define I40E_HW_CAP_MAX_GPIO                    30
 359 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 360 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 361
 362 enum i40e_acpi_programming_method {
 363         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 364         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 365 };
 366
 367 #define I40E_WOL_SUPPORT_MASK                   0x1
 368 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 369 #define I40E_PROXY_SUPPORT_MASK                 0x4
 370
 371 /* Capabilities of a PF or a VF or the whole device */
 372 struct i40e_hw_capabilities {
 373         u32  switch_mode;
 374 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 375 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 376 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 377
 378         u32  management_mode;
 379         u32  mng_protocols_over_mctp;
 380 #define I40E_MNG_PROTOCOL_PLDM          0x2
 381 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 382 #define I40E_MNG_PROTOCOL_NCSI          0x8
 383         u32  npar_enable;
 384         u32  os2bmc;
 385         u32  valid_functions;
 386         bool sr_iov_1_1;
 387         bool vmdq;
 388         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 389         bool evb_802_1_qbh; /* Bridge Port Extension */
 390         bool dcb;
 391         bool fcoe;
 392         bool iscsi; /* Indicates iSCSI enabled */
 393         bool flex10_enable;
 394         bool flex10_capable;
 395         u32  flex10_mode;
 396 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 397 #define I40E_FLEX10_MODE_DCC            0x1
 398 #define I40E_FLEX10_MODE_DCI            0x2
 399
 400         u32 flex10_status;
 401 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 402 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 403
 404         bool sec_rev_disabled;
 405         bool update_disabled;
 406 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 407 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 408
 409         bool mgmt_cem;
 410         bool ieee_1588;
 411         bool iwarp;
 412         bool fd;
 413         u32 fd_filters_guaranteed;
 414         u32 fd_filters_best_effort;
 415         bool rss;
 416         u32 rss_table_size;
 417         u32 rss_table_entry_width;
 418         bool led[I40E_HW_CAP_MAX_GPIO];
 419         bool sdp[I40E_HW_CAP_MAX_GPIO];
 420         u32 nvm_image_type;
 421         u32 num_flow_director_filters;
 422         u32 num_vfs;
 423         u32 vf_base_id;
 424         u32 num_vsis;
 425         u32 num_rx_qp;
 426         u32 num_tx_qp;
 427         u32 base_queue;
 428         u32 num_msix_vectors;
 429         u32 num_msix_vectors_vf;
 430         u32 led_pin_num;
 431         u32 sdp_pin_num;
 432         u32 mdio_port_num;
 433         u32 mdio_port_mode;
 434         u8 rx_buf_chain_len;
 435         u32 enabled_tcmap;
 436         u32 maxtc;
 437         u64 wr_csr_prot;
 438         bool apm_wol_support;
 439         enum i40e_acpi_programming_method acpi_prog_method;
 440         bool proxy_support;
 441 };
 442
 443 struct i40e_mac_info {
 444         enum i40e_mac_type type;
 445         u8 addr[ETH_ALEN];
 446         u8 perm_addr[ETH_ALEN];
 447         u8 san_addr[ETH_ALEN];
 448         u8 port_addr[ETH_ALEN];
 449         u16 max_fcoeq;
 450 };
 451
 452 enum i40e_aq_resources_ids {
 453         I40E_NVM_RESOURCE_ID = 1
 454 };
 455
 456 enum i40e_aq_resource_access_type {
 457         I40E_RESOURCE_READ = 1,
 458         I40E_RESOURCE_WRITE
 459 };
 460
 461 struct i40e_nvm_info {
 462         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 463         u32 timeout;              /* [ms] */
 464         u16 sr_size;              /* Shadow RAM size in words */
 465         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 466         u16 version;              /* NVM package version */
 467         u32 eetrack;              /* NVM data version */
 468         u32 oem_ver;              /* OEM version info */
 469 };
 470
 471 /* definitions used in NVM update support */
 472
 473 enum i40e_nvmupd_cmd {
 474         I40E_NVMUPD_INVALID,
 475         I40E_NVMUPD_READ_CON,
 476         I40E_NVMUPD_READ_SNT,
 477         I40E_NVMUPD_READ_LCB,
 478         I40E_NVMUPD_READ_SA,
 479         I40E_NVMUPD_WRITE_ERA,
 480         I40E_NVMUPD_WRITE_CON,
 481         I40E_NVMUPD_WRITE_SNT,
 482         I40E_NVMUPD_WRITE_LCB,
 483         I40E_NVMUPD_WRITE_SA,
 484         I40E_NVMUPD_CSUM_CON,
 485         I40E_NVMUPD_CSUM_SA,
 486         I40E_NVMUPD_CSUM_LCB,
 487         I40E_NVMUPD_STATUS,
 488         I40E_NVMUPD_EXEC_AQ,
 489         I40E_NVMUPD_GET_AQ_RESULT,
 490 };
 491
 492 enum i40e_nvmupd_state {
 493         I40E_NVMUPD_STATE_INIT,
 494         I40E_NVMUPD_STATE_READING,
 495         I40E_NVMUPD_STATE_WRITING,
 496         I40E_NVMUPD_STATE_INIT_WAIT,
 497         I40E_NVMUPD_STATE_WRITE_WAIT,
 498         I40E_NVMUPD_STATE_ERROR
 499 };
 500
 501 /* nvm_access definition and its masks/shifts need to be accessible to
 502  * application, core driver, and shared code.  Where is the right file?
 503  */
 504 #define I40E_NVM_READ   0xB
 505 #define I40E_NVM_WRITE  0xC
 506
 507 #define I40E_NVM_MOD_PNT_MASK 0xFF
 508
 509 #define I40E_NVM_TRANS_SHIFT    8
 510 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 511 #define I40E_NVM_CON            0x0
 512 #define I40E_NVM_SNT            0x1
 513 #define I40E_NVM_LCB            0x2
 514 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 515 #define I40E_NVM_ERA            0x4
 516 #define I40E_NVM_CSUM           0x8
 517 #define I40E_NVM_EXEC           0xf
 518
 519 #define I40E_NVM_ADAPT_SHIFT    16
 520 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 521
 522 #define I40E_NVMUPD_MAX_DATA    4096
 523 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 524
 525 struct i40e_nvm_access {
 526         u32 command;
 527         u32 config;
 528         u32 offset;     /* in bytes */
 529         u32 data_size;  /* in bytes */
 530         u8 data[1];
 531 };
 532
 533 /* PCI bus types */
 534 enum i40e_bus_type {
 535         i40e_bus_type_unknown = 0,
 536         i40e_bus_type_pci,
 537         i40e_bus_type_pcix,
 538         i40e_bus_type_pci_express,
 539         i40e_bus_type_reserved
 540 };
 541
 542 /* PCI bus speeds */
 543 enum i40e_bus_speed {
 544         i40e_bus_speed_unknown  = 0,
 545         i40e_bus_speed_33       = 33,
 546         i40e_bus_speed_66       = 66,
 547         i40e_bus_speed_100      = 100,
 548         i40e_bus_speed_120      = 120,
 549         i40e_bus_speed_133      = 133,
 550         i40e_bus_speed_2500     = 2500,
 551         i40e_bus_speed_5000     = 5000,
 552         i40e_bus_speed_8000     = 8000,
 553         i40e_bus_speed_reserved
 554 };
 555
 556 /* PCI bus widths */
 557 enum i40e_bus_width {
 558         i40e_bus_width_unknown  = 0,
 559         i40e_bus_width_pcie_x1  = 1,
 560         i40e_bus_width_pcie_x2  = 2,
 561         i40e_bus_width_pcie_x4  = 4,
 562         i40e_bus_width_pcie_x8  = 8,
 563         i40e_bus_width_32       = 32,
 564         i40e_bus_width_64       = 64,
 565         i40e_bus_width_reserved
 566 };
 567
 568 /* Bus parameters */
 569 struct i40e_bus_info {
 570         enum i40e_bus_speed speed;
 571         enum i40e_bus_width width;
 572         enum i40e_bus_type type;
 573
 574         u16 func;
 575         u16 device;
 576         u16 lan_id;
 577         u16 bus_id;
 578 };
 579
 580 /* Flow control (FC) parameters */
 581 struct i40e_fc_info {
 582         enum i40e_fc_mode current_mode; /* FC mode in effect */
 583         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 584 };
 585
 586 #define I40E_MAX_TRAFFIC_CLASS          8
 587 #define I40E_MAX_USER_PRIORITY          8
 588 #define I40E_DCBX_MAX_APPS              32
 589 #define I40E_LLDPDU_SIZE                1500
 590 #define I40E_TLV_STATUS_OPER            0x1
 591 #define I40E_TLV_STATUS_SYNC            0x2
 592 #define I40E_TLV_STATUS_ERR             0x4
 593 #define I40E_CEE_OPER_MAX_APPS          3
 594 #define I40E_APP_PROTOID_FCOE           0x8906
 595 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 596 #define I40E_APP_PROTOID_FIP            0x8914
 597 #define I40E_APP_SEL_ETHTYPE            0x1
 598 #define I40E_APP_SEL_TCPIP              0x2
 599 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 600 #define I40E_CEE_APP_SEL_TCPIP          0x1
 601
 602 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 603 struct i40e_dcb_ets_config {
 604         u8 willing;
 605         u8 cbs;
 606         u8 maxtcs;
 607         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 608         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 609         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 610 };
 611
 612 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 613 struct i40e_dcb_pfc_config {
 614         u8 willing;
 615         u8 mbc;
 616         u8 pfccap;
 617         u8 pfcenable;
 618 };
 619
 620 /* CEE or IEEE 802.1Qaz Application Priority data */
 621 struct i40e_dcb_app_priority_table {
 622         u8  priority;
 623         u8  selector;
 624         u16 protocolid;
 625 };
 626
 627 struct i40e_dcbx_config {
 628         u8  dcbx_mode;
 629 #define I40E_DCBX_MODE_CEE      0x1
 630 #define I40E_DCBX_MODE_IEEE     0x2
 631         u8  app_mode;
 632 #define I40E_DCBX_APPS_NON_WILLING      0x1
 633         u32 numapps;
 634         u32 tlv_status; /* CEE mode TLV status */
 635         struct i40e_dcb_ets_config etscfg;
 636         struct i40e_dcb_ets_config etsrec;
 637         struct i40e_dcb_pfc_config pfc;
 638         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 639 };
 640
 641 /* Port hardware description */
 642 struct i40e_hw {
 643         u8 *hw_addr;
 644         void *back;
 645
 646         /* subsystem structs */
 647         struct i40e_phy_info phy;
 648         struct i40e_mac_info mac;
 649         struct i40e_bus_info bus;
 650         struct i40e_nvm_info nvm;
 651         struct i40e_fc_info fc;
 652
 653         /* pci info */
 654         u16 device_id;
 655         u16 vendor_id;
 656         u16 subsystem_device_id;
 657         u16 subsystem_vendor_id;
 658         u8 revision_id;
 659         u8 port;
 660         bool adapter_stopped;
 661
 662         /* capabilities for entire device and PCI func */
 663         struct i40e_hw_capabilities dev_caps;
 664         struct i40e_hw_capabilities func_caps;
 665
 666         /* Flow Director shared filter space */
 667         u16 fdir_shared_filter_count;
 668
 669         /* device profile info */
 670         u8  pf_id;
 671         u16 main_vsi_seid;
 672
 673         /* for multi-function MACs */
 674         u16 partition_id;
 675         u16 num_partitions;
 676         u16 num_ports;
 677
 678         /* Closest numa node to the device */
 679         u16 numa_node;
 680
 681         /* Admin Queue info */
 682         struct i40e_adminq_info aq;
 683
 684         /* state of nvm update process */
 685         enum i40e_nvmupd_state nvmupd_state;
 686         struct i40e_aq_desc nvm_wb_desc;
 687         struct i40e_virt_mem nvm_buff;
 688         bool nvm_release_on_done;
 689         u16 nvm_wait_opcode;
 690
 691         /* HMC info */
 692         struct i40e_hmc_info hmc; /* HMC info struct */
 693
 694         /* LLDP/DCBX Status */
 695         u16 dcbx_status;
 696
 697         /* DCBX info */
 698         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 699         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 700         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 701
 702         /* WoL and proxy support */
 703         u16 num_wol_proxy_filters;
 704         u16 wol_proxy_vsi_seid;
 705
 706 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 707         u64 flags;
 708
 709         /* debug mask */
 710         u32 debug_mask;
 711         char err_str[16];
 712 };
 713
 714 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 715 {
 716         return (hw->mac.type == I40E_MAC_VF ||
 717                 hw->mac.type == I40E_MAC_X722_VF);
 718 }
 719
 720 struct i40e_driver_version {
 721         u8 major_version;
 722         u8 minor_version;
 723         u8 build_version;
 724         u8 subbuild_version;
 725         u8 driver_string[32];
 726 };
 727
 728 /* RX Descriptors */
 729 union i40e_16byte_rx_desc {
 730         struct {
 731                 __le64 pkt_addr; /* Packet buffer address */
 732                 __le64 hdr_addr; /* Header buffer address */
 733         } read;
 734         struct {
 735                 struct {
 736                         struct {
 737                                 union {
 738                                         __le16 mirroring_status;
 739                                         __le16 fcoe_ctx_id;
 740                                 } mirr_fcoe;
 741                                 __le16 l2tag1;
 742                         } lo_dword;
 743                         union {
 744                                 __le32 rss; /* RSS Hash */
 745                                 __le32 fd_id; /* Flow director filter id */
 746                                 __le32 fcoe_param; /* FCoE DDP Context id */
 747                         } hi_dword;
 748                 } qword0;
 749                 struct {
 750                         /* ext status/error/pktype/length */
 751                         __le64 status_error_len;
 752                 } qword1;
 753         } wb;  /* writeback */
 754 };
 755
 756 union i40e_32byte_rx_desc {
 757         struct {
 758                 __le64  pkt_addr; /* Packet buffer address */
 759                 __le64  hdr_addr; /* Header buffer address */
 760                         /* bit 0 of hdr_buffer_addr is DD bit */
 761                 __le64  rsvd1;
 762                 __le64  rsvd2;
 763         } read;
 764         struct {
 765                 struct {
 766                         struct {
 767                                 union {
 768                                         __le16 mirroring_status;
 769                                         __le16 fcoe_ctx_id;
 770                                 } mirr_fcoe;
 771                                 __le16 l2tag1;
 772                         } lo_dword;
 773                         union {
 774                                 __le32 rss; /* RSS Hash */
 775                                 __le32 fcoe_param; /* FCoE DDP Context id */
 776                                 /* Flow director filter id in case of
 777                                  * Programming status desc WB
 778                                  */
 779                                 __le32 fd_id;
 780                         } hi_dword;
 781                 } qword0;
 782                 struct {
 783                         /* status/error/pktype/length */
 784                         __le64 status_error_len;
 785                 } qword1;
 786                 struct {
 787                         __le16 ext_status; /* extended status */
 788                         __le16 rsvd;
 789                         __le16 l2tag2_1;
 790                         __le16 l2tag2_2;
 791                 } qword2;
 792                 struct {
 793                         union {
 794                                 __le32 flex_bytes_lo;
 795                                 __le32 pe_status;
 796                         } lo_dword;
 797                         union {
 798                                 __le32 flex_bytes_hi;
 799                                 __le32 fd_id;
 800                         } hi_dword;
 801                 } qword3;
 802         } wb;  /* writeback */
 803 };
 804
 805 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 806 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 807                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 808 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 809 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 810                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 811
 812 enum i40e_rx_desc_status_bits {
 813         /* Note: These are predefined bit offsets */
 814         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 815         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 816         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 817         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 818         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 819         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 820         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 821         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 822
 823         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 824         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 825         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 826         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 827         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 828         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 829         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 830         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 831 };
 832
 833 #define I40E_RXD_QW1_STATUS_SHIFT       0
 834 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 835                                          I40E_RXD_QW1_STATUS_SHIFT)
 836
 837 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 838 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 839                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 840
 841 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 842 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 843
 844 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 845 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 846                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 847
 848 enum i40e_rx_desc_fltstat_values {
 849         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 850         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 851         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 852         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 853 };
 854
 855 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 856 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 857 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 858 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 859
 860 #define I40E_RXD_QW1_ERROR_SHIFT        19
 861 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 862
 863 enum i40e_rx_desc_error_bits {
 864         /* Note: These are predefined bit offsets */
 865         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 866         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 867         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 868         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 869         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 870         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 871         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 872         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 873         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 874 };
 875
 876 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 877         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 878         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 879         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 880         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 881         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 882 };
 883
 884 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 885 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 886
 887 /* Packet type non-ip values */
 888 enum i40e_rx_l2_ptype {
 889         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 890         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 891         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 892         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 893         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 894         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 895         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 896         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 897         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 898         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 899         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 900         I40E_RX_PTYPE_L2_ARP                            = 11,
 901         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 902         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 903         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 904         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 905         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 906         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 907         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 908         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 909         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 910         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 911         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 912         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 913         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 914         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 915 };
 916
 917 struct i40e_rx_ptype_decoded {
 918         u32 ptype:8;
 919         u32 known:1;
 920         u32 outer_ip:1;
 921         u32 outer_ip_ver:1;
 922         u32 outer_frag:1;
 923         u32 tunnel_type:3;
 924         u32 tunnel_end_prot:2;
 925         u32 tunnel_end_frag:1;
 926         u32 inner_prot:4;
 927         u32 payload_layer:3;
 928 };
 929
 930 enum i40e_rx_ptype_outer_ip {
 931         I40E_RX_PTYPE_OUTER_L2  = 0,
 932         I40E_RX_PTYPE_OUTER_IP  = 1
 933 };
 934
 935 enum i40e_rx_ptype_outer_ip_ver {
 936         I40E_RX_PTYPE_OUTER_NONE        = 0,
 937         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 938         I40E_RX_PTYPE_OUTER_IPV6        = 1
 939 };
 940
 941 enum i40e_rx_ptype_outer_fragmented {
 942         I40E_RX_PTYPE_NOT_FRAG  = 0,
 943         I40E_RX_PTYPE_FRAG      = 1
 944 };
 945
 946 enum i40e_rx_ptype_tunnel_type {
 947         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 948         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 949         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 950         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 951         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 952 };
 953
 954 enum i40e_rx_ptype_tunnel_end_prot {
 955         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 956         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 957         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 958 };
 959
 960 enum i40e_rx_ptype_inner_prot {
 961         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 962         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 963         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 964         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 965         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 966         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 967 };
 968
 969 enum i40e_rx_ptype_payload_layer {
 970         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 971         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 972         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 973         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 974 };
 975
 976 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 977 #define I40E_RX_PTYPE_SHIFT             56
 978
 979 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 980 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 981                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 982
 983 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 984 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 985                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 986
 987 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 988 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 989
 990 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 991 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 992
 993 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 994 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 995                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 996
 997 enum i40e_rx_desc_ext_status_bits {
 998         /* Note: These are predefined bit offsets */
 999         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1000         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1001         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1002         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1003         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1004         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1005         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1006 };
1007
1008 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1009 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1010
1011 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1012 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1013
1014 enum i40e_rx_desc_pe_status_bits {
1015         /* Note: These are predefined bit offsets */
1016         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1017         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1018         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1019         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1020         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1021         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1022         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1023         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1024         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1025 };
1026
1027 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1028 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1029
1030 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1031 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1032                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1033
1034 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1035 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1036                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1037
1038 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1039 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1040                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1041
1042 enum i40e_rx_prog_status_desc_status_bits {
1043         /* Note: These are predefined bit offsets */
1044         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1045         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1046 };
1047
1048 enum i40e_rx_prog_status_desc_prog_id_masks {
1049         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1050         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1051         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1052 };
1053
1054 enum i40e_rx_prog_status_desc_error_bits {
1055         /* Note: These are predefined bit offsets */
1056         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1057         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1058         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1059         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1060 };
1061
1062 #define I40E_TWO_BIT_MASK       0x3
1063 #define I40E_THREE_BIT_MASK     0x7
1064 #define I40E_FOUR_BIT_MASK      0xF
1065 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1066
1067 /* TX Descriptor */
1068 struct i40e_tx_desc {
1069         __le64 buffer_addr; /* Address of descriptor's data buf */
1070         __le64 cmd_type_offset_bsz;
1071 };
1072
1073 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1074 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1075
1076 enum i40e_tx_desc_dtype_value {
1077         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1078         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1079         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1080         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1081         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1082         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1083         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1084         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1085         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1086         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1087 };
1088
1089 #define I40E_TXD_QW1_CMD_SHIFT  4
1090 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1091
1092 enum i40e_tx_desc_cmd_bits {
1093         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1094         I40E_TX_DESC_CMD_RS                     = 0x0002,
1095         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1096         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1097         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1098         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1099         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1100         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1101         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1102         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1103         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1104         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1105         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1106         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1107         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1108         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1109         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1110         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1111 };
1112
1113 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1114 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1115                                          I40E_TXD_QW1_OFFSET_SHIFT)
1116
1117 enum i40e_tx_desc_length_fields {
1118         /* Note: These are predefined bit offsets */
1119         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1120         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1121         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1122 };
1123
1124 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1125 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1126 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1127 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1128
1129 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1130 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1131                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1132
1133 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1134 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1135
1136 /* Context descriptors */
1137 struct i40e_tx_context_desc {
1138         __le32 tunneling_params;
1139         __le16 l2tag2;
1140         __le16 rsvd;
1141         __le64 type_cmd_tso_mss;
1142 };
1143
1144 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1145 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1146
1147 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1148 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1149
1150 enum i40e_tx_ctx_desc_cmd_bits {
1151         I40E_TX_CTX_DESC_TSO            = 0x01,
1152         I40E_TX_CTX_DESC_TSYN           = 0x02,
1153         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1154         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1155         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1156         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1157         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1158         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1159         I40E_TX_CTX_DESC_SWPE           = 0x40
1160 };
1161
1162 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1163 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1164                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1165
1166 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1167 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1168                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1169
1170 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1171 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1172
1173 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1174 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1175                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1176
1177 enum i40e_tx_ctx_desc_eipt_offload {
1178         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1179         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1180         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1181         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1182 };
1183
1184 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1185 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1186                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1187
1188 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1189 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1190
1191 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1192 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1193
1194 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1195 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1196
1197 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1198
1199 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1200 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1201                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1202
1203 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1204 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1205                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1206
1207 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1208 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1209 struct i40e_nop_desc {
1210         __le64 rsvd;
1211         __le64 dtype_cmd;
1212 };
1213
1214 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1215 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1216
1217 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1218 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1219
1220 enum i40e_tx_nop_desc_cmd_bits {
1221         /* Note: These are predefined bit offsets */
1222         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1223         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1224         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1225 };
1226
1227 struct i40e_filter_program_desc {
1228         __le32 qindex_flex_ptype_vsi;
1229         __le32 rsvd;
1230         __le32 dtype_cmd_cntindex;
1231         __le32 fd_id;
1232 };
1233 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1234 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1235                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1236 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1237 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1238                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1239 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1240 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1241                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1242
1243 /* Packet Classifier Types for filters */
1244 enum i40e_filter_pctype {
1245         /* Note: Values 0-28 are reserved for future use.
1246          * Value 29, 30, 32 are not supported on XL710 and X710.
1247          */
1248         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1249         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1250         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1251         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1252         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1253         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1254         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1255         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1256         /* Note: Values 37-38 are reserved for future use.
1257          * Value 39, 40, 42 are not supported on XL710 and X710.
1258          */
1259         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1260         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1261         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1262         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1263         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1264         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1265         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1266         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1267         /* Note: Value 47 is reserved for future use */
1268         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1269         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1270         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1271         /* Note: Values 51-62 are reserved for future use */
1272         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1273 };
1274
1275 enum i40e_filter_program_desc_dest {
1276         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1277         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1278         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1279 };
1280
1281 enum i40e_filter_program_desc_fd_status {
1282         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1283         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1284         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1285         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1286 };
1287
1288 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1289 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1290                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1291
1292 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1293 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1294
1295 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1296 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1297                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1298
1299 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1300 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1301
1302 enum i40e_filter_program_desc_pcmd {
1303         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1304         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1305 };
1306
1307 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1308 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1309
1310 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1311 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1312
1313 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1314                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1315 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1316                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1317
1318 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1319                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1320 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1321
1322 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1323 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1324                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1325
1326 enum i40e_filter_type {
1327         I40E_FLOW_DIRECTOR_FLTR = 0,
1328         I40E_PE_QUAD_HASH_FLTR = 1,
1329         I40E_ETHERTYPE_FLTR,
1330         I40E_FCOE_CTX_FLTR,
1331         I40E_MAC_VLAN_FLTR,
1332         I40E_HASH_FLTR
1333 };
1334
1335 struct i40e_vsi_context {
1336         u16 seid;
1337         u16 uplink_seid;
1338         u16 vsi_number;
1339         u16 vsis_allocated;
1340         u16 vsis_unallocated;
1341         u16 flags;
1342         u8 pf_num;
1343         u8 vf_num;
1344         u8 connection_type;
1345         struct i40e_aqc_vsi_properties_data info;
1346 };
1347
1348 struct i40e_veb_context {
1349         u16 seid;
1350         u16 uplink_seid;
1351         u16 veb_number;
1352         u16 vebs_allocated;
1353         u16 vebs_unallocated;
1354         u16 flags;
1355         struct i40e_aqc_get_veb_parameters_completion info;
1356 };
1357
1358 /* Statistics collected by each port, VSI, VEB, and S-channel */
1359 struct i40e_eth_stats {
1360         u64 rx_bytes;                   /* gorc */
1361         u64 rx_unicast;                 /* uprc */
1362         u64 rx_multicast;               /* mprc */
1363         u64 rx_broadcast;               /* bprc */
1364         u64 rx_discards;                /* rdpc */
1365         u64 rx_unknown_protocol;        /* rupp */
1366         u64 tx_bytes;                   /* gotc */
1367         u64 tx_unicast;                 /* uptc */
1368         u64 tx_multicast;               /* mptc */
1369         u64 tx_broadcast;               /* bptc */
1370         u64 tx_discards;                /* tdpc */
1371         u64 tx_errors;                  /* tepc */
1372 };
1373
1374 /* Statistics collected per VEB per TC */
1375 struct i40e_veb_tc_stats {
1376         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1377         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1378         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1379         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1380 };
1381
1382 /* Statistics collected per function for FCoE */
1383 struct i40e_fcoe_stats {
1384         u64 rx_fcoe_packets;            /* fcoeprc */
1385         u64 rx_fcoe_dwords;             /* focedwrc */
1386         u64 rx_fcoe_dropped;            /* fcoerpdc */
1387         u64 tx_fcoe_packets;            /* fcoeptc */
1388         u64 tx_fcoe_dwords;             /* focedwtc */
1389         u64 fcoe_bad_fccrc;             /* fcoecrc */
1390         u64 fcoe_last_error;            /* fcoelast */
1391         u64 fcoe_ddp_count;             /* fcoeddpc */
1392 };
1393
1394 /* offset to per function FCoE statistics block */
1395 #define I40E_FCOE_VF_STAT_OFFSET        0
1396 #define I40E_FCOE_PF_STAT_OFFSET        128
1397 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1398
1399 /* Statistics collected by the MAC */
1400 struct i40e_hw_port_stats {
1401         /* eth stats collected by the port */
1402         struct i40e_eth_stats eth;
1403
1404         /* additional port specific stats */
1405         u64 tx_dropped_link_down;       /* tdold */
1406         u64 crc_errors;                 /* crcerrs */
1407         u64 illegal_bytes;              /* illerrc */
1408         u64 error_bytes;                /* errbc */
1409         u64 mac_local_faults;           /* mlfc */
1410         u64 mac_remote_faults;          /* mrfc */
1411         u64 rx_length_errors;           /* rlec */
1412         u64 link_xon_rx;                /* lxonrxc */
1413         u64 link_xoff_rx;               /* lxoffrxc */
1414         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1415         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1416         u64 link_xon_tx;                /* lxontxc */
1417         u64 link_xoff_tx;               /* lxofftxc */
1418         u64 priority_xon_tx[8];         /* pxontxc[8] */
1419         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1420         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1421         u64 rx_size_64;                 /* prc64 */
1422         u64 rx_size_127;                /* prc127 */
1423         u64 rx_size_255;                /* prc255 */
1424         u64 rx_size_511;                /* prc511 */
1425         u64 rx_size_1023;               /* prc1023 */
1426         u64 rx_size_1522;               /* prc1522 */
1427         u64 rx_size_big;                /* prc9522 */
1428         u64 rx_undersize;               /* ruc */
1429         u64 rx_fragments;               /* rfc */
1430         u64 rx_oversize;                /* roc */
1431         u64 rx_jabber;                  /* rjc */
1432         u64 tx_size_64;                 /* ptc64 */
1433         u64 tx_size_127;                /* ptc127 */
1434         u64 tx_size_255;                /* ptc255 */
1435         u64 tx_size_511;                /* ptc511 */
1436         u64 tx_size_1023;               /* ptc1023 */
1437         u64 tx_size_1522;               /* ptc1522 */
1438         u64 tx_size_big;                /* ptc9522 */
1439         u64 mac_short_packet_dropped;   /* mspdc */
1440         u64 checksum_error;             /* xec */
1441         /* flow director stats */
1442         u64 fd_atr_match;
1443         u64 fd_sb_match;
1444         u64 fd_atr_tunnel_match;
1445         u32 fd_atr_status;
1446         u32 fd_sb_status;
1447         /* EEE LPI */
1448         u32 tx_lpi_status;
1449         u32 rx_lpi_status;
1450         u64 tx_lpi_count;               /* etlpic */
1451         u64 rx_lpi_count;               /* erlpic */
1452 };
1453
1454 /* Checksum and Shadow RAM pointers */
1455 #define I40E_SR_NVM_CONTROL_WORD                0x00
1456 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1457 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1458 #define I40E_SR_OPTION_ROM_PTR                  0x05
1459 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1460 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1461 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1462 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1463 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1464 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1465 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1466 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1467 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1468 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1469 #define I40E_SR_PBA_FLAGS                       0x15
1470 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1471 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1472 #define I40E_NVM_OEM_VER_OFF                    0x83
1473 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1474 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1475 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1476 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1477 #define I40E_SR_NVM_MAP_VERSION                 0x29
1478 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1479 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1480 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1481 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1482 #define I40E_SR_VPD_PTR                         0x2F
1483 #define I40E_SR_PXE_SETUP_PTR                   0x30
1484 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1485 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1486 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1487 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1488 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1489 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1490 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1491 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1492 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1493 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1494 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1495 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1496 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1497 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1498 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1499 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1500 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1501 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1502 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1503
1504 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1505 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1506 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1507 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1508 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1509
1510 /* Shadow RAM related */
1511 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1512 #define I40E_SR_BUF_ALIGNMENT           4096
1513 #define I40E_SR_WORDS_IN_1KB            512
1514 /* Checksum should be calculated such that after adding all the words,
1515  * including the checksum word itself, the sum should be 0xBABA.
1516  */
1517 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1518
1519 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1520
1521 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1522
1523 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1524         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1525         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1526         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1527         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1528         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1529         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1530         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1531         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1532         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1533         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1534         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1535         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1536         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1537 };
1538
1539 /* FCoE DIF/DIX Context descriptor */
1540 struct i40e_fcoe_difdix_context_desc {
1541         __le64 flags_buff0_buff1_ref;
1542         __le64 difapp_msk_bias;
1543 };
1544
1545 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1546 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1547                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1548
1549 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1550         /* 2 BITS */
1551         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1552         /* 1 BIT  */
1553         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1554         /* 1 BIT  */
1555         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1556         /* 2 BITS */
1557         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1558         /* 2 BITS */
1559         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1560         /* 2 BITS */
1561         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1562         /* 2 BITS */
1563         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1564         /* 2 BITS */
1565         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1566         /* 2 BITS */
1567         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1568         /* 2 BITS */
1569         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1570         /* 2 BITS */
1571         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1572         /* 1 BIT  */
1573         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1574         /* 1 BIT  */
1575         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1576         /* 2 BITS */
1577         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1578         /* 2 BITS */
1579         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1580         /* 2 BITS */
1581         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1582         /* 2 BITS */
1583         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1584         /* 1 BIT  */
1585         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1586         /* 1 BIT  */
1587         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1588         /* 1 BIT */
1589         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1590         /* 1 BIT */
1591         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1592 };
1593
1594 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1595 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1596                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1597
1598 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1599 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1600                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1601
1602 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1603 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1604                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1605
1606 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1607 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1608                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1609
1610 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1611 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1612                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1613
1614 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1615 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1616                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1617
1618 /* FCoE DIF/DIX Buffers descriptor */
1619 struct i40e_fcoe_difdix_buffers_desc {
1620         __le64 buff_addr0;
1621         __le64 buff_addr1;
1622 };
1623
1624 /* FCoE DDP Context descriptor */
1625 struct i40e_fcoe_ddp_context_desc {
1626         __le64 rsvd;
1627         __le64 type_cmd_foff_lsize;
1628 };
1629
1630 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1631 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1632                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1633
1634 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1635 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1636                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1637
1638 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1639         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1640         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1641         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1642         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1643         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1644         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1645 };
1646
1647 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1648 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1649                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1650
1651 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1652 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1653                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1654
1655 /* FCoE DDP/DWO Queue Context descriptor */
1656 struct i40e_fcoe_queue_context_desc {
1657         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1658         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1659 };
1660
1661 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1662 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1663                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1664
1665 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1666 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1667                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1668
1669 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1670 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1671                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1672
1673 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1674 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1675                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1676
1677 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1678         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1679         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1680 };
1681
1682 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1683 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1684                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1685
1686 /* FCoE DDP/DWO Filter Context descriptor */
1687 struct i40e_fcoe_filter_context_desc {
1688         __le32 param;
1689         __le16 seqn;
1690
1691         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1692         __le16 rsvd_dmaindx;
1693
1694         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1695         __le64 flags_rsvd_lanq;
1696 };
1697
1698 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1699 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1700                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1701
1702 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1703         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1704         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1705         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1706         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1707         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1708         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1709 };
1710
1711 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1712 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1713                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1714
1715 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1716 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1717                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1718
1719 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1720 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1721                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1722
1723 enum i40e_switch_element_types {
1724         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1725         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1726         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1727         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1728         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1729         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1730         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1731         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1732         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1733 };
1734
1735 /* Supported EtherType filters */
1736 enum i40e_ether_type_index {
1737         I40E_ETHER_TYPE_1588            = 0,
1738         I40E_ETHER_TYPE_FIP             = 1,
1739         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1740         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1741         I40E_ETHER_TYPE_LLDP            = 4,
1742         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1743         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1744         I40E_ETHER_TYPE_QCN_CNM         = 7,
1745         I40E_ETHER_TYPE_8021X           = 8,
1746         I40E_ETHER_TYPE_ARP             = 9,
1747         I40E_ETHER_TYPE_RSV1            = 10,
1748         I40E_ETHER_TYPE_RSV2            = 11,
1749 };
1750
1751 /* Filter context base size is 1K */
1752 #define I40E_HASH_FILTER_BASE_SIZE      1024
1753 /* Supported Hash filter values */
1754 enum i40e_hash_filter_size {
1755         I40E_HASH_FILTER_SIZE_1K        = 0,
1756         I40E_HASH_FILTER_SIZE_2K        = 1,
1757         I40E_HASH_FILTER_SIZE_4K        = 2,
1758         I40E_HASH_FILTER_SIZE_8K        = 3,
1759         I40E_HASH_FILTER_SIZE_16K       = 4,
1760         I40E_HASH_FILTER_SIZE_32K       = 5,
1761         I40E_HASH_FILTER_SIZE_64K       = 6,
1762         I40E_HASH_FILTER_SIZE_128K      = 7,
1763         I40E_HASH_FILTER_SIZE_256K      = 8,
1764         I40E_HASH_FILTER_SIZE_512K      = 9,
1765         I40E_HASH_FILTER_SIZE_1M        = 10,
1766 };
1767
1768 /* DMA context base size is 0.5K */
1769 #define I40E_DMA_CNTX_BASE_SIZE         512
1770 /* Supported DMA context values */
1771 enum i40e_dma_cntx_size {
1772         I40E_DMA_CNTX_SIZE_512          = 0,
1773         I40E_DMA_CNTX_SIZE_1K           = 1,
1774         I40E_DMA_CNTX_SIZE_2K           = 2,
1775         I40E_DMA_CNTX_SIZE_4K           = 3,
1776         I40E_DMA_CNTX_SIZE_8K           = 4,
1777         I40E_DMA_CNTX_SIZE_16K          = 5,
1778         I40E_DMA_CNTX_SIZE_32K          = 6,
1779         I40E_DMA_CNTX_SIZE_64K          = 7,
1780         I40E_DMA_CNTX_SIZE_128K         = 8,
1781         I40E_DMA_CNTX_SIZE_256K         = 9,
1782 };
1783
1784 /* Supported Hash look up table (LUT) sizes */
1785 enum i40e_hash_lut_size {
1786         I40E_HASH_LUT_SIZE_128          = 0,
1787         I40E_HASH_LUT_SIZE_512          = 1,
1788 };
1789
1790 /* Structure to hold a per PF filter control settings */
1791 struct i40e_filter_control_settings {
1792         /* number of PE Quad Hash filter buckets */
1793         enum i40e_hash_filter_size pe_filt_num;
1794         /* number of PE Quad Hash contexts */
1795         enum i40e_dma_cntx_size pe_cntx_num;
1796         /* number of FCoE filter buckets */
1797         enum i40e_hash_filter_size fcoe_filt_num;
1798         /* number of FCoE DDP contexts */
1799         enum i40e_dma_cntx_size fcoe_cntx_num;
1800         /* size of the Hash LUT */
1801         enum i40e_hash_lut_size hash_lut_size;
1802         /* enable FDIR filters for PF and its VFs */
1803         bool enable_fdir;
1804         /* enable Ethertype filters for PF and its VFs */
1805         bool enable_ethtype;
1806         /* enable MAC/VLAN filters for PF and its VFs */
1807         bool enable_macvlan;
1808 };
1809
1810 /* Structure to hold device level control filter counts */
1811 struct i40e_control_filter_stats {
1812         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1813         u16 etype_used;       /* Used perfect EtherType filters */
1814         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1815         u16 etype_free;       /* Un-used perfect EtherType filters */
1816 };
1817
1818 enum i40e_reset_type {
1819         I40E_RESET_POR          = 0,
1820         I40E_RESET_CORER        = 1,
1821         I40E_RESET_GLOBR        = 2,
1822         I40E_RESET_EMPR         = 3,
1823 };
1824
1825 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1826 #define I40E_NVM_LLDP_CFG_PTR           0xD
1827 struct i40e_lldp_variables {
1828         u16 length;
1829         u16 adminstatus;
1830         u16 msgfasttx;
1831         u16 msgtxinterval;
1832         u16 txparams;
1833         u16 timers;
1834         u16 crc8;
1835 };
1836
1837 /* Offsets into Alternate Ram */
1838 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1839 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1840 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1841 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1842 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1843 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1844
1845 /* Alternate Ram Bandwidth Masks */
1846 #define I40E_ALT_BW_VALUE_MASK          0xFF
1847 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1848 #define I40E_ALT_BW_VALID_MASK          0x80000000
1849
1850 /* RSS Hash Table Size */
1851 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1852
1853 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1854 #define I40E_L3_SRC_SHIFT               47
1855 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1856 #define I40E_L3_V6_SRC_SHIFT            43
1857 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1858 #define I40E_L3_DST_SHIFT               35
1859 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1860 #define I40E_L3_V6_DST_SHIFT            35
1861 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1862 #define I40E_L4_SRC_SHIFT               34
1863 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1864 #define I40E_L4_DST_SHIFT               33
1865 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1866 #define I40E_VERIFY_TAG_SHIFT           31
1867 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1868
1869 #define I40E_FLEX_50_SHIFT              13
1870 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1871 #define I40E_FLEX_51_SHIFT              12
1872 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1873 #define I40E_FLEX_52_SHIFT              11
1874 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1875 #define I40E_FLEX_53_SHIFT              10
1876 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1877 #define I40E_FLEX_54_SHIFT              9
1878 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1879 #define I40E_FLEX_55_SHIFT              8
1880 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1881 #define I40E_FLEX_56_SHIFT              7
1882 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1883 #define I40E_FLEX_57_SHIFT              6
1884 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1885
1886 /* Version format for Dynamic Device Personalization(DDP) */
1887 struct i40e_ddp_version {
1888         u8 major;
1889         u8 minor;
1890         u8 update;
1891         u8 draft;
1892 };
1893
1894 #define I40E_DDP_NAME_SIZE      32
1895
1896 /* Package header */
1897 struct i40e_package_header {
1898         struct i40e_ddp_version version;
1899         u32 segment_count;
1900         u32 segment_offset[1];
1901 };
1902
1903 /* Generic segment header */
1904 struct i40e_generic_seg_header {
1905 #define SEGMENT_TYPE_METADATA   0x00000001
1906 #define SEGMENT_TYPE_NOTES      0x00000002
1907 #define SEGMENT_TYPE_I40E       0x00000011
1908 #define SEGMENT_TYPE_X722       0x00000012
1909         u32 type;
1910         struct i40e_ddp_version version;
1911         u32 size;
1912         char name[I40E_DDP_NAME_SIZE];
1913 };
1914
1915 struct i40e_metadata_segment {
1916         struct i40e_generic_seg_header header;
1917         struct i40e_ddp_version version;
1918         u32 track_id;
1919         char     name[I40E_DDP_NAME_SIZE];
1920 };
1921
1922 struct i40e_device_id_entry {
1923         u32 vendor_dev_id;
1924         u32 sub_vendor_dev_id;
1925 };
1926
1927 struct i40e_profile_segment {
1928         struct i40e_generic_seg_header header;
1929         struct i40e_ddp_version version;
1930         char name[I40E_DDP_NAME_SIZE];
1931         u32 device_table_count;
1932         struct i40e_device_id_entry device_table[1];
1933 };
1934
1935 struct i40e_section_table {
1936         u32 section_count;
1937         u32 section_offset[1];
1938 };
1939
1940 struct i40e_profile_section_header {
1941         u16 tbl_size;
1942         u16 data_end;
1943         struct {
1944 #define SECTION_TYPE_INFO       0x00000010
1945 #define SECTION_TYPE_MMIO       0x00000800
1946 #define SECTION_TYPE_AQ         0x00000801
1947 #define SECTION_TYPE_NOTE       0x80000000
1948 #define SECTION_TYPE_NAME       0x80000001
1949                 u32 type;
1950                 u32 offset;
1951                 u32 size;
1952         } section;
1953 };
1954
1955 struct i40e_profile_info {
1956         u32 track_id;
1957         struct i40e_ddp_version version;
1958         u8 op;
1959 #define I40E_DDP_ADD_TRACKID            0x01
1960 #define I40E_DDP_REMOVE_TRACKID 0x02
1961         u8 reserved[7];
1962         u8 name[I40E_DDP_NAME_SIZE];
1963 };
1964 #endif /* _I40E_TYPE_H_ */