drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #ifndef ETH_ALEN
  96 #define ETH_ALEN        6
  97 #endif
  98 /* Data type manipulation macros. */
  99 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 100 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 101
 102 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 103 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 104
 105 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 106 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 107
 108 /* Number of Transmit Descriptors must be a multiple of 8. */
 109 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 110 /* Number of Receive Descriptors must be a multiple of 32 if
 111  * the number of descriptors is greater than 32.
 112  */
 113 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 114
 115 #define I40E_DESC_UNUSED(R)     \
 116         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 117         (R)->next_to_clean - (R)->next_to_use - 1)
 118
 119 /* bitfields for Tx queue mapping in QTX_CTL */
 120 #define I40E_QTX_CTL_VF_QUEUE   0x0
 121 #define I40E_QTX_CTL_VM_QUEUE   0x1
 122 #define I40E_QTX_CTL_PF_QUEUE   0x2
 123
 124 /* debug masks - set these bits in hw->debug_mask to control output */
 125 enum i40e_debug_mask {
 126         I40E_DEBUG_INIT                 = 0x00000001,
 127         I40E_DEBUG_RELEASE              = 0x00000002,
 128
 129         I40E_DEBUG_LINK                 = 0x00000010,
 130         I40E_DEBUG_PHY                  = 0x00000020,
 131         I40E_DEBUG_HMC                  = 0x00000040,
 132         I40E_DEBUG_NVM                  = 0x00000080,
 133         I40E_DEBUG_LAN                  = 0x00000100,
 134         I40E_DEBUG_FLOW                 = 0x00000200,
 135         I40E_DEBUG_DCB                  = 0x00000400,
 136         I40E_DEBUG_DIAG                 = 0x00000800,
 137         I40E_DEBUG_FD                   = 0x00001000,
 138         I40E_DEBUG_PACKAGE              = 0x00002000,
 139
 140         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 141         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 142         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 143         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 144         I40E_DEBUG_AQ                   = 0x0F000000,
 145
 146         I40E_DEBUG_USER                 = 0xF0000000,
 147
 148         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 149 };
 150
 151 /* PCI Bus Info */
 152 #define I40E_PCI_LINK_STATUS            0xB2
 153 #define I40E_PCI_LINK_WIDTH             0x3F0
 154 #define I40E_PCI_LINK_WIDTH_1           0x10
 155 #define I40E_PCI_LINK_WIDTH_2           0x20
 156 #define I40E_PCI_LINK_WIDTH_4           0x40
 157 #define I40E_PCI_LINK_WIDTH_8           0x80
 158 #define I40E_PCI_LINK_SPEED             0xF
 159 #define I40E_PCI_LINK_SPEED_2500        0x1
 160 #define I40E_PCI_LINK_SPEED_5000        0x2
 161 #define I40E_PCI_LINK_SPEED_8000        0x3
 162
 163 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 164                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 165 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 166                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 167 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 168                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 169
 170 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 171                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 172 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 173                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 174 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 175                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 176 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 177                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 178 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 179                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 180
 181 #define I40E_PHY_COM_REG_PAGE                   0x1E
 182 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 183 #define I40E_PHY_LED_MANUAL_ON                  0x100
 184 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 185 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 186 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 187
 188 /* Memory types */
 189 enum i40e_memset_type {
 190         I40E_NONDMA_MEM = 0,
 191         I40E_DMA_MEM
 192 };
 193
 194 /* Memcpy types */
 195 enum i40e_memcpy_type {
 196         I40E_NONDMA_TO_NONDMA = 0,
 197         I40E_NONDMA_TO_DMA,
 198         I40E_DMA_TO_DMA,
 199         I40E_DMA_TO_NONDMA
 200 };
 201
 202 /* These are structs for managing the hardware information and the operations.
 203  * The structures of function pointers are filled out at init time when we
 204  * know for sure exactly which hardware we're working with.  This gives us the
 205  * flexibility of using the same main driver code but adapting to slightly
 206  * different hardware needs as new parts are developed.  For this architecture,
 207  * the Firmware and AdminQ are intended to insulate the driver from most of the
 208  * future changes, but these structures will also do part of the job.
 209  */
 210 enum i40e_mac_type {
 211         I40E_MAC_UNKNOWN = 0,
 212         I40E_MAC_XL710,
 213         I40E_MAC_VF,
 214         I40E_MAC_X722,
 215         I40E_MAC_X722_VF,
 216         I40E_MAC_GENERIC,
 217 };
 218
 219 enum i40e_media_type {
 220         I40E_MEDIA_TYPE_UNKNOWN = 0,
 221         I40E_MEDIA_TYPE_FIBER,
 222         I40E_MEDIA_TYPE_BASET,
 223         I40E_MEDIA_TYPE_BACKPLANE,
 224         I40E_MEDIA_TYPE_CX4,
 225         I40E_MEDIA_TYPE_DA,
 226         I40E_MEDIA_TYPE_VIRTUAL
 227 };
 228
 229 enum i40e_fc_mode {
 230         I40E_FC_NONE = 0,
 231         I40E_FC_RX_PAUSE,
 232         I40E_FC_TX_PAUSE,
 233         I40E_FC_FULL,
 234         I40E_FC_PFC,
 235         I40E_FC_DEFAULT
 236 };
 237
 238 enum i40e_set_fc_aq_failures {
 239         I40E_SET_FC_AQ_FAIL_NONE = 0,
 240         I40E_SET_FC_AQ_FAIL_GET = 1,
 241         I40E_SET_FC_AQ_FAIL_SET = 2,
 242         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 243         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 244 };
 245
 246 enum i40e_vsi_type {
 247         I40E_VSI_MAIN   = 0,
 248         I40E_VSI_VMDQ1  = 1,
 249         I40E_VSI_VMDQ2  = 2,
 250         I40E_VSI_CTRL   = 3,
 251         I40E_VSI_FCOE   = 4,
 252         I40E_VSI_MIRROR = 5,
 253         I40E_VSI_SRIOV  = 6,
 254         I40E_VSI_FDIR   = 7,
 255         I40E_VSI_TYPE_UNKNOWN
 256 };
 257
 258 enum i40e_queue_type {
 259         I40E_QUEUE_TYPE_RX = 0,
 260         I40E_QUEUE_TYPE_TX,
 261         I40E_QUEUE_TYPE_PE_CEQ,
 262         I40E_QUEUE_TYPE_UNKNOWN
 263 };
 264
 265 struct i40e_link_status {
 266         enum i40e_aq_phy_type phy_type;
 267         enum i40e_aq_link_speed link_speed;
 268         u8 link_info;
 269         u8 an_info;
 270         u8 req_fec_info;
 271         u8 fec_info;
 272         u8 ext_info;
 273         u8 loopback;
 274         /* is Link Status Event notification to SW enabled */
 275         bool lse_enable;
 276         u16 max_frame_size;
 277         bool crc_enable;
 278         u8 pacing;
 279         u8 requested_speeds;
 280         u8 module_type[3];
 281         /* 1st byte: module identifier */
 282 #define I40E_MODULE_TYPE_SFP            0x03
 283 #define I40E_MODULE_TYPE_QSFP           0x0D
 284         /* 2nd byte: ethernet compliance codes for 10/40G */
 285 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 286 #define I40E_MODULE_TYPE_40G_LR4        0x02
 287 #define I40E_MODULE_TYPE_40G_SR4        0x04
 288 #define I40E_MODULE_TYPE_40G_CR4        0x08
 289 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 290 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 291 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 292 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 293         /* 3rd byte: ethernet compliance codes for 1G */
 294 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 295 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 296 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 297 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 298 };
 299
 300 struct i40e_phy_info {
 301         struct i40e_link_status link_info;
 302         struct i40e_link_status link_info_old;
 303         bool get_link_info;
 304         enum i40e_media_type media_type;
 305         /* all the phy types the NVM is capable of */
 306         u64 phy_types;
 307 };
 308
 309 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 310 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 311 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 312 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 313 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 314 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 315 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 316 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 317 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 318 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 319 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 320 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 321 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 322 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 323 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 324 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 325 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 326 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 327 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 328 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 329 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 330 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 331 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 332 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 333 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 334 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 335 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 336                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 337 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 338 /*
 339  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 340  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 341  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 342  * a shift is needed to adjust for this with values larger than 31. The
 343  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 344  */
 345 #define I40E_PHY_TYPE_OFFSET 1
 346 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 347                                              I40E_PHY_TYPE_OFFSET)
 348 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 349                                              I40E_PHY_TYPE_OFFSET)
 350 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 351                                              I40E_PHY_TYPE_OFFSET)
 352 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 353                                              I40E_PHY_TYPE_OFFSET)
 354 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 355                                              I40E_PHY_TYPE_OFFSET)
 356 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 357                                              I40E_PHY_TYPE_OFFSET)
 358 #define I40E_HW_CAP_MAX_GPIO                    30
 359 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 360 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 361
 362 enum i40e_acpi_programming_method {
 363         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 364         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 365 };
 366
 367 #define I40E_WOL_SUPPORT_MASK                   0x1
 368 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 369 #define I40E_PROXY_SUPPORT_MASK                 0x4
 370
 371 /* Capabilities of a PF or a VF or the whole device */
 372 struct i40e_hw_capabilities {
 373         u32  switch_mode;
 374 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 375 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 376 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 377
 378         u32  management_mode;
 379         u32  mng_protocols_over_mctp;
 380 #define I40E_MNG_PROTOCOL_PLDM          0x2
 381 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 382 #define I40E_MNG_PROTOCOL_NCSI          0x8
 383         u32  npar_enable;
 384         u32  os2bmc;
 385         u32  valid_functions;
 386         bool sr_iov_1_1;
 387         bool vmdq;
 388         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 389         bool evb_802_1_qbh; /* Bridge Port Extension */
 390         bool dcb;
 391         bool fcoe;
 392         bool iscsi; /* Indicates iSCSI enabled */
 393         bool flex10_enable;
 394         bool flex10_capable;
 395         u32  flex10_mode;
 396 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 397 #define I40E_FLEX10_MODE_DCC            0x1
 398 #define I40E_FLEX10_MODE_DCI            0x2
 399
 400         u32 flex10_status;
 401 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 402 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 403
 404         bool sec_rev_disabled;
 405         bool update_disabled;
 406 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 407 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 408
 409         bool mgmt_cem;
 410         bool ieee_1588;
 411         bool iwarp;
 412         bool fd;
 413         u32 fd_filters_guaranteed;
 414         u32 fd_filters_best_effort;
 415         bool rss;
 416         u32 rss_table_size;
 417         u32 rss_table_entry_width;
 418         bool led[I40E_HW_CAP_MAX_GPIO];
 419         bool sdp[I40E_HW_CAP_MAX_GPIO];
 420         u32 nvm_image_type;
 421         u32 num_flow_director_filters;
 422         u32 num_vfs;
 423         u32 vf_base_id;
 424         u32 num_vsis;
 425         u32 num_rx_qp;
 426         u32 num_tx_qp;
 427         u32 base_queue;
 428         u32 num_msix_vectors;
 429         u32 num_msix_vectors_vf;
 430         u32 led_pin_num;
 431         u32 sdp_pin_num;
 432         u32 mdio_port_num;
 433         u32 mdio_port_mode;
 434         u8 rx_buf_chain_len;
 435         u32 enabled_tcmap;
 436         u32 maxtc;
 437         u64 wr_csr_prot;
 438         bool apm_wol_support;
 439         enum i40e_acpi_programming_method acpi_prog_method;
 440         bool proxy_support;
 441 };
 442
 443 struct i40e_mac_info {
 444         enum i40e_mac_type type;
 445         u8 addr[ETH_ALEN];
 446         u8 perm_addr[ETH_ALEN];
 447         u8 san_addr[ETH_ALEN];
 448         u8 port_addr[ETH_ALEN];
 449         u16 max_fcoeq;
 450 };
 451
 452 enum i40e_aq_resources_ids {
 453         I40E_NVM_RESOURCE_ID = 1
 454 };
 455
 456 enum i40e_aq_resource_access_type {
 457         I40E_RESOURCE_READ = 1,
 458         I40E_RESOURCE_WRITE
 459 };
 460
 461 struct i40e_nvm_info {
 462         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 463         u32 timeout;              /* [ms] */
 464         u16 sr_size;              /* Shadow RAM size in words */
 465         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 466         u16 version;              /* NVM package version */
 467         u32 eetrack;              /* NVM data version */
 468         u32 oem_ver;              /* OEM version info */
 469 };
 470
 471 /* definitions used in NVM update support */
 472
 473 enum i40e_nvmupd_cmd {
 474         I40E_NVMUPD_INVALID,
 475         I40E_NVMUPD_READ_CON,
 476         I40E_NVMUPD_READ_SNT,
 477         I40E_NVMUPD_READ_LCB,
 478         I40E_NVMUPD_READ_SA,
 479         I40E_NVMUPD_WRITE_ERA,
 480         I40E_NVMUPD_WRITE_CON,
 481         I40E_NVMUPD_WRITE_SNT,
 482         I40E_NVMUPD_WRITE_LCB,
 483         I40E_NVMUPD_WRITE_SA,
 484         I40E_NVMUPD_CSUM_CON,
 485         I40E_NVMUPD_CSUM_SA,
 486         I40E_NVMUPD_CSUM_LCB,
 487         I40E_NVMUPD_STATUS,
 488         I40E_NVMUPD_EXEC_AQ,
 489         I40E_NVMUPD_GET_AQ_RESULT,
 490 };
 491
 492 enum i40e_nvmupd_state {
 493         I40E_NVMUPD_STATE_INIT,
 494         I40E_NVMUPD_STATE_READING,
 495         I40E_NVMUPD_STATE_WRITING,
 496         I40E_NVMUPD_STATE_INIT_WAIT,
 497         I40E_NVMUPD_STATE_WRITE_WAIT,
 498         I40E_NVMUPD_STATE_ERROR
 499 };
 500
 501 /* nvm_access definition and its masks/shifts need to be accessible to
 502  * application, core driver, and shared code.  Where is the right file?
 503  */
 504 #define I40E_NVM_READ   0xB
 505 #define I40E_NVM_WRITE  0xC
 506
 507 #define I40E_NVM_MOD_PNT_MASK 0xFF
 508
 509 #define I40E_NVM_TRANS_SHIFT    8
 510 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 511 #define I40E_NVM_CON            0x0
 512 #define I40E_NVM_SNT            0x1
 513 #define I40E_NVM_LCB            0x2
 514 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 515 #define I40E_NVM_ERA            0x4
 516 #define I40E_NVM_CSUM           0x8
 517 #define I40E_NVM_EXEC           0xf
 518
 519 #define I40E_NVM_ADAPT_SHIFT    16
 520 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 521
 522 #define I40E_NVMUPD_MAX_DATA    4096
 523 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 524
 525 struct i40e_nvm_access {
 526         u32 command;
 527         u32 config;
 528         u32 offset;     /* in bytes */
 529         u32 data_size;  /* in bytes */
 530         u8 data[1];
 531 };
 532
 533 /* (Q)SFP module access definitions */
 534 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 535 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 536 #define I40E_MODULE_TYPE_ADDR           0x00
 537 #define I40E_MODULE_REVISION_ADDR       0x01
 538 #define I40E_MODULE_SFF_8472_COMP       0x5E
 539 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 540 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 541 #define I40E_MODULE_SFF_DIAG_CAPAB      0x40
 542 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 543 #define I40E_MODULE_TYPE_QSFP28         0x11
 544 #define I40E_MODULE_QSFP_MAX_LEN        640
 545
 546 /* PCI bus types */
 547 enum i40e_bus_type {
 548         i40e_bus_type_unknown = 0,
 549         i40e_bus_type_pci,
 550         i40e_bus_type_pcix,
 551         i40e_bus_type_pci_express,
 552         i40e_bus_type_reserved
 553 };
 554
 555 /* PCI bus speeds */
 556 enum i40e_bus_speed {
 557         i40e_bus_speed_unknown  = 0,
 558         i40e_bus_speed_33       = 33,
 559         i40e_bus_speed_66       = 66,
 560         i40e_bus_speed_100      = 100,
 561         i40e_bus_speed_120      = 120,
 562         i40e_bus_speed_133      = 133,
 563         i40e_bus_speed_2500     = 2500,
 564         i40e_bus_speed_5000     = 5000,
 565         i40e_bus_speed_8000     = 8000,
 566         i40e_bus_speed_reserved
 567 };
 568
 569 /* PCI bus widths */
 570 enum i40e_bus_width {
 571         i40e_bus_width_unknown  = 0,
 572         i40e_bus_width_pcie_x1  = 1,
 573         i40e_bus_width_pcie_x2  = 2,
 574         i40e_bus_width_pcie_x4  = 4,
 575         i40e_bus_width_pcie_x8  = 8,
 576         i40e_bus_width_32       = 32,
 577         i40e_bus_width_64       = 64,
 578         i40e_bus_width_reserved
 579 };
 580
 581 /* Bus parameters */
 582 struct i40e_bus_info {
 583         enum i40e_bus_speed speed;
 584         enum i40e_bus_width width;
 585         enum i40e_bus_type type;
 586
 587         u16 func;
 588         u16 device;
 589         u16 lan_id;
 590         u16 bus_id;
 591 };
 592
 593 /* Flow control (FC) parameters */
 594 struct i40e_fc_info {
 595         enum i40e_fc_mode current_mode; /* FC mode in effect */
 596         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 597 };
 598
 599 #define I40E_MAX_TRAFFIC_CLASS          8
 600 #define I40E_MAX_USER_PRIORITY          8
 601 #define I40E_DCBX_MAX_APPS              32
 602 #define I40E_LLDPDU_SIZE                1500
 603 #define I40E_TLV_STATUS_OPER            0x1
 604 #define I40E_TLV_STATUS_SYNC            0x2
 605 #define I40E_TLV_STATUS_ERR             0x4
 606 #define I40E_CEE_OPER_MAX_APPS          3
 607 #define I40E_APP_PROTOID_FCOE           0x8906
 608 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 609 #define I40E_APP_PROTOID_FIP            0x8914
 610 #define I40E_APP_SEL_ETHTYPE            0x1
 611 #define I40E_APP_SEL_TCPIP              0x2
 612 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 613 #define I40E_CEE_APP_SEL_TCPIP          0x1
 614
 615 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 616 struct i40e_dcb_ets_config {
 617         u8 willing;
 618         u8 cbs;
 619         u8 maxtcs;
 620         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 621         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 622         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 623 };
 624
 625 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 626 struct i40e_dcb_pfc_config {
 627         u8 willing;
 628         u8 mbc;
 629         u8 pfccap;
 630         u8 pfcenable;
 631 };
 632
 633 /* CEE or IEEE 802.1Qaz Application Priority data */
 634 struct i40e_dcb_app_priority_table {
 635         u8  priority;
 636         u8  selector;
 637         u16 protocolid;
 638 };
 639
 640 struct i40e_dcbx_config {
 641         u8  dcbx_mode;
 642 #define I40E_DCBX_MODE_CEE      0x1
 643 #define I40E_DCBX_MODE_IEEE     0x2
 644         u8  app_mode;
 645 #define I40E_DCBX_APPS_NON_WILLING      0x1
 646         u32 numapps;
 647         u32 tlv_status; /* CEE mode TLV status */
 648         struct i40e_dcb_ets_config etscfg;
 649         struct i40e_dcb_ets_config etsrec;
 650         struct i40e_dcb_pfc_config pfc;
 651         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 652 };
 653
 654 /* Port hardware description */
 655 struct i40e_hw {
 656         u8 *hw_addr;
 657         void *back;
 658
 659         /* subsystem structs */
 660         struct i40e_phy_info phy;
 661         struct i40e_mac_info mac;
 662         struct i40e_bus_info bus;
 663         struct i40e_nvm_info nvm;
 664         struct i40e_fc_info fc;
 665
 666         /* pci info */
 667         u16 device_id;
 668         u16 vendor_id;
 669         u16 subsystem_device_id;
 670         u16 subsystem_vendor_id;
 671         u8 revision_id;
 672         u8 port;
 673         bool adapter_stopped;
 674
 675         /* capabilities for entire device and PCI func */
 676         struct i40e_hw_capabilities dev_caps;
 677         struct i40e_hw_capabilities func_caps;
 678
 679         /* Flow Director shared filter space */
 680         u16 fdir_shared_filter_count;
 681
 682         /* device profile info */
 683         u8  pf_id;
 684         u16 main_vsi_seid;
 685
 686         /* for multi-function MACs */
 687         u16 partition_id;
 688         u16 num_partitions;
 689         u16 num_ports;
 690
 691         /* Closest numa node to the device */
 692         u16 numa_node;
 693
 694         /* Admin Queue info */
 695         struct i40e_adminq_info aq;
 696
 697         /* state of nvm update process */
 698         enum i40e_nvmupd_state nvmupd_state;
 699         struct i40e_aq_desc nvm_wb_desc;
 700         struct i40e_virt_mem nvm_buff;
 701         bool nvm_release_on_done;
 702         u16 nvm_wait_opcode;
 703
 704         /* HMC info */
 705         struct i40e_hmc_info hmc; /* HMC info struct */
 706
 707         /* LLDP/DCBX Status */
 708         u16 dcbx_status;
 709
 710         /* DCBX info */
 711         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 712         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 713         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 714
 715         /* WoL and proxy support */
 716         u16 num_wol_proxy_filters;
 717         u16 wol_proxy_vsi_seid;
 718
 719 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 720 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 721 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 722         u64 flags;
 723
 724         /* Used in set switch config AQ command */
 725         u16 switch_tag;
 726         u16 first_tag;
 727         u16 second_tag;
 728
 729         /* debug mask */
 730         u32 debug_mask;
 731         char err_str[16];
 732 };
 733
 734 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 735 {
 736         return (hw->mac.type == I40E_MAC_VF ||
 737                 hw->mac.type == I40E_MAC_X722_VF);
 738 }
 739
 740 struct i40e_driver_version {
 741         u8 major_version;
 742         u8 minor_version;
 743         u8 build_version;
 744         u8 subbuild_version;
 745         u8 driver_string[32];
 746 };
 747
 748 /* RX Descriptors */
 749 union i40e_16byte_rx_desc {
 750         struct {
 751                 __le64 pkt_addr; /* Packet buffer address */
 752                 __le64 hdr_addr; /* Header buffer address */
 753         } read;
 754         struct {
 755                 struct {
 756                         struct {
 757                                 union {
 758                                         __le16 mirroring_status;
 759                                         __le16 fcoe_ctx_id;
 760                                 } mirr_fcoe;
 761                                 __le16 l2tag1;
 762                         } lo_dword;
 763                         union {
 764                                 __le32 rss; /* RSS Hash */
 765                                 __le32 fd_id; /* Flow director filter id */
 766                                 __le32 fcoe_param; /* FCoE DDP Context id */
 767                         } hi_dword;
 768                 } qword0;
 769                 struct {
 770                         /* ext status/error/pktype/length */
 771                         __le64 status_error_len;
 772                 } qword1;
 773         } wb;  /* writeback */
 774 };
 775
 776 union i40e_32byte_rx_desc {
 777         struct {
 778                 __le64  pkt_addr; /* Packet buffer address */
 779                 __le64  hdr_addr; /* Header buffer address */
 780                         /* bit 0 of hdr_buffer_addr is DD bit */
 781                 __le64  rsvd1;
 782                 __le64  rsvd2;
 783         } read;
 784         struct {
 785                 struct {
 786                         struct {
 787                                 union {
 788                                         __le16 mirroring_status;
 789                                         __le16 fcoe_ctx_id;
 790                                 } mirr_fcoe;
 791                                 __le16 l2tag1;
 792                         } lo_dword;
 793                         union {
 794                                 __le32 rss; /* RSS Hash */
 795                                 __le32 fcoe_param; /* FCoE DDP Context id */
 796                                 /* Flow director filter id in case of
 797                                  * Programming status desc WB
 798                                  */
 799                                 __le32 fd_id;
 800                         } hi_dword;
 801                 } qword0;
 802                 struct {
 803                         /* status/error/pktype/length */
 804                         __le64 status_error_len;
 805                 } qword1;
 806                 struct {
 807                         __le16 ext_status; /* extended status */
 808                         __le16 rsvd;
 809                         __le16 l2tag2_1;
 810                         __le16 l2tag2_2;
 811                 } qword2;
 812                 struct {
 813                         union {
 814                                 __le32 flex_bytes_lo;
 815                                 __le32 pe_status;
 816                         } lo_dword;
 817                         union {
 818                                 __le32 flex_bytes_hi;
 819                                 __le32 fd_id;
 820                         } hi_dword;
 821                 } qword3;
 822         } wb;  /* writeback */
 823 };
 824
 825 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 826 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 827                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 828 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 829 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 830                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 831
 832 enum i40e_rx_desc_status_bits {
 833         /* Note: These are predefined bit offsets */
 834         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 835         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 836         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 837         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 838         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 839         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 840         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 841         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 842
 843         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 844         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 845         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 846         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 847         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 848         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 849         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 850         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 851 };
 852
 853 #define I40E_RXD_QW1_STATUS_SHIFT       0
 854 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 855                                          I40E_RXD_QW1_STATUS_SHIFT)
 856
 857 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 858 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 859                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 860
 861 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 862 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 863
 864 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 865 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 866                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 867
 868 enum i40e_rx_desc_fltstat_values {
 869         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 870         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 871         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 872         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 873 };
 874
 875 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 876 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 877 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 878 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 879
 880 #define I40E_RXD_QW1_ERROR_SHIFT        19
 881 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 882
 883 enum i40e_rx_desc_error_bits {
 884         /* Note: These are predefined bit offsets */
 885         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 886         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 887         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 888         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 889         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 890         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 891         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 892         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 893         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 894 };
 895
 896 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 897         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 898         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 899         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 900         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 901         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 902 };
 903
 904 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 905 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 906
 907 /* Packet type non-ip values */
 908 enum i40e_rx_l2_ptype {
 909         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 910         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 911         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 912         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 913         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 914         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 915         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 916         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 917         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 918         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 919         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 920         I40E_RX_PTYPE_L2_ARP                            = 11,
 921         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 922         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 923         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 924         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 925         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 926         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 927         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 928         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 929         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 930         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 931         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 932         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 933         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 934         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 935 };
 936
 937 struct i40e_rx_ptype_decoded {
 938         u32 ptype:8;
 939         u32 known:1;
 940         u32 outer_ip:1;
 941         u32 outer_ip_ver:1;
 942         u32 outer_frag:1;
 943         u32 tunnel_type:3;
 944         u32 tunnel_end_prot:2;
 945         u32 tunnel_end_frag:1;
 946         u32 inner_prot:4;
 947         u32 payload_layer:3;
 948 };
 949
 950 enum i40e_rx_ptype_outer_ip {
 951         I40E_RX_PTYPE_OUTER_L2  = 0,
 952         I40E_RX_PTYPE_OUTER_IP  = 1
 953 };
 954
 955 enum i40e_rx_ptype_outer_ip_ver {
 956         I40E_RX_PTYPE_OUTER_NONE        = 0,
 957         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 958         I40E_RX_PTYPE_OUTER_IPV6        = 1
 959 };
 960
 961 enum i40e_rx_ptype_outer_fragmented {
 962         I40E_RX_PTYPE_NOT_FRAG  = 0,
 963         I40E_RX_PTYPE_FRAG      = 1
 964 };
 965
 966 enum i40e_rx_ptype_tunnel_type {
 967         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 968         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 969         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 970         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 971         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 972 };
 973
 974 enum i40e_rx_ptype_tunnel_end_prot {
 975         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 976         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 977         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 978 };
 979
 980 enum i40e_rx_ptype_inner_prot {
 981         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 982         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 983         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 984         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 985         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 986         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 987 };
 988
 989 enum i40e_rx_ptype_payload_layer {
 990         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 991         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 992         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 993         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 994 };
 995
 996 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 997 #define I40E_RX_PTYPE_SHIFT             56
 998
 999 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
1000 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1001                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1002
1003 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
1004 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1005                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1006
1007 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1008 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1009
1010 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1011 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1012
1013 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1014 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1015                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1016
1017 enum i40e_rx_desc_ext_status_bits {
1018         /* Note: These are predefined bit offsets */
1019         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1020         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1021         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1022         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1023         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1024         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1025         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1026 };
1027
1028 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1029 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1030
1031 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1032 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1033
1034 enum i40e_rx_desc_pe_status_bits {
1035         /* Note: These are predefined bit offsets */
1036         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1037         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1038         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1039         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1040         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1041         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1042         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1043         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1044         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1045 };
1046
1047 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1048 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1049
1050 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1051 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1052                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1053
1054 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1055 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1056                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1057
1058 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1059 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1060                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1061
1062 enum i40e_rx_prog_status_desc_status_bits {
1063         /* Note: These are predefined bit offsets */
1064         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1065         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1066 };
1067
1068 enum i40e_rx_prog_status_desc_prog_id_masks {
1069         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1070         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1071         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1072 };
1073
1074 enum i40e_rx_prog_status_desc_error_bits {
1075         /* Note: These are predefined bit offsets */
1076         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1077         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1078         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1079         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1080 };
1081
1082 #define I40E_TWO_BIT_MASK       0x3
1083 #define I40E_THREE_BIT_MASK     0x7
1084 #define I40E_FOUR_BIT_MASK      0xF
1085 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1086
1087 /* TX Descriptor */
1088 struct i40e_tx_desc {
1089         __le64 buffer_addr; /* Address of descriptor's data buf */
1090         __le64 cmd_type_offset_bsz;
1091 };
1092
1093 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1094 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1095
1096 enum i40e_tx_desc_dtype_value {
1097         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1098         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1099         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1100         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1101         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1102         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1103         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1104         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1105         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1106         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1107 };
1108
1109 #define I40E_TXD_QW1_CMD_SHIFT  4
1110 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1111
1112 enum i40e_tx_desc_cmd_bits {
1113         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1114         I40E_TX_DESC_CMD_RS                     = 0x0002,
1115         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1116         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1117         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1118         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1119         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1120         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1121         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1122         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1123         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1124         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1125         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1126         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1127         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1128         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1129         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1130         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1131 };
1132
1133 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1134 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1135                                          I40E_TXD_QW1_OFFSET_SHIFT)
1136
1137 enum i40e_tx_desc_length_fields {
1138         /* Note: These are predefined bit offsets */
1139         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1140         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1141         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1142 };
1143
1144 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1145 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1146 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1147 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1148
1149 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1150 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1151                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1152
1153 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1154 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1155
1156 /* Context descriptors */
1157 struct i40e_tx_context_desc {
1158         __le32 tunneling_params;
1159         __le16 l2tag2;
1160         __le16 rsvd;
1161         __le64 type_cmd_tso_mss;
1162 };
1163
1164 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1165 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1166
1167 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1168 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1169
1170 enum i40e_tx_ctx_desc_cmd_bits {
1171         I40E_TX_CTX_DESC_TSO            = 0x01,
1172         I40E_TX_CTX_DESC_TSYN           = 0x02,
1173         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1174         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1175         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1176         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1177         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1178         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1179         I40E_TX_CTX_DESC_SWPE           = 0x40
1180 };
1181
1182 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1183 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1184                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1185
1186 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1187 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1188                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1189
1190 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1191 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1192
1193 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1194 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1195                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1196
1197 enum i40e_tx_ctx_desc_eipt_offload {
1198         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1199         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1200         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1201         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1202 };
1203
1204 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1205 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1206                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1207
1208 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1209 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1210
1211 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1212 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1213
1214 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1215 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1216
1217 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1218
1219 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1220 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1221                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1222
1223 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1224 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1225                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1226
1227 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1228 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1229 struct i40e_nop_desc {
1230         __le64 rsvd;
1231         __le64 dtype_cmd;
1232 };
1233
1234 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1235 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1236
1237 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1238 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1239
1240 enum i40e_tx_nop_desc_cmd_bits {
1241         /* Note: These are predefined bit offsets */
1242         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1243         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1244         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1245 };
1246
1247 struct i40e_filter_program_desc {
1248         __le32 qindex_flex_ptype_vsi;
1249         __le32 rsvd;
1250         __le32 dtype_cmd_cntindex;
1251         __le32 fd_id;
1252 };
1253 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1254 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1255                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1256 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1257 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1258                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1259 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1260 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1261                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1262
1263 /* Packet Classifier Types for filters */
1264 enum i40e_filter_pctype {
1265         /* Note: Values 0-28 are reserved for future use.
1266          * Value 29, 30, 32 are not supported on XL710 and X710.
1267          */
1268         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1269         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1270         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1271         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1272         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1273         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1274         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1275         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1276         /* Note: Values 37-38 are reserved for future use.
1277          * Value 39, 40, 42 are not supported on XL710 and X710.
1278          */
1279         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1280         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1281         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1282         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1283         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1284         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1285         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1286         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1287         /* Note: Value 47 is reserved for future use */
1288         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1289         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1290         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1291         /* Note: Values 51-62 are reserved for future use */
1292         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1293 };
1294
1295 enum i40e_filter_program_desc_dest {
1296         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1297         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1298         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1299 };
1300
1301 enum i40e_filter_program_desc_fd_status {
1302         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1303         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1304         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1305         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1306 };
1307
1308 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1309 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1310                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1311
1312 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1313 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1314
1315 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1316 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1317                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1318
1319 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1320 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1321
1322 enum i40e_filter_program_desc_pcmd {
1323         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1324         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1325 };
1326
1327 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1328 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1329
1330 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1331 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1332
1333 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1334                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1335 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1336                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1337
1338 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1339                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1340 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1341
1342 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1343 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1344                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1345
1346 enum i40e_filter_type {
1347         I40E_FLOW_DIRECTOR_FLTR = 0,
1348         I40E_PE_QUAD_HASH_FLTR = 1,
1349         I40E_ETHERTYPE_FLTR,
1350         I40E_FCOE_CTX_FLTR,
1351         I40E_MAC_VLAN_FLTR,
1352         I40E_HASH_FLTR
1353 };
1354
1355 struct i40e_vsi_context {
1356         u16 seid;
1357         u16 uplink_seid;
1358         u16 vsi_number;
1359         u16 vsis_allocated;
1360         u16 vsis_unallocated;
1361         u16 flags;
1362         u8 pf_num;
1363         u8 vf_num;
1364         u8 connection_type;
1365         struct i40e_aqc_vsi_properties_data info;
1366 };
1367
1368 struct i40e_veb_context {
1369         u16 seid;
1370         u16 uplink_seid;
1371         u16 veb_number;
1372         u16 vebs_allocated;
1373         u16 vebs_unallocated;
1374         u16 flags;
1375         struct i40e_aqc_get_veb_parameters_completion info;
1376 };
1377
1378 /* Statistics collected by each port, VSI, VEB, and S-channel */
1379 struct i40e_eth_stats {
1380         u64 rx_bytes;                   /* gorc */
1381         u64 rx_unicast;                 /* uprc */
1382         u64 rx_multicast;               /* mprc */
1383         u64 rx_broadcast;               /* bprc */
1384         u64 rx_discards;                /* rdpc */
1385         u64 rx_unknown_protocol;        /* rupp */
1386         u64 tx_bytes;                   /* gotc */
1387         u64 tx_unicast;                 /* uptc */
1388         u64 tx_multicast;               /* mptc */
1389         u64 tx_broadcast;               /* bptc */
1390         u64 tx_discards;                /* tdpc */
1391         u64 tx_errors;                  /* tepc */
1392 };
1393
1394 /* Statistics collected per VEB per TC */
1395 struct i40e_veb_tc_stats {
1396         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1397         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1398         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1399         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1400 };
1401
1402 /* Statistics collected per function for FCoE */
1403 struct i40e_fcoe_stats {
1404         u64 rx_fcoe_packets;            /* fcoeprc */
1405         u64 rx_fcoe_dwords;             /* focedwrc */
1406         u64 rx_fcoe_dropped;            /* fcoerpdc */
1407         u64 tx_fcoe_packets;            /* fcoeptc */
1408         u64 tx_fcoe_dwords;             /* focedwtc */
1409         u64 fcoe_bad_fccrc;             /* fcoecrc */
1410         u64 fcoe_last_error;            /* fcoelast */
1411         u64 fcoe_ddp_count;             /* fcoeddpc */
1412 };
1413
1414 /* offset to per function FCoE statistics block */
1415 #define I40E_FCOE_VF_STAT_OFFSET        0
1416 #define I40E_FCOE_PF_STAT_OFFSET        128
1417 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1418
1419 /* Statistics collected by the MAC */
1420 struct i40e_hw_port_stats {
1421         /* eth stats collected by the port */
1422         struct i40e_eth_stats eth;
1423
1424         /* additional port specific stats */
1425         u64 tx_dropped_link_down;       /* tdold */
1426         u64 crc_errors;                 /* crcerrs */
1427         u64 illegal_bytes;              /* illerrc */
1428         u64 error_bytes;                /* errbc */
1429         u64 mac_local_faults;           /* mlfc */
1430         u64 mac_remote_faults;          /* mrfc */
1431         u64 rx_length_errors;           /* rlec */
1432         u64 link_xon_rx;                /* lxonrxc */
1433         u64 link_xoff_rx;               /* lxoffrxc */
1434         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1435         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1436         u64 link_xon_tx;                /* lxontxc */
1437         u64 link_xoff_tx;               /* lxofftxc */
1438         u64 priority_xon_tx[8];         /* pxontxc[8] */
1439         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1440         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1441         u64 rx_size_64;                 /* prc64 */
1442         u64 rx_size_127;                /* prc127 */
1443         u64 rx_size_255;                /* prc255 */
1444         u64 rx_size_511;                /* prc511 */
1445         u64 rx_size_1023;               /* prc1023 */
1446         u64 rx_size_1522;               /* prc1522 */
1447         u64 rx_size_big;                /* prc9522 */
1448         u64 rx_undersize;               /* ruc */
1449         u64 rx_fragments;               /* rfc */
1450         u64 rx_oversize;                /* roc */
1451         u64 rx_jabber;                  /* rjc */
1452         u64 tx_size_64;                 /* ptc64 */
1453         u64 tx_size_127;                /* ptc127 */
1454         u64 tx_size_255;                /* ptc255 */
1455         u64 tx_size_511;                /* ptc511 */
1456         u64 tx_size_1023;               /* ptc1023 */
1457         u64 tx_size_1522;               /* ptc1522 */
1458         u64 tx_size_big;                /* ptc9522 */
1459         u64 mac_short_packet_dropped;   /* mspdc */
1460         u64 checksum_error;             /* xec */
1461         /* flow director stats */
1462         u64 fd_atr_match;
1463         u64 fd_sb_match;
1464         u64 fd_atr_tunnel_match;
1465         u32 fd_atr_status;
1466         u32 fd_sb_status;
1467         /* EEE LPI */
1468         u32 tx_lpi_status;
1469         u32 rx_lpi_status;
1470         u64 tx_lpi_count;               /* etlpic */
1471         u64 rx_lpi_count;               /* erlpic */
1472 };
1473
1474 /* Checksum and Shadow RAM pointers */
1475 #define I40E_SR_NVM_CONTROL_WORD                0x00
1476 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1477 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1478 #define I40E_SR_OPTION_ROM_PTR                  0x05
1479 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1480 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1481 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1482 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1483 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1484 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1485 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1486 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1487 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1488 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1489 #define I40E_SR_PBA_FLAGS                       0x15
1490 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1491 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1492 #define I40E_NVM_OEM_VER_OFF                    0x83
1493 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1494 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1495 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1496 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1497 #define I40E_SR_NVM_MAP_VERSION                 0x29
1498 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1499 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1500 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1501 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1502 #define I40E_SR_VPD_PTR                         0x2F
1503 #define I40E_SR_PXE_SETUP_PTR                   0x30
1504 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1505 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1506 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1507 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1508 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1509 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1510 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1511 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1512 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1513 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1514 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1515 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1516 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1517 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1518 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1519 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1520 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1521 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1522 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1523
1524 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1525 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1526 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1527 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1528 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1529
1530 /* Shadow RAM related */
1531 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1532 #define I40E_SR_BUF_ALIGNMENT           4096
1533 #define I40E_SR_WORDS_IN_1KB            512
1534 /* Checksum should be calculated such that after adding all the words,
1535  * including the checksum word itself, the sum should be 0xBABA.
1536  */
1537 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1538
1539 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1540
1541 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1542
1543 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1544         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1545         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1546         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1547         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1548         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1549         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1550         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1551         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1552         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1553         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1554         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1555         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1556         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1557 };
1558
1559 /* FCoE DIF/DIX Context descriptor */
1560 struct i40e_fcoe_difdix_context_desc {
1561         __le64 flags_buff0_buff1_ref;
1562         __le64 difapp_msk_bias;
1563 };
1564
1565 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1566 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1567                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1568
1569 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1570         /* 2 BITS */
1571         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1572         /* 1 BIT  */
1573         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1574         /* 1 BIT  */
1575         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1576         /* 2 BITS */
1577         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1578         /* 2 BITS */
1579         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1580         /* 2 BITS */
1581         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1582         /* 2 BITS */
1583         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1584         /* 2 BITS */
1585         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1586         /* 2 BITS */
1587         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1588         /* 2 BITS */
1589         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1590         /* 2 BITS */
1591         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1592         /* 1 BIT  */
1593         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1594         /* 1 BIT  */
1595         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1596         /* 2 BITS */
1597         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1598         /* 2 BITS */
1599         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1600         /* 2 BITS */
1601         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1602         /* 2 BITS */
1603         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1604         /* 1 BIT  */
1605         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1606         /* 1 BIT  */
1607         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1608         /* 1 BIT */
1609         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1610         /* 1 BIT */
1611         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1612 };
1613
1614 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1615 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1616                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1617
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1619 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1620                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1621
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1623 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1624                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1625
1626 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1627 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1628                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1629
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1631 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1632                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1633
1634 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1635 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1636                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1637
1638 /* FCoE DIF/DIX Buffers descriptor */
1639 struct i40e_fcoe_difdix_buffers_desc {
1640         __le64 buff_addr0;
1641         __le64 buff_addr1;
1642 };
1643
1644 /* FCoE DDP Context descriptor */
1645 struct i40e_fcoe_ddp_context_desc {
1646         __le64 rsvd;
1647         __le64 type_cmd_foff_lsize;
1648 };
1649
1650 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1651 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1652                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1653
1654 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1655 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1656                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1657
1658 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1659         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1660         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1661         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1662         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1663         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1664         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1665 };
1666
1667 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1668 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1669                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1670
1671 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1672 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1673                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1674
1675 /* FCoE DDP/DWO Queue Context descriptor */
1676 struct i40e_fcoe_queue_context_desc {
1677         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1678         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1679 };
1680
1681 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1682 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1683                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1684
1685 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1686 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1687                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1688
1689 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1690 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1691                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1692
1693 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1694 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1695                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1696
1697 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1698         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1699         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1700 };
1701
1702 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1703 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1704                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1705
1706 /* FCoE DDP/DWO Filter Context descriptor */
1707 struct i40e_fcoe_filter_context_desc {
1708         __le32 param;
1709         __le16 seqn;
1710
1711         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1712         __le16 rsvd_dmaindx;
1713
1714         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1715         __le64 flags_rsvd_lanq;
1716 };
1717
1718 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1719 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1720                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1721
1722 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1723         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1724         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1725         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1726         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1727         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1728         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1729 };
1730
1731 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1732 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1733                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1734
1735 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1736 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1737                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1738
1739 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1740 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1741                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1742
1743 enum i40e_switch_element_types {
1744         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1745         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1746         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1747         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1748         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1749         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1750         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1751         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1752         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1753 };
1754
1755 /* Supported EtherType filters */
1756 enum i40e_ether_type_index {
1757         I40E_ETHER_TYPE_1588            = 0,
1758         I40E_ETHER_TYPE_FIP             = 1,
1759         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1760         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1761         I40E_ETHER_TYPE_LLDP            = 4,
1762         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1763         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1764         I40E_ETHER_TYPE_QCN_CNM         = 7,
1765         I40E_ETHER_TYPE_8021X           = 8,
1766         I40E_ETHER_TYPE_ARP             = 9,
1767         I40E_ETHER_TYPE_RSV1            = 10,
1768         I40E_ETHER_TYPE_RSV2            = 11,
1769 };
1770
1771 /* Filter context base size is 1K */
1772 #define I40E_HASH_FILTER_BASE_SIZE      1024
1773 /* Supported Hash filter values */
1774 enum i40e_hash_filter_size {
1775         I40E_HASH_FILTER_SIZE_1K        = 0,
1776         I40E_HASH_FILTER_SIZE_2K        = 1,
1777         I40E_HASH_FILTER_SIZE_4K        = 2,
1778         I40E_HASH_FILTER_SIZE_8K        = 3,
1779         I40E_HASH_FILTER_SIZE_16K       = 4,
1780         I40E_HASH_FILTER_SIZE_32K       = 5,
1781         I40E_HASH_FILTER_SIZE_64K       = 6,
1782         I40E_HASH_FILTER_SIZE_128K      = 7,
1783         I40E_HASH_FILTER_SIZE_256K      = 8,
1784         I40E_HASH_FILTER_SIZE_512K      = 9,
1785         I40E_HASH_FILTER_SIZE_1M        = 10,
1786 };
1787
1788 /* DMA context base size is 0.5K */
1789 #define I40E_DMA_CNTX_BASE_SIZE         512
1790 /* Supported DMA context values */
1791 enum i40e_dma_cntx_size {
1792         I40E_DMA_CNTX_SIZE_512          = 0,
1793         I40E_DMA_CNTX_SIZE_1K           = 1,
1794         I40E_DMA_CNTX_SIZE_2K           = 2,
1795         I40E_DMA_CNTX_SIZE_4K           = 3,
1796         I40E_DMA_CNTX_SIZE_8K           = 4,
1797         I40E_DMA_CNTX_SIZE_16K          = 5,
1798         I40E_DMA_CNTX_SIZE_32K          = 6,
1799         I40E_DMA_CNTX_SIZE_64K          = 7,
1800         I40E_DMA_CNTX_SIZE_128K         = 8,
1801         I40E_DMA_CNTX_SIZE_256K         = 9,
1802 };
1803
1804 /* Supported Hash look up table (LUT) sizes */
1805 enum i40e_hash_lut_size {
1806         I40E_HASH_LUT_SIZE_128          = 0,
1807         I40E_HASH_LUT_SIZE_512          = 1,
1808 };
1809
1810 /* Structure to hold a per PF filter control settings */
1811 struct i40e_filter_control_settings {
1812         /* number of PE Quad Hash filter buckets */
1813         enum i40e_hash_filter_size pe_filt_num;
1814         /* number of PE Quad Hash contexts */
1815         enum i40e_dma_cntx_size pe_cntx_num;
1816         /* number of FCoE filter buckets */
1817         enum i40e_hash_filter_size fcoe_filt_num;
1818         /* number of FCoE DDP contexts */
1819         enum i40e_dma_cntx_size fcoe_cntx_num;
1820         /* size of the Hash LUT */
1821         enum i40e_hash_lut_size hash_lut_size;
1822         /* enable FDIR filters for PF and its VFs */
1823         bool enable_fdir;
1824         /* enable Ethertype filters for PF and its VFs */
1825         bool enable_ethtype;
1826         /* enable MAC/VLAN filters for PF and its VFs */
1827         bool enable_macvlan;
1828 };
1829
1830 /* Structure to hold device level control filter counts */
1831 struct i40e_control_filter_stats {
1832         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1833         u16 etype_used;       /* Used perfect EtherType filters */
1834         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1835         u16 etype_free;       /* Un-used perfect EtherType filters */
1836 };
1837
1838 enum i40e_reset_type {
1839         I40E_RESET_POR          = 0,
1840         I40E_RESET_CORER        = 1,
1841         I40E_RESET_GLOBR        = 2,
1842         I40E_RESET_EMPR         = 3,
1843 };
1844
1845 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1846 #define I40E_NVM_LLDP_CFG_PTR           0xD
1847 struct i40e_lldp_variables {
1848         u16 length;
1849         u16 adminstatus;
1850         u16 msgfasttx;
1851         u16 msgtxinterval;
1852         u16 txparams;
1853         u16 timers;
1854         u16 crc8;
1855 };
1856
1857 /* Offsets into Alternate Ram */
1858 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1859 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1860 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1861 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1862 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1863 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1864
1865 /* Alternate Ram Bandwidth Masks */
1866 #define I40E_ALT_BW_VALUE_MASK          0xFF
1867 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1868 #define I40E_ALT_BW_VALID_MASK          0x80000000
1869
1870 /* RSS Hash Table Size */
1871 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1872
1873 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1874 #define I40E_L3_SRC_SHIFT               47
1875 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1876 #define I40E_L3_V6_SRC_SHIFT            43
1877 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1878 #define I40E_L3_DST_SHIFT               35
1879 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1880 #define I40E_L3_V6_DST_SHIFT            35
1881 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1882 #define I40E_L4_SRC_SHIFT               34
1883 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1884 #define I40E_L4_DST_SHIFT               33
1885 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1886 #define I40E_VERIFY_TAG_SHIFT           31
1887 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1888
1889 #define I40E_FLEX_50_SHIFT              13
1890 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1891 #define I40E_FLEX_51_SHIFT              12
1892 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1893 #define I40E_FLEX_52_SHIFT              11
1894 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1895 #define I40E_FLEX_53_SHIFT              10
1896 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1897 #define I40E_FLEX_54_SHIFT              9
1898 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1899 #define I40E_FLEX_55_SHIFT              8
1900 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1901 #define I40E_FLEX_56_SHIFT              7
1902 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1903 #define I40E_FLEX_57_SHIFT              6
1904 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1905
1906 /* Version format for Dynamic Device Personalization(DDP) */
1907 struct i40e_ddp_version {
1908         u8 major;
1909         u8 minor;
1910         u8 update;
1911         u8 draft;
1912 };
1913
1914 #define I40E_DDP_NAME_SIZE      32
1915
1916 /* Package header */
1917 struct i40e_package_header {
1918         struct i40e_ddp_version version;
1919         u32 segment_count;
1920         u32 segment_offset[1];
1921 };
1922
1923 /* Generic segment header */
1924 struct i40e_generic_seg_header {
1925 #define SEGMENT_TYPE_METADATA   0x00000001
1926 #define SEGMENT_TYPE_NOTES      0x00000002
1927 #define SEGMENT_TYPE_I40E       0x00000011
1928 #define SEGMENT_TYPE_X722       0x00000012
1929         u32 type;
1930         struct i40e_ddp_version version;
1931         u32 size;
1932         char name[I40E_DDP_NAME_SIZE];
1933 };
1934
1935 struct i40e_metadata_segment {
1936         struct i40e_generic_seg_header header;
1937         struct i40e_ddp_version version;
1938 #define I40E_DDP_TRACKID_RDONLY         0
1939 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1940         u32 track_id;
1941         char name[I40E_DDP_NAME_SIZE];
1942 };
1943
1944 struct i40e_device_id_entry {
1945         u32 vendor_dev_id;
1946         u32 sub_vendor_dev_id;
1947 };
1948
1949 struct i40e_profile_segment {
1950         struct i40e_generic_seg_header header;
1951         struct i40e_ddp_version version;
1952         char name[I40E_DDP_NAME_SIZE];
1953         u32 device_table_count;
1954         struct i40e_device_id_entry device_table[1];
1955 };
1956
1957 struct i40e_section_table {
1958         u32 section_count;
1959         u32 section_offset[1];
1960 };
1961
1962 struct i40e_profile_section_header {
1963         u16 tbl_size;
1964         u16 data_end;
1965         struct {
1966 #define SECTION_TYPE_INFO       0x00000010
1967 #define SECTION_TYPE_MMIO       0x00000800
1968 #define SECTION_TYPE_RB_MMIO    0x00001800
1969 #define SECTION_TYPE_AQ         0x00000801
1970 #define SECTION_TYPE_RB_AQ      0x00001801
1971 #define SECTION_TYPE_NOTE       0x80000000
1972 #define SECTION_TYPE_NAME       0x80000001
1973 #define SECTION_TYPE_PROTO      0x80000002
1974 #define SECTION_TYPE_PCTYPE     0x80000003
1975 #define SECTION_TYPE_PTYPE      0x80000004
1976                 u32 type;
1977                 u32 offset;
1978                 u32 size;
1979         } section;
1980 };
1981
1982 struct i40e_profile_tlv_section_record {
1983         u8 rtype;
1984         u8 type;
1985         u16 len;
1986         u8 data[12];
1987 };
1988
1989 /* Generic AQ section in proflie */
1990 struct i40e_profile_aq_section {
1991         u16 opcode;
1992         u16 flags;
1993         u8  param[16];
1994         u16 datalen;
1995         u8  data[1];
1996 };
1997
1998 struct i40e_profile_info {
1999         u32 track_id;
2000         struct i40e_ddp_version version;
2001         u8 op;
2002 #define I40E_DDP_ADD_TRACKID            0x01
2003 #define I40E_DDP_REMOVE_TRACKID 0x02
2004         u8 reserved[7];
2005         u8 name[I40E_DDP_NAME_SIZE];
2006 };
2007 #endif /* _I40E_TYPE_H_ */