drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 /* Memory types */
 161 enum i40e_memset_type {
 162         I40E_NONDMA_MEM = 0,
 163         I40E_DMA_MEM
 164 };
 165
 166 /* Memcpy types */
 167 enum i40e_memcpy_type {
 168         I40E_NONDMA_TO_NONDMA = 0,
 169         I40E_NONDMA_TO_DMA,
 170         I40E_DMA_TO_DMA,
 171         I40E_DMA_TO_NONDMA
 172 };
 173
 174
 175 #ifdef X722_SUPPORT
 176 #define I40E_FW_API_VERSION_MINOR_X722  0x0003
 177 #endif
 178 #define I40E_FW_API_VERSION_MINOR_X710  0x0004
 179
 180
 181 /* These are structs for managing the hardware information and the operations.
 182  * The structures of function pointers are filled out at init time when we
 183  * know for sure exactly which hardware we're working with.  This gives us the
 184  * flexibility of using the same main driver code but adapting to slightly
 185  * different hardware needs as new parts are developed.  For this architecture,
 186  * the Firmware and AdminQ are intended to insulate the driver from most of the
 187  * future changes, but these structures will also do part of the job.
 188  */
 189 enum i40e_mac_type {
 190         I40E_MAC_UNKNOWN = 0,
 191         I40E_MAC_X710,
 192         I40E_MAC_XL710,
 193         I40E_MAC_VF,
 194         I40E_MAC_GENERIC,
 195 };
 196
 197 enum i40e_media_type {
 198         I40E_MEDIA_TYPE_UNKNOWN = 0,
 199         I40E_MEDIA_TYPE_FIBER,
 200         I40E_MEDIA_TYPE_BASET,
 201         I40E_MEDIA_TYPE_BACKPLANE,
 202         I40E_MEDIA_TYPE_CX4,
 203         I40E_MEDIA_TYPE_DA,
 204         I40E_MEDIA_TYPE_VIRTUAL
 205 };
 206
 207 enum i40e_fc_mode {
 208         I40E_FC_NONE = 0,
 209         I40E_FC_RX_PAUSE,
 210         I40E_FC_TX_PAUSE,
 211         I40E_FC_FULL,
 212         I40E_FC_PFC,
 213         I40E_FC_DEFAULT
 214 };
 215
 216 enum i40e_set_fc_aq_failures {
 217         I40E_SET_FC_AQ_FAIL_NONE = 0,
 218         I40E_SET_FC_AQ_FAIL_GET = 1,
 219         I40E_SET_FC_AQ_FAIL_SET = 2,
 220         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 221         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 222 };
 223
 224 enum i40e_vsi_type {
 225         I40E_VSI_MAIN = 0,
 226         I40E_VSI_VMDQ1,
 227         I40E_VSI_VMDQ2,
 228         I40E_VSI_CTRL,
 229         I40E_VSI_FCOE,
 230         I40E_VSI_MIRROR,
 231         I40E_VSI_SRIOV,
 232         I40E_VSI_FDIR,
 233         I40E_VSI_TYPE_UNKNOWN
 234 };
 235
 236 enum i40e_queue_type {
 237         I40E_QUEUE_TYPE_RX = 0,
 238         I40E_QUEUE_TYPE_TX,
 239         I40E_QUEUE_TYPE_PE_CEQ,
 240         I40E_QUEUE_TYPE_UNKNOWN
 241 };
 242
 243 struct i40e_link_status {
 244         enum i40e_aq_phy_type phy_type;
 245         enum i40e_aq_link_speed link_speed;
 246         u8 link_info;
 247         u8 an_info;
 248         u8 ext_info;
 249         u8 loopback;
 250         /* is Link Status Event notification to SW enabled */
 251         bool lse_enable;
 252         u16 max_frame_size;
 253         bool crc_enable;
 254         u8 pacing;
 255         u8 requested_speeds;
 256         u8 module_type[3];
 257         /* 1st byte: module identifier */
 258 #define I40E_MODULE_TYPE_SFP            0x03
 259 #define I40E_MODULE_TYPE_QSFP           0x0D
 260         /* 2nd byte: ethernet compliance codes for 10/40G */
 261 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 262 #define I40E_MODULE_TYPE_40G_LR4        0x02
 263 #define I40E_MODULE_TYPE_40G_SR4        0x04
 264 #define I40E_MODULE_TYPE_40G_CR4        0x08
 265 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 266 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 267 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 268 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 269         /* 3rd byte: ethernet compliance codes for 1G */
 270 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 271 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 272 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 273 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 274 };
 275
 276 struct i40e_phy_info {
 277         struct i40e_link_status link_info;
 278         struct i40e_link_status link_info_old;
 279         u32 autoneg_advertised;
 280         u32 phy_id;
 281         u32 module_type;
 282         bool get_link_info;
 283         enum i40e_media_type media_type;
 284 };
 285
 286 #define I40E_HW_CAP_MAX_GPIO                    30
 287 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 288 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 289
 290 /* Capabilities of a PF or a VF or the whole device */
 291 struct i40e_hw_capabilities {
 292         u32  switch_mode;
 293 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 294 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 295 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 296
 297         u32  management_mode;
 298         u32  npar_enable;
 299         u32  os2bmc;
 300         u32  valid_functions;
 301         bool sr_iov_1_1;
 302         bool vmdq;
 303         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 304         bool evb_802_1_qbh; /* Bridge Port Extension */
 305         bool dcb;
 306         bool fcoe;
 307         bool iscsi; /* Indicates iSCSI enabled */
 308         bool mfp_mode_1;
 309         bool mgmt_cem;
 310         bool ieee_1588;
 311         bool iwarp;
 312         bool fd;
 313         u32 fd_filters_guaranteed;
 314         u32 fd_filters_best_effort;
 315         bool rss;
 316         u32 rss_table_size;
 317         u32 rss_table_entry_width;
 318         bool led[I40E_HW_CAP_MAX_GPIO];
 319         bool sdp[I40E_HW_CAP_MAX_GPIO];
 320         u32 nvm_image_type;
 321         u32 num_flow_director_filters;
 322         u32 num_vfs;
 323         u32 vf_base_id;
 324         u32 num_vsis;
 325         u32 num_rx_qp;
 326         u32 num_tx_qp;
 327         u32 base_queue;
 328         u32 num_msix_vectors;
 329         u32 num_msix_vectors_vf;
 330         u32 led_pin_num;
 331         u32 sdp_pin_num;
 332         u32 mdio_port_num;
 333         u32 mdio_port_mode;
 334         u8 rx_buf_chain_len;
 335         u32 enabled_tcmap;
 336         u32 maxtc;
 337 };
 338
 339 struct i40e_mac_info {
 340         enum i40e_mac_type type;
 341         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 342         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 343         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 344         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 345         u16 max_fcoeq;
 346 };
 347
 348 enum i40e_aq_resources_ids {
 349         I40E_NVM_RESOURCE_ID = 1
 350 };
 351
 352 enum i40e_aq_resource_access_type {
 353         I40E_RESOURCE_READ = 1,
 354         I40E_RESOURCE_WRITE
 355 };
 356
 357 struct i40e_nvm_info {
 358         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 359         u32 timeout;              /* [ms] */
 360         u16 sr_size;              /* Shadow RAM size in words */
 361         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 362         u16 version;              /* NVM package version */
 363         u32 eetrack;              /* NVM data version */
 364         u32 oem_ver;              /* OEM version info */
 365 };
 366
 367 /* definitions used in NVM update support */
 368
 369 enum i40e_nvmupd_cmd {
 370         I40E_NVMUPD_INVALID,
 371         I40E_NVMUPD_READ_CON,
 372         I40E_NVMUPD_READ_SNT,
 373         I40E_NVMUPD_READ_LCB,
 374         I40E_NVMUPD_READ_SA,
 375         I40E_NVMUPD_WRITE_ERA,
 376         I40E_NVMUPD_WRITE_CON,
 377         I40E_NVMUPD_WRITE_SNT,
 378         I40E_NVMUPD_WRITE_LCB,
 379         I40E_NVMUPD_WRITE_SA,
 380         I40E_NVMUPD_CSUM_CON,
 381         I40E_NVMUPD_CSUM_SA,
 382         I40E_NVMUPD_CSUM_LCB,
 383         I40E_NVMUPD_STATUS,
 384         I40E_NVMUPD_EXEC_AQ,
 385         I40E_NVMUPD_GET_AQ_RESULT,
 386 };
 387
 388 enum i40e_nvmupd_state {
 389         I40E_NVMUPD_STATE_INIT,
 390         I40E_NVMUPD_STATE_READING,
 391         I40E_NVMUPD_STATE_WRITING,
 392         I40E_NVMUPD_STATE_INIT_WAIT,
 393         I40E_NVMUPD_STATE_WRITE_WAIT,
 394 };
 395
 396 /* nvm_access definition and its masks/shifts need to be accessible to
 397  * application, core driver, and shared code.  Where is the right file?
 398  */
 399 #define I40E_NVM_READ   0xB
 400 #define I40E_NVM_WRITE  0xC
 401
 402 #define I40E_NVM_MOD_PNT_MASK 0xFF
 403
 404 #define I40E_NVM_TRANS_SHIFT    8
 405 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 406 #define I40E_NVM_CON            0x0
 407 #define I40E_NVM_SNT            0x1
 408 #define I40E_NVM_LCB            0x2
 409 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 410 #define I40E_NVM_ERA            0x4
 411 #define I40E_NVM_CSUM           0x8
 412 #define I40E_NVM_EXEC           0xf
 413
 414 #define I40E_NVM_ADAPT_SHIFT    16
 415 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 416
 417 #define I40E_NVMUPD_MAX_DATA    4096
 418 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 419
 420 struct i40e_nvm_access {
 421         u32 command;
 422         u32 config;
 423         u32 offset;     /* in bytes */
 424         u32 data_size;  /* in bytes */
 425         u8 data[1];
 426 };
 427
 428 /* PCI bus types */
 429 enum i40e_bus_type {
 430         i40e_bus_type_unknown = 0,
 431         i40e_bus_type_pci,
 432         i40e_bus_type_pcix,
 433         i40e_bus_type_pci_express,
 434         i40e_bus_type_reserved
 435 };
 436
 437 /* PCI bus speeds */
 438 enum i40e_bus_speed {
 439         i40e_bus_speed_unknown  = 0,
 440         i40e_bus_speed_33       = 33,
 441         i40e_bus_speed_66       = 66,
 442         i40e_bus_speed_100      = 100,
 443         i40e_bus_speed_120      = 120,
 444         i40e_bus_speed_133      = 133,
 445         i40e_bus_speed_2500     = 2500,
 446         i40e_bus_speed_5000     = 5000,
 447         i40e_bus_speed_8000     = 8000,
 448         i40e_bus_speed_reserved
 449 };
 450
 451 /* PCI bus widths */
 452 enum i40e_bus_width {
 453         i40e_bus_width_unknown  = 0,
 454         i40e_bus_width_pcie_x1  = 1,
 455         i40e_bus_width_pcie_x2  = 2,
 456         i40e_bus_width_pcie_x4  = 4,
 457         i40e_bus_width_pcie_x8  = 8,
 458         i40e_bus_width_32       = 32,
 459         i40e_bus_width_64       = 64,
 460         i40e_bus_width_reserved
 461 };
 462
 463 /* Bus parameters */
 464 struct i40e_bus_info {
 465         enum i40e_bus_speed speed;
 466         enum i40e_bus_width width;
 467         enum i40e_bus_type type;
 468
 469         u16 func;
 470         u16 device;
 471         u16 lan_id;
 472 };
 473
 474 /* Flow control (FC) parameters */
 475 struct i40e_fc_info {
 476         enum i40e_fc_mode current_mode; /* FC mode in effect */
 477         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 478 };
 479
 480 #define I40E_MAX_TRAFFIC_CLASS          8
 481 #define I40E_MAX_USER_PRIORITY          8
 482 #define I40E_DCBX_MAX_APPS              32
 483 #define I40E_LLDPDU_SIZE                1500
 484 #define I40E_TLV_STATUS_OPER            0x1
 485 #define I40E_TLV_STATUS_SYNC            0x2
 486 #define I40E_TLV_STATUS_ERR             0x4
 487 #define I40E_CEE_OPER_MAX_APPS          3
 488 #define I40E_APP_PROTOID_FCOE           0x8906
 489 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 490 #define I40E_APP_PROTOID_FIP            0x8914
 491 #define I40E_APP_SEL_ETHTYPE            0x1
 492 #define I40E_APP_SEL_TCPIP              0x2
 493 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 494 #define I40E_CEE_APP_SEL_TCPIP          0x1
 495
 496 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 497 struct i40e_dcb_ets_config {
 498         u8 willing;
 499         u8 cbs;
 500         u8 maxtcs;
 501         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 502         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 503         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 504 };
 505
 506 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 507 struct i40e_dcb_pfc_config {
 508         u8 willing;
 509         u8 mbc;
 510         u8 pfccap;
 511         u8 pfcenable;
 512 };
 513
 514 /* CEE or IEEE 802.1Qaz Application Priority data */
 515 struct i40e_dcb_app_priority_table {
 516         u8  priority;
 517         u8  selector;
 518         u16 protocolid;
 519 };
 520
 521 struct i40e_dcbx_config {
 522         u8  dcbx_mode;
 523 #define I40E_DCBX_MODE_CEE      0x1
 524 #define I40E_DCBX_MODE_IEEE     0x2
 525         u8  app_mode;
 526 #define I40E_DCBX_APPS_NON_WILLING      0x1
 527         u32 numapps;
 528         struct i40e_dcb_ets_config etscfg;
 529         struct i40e_dcb_ets_config etsrec;
 530         struct i40e_dcb_pfc_config pfc;
 531         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 532 };
 533
 534 /* Port hardware description */
 535 struct i40e_hw {
 536         u8 *hw_addr;
 537         void *back;
 538
 539         /* subsystem structs */
 540         struct i40e_phy_info phy;
 541         struct i40e_mac_info mac;
 542         struct i40e_bus_info bus;
 543         struct i40e_nvm_info nvm;
 544         struct i40e_fc_info fc;
 545
 546         /* pci info */
 547         u16 device_id;
 548         u16 vendor_id;
 549         u16 subsystem_device_id;
 550         u16 subsystem_vendor_id;
 551         u8 revision_id;
 552         u8 port;
 553         bool adapter_stopped;
 554
 555         /* capabilities for entire device and PCI func */
 556         struct i40e_hw_capabilities dev_caps;
 557         struct i40e_hw_capabilities func_caps;
 558
 559         /* Flow Director shared filter space */
 560         u16 fdir_shared_filter_count;
 561
 562         /* device profile info */
 563         u8  pf_id;
 564         u16 main_vsi_seid;
 565
 566         /* for multi-function MACs */
 567         u16 partition_id;
 568         u16 num_partitions;
 569         u16 num_ports;
 570
 571         /* Closest numa node to the device */
 572         u16 numa_node;
 573
 574         /* Admin Queue info */
 575         struct i40e_adminq_info aq;
 576
 577         /* state of nvm update process */
 578         enum i40e_nvmupd_state nvmupd_state;
 579         struct i40e_aq_desc nvm_wb_desc;
 580         struct i40e_virt_mem nvm_buff;
 581
 582         /* HMC info */
 583         struct i40e_hmc_info hmc; /* HMC info struct */
 584
 585         /* LLDP/DCBX Status */
 586         u16 dcbx_status;
 587
 588         /* DCBX info */
 589         struct i40e_dcbx_config local_dcbx_config;
 590         struct i40e_dcbx_config remote_dcbx_config;
 591
 592         /* debug mask */
 593         u32 debug_mask;
 594 #ifndef I40E_NDIS_SUPPORT
 595         char err_str[16];
 596 #endif /* I40E_NDIS_SUPPORT */
 597 };
 598
 599 static inline bool i40e_is_vf(struct i40e_hw *hw)
 600 {
 601         return hw->mac.type == I40E_MAC_VF;
 602 }
 603
 604 struct i40e_driver_version {
 605         u8 major_version;
 606         u8 minor_version;
 607         u8 build_version;
 608         u8 subbuild_version;
 609         u8 driver_string[32];
 610 };
 611
 612 /* RX Descriptors */
 613 union i40e_16byte_rx_desc {
 614         struct {
 615                 __le64 pkt_addr; /* Packet buffer address */
 616                 __le64 hdr_addr; /* Header buffer address */
 617         } read;
 618         struct {
 619                 struct {
 620                         struct {
 621                                 union {
 622                                         __le16 mirroring_status;
 623                                         __le16 fcoe_ctx_id;
 624                                 } mirr_fcoe;
 625                                 __le16 l2tag1;
 626                         } lo_dword;
 627                         union {
 628                                 __le32 rss; /* RSS Hash */
 629                                 __le32 fd_id; /* Flow director filter id */
 630                                 __le32 fcoe_param; /* FCoE DDP Context id */
 631                         } hi_dword;
 632                 } qword0;
 633                 struct {
 634                         /* ext status/error/pktype/length */
 635                         __le64 status_error_len;
 636                 } qword1;
 637         } wb;  /* writeback */
 638 };
 639
 640 union i40e_32byte_rx_desc {
 641         struct {
 642                 __le64  pkt_addr; /* Packet buffer address */
 643                 __le64  hdr_addr; /* Header buffer address */
 644                         /* bit 0 of hdr_buffer_addr is DD bit */
 645                 __le64  rsvd1;
 646                 __le64  rsvd2;
 647         } read;
 648         struct {
 649                 struct {
 650                         struct {
 651                                 union {
 652                                         __le16 mirroring_status;
 653                                         __le16 fcoe_ctx_id;
 654                                 } mirr_fcoe;
 655                                 __le16 l2tag1;
 656                         } lo_dword;
 657                         union {
 658                                 __le32 rss; /* RSS Hash */
 659                                 __le32 fcoe_param; /* FCoE DDP Context id */
 660                                 /* Flow director filter id in case of
 661                                  * Programming status desc WB
 662                                  */
 663                                 __le32 fd_id;
 664                         } hi_dword;
 665                 } qword0;
 666                 struct {
 667                         /* status/error/pktype/length */
 668                         __le64 status_error_len;
 669                 } qword1;
 670                 struct {
 671                         __le16 ext_status; /* extended status */
 672                         __le16 rsvd;
 673                         __le16 l2tag2_1;
 674                         __le16 l2tag2_2;
 675                 } qword2;
 676                 struct {
 677                         union {
 678                                 __le32 flex_bytes_lo;
 679                                 __le32 pe_status;
 680                         } lo_dword;
 681                         union {
 682                                 __le32 flex_bytes_hi;
 683                                 __le32 fd_id;
 684                         } hi_dword;
 685                 } qword3;
 686         } wb;  /* writeback */
 687 };
 688
 689 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 690 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 691                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 692 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 693 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 694                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 695
 696 enum i40e_rx_desc_status_bits {
 697         /* Note: These are predefined bit offsets */
 698         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 699         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 700         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 701         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 702         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 703         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 704         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 705         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 706
 707         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 708         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 709         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 710         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 711         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 712         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 713         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 714         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 715 };
 716
 717 #define I40E_RXD_QW1_STATUS_SHIFT       0
 718 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 719                                          I40E_RXD_QW1_STATUS_SHIFT)
 720
 721 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 722 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 723                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 724
 725 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 726 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 727
 728 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 729 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 730                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 731
 732 enum i40e_rx_desc_fltstat_values {
 733         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 734         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 735         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 736         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 737 };
 738
 739 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 740 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 741 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 742 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 743
 744 #define I40E_RXD_QW1_ERROR_SHIFT        19
 745 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 746
 747 enum i40e_rx_desc_error_bits {
 748         /* Note: These are predefined bit offsets */
 749         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 750         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 751         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 752         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 753         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 754         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 755         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 756         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 757         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 758 };
 759
 760 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 761         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 762         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 763         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 764         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 765         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 766 };
 767
 768 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 769 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 770
 771 /* Packet type non-ip values */
 772 enum i40e_rx_l2_ptype {
 773         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 774         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 775         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 776         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 777         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 778         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 779         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 780         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 781         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 782         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 783         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 784         I40E_RX_PTYPE_L2_ARP                            = 11,
 785         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 786         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 787         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 788         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 789         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 790         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 791         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 792         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 793         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 794         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 795         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 796         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 797         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 798         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 799 };
 800
 801 struct i40e_rx_ptype_decoded {
 802         u32 ptype:8;
 803         u32 known:1;
 804         u32 outer_ip:1;
 805         u32 outer_ip_ver:1;
 806         u32 outer_frag:1;
 807         u32 tunnel_type:3;
 808         u32 tunnel_end_prot:2;
 809         u32 tunnel_end_frag:1;
 810         u32 inner_prot:4;
 811         u32 payload_layer:3;
 812 };
 813
 814 enum i40e_rx_ptype_outer_ip {
 815         I40E_RX_PTYPE_OUTER_L2  = 0,
 816         I40E_RX_PTYPE_OUTER_IP  = 1
 817 };
 818
 819 enum i40e_rx_ptype_outer_ip_ver {
 820         I40E_RX_PTYPE_OUTER_NONE        = 0,
 821         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 822         I40E_RX_PTYPE_OUTER_IPV6        = 1
 823 };
 824
 825 enum i40e_rx_ptype_outer_fragmented {
 826         I40E_RX_PTYPE_NOT_FRAG  = 0,
 827         I40E_RX_PTYPE_FRAG      = 1
 828 };
 829
 830 enum i40e_rx_ptype_tunnel_type {
 831         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 832         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 833         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 834         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 835         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 836 };
 837
 838 enum i40e_rx_ptype_tunnel_end_prot {
 839         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 840         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 841         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 842 };
 843
 844 enum i40e_rx_ptype_inner_prot {
 845         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 846         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 847         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 848         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 849         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 850         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 851 };
 852
 853 enum i40e_rx_ptype_payload_layer {
 854         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 855         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 856         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 857         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 858 };
 859
 860 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 861 #define I40E_RX_PTYPE_SHIFT             56
 862
 863 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 864 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 865                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 866
 867 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 868 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 869                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 870
 871 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 872 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 873
 874 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 875 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 876
 877 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 878 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 879                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 880
 881 enum i40e_rx_desc_ext_status_bits {
 882         /* Note: These are predefined bit offsets */
 883         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 884         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 885         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 886         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 887         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 888         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 889         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 890 };
 891
 892 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 893 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 894
 895 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 896 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 897
 898 enum i40e_rx_desc_pe_status_bits {
 899         /* Note: These are predefined bit offsets */
 900         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 901         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 902         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 903         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 904         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 905         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 906         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 907         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 908         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 909 };
 910
 911 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 912 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 913
 914 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 915 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 916                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 917
 918 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 919 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 920                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 921
 922 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 923 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 924                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 925
 926 enum i40e_rx_prog_status_desc_status_bits {
 927         /* Note: These are predefined bit offsets */
 928         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 929         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 930 };
 931
 932 enum i40e_rx_prog_status_desc_prog_id_masks {
 933         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 934         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 935         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 936 };
 937
 938 enum i40e_rx_prog_status_desc_error_bits {
 939         /* Note: These are predefined bit offsets */
 940         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 941         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 942         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 943         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 944 };
 945
 946 #define I40E_TWO_BIT_MASK       0x3
 947 #define I40E_THREE_BIT_MASK     0x7
 948 #define I40E_FOUR_BIT_MASK      0xF
 949 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 950
 951 /* TX Descriptor */
 952 struct i40e_tx_desc {
 953         __le64 buffer_addr; /* Address of descriptor's data buf */
 954         __le64 cmd_type_offset_bsz;
 955 };
 956
 957 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 958 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 959
 960 enum i40e_tx_desc_dtype_value {
 961         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 962         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 963         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 964         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 965         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 966         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 967         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 968         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 969         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 970         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 971 };
 972
 973 #define I40E_TXD_QW1_CMD_SHIFT  4
 974 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 975
 976 enum i40e_tx_desc_cmd_bits {
 977         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 978         I40E_TX_DESC_CMD_RS                     = 0x0002,
 979         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 980         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 981         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 982         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 983         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 984         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 985         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 986         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 987         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 988         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 989         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 990         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 991         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 992         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 993         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 994         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 995 };
 996
 997 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 998 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 999                                          I40E_TXD_QW1_OFFSET_SHIFT)
1000
1001 enum i40e_tx_desc_length_fields {
1002         /* Note: These are predefined bit offsets */
1003         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1004         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1005         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1006 };
1007
1008 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1009 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1010 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1011 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1012
1013 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1014 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1015                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1016
1017 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1018 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1019
1020 /* Context descriptors */
1021 struct i40e_tx_context_desc {
1022         __le32 tunneling_params;
1023         __le16 l2tag2;
1024         __le16 rsvd;
1025         __le64 type_cmd_tso_mss;
1026 };
1027
1028 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1029 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1030
1031 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1032 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1033
1034 enum i40e_tx_ctx_desc_cmd_bits {
1035         I40E_TX_CTX_DESC_TSO            = 0x01,
1036         I40E_TX_CTX_DESC_TSYN           = 0x02,
1037         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1038         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1039         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1040         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1041         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1042         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1043         I40E_TX_CTX_DESC_SWPE           = 0x40
1044 };
1045
1046 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1047 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1048                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1049
1050 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1051 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1052                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1053
1054 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1055 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1056
1057 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1058 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1059                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1060
1061 enum i40e_tx_ctx_desc_eipt_offload {
1062         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1063         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1064         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1065         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1066 };
1067
1068 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1069 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1070                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1071
1072 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1073 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1074
1075 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1076 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1077
1078 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1079 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1080
1081 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1082
1083 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1084 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1085                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1086
1087 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1088 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1089                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1090
1091 struct i40e_nop_desc {
1092         __le64 rsvd;
1093         __le64 dtype_cmd;
1094 };
1095
1096 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1097 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1098
1099 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1100 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1101
1102 enum i40e_tx_nop_desc_cmd_bits {
1103         /* Note: These are predefined bit offsets */
1104         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1105         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1106         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1107 };
1108
1109 struct i40e_filter_program_desc {
1110         __le32 qindex_flex_ptype_vsi;
1111         __le32 rsvd;
1112         __le32 dtype_cmd_cntindex;
1113         __le32 fd_id;
1114 };
1115 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1116 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1117                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1118 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1119 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1120                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1121 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1122 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1123                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1124
1125 /* Packet Classifier Types for filters */
1126 enum i40e_filter_pctype {
1127         /* Note: Values 0-30 are reserved for future use */
1128         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1129         /* Note: Value 32 is reserved for future use */
1130         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1131         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1132         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1133         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1134         /* Note: Values 37-40 are reserved for future use */
1135         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1136         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1137         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1138         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1139         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1140         /* Note: Value 47 is reserved for future use */
1141         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1142         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1143         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1144         /* Note: Values 51-62 are reserved for future use */
1145         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1146 };
1147
1148 enum i40e_filter_program_desc_dest {
1149         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1150         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1151         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1152 };
1153
1154 enum i40e_filter_program_desc_fd_status {
1155         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1156         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1157         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1158         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1159 };
1160
1161 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1162 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1163                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1164
1165 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1166 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1167
1168 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1169 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1170                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1171
1172 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1173 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1174
1175 enum i40e_filter_program_desc_pcmd {
1176         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1177         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1178 };
1179
1180 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1181 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1182
1183 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1184 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1185
1186 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1187                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1188 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1189                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1190
1191 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1192 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1193                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1194
1195 enum i40e_filter_type {
1196         I40E_FLOW_DIRECTOR_FLTR = 0,
1197         I40E_PE_QUAD_HASH_FLTR = 1,
1198         I40E_ETHERTYPE_FLTR,
1199         I40E_FCOE_CTX_FLTR,
1200         I40E_MAC_VLAN_FLTR,
1201         I40E_HASH_FLTR
1202 };
1203
1204 struct i40e_vsi_context {
1205         u16 seid;
1206         u16 uplink_seid;
1207         u16 vsi_number;
1208         u16 vsis_allocated;
1209         u16 vsis_unallocated;
1210         u16 flags;
1211         u8 pf_num;
1212         u8 vf_num;
1213         u8 connection_type;
1214         struct i40e_aqc_vsi_properties_data info;
1215 };
1216
1217 struct i40e_veb_context {
1218         u16 seid;
1219         u16 uplink_seid;
1220         u16 veb_number;
1221         u16 vebs_allocated;
1222         u16 vebs_unallocated;
1223         u16 flags;
1224         struct i40e_aqc_get_veb_parameters_completion info;
1225 };
1226
1227 /* Statistics collected by each port, VSI, VEB, and S-channel */
1228 struct i40e_eth_stats {
1229         u64 rx_bytes;                   /* gorc */
1230         u64 rx_unicast;                 /* uprc */
1231         u64 rx_multicast;               /* mprc */
1232         u64 rx_broadcast;               /* bprc */
1233         u64 rx_discards;                /* rdpc */
1234         u64 rx_unknown_protocol;        /* rupp */
1235         u64 tx_bytes;                   /* gotc */
1236         u64 tx_unicast;                 /* uptc */
1237         u64 tx_multicast;               /* mptc */
1238         u64 tx_broadcast;               /* bptc */
1239         u64 tx_discards;                /* tdpc */
1240         u64 tx_errors;                  /* tepc */
1241 };
1242
1243 /* Statistics collected per VEB per TC */
1244 struct i40e_veb_tc_stats {
1245         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1246         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1247         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1248         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1249 };
1250
1251 /* Statistics collected by the MAC */
1252 struct i40e_hw_port_stats {
1253         /* eth stats collected by the port */
1254         struct i40e_eth_stats eth;
1255
1256         /* additional port specific stats */
1257         u64 tx_dropped_link_down;       /* tdold */
1258         u64 crc_errors;                 /* crcerrs */
1259         u64 illegal_bytes;              /* illerrc */
1260         u64 error_bytes;                /* errbc */
1261         u64 mac_local_faults;           /* mlfc */
1262         u64 mac_remote_faults;          /* mrfc */
1263         u64 rx_length_errors;           /* rlec */
1264         u64 link_xon_rx;                /* lxonrxc */
1265         u64 link_xoff_rx;               /* lxoffrxc */
1266         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1267         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1268         u64 link_xon_tx;                /* lxontxc */
1269         u64 link_xoff_tx;               /* lxofftxc */
1270         u64 priority_xon_tx[8];         /* pxontxc[8] */
1271         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1272         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1273         u64 rx_size_64;                 /* prc64 */
1274         u64 rx_size_127;                /* prc127 */
1275         u64 rx_size_255;                /* prc255 */
1276         u64 rx_size_511;                /* prc511 */
1277         u64 rx_size_1023;               /* prc1023 */
1278         u64 rx_size_1522;               /* prc1522 */
1279         u64 rx_size_big;                /* prc9522 */
1280         u64 rx_undersize;               /* ruc */
1281         u64 rx_fragments;               /* rfc */
1282         u64 rx_oversize;                /* roc */
1283         u64 rx_jabber;                  /* rjc */
1284         u64 tx_size_64;                 /* ptc64 */
1285         u64 tx_size_127;                /* ptc127 */
1286         u64 tx_size_255;                /* ptc255 */
1287         u64 tx_size_511;                /* ptc511 */
1288         u64 tx_size_1023;               /* ptc1023 */
1289         u64 tx_size_1522;               /* ptc1522 */
1290         u64 tx_size_big;                /* ptc9522 */
1291         u64 mac_short_packet_dropped;   /* mspdc */
1292         u64 checksum_error;             /* xec */
1293         /* flow director stats */
1294         u64 fd_atr_match;
1295         u64 fd_sb_match;
1296         /* EEE LPI */
1297         u32 tx_lpi_status;
1298         u32 rx_lpi_status;
1299         u64 tx_lpi_count;               /* etlpic */
1300         u64 rx_lpi_count;               /* erlpic */
1301 };
1302
1303 /* Checksum and Shadow RAM pointers */
1304 #define I40E_SR_NVM_CONTROL_WORD                0x00
1305 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1306 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1307 #define I40E_SR_OPTION_ROM_PTR                  0x05
1308 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1309 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1310 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1311 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1312 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1313 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1314 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1315 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1316 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1317 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1318 #define I40E_SR_PBA_FLAGS                       0x15
1319 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1320 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1321 #define I40E_NVM_OEM_VER_OFF                    0x83
1322 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1323 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1324 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1325 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1326 #define I40E_SR_NVM_MAP_VERSION                 0x29
1327 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1328 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1329 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1330 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1331 #define I40E_SR_VPD_PTR                         0x2F
1332 #define I40E_SR_PXE_SETUP_PTR                   0x30
1333 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1334 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1335 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1336 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1337 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1338 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1339 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1340 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1341 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1342 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1343 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1344 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1345 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1346 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1347 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1348 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1349 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1350 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1351
1352 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1353 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1354 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1355 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1356 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1357
1358 /* Shadow RAM related */
1359 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1360 #define I40E_SR_BUF_ALIGNMENT           4096
1361 #define I40E_SR_WORDS_IN_1KB            512
1362 /* Checksum should be calculated such that after adding all the words,
1363  * including the checksum word itself, the sum should be 0xBABA.
1364  */
1365 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1366
1367 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1368
1369 enum i40e_switch_element_types {
1370         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1371         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1372         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1373         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1374         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1375         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1376         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1377         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1378         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1379 };
1380
1381 /* Supported EtherType filters */
1382 enum i40e_ether_type_index {
1383         I40E_ETHER_TYPE_1588            = 0,
1384         I40E_ETHER_TYPE_FIP             = 1,
1385         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1386         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1387         I40E_ETHER_TYPE_LLDP            = 4,
1388         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1389         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1390         I40E_ETHER_TYPE_QCN_CNM         = 7,
1391         I40E_ETHER_TYPE_8021X           = 8,
1392         I40E_ETHER_TYPE_ARP             = 9,
1393         I40E_ETHER_TYPE_RSV1            = 10,
1394         I40E_ETHER_TYPE_RSV2            = 11,
1395 };
1396
1397 /* Filter context base size is 1K */
1398 #define I40E_HASH_FILTER_BASE_SIZE      1024
1399 /* Supported Hash filter values */
1400 enum i40e_hash_filter_size {
1401         I40E_HASH_FILTER_SIZE_1K        = 0,
1402         I40E_HASH_FILTER_SIZE_2K        = 1,
1403         I40E_HASH_FILTER_SIZE_4K        = 2,
1404         I40E_HASH_FILTER_SIZE_8K        = 3,
1405         I40E_HASH_FILTER_SIZE_16K       = 4,
1406         I40E_HASH_FILTER_SIZE_32K       = 5,
1407         I40E_HASH_FILTER_SIZE_64K       = 6,
1408         I40E_HASH_FILTER_SIZE_128K      = 7,
1409         I40E_HASH_FILTER_SIZE_256K      = 8,
1410         I40E_HASH_FILTER_SIZE_512K      = 9,
1411         I40E_HASH_FILTER_SIZE_1M        = 10,
1412 };
1413
1414 /* DMA context base size is 0.5K */
1415 #define I40E_DMA_CNTX_BASE_SIZE         512
1416 /* Supported DMA context values */
1417 enum i40e_dma_cntx_size {
1418         I40E_DMA_CNTX_SIZE_512          = 0,
1419         I40E_DMA_CNTX_SIZE_1K           = 1,
1420         I40E_DMA_CNTX_SIZE_2K           = 2,
1421         I40E_DMA_CNTX_SIZE_4K           = 3,
1422         I40E_DMA_CNTX_SIZE_8K           = 4,
1423         I40E_DMA_CNTX_SIZE_16K          = 5,
1424         I40E_DMA_CNTX_SIZE_32K          = 6,
1425         I40E_DMA_CNTX_SIZE_64K          = 7,
1426         I40E_DMA_CNTX_SIZE_128K         = 8,
1427         I40E_DMA_CNTX_SIZE_256K         = 9,
1428 };
1429
1430 /* Supported Hash look up table (LUT) sizes */
1431 enum i40e_hash_lut_size {
1432         I40E_HASH_LUT_SIZE_128          = 0,
1433         I40E_HASH_LUT_SIZE_512          = 1,
1434 };
1435
1436 /* Structure to hold a per PF filter control settings */
1437 struct i40e_filter_control_settings {
1438         /* number of PE Quad Hash filter buckets */
1439         enum i40e_hash_filter_size pe_filt_num;
1440         /* number of PE Quad Hash contexts */
1441         enum i40e_dma_cntx_size pe_cntx_num;
1442         /* number of FCoE filter buckets */
1443         enum i40e_hash_filter_size fcoe_filt_num;
1444         /* number of FCoE DDP contexts */
1445         enum i40e_dma_cntx_size fcoe_cntx_num;
1446         /* size of the Hash LUT */
1447         enum i40e_hash_lut_size hash_lut_size;
1448         /* enable FDIR filters for PF and its VFs */
1449         bool enable_fdir;
1450         /* enable Ethertype filters for PF and its VFs */
1451         bool enable_ethtype;
1452         /* enable MAC/VLAN filters for PF and its VFs */
1453         bool enable_macvlan;
1454 };
1455
1456 /* Structure to hold device level control filter counts */
1457 struct i40e_control_filter_stats {
1458         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1459         u16 etype_used;       /* Used perfect EtherType filters */
1460         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1461         u16 etype_free;       /* Un-used perfect EtherType filters */
1462 };
1463
1464 enum i40e_reset_type {
1465         I40E_RESET_POR          = 0,
1466         I40E_RESET_CORER        = 1,
1467         I40E_RESET_GLOBR        = 2,
1468         I40E_RESET_EMPR         = 3,
1469 };
1470
1471 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1472 #define I40E_NVM_LLDP_CFG_PTR           0xD
1473 struct i40e_lldp_variables {
1474         u16 length;
1475         u16 adminstatus;
1476         u16 msgfasttx;
1477         u16 msgtxinterval;
1478         u16 txparams;
1479         u16 timers;
1480         u16 crc8;
1481 };
1482
1483 /* Offsets into Alternate Ram */
1484 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1485 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1486 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1487 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1488 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1489 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1490
1491 /* Alternate Ram Bandwidth Masks */
1492 #define I40E_ALT_BW_VALUE_MASK          0xFF
1493 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1494 #define I40E_ALT_BW_VALID_MASK          0x80000000
1495
1496 /* RSS Hash Table Size */
1497 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1498 #endif /* _I40E_TYPE_H_ */