drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 /* Memory types */
 161 enum i40e_memset_type {
 162         I40E_NONDMA_MEM = 0,
 163         I40E_DMA_MEM
 164 };
 165
 166 /* Memcpy types */
 167 enum i40e_memcpy_type {
 168         I40E_NONDMA_TO_NONDMA = 0,
 169         I40E_NONDMA_TO_DMA,
 170         I40E_DMA_TO_DMA,
 171         I40E_DMA_TO_NONDMA
 172 };
 173
 174
 175 #ifdef X722_SUPPORT
 176 #define I40E_FW_API_VERSION_MINOR_X722  0x0003
 177 #endif
 178 #define I40E_FW_API_VERSION_MINOR_X710  0x0004
 179
 180
 181 /* These are structs for managing the hardware information and the operations.
 182  * The structures of function pointers are filled out at init time when we
 183  * know for sure exactly which hardware we're working with.  This gives us the
 184  * flexibility of using the same main driver code but adapting to slightly
 185  * different hardware needs as new parts are developed.  For this architecture,
 186  * the Firmware and AdminQ are intended to insulate the driver from most of the
 187  * future changes, but these structures will also do part of the job.
 188  */
 189 enum i40e_mac_type {
 190         I40E_MAC_UNKNOWN = 0,
 191         I40E_MAC_X710,
 192         I40E_MAC_XL710,
 193         I40E_MAC_VF,
 194 #ifdef X722_SUPPORT
 195         I40E_MAC_X722,
 196         I40E_MAC_X722_VF,
 197 #endif
 198         I40E_MAC_GENERIC,
 199 };
 200
 201 enum i40e_media_type {
 202         I40E_MEDIA_TYPE_UNKNOWN = 0,
 203         I40E_MEDIA_TYPE_FIBER,
 204         I40E_MEDIA_TYPE_BASET,
 205         I40E_MEDIA_TYPE_BACKPLANE,
 206         I40E_MEDIA_TYPE_CX4,
 207         I40E_MEDIA_TYPE_DA,
 208         I40E_MEDIA_TYPE_VIRTUAL
 209 };
 210
 211 enum i40e_fc_mode {
 212         I40E_FC_NONE = 0,
 213         I40E_FC_RX_PAUSE,
 214         I40E_FC_TX_PAUSE,
 215         I40E_FC_FULL,
 216         I40E_FC_PFC,
 217         I40E_FC_DEFAULT
 218 };
 219
 220 enum i40e_set_fc_aq_failures {
 221         I40E_SET_FC_AQ_FAIL_NONE = 0,
 222         I40E_SET_FC_AQ_FAIL_GET = 1,
 223         I40E_SET_FC_AQ_FAIL_SET = 2,
 224         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 225         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 226 };
 227
 228 enum i40e_vsi_type {
 229         I40E_VSI_MAIN   = 0,
 230         I40E_VSI_VMDQ1  = 1,
 231         I40E_VSI_VMDQ2  = 2,
 232         I40E_VSI_CTRL   = 3,
 233         I40E_VSI_FCOE   = 4,
 234         I40E_VSI_MIRROR = 5,
 235         I40E_VSI_SRIOV  = 6,
 236         I40E_VSI_FDIR   = 7,
 237         I40E_VSI_TYPE_UNKNOWN
 238 };
 239
 240 enum i40e_queue_type {
 241         I40E_QUEUE_TYPE_RX = 0,
 242         I40E_QUEUE_TYPE_TX,
 243         I40E_QUEUE_TYPE_PE_CEQ,
 244         I40E_QUEUE_TYPE_UNKNOWN
 245 };
 246
 247 struct i40e_link_status {
 248         enum i40e_aq_phy_type phy_type;
 249         enum i40e_aq_link_speed link_speed;
 250         u8 link_info;
 251         u8 an_info;
 252         u8 ext_info;
 253         u8 loopback;
 254         /* is Link Status Event notification to SW enabled */
 255         bool lse_enable;
 256         u16 max_frame_size;
 257         bool crc_enable;
 258         u8 pacing;
 259         u8 requested_speeds;
 260         u8 module_type[3];
 261         /* 1st byte: module identifier */
 262 #define I40E_MODULE_TYPE_SFP            0x03
 263 #define I40E_MODULE_TYPE_QSFP           0x0D
 264         /* 2nd byte: ethernet compliance codes for 10/40G */
 265 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 266 #define I40E_MODULE_TYPE_40G_LR4        0x02
 267 #define I40E_MODULE_TYPE_40G_SR4        0x04
 268 #define I40E_MODULE_TYPE_40G_CR4        0x08
 269 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 270 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 271 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 272 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 273         /* 3rd byte: ethernet compliance codes for 1G */
 274 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 275 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 276 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 277 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 278 };
 279
 280 enum i40e_aq_capabilities_phy_type {
 281         I40E_CAP_PHY_TYPE_SGMII                 = BIT(I40E_PHY_TYPE_SGMII),
 282         I40E_CAP_PHY_TYPE_1000BASE_KX           = BIT(I40E_PHY_TYPE_1000BASE_KX),
 283         I40E_CAP_PHY_TYPE_10GBASE_KX4           = BIT(I40E_PHY_TYPE_10GBASE_KX4),
 284         I40E_CAP_PHY_TYPE_10GBASE_KR            = BIT(I40E_PHY_TYPE_10GBASE_KR),
 285         I40E_CAP_PHY_TYPE_40GBASE_KR4           = BIT(I40E_PHY_TYPE_40GBASE_KR4),
 286         I40E_CAP_PHY_TYPE_XAUI                  = BIT(I40E_PHY_TYPE_XAUI),
 287         I40E_CAP_PHY_TYPE_XFI                   = BIT(I40E_PHY_TYPE_XFI),
 288         I40E_CAP_PHY_TYPE_SFI                   = BIT(I40E_PHY_TYPE_SFI),
 289         I40E_CAP_PHY_TYPE_XLAUI                 = BIT(I40E_PHY_TYPE_XLAUI),
 290         I40E_CAP_PHY_TYPE_XLPPI                 = BIT(I40E_PHY_TYPE_XLPPI),
 291         I40E_CAP_PHY_TYPE_40GBASE_CR4_CU        = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
 292         I40E_CAP_PHY_TYPE_10GBASE_CR1_CU        = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
 293         I40E_CAP_PHY_TYPE_10GBASE_AOC           = BIT(I40E_PHY_TYPE_10GBASE_AOC),
 294         I40E_CAP_PHY_TYPE_40GBASE_AOC           = BIT(I40E_PHY_TYPE_40GBASE_AOC),
 295         I40E_CAP_PHY_TYPE_100BASE_TX            = BIT(I40E_PHY_TYPE_100BASE_TX),
 296         I40E_CAP_PHY_TYPE_1000BASE_T            = BIT(I40E_PHY_TYPE_1000BASE_T),
 297         I40E_CAP_PHY_TYPE_10GBASE_T             = BIT(I40E_PHY_TYPE_10GBASE_T),
 298         I40E_CAP_PHY_TYPE_10GBASE_SR            = BIT(I40E_PHY_TYPE_10GBASE_SR),
 299         I40E_CAP_PHY_TYPE_10GBASE_LR            = BIT(I40E_PHY_TYPE_10GBASE_LR),
 300         I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU       = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
 301         I40E_CAP_PHY_TYPE_10GBASE_CR1           = BIT(I40E_PHY_TYPE_10GBASE_CR1),
 302         I40E_CAP_PHY_TYPE_40GBASE_CR4           = BIT(I40E_PHY_TYPE_40GBASE_CR4),
 303         I40E_CAP_PHY_TYPE_40GBASE_SR4           = BIT(I40E_PHY_TYPE_40GBASE_SR4),
 304         I40E_CAP_PHY_TYPE_40GBASE_LR4           = BIT(I40E_PHY_TYPE_40GBASE_LR4),
 305         I40E_CAP_PHY_TYPE_1000BASE_SX           = BIT(I40E_PHY_TYPE_1000BASE_SX),
 306         I40E_CAP_PHY_TYPE_1000BASE_LX           = BIT(I40E_PHY_TYPE_1000BASE_LX),
 307         I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL    = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
 308         I40E_CAP_PHY_TYPE_20GBASE_KR2           = BIT(I40E_PHY_TYPE_20GBASE_KR2)
 309 };
 310
 311 struct i40e_phy_info {
 312         struct i40e_link_status link_info;
 313         struct i40e_link_status link_info_old;
 314         bool get_link_info;
 315         enum i40e_media_type media_type;
 316         /* all the phy types the NVM is capable of */
 317         u32 phy_types;
 318 };
 319
 320 #define I40E_HW_CAP_MAX_GPIO                    30
 321 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 322 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 323
 324 #ifdef X722_SUPPORT
 325 enum i40e_acpi_programming_method {
 326         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 327         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 328 };
 329
 330 #define I40E_WOL_SUPPORT_MASK                   1
 331 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 332 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 333
 334 #endif
 335 /* Capabilities of a PF or a VF or the whole device */
 336 struct i40e_hw_capabilities {
 337         u32  switch_mode;
 338 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 339 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 340 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 341
 342         u32  management_mode;
 343         u32  npar_enable;
 344         u32  os2bmc;
 345         u32  valid_functions;
 346         bool sr_iov_1_1;
 347         bool vmdq;
 348         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 349         bool evb_802_1_qbh; /* Bridge Port Extension */
 350         bool dcb;
 351         bool fcoe;
 352         bool iscsi; /* Indicates iSCSI enabled */
 353         bool flex10_enable;
 354         bool flex10_capable;
 355         u32  flex10_mode;
 356 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 357 #define I40E_FLEX10_MODE_DCC            0x1
 358 #define I40E_FLEX10_MODE_DCI            0x2
 359
 360         u32 flex10_status;
 361 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 362 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 363
 364         bool mgmt_cem;
 365         bool ieee_1588;
 366         bool iwarp;
 367         bool fd;
 368         u32 fd_filters_guaranteed;
 369         u32 fd_filters_best_effort;
 370         bool rss;
 371         u32 rss_table_size;
 372         u32 rss_table_entry_width;
 373         bool led[I40E_HW_CAP_MAX_GPIO];
 374         bool sdp[I40E_HW_CAP_MAX_GPIO];
 375         u32 nvm_image_type;
 376         u32 num_flow_director_filters;
 377         u32 num_vfs;
 378         u32 vf_base_id;
 379         u32 num_vsis;
 380         u32 num_rx_qp;
 381         u32 num_tx_qp;
 382         u32 base_queue;
 383         u32 num_msix_vectors;
 384         u32 num_msix_vectors_vf;
 385         u32 led_pin_num;
 386         u32 sdp_pin_num;
 387         u32 mdio_port_num;
 388         u32 mdio_port_mode;
 389         u8 rx_buf_chain_len;
 390         u32 enabled_tcmap;
 391         u32 maxtc;
 392         u64 wr_csr_prot;
 393 #ifdef X722_SUPPORT
 394         bool apm_wol_support;
 395         enum i40e_acpi_programming_method acpi_prog_method;
 396         bool proxy_support;
 397 #endif
 398 };
 399
 400 struct i40e_mac_info {
 401         enum i40e_mac_type type;
 402         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 403         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 404         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 405         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 406         u16 max_fcoeq;
 407 };
 408
 409 enum i40e_aq_resources_ids {
 410         I40E_NVM_RESOURCE_ID = 1
 411 };
 412
 413 enum i40e_aq_resource_access_type {
 414         I40E_RESOURCE_READ = 1,
 415         I40E_RESOURCE_WRITE
 416 };
 417
 418 struct i40e_nvm_info {
 419         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 420         u32 timeout;              /* [ms] */
 421         u16 sr_size;              /* Shadow RAM size in words */
 422         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 423         u16 version;              /* NVM package version */
 424         u32 eetrack;              /* NVM data version */
 425         u32 oem_ver;              /* OEM version info */
 426 };
 427
 428 /* definitions used in NVM update support */
 429
 430 enum i40e_nvmupd_cmd {
 431         I40E_NVMUPD_INVALID,
 432         I40E_NVMUPD_READ_CON,
 433         I40E_NVMUPD_READ_SNT,
 434         I40E_NVMUPD_READ_LCB,
 435         I40E_NVMUPD_READ_SA,
 436         I40E_NVMUPD_WRITE_ERA,
 437         I40E_NVMUPD_WRITE_CON,
 438         I40E_NVMUPD_WRITE_SNT,
 439         I40E_NVMUPD_WRITE_LCB,
 440         I40E_NVMUPD_WRITE_SA,
 441         I40E_NVMUPD_CSUM_CON,
 442         I40E_NVMUPD_CSUM_SA,
 443         I40E_NVMUPD_CSUM_LCB,
 444         I40E_NVMUPD_STATUS,
 445         I40E_NVMUPD_EXEC_AQ,
 446         I40E_NVMUPD_GET_AQ_RESULT,
 447 };
 448
 449 enum i40e_nvmupd_state {
 450         I40E_NVMUPD_STATE_INIT,
 451         I40E_NVMUPD_STATE_READING,
 452         I40E_NVMUPD_STATE_WRITING,
 453         I40E_NVMUPD_STATE_INIT_WAIT,
 454         I40E_NVMUPD_STATE_WRITE_WAIT,
 455 };
 456
 457 /* nvm_access definition and its masks/shifts need to be accessible to
 458  * application, core driver, and shared code.  Where is the right file?
 459  */
 460 #define I40E_NVM_READ   0xB
 461 #define I40E_NVM_WRITE  0xC
 462
 463 #define I40E_NVM_MOD_PNT_MASK 0xFF
 464
 465 #define I40E_NVM_TRANS_SHIFT    8
 466 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 467 #define I40E_NVM_CON            0x0
 468 #define I40E_NVM_SNT            0x1
 469 #define I40E_NVM_LCB            0x2
 470 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 471 #define I40E_NVM_ERA            0x4
 472 #define I40E_NVM_CSUM           0x8
 473 #define I40E_NVM_EXEC           0xf
 474
 475 #define I40E_NVM_ADAPT_SHIFT    16
 476 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 477
 478 #define I40E_NVMUPD_MAX_DATA    4096
 479 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 480
 481 struct i40e_nvm_access {
 482         u32 command;
 483         u32 config;
 484         u32 offset;     /* in bytes */
 485         u32 data_size;  /* in bytes */
 486         u8 data[1];
 487 };
 488
 489 /* PCI bus types */
 490 enum i40e_bus_type {
 491         i40e_bus_type_unknown = 0,
 492         i40e_bus_type_pci,
 493         i40e_bus_type_pcix,
 494         i40e_bus_type_pci_express,
 495         i40e_bus_type_reserved
 496 };
 497
 498 /* PCI bus speeds */
 499 enum i40e_bus_speed {
 500         i40e_bus_speed_unknown  = 0,
 501         i40e_bus_speed_33       = 33,
 502         i40e_bus_speed_66       = 66,
 503         i40e_bus_speed_100      = 100,
 504         i40e_bus_speed_120      = 120,
 505         i40e_bus_speed_133      = 133,
 506         i40e_bus_speed_2500     = 2500,
 507         i40e_bus_speed_5000     = 5000,
 508         i40e_bus_speed_8000     = 8000,
 509         i40e_bus_speed_reserved
 510 };
 511
 512 /* PCI bus widths */
 513 enum i40e_bus_width {
 514         i40e_bus_width_unknown  = 0,
 515         i40e_bus_width_pcie_x1  = 1,
 516         i40e_bus_width_pcie_x2  = 2,
 517         i40e_bus_width_pcie_x4  = 4,
 518         i40e_bus_width_pcie_x8  = 8,
 519         i40e_bus_width_32       = 32,
 520         i40e_bus_width_64       = 64,
 521         i40e_bus_width_reserved
 522 };
 523
 524 /* Bus parameters */
 525 struct i40e_bus_info {
 526         enum i40e_bus_speed speed;
 527         enum i40e_bus_width width;
 528         enum i40e_bus_type type;
 529
 530         u16 func;
 531         u16 device;
 532         u16 lan_id;
 533 };
 534
 535 /* Flow control (FC) parameters */
 536 struct i40e_fc_info {
 537         enum i40e_fc_mode current_mode; /* FC mode in effect */
 538         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 539 };
 540
 541 #define I40E_MAX_TRAFFIC_CLASS          8
 542 #define I40E_MAX_USER_PRIORITY          8
 543 #define I40E_DCBX_MAX_APPS              32
 544 #define I40E_LLDPDU_SIZE                1500
 545 #define I40E_TLV_STATUS_OPER            0x1
 546 #define I40E_TLV_STATUS_SYNC            0x2
 547 #define I40E_TLV_STATUS_ERR             0x4
 548 #define I40E_CEE_OPER_MAX_APPS          3
 549 #define I40E_APP_PROTOID_FCOE           0x8906
 550 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 551 #define I40E_APP_PROTOID_FIP            0x8914
 552 #define I40E_APP_SEL_ETHTYPE            0x1
 553 #define I40E_APP_SEL_TCPIP              0x2
 554 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 555 #define I40E_CEE_APP_SEL_TCPIP          0x1
 556
 557 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 558 struct i40e_dcb_ets_config {
 559         u8 willing;
 560         u8 cbs;
 561         u8 maxtcs;
 562         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 563         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 564         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 565 };
 566
 567 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 568 struct i40e_dcb_pfc_config {
 569         u8 willing;
 570         u8 mbc;
 571         u8 pfccap;
 572         u8 pfcenable;
 573 };
 574
 575 /* CEE or IEEE 802.1Qaz Application Priority data */
 576 struct i40e_dcb_app_priority_table {
 577         u8  priority;
 578         u8  selector;
 579         u16 protocolid;
 580 };
 581
 582 struct i40e_dcbx_config {
 583         u8  dcbx_mode;
 584 #define I40E_DCBX_MODE_CEE      0x1
 585 #define I40E_DCBX_MODE_IEEE     0x2
 586         u8  app_mode;
 587 #define I40E_DCBX_APPS_NON_WILLING      0x1
 588         u32 numapps;
 589         u32 tlv_status; /* CEE mode TLV status */
 590         struct i40e_dcb_ets_config etscfg;
 591         struct i40e_dcb_ets_config etsrec;
 592         struct i40e_dcb_pfc_config pfc;
 593         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 594 };
 595
 596 /* Port hardware description */
 597 struct i40e_hw {
 598         u8 *hw_addr;
 599         void *back;
 600
 601         /* subsystem structs */
 602         struct i40e_phy_info phy;
 603         struct i40e_mac_info mac;
 604         struct i40e_bus_info bus;
 605         struct i40e_nvm_info nvm;
 606         struct i40e_fc_info fc;
 607
 608         /* pci info */
 609         u16 device_id;
 610         u16 vendor_id;
 611         u16 subsystem_device_id;
 612         u16 subsystem_vendor_id;
 613         u8 revision_id;
 614         u8 port;
 615         bool adapter_stopped;
 616
 617         /* capabilities for entire device and PCI func */
 618         struct i40e_hw_capabilities dev_caps;
 619         struct i40e_hw_capabilities func_caps;
 620
 621         /* Flow Director shared filter space */
 622         u16 fdir_shared_filter_count;
 623
 624         /* device profile info */
 625         u8  pf_id;
 626         u16 main_vsi_seid;
 627
 628         /* for multi-function MACs */
 629         u16 partition_id;
 630         u16 num_partitions;
 631         u16 num_ports;
 632
 633         /* Closest numa node to the device */
 634         u16 numa_node;
 635
 636         /* Admin Queue info */
 637         struct i40e_adminq_info aq;
 638
 639         /* state of nvm update process */
 640         enum i40e_nvmupd_state nvmupd_state;
 641         struct i40e_aq_desc nvm_wb_desc;
 642         struct i40e_virt_mem nvm_buff;
 643
 644         /* HMC info */
 645         struct i40e_hmc_info hmc; /* HMC info struct */
 646
 647         /* LLDP/DCBX Status */
 648         u16 dcbx_status;
 649
 650         /* DCBX info */
 651         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 652         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 653         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 654
 655 #ifdef X722_SUPPORT
 656         /* WoL and proxy support */
 657         u16 num_wol_proxy_filters;
 658         u16 wol_proxy_vsi_seid;
 659
 660 #endif
 661 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 662         u64 flags;
 663
 664         /* debug mask */
 665         u32 debug_mask;
 666 #ifndef I40E_NDIS_SUPPORT
 667         char err_str[16];
 668 #endif /* I40E_NDIS_SUPPORT */
 669 };
 670
 671 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 672 {
 673 #ifdef X722_SUPPORT
 674         return (hw->mac.type == I40E_MAC_VF ||
 675                 hw->mac.type == I40E_MAC_X722_VF);
 676 #else
 677         return hw->mac.type == I40E_MAC_VF;
 678 #endif
 679 }
 680
 681 struct i40e_driver_version {
 682         u8 major_version;
 683         u8 minor_version;
 684         u8 build_version;
 685         u8 subbuild_version;
 686         u8 driver_string[32];
 687 };
 688
 689 /* RX Descriptors */
 690 union i40e_16byte_rx_desc {
 691         struct {
 692                 __le64 pkt_addr; /* Packet buffer address */
 693                 __le64 hdr_addr; /* Header buffer address */
 694         } read;
 695         struct {
 696                 struct {
 697                         struct {
 698                                 union {
 699                                         __le16 mirroring_status;
 700                                         __le16 fcoe_ctx_id;
 701                                 } mirr_fcoe;
 702                                 __le16 l2tag1;
 703                         } lo_dword;
 704                         union {
 705                                 __le32 rss; /* RSS Hash */
 706                                 __le32 fd_id; /* Flow director filter id */
 707                                 __le32 fcoe_param; /* FCoE DDP Context id */
 708                         } hi_dword;
 709                 } qword0;
 710                 struct {
 711                         /* ext status/error/pktype/length */
 712                         __le64 status_error_len;
 713                 } qword1;
 714         } wb;  /* writeback */
 715 };
 716
 717 union i40e_32byte_rx_desc {
 718         struct {
 719                 __le64  pkt_addr; /* Packet buffer address */
 720                 __le64  hdr_addr; /* Header buffer address */
 721                         /* bit 0 of hdr_buffer_addr is DD bit */
 722                 __le64  rsvd1;
 723                 __le64  rsvd2;
 724         } read;
 725         struct {
 726                 struct {
 727                         struct {
 728                                 union {
 729                                         __le16 mirroring_status;
 730                                         __le16 fcoe_ctx_id;
 731                                 } mirr_fcoe;
 732                                 __le16 l2tag1;
 733                         } lo_dword;
 734                         union {
 735                                 __le32 rss; /* RSS Hash */
 736                                 __le32 fcoe_param; /* FCoE DDP Context id */
 737                                 /* Flow director filter id in case of
 738                                  * Programming status desc WB
 739                                  */
 740                                 __le32 fd_id;
 741                         } hi_dword;
 742                 } qword0;
 743                 struct {
 744                         /* status/error/pktype/length */
 745                         __le64 status_error_len;
 746                 } qword1;
 747                 struct {
 748                         __le16 ext_status; /* extended status */
 749                         __le16 rsvd;
 750                         __le16 l2tag2_1;
 751                         __le16 l2tag2_2;
 752                 } qword2;
 753                 struct {
 754                         union {
 755                                 __le32 flex_bytes_lo;
 756                                 __le32 pe_status;
 757                         } lo_dword;
 758                         union {
 759                                 __le32 flex_bytes_hi;
 760                                 __le32 fd_id;
 761                         } hi_dword;
 762                 } qword3;
 763         } wb;  /* writeback */
 764 };
 765
 766 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 767 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 768                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 769 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 770 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 771                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 772
 773 enum i40e_rx_desc_status_bits {
 774         /* Note: These are predefined bit offsets */
 775         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 776         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 777         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 778         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 779         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 780         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 781         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 782 #ifdef X722_SUPPORT
 783         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 784 #else
 785         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 786 #endif
 787
 788         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 789         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 790         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 791         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 792         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 793         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 794 #ifdef X722_SUPPORT
 795         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 796 #else
 797         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 798 #endif
 799         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 800 };
 801
 802 #define I40E_RXD_QW1_STATUS_SHIFT       0
 803 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 804                                          I40E_RXD_QW1_STATUS_SHIFT)
 805
 806 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 807 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 808                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 809
 810 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 811 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 812
 813 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 814 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 815                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 816
 817 enum i40e_rx_desc_fltstat_values {
 818         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 819         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 820         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 821         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 822 };
 823
 824 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 825 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 826 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 827 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 828
 829 #define I40E_RXD_QW1_ERROR_SHIFT        19
 830 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 831
 832 enum i40e_rx_desc_error_bits {
 833         /* Note: These are predefined bit offsets */
 834         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 835         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 836         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 837         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 838         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 839         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 840         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 841         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 842         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 843 };
 844
 845 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 846         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 847         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 848         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 849         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 850         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 851 };
 852
 853 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 854 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 855
 856 /* Packet type non-ip values */
 857 enum i40e_rx_l2_ptype {
 858         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 859         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 860         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 861         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 862         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 863         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 864         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 865         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 866         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 867         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 868         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 869         I40E_RX_PTYPE_L2_ARP                            = 11,
 870         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 871         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 872         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 873         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 874         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 875         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 876         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 877         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 878         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 879         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 880         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 881         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 882         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 883         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 884 };
 885
 886 struct i40e_rx_ptype_decoded {
 887         u32 ptype:8;
 888         u32 known:1;
 889         u32 outer_ip:1;
 890         u32 outer_ip_ver:1;
 891         u32 outer_frag:1;
 892         u32 tunnel_type:3;
 893         u32 tunnel_end_prot:2;
 894         u32 tunnel_end_frag:1;
 895         u32 inner_prot:4;
 896         u32 payload_layer:3;
 897 };
 898
 899 enum i40e_rx_ptype_outer_ip {
 900         I40E_RX_PTYPE_OUTER_L2  = 0,
 901         I40E_RX_PTYPE_OUTER_IP  = 1
 902 };
 903
 904 enum i40e_rx_ptype_outer_ip_ver {
 905         I40E_RX_PTYPE_OUTER_NONE        = 0,
 906         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 907         I40E_RX_PTYPE_OUTER_IPV6        = 1
 908 };
 909
 910 enum i40e_rx_ptype_outer_fragmented {
 911         I40E_RX_PTYPE_NOT_FRAG  = 0,
 912         I40E_RX_PTYPE_FRAG      = 1
 913 };
 914
 915 enum i40e_rx_ptype_tunnel_type {
 916         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 917         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 918         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 919         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 920         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 921 };
 922
 923 enum i40e_rx_ptype_tunnel_end_prot {
 924         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 925         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 926         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 927 };
 928
 929 enum i40e_rx_ptype_inner_prot {
 930         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 931         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 932         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 933         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 934         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 935         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 936 };
 937
 938 enum i40e_rx_ptype_payload_layer {
 939         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 940         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 941         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 942         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 943 };
 944
 945 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 946 #define I40E_RX_PTYPE_SHIFT             56
 947
 948 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 949 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 950                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 951
 952 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 953 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 954                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 955
 956 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 957 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 958
 959 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 960 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 961
 962 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 963 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 964                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 965
 966 enum i40e_rx_desc_ext_status_bits {
 967         /* Note: These are predefined bit offsets */
 968         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 969         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 970         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 971         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 972         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 973         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 974         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 975 };
 976
 977 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 978 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 979
 980 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 981 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 982
 983 enum i40e_rx_desc_pe_status_bits {
 984         /* Note: These are predefined bit offsets */
 985         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 986         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 987         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 988         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 989         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 990         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 991         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 992         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 993         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 994 };
 995
 996 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 997 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 998
 999 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1000 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1001                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1002
1003 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1004 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1005                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1006
1007 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1008 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1009                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1010
1011 enum i40e_rx_prog_status_desc_status_bits {
1012         /* Note: These are predefined bit offsets */
1013         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1014         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1015 };
1016
1017 enum i40e_rx_prog_status_desc_prog_id_masks {
1018         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1019         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1020         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1021 };
1022
1023 enum i40e_rx_prog_status_desc_error_bits {
1024         /* Note: These are predefined bit offsets */
1025         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1026         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1027         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1028         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1029 };
1030
1031 #define I40E_TWO_BIT_MASK       0x3
1032 #define I40E_THREE_BIT_MASK     0x7
1033 #define I40E_FOUR_BIT_MASK      0xF
1034 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1035
1036 /* TX Descriptor */
1037 struct i40e_tx_desc {
1038         __le64 buffer_addr; /* Address of descriptor's data buf */
1039         __le64 cmd_type_offset_bsz;
1040 };
1041
1042 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1043 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1044
1045 enum i40e_tx_desc_dtype_value {
1046         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1047         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1048         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1049         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1050         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1051         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1052         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1053         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1054         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1055         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1056 };
1057
1058 #define I40E_TXD_QW1_CMD_SHIFT  4
1059 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1060
1061 enum i40e_tx_desc_cmd_bits {
1062         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1063         I40E_TX_DESC_CMD_RS                     = 0x0002,
1064         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1065         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1066         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1067         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1068         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1069         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1070         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1071         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1072         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1073         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1074         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1075         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1076         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1077         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1078         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1079         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1080 };
1081
1082 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1083 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1084                                          I40E_TXD_QW1_OFFSET_SHIFT)
1085
1086 enum i40e_tx_desc_length_fields {
1087         /* Note: These are predefined bit offsets */
1088         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1089         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1090         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1091 };
1092
1093 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1094 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1095 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1096 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1097
1098 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1099 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1100                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1101
1102 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1103 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1104
1105 /* Context descriptors */
1106 struct i40e_tx_context_desc {
1107         __le32 tunneling_params;
1108         __le16 l2tag2;
1109         __le16 rsvd;
1110         __le64 type_cmd_tso_mss;
1111 };
1112
1113 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1114 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1115
1116 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1117 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1118
1119 enum i40e_tx_ctx_desc_cmd_bits {
1120         I40E_TX_CTX_DESC_TSO            = 0x01,
1121         I40E_TX_CTX_DESC_TSYN           = 0x02,
1122         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1123         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1124         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1125         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1126         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1127         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1128         I40E_TX_CTX_DESC_SWPE           = 0x40
1129 };
1130
1131 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1132 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1133                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1134
1135 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1136 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1137                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1138
1139 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1140 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1141
1142 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1143 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1144                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1145
1146 enum i40e_tx_ctx_desc_eipt_offload {
1147         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1148         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1149         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1150         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1151 };
1152
1153 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1154 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1155                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1156
1157 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1158 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1159
1160 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1161 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1162
1163 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1164 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1165
1166 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1167
1168 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1169 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1170                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1171
1172 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1173 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1174                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1175
1176 #ifdef X722_SUPPORT
1177 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1178 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1179 #endif
1180 struct i40e_nop_desc {
1181         __le64 rsvd;
1182         __le64 dtype_cmd;
1183 };
1184
1185 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1186 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1187
1188 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1189 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1190
1191 enum i40e_tx_nop_desc_cmd_bits {
1192         /* Note: These are predefined bit offsets */
1193         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1194         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1195         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1196 };
1197
1198 struct i40e_filter_program_desc {
1199         __le32 qindex_flex_ptype_vsi;
1200         __le32 rsvd;
1201         __le32 dtype_cmd_cntindex;
1202         __le32 fd_id;
1203 };
1204 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1205 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1206                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1207 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1208 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1209                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1210 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1211 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1212                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1213
1214 /* Packet Classifier Types for filters */
1215 enum i40e_filter_pctype {
1216 #ifdef X722_SUPPORT
1217         /* Note: Values 0-28 are reserved for future use.
1218          * Value 29, 30, 32 are not supported on XL710 and X710.
1219          */
1220         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1221         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1222 #else
1223         /* Note: Values 0-30 are reserved for future use */
1224 #endif
1225         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1226 #ifdef X722_SUPPORT
1227         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1228 #else
1229         /* Note: Value 32 is reserved for future use */
1230 #endif
1231         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1232         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1233         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1234         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1235 #ifdef X722_SUPPORT
1236         /* Note: Values 37-38 are reserved for future use.
1237          * Value 39, 40, 42 are not supported on XL710 and X710.
1238          */
1239         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1240         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1241 #else
1242         /* Note: Values 37-40 are reserved for future use */
1243 #endif
1244         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1245 #ifdef X722_SUPPORT
1246         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1247 #endif
1248         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1249         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1250         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1251         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1252         /* Note: Value 47 is reserved for future use */
1253         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1254         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1255         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1256         /* Note: Values 51-62 are reserved for future use */
1257         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1258 };
1259
1260 enum i40e_filter_program_desc_dest {
1261         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1262         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1263         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1264 };
1265
1266 enum i40e_filter_program_desc_fd_status {
1267         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1268         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1269         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1270         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1271 };
1272
1273 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1274 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1275                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1276
1277 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1278 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1279
1280 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1281 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1282                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1283
1284 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1285 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1286
1287 enum i40e_filter_program_desc_pcmd {
1288         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1289         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1290 };
1291
1292 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1293 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1294
1295 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1296 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1297
1298 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1299                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1300 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1301                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1302 #ifdef X722_SUPPORT
1303
1304 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1305                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1306 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1307 #endif
1308
1309 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1310 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1311                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1312
1313 enum i40e_filter_type {
1314         I40E_FLOW_DIRECTOR_FLTR = 0,
1315         I40E_PE_QUAD_HASH_FLTR = 1,
1316         I40E_ETHERTYPE_FLTR,
1317         I40E_FCOE_CTX_FLTR,
1318         I40E_MAC_VLAN_FLTR,
1319         I40E_HASH_FLTR
1320 };
1321
1322 struct i40e_vsi_context {
1323         u16 seid;
1324         u16 uplink_seid;
1325         u16 vsi_number;
1326         u16 vsis_allocated;
1327         u16 vsis_unallocated;
1328         u16 flags;
1329         u8 pf_num;
1330         u8 vf_num;
1331         u8 connection_type;
1332         struct i40e_aqc_vsi_properties_data info;
1333 };
1334
1335 struct i40e_veb_context {
1336         u16 seid;
1337         u16 uplink_seid;
1338         u16 veb_number;
1339         u16 vebs_allocated;
1340         u16 vebs_unallocated;
1341         u16 flags;
1342         struct i40e_aqc_get_veb_parameters_completion info;
1343 };
1344
1345 /* Statistics collected by each port, VSI, VEB, and S-channel */
1346 struct i40e_eth_stats {
1347         u64 rx_bytes;                   /* gorc */
1348         u64 rx_unicast;                 /* uprc */
1349         u64 rx_multicast;               /* mprc */
1350         u64 rx_broadcast;               /* bprc */
1351         u64 rx_discards;                /* rdpc */
1352         u64 rx_unknown_protocol;        /* rupp */
1353         u64 tx_bytes;                   /* gotc */
1354         u64 tx_unicast;                 /* uptc */
1355         u64 tx_multicast;               /* mptc */
1356         u64 tx_broadcast;               /* bptc */
1357         u64 tx_discards;                /* tdpc */
1358         u64 tx_errors;                  /* tepc */
1359 };
1360
1361 /* Statistics collected per VEB per TC */
1362 struct i40e_veb_tc_stats {
1363         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1364         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1365         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1366         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1367 };
1368
1369 /* Statistics collected by the MAC */
1370 struct i40e_hw_port_stats {
1371         /* eth stats collected by the port */
1372         struct i40e_eth_stats eth;
1373
1374         /* additional port specific stats */
1375         u64 tx_dropped_link_down;       /* tdold */
1376         u64 crc_errors;                 /* crcerrs */
1377         u64 illegal_bytes;              /* illerrc */
1378         u64 error_bytes;                /* errbc */
1379         u64 mac_local_faults;           /* mlfc */
1380         u64 mac_remote_faults;          /* mrfc */
1381         u64 rx_length_errors;           /* rlec */
1382         u64 link_xon_rx;                /* lxonrxc */
1383         u64 link_xoff_rx;               /* lxoffrxc */
1384         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1385         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1386         u64 link_xon_tx;                /* lxontxc */
1387         u64 link_xoff_tx;               /* lxofftxc */
1388         u64 priority_xon_tx[8];         /* pxontxc[8] */
1389         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1390         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1391         u64 rx_size_64;                 /* prc64 */
1392         u64 rx_size_127;                /* prc127 */
1393         u64 rx_size_255;                /* prc255 */
1394         u64 rx_size_511;                /* prc511 */
1395         u64 rx_size_1023;               /* prc1023 */
1396         u64 rx_size_1522;               /* prc1522 */
1397         u64 rx_size_big;                /* prc9522 */
1398         u64 rx_undersize;               /* ruc */
1399         u64 rx_fragments;               /* rfc */
1400         u64 rx_oversize;                /* roc */
1401         u64 rx_jabber;                  /* rjc */
1402         u64 tx_size_64;                 /* ptc64 */
1403         u64 tx_size_127;                /* ptc127 */
1404         u64 tx_size_255;                /* ptc255 */
1405         u64 tx_size_511;                /* ptc511 */
1406         u64 tx_size_1023;               /* ptc1023 */
1407         u64 tx_size_1522;               /* ptc1522 */
1408         u64 tx_size_big;                /* ptc9522 */
1409         u64 mac_short_packet_dropped;   /* mspdc */
1410         u64 checksum_error;             /* xec */
1411         /* flow director stats */
1412         u64 fd_atr_match;
1413         u64 fd_sb_match;
1414         u64 fd_atr_tunnel_match;
1415         u32 fd_atr_status;
1416         u32 fd_sb_status;
1417         /* EEE LPI */
1418         u32 tx_lpi_status;
1419         u32 rx_lpi_status;
1420         u64 tx_lpi_count;               /* etlpic */
1421         u64 rx_lpi_count;               /* erlpic */
1422 };
1423
1424 /* Checksum and Shadow RAM pointers */
1425 #define I40E_SR_NVM_CONTROL_WORD                0x00
1426 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1427 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1428 #define I40E_SR_OPTION_ROM_PTR                  0x05
1429 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1430 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1431 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1432 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1433 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1434 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1435 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1436 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1437 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1438 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1439 #define I40E_SR_PBA_FLAGS                       0x15
1440 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1441 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1442 #define I40E_NVM_OEM_VER_OFF                    0x83
1443 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1444 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1445 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1446 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1447 #define I40E_SR_NVM_MAP_VERSION                 0x29
1448 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1449 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1450 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1451 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1452 #define I40E_SR_VPD_PTR                         0x2F
1453 #define I40E_SR_PXE_SETUP_PTR                   0x30
1454 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1455 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1456 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1457 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1458 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1459 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1460 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1461 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1462 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1463 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1464 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1465 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1466 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1467 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1468 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1469 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1470 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1471 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1472
1473 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1474 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1475 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1476 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1477 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1478
1479 /* Shadow RAM related */
1480 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1481 #define I40E_SR_BUF_ALIGNMENT           4096
1482 #define I40E_SR_WORDS_IN_1KB            512
1483 /* Checksum should be calculated such that after adding all the words,
1484  * including the checksum word itself, the sum should be 0xBABA.
1485  */
1486 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1487
1488 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1489
1490 enum i40e_switch_element_types {
1491         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1492         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1493         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1494         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1495         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1496         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1497         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1498         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1499         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1500 };
1501
1502 /* Supported EtherType filters */
1503 enum i40e_ether_type_index {
1504         I40E_ETHER_TYPE_1588            = 0,
1505         I40E_ETHER_TYPE_FIP             = 1,
1506         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1507         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1508         I40E_ETHER_TYPE_LLDP            = 4,
1509         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1510         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1511         I40E_ETHER_TYPE_QCN_CNM         = 7,
1512         I40E_ETHER_TYPE_8021X           = 8,
1513         I40E_ETHER_TYPE_ARP             = 9,
1514         I40E_ETHER_TYPE_RSV1            = 10,
1515         I40E_ETHER_TYPE_RSV2            = 11,
1516 };
1517
1518 /* Filter context base size is 1K */
1519 #define I40E_HASH_FILTER_BASE_SIZE      1024
1520 /* Supported Hash filter values */
1521 enum i40e_hash_filter_size {
1522         I40E_HASH_FILTER_SIZE_1K        = 0,
1523         I40E_HASH_FILTER_SIZE_2K        = 1,
1524         I40E_HASH_FILTER_SIZE_4K        = 2,
1525         I40E_HASH_FILTER_SIZE_8K        = 3,
1526         I40E_HASH_FILTER_SIZE_16K       = 4,
1527         I40E_HASH_FILTER_SIZE_32K       = 5,
1528         I40E_HASH_FILTER_SIZE_64K       = 6,
1529         I40E_HASH_FILTER_SIZE_128K      = 7,
1530         I40E_HASH_FILTER_SIZE_256K      = 8,
1531         I40E_HASH_FILTER_SIZE_512K      = 9,
1532         I40E_HASH_FILTER_SIZE_1M        = 10,
1533 };
1534
1535 /* DMA context base size is 0.5K */
1536 #define I40E_DMA_CNTX_BASE_SIZE         512
1537 /* Supported DMA context values */
1538 enum i40e_dma_cntx_size {
1539         I40E_DMA_CNTX_SIZE_512          = 0,
1540         I40E_DMA_CNTX_SIZE_1K           = 1,
1541         I40E_DMA_CNTX_SIZE_2K           = 2,
1542         I40E_DMA_CNTX_SIZE_4K           = 3,
1543         I40E_DMA_CNTX_SIZE_8K           = 4,
1544         I40E_DMA_CNTX_SIZE_16K          = 5,
1545         I40E_DMA_CNTX_SIZE_32K          = 6,
1546         I40E_DMA_CNTX_SIZE_64K          = 7,
1547         I40E_DMA_CNTX_SIZE_128K         = 8,
1548         I40E_DMA_CNTX_SIZE_256K         = 9,
1549 };
1550
1551 /* Supported Hash look up table (LUT) sizes */
1552 enum i40e_hash_lut_size {
1553         I40E_HASH_LUT_SIZE_128          = 0,
1554         I40E_HASH_LUT_SIZE_512          = 1,
1555 };
1556
1557 /* Structure to hold a per PF filter control settings */
1558 struct i40e_filter_control_settings {
1559         /* number of PE Quad Hash filter buckets */
1560         enum i40e_hash_filter_size pe_filt_num;
1561         /* number of PE Quad Hash contexts */
1562         enum i40e_dma_cntx_size pe_cntx_num;
1563         /* number of FCoE filter buckets */
1564         enum i40e_hash_filter_size fcoe_filt_num;
1565         /* number of FCoE DDP contexts */
1566         enum i40e_dma_cntx_size fcoe_cntx_num;
1567         /* size of the Hash LUT */
1568         enum i40e_hash_lut_size hash_lut_size;
1569         /* enable FDIR filters for PF and its VFs */
1570         bool enable_fdir;
1571         /* enable Ethertype filters for PF and its VFs */
1572         bool enable_ethtype;
1573         /* enable MAC/VLAN filters for PF and its VFs */
1574         bool enable_macvlan;
1575 };
1576
1577 /* Structure to hold device level control filter counts */
1578 struct i40e_control_filter_stats {
1579         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1580         u16 etype_used;       /* Used perfect EtherType filters */
1581         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1582         u16 etype_free;       /* Un-used perfect EtherType filters */
1583 };
1584
1585 enum i40e_reset_type {
1586         I40E_RESET_POR          = 0,
1587         I40E_RESET_CORER        = 1,
1588         I40E_RESET_GLOBR        = 2,
1589         I40E_RESET_EMPR         = 3,
1590 };
1591
1592 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1593 #define I40E_NVM_LLDP_CFG_PTR           0xD
1594 struct i40e_lldp_variables {
1595         u16 length;
1596         u16 adminstatus;
1597         u16 msgfasttx;
1598         u16 msgtxinterval;
1599         u16 txparams;
1600         u16 timers;
1601         u16 crc8;
1602 };
1603
1604 /* Offsets into Alternate Ram */
1605 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1606 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1607 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1608 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1609 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1610 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1611
1612 /* Alternate Ram Bandwidth Masks */
1613 #define I40E_ALT_BW_VALUE_MASK          0xFF
1614 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1615 #define I40E_ALT_BW_VALID_MASK          0x80000000
1616
1617 /* RSS Hash Table Size */
1618 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1619 #endif /* _I40E_TYPE_H_ */