drivers/net/i40e/base/i40e_type.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #ifndef _I40E_TYPE_H_
   6 #define _I40E_TYPE_H_
   7
   8 #include "i40e_status.h"
   9 #include "i40e_osdep.h"
  10 #include "i40e_register.h"
  11 #include "i40e_adminq.h"
  12 #include "i40e_hmc.h"
  13 #include "i40e_lan_hmc.h"
  14 #include "i40e_devids.h"
  15
  16 #define UNREFERENCED_XPARAMETER
  17 #define UNREFERENCED_1PARAMETER(_p) (_p);
  18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  22
  23 #ifndef LINUX_MACROS
  24 #ifndef BIT
  25 #define BIT(a) (1UL << (a))
  26 #endif /* BIT */
  27 #ifndef BIT_ULL
  28 #define BIT_ULL(a) (1ULL << (a))
  29 #endif /* BIT_ULL */
  30 #endif /* LINUX_MACROS */
  31
  32 #ifndef I40E_MASK
  33 /* I40E_MASK is a macro used on 32 bit registers */
  34 #define I40E_MASK(mask, shift) (mask << shift)
  35 #endif
  36
  37 #define I40E_MAX_PF                     16
  38 #define I40E_MAX_PF_VSI                 64
  39 #define I40E_MAX_PF_QP                  128
  40 #define I40E_MAX_VSI_QP                 16
  41 #define I40E_MAX_VF_VSI                 3
  42 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  43 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  44
  45 /* something less than 1 minute */
  46 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  47
  48 /* Max default timeout in ms, */
  49 #define I40E_MAX_NVM_TIMEOUT            18000
  50
  51 /* Max timeout in ms for the phy to respond */
  52 #define I40E_MAX_PHY_TIMEOUT            500
  53
  54 /* Check whether address is multicast. */
  55 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  56
  57 /* Check whether an address is broadcast. */
  58 #define I40E_IS_BROADCAST(address)      \
  59         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  60         (((u8 *)(address))[1] == ((u8)0xff)))
  61
  62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  63 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  64
  65 /* forward declaration */
  66 struct i40e_hw;
  67 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  68
  69 #ifndef ETH_ALEN
  70 #define ETH_ALEN        6
  71 #endif
  72 /* Data type manipulation macros. */
  73 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  74 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  75
  76 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  77 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  78
  79 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  80 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  81
  82 /* Number of Transmit Descriptors must be a multiple of 8. */
  83 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
  84 /* Number of Receive Descriptors must be a multiple of 32 if
  85  * the number of descriptors is greater than 32.
  86  */
  87 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
  88
  89 #define I40E_DESC_UNUSED(R)     \
  90         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  91         (R)->next_to_clean - (R)->next_to_use - 1)
  92
  93 /* bitfields for Tx queue mapping in QTX_CTL */
  94 #define I40E_QTX_CTL_VF_QUEUE   0x0
  95 #define I40E_QTX_CTL_VM_QUEUE   0x1
  96 #define I40E_QTX_CTL_PF_QUEUE   0x2
  97
  98 /* debug masks - set these bits in hw->debug_mask to control output */
  99 enum i40e_debug_mask {
 100         I40E_DEBUG_INIT                 = 0x00000001,
 101         I40E_DEBUG_RELEASE              = 0x00000002,
 102
 103         I40E_DEBUG_LINK                 = 0x00000010,
 104         I40E_DEBUG_PHY                  = 0x00000020,
 105         I40E_DEBUG_HMC                  = 0x00000040,
 106         I40E_DEBUG_NVM                  = 0x00000080,
 107         I40E_DEBUG_LAN                  = 0x00000100,
 108         I40E_DEBUG_FLOW                 = 0x00000200,
 109         I40E_DEBUG_DCB                  = 0x00000400,
 110         I40E_DEBUG_DIAG                 = 0x00000800,
 111         I40E_DEBUG_FD                   = 0x00001000,
 112         I40E_DEBUG_PACKAGE              = 0x00002000,
 113
 114         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 115         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 116         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 117         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 118         I40E_DEBUG_AQ                   = 0x0F000000,
 119
 120         I40E_DEBUG_USER                 = 0xF0000000,
 121
 122         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 123 };
 124
 125 /* PCI Bus Info */
 126 #define I40E_PCI_LINK_STATUS            0xB2
 127 #define I40E_PCI_LINK_WIDTH             0x3F0
 128 #define I40E_PCI_LINK_WIDTH_1           0x10
 129 #define I40E_PCI_LINK_WIDTH_2           0x20
 130 #define I40E_PCI_LINK_WIDTH_4           0x40
 131 #define I40E_PCI_LINK_WIDTH_8           0x80
 132 #define I40E_PCI_LINK_SPEED             0xF
 133 #define I40E_PCI_LINK_SPEED_2500        0x1
 134 #define I40E_PCI_LINK_SPEED_5000        0x2
 135 #define I40E_PCI_LINK_SPEED_8000        0x3
 136
 137 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 138                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 139 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 140                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 141 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 142                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 143
 144 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 145                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 146 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 147                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 148 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 149                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 150 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 151                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 152 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 153                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 154
 155 #define I40E_PHY_COM_REG_PAGE                   0x1E
 156 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 157 #define I40E_PHY_LED_MANUAL_ON                  0x100
 158 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 159 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 160 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 161
 162 /* Memory types */
 163 enum i40e_memset_type {
 164         I40E_NONDMA_MEM = 0,
 165         I40E_DMA_MEM
 166 };
 167
 168 /* Memcpy types */
 169 enum i40e_memcpy_type {
 170         I40E_NONDMA_TO_NONDMA = 0,
 171         I40E_NONDMA_TO_DMA,
 172         I40E_DMA_TO_DMA,
 173         I40E_DMA_TO_NONDMA
 174 };
 175
 176 /* These are structs for managing the hardware information and the operations.
 177  * The structures of function pointers are filled out at init time when we
 178  * know for sure exactly which hardware we're working with.  This gives us the
 179  * flexibility of using the same main driver code but adapting to slightly
 180  * different hardware needs as new parts are developed.  For this architecture,
 181  * the Firmware and AdminQ are intended to insulate the driver from most of the
 182  * future changes, but these structures will also do part of the job.
 183  */
 184 enum i40e_mac_type {
 185         I40E_MAC_UNKNOWN = 0,
 186         I40E_MAC_XL710,
 187         I40E_MAC_VF,
 188         I40E_MAC_X722,
 189         I40E_MAC_X722_VF,
 190         I40E_MAC_GENERIC,
 191 };
 192
 193 enum i40e_media_type {
 194         I40E_MEDIA_TYPE_UNKNOWN = 0,
 195         I40E_MEDIA_TYPE_FIBER,
 196         I40E_MEDIA_TYPE_BASET,
 197         I40E_MEDIA_TYPE_BACKPLANE,
 198         I40E_MEDIA_TYPE_CX4,
 199         I40E_MEDIA_TYPE_DA,
 200         I40E_MEDIA_TYPE_VIRTUAL
 201 };
 202
 203 enum i40e_fc_mode {
 204         I40E_FC_NONE = 0,
 205         I40E_FC_RX_PAUSE,
 206         I40E_FC_TX_PAUSE,
 207         I40E_FC_FULL,
 208         I40E_FC_PFC,
 209         I40E_FC_DEFAULT
 210 };
 211
 212 enum i40e_set_fc_aq_failures {
 213         I40E_SET_FC_AQ_FAIL_NONE = 0,
 214         I40E_SET_FC_AQ_FAIL_GET = 1,
 215         I40E_SET_FC_AQ_FAIL_SET = 2,
 216         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 217         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 218 };
 219
 220 enum i40e_vsi_type {
 221         I40E_VSI_MAIN   = 0,
 222         I40E_VSI_VMDQ1  = 1,
 223         I40E_VSI_VMDQ2  = 2,
 224         I40E_VSI_CTRL   = 3,
 225         I40E_VSI_FCOE   = 4,
 226         I40E_VSI_MIRROR = 5,
 227         I40E_VSI_SRIOV  = 6,
 228         I40E_VSI_FDIR   = 7,
 229         I40E_VSI_TYPE_UNKNOWN
 230 };
 231
 232 enum i40e_queue_type {
 233         I40E_QUEUE_TYPE_RX = 0,
 234         I40E_QUEUE_TYPE_TX,
 235         I40E_QUEUE_TYPE_PE_CEQ,
 236         I40E_QUEUE_TYPE_UNKNOWN
 237 };
 238
 239 struct i40e_link_status {
 240         enum i40e_aq_phy_type phy_type;
 241         enum i40e_aq_link_speed link_speed;
 242         u8 link_info;
 243         u8 an_info;
 244         u8 req_fec_info;
 245         u8 fec_info;
 246         u8 ext_info;
 247         u8 loopback;
 248         /* is Link Status Event notification to SW enabled */
 249         bool lse_enable;
 250         u16 max_frame_size;
 251         bool crc_enable;
 252         u8 pacing;
 253         u8 requested_speeds;
 254         u8 module_type[3];
 255         /* 1st byte: module identifier */
 256 #define I40E_MODULE_TYPE_SFP            0x03
 257 #define I40E_MODULE_TYPE_QSFP           0x0D
 258         /* 2nd byte: ethernet compliance codes for 10/40G */
 259 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 260 #define I40E_MODULE_TYPE_40G_LR4        0x02
 261 #define I40E_MODULE_TYPE_40G_SR4        0x04
 262 #define I40E_MODULE_TYPE_40G_CR4        0x08
 263 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 264 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 265 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 266 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 267         /* 3rd byte: ethernet compliance codes for 1G */
 268 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 269 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 270 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 271 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 272 };
 273
 274 struct i40e_phy_info {
 275         struct i40e_link_status link_info;
 276         struct i40e_link_status link_info_old;
 277         bool get_link_info;
 278         enum i40e_media_type media_type;
 279         /* all the phy types the NVM is capable of */
 280         u64 phy_types;
 281 };
 282
 283 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 284 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 285 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 286 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 287 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 288 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 289 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 290 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 291 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 292 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 293 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 294 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 295 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 296 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 297 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 298 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 299 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 300 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 301 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 302 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 303 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 304 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 305 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 306 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 307 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 308 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 309 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 310                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 311 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 312 /*
 313  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 314  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 315  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 316  * a shift is needed to adjust for this with values larger than 31. The
 317  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 318  */
 319 #define I40E_PHY_TYPE_OFFSET 1
 320 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 321                                              I40E_PHY_TYPE_OFFSET)
 322 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 323                                              I40E_PHY_TYPE_OFFSET)
 324 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 325                                              I40E_PHY_TYPE_OFFSET)
 326 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 327                                              I40E_PHY_TYPE_OFFSET)
 328 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 329                                              I40E_PHY_TYPE_OFFSET)
 330 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 331                                              I40E_PHY_TYPE_OFFSET)
 332 #define I40E_HW_CAP_MAX_GPIO                    30
 333 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 334 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 335
 336 enum i40e_acpi_programming_method {
 337         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 338         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 339 };
 340
 341 #define I40E_WOL_SUPPORT_MASK                   0x1
 342 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 343 #define I40E_PROXY_SUPPORT_MASK                 0x4
 344
 345 /* Capabilities of a PF or a VF or the whole device */
 346 struct i40e_hw_capabilities {
 347         u32  switch_mode;
 348 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 349 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 350 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 351
 352         /* Cloud filter modes:
 353          * Mode1: Filter on L4 port only
 354          * Mode2: Filter for non-tunneled traffic
 355          * Mode3: Filter for tunnel traffic
 356          */
 357 #define I40E_CLOUD_FILTER_MODE1 0x6
 358 #define I40E_CLOUD_FILTER_MODE2 0x7
 359 #define I40E_CLOUD_FILTER_MODE3 0x8
 360 #define I40E_SWITCH_MODE_MASK   0xF
 361
 362         u32  management_mode;
 363         u32  mng_protocols_over_mctp;
 364 #define I40E_MNG_PROTOCOL_PLDM          0x2
 365 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 366 #define I40E_MNG_PROTOCOL_NCSI          0x8
 367         u32  npar_enable;
 368         u32  os2bmc;
 369         u32  valid_functions;
 370         bool sr_iov_1_1;
 371         bool vmdq;
 372         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 373         bool evb_802_1_qbh; /* Bridge Port Extension */
 374         bool dcb;
 375         bool fcoe;
 376         bool iscsi; /* Indicates iSCSI enabled */
 377         bool flex10_enable;
 378         bool flex10_capable;
 379         u32  flex10_mode;
 380 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 381 #define I40E_FLEX10_MODE_DCC            0x1
 382 #define I40E_FLEX10_MODE_DCI            0x2
 383
 384         u32 flex10_status;
 385 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 386 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 387
 388         bool sec_rev_disabled;
 389         bool update_disabled;
 390 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 391 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 392
 393         bool mgmt_cem;
 394         bool ieee_1588;
 395         bool iwarp;
 396         bool fd;
 397         u32 fd_filters_guaranteed;
 398         u32 fd_filters_best_effort;
 399         bool rss;
 400         u32 rss_table_size;
 401         u32 rss_table_entry_width;
 402         bool led[I40E_HW_CAP_MAX_GPIO];
 403         bool sdp[I40E_HW_CAP_MAX_GPIO];
 404         u32 nvm_image_type;
 405         u32 num_flow_director_filters;
 406         u32 num_vfs;
 407         u32 vf_base_id;
 408         u32 num_vsis;
 409         u32 num_rx_qp;
 410         u32 num_tx_qp;
 411         u32 base_queue;
 412         u32 num_msix_vectors;
 413         u32 num_msix_vectors_vf;
 414         u32 led_pin_num;
 415         u32 sdp_pin_num;
 416         u32 mdio_port_num;
 417         u32 mdio_port_mode;
 418         u8 rx_buf_chain_len;
 419         u32 enabled_tcmap;
 420         u32 maxtc;
 421         u64 wr_csr_prot;
 422         bool apm_wol_support;
 423         enum i40e_acpi_programming_method acpi_prog_method;
 424         bool proxy_support;
 425 };
 426
 427 struct i40e_mac_info {
 428         enum i40e_mac_type type;
 429         u8 addr[ETH_ALEN];
 430         u8 perm_addr[ETH_ALEN];
 431         u8 san_addr[ETH_ALEN];
 432         u8 port_addr[ETH_ALEN];
 433         u16 max_fcoeq;
 434 };
 435
 436 enum i40e_aq_resources_ids {
 437         I40E_NVM_RESOURCE_ID = 1
 438 };
 439
 440 enum i40e_aq_resource_access_type {
 441         I40E_RESOURCE_READ = 1,
 442         I40E_RESOURCE_WRITE
 443 };
 444
 445 struct i40e_nvm_info {
 446         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 447         u32 timeout;              /* [ms] */
 448         u16 sr_size;              /* Shadow RAM size in words */
 449         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 450         u16 version;              /* NVM package version */
 451         u32 eetrack;              /* NVM data version */
 452         u32 oem_ver;              /* OEM version info */
 453 };
 454
 455 /* definitions used in NVM update support */
 456
 457 enum i40e_nvmupd_cmd {
 458         I40E_NVMUPD_INVALID,
 459         I40E_NVMUPD_READ_CON,
 460         I40E_NVMUPD_READ_SNT,
 461         I40E_NVMUPD_READ_LCB,
 462         I40E_NVMUPD_READ_SA,
 463         I40E_NVMUPD_WRITE_ERA,
 464         I40E_NVMUPD_WRITE_CON,
 465         I40E_NVMUPD_WRITE_SNT,
 466         I40E_NVMUPD_WRITE_LCB,
 467         I40E_NVMUPD_WRITE_SA,
 468         I40E_NVMUPD_CSUM_CON,
 469         I40E_NVMUPD_CSUM_SA,
 470         I40E_NVMUPD_CSUM_LCB,
 471         I40E_NVMUPD_STATUS,
 472         I40E_NVMUPD_EXEC_AQ,
 473         I40E_NVMUPD_GET_AQ_RESULT,
 474         I40E_NVMUPD_GET_AQ_EVENT,
 475 };
 476
 477 enum i40e_nvmupd_state {
 478         I40E_NVMUPD_STATE_INIT,
 479         I40E_NVMUPD_STATE_READING,
 480         I40E_NVMUPD_STATE_WRITING,
 481         I40E_NVMUPD_STATE_INIT_WAIT,
 482         I40E_NVMUPD_STATE_WRITE_WAIT,
 483         I40E_NVMUPD_STATE_ERROR
 484 };
 485
 486 /* nvm_access definition and its masks/shifts need to be accessible to
 487  * application, core driver, and shared code.  Where is the right file?
 488  */
 489 #define I40E_NVM_READ   0xB
 490 #define I40E_NVM_WRITE  0xC
 491
 492 #define I40E_NVM_MOD_PNT_MASK 0xFF
 493
 494 #define I40E_NVM_TRANS_SHIFT                    8
 495 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 496 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 497 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 498                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 499 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 500 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 501 #define I40E_NVM_CON                            0x0
 502 #define I40E_NVM_SNT                            0x1
 503 #define I40E_NVM_LCB                            0x2
 504 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 505 #define I40E_NVM_ERA                            0x4
 506 #define I40E_NVM_CSUM                           0x8
 507 #define I40E_NVM_AQE                            0xe
 508 #define I40E_NVM_EXEC                           0xf
 509
 510 #define I40E_NVM_ADAPT_SHIFT    16
 511 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 512
 513 #define I40E_NVMUPD_MAX_DATA    4096
 514 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 515
 516 struct i40e_nvm_access {
 517         u32 command;
 518         u32 config;
 519         u32 offset;     /* in bytes */
 520         u32 data_size;  /* in bytes */
 521         u8 data[1];
 522 };
 523
 524 /* (Q)SFP module access definitions */
 525 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 526 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 527 #define I40E_MODULE_TYPE_ADDR           0x00
 528 #define I40E_MODULE_REVISION_ADDR       0x01
 529 #define I40E_MODULE_SFF_8472_COMP       0x5E
 530 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 531 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 532 #define I40E_MODULE_SFF_DIAG_CAPAB      0x40
 533 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 534 #define I40E_MODULE_TYPE_QSFP28         0x11
 535 #define I40E_MODULE_QSFP_MAX_LEN        640
 536
 537 /* PCI bus types */
 538 enum i40e_bus_type {
 539         i40e_bus_type_unknown = 0,
 540         i40e_bus_type_pci,
 541         i40e_bus_type_pcix,
 542         i40e_bus_type_pci_express,
 543         i40e_bus_type_reserved
 544 };
 545
 546 /* PCI bus speeds */
 547 enum i40e_bus_speed {
 548         i40e_bus_speed_unknown  = 0,
 549         i40e_bus_speed_33       = 33,
 550         i40e_bus_speed_66       = 66,
 551         i40e_bus_speed_100      = 100,
 552         i40e_bus_speed_120      = 120,
 553         i40e_bus_speed_133      = 133,
 554         i40e_bus_speed_2500     = 2500,
 555         i40e_bus_speed_5000     = 5000,
 556         i40e_bus_speed_8000     = 8000,
 557         i40e_bus_speed_reserved
 558 };
 559
 560 /* PCI bus widths */
 561 enum i40e_bus_width {
 562         i40e_bus_width_unknown  = 0,
 563         i40e_bus_width_pcie_x1  = 1,
 564         i40e_bus_width_pcie_x2  = 2,
 565         i40e_bus_width_pcie_x4  = 4,
 566         i40e_bus_width_pcie_x8  = 8,
 567         i40e_bus_width_32       = 32,
 568         i40e_bus_width_64       = 64,
 569         i40e_bus_width_reserved
 570 };
 571
 572 /* Bus parameters */
 573 struct i40e_bus_info {
 574         enum i40e_bus_speed speed;
 575         enum i40e_bus_width width;
 576         enum i40e_bus_type type;
 577
 578         u16 func;
 579         u16 device;
 580         u16 lan_id;
 581         u16 bus_id;
 582 };
 583
 584 /* Flow control (FC) parameters */
 585 struct i40e_fc_info {
 586         enum i40e_fc_mode current_mode; /* FC mode in effect */
 587         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 588 };
 589
 590 #define I40E_MAX_TRAFFIC_CLASS          8
 591 #define I40E_MAX_USER_PRIORITY          8
 592 #define I40E_DCBX_MAX_APPS              32
 593 #define I40E_LLDPDU_SIZE                1500
 594 #define I40E_TLV_STATUS_OPER            0x1
 595 #define I40E_TLV_STATUS_SYNC            0x2
 596 #define I40E_TLV_STATUS_ERR             0x4
 597 #define I40E_CEE_OPER_MAX_APPS          3
 598 #define I40E_APP_PROTOID_FCOE           0x8906
 599 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 600 #define I40E_APP_PROTOID_FIP            0x8914
 601 #define I40E_APP_SEL_ETHTYPE            0x1
 602 #define I40E_APP_SEL_TCPIP              0x2
 603 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 604 #define I40E_CEE_APP_SEL_TCPIP          0x1
 605
 606 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 607 struct i40e_dcb_ets_config {
 608         u8 willing;
 609         u8 cbs;
 610         u8 maxtcs;
 611         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 612         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 613         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 614 };
 615
 616 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 617 struct i40e_dcb_pfc_config {
 618         u8 willing;
 619         u8 mbc;
 620         u8 pfccap;
 621         u8 pfcenable;
 622 };
 623
 624 /* CEE or IEEE 802.1Qaz Application Priority data */
 625 struct i40e_dcb_app_priority_table {
 626         u8  priority;
 627         u8  selector;
 628         u16 protocolid;
 629 };
 630
 631 struct i40e_dcbx_config {
 632         u8  dcbx_mode;
 633 #define I40E_DCBX_MODE_CEE      0x1
 634 #define I40E_DCBX_MODE_IEEE     0x2
 635         u8  app_mode;
 636 #define I40E_DCBX_APPS_NON_WILLING      0x1
 637         u32 numapps;
 638         u32 tlv_status; /* CEE mode TLV status */
 639         struct i40e_dcb_ets_config etscfg;
 640         struct i40e_dcb_ets_config etsrec;
 641         struct i40e_dcb_pfc_config pfc;
 642         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 643 };
 644
 645 /* Port hardware description */
 646 struct i40e_hw {
 647         u8 *hw_addr;
 648         void *back;
 649
 650         /* subsystem structs */
 651         struct i40e_phy_info phy;
 652         struct i40e_mac_info mac;
 653         struct i40e_bus_info bus;
 654         struct i40e_nvm_info nvm;
 655         struct i40e_fc_info fc;
 656
 657         /* pci info */
 658         u16 device_id;
 659         u16 vendor_id;
 660         u16 subsystem_device_id;
 661         u16 subsystem_vendor_id;
 662         u8 revision_id;
 663         u8 port;
 664         bool adapter_stopped;
 665
 666         /* capabilities for entire device and PCI func */
 667         struct i40e_hw_capabilities dev_caps;
 668         struct i40e_hw_capabilities func_caps;
 669
 670         /* Flow Director shared filter space */
 671         u16 fdir_shared_filter_count;
 672
 673         /* device profile info */
 674         u8  pf_id;
 675         u16 main_vsi_seid;
 676
 677         /* for multi-function MACs */
 678         u16 partition_id;
 679         u16 num_partitions;
 680         u16 num_ports;
 681
 682         /* Closest numa node to the device */
 683         u16 numa_node;
 684
 685         /* Admin Queue info */
 686         struct i40e_adminq_info aq;
 687
 688         /* state of nvm update process */
 689         enum i40e_nvmupd_state nvmupd_state;
 690         struct i40e_aq_desc nvm_wb_desc;
 691         struct i40e_aq_desc nvm_aq_event_desc;
 692         struct i40e_virt_mem nvm_buff;
 693         bool nvm_release_on_done;
 694         u16 nvm_wait_opcode;
 695
 696         /* HMC info */
 697         struct i40e_hmc_info hmc; /* HMC info struct */
 698
 699         /* LLDP/DCBX Status */
 700         u16 dcbx_status;
 701
 702         /* DCBX info */
 703         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 704         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 705         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 706
 707         /* WoL and proxy support */
 708         u16 num_wol_proxy_filters;
 709         u16 wol_proxy_vsi_seid;
 710
 711 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 712 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 713 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 714 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 715         u64 flags;
 716
 717         /* Used in set switch config AQ command */
 718         u16 switch_tag;
 719         u16 first_tag;
 720         u16 second_tag;
 721
 722         /* debug mask */
 723         u32 debug_mask;
 724         char err_str[16];
 725 };
 726
 727 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 728 {
 729         return (hw->mac.type == I40E_MAC_VF ||
 730                 hw->mac.type == I40E_MAC_X722_VF);
 731 }
 732
 733 struct i40e_driver_version {
 734         u8 major_version;
 735         u8 minor_version;
 736         u8 build_version;
 737         u8 subbuild_version;
 738         u8 driver_string[32];
 739 };
 740
 741 /* RX Descriptors */
 742 union i40e_16byte_rx_desc {
 743         struct {
 744                 __le64 pkt_addr; /* Packet buffer address */
 745                 __le64 hdr_addr; /* Header buffer address */
 746         } read;
 747         struct {
 748                 struct {
 749                         struct {
 750                                 union {
 751                                         __le16 mirroring_status;
 752                                         __le16 fcoe_ctx_id;
 753                                 } mirr_fcoe;
 754                                 __le16 l2tag1;
 755                         } lo_dword;
 756                         union {
 757                                 __le32 rss; /* RSS Hash */
 758                                 __le32 fd_id; /* Flow director filter id */
 759                                 __le32 fcoe_param; /* FCoE DDP Context id */
 760                         } hi_dword;
 761                 } qword0;
 762                 struct {
 763                         /* ext status/error/pktype/length */
 764                         __le64 status_error_len;
 765                 } qword1;
 766         } wb;  /* writeback */
 767 };
 768
 769 union i40e_32byte_rx_desc {
 770         struct {
 771                 __le64  pkt_addr; /* Packet buffer address */
 772                 __le64  hdr_addr; /* Header buffer address */
 773                         /* bit 0 of hdr_buffer_addr is DD bit */
 774                 __le64  rsvd1;
 775                 __le64  rsvd2;
 776         } read;
 777         struct {
 778                 struct {
 779                         struct {
 780                                 union {
 781                                         __le16 mirroring_status;
 782                                         __le16 fcoe_ctx_id;
 783                                 } mirr_fcoe;
 784                                 __le16 l2tag1;
 785                         } lo_dword;
 786                         union {
 787                                 __le32 rss; /* RSS Hash */
 788                                 __le32 fcoe_param; /* FCoE DDP Context id */
 789                                 /* Flow director filter id in case of
 790                                  * Programming status desc WB
 791                                  */
 792                                 __le32 fd_id;
 793                         } hi_dword;
 794                 } qword0;
 795                 struct {
 796                         /* status/error/pktype/length */
 797                         __le64 status_error_len;
 798                 } qword1;
 799                 struct {
 800                         __le16 ext_status; /* extended status */
 801                         __le16 rsvd;
 802                         __le16 l2tag2_1;
 803                         __le16 l2tag2_2;
 804                 } qword2;
 805                 struct {
 806                         union {
 807                                 __le32 flex_bytes_lo;
 808                                 __le32 pe_status;
 809                         } lo_dword;
 810                         union {
 811                                 __le32 flex_bytes_hi;
 812                                 __le32 fd_id;
 813                         } hi_dword;
 814                 } qword3;
 815         } wb;  /* writeback */
 816 };
 817
 818 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 819 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 820                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 821 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 822 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 823                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 824
 825 enum i40e_rx_desc_status_bits {
 826         /* Note: These are predefined bit offsets */
 827         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 828         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 829         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 830         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 831         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 832         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 833         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 834         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 835
 836         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 837         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 838         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 839         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 840         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 841         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 842         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 843         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 844 };
 845
 846 #define I40E_RXD_QW1_STATUS_SHIFT       0
 847 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 848                                          I40E_RXD_QW1_STATUS_SHIFT)
 849
 850 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 851 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 852                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 853
 854 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 855 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 856
 857 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 858 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 859                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 860
 861 enum i40e_rx_desc_fltstat_values {
 862         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 863         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 864         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 865         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 866 };
 867
 868 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 869 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 870 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 871 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 872
 873 #define I40E_RXD_QW1_ERROR_SHIFT        19
 874 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 875
 876 enum i40e_rx_desc_error_bits {
 877         /* Note: These are predefined bit offsets */
 878         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 879         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 880         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 881         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 882         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 883         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 884         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 885         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 886         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 887 };
 888
 889 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 890         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 891         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 892         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 893         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 894         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 895 };
 896
 897 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 898 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 899
 900 /* Packet type non-ip values */
 901 enum i40e_rx_l2_ptype {
 902         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 903         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 904         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 905         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 906         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 907         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 908         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 909         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 910         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 911         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 912         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 913         I40E_RX_PTYPE_L2_ARP                            = 11,
 914         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 915         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 916         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 917         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 918         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 919         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 920         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 921         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 922         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 923         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 924         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 925         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 926         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 927         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 928 };
 929
 930 struct i40e_rx_ptype_decoded {
 931         u32 ptype:8;
 932         u32 known:1;
 933         u32 outer_ip:1;
 934         u32 outer_ip_ver:1;
 935         u32 outer_frag:1;
 936         u32 tunnel_type:3;
 937         u32 tunnel_end_prot:2;
 938         u32 tunnel_end_frag:1;
 939         u32 inner_prot:4;
 940         u32 payload_layer:3;
 941 };
 942
 943 enum i40e_rx_ptype_outer_ip {
 944         I40E_RX_PTYPE_OUTER_L2  = 0,
 945         I40E_RX_PTYPE_OUTER_IP  = 1
 946 };
 947
 948 enum i40e_rx_ptype_outer_ip_ver {
 949         I40E_RX_PTYPE_OUTER_NONE        = 0,
 950         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 951         I40E_RX_PTYPE_OUTER_IPV6        = 1
 952 };
 953
 954 enum i40e_rx_ptype_outer_fragmented {
 955         I40E_RX_PTYPE_NOT_FRAG  = 0,
 956         I40E_RX_PTYPE_FRAG      = 1
 957 };
 958
 959 enum i40e_rx_ptype_tunnel_type {
 960         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 961         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 962         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 963         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 964         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 965 };
 966
 967 enum i40e_rx_ptype_tunnel_end_prot {
 968         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 969         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 970         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 971 };
 972
 973 enum i40e_rx_ptype_inner_prot {
 974         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 975         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 976         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 977         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 978         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 979         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 980 };
 981
 982 enum i40e_rx_ptype_payload_layer {
 983         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 984         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 985         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 986         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 987 };
 988
 989 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 990 #define I40E_RX_PTYPE_SHIFT             56
 991
 992 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 993 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 994                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 995
 996 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 997 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 998                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 999
1000 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1001 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1002
1003 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1004 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1005
1006 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1007 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1008                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1009
1010 enum i40e_rx_desc_ext_status_bits {
1011         /* Note: These are predefined bit offsets */
1012         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1013         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1014         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1015         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1016         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1017         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1018         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1019 };
1020
1021 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1022 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1023
1024 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1025 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1026
1027 enum i40e_rx_desc_pe_status_bits {
1028         /* Note: These are predefined bit offsets */
1029         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1030         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1031         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1032         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1033         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1034         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1035         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1036         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1037         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1038 };
1039
1040 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1041 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1042
1043 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1044 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1045                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1046
1047 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1048 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1049                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1050
1051 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1052 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1053                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1054
1055 enum i40e_rx_prog_status_desc_status_bits {
1056         /* Note: These are predefined bit offsets */
1057         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1058         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1059 };
1060
1061 enum i40e_rx_prog_status_desc_prog_id_masks {
1062         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1063         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1064         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1065 };
1066
1067 enum i40e_rx_prog_status_desc_error_bits {
1068         /* Note: These are predefined bit offsets */
1069         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1070         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1071         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1072         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1073 };
1074
1075 #define I40E_TWO_BIT_MASK       0x3
1076 #define I40E_THREE_BIT_MASK     0x7
1077 #define I40E_FOUR_BIT_MASK      0xF
1078 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1079
1080 /* TX Descriptor */
1081 struct i40e_tx_desc {
1082         __le64 buffer_addr; /* Address of descriptor's data buf */
1083         __le64 cmd_type_offset_bsz;
1084 };
1085
1086 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1087 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1088
1089 enum i40e_tx_desc_dtype_value {
1090         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1091         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1092         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1093         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1094         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1095         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1096         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1097         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1098         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1099         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1100 };
1101
1102 #define I40E_TXD_QW1_CMD_SHIFT  4
1103 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1104
1105 enum i40e_tx_desc_cmd_bits {
1106         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1107         I40E_TX_DESC_CMD_RS                     = 0x0002,
1108         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1109         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1110         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1111         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1112         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1113         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1114         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1115         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1116         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1117         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1118         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1119         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1120         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1121         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1122         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1123         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1124 };
1125
1126 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1127 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1128                                          I40E_TXD_QW1_OFFSET_SHIFT)
1129
1130 enum i40e_tx_desc_length_fields {
1131         /* Note: These are predefined bit offsets */
1132         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1133         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1134         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1135 };
1136
1137 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1138 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1139 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1140 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1141
1142 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1143 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1144                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1145
1146 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1147 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1148
1149 /* Context descriptors */
1150 struct i40e_tx_context_desc {
1151         __le32 tunneling_params;
1152         __le16 l2tag2;
1153         __le16 rsvd;
1154         __le64 type_cmd_tso_mss;
1155 };
1156
1157 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1158 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1159
1160 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1161 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1162
1163 enum i40e_tx_ctx_desc_cmd_bits {
1164         I40E_TX_CTX_DESC_TSO            = 0x01,
1165         I40E_TX_CTX_DESC_TSYN           = 0x02,
1166         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1167         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1168         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1169         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1170         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1171         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1172         I40E_TX_CTX_DESC_SWPE           = 0x40
1173 };
1174
1175 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1176 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1177                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1178
1179 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1180 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1181                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1182
1183 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1184 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1185
1186 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1187 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1188                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1189
1190 enum i40e_tx_ctx_desc_eipt_offload {
1191         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1192         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1193         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1194         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1195 };
1196
1197 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1198 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1199                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1200
1201 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1202 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1203
1204 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1205 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1206
1207 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1208 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1209
1210 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1211
1212 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1213 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1214                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1215
1216 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1217 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1218                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1219
1220 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1221 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1222 struct i40e_nop_desc {
1223         __le64 rsvd;
1224         __le64 dtype_cmd;
1225 };
1226
1227 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1228 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1229
1230 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1231 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1232
1233 enum i40e_tx_nop_desc_cmd_bits {
1234         /* Note: These are predefined bit offsets */
1235         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1236         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1237         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1238 };
1239
1240 struct i40e_filter_program_desc {
1241         __le32 qindex_flex_ptype_vsi;
1242         __le32 rsvd;
1243         __le32 dtype_cmd_cntindex;
1244         __le32 fd_id;
1245 };
1246 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1247 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1248                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1249 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1250 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1251                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1252 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1253 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1254                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1255
1256 /* Packet Classifier Types for filters */
1257 enum i40e_filter_pctype {
1258         /* Note: Values 0-28 are reserved for future use.
1259          * Value 29, 30, 32 are not supported on XL710 and X710.
1260          */
1261         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1262         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1263         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1264         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1265         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1266         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1267         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1268         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1269         /* Note: Values 37-38 are reserved for future use.
1270          * Value 39, 40, 42 are not supported on XL710 and X710.
1271          */
1272         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1273         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1274         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1275         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1276         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1277         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1278         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1279         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1280         /* Note: Value 47 is reserved for future use */
1281         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1282         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1283         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1284         /* Note: Values 51-62 are reserved for future use */
1285         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1286 };
1287
1288 enum i40e_filter_program_desc_dest {
1289         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1290         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1291         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1292 };
1293
1294 enum i40e_filter_program_desc_fd_status {
1295         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1296         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1297         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1298         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1299 };
1300
1301 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1302 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1303                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1304
1305 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1306 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1307
1308 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1309 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1310                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1311
1312 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1313 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1314
1315 enum i40e_filter_program_desc_pcmd {
1316         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1317         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1318 };
1319
1320 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1321 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1322
1323 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1324 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1325
1326 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1327                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1328 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1329                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1330
1331 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1332                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1333 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1334
1335 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1336 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1337                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1338
1339 enum i40e_filter_type {
1340         I40E_FLOW_DIRECTOR_FLTR = 0,
1341         I40E_PE_QUAD_HASH_FLTR = 1,
1342         I40E_ETHERTYPE_FLTR,
1343         I40E_FCOE_CTX_FLTR,
1344         I40E_MAC_VLAN_FLTR,
1345         I40E_HASH_FLTR
1346 };
1347
1348 struct i40e_vsi_context {
1349         u16 seid;
1350         u16 uplink_seid;
1351         u16 vsi_number;
1352         u16 vsis_allocated;
1353         u16 vsis_unallocated;
1354         u16 flags;
1355         u8 pf_num;
1356         u8 vf_num;
1357         u8 connection_type;
1358         struct i40e_aqc_vsi_properties_data info;
1359 };
1360
1361 struct i40e_veb_context {
1362         u16 seid;
1363         u16 uplink_seid;
1364         u16 veb_number;
1365         u16 vebs_allocated;
1366         u16 vebs_unallocated;
1367         u16 flags;
1368         struct i40e_aqc_get_veb_parameters_completion info;
1369 };
1370
1371 /* Statistics collected by each port, VSI, VEB, and S-channel */
1372 struct i40e_eth_stats {
1373         u64 rx_bytes;                   /* gorc */
1374         u64 rx_unicast;                 /* uprc */
1375         u64 rx_multicast;               /* mprc */
1376         u64 rx_broadcast;               /* bprc */
1377         u64 rx_discards;                /* rdpc */
1378         u64 rx_unknown_protocol;        /* rupp */
1379         u64 tx_bytes;                   /* gotc */
1380         u64 tx_unicast;                 /* uptc */
1381         u64 tx_multicast;               /* mptc */
1382         u64 tx_broadcast;               /* bptc */
1383         u64 tx_discards;                /* tdpc */
1384         u64 tx_errors;                  /* tepc */
1385 };
1386
1387 /* Statistics collected per VEB per TC */
1388 struct i40e_veb_tc_stats {
1389         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1390         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1391         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1392         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1393 };
1394
1395 /* Statistics collected per function for FCoE */
1396 struct i40e_fcoe_stats {
1397         u64 rx_fcoe_packets;            /* fcoeprc */
1398         u64 rx_fcoe_dwords;             /* focedwrc */
1399         u64 rx_fcoe_dropped;            /* fcoerpdc */
1400         u64 tx_fcoe_packets;            /* fcoeptc */
1401         u64 tx_fcoe_dwords;             /* focedwtc */
1402         u64 fcoe_bad_fccrc;             /* fcoecrc */
1403         u64 fcoe_last_error;            /* fcoelast */
1404         u64 fcoe_ddp_count;             /* fcoeddpc */
1405 };
1406
1407 /* offset to per function FCoE statistics block */
1408 #define I40E_FCOE_VF_STAT_OFFSET        0
1409 #define I40E_FCOE_PF_STAT_OFFSET        128
1410 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1411
1412 /* Statistics collected by the MAC */
1413 struct i40e_hw_port_stats {
1414         /* eth stats collected by the port */
1415         struct i40e_eth_stats eth;
1416
1417         /* additional port specific stats */
1418         u64 tx_dropped_link_down;       /* tdold */
1419         u64 crc_errors;                 /* crcerrs */
1420         u64 illegal_bytes;              /* illerrc */
1421         u64 error_bytes;                /* errbc */
1422         u64 mac_local_faults;           /* mlfc */
1423         u64 mac_remote_faults;          /* mrfc */
1424         u64 rx_length_errors;           /* rlec */
1425         u64 link_xon_rx;                /* lxonrxc */
1426         u64 link_xoff_rx;               /* lxoffrxc */
1427         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1428         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1429         u64 link_xon_tx;                /* lxontxc */
1430         u64 link_xoff_tx;               /* lxofftxc */
1431         u64 priority_xon_tx[8];         /* pxontxc[8] */
1432         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1433         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1434         u64 rx_size_64;                 /* prc64 */
1435         u64 rx_size_127;                /* prc127 */
1436         u64 rx_size_255;                /* prc255 */
1437         u64 rx_size_511;                /* prc511 */
1438         u64 rx_size_1023;               /* prc1023 */
1439         u64 rx_size_1522;               /* prc1522 */
1440         u64 rx_size_big;                /* prc9522 */
1441         u64 rx_undersize;               /* ruc */
1442         u64 rx_fragments;               /* rfc */
1443         u64 rx_oversize;                /* roc */
1444         u64 rx_jabber;                  /* rjc */
1445         u64 tx_size_64;                 /* ptc64 */
1446         u64 tx_size_127;                /* ptc127 */
1447         u64 tx_size_255;                /* ptc255 */
1448         u64 tx_size_511;                /* ptc511 */
1449         u64 tx_size_1023;               /* ptc1023 */
1450         u64 tx_size_1522;               /* ptc1522 */
1451         u64 tx_size_big;                /* ptc9522 */
1452         u64 mac_short_packet_dropped;   /* mspdc */
1453         u64 checksum_error;             /* xec */
1454         /* flow director stats */
1455         u64 fd_atr_match;
1456         u64 fd_sb_match;
1457         u64 fd_atr_tunnel_match;
1458         u32 fd_atr_status;
1459         u32 fd_sb_status;
1460         /* EEE LPI */
1461         u32 tx_lpi_status;
1462         u32 rx_lpi_status;
1463         u64 tx_lpi_count;               /* etlpic */
1464         u64 rx_lpi_count;               /* erlpic */
1465 };
1466
1467 /* Checksum and Shadow RAM pointers */
1468 #define I40E_SR_NVM_CONTROL_WORD                0x00
1469 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1470 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1471 #define I40E_SR_OPTION_ROM_PTR                  0x05
1472 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1473 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1474 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1475 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1476 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1477 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1478 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1479 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1480 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1481 #define I40E_EMP_MODULE_PTR                     0x0F
1482 #define I40E_SR_EMP_MODULE_PTR                  0x48
1483 #define I40E_SR_PBA_FLAGS                       0x15
1484 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1485 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1486 #define I40E_NVM_OEM_VER_OFF                    0x83
1487 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1488 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1489 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1490 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1491 #define I40E_SR_NVM_MAP_VERSION                 0x29
1492 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1493 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1494 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1495 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1496 #define I40E_SR_VPD_PTR                         0x2F
1497 #define I40E_SR_PXE_SETUP_PTR                   0x30
1498 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1499 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1500 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1501 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1502 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1503 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1504 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1505 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1506 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1507 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1508 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1509 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1510 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1511 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1512 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1513 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1514 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1515 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1516 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1517
1518 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1519 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1520 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1521 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1522 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1523 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1524 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1525 #define I40E_PTR_TYPE                           BIT(15)
1526 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1527 #define I40E_SR_OCP_ENABLED                     BIT(15)
1528
1529 /* Shadow RAM related */
1530 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1531 #define I40E_SR_BUF_ALIGNMENT           4096
1532 #define I40E_SR_WORDS_IN_1KB            512
1533 /* Checksum should be calculated such that after adding all the words,
1534  * including the checksum word itself, the sum should be 0xBABA.
1535  */
1536 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1537
1538 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1539
1540 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1541
1542 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1543         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1544         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1545         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1546         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1547         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1548         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1549         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1550         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1551         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1552         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1553         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1554         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1555         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1556 };
1557
1558 /* FCoE DIF/DIX Context descriptor */
1559 struct i40e_fcoe_difdix_context_desc {
1560         __le64 flags_buff0_buff1_ref;
1561         __le64 difapp_msk_bias;
1562 };
1563
1564 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1565 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1566                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1567
1568 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1569         /* 2 BITS */
1570         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1571         /* 1 BIT  */
1572         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1573         /* 1 BIT  */
1574         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1575         /* 2 BITS */
1576         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1577         /* 2 BITS */
1578         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1579         /* 2 BITS */
1580         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1581         /* 2 BITS */
1582         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1583         /* 2 BITS */
1584         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1585         /* 2 BITS */
1586         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1587         /* 2 BITS */
1588         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1589         /* 2 BITS */
1590         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1591         /* 1 BIT  */
1592         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1593         /* 1 BIT  */
1594         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1595         /* 2 BITS */
1596         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1597         /* 2 BITS */
1598         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1599         /* 2 BITS */
1600         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1601         /* 2 BITS */
1602         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1603         /* 1 BIT  */
1604         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1605         /* 1 BIT  */
1606         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1607         /* 1 BIT */
1608         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1609         /* 1 BIT */
1610         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1611 };
1612
1613 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1614 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1615                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1616
1617 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1619                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1620
1621 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1623                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1624
1625 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1626 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1627                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1628
1629 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1631                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1632
1633 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1634 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1635                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1636
1637 /* FCoE DIF/DIX Buffers descriptor */
1638 struct i40e_fcoe_difdix_buffers_desc {
1639         __le64 buff_addr0;
1640         __le64 buff_addr1;
1641 };
1642
1643 /* FCoE DDP Context descriptor */
1644 struct i40e_fcoe_ddp_context_desc {
1645         __le64 rsvd;
1646         __le64 type_cmd_foff_lsize;
1647 };
1648
1649 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1650 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1651                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1652
1653 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1654 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1655                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1656
1657 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1658         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1659         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1660         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1661         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1662         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1663         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1664 };
1665
1666 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1667 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1668                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1669
1670 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1671 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1672                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1673
1674 /* FCoE DDP/DWO Queue Context descriptor */
1675 struct i40e_fcoe_queue_context_desc {
1676         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1677         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1678 };
1679
1680 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1681 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1682                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1683
1684 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1685 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1686                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1687
1688 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1689 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1690                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1691
1692 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1693 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1694                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1695
1696 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1697         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1698         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1699 };
1700
1701 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1702 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1703                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1704
1705 /* FCoE DDP/DWO Filter Context descriptor */
1706 struct i40e_fcoe_filter_context_desc {
1707         __le32 param;
1708         __le16 seqn;
1709
1710         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1711         __le16 rsvd_dmaindx;
1712
1713         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1714         __le64 flags_rsvd_lanq;
1715 };
1716
1717 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1718 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1719                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1720
1721 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1722         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1723         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1724         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1725         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1726         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1727         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1728 };
1729
1730 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1731 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1732                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1733
1734 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1735 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1736                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1737
1738 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1739 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1740                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1741
1742 enum i40e_switch_element_types {
1743         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1744         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1745         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1746         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1747         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1748         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1749         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1750         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1751         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1752 };
1753
1754 /* Supported EtherType filters */
1755 enum i40e_ether_type_index {
1756         I40E_ETHER_TYPE_1588            = 0,
1757         I40E_ETHER_TYPE_FIP             = 1,
1758         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1759         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1760         I40E_ETHER_TYPE_LLDP            = 4,
1761         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1762         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1763         I40E_ETHER_TYPE_QCN_CNM         = 7,
1764         I40E_ETHER_TYPE_8021X           = 8,
1765         I40E_ETHER_TYPE_ARP             = 9,
1766         I40E_ETHER_TYPE_RSV1            = 10,
1767         I40E_ETHER_TYPE_RSV2            = 11,
1768 };
1769
1770 /* Filter context base size is 1K */
1771 #define I40E_HASH_FILTER_BASE_SIZE      1024
1772 /* Supported Hash filter values */
1773 enum i40e_hash_filter_size {
1774         I40E_HASH_FILTER_SIZE_1K        = 0,
1775         I40E_HASH_FILTER_SIZE_2K        = 1,
1776         I40E_HASH_FILTER_SIZE_4K        = 2,
1777         I40E_HASH_FILTER_SIZE_8K        = 3,
1778         I40E_HASH_FILTER_SIZE_16K       = 4,
1779         I40E_HASH_FILTER_SIZE_32K       = 5,
1780         I40E_HASH_FILTER_SIZE_64K       = 6,
1781         I40E_HASH_FILTER_SIZE_128K      = 7,
1782         I40E_HASH_FILTER_SIZE_256K      = 8,
1783         I40E_HASH_FILTER_SIZE_512K      = 9,
1784         I40E_HASH_FILTER_SIZE_1M        = 10,
1785 };
1786
1787 /* DMA context base size is 0.5K */
1788 #define I40E_DMA_CNTX_BASE_SIZE         512
1789 /* Supported DMA context values */
1790 enum i40e_dma_cntx_size {
1791         I40E_DMA_CNTX_SIZE_512          = 0,
1792         I40E_DMA_CNTX_SIZE_1K           = 1,
1793         I40E_DMA_CNTX_SIZE_2K           = 2,
1794         I40E_DMA_CNTX_SIZE_4K           = 3,
1795         I40E_DMA_CNTX_SIZE_8K           = 4,
1796         I40E_DMA_CNTX_SIZE_16K          = 5,
1797         I40E_DMA_CNTX_SIZE_32K          = 6,
1798         I40E_DMA_CNTX_SIZE_64K          = 7,
1799         I40E_DMA_CNTX_SIZE_128K         = 8,
1800         I40E_DMA_CNTX_SIZE_256K         = 9,
1801 };
1802
1803 /* Supported Hash look up table (LUT) sizes */
1804 enum i40e_hash_lut_size {
1805         I40E_HASH_LUT_SIZE_128          = 0,
1806         I40E_HASH_LUT_SIZE_512          = 1,
1807 };
1808
1809 /* Structure to hold a per PF filter control settings */
1810 struct i40e_filter_control_settings {
1811         /* number of PE Quad Hash filter buckets */
1812         enum i40e_hash_filter_size pe_filt_num;
1813         /* number of PE Quad Hash contexts */
1814         enum i40e_dma_cntx_size pe_cntx_num;
1815         /* number of FCoE filter buckets */
1816         enum i40e_hash_filter_size fcoe_filt_num;
1817         /* number of FCoE DDP contexts */
1818         enum i40e_dma_cntx_size fcoe_cntx_num;
1819         /* size of the Hash LUT */
1820         enum i40e_hash_lut_size hash_lut_size;
1821         /* enable FDIR filters for PF and its VFs */
1822         bool enable_fdir;
1823         /* enable Ethertype filters for PF and its VFs */
1824         bool enable_ethtype;
1825         /* enable MAC/VLAN filters for PF and its VFs */
1826         bool enable_macvlan;
1827 };
1828
1829 /* Structure to hold device level control filter counts */
1830 struct i40e_control_filter_stats {
1831         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1832         u16 etype_used;       /* Used perfect EtherType filters */
1833         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1834         u16 etype_free;       /* Un-used perfect EtherType filters */
1835 };
1836
1837 enum i40e_reset_type {
1838         I40E_RESET_POR          = 0,
1839         I40E_RESET_CORER        = 1,
1840         I40E_RESET_GLOBR        = 2,
1841         I40E_RESET_EMPR         = 3,
1842 };
1843
1844 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1845 #define I40E_NVM_LLDP_CFG_PTR   0x06
1846 #define I40E_SR_LLDP_CFG_PTR    0x31
1847 struct i40e_lldp_variables {
1848         u16 length;
1849         u16 adminstatus;
1850         u16 msgfasttx;
1851         u16 msgtxinterval;
1852         u16 txparams;
1853         u16 timers;
1854         u16 crc8;
1855 };
1856
1857 /* Offsets into Alternate Ram */
1858 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1859 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1860 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1861 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1862 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1863 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1864
1865 /* Alternate Ram Bandwidth Masks */
1866 #define I40E_ALT_BW_VALUE_MASK          0xFF
1867 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1868 #define I40E_ALT_BW_VALID_MASK          0x80000000
1869
1870 /* RSS Hash Table Size */
1871 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1872
1873 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1874 #define I40E_L3_SRC_SHIFT               47
1875 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1876 #define I40E_L3_V6_SRC_SHIFT            43
1877 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1878 #define I40E_L3_DST_SHIFT               35
1879 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1880 #define I40E_L3_V6_DST_SHIFT            35
1881 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1882 #define I40E_L4_SRC_SHIFT               34
1883 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1884 #define I40E_L4_DST_SHIFT               33
1885 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1886 #define I40E_VERIFY_TAG_SHIFT           31
1887 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1888
1889 #define I40E_FLEX_50_SHIFT              13
1890 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1891 #define I40E_FLEX_51_SHIFT              12
1892 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1893 #define I40E_FLEX_52_SHIFT              11
1894 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1895 #define I40E_FLEX_53_SHIFT              10
1896 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1897 #define I40E_FLEX_54_SHIFT              9
1898 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1899 #define I40E_FLEX_55_SHIFT              8
1900 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1901 #define I40E_FLEX_56_SHIFT              7
1902 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1903 #define I40E_FLEX_57_SHIFT              6
1904 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1905
1906 /* Version format for Dynamic Device Personalization(DDP) */
1907 struct i40e_ddp_version {
1908         u8 major;
1909         u8 minor;
1910         u8 update;
1911         u8 draft;
1912 };
1913
1914 #define I40E_DDP_NAME_SIZE      32
1915
1916 /* Package header */
1917 struct i40e_package_header {
1918         struct i40e_ddp_version version;
1919         u32 segment_count;
1920         u32 segment_offset[1];
1921 };
1922
1923 /* Generic segment header */
1924 struct i40e_generic_seg_header {
1925 #define SEGMENT_TYPE_METADATA   0x00000001
1926 #define SEGMENT_TYPE_NOTES      0x00000002
1927 #define SEGMENT_TYPE_I40E       0x00000011
1928 #define SEGMENT_TYPE_X722       0x00000012
1929         u32 type;
1930         struct i40e_ddp_version version;
1931         u32 size;
1932         char name[I40E_DDP_NAME_SIZE];
1933 };
1934
1935 struct i40e_metadata_segment {
1936         struct i40e_generic_seg_header header;
1937         struct i40e_ddp_version version;
1938 #define I40E_DDP_TRACKID_RDONLY         0
1939 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1940         u32 track_id;
1941         char name[I40E_DDP_NAME_SIZE];
1942 };
1943
1944 struct i40e_device_id_entry {
1945         u32 vendor_dev_id;
1946         u32 sub_vendor_dev_id;
1947 };
1948
1949 struct i40e_profile_segment {
1950         struct i40e_generic_seg_header header;
1951         struct i40e_ddp_version version;
1952         char name[I40E_DDP_NAME_SIZE];
1953         u32 device_table_count;
1954         struct i40e_device_id_entry device_table[1];
1955 };
1956
1957 struct i40e_section_table {
1958         u32 section_count;
1959         u32 section_offset[1];
1960 };
1961
1962 struct i40e_profile_section_header {
1963         u16 tbl_size;
1964         u16 data_end;
1965         struct {
1966 #define SECTION_TYPE_INFO       0x00000010
1967 #define SECTION_TYPE_MMIO       0x00000800
1968 #define SECTION_TYPE_RB_MMIO    0x00001800
1969 #define SECTION_TYPE_AQ         0x00000801
1970 #define SECTION_TYPE_RB_AQ      0x00001801
1971 #define SECTION_TYPE_NOTE       0x80000000
1972 #define SECTION_TYPE_NAME       0x80000001
1973 #define SECTION_TYPE_PROTO      0x80000002
1974 #define SECTION_TYPE_PCTYPE     0x80000003
1975 #define SECTION_TYPE_PTYPE      0x80000004
1976                 u32 type;
1977                 u32 offset;
1978                 u32 size;
1979         } section;
1980 };
1981
1982 struct i40e_profile_tlv_section_record {
1983         u8 rtype;
1984         u8 type;
1985         u16 len;
1986         u8 data[12];
1987 };
1988
1989 /* Generic AQ section in proflie */
1990 struct i40e_profile_aq_section {
1991         u16 opcode;
1992         u16 flags;
1993         u8  param[16];
1994         u16 datalen;
1995         u8  data[1];
1996 };
1997
1998 struct i40e_profile_info {
1999         u32 track_id;
2000         struct i40e_ddp_version version;
2001         u8 op;
2002 #define I40E_DDP_ADD_TRACKID            0x01
2003 #define I40E_DDP_REMOVE_TRACKID 0x02
2004         u8 reserved[7];
2005         u8 name[I40E_DDP_NAME_SIZE];
2006 };
2007 #endif /* _I40E_TYPE_H_ */