1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
160 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
161 I40E_GLGEN_MSCA_STCODE_SHIFT)
162 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
163 I40E_GLGEN_MSCA_OPCODE_SHIFT)
164 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
165 I40E_GLGEN_MSCA_OPCODE_SHIFT)
167 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
168 I40E_GLGEN_MSCA_STCODE_SHIFT)
169 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
170 I40E_GLGEN_MSCA_OPCODE_SHIFT)
171 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
172 I40E_GLGEN_MSCA_OPCODE_SHIFT)
173 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
174 I40E_GLGEN_MSCA_OPCODE_SHIFT)
175 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
176 I40E_GLGEN_MSCA_OPCODE_SHIFT)
178 #define I40E_PHY_COM_REG_PAGE 0x1E
179 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
180 #define I40E_PHY_LED_MANUAL_ON 0x100
181 #define I40E_PHY_LED_PROV_REG_1 0xC430
182 #define I40E_PHY_LED_MODE_MASK 0xFFFF
183 #define I40E_PHY_LED_MODE_ORIG 0x80000000
186 enum i40e_memset_type {
192 enum i40e_memcpy_type {
193 I40E_NONDMA_TO_NONDMA = 0,
200 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
202 #define I40E_FW_API_VERSION_MINOR_X710 0x0005
205 /* These are structs for managing the hardware information and the operations.
206 * The structures of function pointers are filled out at init time when we
207 * know for sure exactly which hardware we're working with. This gives us the
208 * flexibility of using the same main driver code but adapting to slightly
209 * different hardware needs as new parts are developed. For this architecture,
210 * the Firmware and AdminQ are intended to insulate the driver from most of the
211 * future changes, but these structures will also do part of the job.
214 I40E_MAC_UNKNOWN = 0,
224 enum i40e_media_type {
225 I40E_MEDIA_TYPE_UNKNOWN = 0,
226 I40E_MEDIA_TYPE_FIBER,
227 I40E_MEDIA_TYPE_BASET,
228 I40E_MEDIA_TYPE_BACKPLANE,
231 I40E_MEDIA_TYPE_VIRTUAL
243 enum i40e_set_fc_aq_failures {
244 I40E_SET_FC_AQ_FAIL_NONE = 0,
245 I40E_SET_FC_AQ_FAIL_GET = 1,
246 I40E_SET_FC_AQ_FAIL_SET = 2,
247 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
248 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
260 I40E_VSI_TYPE_UNKNOWN
263 enum i40e_queue_type {
264 I40E_QUEUE_TYPE_RX = 0,
266 I40E_QUEUE_TYPE_PE_CEQ,
267 I40E_QUEUE_TYPE_UNKNOWN
270 struct i40e_link_status {
271 enum i40e_aq_phy_type phy_type;
272 enum i40e_aq_link_speed link_speed;
277 /* is Link Status Event notification to SW enabled */
284 /* 1st byte: module identifier */
285 #define I40E_MODULE_TYPE_SFP 0x03
286 #define I40E_MODULE_TYPE_QSFP 0x0D
287 /* 2nd byte: ethernet compliance codes for 10/40G */
288 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
289 #define I40E_MODULE_TYPE_40G_LR4 0x02
290 #define I40E_MODULE_TYPE_40G_SR4 0x04
291 #define I40E_MODULE_TYPE_40G_CR4 0x08
292 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
293 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
294 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
295 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
296 /* 3rd byte: ethernet compliance codes for 1G */
297 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
298 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
299 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
300 #define I40E_MODULE_TYPE_1000BASE_T 0x08
303 struct i40e_phy_info {
304 struct i40e_link_status link_info;
305 struct i40e_link_status link_info_old;
307 enum i40e_media_type media_type;
308 /* all the phy types the NVM is capable of */
312 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
313 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
314 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
315 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
316 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
317 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
318 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
319 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
320 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
321 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
323 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
324 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
325 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
326 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
327 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
328 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
329 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
330 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
331 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
332 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
333 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
334 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
335 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
336 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
337 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
338 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
339 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
340 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
342 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
343 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
344 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
345 * a shift is needed to adjust for this with values larger than 31. The
346 * only affected values are I40E_PHY_TYPE_25GBASE_*.
348 #define I40E_PHY_TYPE_OFFSET 1
349 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
350 I40E_PHY_TYPE_OFFSET)
351 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
352 I40E_PHY_TYPE_OFFSET)
353 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
354 I40E_PHY_TYPE_OFFSET)
355 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
356 I40E_PHY_TYPE_OFFSET)
357 #define I40E_HW_CAP_MAX_GPIO 30
358 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
359 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
362 enum i40e_acpi_programming_method {
363 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
364 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
367 #define I40E_WOL_SUPPORT_MASK 1
368 #define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1)
369 #define I40E_PROXY_SUPPORT_MASK (1 << 2)
372 /* Capabilities of a PF or a VF or the whole device */
373 struct i40e_hw_capabilities {
375 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
376 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
377 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
380 u32 mng_protocols_over_mctp;
381 #define I40E_MNG_PROTOCOL_PLDM 0x2
382 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
383 #define I40E_MNG_PROTOCOL_NCSI 0x8
389 bool evb_802_1_qbg; /* Edge Virtual Bridging */
390 bool evb_802_1_qbh; /* Bridge Port Extension */
393 bool iscsi; /* Indicates iSCSI enabled */
397 #define I40E_FLEX10_MODE_UNKNOWN 0x0
398 #define I40E_FLEX10_MODE_DCC 0x1
399 #define I40E_FLEX10_MODE_DCI 0x2
402 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
403 #define I40E_FLEX10_STATUS_VC_MODE 0x2
405 bool sec_rev_disabled;
406 bool update_disabled;
407 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
408 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
414 u32 fd_filters_guaranteed;
415 u32 fd_filters_best_effort;
418 u32 rss_table_entry_width;
419 bool led[I40E_HW_CAP_MAX_GPIO];
420 bool sdp[I40E_HW_CAP_MAX_GPIO];
422 u32 num_flow_director_filters;
429 u32 num_msix_vectors;
430 u32 num_msix_vectors_vf;
440 bool apm_wol_support;
441 enum i40e_acpi_programming_method acpi_prog_method;
446 struct i40e_mac_info {
447 enum i40e_mac_type type;
448 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
449 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
450 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
451 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
455 enum i40e_aq_resources_ids {
456 I40E_NVM_RESOURCE_ID = 1
459 enum i40e_aq_resource_access_type {
460 I40E_RESOURCE_READ = 1,
464 struct i40e_nvm_info {
465 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
466 u32 timeout; /* [ms] */
467 u16 sr_size; /* Shadow RAM size in words */
468 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
469 u16 version; /* NVM package version */
470 u32 eetrack; /* NVM data version */
471 u32 oem_ver; /* OEM version info */
474 /* definitions used in NVM update support */
476 enum i40e_nvmupd_cmd {
478 I40E_NVMUPD_READ_CON,
479 I40E_NVMUPD_READ_SNT,
480 I40E_NVMUPD_READ_LCB,
482 I40E_NVMUPD_WRITE_ERA,
483 I40E_NVMUPD_WRITE_CON,
484 I40E_NVMUPD_WRITE_SNT,
485 I40E_NVMUPD_WRITE_LCB,
486 I40E_NVMUPD_WRITE_SA,
487 I40E_NVMUPD_CSUM_CON,
489 I40E_NVMUPD_CSUM_LCB,
492 I40E_NVMUPD_GET_AQ_RESULT,
495 enum i40e_nvmupd_state {
496 I40E_NVMUPD_STATE_INIT,
497 I40E_NVMUPD_STATE_READING,
498 I40E_NVMUPD_STATE_WRITING,
499 I40E_NVMUPD_STATE_INIT_WAIT,
500 I40E_NVMUPD_STATE_WRITE_WAIT,
503 /* nvm_access definition and its masks/shifts need to be accessible to
504 * application, core driver, and shared code. Where is the right file?
506 #define I40E_NVM_READ 0xB
507 #define I40E_NVM_WRITE 0xC
509 #define I40E_NVM_MOD_PNT_MASK 0xFF
511 #define I40E_NVM_TRANS_SHIFT 8
512 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
513 #define I40E_NVM_CON 0x0
514 #define I40E_NVM_SNT 0x1
515 #define I40E_NVM_LCB 0x2
516 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
517 #define I40E_NVM_ERA 0x4
518 #define I40E_NVM_CSUM 0x8
519 #define I40E_NVM_EXEC 0xf
521 #define I40E_NVM_ADAPT_SHIFT 16
522 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
524 #define I40E_NVMUPD_MAX_DATA 4096
525 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
527 struct i40e_nvm_access {
530 u32 offset; /* in bytes */
531 u32 data_size; /* in bytes */
537 i40e_bus_type_unknown = 0,
540 i40e_bus_type_pci_express,
541 i40e_bus_type_reserved
545 enum i40e_bus_speed {
546 i40e_bus_speed_unknown = 0,
547 i40e_bus_speed_33 = 33,
548 i40e_bus_speed_66 = 66,
549 i40e_bus_speed_100 = 100,
550 i40e_bus_speed_120 = 120,
551 i40e_bus_speed_133 = 133,
552 i40e_bus_speed_2500 = 2500,
553 i40e_bus_speed_5000 = 5000,
554 i40e_bus_speed_8000 = 8000,
555 i40e_bus_speed_reserved
559 enum i40e_bus_width {
560 i40e_bus_width_unknown = 0,
561 i40e_bus_width_pcie_x1 = 1,
562 i40e_bus_width_pcie_x2 = 2,
563 i40e_bus_width_pcie_x4 = 4,
564 i40e_bus_width_pcie_x8 = 8,
565 i40e_bus_width_32 = 32,
566 i40e_bus_width_64 = 64,
567 i40e_bus_width_reserved
571 struct i40e_bus_info {
572 enum i40e_bus_speed speed;
573 enum i40e_bus_width width;
574 enum i40e_bus_type type;
582 /* Flow control (FC) parameters */
583 struct i40e_fc_info {
584 enum i40e_fc_mode current_mode; /* FC mode in effect */
585 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
588 #define I40E_MAX_TRAFFIC_CLASS 8
589 #define I40E_MAX_USER_PRIORITY 8
590 #define I40E_DCBX_MAX_APPS 32
591 #define I40E_LLDPDU_SIZE 1500
592 #define I40E_TLV_STATUS_OPER 0x1
593 #define I40E_TLV_STATUS_SYNC 0x2
594 #define I40E_TLV_STATUS_ERR 0x4
595 #define I40E_CEE_OPER_MAX_APPS 3
596 #define I40E_APP_PROTOID_FCOE 0x8906
597 #define I40E_APP_PROTOID_ISCSI 0x0cbc
598 #define I40E_APP_PROTOID_FIP 0x8914
599 #define I40E_APP_SEL_ETHTYPE 0x1
600 #define I40E_APP_SEL_TCPIP 0x2
601 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
602 #define I40E_CEE_APP_SEL_TCPIP 0x1
604 /* CEE or IEEE 802.1Qaz ETS Configuration data */
605 struct i40e_dcb_ets_config {
609 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
610 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
611 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
614 /* CEE or IEEE 802.1Qaz PFC Configuration data */
615 struct i40e_dcb_pfc_config {
622 /* CEE or IEEE 802.1Qaz Application Priority data */
623 struct i40e_dcb_app_priority_table {
629 struct i40e_dcbx_config {
631 #define I40E_DCBX_MODE_CEE 0x1
632 #define I40E_DCBX_MODE_IEEE 0x2
634 #define I40E_DCBX_APPS_NON_WILLING 0x1
636 u32 tlv_status; /* CEE mode TLV status */
637 struct i40e_dcb_ets_config etscfg;
638 struct i40e_dcb_ets_config etsrec;
639 struct i40e_dcb_pfc_config pfc;
640 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
643 /* Port hardware description */
648 /* subsystem structs */
649 struct i40e_phy_info phy;
650 struct i40e_mac_info mac;
651 struct i40e_bus_info bus;
652 struct i40e_nvm_info nvm;
653 struct i40e_fc_info fc;
658 u16 subsystem_device_id;
659 u16 subsystem_vendor_id;
662 bool adapter_stopped;
664 /* capabilities for entire device and PCI func */
665 struct i40e_hw_capabilities dev_caps;
666 struct i40e_hw_capabilities func_caps;
668 /* Flow Director shared filter space */
669 u16 fdir_shared_filter_count;
671 /* device profile info */
675 /* for multi-function MACs */
680 /* Closest numa node to the device */
683 /* Admin Queue info */
684 struct i40e_adminq_info aq;
686 /* state of nvm update process */
687 enum i40e_nvmupd_state nvmupd_state;
688 struct i40e_aq_desc nvm_wb_desc;
689 struct i40e_virt_mem nvm_buff;
690 bool nvm_release_on_done;
694 struct i40e_hmc_info hmc; /* HMC info struct */
696 /* LLDP/DCBX Status */
700 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
701 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
702 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
705 /* WoL and proxy support */
706 u16 num_wol_proxy_filters;
707 u16 wol_proxy_vsi_seid;
710 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
715 #ifndef I40E_NDIS_SUPPORT
717 #endif /* I40E_NDIS_SUPPORT */
720 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
723 return (hw->mac.type == I40E_MAC_VF ||
724 hw->mac.type == I40E_MAC_X722_VF);
726 return hw->mac.type == I40E_MAC_VF;
730 struct i40e_driver_version {
735 u8 driver_string[32];
739 union i40e_16byte_rx_desc {
741 __le64 pkt_addr; /* Packet buffer address */
742 __le64 hdr_addr; /* Header buffer address */
748 __le16 mirroring_status;
754 __le32 rss; /* RSS Hash */
755 __le32 fd_id; /* Flow director filter id */
756 __le32 fcoe_param; /* FCoE DDP Context id */
760 /* ext status/error/pktype/length */
761 __le64 status_error_len;
763 } wb; /* writeback */
766 union i40e_32byte_rx_desc {
768 __le64 pkt_addr; /* Packet buffer address */
769 __le64 hdr_addr; /* Header buffer address */
770 /* bit 0 of hdr_buffer_addr is DD bit */
778 __le16 mirroring_status;
784 __le32 rss; /* RSS Hash */
785 __le32 fcoe_param; /* FCoE DDP Context id */
786 /* Flow director filter id in case of
787 * Programming status desc WB
793 /* status/error/pktype/length */
794 __le64 status_error_len;
797 __le16 ext_status; /* extended status */
804 __le32 flex_bytes_lo;
808 __le32 flex_bytes_hi;
812 } wb; /* writeback */
815 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
816 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
817 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
818 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
819 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
820 I40E_RXD_QW0_FCOEINDX_SHIFT)
822 enum i40e_rx_desc_status_bits {
823 /* Note: These are predefined bit offsets */
824 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
825 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
826 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
827 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
828 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
829 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
830 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
832 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
834 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
837 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
838 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
839 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
840 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
841 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
842 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
844 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
846 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
848 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
851 #define I40E_RXD_QW1_STATUS_SHIFT 0
852 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
853 I40E_RXD_QW1_STATUS_SHIFT)
855 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
856 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
857 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
859 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
860 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
862 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
863 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
864 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
866 enum i40e_rx_desc_fltstat_values {
867 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
868 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
869 I40E_RX_DESC_FLTSTAT_RSV = 2,
870 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
873 #define I40E_RXD_PACKET_TYPE_UNICAST 0
874 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
875 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
876 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
878 #define I40E_RXD_QW1_ERROR_SHIFT 19
879 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
881 enum i40e_rx_desc_error_bits {
882 /* Note: These are predefined bit offsets */
883 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
884 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
885 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
886 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
887 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
888 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
889 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
890 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
891 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
894 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
895 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
896 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
897 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
898 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
899 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
902 #define I40E_RXD_QW1_PTYPE_SHIFT 30
903 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
905 /* Packet type non-ip values */
906 enum i40e_rx_l2_ptype {
907 I40E_RX_PTYPE_L2_RESERVED = 0,
908 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
909 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
910 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
911 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
912 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
913 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
914 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
915 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
916 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
917 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
918 I40E_RX_PTYPE_L2_ARP = 11,
919 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
920 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
921 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
922 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
923 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
924 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
925 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
926 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
927 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
928 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
929 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
930 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
931 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
932 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
935 struct i40e_rx_ptype_decoded {
942 u32 tunnel_end_prot:2;
943 u32 tunnel_end_frag:1;
948 enum i40e_rx_ptype_outer_ip {
949 I40E_RX_PTYPE_OUTER_L2 = 0,
950 I40E_RX_PTYPE_OUTER_IP = 1
953 enum i40e_rx_ptype_outer_ip_ver {
954 I40E_RX_PTYPE_OUTER_NONE = 0,
955 I40E_RX_PTYPE_OUTER_IPV4 = 0,
956 I40E_RX_PTYPE_OUTER_IPV6 = 1
959 enum i40e_rx_ptype_outer_fragmented {
960 I40E_RX_PTYPE_NOT_FRAG = 0,
961 I40E_RX_PTYPE_FRAG = 1
964 enum i40e_rx_ptype_tunnel_type {
965 I40E_RX_PTYPE_TUNNEL_NONE = 0,
966 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
967 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
968 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
969 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
972 enum i40e_rx_ptype_tunnel_end_prot {
973 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
974 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
975 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
978 enum i40e_rx_ptype_inner_prot {
979 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
980 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
981 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
982 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
983 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
984 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
987 enum i40e_rx_ptype_payload_layer {
988 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
989 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
990 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
991 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
994 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
995 #define I40E_RX_PTYPE_SHIFT 56
997 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
998 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
999 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1001 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
1002 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
1003 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1005 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
1006 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1008 #define I40E_RXD_QW1_NEXTP_SHIFT 38
1009 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1011 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
1012 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
1013 I40E_RXD_QW2_EXT_STATUS_SHIFT)
1015 enum i40e_rx_desc_ext_status_bits {
1016 /* Note: These are predefined bit offsets */
1017 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
1018 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1019 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1020 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1021 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1022 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1023 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1026 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1027 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1029 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1030 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1032 enum i40e_rx_desc_pe_status_bits {
1033 /* Note: These are predefined bit offsets */
1034 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1035 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1036 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1037 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1038 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1039 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1040 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1041 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1042 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1045 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1046 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1048 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1049 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1050 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1052 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1053 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1054 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1056 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1057 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1058 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1060 enum i40e_rx_prog_status_desc_status_bits {
1061 /* Note: These are predefined bit offsets */
1062 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1063 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1066 enum i40e_rx_prog_status_desc_prog_id_masks {
1067 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1068 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1069 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1072 enum i40e_rx_prog_status_desc_error_bits {
1073 /* Note: These are predefined bit offsets */
1074 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1075 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1076 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1077 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1080 #define I40E_TWO_BIT_MASK 0x3
1081 #define I40E_THREE_BIT_MASK 0x7
1082 #define I40E_FOUR_BIT_MASK 0xF
1083 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1086 struct i40e_tx_desc {
1087 __le64 buffer_addr; /* Address of descriptor's data buf */
1088 __le64 cmd_type_offset_bsz;
1091 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1092 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1094 enum i40e_tx_desc_dtype_value {
1095 I40E_TX_DESC_DTYPE_DATA = 0x0,
1096 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1097 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1098 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1099 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1100 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1101 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1102 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1103 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1104 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1107 #define I40E_TXD_QW1_CMD_SHIFT 4
1108 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1110 enum i40e_tx_desc_cmd_bits {
1111 I40E_TX_DESC_CMD_EOP = 0x0001,
1112 I40E_TX_DESC_CMD_RS = 0x0002,
1113 I40E_TX_DESC_CMD_ICRC = 0x0004,
1114 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1115 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1116 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1117 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1118 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1119 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1120 I40E_TX_DESC_CMD_FCOET = 0x0080,
1121 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1122 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1123 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1124 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1125 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1126 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1127 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1128 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1131 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1132 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1133 I40E_TXD_QW1_OFFSET_SHIFT)
1135 enum i40e_tx_desc_length_fields {
1136 /* Note: These are predefined bit offsets */
1137 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1138 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1139 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1142 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1143 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1144 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1145 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1147 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1148 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1149 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1151 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1152 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1154 /* Context descriptors */
1155 struct i40e_tx_context_desc {
1156 __le32 tunneling_params;
1159 __le64 type_cmd_tso_mss;
1162 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1163 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1165 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1166 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1168 enum i40e_tx_ctx_desc_cmd_bits {
1169 I40E_TX_CTX_DESC_TSO = 0x01,
1170 I40E_TX_CTX_DESC_TSYN = 0x02,
1171 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1172 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1173 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1174 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1175 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1176 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1177 I40E_TX_CTX_DESC_SWPE = 0x40
1180 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1181 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1182 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1184 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1185 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1186 I40E_TXD_CTX_QW1_MSS_SHIFT)
1188 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1189 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1191 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1192 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1193 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1195 enum i40e_tx_ctx_desc_eipt_offload {
1196 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1197 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1198 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1199 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1202 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1203 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1204 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1206 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1207 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1209 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1210 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1212 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1213 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1215 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1217 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1218 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1219 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1221 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1222 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1223 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1226 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1227 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1229 struct i40e_nop_desc {
1234 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1235 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1237 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1238 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1240 enum i40e_tx_nop_desc_cmd_bits {
1241 /* Note: These are predefined bit offsets */
1242 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1243 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1244 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1247 struct i40e_filter_program_desc {
1248 __le32 qindex_flex_ptype_vsi;
1250 __le32 dtype_cmd_cntindex;
1253 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1254 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1255 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1256 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1257 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1258 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1259 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1260 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1261 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1263 /* Packet Classifier Types for filters */
1264 enum i40e_filter_pctype {
1266 /* Note: Values 0-28 are reserved for future use.
1267 * Value 29, 30, 32 are not supported on XL710 and X710.
1269 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1270 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1272 /* Note: Values 0-30 are reserved for future use */
1274 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1276 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1278 /* Note: Value 32 is reserved for future use */
1280 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1281 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1282 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1283 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1285 /* Note: Values 37-38 are reserved for future use.
1286 * Value 39, 40, 42 are not supported on XL710 and X710.
1288 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1289 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1291 /* Note: Values 37-40 are reserved for future use */
1293 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1295 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1297 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1298 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1299 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1300 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1301 /* Note: Value 47 is reserved for future use */
1302 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1303 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1304 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1305 /* Note: Values 51-62 are reserved for future use */
1306 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1309 enum i40e_filter_program_desc_dest {
1310 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1311 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1312 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1315 enum i40e_filter_program_desc_fd_status {
1316 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1317 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1318 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1319 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1322 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1323 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1324 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1326 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1327 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1329 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1330 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1331 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1333 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1334 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1336 enum i40e_filter_program_desc_pcmd {
1337 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1338 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1341 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1342 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1344 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1345 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1347 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1348 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1349 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1350 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1353 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1354 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1355 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1358 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1359 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1360 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1362 enum i40e_filter_type {
1363 I40E_FLOW_DIRECTOR_FLTR = 0,
1364 I40E_PE_QUAD_HASH_FLTR = 1,
1365 I40E_ETHERTYPE_FLTR,
1371 struct i40e_vsi_context {
1376 u16 vsis_unallocated;
1381 struct i40e_aqc_vsi_properties_data info;
1384 struct i40e_veb_context {
1389 u16 vebs_unallocated;
1391 struct i40e_aqc_get_veb_parameters_completion info;
1394 /* Statistics collected by each port, VSI, VEB, and S-channel */
1395 struct i40e_eth_stats {
1396 u64 rx_bytes; /* gorc */
1397 u64 rx_unicast; /* uprc */
1398 u64 rx_multicast; /* mprc */
1399 u64 rx_broadcast; /* bprc */
1400 u64 rx_discards; /* rdpc */
1401 u64 rx_unknown_protocol; /* rupp */
1402 u64 tx_bytes; /* gotc */
1403 u64 tx_unicast; /* uptc */
1404 u64 tx_multicast; /* mptc */
1405 u64 tx_broadcast; /* bptc */
1406 u64 tx_discards; /* tdpc */
1407 u64 tx_errors; /* tepc */
1410 /* Statistics collected per VEB per TC */
1411 struct i40e_veb_tc_stats {
1412 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1413 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1414 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1415 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1418 /* Statistics collected per function for FCoE */
1419 struct i40e_fcoe_stats {
1420 u64 rx_fcoe_packets; /* fcoeprc */
1421 u64 rx_fcoe_dwords; /* focedwrc */
1422 u64 rx_fcoe_dropped; /* fcoerpdc */
1423 u64 tx_fcoe_packets; /* fcoeptc */
1424 u64 tx_fcoe_dwords; /* focedwtc */
1425 u64 fcoe_bad_fccrc; /* fcoecrc */
1426 u64 fcoe_last_error; /* fcoelast */
1427 u64 fcoe_ddp_count; /* fcoeddpc */
1430 /* offset to per function FCoE statistics block */
1431 #define I40E_FCOE_VF_STAT_OFFSET 0
1432 #define I40E_FCOE_PF_STAT_OFFSET 128
1433 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1435 /* Statistics collected by the MAC */
1436 struct i40e_hw_port_stats {
1437 /* eth stats collected by the port */
1438 struct i40e_eth_stats eth;
1440 /* additional port specific stats */
1441 u64 tx_dropped_link_down; /* tdold */
1442 u64 crc_errors; /* crcerrs */
1443 u64 illegal_bytes; /* illerrc */
1444 u64 error_bytes; /* errbc */
1445 u64 mac_local_faults; /* mlfc */
1446 u64 mac_remote_faults; /* mrfc */
1447 u64 rx_length_errors; /* rlec */
1448 u64 link_xon_rx; /* lxonrxc */
1449 u64 link_xoff_rx; /* lxoffrxc */
1450 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1451 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1452 u64 link_xon_tx; /* lxontxc */
1453 u64 link_xoff_tx; /* lxofftxc */
1454 u64 priority_xon_tx[8]; /* pxontxc[8] */
1455 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1456 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1457 u64 rx_size_64; /* prc64 */
1458 u64 rx_size_127; /* prc127 */
1459 u64 rx_size_255; /* prc255 */
1460 u64 rx_size_511; /* prc511 */
1461 u64 rx_size_1023; /* prc1023 */
1462 u64 rx_size_1522; /* prc1522 */
1463 u64 rx_size_big; /* prc9522 */
1464 u64 rx_undersize; /* ruc */
1465 u64 rx_fragments; /* rfc */
1466 u64 rx_oversize; /* roc */
1467 u64 rx_jabber; /* rjc */
1468 u64 tx_size_64; /* ptc64 */
1469 u64 tx_size_127; /* ptc127 */
1470 u64 tx_size_255; /* ptc255 */
1471 u64 tx_size_511; /* ptc511 */
1472 u64 tx_size_1023; /* ptc1023 */
1473 u64 tx_size_1522; /* ptc1522 */
1474 u64 tx_size_big; /* ptc9522 */
1475 u64 mac_short_packet_dropped; /* mspdc */
1476 u64 checksum_error; /* xec */
1477 /* flow director stats */
1480 u64 fd_atr_tunnel_match;
1486 u64 tx_lpi_count; /* etlpic */
1487 u64 rx_lpi_count; /* erlpic */
1490 /* Checksum and Shadow RAM pointers */
1491 #define I40E_SR_NVM_CONTROL_WORD 0x00
1492 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1493 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1494 #define I40E_SR_OPTION_ROM_PTR 0x05
1495 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1496 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1497 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1498 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1499 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1500 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1501 #define I40E_SR_PE_IMAGE_PTR 0x0C
1502 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1503 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1504 #define I40E_SR_EMP_MODULE_PTR 0x0F
1505 #define I40E_SR_PBA_FLAGS 0x15
1506 #define I40E_SR_PBA_BLOCK_PTR 0x16
1507 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1508 #define I40E_NVM_OEM_VER_OFF 0x83
1509 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1510 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1511 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1512 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1513 #define I40E_SR_NVM_MAP_VERSION 0x29
1514 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1515 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1516 #define I40E_SR_NVM_EETRACK_LO 0x2D
1517 #define I40E_SR_NVM_EETRACK_HI 0x2E
1518 #define I40E_SR_VPD_PTR 0x2F
1519 #define I40E_SR_PXE_SETUP_PTR 0x30
1520 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1521 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1522 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1523 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1524 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1525 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1526 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1527 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1528 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1529 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1530 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1531 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1532 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1533 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1534 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1535 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1536 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1537 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1539 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1540 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1541 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1542 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1543 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1545 /* Shadow RAM related */
1546 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1547 #define I40E_SR_BUF_ALIGNMENT 4096
1548 #define I40E_SR_WORDS_IN_1KB 512
1549 /* Checksum should be calculated such that after adding all the words,
1550 * including the checksum word itself, the sum should be 0xBABA.
1552 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1554 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1556 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1558 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1559 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1560 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1561 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1562 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1563 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1564 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1565 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1566 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1567 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1568 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1569 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1570 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1571 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1574 /* FCoE DIF/DIX Context descriptor */
1575 struct i40e_fcoe_difdix_context_desc {
1576 __le64 flags_buff0_buff1_ref;
1577 __le64 difapp_msk_bias;
1580 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1581 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1582 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1584 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1586 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1588 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1590 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1592 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1594 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1596 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1598 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1600 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1602 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1604 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1606 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1608 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1610 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1612 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1614 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1616 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1618 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1620 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1622 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1624 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1626 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1629 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1630 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1631 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1633 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1634 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1635 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1637 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1638 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1639 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1641 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1642 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1643 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1645 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1646 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1647 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1649 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1650 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1651 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1653 /* FCoE DIF/DIX Buffers descriptor */
1654 struct i40e_fcoe_difdix_buffers_desc {
1659 /* FCoE DDP Context descriptor */
1660 struct i40e_fcoe_ddp_context_desc {
1662 __le64 type_cmd_foff_lsize;
1665 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1666 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1667 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1669 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1670 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1671 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1673 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1674 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1675 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1676 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1677 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1678 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1679 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1682 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1683 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1684 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1686 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1687 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1688 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1690 /* FCoE DDP/DWO Queue Context descriptor */
1691 struct i40e_fcoe_queue_context_desc {
1692 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1693 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1696 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1697 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1698 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1700 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1701 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1702 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1704 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1705 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1706 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1708 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1709 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1710 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1712 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1713 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1714 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1717 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1718 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1719 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1721 /* FCoE DDP/DWO Filter Context descriptor */
1722 struct i40e_fcoe_filter_context_desc {
1726 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1727 __le16 rsvd_dmaindx;
1729 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1730 __le64 flags_rsvd_lanq;
1733 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1734 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1735 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1737 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1738 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1739 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1740 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1741 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1742 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1743 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1746 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1747 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1748 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1750 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1751 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1752 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1754 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1755 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1756 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1758 enum i40e_switch_element_types {
1759 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1760 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1761 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1762 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1763 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1764 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1765 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1766 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1767 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1770 /* Supported EtherType filters */
1771 enum i40e_ether_type_index {
1772 I40E_ETHER_TYPE_1588 = 0,
1773 I40E_ETHER_TYPE_FIP = 1,
1774 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1775 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1776 I40E_ETHER_TYPE_LLDP = 4,
1777 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1778 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1779 I40E_ETHER_TYPE_QCN_CNM = 7,
1780 I40E_ETHER_TYPE_8021X = 8,
1781 I40E_ETHER_TYPE_ARP = 9,
1782 I40E_ETHER_TYPE_RSV1 = 10,
1783 I40E_ETHER_TYPE_RSV2 = 11,
1786 /* Filter context base size is 1K */
1787 #define I40E_HASH_FILTER_BASE_SIZE 1024
1788 /* Supported Hash filter values */
1789 enum i40e_hash_filter_size {
1790 I40E_HASH_FILTER_SIZE_1K = 0,
1791 I40E_HASH_FILTER_SIZE_2K = 1,
1792 I40E_HASH_FILTER_SIZE_4K = 2,
1793 I40E_HASH_FILTER_SIZE_8K = 3,
1794 I40E_HASH_FILTER_SIZE_16K = 4,
1795 I40E_HASH_FILTER_SIZE_32K = 5,
1796 I40E_HASH_FILTER_SIZE_64K = 6,
1797 I40E_HASH_FILTER_SIZE_128K = 7,
1798 I40E_HASH_FILTER_SIZE_256K = 8,
1799 I40E_HASH_FILTER_SIZE_512K = 9,
1800 I40E_HASH_FILTER_SIZE_1M = 10,
1803 /* DMA context base size is 0.5K */
1804 #define I40E_DMA_CNTX_BASE_SIZE 512
1805 /* Supported DMA context values */
1806 enum i40e_dma_cntx_size {
1807 I40E_DMA_CNTX_SIZE_512 = 0,
1808 I40E_DMA_CNTX_SIZE_1K = 1,
1809 I40E_DMA_CNTX_SIZE_2K = 2,
1810 I40E_DMA_CNTX_SIZE_4K = 3,
1811 I40E_DMA_CNTX_SIZE_8K = 4,
1812 I40E_DMA_CNTX_SIZE_16K = 5,
1813 I40E_DMA_CNTX_SIZE_32K = 6,
1814 I40E_DMA_CNTX_SIZE_64K = 7,
1815 I40E_DMA_CNTX_SIZE_128K = 8,
1816 I40E_DMA_CNTX_SIZE_256K = 9,
1819 /* Supported Hash look up table (LUT) sizes */
1820 enum i40e_hash_lut_size {
1821 I40E_HASH_LUT_SIZE_128 = 0,
1822 I40E_HASH_LUT_SIZE_512 = 1,
1825 /* Structure to hold a per PF filter control settings */
1826 struct i40e_filter_control_settings {
1827 /* number of PE Quad Hash filter buckets */
1828 enum i40e_hash_filter_size pe_filt_num;
1829 /* number of PE Quad Hash contexts */
1830 enum i40e_dma_cntx_size pe_cntx_num;
1831 /* number of FCoE filter buckets */
1832 enum i40e_hash_filter_size fcoe_filt_num;
1833 /* number of FCoE DDP contexts */
1834 enum i40e_dma_cntx_size fcoe_cntx_num;
1835 /* size of the Hash LUT */
1836 enum i40e_hash_lut_size hash_lut_size;
1837 /* enable FDIR filters for PF and its VFs */
1839 /* enable Ethertype filters for PF and its VFs */
1840 bool enable_ethtype;
1841 /* enable MAC/VLAN filters for PF and its VFs */
1842 bool enable_macvlan;
1845 /* Structure to hold device level control filter counts */
1846 struct i40e_control_filter_stats {
1847 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1848 u16 etype_used; /* Used perfect EtherType filters */
1849 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1850 u16 etype_free; /* Un-used perfect EtherType filters */
1853 enum i40e_reset_type {
1855 I40E_RESET_CORER = 1,
1856 I40E_RESET_GLOBR = 2,
1857 I40E_RESET_EMPR = 3,
1860 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1861 #define I40E_NVM_LLDP_CFG_PTR 0xD
1862 struct i40e_lldp_variables {
1872 /* Offsets into Alternate Ram */
1873 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1874 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1875 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1876 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1877 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1878 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1880 /* Alternate Ram Bandwidth Masks */
1881 #define I40E_ALT_BW_VALUE_MASK 0xFF
1882 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1883 #define I40E_ALT_BW_VALID_MASK 0x80000000
1885 /* RSS Hash Table Size */
1886 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1888 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1889 #define I40E_L3_SRC_SHIFT 47
1890 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1891 #define I40E_L3_V6_SRC_SHIFT 43
1892 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1893 #define I40E_L3_DST_SHIFT 35
1894 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1895 #define I40E_L3_V6_DST_SHIFT 35
1896 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1897 #define I40E_L4_SRC_SHIFT 34
1898 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1899 #define I40E_L4_DST_SHIFT 33
1900 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1901 #define I40E_VERIFY_TAG_SHIFT 31
1902 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1904 #define I40E_FLEX_50_SHIFT 13
1905 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1906 #define I40E_FLEX_51_SHIFT 12
1907 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1908 #define I40E_FLEX_52_SHIFT 11
1909 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1910 #define I40E_FLEX_53_SHIFT 10
1911 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1912 #define I40E_FLEX_54_SHIFT 9
1913 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1914 #define I40E_FLEX_55_SHIFT 8
1915 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1916 #define I40E_FLEX_56_SHIFT 7
1917 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1918 #define I40E_FLEX_57_SHIFT 6
1919 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1920 #endif /* _I40E_TYPE_H_ */