1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
8 #include "i40e_status.h"
9 #include "i40e_osdep.h"
10 #include "i40e_register.h"
11 #include "i40e_adminq.h"
13 #include "i40e_lan_hmc.h"
14 #include "i40e_devids.h"
16 #define UNREFERENCED_XPARAMETER
17 #define UNREFERENCED_1PARAMETER(_p) (_p);
18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
25 #define BIT(a) (1UL << (a))
28 #define BIT_ULL(a) (1ULL << (a))
30 #endif /* LINUX_MACROS */
33 /* I40E_MASK is a macro used on 32 bit registers */
34 #define I40E_MASK(mask, shift) (mask << shift)
37 #define I40E_MAX_PF 16
38 #define I40E_MAX_PF_VSI 64
39 #define I40E_MAX_PF_QP 128
40 #define I40E_MAX_VSI_QP 16
41 #define I40E_MAX_VF_VSI 4
42 #define I40E_MAX_CHAINED_RX_BUFFERS 5
43 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45 /* something less than 1 minute */
46 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
48 /* Max default timeout in ms, */
49 #define I40E_MAX_NVM_TIMEOUT 18000
51 /* Max timeout in ms for the phy to respond */
52 #define I40E_MAX_PHY_TIMEOUT 500
54 /* Check whether address is multicast. */
55 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
57 /* Check whether an address is broadcast. */
58 #define I40E_IS_BROADCAST(address) \
59 ((((u8 *)(address))[0] == ((u8)0xff)) && \
60 (((u8 *)(address))[1] == ((u8)0xff)))
62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
63 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
65 /* forward declaration */
67 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
72 /* Data type manipulation macros. */
73 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
74 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
76 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
77 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
79 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
80 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
82 /* Number of Transmit Descriptors must be a multiple of 8. */
83 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
84 /* Number of Receive Descriptors must be a multiple of 32 if
85 * the number of descriptors is greater than 32.
87 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
89 #define I40E_DESC_UNUSED(R) \
90 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
91 (R)->next_to_clean - (R)->next_to_use - 1)
93 /* bitfields for Tx queue mapping in QTX_CTL */
94 #define I40E_QTX_CTL_VF_QUEUE 0x0
95 #define I40E_QTX_CTL_VM_QUEUE 0x1
96 #define I40E_QTX_CTL_PF_QUEUE 0x2
98 /* debug masks - set these bits in hw->debug_mask to control output */
99 enum i40e_debug_mask {
100 I40E_DEBUG_INIT = 0x00000001,
101 I40E_DEBUG_RELEASE = 0x00000002,
103 I40E_DEBUG_LINK = 0x00000010,
104 I40E_DEBUG_PHY = 0x00000020,
105 I40E_DEBUG_HMC = 0x00000040,
106 I40E_DEBUG_NVM = 0x00000080,
107 I40E_DEBUG_LAN = 0x00000100,
108 I40E_DEBUG_FLOW = 0x00000200,
109 I40E_DEBUG_DCB = 0x00000400,
110 I40E_DEBUG_DIAG = 0x00000800,
111 I40E_DEBUG_FD = 0x00001000,
112 I40E_DEBUG_PACKAGE = 0x00002000,
114 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
115 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
116 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
117 I40E_DEBUG_AQ_COMMAND = 0x06000000,
118 I40E_DEBUG_AQ = 0x0F000000,
120 I40E_DEBUG_USER = 0xF0000000,
122 I40E_DEBUG_ALL = 0xFFFFFFFF
126 #define I40E_PCI_LINK_STATUS 0xB2
127 #define I40E_PCI_LINK_WIDTH 0x3F0
128 #define I40E_PCI_LINK_WIDTH_1 0x10
129 #define I40E_PCI_LINK_WIDTH_2 0x20
130 #define I40E_PCI_LINK_WIDTH_4 0x40
131 #define I40E_PCI_LINK_WIDTH_8 0x80
132 #define I40E_PCI_LINK_SPEED 0xF
133 #define I40E_PCI_LINK_SPEED_2500 0x1
134 #define I40E_PCI_LINK_SPEED_5000 0x2
135 #define I40E_PCI_LINK_SPEED_8000 0x3
137 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
138 I40E_GLGEN_MSCA_STCODE_SHIFT)
139 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
140 I40E_GLGEN_MSCA_OPCODE_SHIFT)
141 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
142 I40E_GLGEN_MSCA_OPCODE_SHIFT)
144 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
145 I40E_GLGEN_MSCA_STCODE_SHIFT)
146 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
147 I40E_GLGEN_MSCA_OPCODE_SHIFT)
148 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
149 I40E_GLGEN_MSCA_OPCODE_SHIFT)
150 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
151 I40E_GLGEN_MSCA_OPCODE_SHIFT)
152 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
153 I40E_GLGEN_MSCA_OPCODE_SHIFT)
155 #define I40E_PHY_COM_REG_PAGE 0x1E
156 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
157 #define I40E_PHY_LED_MANUAL_ON 0x100
158 #define I40E_PHY_LED_PROV_REG_1 0xC430
159 #define I40E_PHY_LED_MODE_MASK 0xFFFF
160 #define I40E_PHY_LED_MODE_ORIG 0x80000000
163 enum i40e_memset_type {
169 enum i40e_memcpy_type {
170 I40E_NONDMA_TO_NONDMA = 0,
176 /* These are structs for managing the hardware information and the operations.
177 * The structures of function pointers are filled out at init time when we
178 * know for sure exactly which hardware we're working with. This gives us the
179 * flexibility of using the same main driver code but adapting to slightly
180 * different hardware needs as new parts are developed. For this architecture,
181 * the Firmware and AdminQ are intended to insulate the driver from most of the
182 * future changes, but these structures will also do part of the job.
185 I40E_MAC_UNKNOWN = 0,
193 enum i40e_media_type {
194 I40E_MEDIA_TYPE_UNKNOWN = 0,
195 I40E_MEDIA_TYPE_FIBER,
196 I40E_MEDIA_TYPE_BASET,
197 I40E_MEDIA_TYPE_BACKPLANE,
200 I40E_MEDIA_TYPE_VIRTUAL
212 enum i40e_set_fc_aq_failures {
213 I40E_SET_FC_AQ_FAIL_NONE = 0,
214 I40E_SET_FC_AQ_FAIL_GET = 1,
215 I40E_SET_FC_AQ_FAIL_SET = 2,
216 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
217 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
229 I40E_VSI_TYPE_UNKNOWN
232 enum i40e_queue_type {
233 I40E_QUEUE_TYPE_RX = 0,
235 I40E_QUEUE_TYPE_PE_CEQ,
236 I40E_QUEUE_TYPE_UNKNOWN
239 struct i40e_link_status {
240 enum i40e_aq_phy_type phy_type;
241 enum i40e_aq_link_speed link_speed;
248 /* is Link Status Event notification to SW enabled */
255 /* 1st byte: module identifier */
256 #define I40E_MODULE_TYPE_SFP 0x03
257 #define I40E_MODULE_TYPE_QSFP 0x0D
258 /* 2nd byte: ethernet compliance codes for 10/40G */
259 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
260 #define I40E_MODULE_TYPE_40G_LR4 0x02
261 #define I40E_MODULE_TYPE_40G_SR4 0x04
262 #define I40E_MODULE_TYPE_40G_CR4 0x08
263 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
264 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
265 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
266 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
267 /* 3rd byte: ethernet compliance codes for 1G */
268 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
269 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
270 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
271 #define I40E_MODULE_TYPE_1000BASE_T 0x08
274 struct i40e_phy_info {
275 struct i40e_link_status link_info;
276 struct i40e_link_status link_info_old;
278 enum i40e_media_type media_type;
279 /* all the phy types the NVM is capable of */
283 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
284 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
285 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
286 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
287 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
288 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
289 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
290 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
291 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
292 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
293 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
294 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
295 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
296 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
297 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
298 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
299 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
300 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
301 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
302 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
303 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
304 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
305 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
306 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
307 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
308 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
309 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
310 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
311 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
313 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
314 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
315 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
316 * a shift is needed to adjust for this with values larger than 31. The
317 * only affected values are I40E_PHY_TYPE_25GBASE_*.
319 #define I40E_PHY_TYPE_OFFSET 1
320 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
321 I40E_PHY_TYPE_OFFSET)
322 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
323 I40E_PHY_TYPE_OFFSET)
324 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
325 I40E_PHY_TYPE_OFFSET)
326 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
327 I40E_PHY_TYPE_OFFSET)
328 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
329 I40E_PHY_TYPE_OFFSET)
330 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
331 I40E_PHY_TYPE_OFFSET)
332 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
333 #define I40E_PHY_TYPE_OFFSET2 (-10)
334 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
335 I40E_PHY_TYPE_OFFSET2)
336 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
337 I40E_PHY_TYPE_OFFSET2)
338 #define I40E_HW_CAP_MAX_GPIO 30
339 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
340 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
342 enum i40e_acpi_programming_method {
343 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
344 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
347 #define I40E_WOL_SUPPORT_MASK 0x1
348 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
349 #define I40E_PROXY_SUPPORT_MASK 0x4
351 /* Capabilities of a PF or a VF or the whole device */
352 struct i40e_hw_capabilities {
354 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
355 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
356 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
358 /* Cloud filter modes:
359 * Mode1: Filter on L4 port only
360 * Mode2: Filter for non-tunneled traffic
361 * Mode3: Filter for tunnel traffic
363 #define I40E_CLOUD_FILTER_MODE1 0x6
364 #define I40E_CLOUD_FILTER_MODE2 0x7
365 #define I40E_CLOUD_FILTER_MODE3 0x8
366 #define I40E_SWITCH_MODE_MASK 0xF
369 u32 mng_protocols_over_mctp;
370 #define I40E_MNG_PROTOCOL_PLDM 0x2
371 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
372 #define I40E_MNG_PROTOCOL_NCSI 0x8
378 bool evb_802_1_qbg; /* Edge Virtual Bridging */
379 bool evb_802_1_qbh; /* Bridge Port Extension */
382 bool iscsi; /* Indicates iSCSI enabled */
386 #define I40E_FLEX10_MODE_UNKNOWN 0x0
387 #define I40E_FLEX10_MODE_DCC 0x1
388 #define I40E_FLEX10_MODE_DCI 0x2
391 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
392 #define I40E_FLEX10_STATUS_VC_MODE 0x2
394 bool sec_rev_disabled;
395 bool update_disabled;
396 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
397 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
403 u32 fd_filters_guaranteed;
404 u32 fd_filters_best_effort;
407 u32 rss_table_entry_width;
408 bool led[I40E_HW_CAP_MAX_GPIO];
409 bool sdp[I40E_HW_CAP_MAX_GPIO];
411 u32 num_flow_director_filters;
418 u32 num_msix_vectors;
419 u32 num_msix_vectors_vf;
428 bool apm_wol_support;
429 enum i40e_acpi_programming_method acpi_prog_method;
433 struct i40e_mac_info {
434 enum i40e_mac_type type;
436 u8 perm_addr[ETH_ALEN];
437 u8 san_addr[ETH_ALEN];
438 u8 port_addr[ETH_ALEN];
442 enum i40e_aq_resources_ids {
443 I40E_NVM_RESOURCE_ID = 1
446 enum i40e_aq_resource_access_type {
447 I40E_RESOURCE_READ = 1,
451 struct i40e_nvm_info {
452 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
453 u32 timeout; /* [ms] */
454 u16 sr_size; /* Shadow RAM size in words */
455 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
456 u16 version; /* NVM package version */
457 u32 eetrack; /* NVM data version */
458 u32 oem_ver; /* OEM version info */
461 /* definitions used in NVM update support */
463 enum i40e_nvmupd_cmd {
465 I40E_NVMUPD_READ_CON,
466 I40E_NVMUPD_READ_SNT,
467 I40E_NVMUPD_READ_LCB,
469 I40E_NVMUPD_WRITE_ERA,
470 I40E_NVMUPD_WRITE_CON,
471 I40E_NVMUPD_WRITE_SNT,
472 I40E_NVMUPD_WRITE_LCB,
473 I40E_NVMUPD_WRITE_SA,
474 I40E_NVMUPD_CSUM_CON,
476 I40E_NVMUPD_CSUM_LCB,
479 I40E_NVMUPD_GET_AQ_RESULT,
480 I40E_NVMUPD_GET_AQ_EVENT,
481 I40E_NVMUPD_FEATURES,
484 enum i40e_nvmupd_state {
485 I40E_NVMUPD_STATE_INIT,
486 I40E_NVMUPD_STATE_READING,
487 I40E_NVMUPD_STATE_WRITING,
488 I40E_NVMUPD_STATE_INIT_WAIT,
489 I40E_NVMUPD_STATE_WRITE_WAIT,
490 I40E_NVMUPD_STATE_ERROR
493 /* nvm_access definition and its masks/shifts need to be accessible to
494 * application, core driver, and shared code. Where is the right file?
496 #define I40E_NVM_READ 0xB
497 #define I40E_NVM_WRITE 0xC
499 #define I40E_NVM_MOD_PNT_MASK 0xFF
501 #define I40E_NVM_TRANS_SHIFT 8
502 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
503 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
504 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
505 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
506 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
507 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
508 #define I40E_NVM_CON 0x0
509 #define I40E_NVM_SNT 0x1
510 #define I40E_NVM_LCB 0x2
511 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
512 #define I40E_NVM_ERA 0x4
513 #define I40E_NVM_CSUM 0x8
514 #define I40E_NVM_AQE 0xe
515 #define I40E_NVM_EXEC 0xf
517 #define I40E_NVM_EXEC_GET_AQ_RESULT 0x0
518 #define I40E_NVM_EXEC_FEATURES 0xe
519 #define I40E_NVM_EXEC_STATUS 0xf
521 #define I40E_NVM_ADAPT_SHIFT 16
522 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
524 #define I40E_NVMUPD_MAX_DATA 4096
525 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
527 struct i40e_nvm_access {
530 u32 offset; /* in bytes */
531 u32 data_size; /* in bytes */
535 /* NVMUpdate features API */
536 #define I40E_NVMUPD_FEATURES_API_VER_MAJOR 0
537 #define I40E_NVMUPD_FEATURES_API_VER_MINOR 14
538 #define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12
540 #define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0)
542 struct i40e_nvmupd_features {
546 u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
549 /* (Q)SFP module access definitions */
550 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
551 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
552 #define I40E_MODULE_TYPE_ADDR 0x00
553 #define I40E_MODULE_REVISION_ADDR 0x01
554 #define I40E_MODULE_SFF_8472_COMP 0x5E
555 #define I40E_MODULE_SFF_8472_SWAP 0x5C
556 #define I40E_MODULE_SFF_ADDR_MODE 0x04
557 #define I40E_MODULE_SFF_DIAG_CAPAB 0x40
558 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
559 #define I40E_MODULE_TYPE_QSFP28 0x11
560 #define I40E_MODULE_QSFP_MAX_LEN 640
564 i40e_bus_type_unknown = 0,
567 i40e_bus_type_pci_express,
568 i40e_bus_type_reserved
572 enum i40e_bus_speed {
573 i40e_bus_speed_unknown = 0,
574 i40e_bus_speed_33 = 33,
575 i40e_bus_speed_66 = 66,
576 i40e_bus_speed_100 = 100,
577 i40e_bus_speed_120 = 120,
578 i40e_bus_speed_133 = 133,
579 i40e_bus_speed_2500 = 2500,
580 i40e_bus_speed_5000 = 5000,
581 i40e_bus_speed_8000 = 8000,
582 i40e_bus_speed_reserved
586 enum i40e_bus_width {
587 i40e_bus_width_unknown = 0,
588 i40e_bus_width_pcie_x1 = 1,
589 i40e_bus_width_pcie_x2 = 2,
590 i40e_bus_width_pcie_x4 = 4,
591 i40e_bus_width_pcie_x8 = 8,
592 i40e_bus_width_32 = 32,
593 i40e_bus_width_64 = 64,
594 i40e_bus_width_reserved
598 struct i40e_bus_info {
599 enum i40e_bus_speed speed;
600 enum i40e_bus_width width;
601 enum i40e_bus_type type;
609 /* Flow control (FC) parameters */
610 struct i40e_fc_info {
611 enum i40e_fc_mode current_mode; /* FC mode in effect */
612 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
615 #define I40E_MAX_TRAFFIC_CLASS 8
616 #define I40E_MAX_USER_PRIORITY 8
617 #define I40E_DCBX_MAX_APPS 32
618 #define I40E_LLDPDU_SIZE 1500
619 #define I40E_TLV_STATUS_OPER 0x1
620 #define I40E_TLV_STATUS_SYNC 0x2
621 #define I40E_TLV_STATUS_ERR 0x4
622 #define I40E_CEE_OPER_MAX_APPS 3
623 #define I40E_APP_PROTOID_FCOE 0x8906
624 #define I40E_APP_PROTOID_ISCSI 0x0cbc
625 #define I40E_APP_PROTOID_FIP 0x8914
626 #define I40E_APP_SEL_ETHTYPE 0x1
627 #define I40E_APP_SEL_TCPIP 0x2
628 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
629 #define I40E_CEE_APP_SEL_TCPIP 0x1
631 /* CEE or IEEE 802.1Qaz ETS Configuration data */
632 struct i40e_dcb_ets_config {
636 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
637 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
638 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
641 /* CEE or IEEE 802.1Qaz PFC Configuration data */
642 struct i40e_dcb_pfc_config {
649 /* CEE or IEEE 802.1Qaz Application Priority data */
650 struct i40e_dcb_app_priority_table {
656 struct i40e_dcbx_config {
658 #define I40E_DCBX_MODE_CEE 0x1
659 #define I40E_DCBX_MODE_IEEE 0x2
661 #define I40E_DCBX_APPS_NON_WILLING 0x1
663 u32 tlv_status; /* CEE mode TLV status */
664 struct i40e_dcb_ets_config etscfg;
665 struct i40e_dcb_ets_config etsrec;
666 struct i40e_dcb_pfc_config pfc;
667 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
670 /* Port hardware description */
675 /* subsystem structs */
676 struct i40e_phy_info phy;
677 struct i40e_mac_info mac;
678 struct i40e_bus_info bus;
679 struct i40e_nvm_info nvm;
680 struct i40e_fc_info fc;
682 /* switch device is used to get link status when i40e is in ipn3ke */
683 struct rte_eth_dev *switch_dev;
688 u16 subsystem_device_id;
689 u16 subsystem_vendor_id;
692 bool adapter_stopped;
695 /* capabilities for entire device and PCI func */
696 struct i40e_hw_capabilities dev_caps;
697 struct i40e_hw_capabilities func_caps;
699 /* Flow Director shared filter space */
700 u16 fdir_shared_filter_count;
702 /* device profile info */
706 /* for multi-function MACs */
711 /* Closest numa node to the device */
714 /* Admin Queue info */
715 struct i40e_adminq_info aq;
717 /* state of nvm update process */
718 enum i40e_nvmupd_state nvmupd_state;
719 struct i40e_aq_desc nvm_wb_desc;
720 struct i40e_aq_desc nvm_aq_event_desc;
721 struct i40e_virt_mem nvm_buff;
722 bool nvm_release_on_done;
726 struct i40e_hmc_info hmc; /* HMC info struct */
728 /* LLDP/DCBX Status */
732 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
733 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
734 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
736 /* WoL and proxy support */
737 u16 num_wol_proxy_filters;
738 u16 wol_proxy_vsi_seid;
740 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
741 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
742 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
743 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
744 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
745 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
748 /* Used in set switch config AQ command */
753 /* NVMUpdate features */
754 struct i40e_nvmupd_features nvmupd_features;
761 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
763 return (hw->mac.type == I40E_MAC_VF ||
764 hw->mac.type == I40E_MAC_X722_VF);
767 struct i40e_driver_version {
772 u8 driver_string[32];
776 union i40e_16byte_rx_desc {
778 __le64 pkt_addr; /* Packet buffer address */
779 __le64 hdr_addr; /* Header buffer address */
785 __le16 mirroring_status;
791 __le32 rss; /* RSS Hash */
792 __le32 fd_id; /* Flow director filter id */
793 __le32 fcoe_param; /* FCoE DDP Context id */
797 /* ext status/error/pktype/length */
798 __le64 status_error_len;
800 } wb; /* writeback */
803 union i40e_32byte_rx_desc {
805 __le64 pkt_addr; /* Packet buffer address */
806 __le64 hdr_addr; /* Header buffer address */
807 /* bit 0 of hdr_buffer_addr is DD bit */
815 __le16 mirroring_status;
821 __le32 rss; /* RSS Hash */
822 __le32 fcoe_param; /* FCoE DDP Context id */
823 /* Flow director filter id in case of
824 * Programming status desc WB
830 /* status/error/pktype/length */
831 __le64 status_error_len;
834 __le16 ext_status; /* extended status */
841 __le32 flex_bytes_lo;
845 __le32 flex_bytes_hi;
849 } wb; /* writeback */
852 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
853 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
854 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
855 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
856 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
857 I40E_RXD_QW0_FCOEINDX_SHIFT)
859 enum i40e_rx_desc_status_bits {
860 /* Note: These are predefined bit offsets */
861 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
862 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
863 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
864 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
865 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
866 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
867 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
868 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
870 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
871 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
872 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
873 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
874 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
875 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
876 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
877 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
880 #define I40E_RXD_QW1_STATUS_SHIFT 0
881 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
882 I40E_RXD_QW1_STATUS_SHIFT)
884 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
885 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
886 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
888 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
889 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
891 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
892 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
893 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
895 enum i40e_rx_desc_fltstat_values {
896 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
897 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
898 I40E_RX_DESC_FLTSTAT_RSV = 2,
899 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
902 #define I40E_RXD_PACKET_TYPE_UNICAST 0
903 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
904 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
905 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
907 #define I40E_RXD_QW1_ERROR_SHIFT 19
908 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
910 enum i40e_rx_desc_error_bits {
911 /* Note: These are predefined bit offsets */
912 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
913 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
914 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
915 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
916 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
917 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
918 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
919 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
920 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
923 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
924 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
925 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
926 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
927 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
928 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
931 #define I40E_RXD_QW1_PTYPE_SHIFT 30
932 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
934 /* Packet type non-ip values */
935 enum i40e_rx_l2_ptype {
936 I40E_RX_PTYPE_L2_RESERVED = 0,
937 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
938 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
939 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
940 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
941 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
942 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
943 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
944 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
945 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
946 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
947 I40E_RX_PTYPE_L2_ARP = 11,
948 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
949 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
950 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
951 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
952 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
953 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
954 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
955 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
956 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
957 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
958 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
959 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
960 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
961 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
964 struct i40e_rx_ptype_decoded {
971 u32 tunnel_end_prot:2;
972 u32 tunnel_end_frag:1;
977 enum i40e_rx_ptype_outer_ip {
978 I40E_RX_PTYPE_OUTER_L2 = 0,
979 I40E_RX_PTYPE_OUTER_IP = 1
982 enum i40e_rx_ptype_outer_ip_ver {
983 I40E_RX_PTYPE_OUTER_NONE = 0,
984 I40E_RX_PTYPE_OUTER_IPV4 = 0,
985 I40E_RX_PTYPE_OUTER_IPV6 = 1
988 enum i40e_rx_ptype_outer_fragmented {
989 I40E_RX_PTYPE_NOT_FRAG = 0,
990 I40E_RX_PTYPE_FRAG = 1
993 enum i40e_rx_ptype_tunnel_type {
994 I40E_RX_PTYPE_TUNNEL_NONE = 0,
995 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
996 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
997 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
998 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
1001 enum i40e_rx_ptype_tunnel_end_prot {
1002 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
1003 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
1004 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
1007 enum i40e_rx_ptype_inner_prot {
1008 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
1009 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
1010 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
1011 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
1012 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
1013 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
1016 enum i40e_rx_ptype_payload_layer {
1017 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
1018 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
1019 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
1020 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
1023 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
1024 #define I40E_RX_PTYPE_SHIFT 56
1026 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
1027 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
1028 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1030 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
1031 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
1032 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1034 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
1035 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1037 #define I40E_RXD_QW1_NEXTP_SHIFT 38
1038 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1040 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
1041 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
1042 I40E_RXD_QW2_EXT_STATUS_SHIFT)
1044 enum i40e_rx_desc_ext_status_bits {
1045 /* Note: These are predefined bit offsets */
1046 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
1047 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1048 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1049 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1050 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1051 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1052 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1055 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1056 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1058 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1059 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1061 enum i40e_rx_desc_pe_status_bits {
1062 /* Note: These are predefined bit offsets */
1063 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1064 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1065 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1066 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1067 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1068 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1069 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1070 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1071 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1074 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1075 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1077 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1078 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1079 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1081 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1082 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1083 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1085 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1086 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1087 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1089 enum i40e_rx_prog_status_desc_status_bits {
1090 /* Note: These are predefined bit offsets */
1091 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1092 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1095 enum i40e_rx_prog_status_desc_prog_id_masks {
1096 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1097 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1098 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1101 enum i40e_rx_prog_status_desc_error_bits {
1102 /* Note: These are predefined bit offsets */
1103 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1104 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1105 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1106 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1109 #define I40E_TWO_BIT_MASK 0x3
1110 #define I40E_THREE_BIT_MASK 0x7
1111 #define I40E_FOUR_BIT_MASK 0xF
1112 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1115 struct i40e_tx_desc {
1116 __le64 buffer_addr; /* Address of descriptor's data buf */
1117 __le64 cmd_type_offset_bsz;
1120 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1121 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1123 enum i40e_tx_desc_dtype_value {
1124 I40E_TX_DESC_DTYPE_DATA = 0x0,
1125 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1126 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1127 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1128 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1129 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1130 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1131 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1132 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1133 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1136 #define I40E_TXD_QW1_CMD_SHIFT 4
1137 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1139 enum i40e_tx_desc_cmd_bits {
1140 I40E_TX_DESC_CMD_EOP = 0x0001,
1141 I40E_TX_DESC_CMD_RS = 0x0002,
1142 I40E_TX_DESC_CMD_ICRC = 0x0004,
1143 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1144 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1145 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1146 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1147 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1148 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1149 I40E_TX_DESC_CMD_FCOET = 0x0080,
1150 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1151 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1152 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1153 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1154 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1155 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1156 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1157 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1160 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1161 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1162 I40E_TXD_QW1_OFFSET_SHIFT)
1164 enum i40e_tx_desc_length_fields {
1165 /* Note: These are predefined bit offsets */
1166 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1167 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1168 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1171 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1172 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1173 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1174 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1176 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1177 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1178 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1180 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1181 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1183 /* Context descriptors */
1184 struct i40e_tx_context_desc {
1185 __le32 tunneling_params;
1188 __le64 type_cmd_tso_mss;
1191 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1192 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1194 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1195 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1197 enum i40e_tx_ctx_desc_cmd_bits {
1198 I40E_TX_CTX_DESC_TSO = 0x01,
1199 I40E_TX_CTX_DESC_TSYN = 0x02,
1200 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1201 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1202 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1203 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1204 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1205 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1206 I40E_TX_CTX_DESC_SWPE = 0x40
1209 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1210 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1211 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1213 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1214 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1215 I40E_TXD_CTX_QW1_MSS_SHIFT)
1217 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1218 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1220 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1221 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1222 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1224 enum i40e_tx_ctx_desc_eipt_offload {
1225 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1226 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1227 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1228 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1231 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1232 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1233 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1235 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1236 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1238 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1239 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1241 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1242 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1244 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1246 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1247 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1248 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1250 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1251 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1252 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1254 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1255 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1256 struct i40e_nop_desc {
1261 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1262 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1264 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1265 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1267 enum i40e_tx_nop_desc_cmd_bits {
1268 /* Note: These are predefined bit offsets */
1269 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1270 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1271 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1274 struct i40e_filter_program_desc {
1275 __le32 qindex_flex_ptype_vsi;
1277 __le32 dtype_cmd_cntindex;
1280 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1281 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1282 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1283 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1284 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1285 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1286 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1287 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1288 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1290 /* Packet Classifier Types for filters */
1291 enum i40e_filter_pctype {
1292 /* Note: Values 0-28 are reserved for future use.
1293 * Value 29, 30, 32 are not supported on XL710 and X710.
1295 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1296 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1297 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1298 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1299 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1300 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1301 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1302 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1303 /* Note: Values 37-38 are reserved for future use.
1304 * Value 39, 40, 42 are not supported on XL710 and X710.
1306 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1307 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1308 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1309 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1310 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1311 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1312 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1313 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1314 /* Note: Value 47 is reserved for future use */
1315 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1316 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1317 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1318 /* Note: Values 51-62 are reserved for future use */
1319 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1322 enum i40e_filter_program_desc_dest {
1323 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1324 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1325 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1328 enum i40e_filter_program_desc_fd_status {
1329 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1330 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1331 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1332 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1335 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1336 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1337 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1339 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1340 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1342 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1343 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1344 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1346 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1347 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1349 enum i40e_filter_program_desc_pcmd {
1350 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1351 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1354 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1355 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1357 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1358 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1360 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1361 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1362 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1363 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1365 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1366 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1367 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1369 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1370 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1371 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1373 enum i40e_filter_type {
1374 I40E_FLOW_DIRECTOR_FLTR = 0,
1375 I40E_PE_QUAD_HASH_FLTR = 1,
1376 I40E_ETHERTYPE_FLTR,
1382 struct i40e_vsi_context {
1387 u16 vsis_unallocated;
1392 struct i40e_aqc_vsi_properties_data info;
1395 struct i40e_veb_context {
1400 u16 vebs_unallocated;
1402 struct i40e_aqc_get_veb_parameters_completion info;
1405 /* Statistics collected by each port, VSI, VEB, and S-channel */
1406 struct i40e_eth_stats {
1407 u64 rx_bytes; /* gorc */
1408 u64 rx_unicast; /* uprc */
1409 u64 rx_multicast; /* mprc */
1410 u64 rx_broadcast; /* bprc */
1411 u64 rx_discards; /* rdpc */
1412 u64 rx_unknown_protocol; /* rupp */
1413 u64 tx_bytes; /* gotc */
1414 u64 tx_unicast; /* uptc */
1415 u64 tx_multicast; /* mptc */
1416 u64 tx_broadcast; /* bptc */
1417 u64 tx_discards; /* tdpc */
1418 u64 tx_errors; /* tepc */
1421 /* Statistics collected per VEB per TC */
1422 struct i40e_veb_tc_stats {
1423 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1424 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1425 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1426 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1429 /* Statistics collected per function for FCoE */
1430 struct i40e_fcoe_stats {
1431 u64 rx_fcoe_packets; /* fcoeprc */
1432 u64 rx_fcoe_dwords; /* focedwrc */
1433 u64 rx_fcoe_dropped; /* fcoerpdc */
1434 u64 tx_fcoe_packets; /* fcoeptc */
1435 u64 tx_fcoe_dwords; /* focedwtc */
1436 u64 fcoe_bad_fccrc; /* fcoecrc */
1437 u64 fcoe_last_error; /* fcoelast */
1438 u64 fcoe_ddp_count; /* fcoeddpc */
1441 /* offset to per function FCoE statistics block */
1442 #define I40E_FCOE_VF_STAT_OFFSET 0
1443 #define I40E_FCOE_PF_STAT_OFFSET 128
1444 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1446 /* Statistics collected by the MAC */
1447 struct i40e_hw_port_stats {
1448 /* eth stats collected by the port */
1449 struct i40e_eth_stats eth;
1451 /* additional port specific stats */
1452 u64 tx_dropped_link_down; /* tdold */
1453 u64 crc_errors; /* crcerrs */
1454 u64 illegal_bytes; /* illerrc */
1455 u64 error_bytes; /* errbc */
1456 u64 mac_local_faults; /* mlfc */
1457 u64 mac_remote_faults; /* mrfc */
1458 u64 rx_length_errors; /* rlec */
1459 u64 link_xon_rx; /* lxonrxc */
1460 u64 link_xoff_rx; /* lxoffrxc */
1461 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1462 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1463 u64 link_xon_tx; /* lxontxc */
1464 u64 link_xoff_tx; /* lxofftxc */
1465 u64 priority_xon_tx[8]; /* pxontxc[8] */
1466 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1467 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1468 u64 rx_size_64; /* prc64 */
1469 u64 rx_size_127; /* prc127 */
1470 u64 rx_size_255; /* prc255 */
1471 u64 rx_size_511; /* prc511 */
1472 u64 rx_size_1023; /* prc1023 */
1473 u64 rx_size_1522; /* prc1522 */
1474 u64 rx_size_big; /* prc9522 */
1475 u64 rx_undersize; /* ruc */
1476 u64 rx_fragments; /* rfc */
1477 u64 rx_oversize; /* roc */
1478 u64 rx_jabber; /* rjc */
1479 u64 tx_size_64; /* ptc64 */
1480 u64 tx_size_127; /* ptc127 */
1481 u64 tx_size_255; /* ptc255 */
1482 u64 tx_size_511; /* ptc511 */
1483 u64 tx_size_1023; /* ptc1023 */
1484 u64 tx_size_1522; /* ptc1522 */
1485 u64 tx_size_big; /* ptc9522 */
1486 u64 mac_short_packet_dropped; /* mspdc */
1487 u64 checksum_error; /* xec */
1488 /* flow director stats */
1491 u64 fd_atr_tunnel_match;
1497 u64 tx_lpi_count; /* etlpic */
1498 u64 rx_lpi_count; /* erlpic */
1501 /* Checksum and Shadow RAM pointers */
1502 #define I40E_SR_NVM_CONTROL_WORD 0x00
1503 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1504 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1505 #define I40E_SR_OPTION_ROM_PTR 0x05
1506 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1507 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1508 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1509 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1510 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1511 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1512 #define I40E_SR_PE_IMAGE_PTR 0x0C
1513 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1514 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1515 #define I40E_EMP_MODULE_PTR 0x0F
1516 #define I40E_SR_EMP_MODULE_PTR 0x48
1517 #define I40E_SR_PBA_FLAGS 0x15
1518 #define I40E_SR_PBA_BLOCK_PTR 0x16
1519 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1520 #define I40E_NVM_OEM_VER_OFF 0x83
1521 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1522 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1523 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1524 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1525 #define I40E_SR_NVM_MAP_VERSION 0x29
1526 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1527 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1528 #define I40E_SR_NVM_EETRACK_LO 0x2D
1529 #define I40E_SR_NVM_EETRACK_HI 0x2E
1530 #define I40E_SR_VPD_PTR 0x2F
1531 #define I40E_SR_PXE_SETUP_PTR 0x30
1532 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1533 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1534 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1535 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1536 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1537 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1538 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1539 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1540 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1541 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1542 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1543 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1544 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1545 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1546 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1547 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1548 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1549 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1550 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1552 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1553 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1554 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1555 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1556 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1557 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
1558 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
1559 #define I40E_PTR_TYPE BIT(15)
1560 #define I40E_SR_OCP_CFG_WORD0 0x2B
1561 #define I40E_SR_OCP_ENABLED BIT(15)
1563 /* Shadow RAM related */
1564 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1565 #define I40E_SR_BUF_ALIGNMENT 4096
1566 #define I40E_SR_WORDS_IN_1KB 512
1567 /* Checksum should be calculated such that after adding all the words,
1568 * including the checksum word itself, the sum should be 0xBABA.
1570 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1572 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1574 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1576 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1577 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1578 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1579 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1580 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1581 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1582 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1583 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1584 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1585 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1586 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1587 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1588 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1589 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1592 /* FCoE DIF/DIX Context descriptor */
1593 struct i40e_fcoe_difdix_context_desc {
1594 __le64 flags_buff0_buff1_ref;
1595 __le64 difapp_msk_bias;
1598 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1599 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1600 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1602 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1604 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1606 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1608 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1610 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1612 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1614 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1616 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1618 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1620 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1622 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1624 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1626 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1628 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1630 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1632 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1634 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1636 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1638 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1640 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1642 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1644 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1647 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1648 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1649 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1651 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1652 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1653 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1655 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1656 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1657 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1659 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1660 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1661 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1663 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1664 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1665 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1667 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1668 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1669 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1671 /* FCoE DIF/DIX Buffers descriptor */
1672 struct i40e_fcoe_difdix_buffers_desc {
1677 /* FCoE DDP Context descriptor */
1678 struct i40e_fcoe_ddp_context_desc {
1680 __le64 type_cmd_foff_lsize;
1683 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1684 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1685 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1687 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1688 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1689 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1691 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1692 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1693 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1694 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1695 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1696 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1697 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1700 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1701 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1702 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1704 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1705 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1706 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1708 /* FCoE DDP/DWO Queue Context descriptor */
1709 struct i40e_fcoe_queue_context_desc {
1710 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1711 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1714 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1715 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1716 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1718 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1719 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1720 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1722 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1723 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1724 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1726 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1727 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1728 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1730 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1731 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1732 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1735 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1736 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1737 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1739 /* FCoE DDP/DWO Filter Context descriptor */
1740 struct i40e_fcoe_filter_context_desc {
1744 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1745 __le16 rsvd_dmaindx;
1747 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1748 __le64 flags_rsvd_lanq;
1751 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1752 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1753 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1755 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1756 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1757 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1758 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1759 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1760 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1761 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1764 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1765 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1766 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1768 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1769 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1770 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1772 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1773 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1774 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1776 enum i40e_switch_element_types {
1777 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1778 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1779 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1780 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1781 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1782 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1783 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1784 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1785 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1788 /* Supported EtherType filters */
1789 enum i40e_ether_type_index {
1790 I40E_ETHER_TYPE_1588 = 0,
1791 I40E_ETHER_TYPE_FIP = 1,
1792 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1793 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1794 I40E_ETHER_TYPE_LLDP = 4,
1795 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1796 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1797 I40E_ETHER_TYPE_QCN_CNM = 7,
1798 I40E_ETHER_TYPE_8021X = 8,
1799 I40E_ETHER_TYPE_ARP = 9,
1800 I40E_ETHER_TYPE_RSV1 = 10,
1801 I40E_ETHER_TYPE_RSV2 = 11,
1804 /* Filter context base size is 1K */
1805 #define I40E_HASH_FILTER_BASE_SIZE 1024
1806 /* Supported Hash filter values */
1807 enum i40e_hash_filter_size {
1808 I40E_HASH_FILTER_SIZE_1K = 0,
1809 I40E_HASH_FILTER_SIZE_2K = 1,
1810 I40E_HASH_FILTER_SIZE_4K = 2,
1811 I40E_HASH_FILTER_SIZE_8K = 3,
1812 I40E_HASH_FILTER_SIZE_16K = 4,
1813 I40E_HASH_FILTER_SIZE_32K = 5,
1814 I40E_HASH_FILTER_SIZE_64K = 6,
1815 I40E_HASH_FILTER_SIZE_128K = 7,
1816 I40E_HASH_FILTER_SIZE_256K = 8,
1817 I40E_HASH_FILTER_SIZE_512K = 9,
1818 I40E_HASH_FILTER_SIZE_1M = 10,
1821 /* DMA context base size is 0.5K */
1822 #define I40E_DMA_CNTX_BASE_SIZE 512
1823 /* Supported DMA context values */
1824 enum i40e_dma_cntx_size {
1825 I40E_DMA_CNTX_SIZE_512 = 0,
1826 I40E_DMA_CNTX_SIZE_1K = 1,
1827 I40E_DMA_CNTX_SIZE_2K = 2,
1828 I40E_DMA_CNTX_SIZE_4K = 3,
1829 I40E_DMA_CNTX_SIZE_8K = 4,
1830 I40E_DMA_CNTX_SIZE_16K = 5,
1831 I40E_DMA_CNTX_SIZE_32K = 6,
1832 I40E_DMA_CNTX_SIZE_64K = 7,
1833 I40E_DMA_CNTX_SIZE_128K = 8,
1834 I40E_DMA_CNTX_SIZE_256K = 9,
1837 /* Supported Hash look up table (LUT) sizes */
1838 enum i40e_hash_lut_size {
1839 I40E_HASH_LUT_SIZE_128 = 0,
1840 I40E_HASH_LUT_SIZE_512 = 1,
1843 /* Structure to hold a per PF filter control settings */
1844 struct i40e_filter_control_settings {
1845 /* number of PE Quad Hash filter buckets */
1846 enum i40e_hash_filter_size pe_filt_num;
1847 /* number of PE Quad Hash contexts */
1848 enum i40e_dma_cntx_size pe_cntx_num;
1849 /* number of FCoE filter buckets */
1850 enum i40e_hash_filter_size fcoe_filt_num;
1851 /* number of FCoE DDP contexts */
1852 enum i40e_dma_cntx_size fcoe_cntx_num;
1853 /* size of the Hash LUT */
1854 enum i40e_hash_lut_size hash_lut_size;
1855 /* enable FDIR filters for PF and its VFs */
1857 /* enable Ethertype filters for PF and its VFs */
1858 bool enable_ethtype;
1859 /* enable MAC/VLAN filters for PF and its VFs */
1860 bool enable_macvlan;
1863 /* Structure to hold device level control filter counts */
1864 struct i40e_control_filter_stats {
1865 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1866 u16 etype_used; /* Used perfect EtherType filters */
1867 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1868 u16 etype_free; /* Un-used perfect EtherType filters */
1871 enum i40e_reset_type {
1873 I40E_RESET_CORER = 1,
1874 I40E_RESET_GLOBR = 2,
1875 I40E_RESET_EMPR = 3,
1878 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1879 #define I40E_NVM_LLDP_CFG_PTR 0x06
1880 #define I40E_SR_LLDP_CFG_PTR 0x31
1881 struct i40e_lldp_variables {
1891 /* Offsets into Alternate Ram */
1892 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1893 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1894 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1895 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1896 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1897 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1899 /* Alternate Ram Bandwidth Masks */
1900 #define I40E_ALT_BW_VALUE_MASK 0xFF
1901 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1902 #define I40E_ALT_BW_VALID_MASK 0x80000000
1904 /* RSS Hash Table Size */
1905 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1907 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1908 #define I40E_L3_SRC_SHIFT 47
1909 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1910 #define I40E_L3_V6_SRC_SHIFT 43
1911 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1912 #define I40E_L3_DST_SHIFT 35
1913 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1914 #define I40E_L3_V6_DST_SHIFT 35
1915 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1916 #define I40E_L4_SRC_SHIFT 34
1917 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1918 #define I40E_L4_DST_SHIFT 33
1919 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1920 #define I40E_VERIFY_TAG_SHIFT 31
1921 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1923 #define I40E_FLEX_50_SHIFT 13
1924 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1925 #define I40E_FLEX_51_SHIFT 12
1926 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1927 #define I40E_FLEX_52_SHIFT 11
1928 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1929 #define I40E_FLEX_53_SHIFT 10
1930 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1931 #define I40E_FLEX_54_SHIFT 9
1932 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1933 #define I40E_FLEX_55_SHIFT 8
1934 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1935 #define I40E_FLEX_56_SHIFT 7
1936 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1937 #define I40E_FLEX_57_SHIFT 6
1938 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1940 /* Version format for Dynamic Device Personalization(DDP) */
1941 struct i40e_ddp_version {
1948 #define I40E_DDP_NAME_SIZE 32
1950 /* Package header */
1951 struct i40e_package_header {
1952 struct i40e_ddp_version version;
1954 u32 segment_offset[1];
1957 /* Generic segment header */
1958 struct i40e_generic_seg_header {
1959 #define SEGMENT_TYPE_METADATA 0x00000001
1960 #define SEGMENT_TYPE_NOTES 0x00000002
1961 #define SEGMENT_TYPE_I40E 0x00000011
1962 #define SEGMENT_TYPE_X722 0x00000012
1964 struct i40e_ddp_version version;
1966 char name[I40E_DDP_NAME_SIZE];
1969 struct i40e_metadata_segment {
1970 struct i40e_generic_seg_header header;
1971 struct i40e_ddp_version version;
1972 #define I40E_DDP_TRACKID_RDONLY 0
1973 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
1975 char name[I40E_DDP_NAME_SIZE];
1978 struct i40e_device_id_entry {
1980 u32 sub_vendor_dev_id;
1983 struct i40e_profile_segment {
1984 struct i40e_generic_seg_header header;
1985 struct i40e_ddp_version version;
1986 char name[I40E_DDP_NAME_SIZE];
1987 u32 device_table_count;
1988 struct i40e_device_id_entry device_table[1];
1991 struct i40e_section_table {
1993 u32 section_offset[1];
1996 struct i40e_profile_section_header {
2000 #define SECTION_TYPE_INFO 0x00000010
2001 #define SECTION_TYPE_MMIO 0x00000800
2002 #define SECTION_TYPE_RB_MMIO 0x00001800
2003 #define SECTION_TYPE_AQ 0x00000801
2004 #define SECTION_TYPE_RB_AQ 0x00001801
2005 #define SECTION_TYPE_NOTE 0x80000000
2006 #define SECTION_TYPE_NAME 0x80000001
2007 #define SECTION_TYPE_PROTO 0x80000002
2008 #define SECTION_TYPE_PCTYPE 0x80000003
2009 #define SECTION_TYPE_PTYPE 0x80000004
2016 struct i40e_profile_tlv_section_record {
2023 /* Generic AQ section in proflie */
2024 struct i40e_profile_aq_section {
2032 struct i40e_profile_info {
2034 struct i40e_ddp_version version;
2036 #define I40E_DDP_ADD_TRACKID 0x01
2037 #define I40E_DDP_REMOVE_TRACKID 0x02
2039 u8 name[I40E_DDP_NAME_SIZE];
2041 #endif /* _I40E_TYPE_H_ */