drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 /* Memory types */
 161 enum i40e_memset_type {
 162         I40E_NONDMA_MEM = 0,
 163         I40E_DMA_MEM
 164 };
 165
 166 /* Memcpy types */
 167 enum i40e_memcpy_type {
 168         I40E_NONDMA_TO_NONDMA = 0,
 169         I40E_NONDMA_TO_DMA,
 170         I40E_DMA_TO_DMA,
 171         I40E_DMA_TO_NONDMA
 172 };
 173
 174
 175 #ifdef X722_SUPPORT
 176 #define I40E_FW_API_VERSION_MINOR_X722  0x0003
 177 #endif
 178 #define I40E_FW_API_VERSION_MINOR_X710  0x0004
 179
 180
 181 /* These are structs for managing the hardware information and the operations.
 182  * The structures of function pointers are filled out at init time when we
 183  * know for sure exactly which hardware we're working with.  This gives us the
 184  * flexibility of using the same main driver code but adapting to slightly
 185  * different hardware needs as new parts are developed.  For this architecture,
 186  * the Firmware and AdminQ are intended to insulate the driver from most of the
 187  * future changes, but these structures will also do part of the job.
 188  */
 189 enum i40e_mac_type {
 190         I40E_MAC_UNKNOWN = 0,
 191         I40E_MAC_X710,
 192         I40E_MAC_XL710,
 193         I40E_MAC_VF,
 194 #ifdef X722_SUPPORT
 195         I40E_MAC_X722,
 196         I40E_MAC_X722_VF,
 197 #endif
 198         I40E_MAC_GENERIC,
 199 };
 200
 201 enum i40e_media_type {
 202         I40E_MEDIA_TYPE_UNKNOWN = 0,
 203         I40E_MEDIA_TYPE_FIBER,
 204         I40E_MEDIA_TYPE_BASET,
 205         I40E_MEDIA_TYPE_BACKPLANE,
 206         I40E_MEDIA_TYPE_CX4,
 207         I40E_MEDIA_TYPE_DA,
 208         I40E_MEDIA_TYPE_VIRTUAL
 209 };
 210
 211 enum i40e_fc_mode {
 212         I40E_FC_NONE = 0,
 213         I40E_FC_RX_PAUSE,
 214         I40E_FC_TX_PAUSE,
 215         I40E_FC_FULL,
 216         I40E_FC_PFC,
 217         I40E_FC_DEFAULT
 218 };
 219
 220 enum i40e_set_fc_aq_failures {
 221         I40E_SET_FC_AQ_FAIL_NONE = 0,
 222         I40E_SET_FC_AQ_FAIL_GET = 1,
 223         I40E_SET_FC_AQ_FAIL_SET = 2,
 224         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 225         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 226 };
 227
 228 enum i40e_vsi_type {
 229         I40E_VSI_MAIN   = 0,
 230         I40E_VSI_VMDQ1  = 1,
 231         I40E_VSI_VMDQ2  = 2,
 232         I40E_VSI_CTRL   = 3,
 233         I40E_VSI_FCOE   = 4,
 234         I40E_VSI_MIRROR = 5,
 235         I40E_VSI_SRIOV  = 6,
 236         I40E_VSI_FDIR   = 7,
 237         I40E_VSI_TYPE_UNKNOWN
 238 };
 239
 240 enum i40e_queue_type {
 241         I40E_QUEUE_TYPE_RX = 0,
 242         I40E_QUEUE_TYPE_TX,
 243         I40E_QUEUE_TYPE_PE_CEQ,
 244         I40E_QUEUE_TYPE_UNKNOWN
 245 };
 246
 247 struct i40e_link_status {
 248         enum i40e_aq_phy_type phy_type;
 249         enum i40e_aq_link_speed link_speed;
 250         u8 link_info;
 251         u8 an_info;
 252         u8 ext_info;
 253         u8 loopback;
 254         /* is Link Status Event notification to SW enabled */
 255         bool lse_enable;
 256         u16 max_frame_size;
 257         bool crc_enable;
 258         u8 pacing;
 259         u8 requested_speeds;
 260         u8 module_type[3];
 261         /* 1st byte: module identifier */
 262 #define I40E_MODULE_TYPE_SFP            0x03
 263 #define I40E_MODULE_TYPE_QSFP           0x0D
 264         /* 2nd byte: ethernet compliance codes for 10/40G */
 265 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 266 #define I40E_MODULE_TYPE_40G_LR4        0x02
 267 #define I40E_MODULE_TYPE_40G_SR4        0x04
 268 #define I40E_MODULE_TYPE_40G_CR4        0x08
 269 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 270 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 271 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 272 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 273         /* 3rd byte: ethernet compliance codes for 1G */
 274 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 275 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 276 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 277 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 278 };
 279
 280 enum i40e_aq_capabilities_phy_type {
 281         I40E_CAP_PHY_TYPE_SGMII                 = BIT(I40E_PHY_TYPE_SGMII),
 282         I40E_CAP_PHY_TYPE_1000BASE_KX           = BIT(I40E_PHY_TYPE_1000BASE_KX),
 283         I40E_CAP_PHY_TYPE_10GBASE_KX4           = BIT(I40E_PHY_TYPE_10GBASE_KX4),
 284         I40E_CAP_PHY_TYPE_10GBASE_KR            = BIT(I40E_PHY_TYPE_10GBASE_KR),
 285         I40E_CAP_PHY_TYPE_40GBASE_KR4           = BIT(I40E_PHY_TYPE_40GBASE_KR4),
 286         I40E_CAP_PHY_TYPE_XAUI                  = BIT(I40E_PHY_TYPE_XAUI),
 287         I40E_CAP_PHY_TYPE_XFI                   = BIT(I40E_PHY_TYPE_XFI),
 288         I40E_CAP_PHY_TYPE_SFI                   = BIT(I40E_PHY_TYPE_SFI),
 289         I40E_CAP_PHY_TYPE_XLAUI                 = BIT(I40E_PHY_TYPE_XLAUI),
 290         I40E_CAP_PHY_TYPE_XLPPI                 = BIT(I40E_PHY_TYPE_XLPPI),
 291         I40E_CAP_PHY_TYPE_40GBASE_CR4_CU        = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
 292         I40E_CAP_PHY_TYPE_10GBASE_CR1_CU        = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
 293         I40E_CAP_PHY_TYPE_10GBASE_AOC           = BIT(I40E_PHY_TYPE_10GBASE_AOC),
 294         I40E_CAP_PHY_TYPE_40GBASE_AOC           = BIT(I40E_PHY_TYPE_40GBASE_AOC),
 295         I40E_CAP_PHY_TYPE_100BASE_TX            = BIT(I40E_PHY_TYPE_100BASE_TX),
 296         I40E_CAP_PHY_TYPE_1000BASE_T            = BIT(I40E_PHY_TYPE_1000BASE_T),
 297         I40E_CAP_PHY_TYPE_10GBASE_T             = BIT(I40E_PHY_TYPE_10GBASE_T),
 298         I40E_CAP_PHY_TYPE_10GBASE_SR            = BIT(I40E_PHY_TYPE_10GBASE_SR),
 299         I40E_CAP_PHY_TYPE_10GBASE_LR            = BIT(I40E_PHY_TYPE_10GBASE_LR),
 300         I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU       = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
 301         I40E_CAP_PHY_TYPE_10GBASE_CR1           = BIT(I40E_PHY_TYPE_10GBASE_CR1),
 302         I40E_CAP_PHY_TYPE_40GBASE_CR4           = BIT(I40E_PHY_TYPE_40GBASE_CR4),
 303         I40E_CAP_PHY_TYPE_40GBASE_SR4           = BIT(I40E_PHY_TYPE_40GBASE_SR4),
 304         I40E_CAP_PHY_TYPE_40GBASE_LR4           = BIT(I40E_PHY_TYPE_40GBASE_LR4),
 305         I40E_CAP_PHY_TYPE_1000BASE_SX           = BIT(I40E_PHY_TYPE_1000BASE_SX),
 306         I40E_CAP_PHY_TYPE_1000BASE_LX           = BIT(I40E_PHY_TYPE_1000BASE_LX),
 307         I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL    = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
 308         I40E_CAP_PHY_TYPE_20GBASE_KR2           = BIT(I40E_PHY_TYPE_20GBASE_KR2)
 309 };
 310
 311 struct i40e_phy_info {
 312         struct i40e_link_status link_info;
 313         struct i40e_link_status link_info_old;
 314         bool get_link_info;
 315         enum i40e_media_type media_type;
 316         /* all the phy types the NVM is capable of */
 317         u32 phy_types;
 318 };
 319
 320 #define I40E_HW_CAP_MAX_GPIO                    30
 321 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 322 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 323
 324 /* Capabilities of a PF or a VF or the whole device */
 325 struct i40e_hw_capabilities {
 326         u32  switch_mode;
 327 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 328 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 329 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 330
 331         u32  management_mode;
 332         u32  npar_enable;
 333         u32  os2bmc;
 334         u32  valid_functions;
 335         bool sr_iov_1_1;
 336         bool vmdq;
 337         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 338         bool evb_802_1_qbh; /* Bridge Port Extension */
 339         bool dcb;
 340         bool fcoe;
 341         bool iscsi; /* Indicates iSCSI enabled */
 342         bool flex10_enable;
 343         bool flex10_capable;
 344         u32  flex10_mode;
 345 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 346 #define I40E_FLEX10_MODE_DCC            0x1
 347 #define I40E_FLEX10_MODE_DCI            0x2
 348
 349         u32 flex10_status;
 350 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 351 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 352
 353         bool mgmt_cem;
 354         bool ieee_1588;
 355         bool iwarp;
 356         bool fd;
 357         u32 fd_filters_guaranteed;
 358         u32 fd_filters_best_effort;
 359         bool rss;
 360         u32 rss_table_size;
 361         u32 rss_table_entry_width;
 362         bool led[I40E_HW_CAP_MAX_GPIO];
 363         bool sdp[I40E_HW_CAP_MAX_GPIO];
 364         u32 nvm_image_type;
 365         u32 num_flow_director_filters;
 366         u32 num_vfs;
 367         u32 vf_base_id;
 368         u32 num_vsis;
 369         u32 num_rx_qp;
 370         u32 num_tx_qp;
 371         u32 base_queue;
 372         u32 num_msix_vectors;
 373         u32 num_msix_vectors_vf;
 374         u32 led_pin_num;
 375         u32 sdp_pin_num;
 376         u32 mdio_port_num;
 377         u32 mdio_port_mode;
 378         u8 rx_buf_chain_len;
 379         u32 enabled_tcmap;
 380         u32 maxtc;
 381 };
 382
 383 struct i40e_mac_info {
 384         enum i40e_mac_type type;
 385         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 386         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 387         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 388         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 389         u16 max_fcoeq;
 390 };
 391
 392 enum i40e_aq_resources_ids {
 393         I40E_NVM_RESOURCE_ID = 1
 394 };
 395
 396 enum i40e_aq_resource_access_type {
 397         I40E_RESOURCE_READ = 1,
 398         I40E_RESOURCE_WRITE
 399 };
 400
 401 struct i40e_nvm_info {
 402         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 403         u32 timeout;              /* [ms] */
 404         u16 sr_size;              /* Shadow RAM size in words */
 405         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 406         u16 version;              /* NVM package version */
 407         u32 eetrack;              /* NVM data version */
 408         u32 oem_ver;              /* OEM version info */
 409 };
 410
 411 /* definitions used in NVM update support */
 412
 413 enum i40e_nvmupd_cmd {
 414         I40E_NVMUPD_INVALID,
 415         I40E_NVMUPD_READ_CON,
 416         I40E_NVMUPD_READ_SNT,
 417         I40E_NVMUPD_READ_LCB,
 418         I40E_NVMUPD_READ_SA,
 419         I40E_NVMUPD_WRITE_ERA,
 420         I40E_NVMUPD_WRITE_CON,
 421         I40E_NVMUPD_WRITE_SNT,
 422         I40E_NVMUPD_WRITE_LCB,
 423         I40E_NVMUPD_WRITE_SA,
 424         I40E_NVMUPD_CSUM_CON,
 425         I40E_NVMUPD_CSUM_SA,
 426         I40E_NVMUPD_CSUM_LCB,
 427         I40E_NVMUPD_STATUS,
 428         I40E_NVMUPD_EXEC_AQ,
 429         I40E_NVMUPD_GET_AQ_RESULT,
 430 };
 431
 432 enum i40e_nvmupd_state {
 433         I40E_NVMUPD_STATE_INIT,
 434         I40E_NVMUPD_STATE_READING,
 435         I40E_NVMUPD_STATE_WRITING,
 436         I40E_NVMUPD_STATE_INIT_WAIT,
 437         I40E_NVMUPD_STATE_WRITE_WAIT,
 438 };
 439
 440 /* nvm_access definition and its masks/shifts need to be accessible to
 441  * application, core driver, and shared code.  Where is the right file?
 442  */
 443 #define I40E_NVM_READ   0xB
 444 #define I40E_NVM_WRITE  0xC
 445
 446 #define I40E_NVM_MOD_PNT_MASK 0xFF
 447
 448 #define I40E_NVM_TRANS_SHIFT    8
 449 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 450 #define I40E_NVM_CON            0x0
 451 #define I40E_NVM_SNT            0x1
 452 #define I40E_NVM_LCB            0x2
 453 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 454 #define I40E_NVM_ERA            0x4
 455 #define I40E_NVM_CSUM           0x8
 456 #define I40E_NVM_EXEC           0xf
 457
 458 #define I40E_NVM_ADAPT_SHIFT    16
 459 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 460
 461 #define I40E_NVMUPD_MAX_DATA    4096
 462 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 463
 464 struct i40e_nvm_access {
 465         u32 command;
 466         u32 config;
 467         u32 offset;     /* in bytes */
 468         u32 data_size;  /* in bytes */
 469         u8 data[1];
 470 };
 471
 472 /* PCI bus types */
 473 enum i40e_bus_type {
 474         i40e_bus_type_unknown = 0,
 475         i40e_bus_type_pci,
 476         i40e_bus_type_pcix,
 477         i40e_bus_type_pci_express,
 478         i40e_bus_type_reserved
 479 };
 480
 481 /* PCI bus speeds */
 482 enum i40e_bus_speed {
 483         i40e_bus_speed_unknown  = 0,
 484         i40e_bus_speed_33       = 33,
 485         i40e_bus_speed_66       = 66,
 486         i40e_bus_speed_100      = 100,
 487         i40e_bus_speed_120      = 120,
 488         i40e_bus_speed_133      = 133,
 489         i40e_bus_speed_2500     = 2500,
 490         i40e_bus_speed_5000     = 5000,
 491         i40e_bus_speed_8000     = 8000,
 492         i40e_bus_speed_reserved
 493 };
 494
 495 /* PCI bus widths */
 496 enum i40e_bus_width {
 497         i40e_bus_width_unknown  = 0,
 498         i40e_bus_width_pcie_x1  = 1,
 499         i40e_bus_width_pcie_x2  = 2,
 500         i40e_bus_width_pcie_x4  = 4,
 501         i40e_bus_width_pcie_x8  = 8,
 502         i40e_bus_width_32       = 32,
 503         i40e_bus_width_64       = 64,
 504         i40e_bus_width_reserved
 505 };
 506
 507 /* Bus parameters */
 508 struct i40e_bus_info {
 509         enum i40e_bus_speed speed;
 510         enum i40e_bus_width width;
 511         enum i40e_bus_type type;
 512
 513         u16 func;
 514         u16 device;
 515         u16 lan_id;
 516 };
 517
 518 /* Flow control (FC) parameters */
 519 struct i40e_fc_info {
 520         enum i40e_fc_mode current_mode; /* FC mode in effect */
 521         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 522 };
 523
 524 #define I40E_MAX_TRAFFIC_CLASS          8
 525 #define I40E_MAX_USER_PRIORITY          8
 526 #define I40E_DCBX_MAX_APPS              32
 527 #define I40E_LLDPDU_SIZE                1500
 528 #define I40E_TLV_STATUS_OPER            0x1
 529 #define I40E_TLV_STATUS_SYNC            0x2
 530 #define I40E_TLV_STATUS_ERR             0x4
 531 #define I40E_CEE_OPER_MAX_APPS          3
 532 #define I40E_APP_PROTOID_FCOE           0x8906
 533 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 534 #define I40E_APP_PROTOID_FIP            0x8914
 535 #define I40E_APP_SEL_ETHTYPE            0x1
 536 #define I40E_APP_SEL_TCPIP              0x2
 537 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 538 #define I40E_CEE_APP_SEL_TCPIP          0x1
 539
 540 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 541 struct i40e_dcb_ets_config {
 542         u8 willing;
 543         u8 cbs;
 544         u8 maxtcs;
 545         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 546         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 547         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 548 };
 549
 550 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 551 struct i40e_dcb_pfc_config {
 552         u8 willing;
 553         u8 mbc;
 554         u8 pfccap;
 555         u8 pfcenable;
 556 };
 557
 558 /* CEE or IEEE 802.1Qaz Application Priority data */
 559 struct i40e_dcb_app_priority_table {
 560         u8  priority;
 561         u8  selector;
 562         u16 protocolid;
 563 };
 564
 565 struct i40e_dcbx_config {
 566         u8  dcbx_mode;
 567 #define I40E_DCBX_MODE_CEE      0x1
 568 #define I40E_DCBX_MODE_IEEE     0x2
 569         u8  app_mode;
 570 #define I40E_DCBX_APPS_NON_WILLING      0x1
 571         u32 numapps;
 572         u32 tlv_status; /* CEE mode TLV status */
 573         struct i40e_dcb_ets_config etscfg;
 574         struct i40e_dcb_ets_config etsrec;
 575         struct i40e_dcb_pfc_config pfc;
 576         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 577 };
 578
 579 /* Port hardware description */
 580 struct i40e_hw {
 581         u8 *hw_addr;
 582         void *back;
 583
 584         /* subsystem structs */
 585         struct i40e_phy_info phy;
 586         struct i40e_mac_info mac;
 587         struct i40e_bus_info bus;
 588         struct i40e_nvm_info nvm;
 589         struct i40e_fc_info fc;
 590
 591         /* pci info */
 592         u16 device_id;
 593         u16 vendor_id;
 594         u16 subsystem_device_id;
 595         u16 subsystem_vendor_id;
 596         u8 revision_id;
 597         u8 port;
 598         bool adapter_stopped;
 599
 600         /* capabilities for entire device and PCI func */
 601         struct i40e_hw_capabilities dev_caps;
 602         struct i40e_hw_capabilities func_caps;
 603
 604         /* Flow Director shared filter space */
 605         u16 fdir_shared_filter_count;
 606
 607         /* device profile info */
 608         u8  pf_id;
 609         u16 main_vsi_seid;
 610
 611         /* for multi-function MACs */
 612         u16 partition_id;
 613         u16 num_partitions;
 614         u16 num_ports;
 615
 616         /* Closest numa node to the device */
 617         u16 numa_node;
 618
 619         /* Admin Queue info */
 620         struct i40e_adminq_info aq;
 621
 622         /* state of nvm update process */
 623         enum i40e_nvmupd_state nvmupd_state;
 624         struct i40e_aq_desc nvm_wb_desc;
 625         struct i40e_virt_mem nvm_buff;
 626
 627         /* HMC info */
 628         struct i40e_hmc_info hmc; /* HMC info struct */
 629
 630         /* LLDP/DCBX Status */
 631         u16 dcbx_status;
 632
 633         /* DCBX info */
 634         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 635         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 636         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 637
 638         /* debug mask */
 639         u32 debug_mask;
 640 #ifndef I40E_NDIS_SUPPORT
 641         char err_str[16];
 642 #endif /* I40E_NDIS_SUPPORT */
 643 };
 644
 645 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 646 {
 647 #ifdef X722_SUPPORT
 648         return (hw->mac.type == I40E_MAC_VF ||
 649                 hw->mac.type == I40E_MAC_X722_VF);
 650 #else
 651         return hw->mac.type == I40E_MAC_VF;
 652 #endif
 653 }
 654
 655 struct i40e_driver_version {
 656         u8 major_version;
 657         u8 minor_version;
 658         u8 build_version;
 659         u8 subbuild_version;
 660         u8 driver_string[32];
 661 };
 662
 663 /* RX Descriptors */
 664 union i40e_16byte_rx_desc {
 665         struct {
 666                 __le64 pkt_addr; /* Packet buffer address */
 667                 __le64 hdr_addr; /* Header buffer address */
 668         } read;
 669         struct {
 670                 struct {
 671                         struct {
 672                                 union {
 673                                         __le16 mirroring_status;
 674                                         __le16 fcoe_ctx_id;
 675                                 } mirr_fcoe;
 676                                 __le16 l2tag1;
 677                         } lo_dword;
 678                         union {
 679                                 __le32 rss; /* RSS Hash */
 680                                 __le32 fd_id; /* Flow director filter id */
 681                                 __le32 fcoe_param; /* FCoE DDP Context id */
 682                         } hi_dword;
 683                 } qword0;
 684                 struct {
 685                         /* ext status/error/pktype/length */
 686                         __le64 status_error_len;
 687                 } qword1;
 688         } wb;  /* writeback */
 689 };
 690
 691 union i40e_32byte_rx_desc {
 692         struct {
 693                 __le64  pkt_addr; /* Packet buffer address */
 694                 __le64  hdr_addr; /* Header buffer address */
 695                         /* bit 0 of hdr_buffer_addr is DD bit */
 696                 __le64  rsvd1;
 697                 __le64  rsvd2;
 698         } read;
 699         struct {
 700                 struct {
 701                         struct {
 702                                 union {
 703                                         __le16 mirroring_status;
 704                                         __le16 fcoe_ctx_id;
 705                                 } mirr_fcoe;
 706                                 __le16 l2tag1;
 707                         } lo_dword;
 708                         union {
 709                                 __le32 rss; /* RSS Hash */
 710                                 __le32 fcoe_param; /* FCoE DDP Context id */
 711                                 /* Flow director filter id in case of
 712                                  * Programming status desc WB
 713                                  */
 714                                 __le32 fd_id;
 715                         } hi_dword;
 716                 } qword0;
 717                 struct {
 718                         /* status/error/pktype/length */
 719                         __le64 status_error_len;
 720                 } qword1;
 721                 struct {
 722                         __le16 ext_status; /* extended status */
 723                         __le16 rsvd;
 724                         __le16 l2tag2_1;
 725                         __le16 l2tag2_2;
 726                 } qword2;
 727                 struct {
 728                         union {
 729                                 __le32 flex_bytes_lo;
 730                                 __le32 pe_status;
 731                         } lo_dword;
 732                         union {
 733                                 __le32 flex_bytes_hi;
 734                                 __le32 fd_id;
 735                         } hi_dword;
 736                 } qword3;
 737         } wb;  /* writeback */
 738 };
 739
 740 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 741 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 742                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 743 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 744 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 745                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 746
 747 enum i40e_rx_desc_status_bits {
 748         /* Note: These are predefined bit offsets */
 749         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 750         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 751         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 752         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 753         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 754         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 755         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 756         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 757
 758         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 759         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 760         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 761         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 762         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 763         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 764         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 765         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 766 };
 767
 768 #define I40E_RXD_QW1_STATUS_SHIFT       0
 769 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 770                                          I40E_RXD_QW1_STATUS_SHIFT)
 771
 772 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 773 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 774                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 775
 776 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 777 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 778
 779 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 780 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 781                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 782
 783 enum i40e_rx_desc_fltstat_values {
 784         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 785         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 786         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 787         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 788 };
 789
 790 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 791 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 792 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 793 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 794
 795 #define I40E_RXD_QW1_ERROR_SHIFT        19
 796 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 797
 798 enum i40e_rx_desc_error_bits {
 799         /* Note: These are predefined bit offsets */
 800         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 801         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 802         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 803         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 804         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 805         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 806         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 807         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 808         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 809 };
 810
 811 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 812         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 813         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 814         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 815         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 816         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 817 };
 818
 819 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 820 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 821
 822 /* Packet type non-ip values */
 823 enum i40e_rx_l2_ptype {
 824         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 825         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 826         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 827         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 828         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 829         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 830         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 831         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 832         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 833         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 834         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 835         I40E_RX_PTYPE_L2_ARP                            = 11,
 836         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 837         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 838         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 839         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 840         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 841         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 842         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 843         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 844         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 845         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 846         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 847         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 848         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 849         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 850 };
 851
 852 struct i40e_rx_ptype_decoded {
 853         u32 ptype:8;
 854         u32 known:1;
 855         u32 outer_ip:1;
 856         u32 outer_ip_ver:1;
 857         u32 outer_frag:1;
 858         u32 tunnel_type:3;
 859         u32 tunnel_end_prot:2;
 860         u32 tunnel_end_frag:1;
 861         u32 inner_prot:4;
 862         u32 payload_layer:3;
 863 };
 864
 865 enum i40e_rx_ptype_outer_ip {
 866         I40E_RX_PTYPE_OUTER_L2  = 0,
 867         I40E_RX_PTYPE_OUTER_IP  = 1
 868 };
 869
 870 enum i40e_rx_ptype_outer_ip_ver {
 871         I40E_RX_PTYPE_OUTER_NONE        = 0,
 872         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 873         I40E_RX_PTYPE_OUTER_IPV6        = 1
 874 };
 875
 876 enum i40e_rx_ptype_outer_fragmented {
 877         I40E_RX_PTYPE_NOT_FRAG  = 0,
 878         I40E_RX_PTYPE_FRAG      = 1
 879 };
 880
 881 enum i40e_rx_ptype_tunnel_type {
 882         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 883         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 884         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 885         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 886         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 887 };
 888
 889 enum i40e_rx_ptype_tunnel_end_prot {
 890         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 891         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 892         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 893 };
 894
 895 enum i40e_rx_ptype_inner_prot {
 896         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 897         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 898         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 899         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 900         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 901         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 902 };
 903
 904 enum i40e_rx_ptype_payload_layer {
 905         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 906         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 907         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 908         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 909 };
 910
 911 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 912 #define I40E_RX_PTYPE_SHIFT             56
 913
 914 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 915 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 916                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 917
 918 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 919 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 920                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 921
 922 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 923 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 924
 925 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 926 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 927
 928 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 929 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 930                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 931
 932 enum i40e_rx_desc_ext_status_bits {
 933         /* Note: These are predefined bit offsets */
 934         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 935         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 936         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 937         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 938         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 939         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 940         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 941 };
 942
 943 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 944 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 945
 946 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 947 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 948
 949 enum i40e_rx_desc_pe_status_bits {
 950         /* Note: These are predefined bit offsets */
 951         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 952         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 953         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 954         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 955         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 956         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 957         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 958         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 959         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 960 };
 961
 962 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 963 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 964
 965 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 966 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 967                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 968
 969 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 970 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 971                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 972
 973 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 974 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 975                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 976
 977 enum i40e_rx_prog_status_desc_status_bits {
 978         /* Note: These are predefined bit offsets */
 979         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 980         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 981 };
 982
 983 enum i40e_rx_prog_status_desc_prog_id_masks {
 984         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 985         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 986         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 987 };
 988
 989 enum i40e_rx_prog_status_desc_error_bits {
 990         /* Note: These are predefined bit offsets */
 991         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 992         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 993         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 994         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 995 };
 996
 997 #define I40E_TWO_BIT_MASK       0x3
 998 #define I40E_THREE_BIT_MASK     0x7
 999 #define I40E_FOUR_BIT_MASK      0xF
1000 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1001
1002 /* TX Descriptor */
1003 struct i40e_tx_desc {
1004         __le64 buffer_addr; /* Address of descriptor's data buf */
1005         __le64 cmd_type_offset_bsz;
1006 };
1007
1008 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1009 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1010
1011 enum i40e_tx_desc_dtype_value {
1012         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1013         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1014         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1015         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1016         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1017         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1018         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1019         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1020         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1021         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1022 };
1023
1024 #define I40E_TXD_QW1_CMD_SHIFT  4
1025 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1026
1027 enum i40e_tx_desc_cmd_bits {
1028         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1029         I40E_TX_DESC_CMD_RS                     = 0x0002,
1030         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1031         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1032         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1033         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1034         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1035         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1036         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1037         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1038         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1039         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1040         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1041         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1042         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1043         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1044         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1045         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1046 };
1047
1048 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1049 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1050                                          I40E_TXD_QW1_OFFSET_SHIFT)
1051
1052 enum i40e_tx_desc_length_fields {
1053         /* Note: These are predefined bit offsets */
1054         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1055         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1056         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1057 };
1058
1059 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1060 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1061 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1062 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1063
1064 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1065 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1066                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1067
1068 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1069 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1070
1071 /* Context descriptors */
1072 struct i40e_tx_context_desc {
1073         __le32 tunneling_params;
1074         __le16 l2tag2;
1075         __le16 rsvd;
1076         __le64 type_cmd_tso_mss;
1077 };
1078
1079 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1080 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1081
1082 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1083 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1084
1085 enum i40e_tx_ctx_desc_cmd_bits {
1086         I40E_TX_CTX_DESC_TSO            = 0x01,
1087         I40E_TX_CTX_DESC_TSYN           = 0x02,
1088         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1089         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1090         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1091         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1092         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1093         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1094         I40E_TX_CTX_DESC_SWPE           = 0x40
1095 };
1096
1097 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1098 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1099                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1100
1101 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1102 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1103                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1104
1105 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1106 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1107
1108 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1109 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1110                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1111
1112 enum i40e_tx_ctx_desc_eipt_offload {
1113         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1114         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1115         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1116         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1117 };
1118
1119 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1120 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1121                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1122
1123 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1124 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1125
1126 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1127 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1128
1129 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1130 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1131
1132 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1133
1134 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1135 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1136                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1137
1138 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1139 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1140                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1141
1142 struct i40e_nop_desc {
1143         __le64 rsvd;
1144         __le64 dtype_cmd;
1145 };
1146
1147 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1148 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1149
1150 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1151 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1152
1153 enum i40e_tx_nop_desc_cmd_bits {
1154         /* Note: These are predefined bit offsets */
1155         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1156         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1157         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1158 };
1159
1160 struct i40e_filter_program_desc {
1161         __le32 qindex_flex_ptype_vsi;
1162         __le32 rsvd;
1163         __le32 dtype_cmd_cntindex;
1164         __le32 fd_id;
1165 };
1166 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1167 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1168                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1169 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1170 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1171                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1172 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1173 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1174                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1175
1176 /* Packet Classifier Types for filters */
1177 enum i40e_filter_pctype {
1178 #ifdef X722_SUPPORT
1179         /* Note: Values 0-28 are reserved for future use.
1180          * Value 29, 30, 32 are not supported on XL710 and X710.
1181          */
1182         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1183         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1184 #else
1185         /* Note: Values 0-30 are reserved for future use */
1186 #endif
1187         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1188 #ifdef X722_SUPPORT
1189         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1190 #else
1191         /* Note: Value 32 is reserved for future use */
1192 #endif
1193         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1194         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1195         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1196         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1197 #ifdef X722_SUPPORT
1198         /* Note: Values 37-38 are reserved for future use.
1199          * Value 39, 40, 42 are not supported on XL710 and X710.
1200          */
1201         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1202         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1203 #else
1204         /* Note: Values 37-40 are reserved for future use */
1205 #endif
1206         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1207 #ifdef X722_SUPPORT
1208         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1209 #endif
1210         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1211         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1212         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1213         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1214         /* Note: Value 47 is reserved for future use */
1215         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1216         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1217         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1218         /* Note: Values 51-62 are reserved for future use */
1219         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1220 };
1221
1222 enum i40e_filter_program_desc_dest {
1223         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1224         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1225         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1226 };
1227
1228 enum i40e_filter_program_desc_fd_status {
1229         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1230         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1231         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1232         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1233 };
1234
1235 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1236 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1237                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1238
1239 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1240 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1241
1242 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1243 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1244                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1245
1246 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1247 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1248
1249 enum i40e_filter_program_desc_pcmd {
1250         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1251         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1252 };
1253
1254 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1255 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1256
1257 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1258 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1259
1260 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1261                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1262 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1263                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1264 #ifdef X722_SUPPORT
1265
1266 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1267                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1268 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1269 #endif
1270
1271 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1272 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1273                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1274
1275 enum i40e_filter_type {
1276         I40E_FLOW_DIRECTOR_FLTR = 0,
1277         I40E_PE_QUAD_HASH_FLTR = 1,
1278         I40E_ETHERTYPE_FLTR,
1279         I40E_FCOE_CTX_FLTR,
1280         I40E_MAC_VLAN_FLTR,
1281         I40E_HASH_FLTR
1282 };
1283
1284 struct i40e_vsi_context {
1285         u16 seid;
1286         u16 uplink_seid;
1287         u16 vsi_number;
1288         u16 vsis_allocated;
1289         u16 vsis_unallocated;
1290         u16 flags;
1291         u8 pf_num;
1292         u8 vf_num;
1293         u8 connection_type;
1294         struct i40e_aqc_vsi_properties_data info;
1295 };
1296
1297 struct i40e_veb_context {
1298         u16 seid;
1299         u16 uplink_seid;
1300         u16 veb_number;
1301         u16 vebs_allocated;
1302         u16 vebs_unallocated;
1303         u16 flags;
1304         struct i40e_aqc_get_veb_parameters_completion info;
1305 };
1306
1307 /* Statistics collected by each port, VSI, VEB, and S-channel */
1308 struct i40e_eth_stats {
1309         u64 rx_bytes;                   /* gorc */
1310         u64 rx_unicast;                 /* uprc */
1311         u64 rx_multicast;               /* mprc */
1312         u64 rx_broadcast;               /* bprc */
1313         u64 rx_discards;                /* rdpc */
1314         u64 rx_unknown_protocol;        /* rupp */
1315         u64 tx_bytes;                   /* gotc */
1316         u64 tx_unicast;                 /* uptc */
1317         u64 tx_multicast;               /* mptc */
1318         u64 tx_broadcast;               /* bptc */
1319         u64 tx_discards;                /* tdpc */
1320         u64 tx_errors;                  /* tepc */
1321 };
1322
1323 /* Statistics collected per VEB per TC */
1324 struct i40e_veb_tc_stats {
1325         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1326         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1327         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1328         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1329 };
1330
1331 /* Statistics collected by the MAC */
1332 struct i40e_hw_port_stats {
1333         /* eth stats collected by the port */
1334         struct i40e_eth_stats eth;
1335
1336         /* additional port specific stats */
1337         u64 tx_dropped_link_down;       /* tdold */
1338         u64 crc_errors;                 /* crcerrs */
1339         u64 illegal_bytes;              /* illerrc */
1340         u64 error_bytes;                /* errbc */
1341         u64 mac_local_faults;           /* mlfc */
1342         u64 mac_remote_faults;          /* mrfc */
1343         u64 rx_length_errors;           /* rlec */
1344         u64 link_xon_rx;                /* lxonrxc */
1345         u64 link_xoff_rx;               /* lxoffrxc */
1346         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1347         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1348         u64 link_xon_tx;                /* lxontxc */
1349         u64 link_xoff_tx;               /* lxofftxc */
1350         u64 priority_xon_tx[8];         /* pxontxc[8] */
1351         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1352         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1353         u64 rx_size_64;                 /* prc64 */
1354         u64 rx_size_127;                /* prc127 */
1355         u64 rx_size_255;                /* prc255 */
1356         u64 rx_size_511;                /* prc511 */
1357         u64 rx_size_1023;               /* prc1023 */
1358         u64 rx_size_1522;               /* prc1522 */
1359         u64 rx_size_big;                /* prc9522 */
1360         u64 rx_undersize;               /* ruc */
1361         u64 rx_fragments;               /* rfc */
1362         u64 rx_oversize;                /* roc */
1363         u64 rx_jabber;                  /* rjc */
1364         u64 tx_size_64;                 /* ptc64 */
1365         u64 tx_size_127;                /* ptc127 */
1366         u64 tx_size_255;                /* ptc255 */
1367         u64 tx_size_511;                /* ptc511 */
1368         u64 tx_size_1023;               /* ptc1023 */
1369         u64 tx_size_1522;               /* ptc1522 */
1370         u64 tx_size_big;                /* ptc9522 */
1371         u64 mac_short_packet_dropped;   /* mspdc */
1372         u64 checksum_error;             /* xec */
1373         /* flow director stats */
1374         u64 fd_atr_match;
1375         u64 fd_sb_match;
1376         u64 fd_atr_tunnel_match;
1377         u32 fd_atr_status;
1378         u32 fd_sb_status;
1379         /* EEE LPI */
1380         u32 tx_lpi_status;
1381         u32 rx_lpi_status;
1382         u64 tx_lpi_count;               /* etlpic */
1383         u64 rx_lpi_count;               /* erlpic */
1384 };
1385
1386 /* Checksum and Shadow RAM pointers */
1387 #define I40E_SR_NVM_CONTROL_WORD                0x00
1388 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1389 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1390 #define I40E_SR_OPTION_ROM_PTR                  0x05
1391 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1392 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1393 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1394 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1395 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1396 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1397 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1398 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1399 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1400 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1401 #define I40E_SR_PBA_FLAGS                       0x15
1402 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1403 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1404 #define I40E_NVM_OEM_VER_OFF                    0x83
1405 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1406 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1407 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1408 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1409 #define I40E_SR_NVM_MAP_VERSION                 0x29
1410 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1411 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1412 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1413 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1414 #define I40E_SR_VPD_PTR                         0x2F
1415 #define I40E_SR_PXE_SETUP_PTR                   0x30
1416 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1417 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1418 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1419 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1420 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1421 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1422 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1423 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1424 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1425 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1426 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1427 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1428 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1429 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1430 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1431 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1432 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1433 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1434
1435 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1436 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1437 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1438 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1439 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1440
1441 /* Shadow RAM related */
1442 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1443 #define I40E_SR_BUF_ALIGNMENT           4096
1444 #define I40E_SR_WORDS_IN_1KB            512
1445 /* Checksum should be calculated such that after adding all the words,
1446  * including the checksum word itself, the sum should be 0xBABA.
1447  */
1448 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1449
1450 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1451
1452 enum i40e_switch_element_types {
1453         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1454         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1455         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1456         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1457         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1458         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1459         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1460         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1461         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1462 };
1463
1464 /* Supported EtherType filters */
1465 enum i40e_ether_type_index {
1466         I40E_ETHER_TYPE_1588            = 0,
1467         I40E_ETHER_TYPE_FIP             = 1,
1468         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1469         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1470         I40E_ETHER_TYPE_LLDP            = 4,
1471         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1472         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1473         I40E_ETHER_TYPE_QCN_CNM         = 7,
1474         I40E_ETHER_TYPE_8021X           = 8,
1475         I40E_ETHER_TYPE_ARP             = 9,
1476         I40E_ETHER_TYPE_RSV1            = 10,
1477         I40E_ETHER_TYPE_RSV2            = 11,
1478 };
1479
1480 /* Filter context base size is 1K */
1481 #define I40E_HASH_FILTER_BASE_SIZE      1024
1482 /* Supported Hash filter values */
1483 enum i40e_hash_filter_size {
1484         I40E_HASH_FILTER_SIZE_1K        = 0,
1485         I40E_HASH_FILTER_SIZE_2K        = 1,
1486         I40E_HASH_FILTER_SIZE_4K        = 2,
1487         I40E_HASH_FILTER_SIZE_8K        = 3,
1488         I40E_HASH_FILTER_SIZE_16K       = 4,
1489         I40E_HASH_FILTER_SIZE_32K       = 5,
1490         I40E_HASH_FILTER_SIZE_64K       = 6,
1491         I40E_HASH_FILTER_SIZE_128K      = 7,
1492         I40E_HASH_FILTER_SIZE_256K      = 8,
1493         I40E_HASH_FILTER_SIZE_512K      = 9,
1494         I40E_HASH_FILTER_SIZE_1M        = 10,
1495 };
1496
1497 /* DMA context base size is 0.5K */
1498 #define I40E_DMA_CNTX_BASE_SIZE         512
1499 /* Supported DMA context values */
1500 enum i40e_dma_cntx_size {
1501         I40E_DMA_CNTX_SIZE_512          = 0,
1502         I40E_DMA_CNTX_SIZE_1K           = 1,
1503         I40E_DMA_CNTX_SIZE_2K           = 2,
1504         I40E_DMA_CNTX_SIZE_4K           = 3,
1505         I40E_DMA_CNTX_SIZE_8K           = 4,
1506         I40E_DMA_CNTX_SIZE_16K          = 5,
1507         I40E_DMA_CNTX_SIZE_32K          = 6,
1508         I40E_DMA_CNTX_SIZE_64K          = 7,
1509         I40E_DMA_CNTX_SIZE_128K         = 8,
1510         I40E_DMA_CNTX_SIZE_256K         = 9,
1511 };
1512
1513 /* Supported Hash look up table (LUT) sizes */
1514 enum i40e_hash_lut_size {
1515         I40E_HASH_LUT_SIZE_128          = 0,
1516         I40E_HASH_LUT_SIZE_512          = 1,
1517 };
1518
1519 /* Structure to hold a per PF filter control settings */
1520 struct i40e_filter_control_settings {
1521         /* number of PE Quad Hash filter buckets */
1522         enum i40e_hash_filter_size pe_filt_num;
1523         /* number of PE Quad Hash contexts */
1524         enum i40e_dma_cntx_size pe_cntx_num;
1525         /* number of FCoE filter buckets */
1526         enum i40e_hash_filter_size fcoe_filt_num;
1527         /* number of FCoE DDP contexts */
1528         enum i40e_dma_cntx_size fcoe_cntx_num;
1529         /* size of the Hash LUT */
1530         enum i40e_hash_lut_size hash_lut_size;
1531         /* enable FDIR filters for PF and its VFs */
1532         bool enable_fdir;
1533         /* enable Ethertype filters for PF and its VFs */
1534         bool enable_ethtype;
1535         /* enable MAC/VLAN filters for PF and its VFs */
1536         bool enable_macvlan;
1537 };
1538
1539 /* Structure to hold device level control filter counts */
1540 struct i40e_control_filter_stats {
1541         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1542         u16 etype_used;       /* Used perfect EtherType filters */
1543         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1544         u16 etype_free;       /* Un-used perfect EtherType filters */
1545 };
1546
1547 enum i40e_reset_type {
1548         I40E_RESET_POR          = 0,
1549         I40E_RESET_CORER        = 1,
1550         I40E_RESET_GLOBR        = 2,
1551         I40E_RESET_EMPR         = 3,
1552 };
1553
1554 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1555 #define I40E_NVM_LLDP_CFG_PTR           0xD
1556 struct i40e_lldp_variables {
1557         u16 length;
1558         u16 adminstatus;
1559         u16 msgfasttx;
1560         u16 msgtxinterval;
1561         u16 txparams;
1562         u16 timers;
1563         u16 crc8;
1564 };
1565
1566 /* Offsets into Alternate Ram */
1567 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1568 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1569 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1570 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1571 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1572 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1573
1574 /* Alternate Ram Bandwidth Masks */
1575 #define I40E_ALT_BW_VALUE_MASK          0xFF
1576 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1577 #define I40E_ALT_BW_VALID_MASK          0x80000000
1578
1579 /* RSS Hash Table Size */
1580 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1581 #endif /* _I40E_TYPE_H_ */