1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Max timeout in ms for the phy to respond */
81 #define I40E_MAX_PHY_TIMEOUT 500
83 /* Check whether address is multicast. */
84 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
86 /* Check whether an address is broadcast. */
87 #define I40E_IS_BROADCAST(address) \
88 ((((u8 *)(address))[0] == ((u8)0xff)) && \
89 (((u8 *)(address))[1] == ((u8)0xff)))
91 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
92 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
94 /* forward declaration */
96 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
101 /* Data type manipulation macros. */
102 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
103 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
105 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
106 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
108 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
109 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
111 /* Number of Transmit Descriptors must be a multiple of 8. */
112 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
113 /* Number of Receive Descriptors must be a multiple of 32 if
114 * the number of descriptors is greater than 32.
116 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
118 #define I40E_DESC_UNUSED(R) \
119 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
120 (R)->next_to_clean - (R)->next_to_use - 1)
122 /* bitfields for Tx queue mapping in QTX_CTL */
123 #define I40E_QTX_CTL_VF_QUEUE 0x0
124 #define I40E_QTX_CTL_VM_QUEUE 0x1
125 #define I40E_QTX_CTL_PF_QUEUE 0x2
127 /* debug masks - set these bits in hw->debug_mask to control output */
128 enum i40e_debug_mask {
129 I40E_DEBUG_INIT = 0x00000001,
130 I40E_DEBUG_RELEASE = 0x00000002,
132 I40E_DEBUG_LINK = 0x00000010,
133 I40E_DEBUG_PHY = 0x00000020,
134 I40E_DEBUG_HMC = 0x00000040,
135 I40E_DEBUG_NVM = 0x00000080,
136 I40E_DEBUG_LAN = 0x00000100,
137 I40E_DEBUG_FLOW = 0x00000200,
138 I40E_DEBUG_DCB = 0x00000400,
139 I40E_DEBUG_DIAG = 0x00000800,
140 I40E_DEBUG_FD = 0x00001000,
141 I40E_DEBUG_PACKAGE = 0x00002000,
143 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
144 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
145 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
146 I40E_DEBUG_AQ_COMMAND = 0x06000000,
147 I40E_DEBUG_AQ = 0x0F000000,
149 I40E_DEBUG_USER = 0xF0000000,
151 I40E_DEBUG_ALL = 0xFFFFFFFF
155 #define I40E_PCI_LINK_STATUS 0xB2
156 #define I40E_PCI_LINK_WIDTH 0x3F0
157 #define I40E_PCI_LINK_WIDTH_1 0x10
158 #define I40E_PCI_LINK_WIDTH_2 0x20
159 #define I40E_PCI_LINK_WIDTH_4 0x40
160 #define I40E_PCI_LINK_WIDTH_8 0x80
161 #define I40E_PCI_LINK_SPEED 0xF
162 #define I40E_PCI_LINK_SPEED_2500 0x1
163 #define I40E_PCI_LINK_SPEED_5000 0x2
164 #define I40E_PCI_LINK_SPEED_8000 0x3
166 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
167 I40E_GLGEN_MSCA_STCODE_SHIFT)
168 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
169 I40E_GLGEN_MSCA_OPCODE_SHIFT)
170 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
171 I40E_GLGEN_MSCA_OPCODE_SHIFT)
173 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
174 I40E_GLGEN_MSCA_STCODE_SHIFT)
175 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
176 I40E_GLGEN_MSCA_OPCODE_SHIFT)
177 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
178 I40E_GLGEN_MSCA_OPCODE_SHIFT)
179 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
180 I40E_GLGEN_MSCA_OPCODE_SHIFT)
181 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
182 I40E_GLGEN_MSCA_OPCODE_SHIFT)
184 #define I40E_PHY_COM_REG_PAGE 0x1E
185 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
186 #define I40E_PHY_LED_MANUAL_ON 0x100
187 #define I40E_PHY_LED_PROV_REG_1 0xC430
188 #define I40E_PHY_LED_MODE_MASK 0xFFFF
189 #define I40E_PHY_LED_MODE_ORIG 0x80000000
192 enum i40e_memset_type {
198 enum i40e_memcpy_type {
199 I40E_NONDMA_TO_NONDMA = 0,
205 /* These are structs for managing the hardware information and the operations.
206 * The structures of function pointers are filled out at init time when we
207 * know for sure exactly which hardware we're working with. This gives us the
208 * flexibility of using the same main driver code but adapting to slightly
209 * different hardware needs as new parts are developed. For this architecture,
210 * the Firmware and AdminQ are intended to insulate the driver from most of the
211 * future changes, but these structures will also do part of the job.
214 I40E_MAC_UNKNOWN = 0,
222 enum i40e_media_type {
223 I40E_MEDIA_TYPE_UNKNOWN = 0,
224 I40E_MEDIA_TYPE_FIBER,
225 I40E_MEDIA_TYPE_BASET,
226 I40E_MEDIA_TYPE_BACKPLANE,
229 I40E_MEDIA_TYPE_VIRTUAL
241 enum i40e_set_fc_aq_failures {
242 I40E_SET_FC_AQ_FAIL_NONE = 0,
243 I40E_SET_FC_AQ_FAIL_GET = 1,
244 I40E_SET_FC_AQ_FAIL_SET = 2,
245 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
246 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
258 I40E_VSI_TYPE_UNKNOWN
261 enum i40e_queue_type {
262 I40E_QUEUE_TYPE_RX = 0,
264 I40E_QUEUE_TYPE_PE_CEQ,
265 I40E_QUEUE_TYPE_UNKNOWN
268 struct i40e_link_status {
269 enum i40e_aq_phy_type phy_type;
270 enum i40e_aq_link_speed link_speed;
277 /* is Link Status Event notification to SW enabled */
284 /* 1st byte: module identifier */
285 #define I40E_MODULE_TYPE_SFP 0x03
286 #define I40E_MODULE_TYPE_QSFP 0x0D
287 /* 2nd byte: ethernet compliance codes for 10/40G */
288 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
289 #define I40E_MODULE_TYPE_40G_LR4 0x02
290 #define I40E_MODULE_TYPE_40G_SR4 0x04
291 #define I40E_MODULE_TYPE_40G_CR4 0x08
292 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
293 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
294 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
295 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
296 /* 3rd byte: ethernet compliance codes for 1G */
297 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
298 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
299 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
300 #define I40E_MODULE_TYPE_1000BASE_T 0x08
303 struct i40e_phy_info {
304 struct i40e_link_status link_info;
305 struct i40e_link_status link_info_old;
307 enum i40e_media_type media_type;
308 /* all the phy types the NVM is capable of */
312 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
313 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
314 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
315 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
316 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
317 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
318 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
319 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
320 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
321 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
323 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
324 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
325 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
326 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
327 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
328 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
329 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
330 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
331 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
332 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
333 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
334 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
335 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
336 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
337 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
338 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
339 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
340 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
342 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
343 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
344 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
345 * a shift is needed to adjust for this with values larger than 31. The
346 * only affected values are I40E_PHY_TYPE_25GBASE_*.
348 #define I40E_PHY_TYPE_OFFSET 1
349 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
350 I40E_PHY_TYPE_OFFSET)
351 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
352 I40E_PHY_TYPE_OFFSET)
353 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
354 I40E_PHY_TYPE_OFFSET)
355 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
356 I40E_PHY_TYPE_OFFSET)
357 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
358 I40E_PHY_TYPE_OFFSET)
359 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
360 I40E_PHY_TYPE_OFFSET)
361 #define I40E_HW_CAP_MAX_GPIO 30
362 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
363 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
365 enum i40e_acpi_programming_method {
366 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
367 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
370 #define I40E_WOL_SUPPORT_MASK 0x1
371 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
372 #define I40E_PROXY_SUPPORT_MASK 0x4
374 /* Capabilities of a PF or a VF or the whole device */
375 struct i40e_hw_capabilities {
377 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
378 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
379 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
382 u32 mng_protocols_over_mctp;
383 #define I40E_MNG_PROTOCOL_PLDM 0x2
384 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
385 #define I40E_MNG_PROTOCOL_NCSI 0x8
391 bool evb_802_1_qbg; /* Edge Virtual Bridging */
392 bool evb_802_1_qbh; /* Bridge Port Extension */
395 bool iscsi; /* Indicates iSCSI enabled */
399 #define I40E_FLEX10_MODE_UNKNOWN 0x0
400 #define I40E_FLEX10_MODE_DCC 0x1
401 #define I40E_FLEX10_MODE_DCI 0x2
404 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
405 #define I40E_FLEX10_STATUS_VC_MODE 0x2
407 bool sec_rev_disabled;
408 bool update_disabled;
409 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
410 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
416 u32 fd_filters_guaranteed;
417 u32 fd_filters_best_effort;
420 u32 rss_table_entry_width;
421 bool led[I40E_HW_CAP_MAX_GPIO];
422 bool sdp[I40E_HW_CAP_MAX_GPIO];
424 u32 num_flow_director_filters;
431 u32 num_msix_vectors;
432 u32 num_msix_vectors_vf;
441 bool apm_wol_support;
442 enum i40e_acpi_programming_method acpi_prog_method;
446 struct i40e_mac_info {
447 enum i40e_mac_type type;
449 u8 perm_addr[ETH_ALEN];
450 u8 san_addr[ETH_ALEN];
451 u8 port_addr[ETH_ALEN];
455 enum i40e_aq_resources_ids {
456 I40E_NVM_RESOURCE_ID = 1
459 enum i40e_aq_resource_access_type {
460 I40E_RESOURCE_READ = 1,
464 struct i40e_nvm_info {
465 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
466 u32 timeout; /* [ms] */
467 u16 sr_size; /* Shadow RAM size in words */
468 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
469 u16 version; /* NVM package version */
470 u32 eetrack; /* NVM data version */
471 u32 oem_ver; /* OEM version info */
474 /* definitions used in NVM update support */
476 enum i40e_nvmupd_cmd {
478 I40E_NVMUPD_READ_CON,
479 I40E_NVMUPD_READ_SNT,
480 I40E_NVMUPD_READ_LCB,
482 I40E_NVMUPD_WRITE_ERA,
483 I40E_NVMUPD_WRITE_CON,
484 I40E_NVMUPD_WRITE_SNT,
485 I40E_NVMUPD_WRITE_LCB,
486 I40E_NVMUPD_WRITE_SA,
487 I40E_NVMUPD_CSUM_CON,
489 I40E_NVMUPD_CSUM_LCB,
492 I40E_NVMUPD_GET_AQ_RESULT,
495 enum i40e_nvmupd_state {
496 I40E_NVMUPD_STATE_INIT,
497 I40E_NVMUPD_STATE_READING,
498 I40E_NVMUPD_STATE_WRITING,
499 I40E_NVMUPD_STATE_INIT_WAIT,
500 I40E_NVMUPD_STATE_WRITE_WAIT,
501 I40E_NVMUPD_STATE_ERROR
504 /* nvm_access definition and its masks/shifts need to be accessible to
505 * application, core driver, and shared code. Where is the right file?
507 #define I40E_NVM_READ 0xB
508 #define I40E_NVM_WRITE 0xC
510 #define I40E_NVM_MOD_PNT_MASK 0xFF
512 #define I40E_NVM_TRANS_SHIFT 8
513 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
514 #define I40E_NVM_CON 0x0
515 #define I40E_NVM_SNT 0x1
516 #define I40E_NVM_LCB 0x2
517 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
518 #define I40E_NVM_ERA 0x4
519 #define I40E_NVM_CSUM 0x8
520 #define I40E_NVM_EXEC 0xf
522 #define I40E_NVM_ADAPT_SHIFT 16
523 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
525 #define I40E_NVMUPD_MAX_DATA 4096
526 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
528 struct i40e_nvm_access {
531 u32 offset; /* in bytes */
532 u32 data_size; /* in bytes */
536 /* (Q)SFP module access definitions */
537 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
538 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
539 #define I40E_MODULE_TYPE_ADDR 0x00
540 #define I40E_MODULE_REVISION_ADDR 0x01
541 #define I40E_MODULE_SFF_8472_COMP 0x5E
542 #define I40E_MODULE_SFF_8472_SWAP 0x5C
543 #define I40E_MODULE_SFF_ADDR_MODE 0x04
544 #define I40E_MODULE_SFF_DIAG_CAPAB 0x40
545 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
546 #define I40E_MODULE_TYPE_QSFP28 0x11
547 #define I40E_MODULE_QSFP_MAX_LEN 640
551 i40e_bus_type_unknown = 0,
554 i40e_bus_type_pci_express,
555 i40e_bus_type_reserved
559 enum i40e_bus_speed {
560 i40e_bus_speed_unknown = 0,
561 i40e_bus_speed_33 = 33,
562 i40e_bus_speed_66 = 66,
563 i40e_bus_speed_100 = 100,
564 i40e_bus_speed_120 = 120,
565 i40e_bus_speed_133 = 133,
566 i40e_bus_speed_2500 = 2500,
567 i40e_bus_speed_5000 = 5000,
568 i40e_bus_speed_8000 = 8000,
569 i40e_bus_speed_reserved
573 enum i40e_bus_width {
574 i40e_bus_width_unknown = 0,
575 i40e_bus_width_pcie_x1 = 1,
576 i40e_bus_width_pcie_x2 = 2,
577 i40e_bus_width_pcie_x4 = 4,
578 i40e_bus_width_pcie_x8 = 8,
579 i40e_bus_width_32 = 32,
580 i40e_bus_width_64 = 64,
581 i40e_bus_width_reserved
585 struct i40e_bus_info {
586 enum i40e_bus_speed speed;
587 enum i40e_bus_width width;
588 enum i40e_bus_type type;
596 /* Flow control (FC) parameters */
597 struct i40e_fc_info {
598 enum i40e_fc_mode current_mode; /* FC mode in effect */
599 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
602 #define I40E_MAX_TRAFFIC_CLASS 8
603 #define I40E_MAX_USER_PRIORITY 8
604 #define I40E_DCBX_MAX_APPS 32
605 #define I40E_LLDPDU_SIZE 1500
606 #define I40E_TLV_STATUS_OPER 0x1
607 #define I40E_TLV_STATUS_SYNC 0x2
608 #define I40E_TLV_STATUS_ERR 0x4
609 #define I40E_CEE_OPER_MAX_APPS 3
610 #define I40E_APP_PROTOID_FCOE 0x8906
611 #define I40E_APP_PROTOID_ISCSI 0x0cbc
612 #define I40E_APP_PROTOID_FIP 0x8914
613 #define I40E_APP_SEL_ETHTYPE 0x1
614 #define I40E_APP_SEL_TCPIP 0x2
615 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
616 #define I40E_CEE_APP_SEL_TCPIP 0x1
618 /* CEE or IEEE 802.1Qaz ETS Configuration data */
619 struct i40e_dcb_ets_config {
623 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
624 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
625 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
628 /* CEE or IEEE 802.1Qaz PFC Configuration data */
629 struct i40e_dcb_pfc_config {
636 /* CEE or IEEE 802.1Qaz Application Priority data */
637 struct i40e_dcb_app_priority_table {
643 struct i40e_dcbx_config {
645 #define I40E_DCBX_MODE_CEE 0x1
646 #define I40E_DCBX_MODE_IEEE 0x2
648 #define I40E_DCBX_APPS_NON_WILLING 0x1
650 u32 tlv_status; /* CEE mode TLV status */
651 struct i40e_dcb_ets_config etscfg;
652 struct i40e_dcb_ets_config etsrec;
653 struct i40e_dcb_pfc_config pfc;
654 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
657 /* Port hardware description */
662 /* subsystem structs */
663 struct i40e_phy_info phy;
664 struct i40e_mac_info mac;
665 struct i40e_bus_info bus;
666 struct i40e_nvm_info nvm;
667 struct i40e_fc_info fc;
672 u16 subsystem_device_id;
673 u16 subsystem_vendor_id;
676 bool adapter_stopped;
678 /* capabilities for entire device and PCI func */
679 struct i40e_hw_capabilities dev_caps;
680 struct i40e_hw_capabilities func_caps;
682 /* Flow Director shared filter space */
683 u16 fdir_shared_filter_count;
685 /* device profile info */
689 /* for multi-function MACs */
694 /* Closest numa node to the device */
697 /* Admin Queue info */
698 struct i40e_adminq_info aq;
700 /* state of nvm update process */
701 enum i40e_nvmupd_state nvmupd_state;
702 struct i40e_aq_desc nvm_wb_desc;
703 struct i40e_virt_mem nvm_buff;
704 bool nvm_release_on_done;
708 struct i40e_hmc_info hmc; /* HMC info struct */
710 /* LLDP/DCBX Status */
714 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
715 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
716 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
718 /* WoL and proxy support */
719 u16 num_wol_proxy_filters;
720 u16 wol_proxy_vsi_seid;
722 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
723 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
724 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
727 /* Used in set switch config AQ command */
737 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
739 return (hw->mac.type == I40E_MAC_VF ||
740 hw->mac.type == I40E_MAC_X722_VF);
743 struct i40e_driver_version {
748 u8 driver_string[32];
752 union i40e_16byte_rx_desc {
754 __le64 pkt_addr; /* Packet buffer address */
755 __le64 hdr_addr; /* Header buffer address */
761 __le16 mirroring_status;
767 __le32 rss; /* RSS Hash */
768 __le32 fd_id; /* Flow director filter id */
769 __le32 fcoe_param; /* FCoE DDP Context id */
773 /* ext status/error/pktype/length */
774 __le64 status_error_len;
776 } wb; /* writeback */
779 union i40e_32byte_rx_desc {
781 __le64 pkt_addr; /* Packet buffer address */
782 __le64 hdr_addr; /* Header buffer address */
783 /* bit 0 of hdr_buffer_addr is DD bit */
791 __le16 mirroring_status;
797 __le32 rss; /* RSS Hash */
798 __le32 fcoe_param; /* FCoE DDP Context id */
799 /* Flow director filter id in case of
800 * Programming status desc WB
806 /* status/error/pktype/length */
807 __le64 status_error_len;
810 __le16 ext_status; /* extended status */
817 __le32 flex_bytes_lo;
821 __le32 flex_bytes_hi;
825 } wb; /* writeback */
828 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
829 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
830 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
831 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
832 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
833 I40E_RXD_QW0_FCOEINDX_SHIFT)
835 enum i40e_rx_desc_status_bits {
836 /* Note: These are predefined bit offsets */
837 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
838 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
839 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
840 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
841 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
842 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
843 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
844 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
846 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
847 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
848 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
849 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
850 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
851 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
852 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
853 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
856 #define I40E_RXD_QW1_STATUS_SHIFT 0
857 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
858 I40E_RXD_QW1_STATUS_SHIFT)
860 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
861 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
862 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
864 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
865 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
867 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
868 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
869 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
871 enum i40e_rx_desc_fltstat_values {
872 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
873 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
874 I40E_RX_DESC_FLTSTAT_RSV = 2,
875 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
878 #define I40E_RXD_PACKET_TYPE_UNICAST 0
879 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
880 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
881 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
883 #define I40E_RXD_QW1_ERROR_SHIFT 19
884 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
886 enum i40e_rx_desc_error_bits {
887 /* Note: These are predefined bit offsets */
888 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
889 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
890 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
891 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
892 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
893 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
894 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
895 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
896 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
899 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
900 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
901 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
902 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
903 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
904 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
907 #define I40E_RXD_QW1_PTYPE_SHIFT 30
908 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
910 /* Packet type non-ip values */
911 enum i40e_rx_l2_ptype {
912 I40E_RX_PTYPE_L2_RESERVED = 0,
913 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
914 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
915 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
916 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
917 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
918 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
919 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
920 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
921 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
922 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
923 I40E_RX_PTYPE_L2_ARP = 11,
924 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
925 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
926 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
927 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
928 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
929 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
930 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
931 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
932 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
933 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
934 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
935 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
936 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
937 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
940 struct i40e_rx_ptype_decoded {
947 u32 tunnel_end_prot:2;
948 u32 tunnel_end_frag:1;
953 enum i40e_rx_ptype_outer_ip {
954 I40E_RX_PTYPE_OUTER_L2 = 0,
955 I40E_RX_PTYPE_OUTER_IP = 1
958 enum i40e_rx_ptype_outer_ip_ver {
959 I40E_RX_PTYPE_OUTER_NONE = 0,
960 I40E_RX_PTYPE_OUTER_IPV4 = 0,
961 I40E_RX_PTYPE_OUTER_IPV6 = 1
964 enum i40e_rx_ptype_outer_fragmented {
965 I40E_RX_PTYPE_NOT_FRAG = 0,
966 I40E_RX_PTYPE_FRAG = 1
969 enum i40e_rx_ptype_tunnel_type {
970 I40E_RX_PTYPE_TUNNEL_NONE = 0,
971 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
972 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
973 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
974 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
977 enum i40e_rx_ptype_tunnel_end_prot {
978 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
979 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
980 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
983 enum i40e_rx_ptype_inner_prot {
984 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
985 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
986 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
987 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
988 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
989 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
992 enum i40e_rx_ptype_payload_layer {
993 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
994 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
995 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
996 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
999 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
1000 #define I40E_RX_PTYPE_SHIFT 56
1002 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
1003 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
1004 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1006 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
1007 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
1008 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1010 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
1011 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1013 #define I40E_RXD_QW1_NEXTP_SHIFT 38
1014 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1016 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
1017 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
1018 I40E_RXD_QW2_EXT_STATUS_SHIFT)
1020 enum i40e_rx_desc_ext_status_bits {
1021 /* Note: These are predefined bit offsets */
1022 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
1023 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1024 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1025 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1026 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1027 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1028 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1031 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1032 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1034 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1035 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1037 enum i40e_rx_desc_pe_status_bits {
1038 /* Note: These are predefined bit offsets */
1039 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1040 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1041 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1042 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1043 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1044 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1045 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1046 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1047 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1050 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1051 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1053 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1054 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1055 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1057 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1058 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1059 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1061 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1062 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1063 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1065 enum i40e_rx_prog_status_desc_status_bits {
1066 /* Note: These are predefined bit offsets */
1067 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1068 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1071 enum i40e_rx_prog_status_desc_prog_id_masks {
1072 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1073 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1074 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1077 enum i40e_rx_prog_status_desc_error_bits {
1078 /* Note: These are predefined bit offsets */
1079 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1080 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1081 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1082 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1085 #define I40E_TWO_BIT_MASK 0x3
1086 #define I40E_THREE_BIT_MASK 0x7
1087 #define I40E_FOUR_BIT_MASK 0xF
1088 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1091 struct i40e_tx_desc {
1092 __le64 buffer_addr; /* Address of descriptor's data buf */
1093 __le64 cmd_type_offset_bsz;
1096 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1097 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1099 enum i40e_tx_desc_dtype_value {
1100 I40E_TX_DESC_DTYPE_DATA = 0x0,
1101 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1102 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1103 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1104 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1105 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1106 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1107 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1108 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1109 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1112 #define I40E_TXD_QW1_CMD_SHIFT 4
1113 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1115 enum i40e_tx_desc_cmd_bits {
1116 I40E_TX_DESC_CMD_EOP = 0x0001,
1117 I40E_TX_DESC_CMD_RS = 0x0002,
1118 I40E_TX_DESC_CMD_ICRC = 0x0004,
1119 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1120 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1121 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1122 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1123 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1124 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1125 I40E_TX_DESC_CMD_FCOET = 0x0080,
1126 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1127 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1128 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1129 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1130 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1131 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1132 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1133 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1136 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1137 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1138 I40E_TXD_QW1_OFFSET_SHIFT)
1140 enum i40e_tx_desc_length_fields {
1141 /* Note: These are predefined bit offsets */
1142 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1143 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1144 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1147 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1148 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1149 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1150 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1152 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1153 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1154 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1156 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1157 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1159 /* Context descriptors */
1160 struct i40e_tx_context_desc {
1161 __le32 tunneling_params;
1164 __le64 type_cmd_tso_mss;
1167 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1168 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1170 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1171 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1173 enum i40e_tx_ctx_desc_cmd_bits {
1174 I40E_TX_CTX_DESC_TSO = 0x01,
1175 I40E_TX_CTX_DESC_TSYN = 0x02,
1176 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1177 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1178 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1179 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1180 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1181 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1182 I40E_TX_CTX_DESC_SWPE = 0x40
1185 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1186 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1187 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1189 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1190 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1191 I40E_TXD_CTX_QW1_MSS_SHIFT)
1193 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1194 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1196 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1197 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1198 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1200 enum i40e_tx_ctx_desc_eipt_offload {
1201 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1202 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1203 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1204 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1207 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1208 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1209 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1211 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1212 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1214 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1215 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1217 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1218 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1220 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1222 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1223 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1224 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1226 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1227 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1228 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1230 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1231 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1232 struct i40e_nop_desc {
1237 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1238 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1240 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1241 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1243 enum i40e_tx_nop_desc_cmd_bits {
1244 /* Note: These are predefined bit offsets */
1245 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1246 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1247 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1250 struct i40e_filter_program_desc {
1251 __le32 qindex_flex_ptype_vsi;
1253 __le32 dtype_cmd_cntindex;
1256 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1257 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1258 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1259 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1260 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1261 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1262 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1263 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1264 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1266 /* Packet Classifier Types for filters */
1267 enum i40e_filter_pctype {
1268 /* Note: Values 0-28 are reserved for future use.
1269 * Value 29, 30, 32 are not supported on XL710 and X710.
1271 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1272 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1273 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1274 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1275 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1276 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1277 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1278 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1279 /* Note: Values 37-38 are reserved for future use.
1280 * Value 39, 40, 42 are not supported on XL710 and X710.
1282 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1283 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1284 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1285 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1286 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1287 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1288 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1289 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1290 /* Note: Value 47 is reserved for future use */
1291 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1292 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1293 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1294 /* Note: Values 51-62 are reserved for future use */
1295 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1298 enum i40e_filter_program_desc_dest {
1299 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1300 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1301 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1304 enum i40e_filter_program_desc_fd_status {
1305 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1306 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1307 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1308 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1311 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1312 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1313 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1315 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1316 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1318 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1319 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1320 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1322 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1323 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1325 enum i40e_filter_program_desc_pcmd {
1326 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1327 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1330 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1331 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1333 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1334 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1336 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1337 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1338 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1339 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1341 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1342 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1343 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1345 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1346 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1347 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1349 enum i40e_filter_type {
1350 I40E_FLOW_DIRECTOR_FLTR = 0,
1351 I40E_PE_QUAD_HASH_FLTR = 1,
1352 I40E_ETHERTYPE_FLTR,
1358 struct i40e_vsi_context {
1363 u16 vsis_unallocated;
1368 struct i40e_aqc_vsi_properties_data info;
1371 struct i40e_veb_context {
1376 u16 vebs_unallocated;
1378 struct i40e_aqc_get_veb_parameters_completion info;
1381 /* Statistics collected by each port, VSI, VEB, and S-channel */
1382 struct i40e_eth_stats {
1383 u64 rx_bytes; /* gorc */
1384 u64 rx_unicast; /* uprc */
1385 u64 rx_multicast; /* mprc */
1386 u64 rx_broadcast; /* bprc */
1387 u64 rx_discards; /* rdpc */
1388 u64 rx_unknown_protocol; /* rupp */
1389 u64 tx_bytes; /* gotc */
1390 u64 tx_unicast; /* uptc */
1391 u64 tx_multicast; /* mptc */
1392 u64 tx_broadcast; /* bptc */
1393 u64 tx_discards; /* tdpc */
1394 u64 tx_errors; /* tepc */
1397 /* Statistics collected per VEB per TC */
1398 struct i40e_veb_tc_stats {
1399 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1400 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1401 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1402 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1405 /* Statistics collected per function for FCoE */
1406 struct i40e_fcoe_stats {
1407 u64 rx_fcoe_packets; /* fcoeprc */
1408 u64 rx_fcoe_dwords; /* focedwrc */
1409 u64 rx_fcoe_dropped; /* fcoerpdc */
1410 u64 tx_fcoe_packets; /* fcoeptc */
1411 u64 tx_fcoe_dwords; /* focedwtc */
1412 u64 fcoe_bad_fccrc; /* fcoecrc */
1413 u64 fcoe_last_error; /* fcoelast */
1414 u64 fcoe_ddp_count; /* fcoeddpc */
1417 /* offset to per function FCoE statistics block */
1418 #define I40E_FCOE_VF_STAT_OFFSET 0
1419 #define I40E_FCOE_PF_STAT_OFFSET 128
1420 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1422 /* Statistics collected by the MAC */
1423 struct i40e_hw_port_stats {
1424 /* eth stats collected by the port */
1425 struct i40e_eth_stats eth;
1427 /* additional port specific stats */
1428 u64 tx_dropped_link_down; /* tdold */
1429 u64 crc_errors; /* crcerrs */
1430 u64 illegal_bytes; /* illerrc */
1431 u64 error_bytes; /* errbc */
1432 u64 mac_local_faults; /* mlfc */
1433 u64 mac_remote_faults; /* mrfc */
1434 u64 rx_length_errors; /* rlec */
1435 u64 link_xon_rx; /* lxonrxc */
1436 u64 link_xoff_rx; /* lxoffrxc */
1437 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1438 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1439 u64 link_xon_tx; /* lxontxc */
1440 u64 link_xoff_tx; /* lxofftxc */
1441 u64 priority_xon_tx[8]; /* pxontxc[8] */
1442 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1443 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1444 u64 rx_size_64; /* prc64 */
1445 u64 rx_size_127; /* prc127 */
1446 u64 rx_size_255; /* prc255 */
1447 u64 rx_size_511; /* prc511 */
1448 u64 rx_size_1023; /* prc1023 */
1449 u64 rx_size_1522; /* prc1522 */
1450 u64 rx_size_big; /* prc9522 */
1451 u64 rx_undersize; /* ruc */
1452 u64 rx_fragments; /* rfc */
1453 u64 rx_oversize; /* roc */
1454 u64 rx_jabber; /* rjc */
1455 u64 tx_size_64; /* ptc64 */
1456 u64 tx_size_127; /* ptc127 */
1457 u64 tx_size_255; /* ptc255 */
1458 u64 tx_size_511; /* ptc511 */
1459 u64 tx_size_1023; /* ptc1023 */
1460 u64 tx_size_1522; /* ptc1522 */
1461 u64 tx_size_big; /* ptc9522 */
1462 u64 mac_short_packet_dropped; /* mspdc */
1463 u64 checksum_error; /* xec */
1464 /* flow director stats */
1467 u64 fd_atr_tunnel_match;
1473 u64 tx_lpi_count; /* etlpic */
1474 u64 rx_lpi_count; /* erlpic */
1477 /* Checksum and Shadow RAM pointers */
1478 #define I40E_SR_NVM_CONTROL_WORD 0x00
1479 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1480 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1481 #define I40E_SR_OPTION_ROM_PTR 0x05
1482 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1483 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1484 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1485 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1486 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1487 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1488 #define I40E_SR_PE_IMAGE_PTR 0x0C
1489 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1490 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1491 #define I40E_SR_EMP_MODULE_PTR 0x0F
1492 #define I40E_SR_PBA_FLAGS 0x15
1493 #define I40E_SR_PBA_BLOCK_PTR 0x16
1494 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1495 #define I40E_NVM_OEM_VER_OFF 0x83
1496 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1497 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1498 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1499 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1500 #define I40E_SR_NVM_MAP_VERSION 0x29
1501 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1502 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1503 #define I40E_SR_NVM_EETRACK_LO 0x2D
1504 #define I40E_SR_NVM_EETRACK_HI 0x2E
1505 #define I40E_SR_VPD_PTR 0x2F
1506 #define I40E_SR_PXE_SETUP_PTR 0x30
1507 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1508 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1509 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1510 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1511 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1512 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1513 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1514 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1515 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1516 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1517 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1518 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1519 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1520 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1521 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1522 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1523 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1524 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1525 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1527 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1528 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1529 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1530 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1531 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1533 /* Shadow RAM related */
1534 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1535 #define I40E_SR_BUF_ALIGNMENT 4096
1536 #define I40E_SR_WORDS_IN_1KB 512
1537 /* Checksum should be calculated such that after adding all the words,
1538 * including the checksum word itself, the sum should be 0xBABA.
1540 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1542 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1544 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1546 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1547 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1548 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1549 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1550 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1551 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1552 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1553 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1554 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1555 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1556 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1557 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1558 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1559 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1562 /* FCoE DIF/DIX Context descriptor */
1563 struct i40e_fcoe_difdix_context_desc {
1564 __le64 flags_buff0_buff1_ref;
1565 __le64 difapp_msk_bias;
1568 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1569 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1570 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1572 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1574 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1576 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1578 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1580 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1582 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1584 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1586 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1588 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1590 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1592 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1594 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1596 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1598 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1600 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1602 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1604 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1606 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1608 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1610 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1612 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1614 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1617 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1618 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1619 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1621 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1622 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1623 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1625 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1626 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1627 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1629 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1630 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1631 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1633 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1634 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1635 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1637 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1638 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1639 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1641 /* FCoE DIF/DIX Buffers descriptor */
1642 struct i40e_fcoe_difdix_buffers_desc {
1647 /* FCoE DDP Context descriptor */
1648 struct i40e_fcoe_ddp_context_desc {
1650 __le64 type_cmd_foff_lsize;
1653 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1654 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1655 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1657 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1658 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1659 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1661 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1662 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1663 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1664 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1665 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1666 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1667 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1670 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1671 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1672 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1674 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1675 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1676 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1678 /* FCoE DDP/DWO Queue Context descriptor */
1679 struct i40e_fcoe_queue_context_desc {
1680 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1681 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1684 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1685 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1686 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1688 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1689 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1690 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1692 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1693 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1694 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1696 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1697 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1698 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1700 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1701 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1702 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1705 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1706 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1707 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1709 /* FCoE DDP/DWO Filter Context descriptor */
1710 struct i40e_fcoe_filter_context_desc {
1714 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1715 __le16 rsvd_dmaindx;
1717 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1718 __le64 flags_rsvd_lanq;
1721 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1722 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1723 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1725 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1726 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1727 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1728 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1729 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1730 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1731 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1734 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1735 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1736 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1738 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1739 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1740 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1742 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1743 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1744 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1746 enum i40e_switch_element_types {
1747 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1748 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1749 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1750 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1751 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1752 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1753 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1754 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1755 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1758 /* Supported EtherType filters */
1759 enum i40e_ether_type_index {
1760 I40E_ETHER_TYPE_1588 = 0,
1761 I40E_ETHER_TYPE_FIP = 1,
1762 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1763 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1764 I40E_ETHER_TYPE_LLDP = 4,
1765 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1766 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1767 I40E_ETHER_TYPE_QCN_CNM = 7,
1768 I40E_ETHER_TYPE_8021X = 8,
1769 I40E_ETHER_TYPE_ARP = 9,
1770 I40E_ETHER_TYPE_RSV1 = 10,
1771 I40E_ETHER_TYPE_RSV2 = 11,
1774 /* Filter context base size is 1K */
1775 #define I40E_HASH_FILTER_BASE_SIZE 1024
1776 /* Supported Hash filter values */
1777 enum i40e_hash_filter_size {
1778 I40E_HASH_FILTER_SIZE_1K = 0,
1779 I40E_HASH_FILTER_SIZE_2K = 1,
1780 I40E_HASH_FILTER_SIZE_4K = 2,
1781 I40E_HASH_FILTER_SIZE_8K = 3,
1782 I40E_HASH_FILTER_SIZE_16K = 4,
1783 I40E_HASH_FILTER_SIZE_32K = 5,
1784 I40E_HASH_FILTER_SIZE_64K = 6,
1785 I40E_HASH_FILTER_SIZE_128K = 7,
1786 I40E_HASH_FILTER_SIZE_256K = 8,
1787 I40E_HASH_FILTER_SIZE_512K = 9,
1788 I40E_HASH_FILTER_SIZE_1M = 10,
1791 /* DMA context base size is 0.5K */
1792 #define I40E_DMA_CNTX_BASE_SIZE 512
1793 /* Supported DMA context values */
1794 enum i40e_dma_cntx_size {
1795 I40E_DMA_CNTX_SIZE_512 = 0,
1796 I40E_DMA_CNTX_SIZE_1K = 1,
1797 I40E_DMA_CNTX_SIZE_2K = 2,
1798 I40E_DMA_CNTX_SIZE_4K = 3,
1799 I40E_DMA_CNTX_SIZE_8K = 4,
1800 I40E_DMA_CNTX_SIZE_16K = 5,
1801 I40E_DMA_CNTX_SIZE_32K = 6,
1802 I40E_DMA_CNTX_SIZE_64K = 7,
1803 I40E_DMA_CNTX_SIZE_128K = 8,
1804 I40E_DMA_CNTX_SIZE_256K = 9,
1807 /* Supported Hash look up table (LUT) sizes */
1808 enum i40e_hash_lut_size {
1809 I40E_HASH_LUT_SIZE_128 = 0,
1810 I40E_HASH_LUT_SIZE_512 = 1,
1813 /* Structure to hold a per PF filter control settings */
1814 struct i40e_filter_control_settings {
1815 /* number of PE Quad Hash filter buckets */
1816 enum i40e_hash_filter_size pe_filt_num;
1817 /* number of PE Quad Hash contexts */
1818 enum i40e_dma_cntx_size pe_cntx_num;
1819 /* number of FCoE filter buckets */
1820 enum i40e_hash_filter_size fcoe_filt_num;
1821 /* number of FCoE DDP contexts */
1822 enum i40e_dma_cntx_size fcoe_cntx_num;
1823 /* size of the Hash LUT */
1824 enum i40e_hash_lut_size hash_lut_size;
1825 /* enable FDIR filters for PF and its VFs */
1827 /* enable Ethertype filters for PF and its VFs */
1828 bool enable_ethtype;
1829 /* enable MAC/VLAN filters for PF and its VFs */
1830 bool enable_macvlan;
1833 /* Structure to hold device level control filter counts */
1834 struct i40e_control_filter_stats {
1835 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1836 u16 etype_used; /* Used perfect EtherType filters */
1837 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1838 u16 etype_free; /* Un-used perfect EtherType filters */
1841 enum i40e_reset_type {
1843 I40E_RESET_CORER = 1,
1844 I40E_RESET_GLOBR = 2,
1845 I40E_RESET_EMPR = 3,
1848 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1849 #define I40E_NVM_LLDP_CFG_PTR 0xD
1850 struct i40e_lldp_variables {
1860 /* Offsets into Alternate Ram */
1861 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1862 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1863 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1864 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1865 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1866 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1868 /* Alternate Ram Bandwidth Masks */
1869 #define I40E_ALT_BW_VALUE_MASK 0xFF
1870 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1871 #define I40E_ALT_BW_VALID_MASK 0x80000000
1873 /* RSS Hash Table Size */
1874 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1876 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1877 #define I40E_L3_SRC_SHIFT 47
1878 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1879 #define I40E_L3_V6_SRC_SHIFT 43
1880 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1881 #define I40E_L3_DST_SHIFT 35
1882 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1883 #define I40E_L3_V6_DST_SHIFT 35
1884 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1885 #define I40E_L4_SRC_SHIFT 34
1886 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1887 #define I40E_L4_DST_SHIFT 33
1888 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1889 #define I40E_VERIFY_TAG_SHIFT 31
1890 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1892 #define I40E_FLEX_50_SHIFT 13
1893 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1894 #define I40E_FLEX_51_SHIFT 12
1895 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1896 #define I40E_FLEX_52_SHIFT 11
1897 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1898 #define I40E_FLEX_53_SHIFT 10
1899 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1900 #define I40E_FLEX_54_SHIFT 9
1901 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1902 #define I40E_FLEX_55_SHIFT 8
1903 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1904 #define I40E_FLEX_56_SHIFT 7
1905 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1906 #define I40E_FLEX_57_SHIFT 6
1907 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1909 /* Version format for Dynamic Device Personalization(DDP) */
1910 struct i40e_ddp_version {
1917 #define I40E_DDP_NAME_SIZE 32
1919 /* Package header */
1920 struct i40e_package_header {
1921 struct i40e_ddp_version version;
1923 u32 segment_offset[1];
1926 /* Generic segment header */
1927 struct i40e_generic_seg_header {
1928 #define SEGMENT_TYPE_METADATA 0x00000001
1929 #define SEGMENT_TYPE_NOTES 0x00000002
1930 #define SEGMENT_TYPE_I40E 0x00000011
1931 #define SEGMENT_TYPE_X722 0x00000012
1933 struct i40e_ddp_version version;
1935 char name[I40E_DDP_NAME_SIZE];
1938 struct i40e_metadata_segment {
1939 struct i40e_generic_seg_header header;
1940 struct i40e_ddp_version version;
1941 #define I40E_DDP_TRACKID_RDONLY 0
1942 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
1944 char name[I40E_DDP_NAME_SIZE];
1947 struct i40e_device_id_entry {
1949 u32 sub_vendor_dev_id;
1952 struct i40e_profile_segment {
1953 struct i40e_generic_seg_header header;
1954 struct i40e_ddp_version version;
1955 char name[I40E_DDP_NAME_SIZE];
1956 u32 device_table_count;
1957 struct i40e_device_id_entry device_table[1];
1960 struct i40e_section_table {
1962 u32 section_offset[1];
1965 struct i40e_profile_section_header {
1969 #define SECTION_TYPE_INFO 0x00000010
1970 #define SECTION_TYPE_MMIO 0x00000800
1971 #define SECTION_TYPE_RB_MMIO 0x00001800
1972 #define SECTION_TYPE_AQ 0x00000801
1973 #define SECTION_TYPE_RB_AQ 0x00001801
1974 #define SECTION_TYPE_NOTE 0x80000000
1975 #define SECTION_TYPE_NAME 0x80000001
1976 #define SECTION_TYPE_PROTO 0x80000002
1977 #define SECTION_TYPE_PCTYPE 0x80000003
1978 #define SECTION_TYPE_PTYPE 0x80000004
1985 struct i40e_profile_tlv_section_record {
1992 /* Generic AQ section in proflie */
1993 struct i40e_profile_aq_section {
2001 struct i40e_profile_info {
2003 struct i40e_ddp_version version;
2005 #define I40E_DDP_ADD_TRACKID 0x01
2006 #define I40E_DDP_REMOVE_TRACKID 0x02
2008 u8 name[I40E_DDP_NAME_SIZE];
2010 #endif /* _I40E_TYPE_H_ */