1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Max timeout in ms for the phy to respond */
81 #define I40E_MAX_PHY_TIMEOUT 500
83 /* Check whether address is multicast. */
84 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
86 /* Check whether an address is broadcast. */
87 #define I40E_IS_BROADCAST(address) \
88 ((((u8 *)(address))[0] == ((u8)0xff)) && \
89 (((u8 *)(address))[1] == ((u8)0xff)))
91 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
92 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
94 /* forward declaration */
96 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
101 /* Data type manipulation macros. */
102 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
103 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
105 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
106 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
108 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
109 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
111 /* Number of Transmit Descriptors must be a multiple of 8. */
112 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
113 /* Number of Receive Descriptors must be a multiple of 32 if
114 * the number of descriptors is greater than 32.
116 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
118 #define I40E_DESC_UNUSED(R) \
119 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
120 (R)->next_to_clean - (R)->next_to_use - 1)
122 /* bitfields for Tx queue mapping in QTX_CTL */
123 #define I40E_QTX_CTL_VF_QUEUE 0x0
124 #define I40E_QTX_CTL_VM_QUEUE 0x1
125 #define I40E_QTX_CTL_PF_QUEUE 0x2
127 /* debug masks - set these bits in hw->debug_mask to control output */
128 enum i40e_debug_mask {
129 I40E_DEBUG_INIT = 0x00000001,
130 I40E_DEBUG_RELEASE = 0x00000002,
132 I40E_DEBUG_LINK = 0x00000010,
133 I40E_DEBUG_PHY = 0x00000020,
134 I40E_DEBUG_HMC = 0x00000040,
135 I40E_DEBUG_NVM = 0x00000080,
136 I40E_DEBUG_LAN = 0x00000100,
137 I40E_DEBUG_FLOW = 0x00000200,
138 I40E_DEBUG_DCB = 0x00000400,
139 I40E_DEBUG_DIAG = 0x00000800,
140 I40E_DEBUG_FD = 0x00001000,
141 I40E_DEBUG_PACKAGE = 0x00002000,
143 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
144 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
145 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
146 I40E_DEBUG_AQ_COMMAND = 0x06000000,
147 I40E_DEBUG_AQ = 0x0F000000,
149 I40E_DEBUG_USER = 0xF0000000,
151 I40E_DEBUG_ALL = 0xFFFFFFFF
155 #define I40E_PCI_LINK_STATUS 0xB2
156 #define I40E_PCI_LINK_WIDTH 0x3F0
157 #define I40E_PCI_LINK_WIDTH_1 0x10
158 #define I40E_PCI_LINK_WIDTH_2 0x20
159 #define I40E_PCI_LINK_WIDTH_4 0x40
160 #define I40E_PCI_LINK_WIDTH_8 0x80
161 #define I40E_PCI_LINK_SPEED 0xF
162 #define I40E_PCI_LINK_SPEED_2500 0x1
163 #define I40E_PCI_LINK_SPEED_5000 0x2
164 #define I40E_PCI_LINK_SPEED_8000 0x3
166 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
167 I40E_GLGEN_MSCA_STCODE_SHIFT)
168 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
169 I40E_GLGEN_MSCA_OPCODE_SHIFT)
170 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
171 I40E_GLGEN_MSCA_OPCODE_SHIFT)
173 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
174 I40E_GLGEN_MSCA_STCODE_SHIFT)
175 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
176 I40E_GLGEN_MSCA_OPCODE_SHIFT)
177 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
178 I40E_GLGEN_MSCA_OPCODE_SHIFT)
179 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
180 I40E_GLGEN_MSCA_OPCODE_SHIFT)
181 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
182 I40E_GLGEN_MSCA_OPCODE_SHIFT)
184 #define I40E_PHY_COM_REG_PAGE 0x1E
185 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
186 #define I40E_PHY_LED_MANUAL_ON 0x100
187 #define I40E_PHY_LED_PROV_REG_1 0xC430
188 #define I40E_PHY_LED_MODE_MASK 0xFFFF
189 #define I40E_PHY_LED_MODE_ORIG 0x80000000
192 enum i40e_memset_type {
198 enum i40e_memcpy_type {
199 I40E_NONDMA_TO_NONDMA = 0,
205 /* These are structs for managing the hardware information and the operations.
206 * The structures of function pointers are filled out at init time when we
207 * know for sure exactly which hardware we're working with. This gives us the
208 * flexibility of using the same main driver code but adapting to slightly
209 * different hardware needs as new parts are developed. For this architecture,
210 * the Firmware and AdminQ are intended to insulate the driver from most of the
211 * future changes, but these structures will also do part of the job.
214 I40E_MAC_UNKNOWN = 0,
222 enum i40e_media_type {
223 I40E_MEDIA_TYPE_UNKNOWN = 0,
224 I40E_MEDIA_TYPE_FIBER,
225 I40E_MEDIA_TYPE_BASET,
226 I40E_MEDIA_TYPE_BACKPLANE,
229 I40E_MEDIA_TYPE_VIRTUAL
241 enum i40e_set_fc_aq_failures {
242 I40E_SET_FC_AQ_FAIL_NONE = 0,
243 I40E_SET_FC_AQ_FAIL_GET = 1,
244 I40E_SET_FC_AQ_FAIL_SET = 2,
245 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
246 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
258 I40E_VSI_TYPE_UNKNOWN
261 enum i40e_queue_type {
262 I40E_QUEUE_TYPE_RX = 0,
264 I40E_QUEUE_TYPE_PE_CEQ,
265 I40E_QUEUE_TYPE_UNKNOWN
268 struct i40e_link_status {
269 enum i40e_aq_phy_type phy_type;
270 enum i40e_aq_link_speed link_speed;
277 /* is Link Status Event notification to SW enabled */
284 /* 1st byte: module identifier */
285 #define I40E_MODULE_TYPE_SFP 0x03
286 #define I40E_MODULE_TYPE_QSFP 0x0D
287 /* 2nd byte: ethernet compliance codes for 10/40G */
288 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
289 #define I40E_MODULE_TYPE_40G_LR4 0x02
290 #define I40E_MODULE_TYPE_40G_SR4 0x04
291 #define I40E_MODULE_TYPE_40G_CR4 0x08
292 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
293 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
294 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
295 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
296 /* 3rd byte: ethernet compliance codes for 1G */
297 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
298 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
299 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
300 #define I40E_MODULE_TYPE_1000BASE_T 0x08
303 struct i40e_phy_info {
304 struct i40e_link_status link_info;
305 struct i40e_link_status link_info_old;
307 enum i40e_media_type media_type;
308 /* all the phy types the NVM is capable of */
312 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
313 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
314 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
315 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
316 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
317 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
318 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
319 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
320 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
321 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
323 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
324 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
325 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
326 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
327 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
328 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
329 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
330 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
331 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
332 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
333 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
334 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
335 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
336 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
337 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
338 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
339 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
340 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
342 * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
343 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
344 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
345 * a shift is needed to adjust for this with values larger than 31. The
346 * only affected values are I40E_PHY_TYPE_25GBASE_*.
348 #define I40E_PHY_TYPE_OFFSET 1
349 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
350 I40E_PHY_TYPE_OFFSET)
351 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
352 I40E_PHY_TYPE_OFFSET)
353 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
354 I40E_PHY_TYPE_OFFSET)
355 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
356 I40E_PHY_TYPE_OFFSET)
357 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
358 I40E_PHY_TYPE_OFFSET)
359 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
360 I40E_PHY_TYPE_OFFSET)
361 #define I40E_HW_CAP_MAX_GPIO 30
362 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
363 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
365 enum i40e_acpi_programming_method {
366 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
367 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
370 #define I40E_WOL_SUPPORT_MASK 0x1
371 #define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
372 #define I40E_PROXY_SUPPORT_MASK 0x4
374 /* Capabilities of a PF or a VF or the whole device */
375 struct i40e_hw_capabilities {
377 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
378 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
379 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
382 u32 mng_protocols_over_mctp;
383 #define I40E_MNG_PROTOCOL_PLDM 0x2
384 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
385 #define I40E_MNG_PROTOCOL_NCSI 0x8
391 bool evb_802_1_qbg; /* Edge Virtual Bridging */
392 bool evb_802_1_qbh; /* Bridge Port Extension */
395 bool iscsi; /* Indicates iSCSI enabled */
399 #define I40E_FLEX10_MODE_UNKNOWN 0x0
400 #define I40E_FLEX10_MODE_DCC 0x1
401 #define I40E_FLEX10_MODE_DCI 0x2
404 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
405 #define I40E_FLEX10_STATUS_VC_MODE 0x2
407 bool sec_rev_disabled;
408 bool update_disabled;
409 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
410 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
416 u32 fd_filters_guaranteed;
417 u32 fd_filters_best_effort;
420 u32 rss_table_entry_width;
421 bool led[I40E_HW_CAP_MAX_GPIO];
422 bool sdp[I40E_HW_CAP_MAX_GPIO];
424 u32 num_flow_director_filters;
431 u32 num_msix_vectors;
432 u32 num_msix_vectors_vf;
441 bool apm_wol_support;
442 enum i40e_acpi_programming_method acpi_prog_method;
446 struct i40e_mac_info {
447 enum i40e_mac_type type;
449 u8 perm_addr[ETH_ALEN];
450 u8 san_addr[ETH_ALEN];
451 u8 port_addr[ETH_ALEN];
455 enum i40e_aq_resources_ids {
456 I40E_NVM_RESOURCE_ID = 1
459 enum i40e_aq_resource_access_type {
460 I40E_RESOURCE_READ = 1,
464 struct i40e_nvm_info {
465 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
466 u32 timeout; /* [ms] */
467 u16 sr_size; /* Shadow RAM size in words */
468 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
469 u16 version; /* NVM package version */
470 u32 eetrack; /* NVM data version */
471 u32 oem_ver; /* OEM version info */
474 /* definitions used in NVM update support */
476 enum i40e_nvmupd_cmd {
478 I40E_NVMUPD_READ_CON,
479 I40E_NVMUPD_READ_SNT,
480 I40E_NVMUPD_READ_LCB,
482 I40E_NVMUPD_WRITE_ERA,
483 I40E_NVMUPD_WRITE_CON,
484 I40E_NVMUPD_WRITE_SNT,
485 I40E_NVMUPD_WRITE_LCB,
486 I40E_NVMUPD_WRITE_SA,
487 I40E_NVMUPD_CSUM_CON,
489 I40E_NVMUPD_CSUM_LCB,
492 I40E_NVMUPD_GET_AQ_RESULT,
495 enum i40e_nvmupd_state {
496 I40E_NVMUPD_STATE_INIT,
497 I40E_NVMUPD_STATE_READING,
498 I40E_NVMUPD_STATE_WRITING,
499 I40E_NVMUPD_STATE_INIT_WAIT,
500 I40E_NVMUPD_STATE_WRITE_WAIT,
501 I40E_NVMUPD_STATE_ERROR
504 /* nvm_access definition and its masks/shifts need to be accessible to
505 * application, core driver, and shared code. Where is the right file?
507 #define I40E_NVM_READ 0xB
508 #define I40E_NVM_WRITE 0xC
510 #define I40E_NVM_MOD_PNT_MASK 0xFF
512 #define I40E_NVM_TRANS_SHIFT 8
513 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
514 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
515 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
516 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
517 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
518 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
519 #define I40E_NVM_CON 0x0
520 #define I40E_NVM_SNT 0x1
521 #define I40E_NVM_LCB 0x2
522 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
523 #define I40E_NVM_ERA 0x4
524 #define I40E_NVM_CSUM 0x8
525 #define I40E_NVM_EXEC 0xf
527 #define I40E_NVM_ADAPT_SHIFT 16
528 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
530 #define I40E_NVMUPD_MAX_DATA 4096
531 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
533 struct i40e_nvm_access {
536 u32 offset; /* in bytes */
537 u32 data_size; /* in bytes */
541 /* (Q)SFP module access definitions */
542 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
543 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
544 #define I40E_MODULE_TYPE_ADDR 0x00
545 #define I40E_MODULE_REVISION_ADDR 0x01
546 #define I40E_MODULE_SFF_8472_COMP 0x5E
547 #define I40E_MODULE_SFF_8472_SWAP 0x5C
548 #define I40E_MODULE_SFF_ADDR_MODE 0x04
549 #define I40E_MODULE_SFF_DIAG_CAPAB 0x40
550 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
551 #define I40E_MODULE_TYPE_QSFP28 0x11
552 #define I40E_MODULE_QSFP_MAX_LEN 640
556 i40e_bus_type_unknown = 0,
559 i40e_bus_type_pci_express,
560 i40e_bus_type_reserved
564 enum i40e_bus_speed {
565 i40e_bus_speed_unknown = 0,
566 i40e_bus_speed_33 = 33,
567 i40e_bus_speed_66 = 66,
568 i40e_bus_speed_100 = 100,
569 i40e_bus_speed_120 = 120,
570 i40e_bus_speed_133 = 133,
571 i40e_bus_speed_2500 = 2500,
572 i40e_bus_speed_5000 = 5000,
573 i40e_bus_speed_8000 = 8000,
574 i40e_bus_speed_reserved
578 enum i40e_bus_width {
579 i40e_bus_width_unknown = 0,
580 i40e_bus_width_pcie_x1 = 1,
581 i40e_bus_width_pcie_x2 = 2,
582 i40e_bus_width_pcie_x4 = 4,
583 i40e_bus_width_pcie_x8 = 8,
584 i40e_bus_width_32 = 32,
585 i40e_bus_width_64 = 64,
586 i40e_bus_width_reserved
590 struct i40e_bus_info {
591 enum i40e_bus_speed speed;
592 enum i40e_bus_width width;
593 enum i40e_bus_type type;
601 /* Flow control (FC) parameters */
602 struct i40e_fc_info {
603 enum i40e_fc_mode current_mode; /* FC mode in effect */
604 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
607 #define I40E_MAX_TRAFFIC_CLASS 8
608 #define I40E_MAX_USER_PRIORITY 8
609 #define I40E_DCBX_MAX_APPS 32
610 #define I40E_LLDPDU_SIZE 1500
611 #define I40E_TLV_STATUS_OPER 0x1
612 #define I40E_TLV_STATUS_SYNC 0x2
613 #define I40E_TLV_STATUS_ERR 0x4
614 #define I40E_CEE_OPER_MAX_APPS 3
615 #define I40E_APP_PROTOID_FCOE 0x8906
616 #define I40E_APP_PROTOID_ISCSI 0x0cbc
617 #define I40E_APP_PROTOID_FIP 0x8914
618 #define I40E_APP_SEL_ETHTYPE 0x1
619 #define I40E_APP_SEL_TCPIP 0x2
620 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
621 #define I40E_CEE_APP_SEL_TCPIP 0x1
623 /* CEE or IEEE 802.1Qaz ETS Configuration data */
624 struct i40e_dcb_ets_config {
628 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
629 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
630 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
633 /* CEE or IEEE 802.1Qaz PFC Configuration data */
634 struct i40e_dcb_pfc_config {
641 /* CEE or IEEE 802.1Qaz Application Priority data */
642 struct i40e_dcb_app_priority_table {
648 struct i40e_dcbx_config {
650 #define I40E_DCBX_MODE_CEE 0x1
651 #define I40E_DCBX_MODE_IEEE 0x2
653 #define I40E_DCBX_APPS_NON_WILLING 0x1
655 u32 tlv_status; /* CEE mode TLV status */
656 struct i40e_dcb_ets_config etscfg;
657 struct i40e_dcb_ets_config etsrec;
658 struct i40e_dcb_pfc_config pfc;
659 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
662 /* Port hardware description */
667 /* subsystem structs */
668 struct i40e_phy_info phy;
669 struct i40e_mac_info mac;
670 struct i40e_bus_info bus;
671 struct i40e_nvm_info nvm;
672 struct i40e_fc_info fc;
677 u16 subsystem_device_id;
678 u16 subsystem_vendor_id;
681 bool adapter_stopped;
683 /* capabilities for entire device and PCI func */
684 struct i40e_hw_capabilities dev_caps;
685 struct i40e_hw_capabilities func_caps;
687 /* Flow Director shared filter space */
688 u16 fdir_shared_filter_count;
690 /* device profile info */
694 /* for multi-function MACs */
699 /* Closest numa node to the device */
702 /* Admin Queue info */
703 struct i40e_adminq_info aq;
705 /* state of nvm update process */
706 enum i40e_nvmupd_state nvmupd_state;
707 struct i40e_aq_desc nvm_wb_desc;
708 struct i40e_virt_mem nvm_buff;
709 bool nvm_release_on_done;
713 struct i40e_hmc_info hmc; /* HMC info struct */
715 /* LLDP/DCBX Status */
719 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
720 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
721 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
723 /* WoL and proxy support */
724 u16 num_wol_proxy_filters;
725 u16 wol_proxy_vsi_seid;
727 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
728 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
729 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
730 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
733 /* Used in set switch config AQ command */
743 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
745 return (hw->mac.type == I40E_MAC_VF ||
746 hw->mac.type == I40E_MAC_X722_VF);
749 struct i40e_driver_version {
754 u8 driver_string[32];
758 union i40e_16byte_rx_desc {
760 __le64 pkt_addr; /* Packet buffer address */
761 __le64 hdr_addr; /* Header buffer address */
767 __le16 mirroring_status;
773 __le32 rss; /* RSS Hash */
774 __le32 fd_id; /* Flow director filter id */
775 __le32 fcoe_param; /* FCoE DDP Context id */
779 /* ext status/error/pktype/length */
780 __le64 status_error_len;
782 } wb; /* writeback */
785 union i40e_32byte_rx_desc {
787 __le64 pkt_addr; /* Packet buffer address */
788 __le64 hdr_addr; /* Header buffer address */
789 /* bit 0 of hdr_buffer_addr is DD bit */
797 __le16 mirroring_status;
803 __le32 rss; /* RSS Hash */
804 __le32 fcoe_param; /* FCoE DDP Context id */
805 /* Flow director filter id in case of
806 * Programming status desc WB
812 /* status/error/pktype/length */
813 __le64 status_error_len;
816 __le16 ext_status; /* extended status */
823 __le32 flex_bytes_lo;
827 __le32 flex_bytes_hi;
831 } wb; /* writeback */
834 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
835 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
836 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
837 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
838 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
839 I40E_RXD_QW0_FCOEINDX_SHIFT)
841 enum i40e_rx_desc_status_bits {
842 /* Note: These are predefined bit offsets */
843 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
844 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
845 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
846 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
847 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
848 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
849 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
850 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
852 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
853 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
854 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
855 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
856 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
857 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
858 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
859 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
862 #define I40E_RXD_QW1_STATUS_SHIFT 0
863 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
864 I40E_RXD_QW1_STATUS_SHIFT)
866 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
867 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
868 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
870 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
871 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
873 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
874 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
875 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
877 enum i40e_rx_desc_fltstat_values {
878 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
879 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
880 I40E_RX_DESC_FLTSTAT_RSV = 2,
881 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
884 #define I40E_RXD_PACKET_TYPE_UNICAST 0
885 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
886 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
887 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
889 #define I40E_RXD_QW1_ERROR_SHIFT 19
890 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
892 enum i40e_rx_desc_error_bits {
893 /* Note: These are predefined bit offsets */
894 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
895 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
896 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
897 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
898 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
899 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
900 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
901 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
902 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
905 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
906 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
907 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
908 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
909 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
910 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
913 #define I40E_RXD_QW1_PTYPE_SHIFT 30
914 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
916 /* Packet type non-ip values */
917 enum i40e_rx_l2_ptype {
918 I40E_RX_PTYPE_L2_RESERVED = 0,
919 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
920 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
921 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
922 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
923 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
924 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
925 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
926 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
927 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
928 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
929 I40E_RX_PTYPE_L2_ARP = 11,
930 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
931 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
932 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
933 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
934 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
935 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
936 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
937 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
938 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
939 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
940 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
941 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
942 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
943 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
946 struct i40e_rx_ptype_decoded {
953 u32 tunnel_end_prot:2;
954 u32 tunnel_end_frag:1;
959 enum i40e_rx_ptype_outer_ip {
960 I40E_RX_PTYPE_OUTER_L2 = 0,
961 I40E_RX_PTYPE_OUTER_IP = 1
964 enum i40e_rx_ptype_outer_ip_ver {
965 I40E_RX_PTYPE_OUTER_NONE = 0,
966 I40E_RX_PTYPE_OUTER_IPV4 = 0,
967 I40E_RX_PTYPE_OUTER_IPV6 = 1
970 enum i40e_rx_ptype_outer_fragmented {
971 I40E_RX_PTYPE_NOT_FRAG = 0,
972 I40E_RX_PTYPE_FRAG = 1
975 enum i40e_rx_ptype_tunnel_type {
976 I40E_RX_PTYPE_TUNNEL_NONE = 0,
977 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
978 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
979 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
980 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
983 enum i40e_rx_ptype_tunnel_end_prot {
984 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
985 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
986 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
989 enum i40e_rx_ptype_inner_prot {
990 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
991 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
992 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
993 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
994 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
995 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
998 enum i40e_rx_ptype_payload_layer {
999 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
1000 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
1001 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
1002 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
1005 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
1006 #define I40E_RX_PTYPE_SHIFT 56
1008 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
1009 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
1010 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1012 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
1013 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
1014 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1016 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
1017 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1019 #define I40E_RXD_QW1_NEXTP_SHIFT 38
1020 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1022 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
1023 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
1024 I40E_RXD_QW2_EXT_STATUS_SHIFT)
1026 enum i40e_rx_desc_ext_status_bits {
1027 /* Note: These are predefined bit offsets */
1028 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
1029 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
1030 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
1031 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
1032 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
1033 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1034 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
1037 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
1038 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1040 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
1041 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1043 enum i40e_rx_desc_pe_status_bits {
1044 /* Note: These are predefined bit offsets */
1045 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
1046 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
1047 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
1048 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
1049 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
1050 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
1051 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
1052 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
1053 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
1056 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1057 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1059 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1060 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1061 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1063 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1064 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1065 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1067 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1068 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1069 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1071 enum i40e_rx_prog_status_desc_status_bits {
1072 /* Note: These are predefined bit offsets */
1073 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1074 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1077 enum i40e_rx_prog_status_desc_prog_id_masks {
1078 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1079 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1080 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1083 enum i40e_rx_prog_status_desc_error_bits {
1084 /* Note: These are predefined bit offsets */
1085 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1086 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1087 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1088 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1091 #define I40E_TWO_BIT_MASK 0x3
1092 #define I40E_THREE_BIT_MASK 0x7
1093 #define I40E_FOUR_BIT_MASK 0xF
1094 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1097 struct i40e_tx_desc {
1098 __le64 buffer_addr; /* Address of descriptor's data buf */
1099 __le64 cmd_type_offset_bsz;
1102 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1103 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1105 enum i40e_tx_desc_dtype_value {
1106 I40E_TX_DESC_DTYPE_DATA = 0x0,
1107 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1108 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1109 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1110 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1111 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1112 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1113 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1114 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1115 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1118 #define I40E_TXD_QW1_CMD_SHIFT 4
1119 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1121 enum i40e_tx_desc_cmd_bits {
1122 I40E_TX_DESC_CMD_EOP = 0x0001,
1123 I40E_TX_DESC_CMD_RS = 0x0002,
1124 I40E_TX_DESC_CMD_ICRC = 0x0004,
1125 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1126 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1127 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1128 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1129 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1130 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1131 I40E_TX_DESC_CMD_FCOET = 0x0080,
1132 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1133 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1134 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1135 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1136 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1137 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1138 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1139 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1142 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1143 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1144 I40E_TXD_QW1_OFFSET_SHIFT)
1146 enum i40e_tx_desc_length_fields {
1147 /* Note: These are predefined bit offsets */
1148 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1149 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1150 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1153 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1154 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1155 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1156 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1158 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1159 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1160 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1162 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1163 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1165 /* Context descriptors */
1166 struct i40e_tx_context_desc {
1167 __le32 tunneling_params;
1170 __le64 type_cmd_tso_mss;
1173 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1174 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1176 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1177 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1179 enum i40e_tx_ctx_desc_cmd_bits {
1180 I40E_TX_CTX_DESC_TSO = 0x01,
1181 I40E_TX_CTX_DESC_TSYN = 0x02,
1182 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1183 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1184 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1185 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1186 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1187 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1188 I40E_TX_CTX_DESC_SWPE = 0x40
1191 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1192 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1193 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1195 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1196 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1197 I40E_TXD_CTX_QW1_MSS_SHIFT)
1199 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1200 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1202 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1203 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1204 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1206 enum i40e_tx_ctx_desc_eipt_offload {
1207 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1208 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1209 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1210 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1213 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1214 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1215 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1217 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1218 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1220 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1221 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1223 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1224 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1226 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1228 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1229 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1230 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1232 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1233 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1234 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1236 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1237 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1238 struct i40e_nop_desc {
1243 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1244 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1246 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1247 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1249 enum i40e_tx_nop_desc_cmd_bits {
1250 /* Note: These are predefined bit offsets */
1251 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1252 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1253 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1256 struct i40e_filter_program_desc {
1257 __le32 qindex_flex_ptype_vsi;
1259 __le32 dtype_cmd_cntindex;
1262 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1263 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1264 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1265 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1266 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1267 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1268 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1269 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1270 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1272 /* Packet Classifier Types for filters */
1273 enum i40e_filter_pctype {
1274 /* Note: Values 0-28 are reserved for future use.
1275 * Value 29, 30, 32 are not supported on XL710 and X710.
1277 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1278 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1279 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1280 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1281 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1282 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1283 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1284 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1285 /* Note: Values 37-38 are reserved for future use.
1286 * Value 39, 40, 42 are not supported on XL710 and X710.
1288 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1289 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1290 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1291 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1292 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1293 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1294 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1295 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1296 /* Note: Value 47 is reserved for future use */
1297 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1298 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1299 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1300 /* Note: Values 51-62 are reserved for future use */
1301 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1304 enum i40e_filter_program_desc_dest {
1305 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1306 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1307 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1310 enum i40e_filter_program_desc_fd_status {
1311 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1312 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1313 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1314 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1317 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1318 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1319 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1321 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1322 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1324 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1325 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1326 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1328 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1329 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1331 enum i40e_filter_program_desc_pcmd {
1332 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1333 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1336 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1337 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1339 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1340 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1342 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1343 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1344 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1345 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1347 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1348 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1349 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1351 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1352 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1353 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1355 enum i40e_filter_type {
1356 I40E_FLOW_DIRECTOR_FLTR = 0,
1357 I40E_PE_QUAD_HASH_FLTR = 1,
1358 I40E_ETHERTYPE_FLTR,
1364 struct i40e_vsi_context {
1369 u16 vsis_unallocated;
1374 struct i40e_aqc_vsi_properties_data info;
1377 struct i40e_veb_context {
1382 u16 vebs_unallocated;
1384 struct i40e_aqc_get_veb_parameters_completion info;
1387 /* Statistics collected by each port, VSI, VEB, and S-channel */
1388 struct i40e_eth_stats {
1389 u64 rx_bytes; /* gorc */
1390 u64 rx_unicast; /* uprc */
1391 u64 rx_multicast; /* mprc */
1392 u64 rx_broadcast; /* bprc */
1393 u64 rx_discards; /* rdpc */
1394 u64 rx_unknown_protocol; /* rupp */
1395 u64 tx_bytes; /* gotc */
1396 u64 tx_unicast; /* uptc */
1397 u64 tx_multicast; /* mptc */
1398 u64 tx_broadcast; /* bptc */
1399 u64 tx_discards; /* tdpc */
1400 u64 tx_errors; /* tepc */
1403 /* Statistics collected per VEB per TC */
1404 struct i40e_veb_tc_stats {
1405 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1406 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1407 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1408 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1411 /* Statistics collected per function for FCoE */
1412 struct i40e_fcoe_stats {
1413 u64 rx_fcoe_packets; /* fcoeprc */
1414 u64 rx_fcoe_dwords; /* focedwrc */
1415 u64 rx_fcoe_dropped; /* fcoerpdc */
1416 u64 tx_fcoe_packets; /* fcoeptc */
1417 u64 tx_fcoe_dwords; /* focedwtc */
1418 u64 fcoe_bad_fccrc; /* fcoecrc */
1419 u64 fcoe_last_error; /* fcoelast */
1420 u64 fcoe_ddp_count; /* fcoeddpc */
1423 /* offset to per function FCoE statistics block */
1424 #define I40E_FCOE_VF_STAT_OFFSET 0
1425 #define I40E_FCOE_PF_STAT_OFFSET 128
1426 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1428 /* Statistics collected by the MAC */
1429 struct i40e_hw_port_stats {
1430 /* eth stats collected by the port */
1431 struct i40e_eth_stats eth;
1433 /* additional port specific stats */
1434 u64 tx_dropped_link_down; /* tdold */
1435 u64 crc_errors; /* crcerrs */
1436 u64 illegal_bytes; /* illerrc */
1437 u64 error_bytes; /* errbc */
1438 u64 mac_local_faults; /* mlfc */
1439 u64 mac_remote_faults; /* mrfc */
1440 u64 rx_length_errors; /* rlec */
1441 u64 link_xon_rx; /* lxonrxc */
1442 u64 link_xoff_rx; /* lxoffrxc */
1443 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1444 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1445 u64 link_xon_tx; /* lxontxc */
1446 u64 link_xoff_tx; /* lxofftxc */
1447 u64 priority_xon_tx[8]; /* pxontxc[8] */
1448 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1449 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1450 u64 rx_size_64; /* prc64 */
1451 u64 rx_size_127; /* prc127 */
1452 u64 rx_size_255; /* prc255 */
1453 u64 rx_size_511; /* prc511 */
1454 u64 rx_size_1023; /* prc1023 */
1455 u64 rx_size_1522; /* prc1522 */
1456 u64 rx_size_big; /* prc9522 */
1457 u64 rx_undersize; /* ruc */
1458 u64 rx_fragments; /* rfc */
1459 u64 rx_oversize; /* roc */
1460 u64 rx_jabber; /* rjc */
1461 u64 tx_size_64; /* ptc64 */
1462 u64 tx_size_127; /* ptc127 */
1463 u64 tx_size_255; /* ptc255 */
1464 u64 tx_size_511; /* ptc511 */
1465 u64 tx_size_1023; /* ptc1023 */
1466 u64 tx_size_1522; /* ptc1522 */
1467 u64 tx_size_big; /* ptc9522 */
1468 u64 mac_short_packet_dropped; /* mspdc */
1469 u64 checksum_error; /* xec */
1470 /* flow director stats */
1473 u64 fd_atr_tunnel_match;
1479 u64 tx_lpi_count; /* etlpic */
1480 u64 rx_lpi_count; /* erlpic */
1483 /* Checksum and Shadow RAM pointers */
1484 #define I40E_SR_NVM_CONTROL_WORD 0x00
1485 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1486 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1487 #define I40E_SR_OPTION_ROM_PTR 0x05
1488 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1489 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1490 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1491 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1492 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1493 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1494 #define I40E_SR_PE_IMAGE_PTR 0x0C
1495 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1496 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1497 #define I40E_SR_EMP_MODULE_PTR 0x0F
1498 #define I40E_SR_PBA_FLAGS 0x15
1499 #define I40E_SR_PBA_BLOCK_PTR 0x16
1500 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1501 #define I40E_NVM_OEM_VER_OFF 0x83
1502 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1503 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1504 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1505 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1506 #define I40E_SR_NVM_MAP_VERSION 0x29
1507 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1508 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1509 #define I40E_SR_NVM_EETRACK_LO 0x2D
1510 #define I40E_SR_NVM_EETRACK_HI 0x2E
1511 #define I40E_SR_VPD_PTR 0x2F
1512 #define I40E_SR_PXE_SETUP_PTR 0x30
1513 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1514 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1515 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1516 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1517 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1518 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1519 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1520 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1521 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1522 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1523 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1524 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1525 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1526 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1527 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1528 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1529 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1530 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1531 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1533 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1534 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1535 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1536 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1537 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1539 /* Shadow RAM related */
1540 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1541 #define I40E_SR_BUF_ALIGNMENT 4096
1542 #define I40E_SR_WORDS_IN_1KB 512
1543 /* Checksum should be calculated such that after adding all the words,
1544 * including the checksum word itself, the sum should be 0xBABA.
1546 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1548 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1550 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1552 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1553 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1554 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1555 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1556 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1557 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1558 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1559 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1560 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1561 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1562 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1563 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1564 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1565 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1568 /* FCoE DIF/DIX Context descriptor */
1569 struct i40e_fcoe_difdix_context_desc {
1570 __le64 flags_buff0_buff1_ref;
1571 __le64 difapp_msk_bias;
1574 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
1575 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
1576 I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1578 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1580 I40E_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
1582 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
1584 I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
1586 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
1588 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
1590 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
1592 I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
1594 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
1596 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
1598 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
1600 I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
1602 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
1604 I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
1606 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
1608 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
1610 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
1612 I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
1614 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
1616 I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
1618 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
1620 I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
1623 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
1624 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
1625 I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1627 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
1628 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
1629 I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1631 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
1632 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
1633 I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1635 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
1636 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
1637 I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1639 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
1640 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
1641 I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1643 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1644 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
1645 I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1647 /* FCoE DIF/DIX Buffers descriptor */
1648 struct i40e_fcoe_difdix_buffers_desc {
1653 /* FCoE DDP Context descriptor */
1654 struct i40e_fcoe_ddp_context_desc {
1656 __le64 type_cmd_foff_lsize;
1659 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1660 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1661 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1663 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1664 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1665 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1667 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1668 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1669 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1670 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1671 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1672 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1673 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1676 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1677 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1678 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1680 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1681 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1682 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1684 /* FCoE DDP/DWO Queue Context descriptor */
1685 struct i40e_fcoe_queue_context_desc {
1686 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1687 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1690 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1691 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1692 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1694 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1695 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1696 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1698 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1699 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1700 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1702 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1703 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1704 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1706 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1707 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1708 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1711 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1712 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1713 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1715 /* FCoE DDP/DWO Filter Context descriptor */
1716 struct i40e_fcoe_filter_context_desc {
1720 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1721 __le16 rsvd_dmaindx;
1723 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1724 __le64 flags_rsvd_lanq;
1727 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1728 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1729 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1731 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1732 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1733 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1734 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1735 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1736 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1737 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1740 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1741 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1742 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1744 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1745 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1746 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1748 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1749 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1750 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1752 enum i40e_switch_element_types {
1753 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1754 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1755 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1756 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1757 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1758 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1759 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1760 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1761 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1764 /* Supported EtherType filters */
1765 enum i40e_ether_type_index {
1766 I40E_ETHER_TYPE_1588 = 0,
1767 I40E_ETHER_TYPE_FIP = 1,
1768 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1769 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1770 I40E_ETHER_TYPE_LLDP = 4,
1771 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1772 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1773 I40E_ETHER_TYPE_QCN_CNM = 7,
1774 I40E_ETHER_TYPE_8021X = 8,
1775 I40E_ETHER_TYPE_ARP = 9,
1776 I40E_ETHER_TYPE_RSV1 = 10,
1777 I40E_ETHER_TYPE_RSV2 = 11,
1780 /* Filter context base size is 1K */
1781 #define I40E_HASH_FILTER_BASE_SIZE 1024
1782 /* Supported Hash filter values */
1783 enum i40e_hash_filter_size {
1784 I40E_HASH_FILTER_SIZE_1K = 0,
1785 I40E_HASH_FILTER_SIZE_2K = 1,
1786 I40E_HASH_FILTER_SIZE_4K = 2,
1787 I40E_HASH_FILTER_SIZE_8K = 3,
1788 I40E_HASH_FILTER_SIZE_16K = 4,
1789 I40E_HASH_FILTER_SIZE_32K = 5,
1790 I40E_HASH_FILTER_SIZE_64K = 6,
1791 I40E_HASH_FILTER_SIZE_128K = 7,
1792 I40E_HASH_FILTER_SIZE_256K = 8,
1793 I40E_HASH_FILTER_SIZE_512K = 9,
1794 I40E_HASH_FILTER_SIZE_1M = 10,
1797 /* DMA context base size is 0.5K */
1798 #define I40E_DMA_CNTX_BASE_SIZE 512
1799 /* Supported DMA context values */
1800 enum i40e_dma_cntx_size {
1801 I40E_DMA_CNTX_SIZE_512 = 0,
1802 I40E_DMA_CNTX_SIZE_1K = 1,
1803 I40E_DMA_CNTX_SIZE_2K = 2,
1804 I40E_DMA_CNTX_SIZE_4K = 3,
1805 I40E_DMA_CNTX_SIZE_8K = 4,
1806 I40E_DMA_CNTX_SIZE_16K = 5,
1807 I40E_DMA_CNTX_SIZE_32K = 6,
1808 I40E_DMA_CNTX_SIZE_64K = 7,
1809 I40E_DMA_CNTX_SIZE_128K = 8,
1810 I40E_DMA_CNTX_SIZE_256K = 9,
1813 /* Supported Hash look up table (LUT) sizes */
1814 enum i40e_hash_lut_size {
1815 I40E_HASH_LUT_SIZE_128 = 0,
1816 I40E_HASH_LUT_SIZE_512 = 1,
1819 /* Structure to hold a per PF filter control settings */
1820 struct i40e_filter_control_settings {
1821 /* number of PE Quad Hash filter buckets */
1822 enum i40e_hash_filter_size pe_filt_num;
1823 /* number of PE Quad Hash contexts */
1824 enum i40e_dma_cntx_size pe_cntx_num;
1825 /* number of FCoE filter buckets */
1826 enum i40e_hash_filter_size fcoe_filt_num;
1827 /* number of FCoE DDP contexts */
1828 enum i40e_dma_cntx_size fcoe_cntx_num;
1829 /* size of the Hash LUT */
1830 enum i40e_hash_lut_size hash_lut_size;
1831 /* enable FDIR filters for PF and its VFs */
1833 /* enable Ethertype filters for PF and its VFs */
1834 bool enable_ethtype;
1835 /* enable MAC/VLAN filters for PF and its VFs */
1836 bool enable_macvlan;
1839 /* Structure to hold device level control filter counts */
1840 struct i40e_control_filter_stats {
1841 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1842 u16 etype_used; /* Used perfect EtherType filters */
1843 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1844 u16 etype_free; /* Un-used perfect EtherType filters */
1847 enum i40e_reset_type {
1849 I40E_RESET_CORER = 1,
1850 I40E_RESET_GLOBR = 2,
1851 I40E_RESET_EMPR = 3,
1854 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1855 #define I40E_NVM_LLDP_CFG_PTR 0xD
1856 struct i40e_lldp_variables {
1866 /* Offsets into Alternate Ram */
1867 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1868 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1869 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1870 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1871 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1872 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1874 /* Alternate Ram Bandwidth Masks */
1875 #define I40E_ALT_BW_VALUE_MASK 0xFF
1876 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1877 #define I40E_ALT_BW_VALID_MASK 0x80000000
1879 /* RSS Hash Table Size */
1880 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1882 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1883 #define I40E_L3_SRC_SHIFT 47
1884 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1885 #define I40E_L3_V6_SRC_SHIFT 43
1886 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1887 #define I40E_L3_DST_SHIFT 35
1888 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1889 #define I40E_L3_V6_DST_SHIFT 35
1890 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1891 #define I40E_L4_SRC_SHIFT 34
1892 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1893 #define I40E_L4_DST_SHIFT 33
1894 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1895 #define I40E_VERIFY_TAG_SHIFT 31
1896 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1898 #define I40E_FLEX_50_SHIFT 13
1899 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1900 #define I40E_FLEX_51_SHIFT 12
1901 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1902 #define I40E_FLEX_52_SHIFT 11
1903 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1904 #define I40E_FLEX_53_SHIFT 10
1905 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1906 #define I40E_FLEX_54_SHIFT 9
1907 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1908 #define I40E_FLEX_55_SHIFT 8
1909 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1910 #define I40E_FLEX_56_SHIFT 7
1911 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1912 #define I40E_FLEX_57_SHIFT 6
1913 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1915 /* Version format for Dynamic Device Personalization(DDP) */
1916 struct i40e_ddp_version {
1923 #define I40E_DDP_NAME_SIZE 32
1925 /* Package header */
1926 struct i40e_package_header {
1927 struct i40e_ddp_version version;
1929 u32 segment_offset[1];
1932 /* Generic segment header */
1933 struct i40e_generic_seg_header {
1934 #define SEGMENT_TYPE_METADATA 0x00000001
1935 #define SEGMENT_TYPE_NOTES 0x00000002
1936 #define SEGMENT_TYPE_I40E 0x00000011
1937 #define SEGMENT_TYPE_X722 0x00000012
1939 struct i40e_ddp_version version;
1941 char name[I40E_DDP_NAME_SIZE];
1944 struct i40e_metadata_segment {
1945 struct i40e_generic_seg_header header;
1946 struct i40e_ddp_version version;
1947 #define I40E_DDP_TRACKID_RDONLY 0
1948 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
1950 char name[I40E_DDP_NAME_SIZE];
1953 struct i40e_device_id_entry {
1955 u32 sub_vendor_dev_id;
1958 struct i40e_profile_segment {
1959 struct i40e_generic_seg_header header;
1960 struct i40e_ddp_version version;
1961 char name[I40E_DDP_NAME_SIZE];
1962 u32 device_table_count;
1963 struct i40e_device_id_entry device_table[1];
1966 struct i40e_section_table {
1968 u32 section_offset[1];
1971 struct i40e_profile_section_header {
1975 #define SECTION_TYPE_INFO 0x00000010
1976 #define SECTION_TYPE_MMIO 0x00000800
1977 #define SECTION_TYPE_RB_MMIO 0x00001800
1978 #define SECTION_TYPE_AQ 0x00000801
1979 #define SECTION_TYPE_RB_AQ 0x00001801
1980 #define SECTION_TYPE_NOTE 0x80000000
1981 #define SECTION_TYPE_NAME 0x80000001
1982 #define SECTION_TYPE_PROTO 0x80000002
1983 #define SECTION_TYPE_PCTYPE 0x80000003
1984 #define SECTION_TYPE_PTYPE 0x80000004
1991 struct i40e_profile_tlv_section_record {
1998 /* Generic AQ section in proflie */
1999 struct i40e_profile_aq_section {
2007 struct i40e_profile_info {
2009 struct i40e_ddp_version version;
2011 #define I40E_DDP_ADD_TRACKID 0x01
2012 #define I40E_DDP_REMOVE_TRACKID 0x02
2014 u8 name[I40E_DDP_NAME_SIZE];
2016 #endif /* _I40E_TYPE_H_ */