drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef I40E_MASK
  53 /* I40E_MASK is a macro used on 32 bit registers */
  54 #define I40E_MASK(mask, shift) (mask << shift)
  55 #endif
  56
  57 #define I40E_MAX_PF                     16
  58 #define I40E_MAX_PF_VSI                 64
  59 #define I40E_MAX_PF_QP                  128
  60 #define I40E_MAX_VSI_QP                 16
  61 #define I40E_MAX_VF_VSI                 3
  62 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  63 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  64
  65 /* something less than 1 minute */
  66 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  67
  68 /* Max default timeout in ms, */
  69 #define I40E_MAX_NVM_TIMEOUT            18000
  70
  71 /* Check whether address is multicast. */
  72 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  73
  74 /* Check whether an address is broadcast. */
  75 #define I40E_IS_BROADCAST(address)      \
  76         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  77         (((u8 *)(address))[1] == ((u8)0xff)))
  78
  79 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  80 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  81
  82 /* forward declaration */
  83 struct i40e_hw;
  84 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  85
  86 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  87 /* Data type manipulation macros. */
  88 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  89 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  90
  91 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  92 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  93
  94 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  95 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  96
  97 /* Number of Transmit Descriptors must be a multiple of 8. */
  98 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
  99 /* Number of Receive Descriptors must be a multiple of 32 if
 100  * the number of descriptors is greater than 32.
 101  */
 102 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 103
 104 #define I40E_DESC_UNUSED(R)     \
 105         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 106         (R)->next_to_clean - (R)->next_to_use - 1)
 107
 108 /* bitfields for Tx queue mapping in QTX_CTL */
 109 #define I40E_QTX_CTL_VF_QUEUE   0x0
 110 #define I40E_QTX_CTL_VM_QUEUE   0x1
 111 #define I40E_QTX_CTL_PF_QUEUE   0x2
 112
 113 /* debug masks - set these bits in hw->debug_mask to control output */
 114 enum i40e_debug_mask {
 115         I40E_DEBUG_INIT                 = 0x00000001,
 116         I40E_DEBUG_RELEASE              = 0x00000002,
 117
 118         I40E_DEBUG_LINK                 = 0x00000010,
 119         I40E_DEBUG_PHY                  = 0x00000020,
 120         I40E_DEBUG_HMC                  = 0x00000040,
 121         I40E_DEBUG_NVM                  = 0x00000080,
 122         I40E_DEBUG_LAN                  = 0x00000100,
 123         I40E_DEBUG_FLOW                 = 0x00000200,
 124         I40E_DEBUG_DCB                  = 0x00000400,
 125         I40E_DEBUG_DIAG                 = 0x00000800,
 126         I40E_DEBUG_FD                   = 0x00001000,
 127
 128         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 129         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 130         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 131         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 132         I40E_DEBUG_AQ                   = 0x0F000000,
 133
 134         I40E_DEBUG_USER                 = 0xF0000000,
 135
 136         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 137 };
 138
 139 /* PCI Bus Info */
 140 #define I40E_PCI_LINK_STATUS            0xB2
 141 #define I40E_PCI_LINK_WIDTH             0x3F0
 142 #define I40E_PCI_LINK_WIDTH_1           0x10
 143 #define I40E_PCI_LINK_WIDTH_2           0x20
 144 #define I40E_PCI_LINK_WIDTH_4           0x40
 145 #define I40E_PCI_LINK_WIDTH_8           0x80
 146 #define I40E_PCI_LINK_SPEED             0xF
 147 #define I40E_PCI_LINK_SPEED_2500        0x1
 148 #define I40E_PCI_LINK_SPEED_5000        0x2
 149 #define I40E_PCI_LINK_SPEED_8000        0x3
 150
 151 /* Memory types */
 152 enum i40e_memset_type {
 153         I40E_NONDMA_MEM = 0,
 154         I40E_DMA_MEM
 155 };
 156
 157 /* Memcpy types */
 158 enum i40e_memcpy_type {
 159         I40E_NONDMA_TO_NONDMA = 0,
 160         I40E_NONDMA_TO_DMA,
 161         I40E_DMA_TO_DMA,
 162         I40E_DMA_TO_NONDMA
 163 };
 164
 165 /* These are structs for managing the hardware information and the operations.
 166  * The structures of function pointers are filled out at init time when we
 167  * know for sure exactly which hardware we're working with.  This gives us the
 168  * flexibility of using the same main driver code but adapting to slightly
 169  * different hardware needs as new parts are developed.  For this architecture,
 170  * the Firmware and AdminQ are intended to insulate the driver from most of the
 171  * future changes, but these structures will also do part of the job.
 172  */
 173 enum i40e_mac_type {
 174         I40E_MAC_UNKNOWN = 0,
 175         I40E_MAC_X710,
 176         I40E_MAC_XL710,
 177         I40E_MAC_VF,
 178         I40E_MAC_GENERIC,
 179 };
 180
 181 enum i40e_media_type {
 182         I40E_MEDIA_TYPE_UNKNOWN = 0,
 183         I40E_MEDIA_TYPE_FIBER,
 184         I40E_MEDIA_TYPE_BASET,
 185         I40E_MEDIA_TYPE_BACKPLANE,
 186         I40E_MEDIA_TYPE_CX4,
 187         I40E_MEDIA_TYPE_DA,
 188         I40E_MEDIA_TYPE_VIRTUAL
 189 };
 190
 191 enum i40e_fc_mode {
 192         I40E_FC_NONE = 0,
 193         I40E_FC_RX_PAUSE,
 194         I40E_FC_TX_PAUSE,
 195         I40E_FC_FULL,
 196         I40E_FC_PFC,
 197         I40E_FC_DEFAULT
 198 };
 199
 200 enum i40e_set_fc_aq_failures {
 201         I40E_SET_FC_AQ_FAIL_NONE = 0,
 202         I40E_SET_FC_AQ_FAIL_GET = 1,
 203         I40E_SET_FC_AQ_FAIL_SET = 2,
 204         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 205         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 206 };
 207
 208 enum i40e_vsi_type {
 209         I40E_VSI_MAIN = 0,
 210         I40E_VSI_VMDQ1,
 211         I40E_VSI_VMDQ2,
 212         I40E_VSI_CTRL,
 213         I40E_VSI_FCOE,
 214         I40E_VSI_MIRROR,
 215         I40E_VSI_SRIOV,
 216         I40E_VSI_FDIR,
 217         I40E_VSI_TYPE_UNKNOWN
 218 };
 219
 220 enum i40e_queue_type {
 221         I40E_QUEUE_TYPE_RX = 0,
 222         I40E_QUEUE_TYPE_TX,
 223         I40E_QUEUE_TYPE_PE_CEQ,
 224         I40E_QUEUE_TYPE_UNKNOWN
 225 };
 226
 227 struct i40e_link_status {
 228         enum i40e_aq_phy_type phy_type;
 229         enum i40e_aq_link_speed link_speed;
 230         u8 link_info;
 231         u8 an_info;
 232         u8 ext_info;
 233         u8 loopback;
 234         /* is Link Status Event notification to SW enabled */
 235         bool lse_enable;
 236         u16 max_frame_size;
 237         bool crc_enable;
 238         u8 pacing;
 239         u8 requested_speeds;
 240         u8 module_type[3];
 241         /* 1st byte: module identifier */
 242 #define I40E_MODULE_TYPE_SFP            0x03
 243 #define I40E_MODULE_TYPE_QSFP           0x0D
 244         /* 2nd byte: ethernet compliance codes for 10/40G */
 245 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 246 #define I40E_MODULE_TYPE_40G_LR4        0x02
 247 #define I40E_MODULE_TYPE_40G_SR4        0x04
 248 #define I40E_MODULE_TYPE_40G_CR4        0x08
 249 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 250 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 251 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 252 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 253         /* 3rd byte: ethernet compliance codes for 1G */
 254 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 255 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 256 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 257 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 258 };
 259
 260 struct i40e_phy_info {
 261         struct i40e_link_status link_info;
 262         struct i40e_link_status link_info_old;
 263         u32 autoneg_advertised;
 264         u32 phy_id;
 265         u32 module_type;
 266         bool get_link_info;
 267         enum i40e_media_type media_type;
 268 };
 269
 270 #define I40E_HW_CAP_MAX_GPIO                    30
 271 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 272 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 273
 274 /* Capabilities of a PF or a VF or the whole device */
 275 struct i40e_hw_capabilities {
 276         u32  switch_mode;
 277 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 278 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 279 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 280
 281         u32  management_mode;
 282         u32  npar_enable;
 283         u32  os2bmc;
 284         u32  valid_functions;
 285         bool sr_iov_1_1;
 286         bool vmdq;
 287         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 288         bool evb_802_1_qbh; /* Bridge Port Extension */
 289         bool dcb;
 290         bool fcoe;
 291         bool iscsi; /* Indicates iSCSI enabled */
 292         bool mfp_mode_1;
 293         bool mgmt_cem;
 294         bool ieee_1588;
 295         bool iwarp;
 296         bool fd;
 297         u32 fd_filters_guaranteed;
 298         u32 fd_filters_best_effort;
 299         bool rss;
 300         u32 rss_table_size;
 301         u32 rss_table_entry_width;
 302         bool led[I40E_HW_CAP_MAX_GPIO];
 303         bool sdp[I40E_HW_CAP_MAX_GPIO];
 304         u32 nvm_image_type;
 305         u32 num_flow_director_filters;
 306         u32 num_vfs;
 307         u32 vf_base_id;
 308         u32 num_vsis;
 309         u32 num_rx_qp;
 310         u32 num_tx_qp;
 311         u32 base_queue;
 312         u32 num_msix_vectors;
 313         u32 num_msix_vectors_vf;
 314         u32 led_pin_num;
 315         u32 sdp_pin_num;
 316         u32 mdio_port_num;
 317         u32 mdio_port_mode;
 318         u8 rx_buf_chain_len;
 319         u32 enabled_tcmap;
 320         u32 maxtc;
 321 };
 322
 323 struct i40e_mac_info {
 324         enum i40e_mac_type type;
 325         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 326         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 327         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 328         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 329         u16 max_fcoeq;
 330 };
 331
 332 enum i40e_aq_resources_ids {
 333         I40E_NVM_RESOURCE_ID = 1
 334 };
 335
 336 enum i40e_aq_resource_access_type {
 337         I40E_RESOURCE_READ = 1,
 338         I40E_RESOURCE_WRITE
 339 };
 340
 341 struct i40e_nvm_info {
 342         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 343         u32 timeout;              /* [ms] */
 344         u16 sr_size;              /* Shadow RAM size in words */
 345         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 346         u16 version;              /* NVM package version */
 347         u32 eetrack;              /* NVM data version */
 348         u32 oem_ver;              /* OEM version info */
 349 };
 350
 351 /* definitions used in NVM update support */
 352
 353 enum i40e_nvmupd_cmd {
 354         I40E_NVMUPD_INVALID,
 355         I40E_NVMUPD_READ_CON,
 356         I40E_NVMUPD_READ_SNT,
 357         I40E_NVMUPD_READ_LCB,
 358         I40E_NVMUPD_READ_SA,
 359         I40E_NVMUPD_WRITE_ERA,
 360         I40E_NVMUPD_WRITE_CON,
 361         I40E_NVMUPD_WRITE_SNT,
 362         I40E_NVMUPD_WRITE_LCB,
 363         I40E_NVMUPD_WRITE_SA,
 364         I40E_NVMUPD_CSUM_CON,
 365         I40E_NVMUPD_CSUM_SA,
 366         I40E_NVMUPD_CSUM_LCB,
 367         I40E_NVMUPD_STATUS,
 368         I40E_NVMUPD_EXEC_AQ,
 369         I40E_NVMUPD_GET_AQ_RESULT,
 370 };
 371
 372 enum i40e_nvmupd_state {
 373         I40E_NVMUPD_STATE_INIT,
 374         I40E_NVMUPD_STATE_READING,
 375         I40E_NVMUPD_STATE_WRITING,
 376         I40E_NVMUPD_STATE_INIT_WAIT,
 377         I40E_NVMUPD_STATE_WRITE_WAIT,
 378 };
 379
 380 /* nvm_access definition and its masks/shifts need to be accessible to
 381  * application, core driver, and shared code.  Where is the right file?
 382  */
 383 #define I40E_NVM_READ   0xB
 384 #define I40E_NVM_WRITE  0xC
 385
 386 #define I40E_NVM_MOD_PNT_MASK 0xFF
 387
 388 #define I40E_NVM_TRANS_SHIFT    8
 389 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 390 #define I40E_NVM_CON            0x0
 391 #define I40E_NVM_SNT            0x1
 392 #define I40E_NVM_LCB            0x2
 393 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 394 #define I40E_NVM_ERA            0x4
 395 #define I40E_NVM_CSUM           0x8
 396 #define I40E_NVM_EXEC           0xf
 397
 398 #define I40E_NVM_ADAPT_SHIFT    16
 399 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 400
 401 #define I40E_NVMUPD_MAX_DATA    4096
 402 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 403
 404 struct i40e_nvm_access {
 405         u32 command;
 406         u32 config;
 407         u32 offset;     /* in bytes */
 408         u32 data_size;  /* in bytes */
 409         u8 data[1];
 410 };
 411
 412 /* PCI bus types */
 413 enum i40e_bus_type {
 414         i40e_bus_type_unknown = 0,
 415         i40e_bus_type_pci,
 416         i40e_bus_type_pcix,
 417         i40e_bus_type_pci_express,
 418         i40e_bus_type_reserved
 419 };
 420
 421 /* PCI bus speeds */
 422 enum i40e_bus_speed {
 423         i40e_bus_speed_unknown  = 0,
 424         i40e_bus_speed_33       = 33,
 425         i40e_bus_speed_66       = 66,
 426         i40e_bus_speed_100      = 100,
 427         i40e_bus_speed_120      = 120,
 428         i40e_bus_speed_133      = 133,
 429         i40e_bus_speed_2500     = 2500,
 430         i40e_bus_speed_5000     = 5000,
 431         i40e_bus_speed_8000     = 8000,
 432         i40e_bus_speed_reserved
 433 };
 434
 435 /* PCI bus widths */
 436 enum i40e_bus_width {
 437         i40e_bus_width_unknown  = 0,
 438         i40e_bus_width_pcie_x1  = 1,
 439         i40e_bus_width_pcie_x2  = 2,
 440         i40e_bus_width_pcie_x4  = 4,
 441         i40e_bus_width_pcie_x8  = 8,
 442         i40e_bus_width_32       = 32,
 443         i40e_bus_width_64       = 64,
 444         i40e_bus_width_reserved
 445 };
 446
 447 /* Bus parameters */
 448 struct i40e_bus_info {
 449         enum i40e_bus_speed speed;
 450         enum i40e_bus_width width;
 451         enum i40e_bus_type type;
 452
 453         u16 func;
 454         u16 device;
 455         u16 lan_id;
 456 };
 457
 458 /* Flow control (FC) parameters */
 459 struct i40e_fc_info {
 460         enum i40e_fc_mode current_mode; /* FC mode in effect */
 461         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 462 };
 463
 464 #define I40E_MAX_TRAFFIC_CLASS          8
 465 #define I40E_MAX_USER_PRIORITY          8
 466 #define I40E_DCBX_MAX_APPS              32
 467 #define I40E_LLDPDU_SIZE                1500
 468 #define I40E_TLV_STATUS_OPER            0x1
 469 #define I40E_TLV_STATUS_SYNC            0x2
 470 #define I40E_TLV_STATUS_ERR             0x4
 471 #define I40E_CEE_OPER_MAX_APPS          3
 472 #define I40E_APP_PROTOID_FCOE           0x8906
 473 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 474 #define I40E_APP_PROTOID_FIP            0x8914
 475 #define I40E_APP_SEL_ETHTYPE            0x1
 476 #define I40E_APP_SEL_TCPIP              0x2
 477
 478 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 479 struct i40e_dcb_ets_config {
 480         u8 willing;
 481         u8 cbs;
 482         u8 maxtcs;
 483         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 484         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 485         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 486 };
 487
 488 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 489 struct i40e_dcb_pfc_config {
 490         u8 willing;
 491         u8 mbc;
 492         u8 pfccap;
 493         u8 pfcenable;
 494 };
 495
 496 /* CEE or IEEE 802.1Qaz Application Priority data */
 497 struct i40e_dcb_app_priority_table {
 498         u8  priority;
 499         u8  selector;
 500         u16 protocolid;
 501 };
 502
 503 struct i40e_dcbx_config {
 504         u8  dcbx_mode;
 505 #define I40E_DCBX_MODE_CEE      0x1
 506 #define I40E_DCBX_MODE_IEEE     0x2
 507         u32 numapps;
 508         struct i40e_dcb_ets_config etscfg;
 509         struct i40e_dcb_ets_config etsrec;
 510         struct i40e_dcb_pfc_config pfc;
 511         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 512 };
 513
 514 /* Port hardware description */
 515 struct i40e_hw {
 516         u8 *hw_addr;
 517         void *back;
 518
 519         /* subsystem structs */
 520         struct i40e_phy_info phy;
 521         struct i40e_mac_info mac;
 522         struct i40e_bus_info bus;
 523         struct i40e_nvm_info nvm;
 524         struct i40e_fc_info fc;
 525
 526         /* pci info */
 527         u16 device_id;
 528         u16 vendor_id;
 529         u16 subsystem_device_id;
 530         u16 subsystem_vendor_id;
 531         u8 revision_id;
 532         u8 port;
 533         bool adapter_stopped;
 534
 535         /* capabilities for entire device and PCI func */
 536         struct i40e_hw_capabilities dev_caps;
 537         struct i40e_hw_capabilities func_caps;
 538
 539         /* Flow Director shared filter space */
 540         u16 fdir_shared_filter_count;
 541
 542         /* device profile info */
 543         u8  pf_id;
 544         u16 main_vsi_seid;
 545
 546         /* for multi-function MACs */
 547         u16 partition_id;
 548         u16 num_partitions;
 549         u16 num_ports;
 550
 551         /* Closest numa node to the device */
 552         u16 numa_node;
 553
 554         /* Admin Queue info */
 555         struct i40e_adminq_info aq;
 556
 557         /* state of nvm update process */
 558         enum i40e_nvmupd_state nvmupd_state;
 559         struct i40e_aq_desc nvm_wb_desc;
 560         struct i40e_virt_mem nvm_buff;
 561
 562         /* HMC info */
 563         struct i40e_hmc_info hmc; /* HMC info struct */
 564
 565         /* LLDP/DCBX Status */
 566         u16 dcbx_status;
 567
 568         /* DCBX info */
 569         struct i40e_dcbx_config local_dcbx_config;
 570         struct i40e_dcbx_config remote_dcbx_config;
 571
 572         /* debug mask */
 573         u32 debug_mask;
 574 #ifndef I40E_NDIS_SUPPORT
 575         char err_str[16];
 576 #endif /* I40E_NDIS_SUPPORT */
 577 };
 578
 579 static inline bool i40e_is_vf(struct i40e_hw *hw)
 580 {
 581         return hw->mac.type == I40E_MAC_VF;
 582 }
 583
 584 struct i40e_driver_version {
 585         u8 major_version;
 586         u8 minor_version;
 587         u8 build_version;
 588         u8 subbuild_version;
 589         u8 driver_string[32];
 590 };
 591
 592 /* RX Descriptors */
 593 union i40e_16byte_rx_desc {
 594         struct {
 595                 __le64 pkt_addr; /* Packet buffer address */
 596                 __le64 hdr_addr; /* Header buffer address */
 597         } read;
 598         struct {
 599                 struct {
 600                         struct {
 601                                 union {
 602                                         __le16 mirroring_status;
 603                                         __le16 fcoe_ctx_id;
 604                                 } mirr_fcoe;
 605                                 __le16 l2tag1;
 606                         } lo_dword;
 607                         union {
 608                                 __le32 rss; /* RSS Hash */
 609                                 __le32 fd_id; /* Flow director filter id */
 610                                 __le32 fcoe_param; /* FCoE DDP Context id */
 611                         } hi_dword;
 612                 } qword0;
 613                 struct {
 614                         /* ext status/error/pktype/length */
 615                         __le64 status_error_len;
 616                 } qword1;
 617         } wb;  /* writeback */
 618 };
 619
 620 union i40e_32byte_rx_desc {
 621         struct {
 622                 __le64  pkt_addr; /* Packet buffer address */
 623                 __le64  hdr_addr; /* Header buffer address */
 624                         /* bit 0 of hdr_buffer_addr is DD bit */
 625                 __le64  rsvd1;
 626                 __le64  rsvd2;
 627         } read;
 628         struct {
 629                 struct {
 630                         struct {
 631                                 union {
 632                                         __le16 mirroring_status;
 633                                         __le16 fcoe_ctx_id;
 634                                 } mirr_fcoe;
 635                                 __le16 l2tag1;
 636                         } lo_dword;
 637                         union {
 638                                 __le32 rss; /* RSS Hash */
 639                                 __le32 fcoe_param; /* FCoE DDP Context id */
 640                                 /* Flow director filter id in case of
 641                                  * Programming status desc WB
 642                                  */
 643                                 __le32 fd_id;
 644                         } hi_dword;
 645                 } qword0;
 646                 struct {
 647                         /* status/error/pktype/length */
 648                         __le64 status_error_len;
 649                 } qword1;
 650                 struct {
 651                         __le16 ext_status; /* extended status */
 652                         __le16 rsvd;
 653                         __le16 l2tag2_1;
 654                         __le16 l2tag2_2;
 655                 } qword2;
 656                 struct {
 657                         union {
 658                                 __le32 flex_bytes_lo;
 659                                 __le32 pe_status;
 660                         } lo_dword;
 661                         union {
 662                                 __le32 flex_bytes_hi;
 663                                 __le32 fd_id;
 664                         } hi_dword;
 665                 } qword3;
 666         } wb;  /* writeback */
 667 };
 668
 669 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 670 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 671                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 672 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 673 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 674                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 675
 676 enum i40e_rx_desc_status_bits {
 677         /* Note: These are predefined bit offsets */
 678         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 679         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 680         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 681         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 682         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 683         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 684         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 685         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 686
 687         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 688         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 689         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 690         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 691         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 692         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 693         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 694         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 695 };
 696
 697 #define I40E_RXD_QW1_STATUS_SHIFT       0
 698 #define I40E_RXD_QW1_STATUS_MASK        (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
 699                                          I40E_RXD_QW1_STATUS_SHIFT)
 700
 701 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 702 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 703                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 704
 705 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 706 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 707                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 708
 709 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 710 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 711                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 712
 713 enum i40e_rx_desc_fltstat_values {
 714         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 715         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 716         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 717         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 718 };
 719
 720 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 721 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 722 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 723 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 724
 725 #define I40E_RXD_QW1_ERROR_SHIFT        19
 726 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 727
 728 enum i40e_rx_desc_error_bits {
 729         /* Note: These are predefined bit offsets */
 730         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 731         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 732         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 733         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 734         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 735         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 736         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 737         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 738         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 739 };
 740
 741 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 742         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 743         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 744         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 745         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 746         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 747 };
 748
 749 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 750 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 751
 752 /* Packet type non-ip values */
 753 enum i40e_rx_l2_ptype {
 754         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 755         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 756         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 757         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 758         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 759         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 760         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 761         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 762         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 763         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 764         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 765         I40E_RX_PTYPE_L2_ARP                            = 11,
 766         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 767         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 768         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 769         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 770         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 771         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 772         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 773         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 774         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 775         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 776         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 777         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 778         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 779         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 780 };
 781
 782 struct i40e_rx_ptype_decoded {
 783         u32 ptype:8;
 784         u32 known:1;
 785         u32 outer_ip:1;
 786         u32 outer_ip_ver:1;
 787         u32 outer_frag:1;
 788         u32 tunnel_type:3;
 789         u32 tunnel_end_prot:2;
 790         u32 tunnel_end_frag:1;
 791         u32 inner_prot:4;
 792         u32 payload_layer:3;
 793 };
 794
 795 enum i40e_rx_ptype_outer_ip {
 796         I40E_RX_PTYPE_OUTER_L2  = 0,
 797         I40E_RX_PTYPE_OUTER_IP  = 1
 798 };
 799
 800 enum i40e_rx_ptype_outer_ip_ver {
 801         I40E_RX_PTYPE_OUTER_NONE        = 0,
 802         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 803         I40E_RX_PTYPE_OUTER_IPV6        = 1
 804 };
 805
 806 enum i40e_rx_ptype_outer_fragmented {
 807         I40E_RX_PTYPE_NOT_FRAG  = 0,
 808         I40E_RX_PTYPE_FRAG      = 1
 809 };
 810
 811 enum i40e_rx_ptype_tunnel_type {
 812         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 813         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 814         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 815         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 816         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 817 };
 818
 819 enum i40e_rx_ptype_tunnel_end_prot {
 820         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 821         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 822         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 823 };
 824
 825 enum i40e_rx_ptype_inner_prot {
 826         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 827         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 828         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 829         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 830         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 831         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 832 };
 833
 834 enum i40e_rx_ptype_payload_layer {
 835         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 836         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 837         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 838         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 839 };
 840
 841 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 842 #define I40E_RX_PTYPE_SHIFT             56
 843
 844 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 845 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 846                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 847
 848 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 849 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 850                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 851
 852 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 853 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 854                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 855
 856 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 857 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 858
 859 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 860 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 861                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 862
 863 enum i40e_rx_desc_ext_status_bits {
 864         /* Note: These are predefined bit offsets */
 865         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 866         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 867         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 868         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 869         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 870         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 871         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 872 };
 873
 874 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 875 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 876
 877 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 878 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 879
 880 enum i40e_rx_desc_pe_status_bits {
 881         /* Note: These are predefined bit offsets */
 882         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 883         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 884         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 885         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 886         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 887         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 888         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 889         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 890         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 891 };
 892
 893 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 894 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 895
 896 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 897 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 898                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 899
 900 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 901 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 902                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 903
 904 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 905 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 906                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 907
 908 enum i40e_rx_prog_status_desc_status_bits {
 909         /* Note: These are predefined bit offsets */
 910         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 911         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 912 };
 913
 914 enum i40e_rx_prog_status_desc_prog_id_masks {
 915         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 916         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 917         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 918 };
 919
 920 enum i40e_rx_prog_status_desc_error_bits {
 921         /* Note: These are predefined bit offsets */
 922         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 923         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 924         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 925         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 926 };
 927
 928 #define I40E_TWO_BIT_MASK       0x3
 929 #define I40E_THREE_BIT_MASK     0x7
 930 #define I40E_FOUR_BIT_MASK      0xF
 931 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 932
 933 /* TX Descriptor */
 934 struct i40e_tx_desc {
 935         __le64 buffer_addr; /* Address of descriptor's data buf */
 936         __le64 cmd_type_offset_bsz;
 937 };
 938
 939 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 940 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 941
 942 enum i40e_tx_desc_dtype_value {
 943         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 944         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 945         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 946         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 947         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 948         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 949         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 950         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 951         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 952         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 953 };
 954
 955 #define I40E_TXD_QW1_CMD_SHIFT  4
 956 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 957
 958 enum i40e_tx_desc_cmd_bits {
 959         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 960         I40E_TX_DESC_CMD_RS                     = 0x0002,
 961         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 962         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 963         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 964         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 965         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 966         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 967         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 968         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 969         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 970         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 971         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 972         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 973         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 974         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 975         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 976         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 977 };
 978
 979 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 980 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 981                                          I40E_TXD_QW1_OFFSET_SHIFT)
 982
 983 enum i40e_tx_desc_length_fields {
 984         /* Note: These are predefined bit offsets */
 985         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 986         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 987         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 988 };
 989
 990 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
 991 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
 992 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 993 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 994
 995 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 996 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 997                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 998
 999 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1000 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1001
1002 /* Context descriptors */
1003 struct i40e_tx_context_desc {
1004         __le32 tunneling_params;
1005         __le16 l2tag2;
1006         __le16 rsvd;
1007         __le64 type_cmd_tso_mss;
1008 };
1009
1010 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1011 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1012
1013 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1014 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1015
1016 enum i40e_tx_ctx_desc_cmd_bits {
1017         I40E_TX_CTX_DESC_TSO            = 0x01,
1018         I40E_TX_CTX_DESC_TSYN           = 0x02,
1019         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1020         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1021         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1022         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1023         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1024         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1025         I40E_TX_CTX_DESC_SWPE           = 0x40
1026 };
1027
1028 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1029 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1030                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1031
1032 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1033 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1034                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1035
1036 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1037 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1038
1039 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1040 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1041                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1042
1043 enum i40e_tx_ctx_desc_eipt_offload {
1044         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1045         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1046         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1047         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1048 };
1049
1050 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1051 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1052                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1053
1054 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1055 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1056
1057 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1058 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1059
1060 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1061 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1062                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1063
1064 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1065
1066 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1067 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1068                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1069
1070 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1071 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1072                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1073
1074 struct i40e_nop_desc {
1075         __le64 rsvd;
1076         __le64 dtype_cmd;
1077 };
1078
1079 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1080 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1081
1082 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1083 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1084
1085 enum i40e_tx_nop_desc_cmd_bits {
1086         /* Note: These are predefined bit offsets */
1087         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1088         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1089         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1090 };
1091
1092 struct i40e_filter_program_desc {
1093         __le32 qindex_flex_ptype_vsi;
1094         __le32 rsvd;
1095         __le32 dtype_cmd_cntindex;
1096         __le32 fd_id;
1097 };
1098 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1099 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1100                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1101 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1102 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1103                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1104 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1105 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1106                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1107
1108 /* Packet Classifier Types for filters */
1109 enum i40e_filter_pctype {
1110         /* Note: Values 0-30 are reserved for future use */
1111         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1112         /* Note: Value 32 is reserved for future use */
1113         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1114         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1115         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1116         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1117         /* Note: Values 37-40 are reserved for future use */
1118         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1119         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1120         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1121         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1122         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1123         /* Note: Value 47 is reserved for future use */
1124         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1125         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1126         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1127         /* Note: Values 51-62 are reserved for future use */
1128         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1129 };
1130
1131 enum i40e_filter_program_desc_dest {
1132         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1133         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1134         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1135 };
1136
1137 enum i40e_filter_program_desc_fd_status {
1138         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1139         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1140         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1141         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1142 };
1143
1144 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1145 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1146                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1147
1148 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1149 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1150
1151 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1152 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1153                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1154
1155 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1156 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1157
1158 enum i40e_filter_program_desc_pcmd {
1159         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1160         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1161 };
1162
1163 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1164 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1165
1166 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1167 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
1168                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1169
1170 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1171                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1172 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1173                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1174
1175 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1176 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1177                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1178
1179 enum i40e_filter_type {
1180         I40E_FLOW_DIRECTOR_FLTR = 0,
1181         I40E_PE_QUAD_HASH_FLTR = 1,
1182         I40E_ETHERTYPE_FLTR,
1183         I40E_FCOE_CTX_FLTR,
1184         I40E_MAC_VLAN_FLTR,
1185         I40E_HASH_FLTR
1186 };
1187
1188 struct i40e_vsi_context {
1189         u16 seid;
1190         u16 uplink_seid;
1191         u16 vsi_number;
1192         u16 vsis_allocated;
1193         u16 vsis_unallocated;
1194         u16 flags;
1195         u8 pf_num;
1196         u8 vf_num;
1197         u8 connection_type;
1198         struct i40e_aqc_vsi_properties_data info;
1199 };
1200
1201 struct i40e_veb_context {
1202         u16 seid;
1203         u16 uplink_seid;
1204         u16 veb_number;
1205         u16 vebs_allocated;
1206         u16 vebs_unallocated;
1207         u16 flags;
1208         struct i40e_aqc_get_veb_parameters_completion info;
1209 };
1210
1211 /* Statistics collected by each port, VSI, VEB, and S-channel */
1212 struct i40e_eth_stats {
1213         u64 rx_bytes;                   /* gorc */
1214         u64 rx_unicast;                 /* uprc */
1215         u64 rx_multicast;               /* mprc */
1216         u64 rx_broadcast;               /* bprc */
1217         u64 rx_discards;                /* rdpc */
1218         u64 rx_unknown_protocol;        /* rupp */
1219         u64 tx_bytes;                   /* gotc */
1220         u64 tx_unicast;                 /* uptc */
1221         u64 tx_multicast;               /* mptc */
1222         u64 tx_broadcast;               /* bptc */
1223         u64 tx_discards;                /* tdpc */
1224         u64 tx_errors;                  /* tepc */
1225 };
1226
1227 /* Statistics collected per VEB per TC */
1228 struct i40e_veb_tc_stats {
1229         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1230         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1231         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1232         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1233 };
1234
1235 /* Statistics collected by the MAC */
1236 struct i40e_hw_port_stats {
1237         /* eth stats collected by the port */
1238         struct i40e_eth_stats eth;
1239
1240         /* additional port specific stats */
1241         u64 tx_dropped_link_down;       /* tdold */
1242         u64 crc_errors;                 /* crcerrs */
1243         u64 illegal_bytes;              /* illerrc */
1244         u64 error_bytes;                /* errbc */
1245         u64 mac_local_faults;           /* mlfc */
1246         u64 mac_remote_faults;          /* mrfc */
1247         u64 rx_length_errors;           /* rlec */
1248         u64 link_xon_rx;                /* lxonrxc */
1249         u64 link_xoff_rx;               /* lxoffrxc */
1250         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1251         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1252         u64 link_xon_tx;                /* lxontxc */
1253         u64 link_xoff_tx;               /* lxofftxc */
1254         u64 priority_xon_tx[8];         /* pxontxc[8] */
1255         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1256         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1257         u64 rx_size_64;                 /* prc64 */
1258         u64 rx_size_127;                /* prc127 */
1259         u64 rx_size_255;                /* prc255 */
1260         u64 rx_size_511;                /* prc511 */
1261         u64 rx_size_1023;               /* prc1023 */
1262         u64 rx_size_1522;               /* prc1522 */
1263         u64 rx_size_big;                /* prc9522 */
1264         u64 rx_undersize;               /* ruc */
1265         u64 rx_fragments;               /* rfc */
1266         u64 rx_oversize;                /* roc */
1267         u64 rx_jabber;                  /* rjc */
1268         u64 tx_size_64;                 /* ptc64 */
1269         u64 tx_size_127;                /* ptc127 */
1270         u64 tx_size_255;                /* ptc255 */
1271         u64 tx_size_511;                /* ptc511 */
1272         u64 tx_size_1023;               /* ptc1023 */
1273         u64 tx_size_1522;               /* ptc1522 */
1274         u64 tx_size_big;                /* ptc9522 */
1275         u64 mac_short_packet_dropped;   /* mspdc */
1276         u64 checksum_error;             /* xec */
1277         /* flow director stats */
1278         u64 fd_atr_match;
1279         u64 fd_sb_match;
1280         /* EEE LPI */
1281         u32 tx_lpi_status;
1282         u32 rx_lpi_status;
1283         u64 tx_lpi_count;               /* etlpic */
1284         u64 rx_lpi_count;               /* erlpic */
1285 };
1286
1287 /* Checksum and Shadow RAM pointers */
1288 #define I40E_SR_NVM_CONTROL_WORD                0x00
1289 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1290 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1291 #define I40E_SR_OPTION_ROM_PTR                  0x05
1292 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1293 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1294 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1295 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1296 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1297 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1298 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1299 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1300 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1301 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1302 #define I40E_SR_PBA_FLAGS                       0x15
1303 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1304 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1305 #define I40E_NVM_OEM_VER_OFF                    0x83
1306 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1307 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1308 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1309 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1310 #define I40E_SR_NVM_MAP_VERSION                 0x29
1311 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1312 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1313 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1314 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1315 #define I40E_SR_VPD_PTR                         0x2F
1316 #define I40E_SR_PXE_SETUP_PTR                   0x30
1317 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1318 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1319 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1320 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1321 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1322 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1323 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1324 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1325 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1326 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1327 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1328 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1329 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1330 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1331 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1332 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1333 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1334 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1335
1336 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1337 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1338 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1339 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1340 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1341
1342 /* Shadow RAM related */
1343 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1344 #define I40E_SR_BUF_ALIGNMENT           4096
1345 #define I40E_SR_WORDS_IN_1KB            512
1346 /* Checksum should be calculated such that after adding all the words,
1347  * including the checksum word itself, the sum should be 0xBABA.
1348  */
1349 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1350
1351 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1352
1353 enum i40e_switch_element_types {
1354         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1355         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1356         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1357         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1358         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1359         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1360         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1361         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1362         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1363 };
1364
1365 /* Supported EtherType filters */
1366 enum i40e_ether_type_index {
1367         I40E_ETHER_TYPE_1588            = 0,
1368         I40E_ETHER_TYPE_FIP             = 1,
1369         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1370         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1371         I40E_ETHER_TYPE_LLDP            = 4,
1372         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1373         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1374         I40E_ETHER_TYPE_QCN_CNM         = 7,
1375         I40E_ETHER_TYPE_8021X           = 8,
1376         I40E_ETHER_TYPE_ARP             = 9,
1377         I40E_ETHER_TYPE_RSV1            = 10,
1378         I40E_ETHER_TYPE_RSV2            = 11,
1379 };
1380
1381 /* Filter context base size is 1K */
1382 #define I40E_HASH_FILTER_BASE_SIZE      1024
1383 /* Supported Hash filter values */
1384 enum i40e_hash_filter_size {
1385         I40E_HASH_FILTER_SIZE_1K        = 0,
1386         I40E_HASH_FILTER_SIZE_2K        = 1,
1387         I40E_HASH_FILTER_SIZE_4K        = 2,
1388         I40E_HASH_FILTER_SIZE_8K        = 3,
1389         I40E_HASH_FILTER_SIZE_16K       = 4,
1390         I40E_HASH_FILTER_SIZE_32K       = 5,
1391         I40E_HASH_FILTER_SIZE_64K       = 6,
1392         I40E_HASH_FILTER_SIZE_128K      = 7,
1393         I40E_HASH_FILTER_SIZE_256K      = 8,
1394         I40E_HASH_FILTER_SIZE_512K      = 9,
1395         I40E_HASH_FILTER_SIZE_1M        = 10,
1396 };
1397
1398 /* DMA context base size is 0.5K */
1399 #define I40E_DMA_CNTX_BASE_SIZE         512
1400 /* Supported DMA context values */
1401 enum i40e_dma_cntx_size {
1402         I40E_DMA_CNTX_SIZE_512          = 0,
1403         I40E_DMA_CNTX_SIZE_1K           = 1,
1404         I40E_DMA_CNTX_SIZE_2K           = 2,
1405         I40E_DMA_CNTX_SIZE_4K           = 3,
1406         I40E_DMA_CNTX_SIZE_8K           = 4,
1407         I40E_DMA_CNTX_SIZE_16K          = 5,
1408         I40E_DMA_CNTX_SIZE_32K          = 6,
1409         I40E_DMA_CNTX_SIZE_64K          = 7,
1410         I40E_DMA_CNTX_SIZE_128K         = 8,
1411         I40E_DMA_CNTX_SIZE_256K         = 9,
1412 };
1413
1414 /* Supported Hash look up table (LUT) sizes */
1415 enum i40e_hash_lut_size {
1416         I40E_HASH_LUT_SIZE_128          = 0,
1417         I40E_HASH_LUT_SIZE_512          = 1,
1418 };
1419
1420 /* Structure to hold a per PF filter control settings */
1421 struct i40e_filter_control_settings {
1422         /* number of PE Quad Hash filter buckets */
1423         enum i40e_hash_filter_size pe_filt_num;
1424         /* number of PE Quad Hash contexts */
1425         enum i40e_dma_cntx_size pe_cntx_num;
1426         /* number of FCoE filter buckets */
1427         enum i40e_hash_filter_size fcoe_filt_num;
1428         /* number of FCoE DDP contexts */
1429         enum i40e_dma_cntx_size fcoe_cntx_num;
1430         /* size of the Hash LUT */
1431         enum i40e_hash_lut_size hash_lut_size;
1432         /* enable FDIR filters for PF and its VFs */
1433         bool enable_fdir;
1434         /* enable Ethertype filters for PF and its VFs */
1435         bool enable_ethtype;
1436         /* enable MAC/VLAN filters for PF and its VFs */
1437         bool enable_macvlan;
1438 };
1439
1440 /* Structure to hold device level control filter counts */
1441 struct i40e_control_filter_stats {
1442         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1443         u16 etype_used;       /* Used perfect EtherType filters */
1444         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1445         u16 etype_free;       /* Un-used perfect EtherType filters */
1446 };
1447
1448 enum i40e_reset_type {
1449         I40E_RESET_POR          = 0,
1450         I40E_RESET_CORER        = 1,
1451         I40E_RESET_GLOBR        = 2,
1452         I40E_RESET_EMPR         = 3,
1453 };
1454
1455 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1456 #define I40E_NVM_LLDP_CFG_PTR           0xD
1457 struct i40e_lldp_variables {
1458         u16 length;
1459         u16 adminstatus;
1460         u16 msgfasttx;
1461         u16 msgtxinterval;
1462         u16 txparams;
1463         u16 timers;
1464         u16 crc8;
1465 };
1466
1467 /* Offsets into Alternate Ram */
1468 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1469 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1470 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1471 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1472 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1473 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1474
1475 /* Alternate Ram Bandwidth Masks */
1476 #define I40E_ALT_BW_VALUE_MASK          0xFF
1477 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1478 #define I40E_ALT_BW_VALID_MASK          0x80000000
1479
1480 /* RSS Hash Table Size */
1481 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1482 #endif /* _I40E_TYPE_H_ */