drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 /* Memory types */
 161 enum i40e_memset_type {
 162         I40E_NONDMA_MEM = 0,
 163         I40E_DMA_MEM
 164 };
 165
 166 /* Memcpy types */
 167 enum i40e_memcpy_type {
 168         I40E_NONDMA_TO_NONDMA = 0,
 169         I40E_NONDMA_TO_DMA,
 170         I40E_DMA_TO_DMA,
 171         I40E_DMA_TO_NONDMA
 172 };
 173
 174
 175 #ifdef X722_SUPPORT
 176 #define I40E_FW_API_VERSION_MINOR_X722  0x0003
 177 #endif
 178 #define I40E_FW_API_VERSION_MINOR_X710  0x0004
 179
 180
 181 /* These are structs for managing the hardware information and the operations.
 182  * The structures of function pointers are filled out at init time when we
 183  * know for sure exactly which hardware we're working with.  This gives us the
 184  * flexibility of using the same main driver code but adapting to slightly
 185  * different hardware needs as new parts are developed.  For this architecture,
 186  * the Firmware and AdminQ are intended to insulate the driver from most of the
 187  * future changes, but these structures will also do part of the job.
 188  */
 189 enum i40e_mac_type {
 190         I40E_MAC_UNKNOWN = 0,
 191         I40E_MAC_X710,
 192         I40E_MAC_XL710,
 193         I40E_MAC_VF,
 194         I40E_MAC_GENERIC,
 195 };
 196
 197 enum i40e_media_type {
 198         I40E_MEDIA_TYPE_UNKNOWN = 0,
 199         I40E_MEDIA_TYPE_FIBER,
 200         I40E_MEDIA_TYPE_BASET,
 201         I40E_MEDIA_TYPE_BACKPLANE,
 202         I40E_MEDIA_TYPE_CX4,
 203         I40E_MEDIA_TYPE_DA,
 204         I40E_MEDIA_TYPE_VIRTUAL
 205 };
 206
 207 enum i40e_fc_mode {
 208         I40E_FC_NONE = 0,
 209         I40E_FC_RX_PAUSE,
 210         I40E_FC_TX_PAUSE,
 211         I40E_FC_FULL,
 212         I40E_FC_PFC,
 213         I40E_FC_DEFAULT
 214 };
 215
 216 enum i40e_set_fc_aq_failures {
 217         I40E_SET_FC_AQ_FAIL_NONE = 0,
 218         I40E_SET_FC_AQ_FAIL_GET = 1,
 219         I40E_SET_FC_AQ_FAIL_SET = 2,
 220         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 221         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 222 };
 223
 224 enum i40e_vsi_type {
 225         I40E_VSI_MAIN = 0,
 226         I40E_VSI_VMDQ1,
 227         I40E_VSI_VMDQ2,
 228         I40E_VSI_CTRL,
 229         I40E_VSI_FCOE,
 230         I40E_VSI_MIRROR,
 231         I40E_VSI_SRIOV,
 232         I40E_VSI_FDIR,
 233         I40E_VSI_TYPE_UNKNOWN
 234 };
 235
 236 enum i40e_queue_type {
 237         I40E_QUEUE_TYPE_RX = 0,
 238         I40E_QUEUE_TYPE_TX,
 239         I40E_QUEUE_TYPE_PE_CEQ,
 240         I40E_QUEUE_TYPE_UNKNOWN
 241 };
 242
 243 struct i40e_link_status {
 244         enum i40e_aq_phy_type phy_type;
 245         enum i40e_aq_link_speed link_speed;
 246         u8 link_info;
 247         u8 an_info;
 248         u8 ext_info;
 249         u8 loopback;
 250         /* is Link Status Event notification to SW enabled */
 251         bool lse_enable;
 252         u16 max_frame_size;
 253         bool crc_enable;
 254         u8 pacing;
 255         u8 requested_speeds;
 256         u8 module_type[3];
 257         /* 1st byte: module identifier */
 258 #define I40E_MODULE_TYPE_SFP            0x03
 259 #define I40E_MODULE_TYPE_QSFP           0x0D
 260         /* 2nd byte: ethernet compliance codes for 10/40G */
 261 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 262 #define I40E_MODULE_TYPE_40G_LR4        0x02
 263 #define I40E_MODULE_TYPE_40G_SR4        0x04
 264 #define I40E_MODULE_TYPE_40G_CR4        0x08
 265 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 266 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 267 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 268 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 269         /* 3rd byte: ethernet compliance codes for 1G */
 270 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 271 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 272 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 273 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 274 };
 275
 276 enum i40e_aq_capabilities_phy_type {
 277         I40E_CAP_PHY_TYPE_SGMII                 = BIT(I40E_PHY_TYPE_SGMII),
 278         I40E_CAP_PHY_TYPE_1000BASE_KX           = BIT(I40E_PHY_TYPE_1000BASE_KX),
 279         I40E_CAP_PHY_TYPE_10GBASE_KX4           = BIT(I40E_PHY_TYPE_10GBASE_KX4),
 280         I40E_CAP_PHY_TYPE_10GBASE_KR            = BIT(I40E_PHY_TYPE_10GBASE_KR),
 281         I40E_CAP_PHY_TYPE_40GBASE_KR4           = BIT(I40E_PHY_TYPE_40GBASE_KR4),
 282         I40E_CAP_PHY_TYPE_XAUI                  = BIT(I40E_PHY_TYPE_XAUI),
 283         I40E_CAP_PHY_TYPE_XFI                   = BIT(I40E_PHY_TYPE_XFI),
 284         I40E_CAP_PHY_TYPE_SFI                   = BIT(I40E_PHY_TYPE_SFI),
 285         I40E_CAP_PHY_TYPE_XLAUI                 = BIT(I40E_PHY_TYPE_XLAUI),
 286         I40E_CAP_PHY_TYPE_XLPPI                 = BIT(I40E_PHY_TYPE_XLPPI),
 287         I40E_CAP_PHY_TYPE_40GBASE_CR4_CU        = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
 288         I40E_CAP_PHY_TYPE_10GBASE_CR1_CU        = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
 289         I40E_CAP_PHY_TYPE_10GBASE_AOC           = BIT(I40E_PHY_TYPE_10GBASE_AOC),
 290         I40E_CAP_PHY_TYPE_40GBASE_AOC           = BIT(I40E_PHY_TYPE_40GBASE_AOC),
 291         I40E_CAP_PHY_TYPE_100BASE_TX            = BIT(I40E_PHY_TYPE_100BASE_TX),
 292         I40E_CAP_PHY_TYPE_1000BASE_T            = BIT(I40E_PHY_TYPE_1000BASE_T),
 293         I40E_CAP_PHY_TYPE_10GBASE_T             = BIT(I40E_PHY_TYPE_10GBASE_T),
 294         I40E_CAP_PHY_TYPE_10GBASE_SR            = BIT(I40E_PHY_TYPE_10GBASE_SR),
 295         I40E_CAP_PHY_TYPE_10GBASE_LR            = BIT(I40E_PHY_TYPE_10GBASE_LR),
 296         I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU       = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
 297         I40E_CAP_PHY_TYPE_10GBASE_CR1           = BIT(I40E_PHY_TYPE_10GBASE_CR1),
 298         I40E_CAP_PHY_TYPE_40GBASE_CR4           = BIT(I40E_PHY_TYPE_40GBASE_CR4),
 299         I40E_CAP_PHY_TYPE_40GBASE_SR4           = BIT(I40E_PHY_TYPE_40GBASE_SR4),
 300         I40E_CAP_PHY_TYPE_40GBASE_LR4           = BIT(I40E_PHY_TYPE_40GBASE_LR4),
 301         I40E_CAP_PHY_TYPE_1000BASE_SX           = BIT(I40E_PHY_TYPE_1000BASE_SX),
 302         I40E_CAP_PHY_TYPE_1000BASE_LX           = BIT(I40E_PHY_TYPE_1000BASE_LX),
 303         I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL    = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
 304         I40E_CAP_PHY_TYPE_20GBASE_KR2           = BIT(I40E_PHY_TYPE_20GBASE_KR2)
 305 };
 306
 307 struct i40e_phy_info {
 308         struct i40e_link_status link_info;
 309         struct i40e_link_status link_info_old;
 310         bool get_link_info;
 311         enum i40e_media_type media_type;
 312         /* all the phy types the NVM is capable of */
 313         u32 phy_types;
 314 };
 315
 316 #define I40E_HW_CAP_MAX_GPIO                    30
 317 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 318 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 319
 320 /* Capabilities of a PF or a VF or the whole device */
 321 struct i40e_hw_capabilities {
 322         u32  switch_mode;
 323 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 324 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 325 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 326
 327         u32  management_mode;
 328         u32  npar_enable;
 329         u32  os2bmc;
 330         u32  valid_functions;
 331         bool sr_iov_1_1;
 332         bool vmdq;
 333         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 334         bool evb_802_1_qbh; /* Bridge Port Extension */
 335         bool dcb;
 336         bool fcoe;
 337         bool iscsi; /* Indicates iSCSI enabled */
 338         bool mfp_mode_1;
 339         bool mgmt_cem;
 340         bool ieee_1588;
 341         bool iwarp;
 342         bool fd;
 343         u32 fd_filters_guaranteed;
 344         u32 fd_filters_best_effort;
 345         bool rss;
 346         u32 rss_table_size;
 347         u32 rss_table_entry_width;
 348         bool led[I40E_HW_CAP_MAX_GPIO];
 349         bool sdp[I40E_HW_CAP_MAX_GPIO];
 350         u32 nvm_image_type;
 351         u32 num_flow_director_filters;
 352         u32 num_vfs;
 353         u32 vf_base_id;
 354         u32 num_vsis;
 355         u32 num_rx_qp;
 356         u32 num_tx_qp;
 357         u32 base_queue;
 358         u32 num_msix_vectors;
 359         u32 num_msix_vectors_vf;
 360         u32 led_pin_num;
 361         u32 sdp_pin_num;
 362         u32 mdio_port_num;
 363         u32 mdio_port_mode;
 364         u8 rx_buf_chain_len;
 365         u32 enabled_tcmap;
 366         u32 maxtc;
 367 };
 368
 369 struct i40e_mac_info {
 370         enum i40e_mac_type type;
 371         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 372         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 373         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 374         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 375         u16 max_fcoeq;
 376 };
 377
 378 enum i40e_aq_resources_ids {
 379         I40E_NVM_RESOURCE_ID = 1
 380 };
 381
 382 enum i40e_aq_resource_access_type {
 383         I40E_RESOURCE_READ = 1,
 384         I40E_RESOURCE_WRITE
 385 };
 386
 387 struct i40e_nvm_info {
 388         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 389         u32 timeout;              /* [ms] */
 390         u16 sr_size;              /* Shadow RAM size in words */
 391         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 392         u16 version;              /* NVM package version */
 393         u32 eetrack;              /* NVM data version */
 394         u32 oem_ver;              /* OEM version info */
 395 };
 396
 397 /* definitions used in NVM update support */
 398
 399 enum i40e_nvmupd_cmd {
 400         I40E_NVMUPD_INVALID,
 401         I40E_NVMUPD_READ_CON,
 402         I40E_NVMUPD_READ_SNT,
 403         I40E_NVMUPD_READ_LCB,
 404         I40E_NVMUPD_READ_SA,
 405         I40E_NVMUPD_WRITE_ERA,
 406         I40E_NVMUPD_WRITE_CON,
 407         I40E_NVMUPD_WRITE_SNT,
 408         I40E_NVMUPD_WRITE_LCB,
 409         I40E_NVMUPD_WRITE_SA,
 410         I40E_NVMUPD_CSUM_CON,
 411         I40E_NVMUPD_CSUM_SA,
 412         I40E_NVMUPD_CSUM_LCB,
 413         I40E_NVMUPD_STATUS,
 414         I40E_NVMUPD_EXEC_AQ,
 415         I40E_NVMUPD_GET_AQ_RESULT,
 416 };
 417
 418 enum i40e_nvmupd_state {
 419         I40E_NVMUPD_STATE_INIT,
 420         I40E_NVMUPD_STATE_READING,
 421         I40E_NVMUPD_STATE_WRITING,
 422         I40E_NVMUPD_STATE_INIT_WAIT,
 423         I40E_NVMUPD_STATE_WRITE_WAIT,
 424 };
 425
 426 /* nvm_access definition and its masks/shifts need to be accessible to
 427  * application, core driver, and shared code.  Where is the right file?
 428  */
 429 #define I40E_NVM_READ   0xB
 430 #define I40E_NVM_WRITE  0xC
 431
 432 #define I40E_NVM_MOD_PNT_MASK 0xFF
 433
 434 #define I40E_NVM_TRANS_SHIFT    8
 435 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 436 #define I40E_NVM_CON            0x0
 437 #define I40E_NVM_SNT            0x1
 438 #define I40E_NVM_LCB            0x2
 439 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 440 #define I40E_NVM_ERA            0x4
 441 #define I40E_NVM_CSUM           0x8
 442 #define I40E_NVM_EXEC           0xf
 443
 444 #define I40E_NVM_ADAPT_SHIFT    16
 445 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 446
 447 #define I40E_NVMUPD_MAX_DATA    4096
 448 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 449
 450 struct i40e_nvm_access {
 451         u32 command;
 452         u32 config;
 453         u32 offset;     /* in bytes */
 454         u32 data_size;  /* in bytes */
 455         u8 data[1];
 456 };
 457
 458 /* PCI bus types */
 459 enum i40e_bus_type {
 460         i40e_bus_type_unknown = 0,
 461         i40e_bus_type_pci,
 462         i40e_bus_type_pcix,
 463         i40e_bus_type_pci_express,
 464         i40e_bus_type_reserved
 465 };
 466
 467 /* PCI bus speeds */
 468 enum i40e_bus_speed {
 469         i40e_bus_speed_unknown  = 0,
 470         i40e_bus_speed_33       = 33,
 471         i40e_bus_speed_66       = 66,
 472         i40e_bus_speed_100      = 100,
 473         i40e_bus_speed_120      = 120,
 474         i40e_bus_speed_133      = 133,
 475         i40e_bus_speed_2500     = 2500,
 476         i40e_bus_speed_5000     = 5000,
 477         i40e_bus_speed_8000     = 8000,
 478         i40e_bus_speed_reserved
 479 };
 480
 481 /* PCI bus widths */
 482 enum i40e_bus_width {
 483         i40e_bus_width_unknown  = 0,
 484         i40e_bus_width_pcie_x1  = 1,
 485         i40e_bus_width_pcie_x2  = 2,
 486         i40e_bus_width_pcie_x4  = 4,
 487         i40e_bus_width_pcie_x8  = 8,
 488         i40e_bus_width_32       = 32,
 489         i40e_bus_width_64       = 64,
 490         i40e_bus_width_reserved
 491 };
 492
 493 /* Bus parameters */
 494 struct i40e_bus_info {
 495         enum i40e_bus_speed speed;
 496         enum i40e_bus_width width;
 497         enum i40e_bus_type type;
 498
 499         u16 func;
 500         u16 device;
 501         u16 lan_id;
 502 };
 503
 504 /* Flow control (FC) parameters */
 505 struct i40e_fc_info {
 506         enum i40e_fc_mode current_mode; /* FC mode in effect */
 507         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 508 };
 509
 510 #define I40E_MAX_TRAFFIC_CLASS          8
 511 #define I40E_MAX_USER_PRIORITY          8
 512 #define I40E_DCBX_MAX_APPS              32
 513 #define I40E_LLDPDU_SIZE                1500
 514 #define I40E_TLV_STATUS_OPER            0x1
 515 #define I40E_TLV_STATUS_SYNC            0x2
 516 #define I40E_TLV_STATUS_ERR             0x4
 517 #define I40E_CEE_OPER_MAX_APPS          3
 518 #define I40E_APP_PROTOID_FCOE           0x8906
 519 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 520 #define I40E_APP_PROTOID_FIP            0x8914
 521 #define I40E_APP_SEL_ETHTYPE            0x1
 522 #define I40E_APP_SEL_TCPIP              0x2
 523 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 524 #define I40E_CEE_APP_SEL_TCPIP          0x1
 525
 526 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 527 struct i40e_dcb_ets_config {
 528         u8 willing;
 529         u8 cbs;
 530         u8 maxtcs;
 531         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 532         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 533         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 534 };
 535
 536 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 537 struct i40e_dcb_pfc_config {
 538         u8 willing;
 539         u8 mbc;
 540         u8 pfccap;
 541         u8 pfcenable;
 542 };
 543
 544 /* CEE or IEEE 802.1Qaz Application Priority data */
 545 struct i40e_dcb_app_priority_table {
 546         u8  priority;
 547         u8  selector;
 548         u16 protocolid;
 549 };
 550
 551 struct i40e_dcbx_config {
 552         u8  dcbx_mode;
 553 #define I40E_DCBX_MODE_CEE      0x1
 554 #define I40E_DCBX_MODE_IEEE     0x2
 555         u8  app_mode;
 556 #define I40E_DCBX_APPS_NON_WILLING      0x1
 557         u32 numapps;
 558         struct i40e_dcb_ets_config etscfg;
 559         struct i40e_dcb_ets_config etsrec;
 560         struct i40e_dcb_pfc_config pfc;
 561         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 562 };
 563
 564 /* Port hardware description */
 565 struct i40e_hw {
 566         u8 *hw_addr;
 567         void *back;
 568
 569         /* subsystem structs */
 570         struct i40e_phy_info phy;
 571         struct i40e_mac_info mac;
 572         struct i40e_bus_info bus;
 573         struct i40e_nvm_info nvm;
 574         struct i40e_fc_info fc;
 575
 576         /* pci info */
 577         u16 device_id;
 578         u16 vendor_id;
 579         u16 subsystem_device_id;
 580         u16 subsystem_vendor_id;
 581         u8 revision_id;
 582         u8 port;
 583         bool adapter_stopped;
 584
 585         /* capabilities for entire device and PCI func */
 586         struct i40e_hw_capabilities dev_caps;
 587         struct i40e_hw_capabilities func_caps;
 588
 589         /* Flow Director shared filter space */
 590         u16 fdir_shared_filter_count;
 591
 592         /* device profile info */
 593         u8  pf_id;
 594         u16 main_vsi_seid;
 595
 596         /* for multi-function MACs */
 597         u16 partition_id;
 598         u16 num_partitions;
 599         u16 num_ports;
 600
 601         /* Closest numa node to the device */
 602         u16 numa_node;
 603
 604         /* Admin Queue info */
 605         struct i40e_adminq_info aq;
 606
 607         /* state of nvm update process */
 608         enum i40e_nvmupd_state nvmupd_state;
 609         struct i40e_aq_desc nvm_wb_desc;
 610         struct i40e_virt_mem nvm_buff;
 611
 612         /* HMC info */
 613         struct i40e_hmc_info hmc; /* HMC info struct */
 614
 615         /* LLDP/DCBX Status */
 616         u16 dcbx_status;
 617
 618         /* DCBX info */
 619         struct i40e_dcbx_config local_dcbx_config;
 620         struct i40e_dcbx_config remote_dcbx_config;
 621
 622         /* debug mask */
 623         u32 debug_mask;
 624 #ifndef I40E_NDIS_SUPPORT
 625         char err_str[16];
 626 #endif /* I40E_NDIS_SUPPORT */
 627 };
 628
 629 static inline bool i40e_is_vf(struct i40e_hw *hw)
 630 {
 631         return hw->mac.type == I40E_MAC_VF;
 632 }
 633
 634 struct i40e_driver_version {
 635         u8 major_version;
 636         u8 minor_version;
 637         u8 build_version;
 638         u8 subbuild_version;
 639         u8 driver_string[32];
 640 };
 641
 642 /* RX Descriptors */
 643 union i40e_16byte_rx_desc {
 644         struct {
 645                 __le64 pkt_addr; /* Packet buffer address */
 646                 __le64 hdr_addr; /* Header buffer address */
 647         } read;
 648         struct {
 649                 struct {
 650                         struct {
 651                                 union {
 652                                         __le16 mirroring_status;
 653                                         __le16 fcoe_ctx_id;
 654                                 } mirr_fcoe;
 655                                 __le16 l2tag1;
 656                         } lo_dword;
 657                         union {
 658                                 __le32 rss; /* RSS Hash */
 659                                 __le32 fd_id; /* Flow director filter id */
 660                                 __le32 fcoe_param; /* FCoE DDP Context id */
 661                         } hi_dword;
 662                 } qword0;
 663                 struct {
 664                         /* ext status/error/pktype/length */
 665                         __le64 status_error_len;
 666                 } qword1;
 667         } wb;  /* writeback */
 668 };
 669
 670 union i40e_32byte_rx_desc {
 671         struct {
 672                 __le64  pkt_addr; /* Packet buffer address */
 673                 __le64  hdr_addr; /* Header buffer address */
 674                         /* bit 0 of hdr_buffer_addr is DD bit */
 675                 __le64  rsvd1;
 676                 __le64  rsvd2;
 677         } read;
 678         struct {
 679                 struct {
 680                         struct {
 681                                 union {
 682                                         __le16 mirroring_status;
 683                                         __le16 fcoe_ctx_id;
 684                                 } mirr_fcoe;
 685                                 __le16 l2tag1;
 686                         } lo_dword;
 687                         union {
 688                                 __le32 rss; /* RSS Hash */
 689                                 __le32 fcoe_param; /* FCoE DDP Context id */
 690                                 /* Flow director filter id in case of
 691                                  * Programming status desc WB
 692                                  */
 693                                 __le32 fd_id;
 694                         } hi_dword;
 695                 } qword0;
 696                 struct {
 697                         /* status/error/pktype/length */
 698                         __le64 status_error_len;
 699                 } qword1;
 700                 struct {
 701                         __le16 ext_status; /* extended status */
 702                         __le16 rsvd;
 703                         __le16 l2tag2_1;
 704                         __le16 l2tag2_2;
 705                 } qword2;
 706                 struct {
 707                         union {
 708                                 __le32 flex_bytes_lo;
 709                                 __le32 pe_status;
 710                         } lo_dword;
 711                         union {
 712                                 __le32 flex_bytes_hi;
 713                                 __le32 fd_id;
 714                         } hi_dword;
 715                 } qword3;
 716         } wb;  /* writeback */
 717 };
 718
 719 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 720 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 721                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 722 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 723 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 724                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 725
 726 enum i40e_rx_desc_status_bits {
 727         /* Note: These are predefined bit offsets */
 728         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 729         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 730         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 731         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 732         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 733         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 734         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 735         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 736
 737         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 738         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 739         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 740         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 741         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 742         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 743         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 744         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 745 };
 746
 747 #define I40E_RXD_QW1_STATUS_SHIFT       0
 748 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 749                                          I40E_RXD_QW1_STATUS_SHIFT)
 750
 751 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 752 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 753                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 754
 755 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 756 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 757
 758 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 759 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 760                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 761
 762 enum i40e_rx_desc_fltstat_values {
 763         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 764         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 765         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 766         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 767 };
 768
 769 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 770 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 771 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 772 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 773
 774 #define I40E_RXD_QW1_ERROR_SHIFT        19
 775 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 776
 777 enum i40e_rx_desc_error_bits {
 778         /* Note: These are predefined bit offsets */
 779         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 780         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 781         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 782         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 783         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 784         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 785         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 786         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 787         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 788 };
 789
 790 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 791         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 792         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 793         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 794         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 795         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 796 };
 797
 798 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 799 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 800
 801 /* Packet type non-ip values */
 802 enum i40e_rx_l2_ptype {
 803         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 804         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 805         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 806         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 807         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 808         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 809         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 810         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 811         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 812         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 813         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 814         I40E_RX_PTYPE_L2_ARP                            = 11,
 815         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 816         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 817         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 818         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 819         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 820         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 821         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 822         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 823         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 824         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 825         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 826         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 827         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 828         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 829 };
 830
 831 struct i40e_rx_ptype_decoded {
 832         u32 ptype:8;
 833         u32 known:1;
 834         u32 outer_ip:1;
 835         u32 outer_ip_ver:1;
 836         u32 outer_frag:1;
 837         u32 tunnel_type:3;
 838         u32 tunnel_end_prot:2;
 839         u32 tunnel_end_frag:1;
 840         u32 inner_prot:4;
 841         u32 payload_layer:3;
 842 };
 843
 844 enum i40e_rx_ptype_outer_ip {
 845         I40E_RX_PTYPE_OUTER_L2  = 0,
 846         I40E_RX_PTYPE_OUTER_IP  = 1
 847 };
 848
 849 enum i40e_rx_ptype_outer_ip_ver {
 850         I40E_RX_PTYPE_OUTER_NONE        = 0,
 851         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 852         I40E_RX_PTYPE_OUTER_IPV6        = 1
 853 };
 854
 855 enum i40e_rx_ptype_outer_fragmented {
 856         I40E_RX_PTYPE_NOT_FRAG  = 0,
 857         I40E_RX_PTYPE_FRAG      = 1
 858 };
 859
 860 enum i40e_rx_ptype_tunnel_type {
 861         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 862         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 863         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 864         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 865         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 866 };
 867
 868 enum i40e_rx_ptype_tunnel_end_prot {
 869         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 870         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 871         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 872 };
 873
 874 enum i40e_rx_ptype_inner_prot {
 875         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 876         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 877         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 878         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 879         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 880         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 881 };
 882
 883 enum i40e_rx_ptype_payload_layer {
 884         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 885         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 886         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 887         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 888 };
 889
 890 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 891 #define I40E_RX_PTYPE_SHIFT             56
 892
 893 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 894 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 895                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 896
 897 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 898 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 899                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 900
 901 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 902 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 903
 904 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 905 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 906
 907 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 908 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 909                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 910
 911 enum i40e_rx_desc_ext_status_bits {
 912         /* Note: These are predefined bit offsets */
 913         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 914         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 915         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 916         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 917         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 918         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 919         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 920 };
 921
 922 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 923 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 924
 925 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 926 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 927
 928 enum i40e_rx_desc_pe_status_bits {
 929         /* Note: These are predefined bit offsets */
 930         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 931         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 932         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 933         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 934         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 935         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 936         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 937         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 938         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 939 };
 940
 941 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 942 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 943
 944 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 945 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 946                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 947
 948 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 949 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 950                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 951
 952 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 953 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 954                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 955
 956 enum i40e_rx_prog_status_desc_status_bits {
 957         /* Note: These are predefined bit offsets */
 958         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 959         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 960 };
 961
 962 enum i40e_rx_prog_status_desc_prog_id_masks {
 963         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 964         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 965         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 966 };
 967
 968 enum i40e_rx_prog_status_desc_error_bits {
 969         /* Note: These are predefined bit offsets */
 970         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 971         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 972         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 973         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 974 };
 975
 976 #define I40E_TWO_BIT_MASK       0x3
 977 #define I40E_THREE_BIT_MASK     0x7
 978 #define I40E_FOUR_BIT_MASK      0xF
 979 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
 980
 981 /* TX Descriptor */
 982 struct i40e_tx_desc {
 983         __le64 buffer_addr; /* Address of descriptor's data buf */
 984         __le64 cmd_type_offset_bsz;
 985 };
 986
 987 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 988 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 989
 990 enum i40e_tx_desc_dtype_value {
 991         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 992         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 993         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 994         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 995         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 996         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 997         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 998         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 999         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1000         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1001 };
1002
1003 #define I40E_TXD_QW1_CMD_SHIFT  4
1004 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1005
1006 enum i40e_tx_desc_cmd_bits {
1007         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1008         I40E_TX_DESC_CMD_RS                     = 0x0002,
1009         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1010         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1011         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1012         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1013         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1014         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1015         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1016         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1017         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1018         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1019         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1020         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1021         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1022         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1023         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1024         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1025 };
1026
1027 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1028 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1029                                          I40E_TXD_QW1_OFFSET_SHIFT)
1030
1031 enum i40e_tx_desc_length_fields {
1032         /* Note: These are predefined bit offsets */
1033         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1034         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1035         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1036 };
1037
1038 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1039 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1040 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1041 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1042
1043 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1044 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1045                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1046
1047 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1048 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1049
1050 /* Context descriptors */
1051 struct i40e_tx_context_desc {
1052         __le32 tunneling_params;
1053         __le16 l2tag2;
1054         __le16 rsvd;
1055         __le64 type_cmd_tso_mss;
1056 };
1057
1058 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1059 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1060
1061 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1062 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1063
1064 enum i40e_tx_ctx_desc_cmd_bits {
1065         I40E_TX_CTX_DESC_TSO            = 0x01,
1066         I40E_TX_CTX_DESC_TSYN           = 0x02,
1067         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1068         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1069         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1070         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1071         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1072         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1073         I40E_TX_CTX_DESC_SWPE           = 0x40
1074 };
1075
1076 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1077 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1078                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1079
1080 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1081 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1082                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1083
1084 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1085 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1086
1087 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1088 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1089                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1090
1091 enum i40e_tx_ctx_desc_eipt_offload {
1092         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1093         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1094         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1095         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1096 };
1097
1098 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1099 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1100                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1101
1102 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1103 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1104
1105 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1106 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1107
1108 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1109 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1110
1111 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1112
1113 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1114 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1115                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1116
1117 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1118 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1119                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1120
1121 struct i40e_nop_desc {
1122         __le64 rsvd;
1123         __le64 dtype_cmd;
1124 };
1125
1126 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1127 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1128
1129 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1130 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1131
1132 enum i40e_tx_nop_desc_cmd_bits {
1133         /* Note: These are predefined bit offsets */
1134         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1135         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1136         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1137 };
1138
1139 struct i40e_filter_program_desc {
1140         __le32 qindex_flex_ptype_vsi;
1141         __le32 rsvd;
1142         __le32 dtype_cmd_cntindex;
1143         __le32 fd_id;
1144 };
1145 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1146 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1147                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1148 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1149 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1150                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1151 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1152 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1153                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1154
1155 /* Packet Classifier Types for filters */
1156 enum i40e_filter_pctype {
1157         /* Note: Values 0-30 are reserved for future use */
1158         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1159         /* Note: Value 32 is reserved for future use */
1160         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1161         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1162         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1163         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1164         /* Note: Values 37-40 are reserved for future use */
1165         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1166         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1167         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1168         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1169         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1170         /* Note: Value 47 is reserved for future use */
1171         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1172         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1173         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1174         /* Note: Values 51-62 are reserved for future use */
1175         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1176 };
1177
1178 enum i40e_filter_program_desc_dest {
1179         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1180         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1181         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1182 };
1183
1184 enum i40e_filter_program_desc_fd_status {
1185         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1186         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1187         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1188         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1189 };
1190
1191 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1192 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1193                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1194
1195 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1196 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1197
1198 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1199 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1200                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1201
1202 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1203 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1204
1205 enum i40e_filter_program_desc_pcmd {
1206         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1207         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1208 };
1209
1210 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1211 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1212
1213 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1214 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1215
1216 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1217                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1218 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1219                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1220
1221 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1222 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1223                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1224
1225 enum i40e_filter_type {
1226         I40E_FLOW_DIRECTOR_FLTR = 0,
1227         I40E_PE_QUAD_HASH_FLTR = 1,
1228         I40E_ETHERTYPE_FLTR,
1229         I40E_FCOE_CTX_FLTR,
1230         I40E_MAC_VLAN_FLTR,
1231         I40E_HASH_FLTR
1232 };
1233
1234 struct i40e_vsi_context {
1235         u16 seid;
1236         u16 uplink_seid;
1237         u16 vsi_number;
1238         u16 vsis_allocated;
1239         u16 vsis_unallocated;
1240         u16 flags;
1241         u8 pf_num;
1242         u8 vf_num;
1243         u8 connection_type;
1244         struct i40e_aqc_vsi_properties_data info;
1245 };
1246
1247 struct i40e_veb_context {
1248         u16 seid;
1249         u16 uplink_seid;
1250         u16 veb_number;
1251         u16 vebs_allocated;
1252         u16 vebs_unallocated;
1253         u16 flags;
1254         struct i40e_aqc_get_veb_parameters_completion info;
1255 };
1256
1257 /* Statistics collected by each port, VSI, VEB, and S-channel */
1258 struct i40e_eth_stats {
1259         u64 rx_bytes;                   /* gorc */
1260         u64 rx_unicast;                 /* uprc */
1261         u64 rx_multicast;               /* mprc */
1262         u64 rx_broadcast;               /* bprc */
1263         u64 rx_discards;                /* rdpc */
1264         u64 rx_unknown_protocol;        /* rupp */
1265         u64 tx_bytes;                   /* gotc */
1266         u64 tx_unicast;                 /* uptc */
1267         u64 tx_multicast;               /* mptc */
1268         u64 tx_broadcast;               /* bptc */
1269         u64 tx_discards;                /* tdpc */
1270         u64 tx_errors;                  /* tepc */
1271 };
1272
1273 /* Statistics collected per VEB per TC */
1274 struct i40e_veb_tc_stats {
1275         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1276         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1277         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1278         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1279 };
1280
1281 /* Statistics collected by the MAC */
1282 struct i40e_hw_port_stats {
1283         /* eth stats collected by the port */
1284         struct i40e_eth_stats eth;
1285
1286         /* additional port specific stats */
1287         u64 tx_dropped_link_down;       /* tdold */
1288         u64 crc_errors;                 /* crcerrs */
1289         u64 illegal_bytes;              /* illerrc */
1290         u64 error_bytes;                /* errbc */
1291         u64 mac_local_faults;           /* mlfc */
1292         u64 mac_remote_faults;          /* mrfc */
1293         u64 rx_length_errors;           /* rlec */
1294         u64 link_xon_rx;                /* lxonrxc */
1295         u64 link_xoff_rx;               /* lxoffrxc */
1296         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1297         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1298         u64 link_xon_tx;                /* lxontxc */
1299         u64 link_xoff_tx;               /* lxofftxc */
1300         u64 priority_xon_tx[8];         /* pxontxc[8] */
1301         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1302         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1303         u64 rx_size_64;                 /* prc64 */
1304         u64 rx_size_127;                /* prc127 */
1305         u64 rx_size_255;                /* prc255 */
1306         u64 rx_size_511;                /* prc511 */
1307         u64 rx_size_1023;               /* prc1023 */
1308         u64 rx_size_1522;               /* prc1522 */
1309         u64 rx_size_big;                /* prc9522 */
1310         u64 rx_undersize;               /* ruc */
1311         u64 rx_fragments;               /* rfc */
1312         u64 rx_oversize;                /* roc */
1313         u64 rx_jabber;                  /* rjc */
1314         u64 tx_size_64;                 /* ptc64 */
1315         u64 tx_size_127;                /* ptc127 */
1316         u64 tx_size_255;                /* ptc255 */
1317         u64 tx_size_511;                /* ptc511 */
1318         u64 tx_size_1023;               /* ptc1023 */
1319         u64 tx_size_1522;               /* ptc1522 */
1320         u64 tx_size_big;                /* ptc9522 */
1321         u64 mac_short_packet_dropped;   /* mspdc */
1322         u64 checksum_error;             /* xec */
1323         /* flow director stats */
1324         u64 fd_atr_match;
1325         u64 fd_sb_match;
1326         /* EEE LPI */
1327         u32 tx_lpi_status;
1328         u32 rx_lpi_status;
1329         u64 tx_lpi_count;               /* etlpic */
1330         u64 rx_lpi_count;               /* erlpic */
1331 };
1332
1333 /* Checksum and Shadow RAM pointers */
1334 #define I40E_SR_NVM_CONTROL_WORD                0x00
1335 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1336 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1337 #define I40E_SR_OPTION_ROM_PTR                  0x05
1338 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1339 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1340 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1341 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1342 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1343 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1344 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1345 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1346 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1347 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1348 #define I40E_SR_PBA_FLAGS                       0x15
1349 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1350 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1351 #define I40E_NVM_OEM_VER_OFF                    0x83
1352 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1353 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1354 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1355 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1356 #define I40E_SR_NVM_MAP_VERSION                 0x29
1357 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1358 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1359 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1360 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1361 #define I40E_SR_VPD_PTR                         0x2F
1362 #define I40E_SR_PXE_SETUP_PTR                   0x30
1363 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1364 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1365 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1366 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1367 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1368 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1369 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1370 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1371 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1372 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1373 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1374 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1375 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1376 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1377 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1378 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1379 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1380 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1381
1382 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1383 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1384 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1385 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1386 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1387
1388 /* Shadow RAM related */
1389 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1390 #define I40E_SR_BUF_ALIGNMENT           4096
1391 #define I40E_SR_WORDS_IN_1KB            512
1392 /* Checksum should be calculated such that after adding all the words,
1393  * including the checksum word itself, the sum should be 0xBABA.
1394  */
1395 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1396
1397 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1398
1399 enum i40e_switch_element_types {
1400         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1401         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1402         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1403         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1404         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1405         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1406         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1407         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1408         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1409 };
1410
1411 /* Supported EtherType filters */
1412 enum i40e_ether_type_index {
1413         I40E_ETHER_TYPE_1588            = 0,
1414         I40E_ETHER_TYPE_FIP             = 1,
1415         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1416         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1417         I40E_ETHER_TYPE_LLDP            = 4,
1418         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1419         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1420         I40E_ETHER_TYPE_QCN_CNM         = 7,
1421         I40E_ETHER_TYPE_8021X           = 8,
1422         I40E_ETHER_TYPE_ARP             = 9,
1423         I40E_ETHER_TYPE_RSV1            = 10,
1424         I40E_ETHER_TYPE_RSV2            = 11,
1425 };
1426
1427 /* Filter context base size is 1K */
1428 #define I40E_HASH_FILTER_BASE_SIZE      1024
1429 /* Supported Hash filter values */
1430 enum i40e_hash_filter_size {
1431         I40E_HASH_FILTER_SIZE_1K        = 0,
1432         I40E_HASH_FILTER_SIZE_2K        = 1,
1433         I40E_HASH_FILTER_SIZE_4K        = 2,
1434         I40E_HASH_FILTER_SIZE_8K        = 3,
1435         I40E_HASH_FILTER_SIZE_16K       = 4,
1436         I40E_HASH_FILTER_SIZE_32K       = 5,
1437         I40E_HASH_FILTER_SIZE_64K       = 6,
1438         I40E_HASH_FILTER_SIZE_128K      = 7,
1439         I40E_HASH_FILTER_SIZE_256K      = 8,
1440         I40E_HASH_FILTER_SIZE_512K      = 9,
1441         I40E_HASH_FILTER_SIZE_1M        = 10,
1442 };
1443
1444 /* DMA context base size is 0.5K */
1445 #define I40E_DMA_CNTX_BASE_SIZE         512
1446 /* Supported DMA context values */
1447 enum i40e_dma_cntx_size {
1448         I40E_DMA_CNTX_SIZE_512          = 0,
1449         I40E_DMA_CNTX_SIZE_1K           = 1,
1450         I40E_DMA_CNTX_SIZE_2K           = 2,
1451         I40E_DMA_CNTX_SIZE_4K           = 3,
1452         I40E_DMA_CNTX_SIZE_8K           = 4,
1453         I40E_DMA_CNTX_SIZE_16K          = 5,
1454         I40E_DMA_CNTX_SIZE_32K          = 6,
1455         I40E_DMA_CNTX_SIZE_64K          = 7,
1456         I40E_DMA_CNTX_SIZE_128K         = 8,
1457         I40E_DMA_CNTX_SIZE_256K         = 9,
1458 };
1459
1460 /* Supported Hash look up table (LUT) sizes */
1461 enum i40e_hash_lut_size {
1462         I40E_HASH_LUT_SIZE_128          = 0,
1463         I40E_HASH_LUT_SIZE_512          = 1,
1464 };
1465
1466 /* Structure to hold a per PF filter control settings */
1467 struct i40e_filter_control_settings {
1468         /* number of PE Quad Hash filter buckets */
1469         enum i40e_hash_filter_size pe_filt_num;
1470         /* number of PE Quad Hash contexts */
1471         enum i40e_dma_cntx_size pe_cntx_num;
1472         /* number of FCoE filter buckets */
1473         enum i40e_hash_filter_size fcoe_filt_num;
1474         /* number of FCoE DDP contexts */
1475         enum i40e_dma_cntx_size fcoe_cntx_num;
1476         /* size of the Hash LUT */
1477         enum i40e_hash_lut_size hash_lut_size;
1478         /* enable FDIR filters for PF and its VFs */
1479         bool enable_fdir;
1480         /* enable Ethertype filters for PF and its VFs */
1481         bool enable_ethtype;
1482         /* enable MAC/VLAN filters for PF and its VFs */
1483         bool enable_macvlan;
1484 };
1485
1486 /* Structure to hold device level control filter counts */
1487 struct i40e_control_filter_stats {
1488         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1489         u16 etype_used;       /* Used perfect EtherType filters */
1490         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1491         u16 etype_free;       /* Un-used perfect EtherType filters */
1492 };
1493
1494 enum i40e_reset_type {
1495         I40E_RESET_POR          = 0,
1496         I40E_RESET_CORER        = 1,
1497         I40E_RESET_GLOBR        = 2,
1498         I40E_RESET_EMPR         = 3,
1499 };
1500
1501 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1502 #define I40E_NVM_LLDP_CFG_PTR           0xD
1503 struct i40e_lldp_variables {
1504         u16 length;
1505         u16 adminstatus;
1506         u16 msgfasttx;
1507         u16 msgtxinterval;
1508         u16 txparams;
1509         u16 timers;
1510         u16 crc8;
1511 };
1512
1513 /* Offsets into Alternate Ram */
1514 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1515 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1516 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1517 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1518 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1519 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1520
1521 /* Alternate Ram Bandwidth Masks */
1522 #define I40E_ALT_BW_VALUE_MASK          0xFF
1523 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1524 #define I40E_ALT_BW_VALID_MASK          0x80000000
1525
1526 /* RSS Hash Table Size */
1527 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1528 #endif /* _I40E_TYPE_H_ */