4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 /* The max bandwidth of i40e is 40Gbps. */
247 #define I40E_QOS_BW_MAX 40000
248 /* The bandwidth should be the multiple of 50Mbps. */
249 #define I40E_QOS_BW_GRANULARITY 50
250 /* The min bandwidth weight is 1. */
251 #define I40E_QOS_BW_WEIGHT_MIN 1
252 /* The max bandwidth weight is 127. */
253 #define I40E_QOS_BW_WEIGHT_MAX 127
255 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
256 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
257 static int i40e_dev_configure(struct rte_eth_dev *dev);
258 static int i40e_dev_start(struct rte_eth_dev *dev);
259 static void i40e_dev_stop(struct rte_eth_dev *dev);
260 static void i40e_dev_close(struct rte_eth_dev *dev);
261 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
262 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
263 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
264 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
266 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
267 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
270 struct rte_eth_xstat *xstats, unsigned n);
271 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
272 struct rte_eth_xstat_name *xstats_names,
274 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
275 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
279 static int i40e_fw_version_get(struct rte_eth_dev *dev,
280 char *fw_version, size_t fw_size);
281 static void i40e_dev_info_get(struct rte_eth_dev *dev,
282 struct rte_eth_dev_info *dev_info);
283 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
287 enum rte_vlan_type vlan_type,
289 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
290 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
293 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
294 static int i40e_dev_led_on(struct rte_eth_dev *dev);
295 static int i40e_dev_led_off(struct rte_eth_dev *dev);
296 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
297 struct rte_eth_fc_conf *fc_conf);
298 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
299 struct rte_eth_fc_conf *fc_conf);
300 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
301 struct rte_eth_pfc_conf *pfc_conf);
302 static void i40e_macaddr_add(struct rte_eth_dev *dev,
303 struct ether_addr *mac_addr,
306 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
307 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
308 struct rte_eth_rss_reta_entry64 *reta_conf,
310 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
311 struct rte_eth_rss_reta_entry64 *reta_conf,
314 static int i40e_get_cap(struct i40e_hw *hw);
315 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
316 static int i40e_pf_setup(struct i40e_pf *pf);
317 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
318 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
319 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
320 static int i40e_dcb_setup(struct rte_eth_dev *dev);
321 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
322 bool offset_loaded, uint64_t *offset, uint64_t *stat);
323 static void i40e_stat_update_48(struct i40e_hw *hw,
329 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
330 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
332 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
333 uint32_t base, uint32_t num);
334 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
335 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
337 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
339 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
340 static int i40e_veb_release(struct i40e_veb *veb);
341 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
342 struct i40e_vsi *vsi);
343 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
344 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
345 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
346 struct i40e_macvlan_filter *mv_f,
348 struct ether_addr *addr);
349 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
350 struct i40e_macvlan_filter *mv_f,
353 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
354 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
355 struct rte_eth_rss_conf *rss_conf);
356 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
357 struct rte_eth_rss_conf *rss_conf);
358 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
359 struct rte_eth_udp_tunnel *udp_tunnel);
360 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static void i40e_filter_input_set_init(struct i40e_pf *pf);
363 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
366 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
367 enum rte_filter_type filter_type,
368 enum rte_filter_op filter_op,
370 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
371 struct rte_eth_dcb_info *dcb_info);
372 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
373 static void i40e_configure_registers(struct i40e_hw *hw);
374 static void i40e_hw_init(struct rte_eth_dev *dev);
375 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
376 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
377 struct rte_eth_mirror_conf *mirror_conf,
378 uint8_t sw_id, uint8_t on);
379 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
381 static int i40e_timesync_enable(struct rte_eth_dev *dev);
382 static int i40e_timesync_disable(struct rte_eth_dev *dev);
383 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
384 struct timespec *timestamp,
386 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
387 struct timespec *timestamp);
388 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
390 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
392 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
393 struct timespec *timestamp);
394 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
395 const struct timespec *timestamp);
397 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
399 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
402 static int i40e_get_regs(struct rte_eth_dev *dev,
403 struct rte_dev_reg_info *regs);
405 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
407 static int i40e_get_eeprom(struct rte_eth_dev *dev,
408 struct rte_dev_eeprom_info *eeprom);
410 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
411 struct ether_addr *mac_addr);
413 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
415 static int i40e_ethertype_filter_convert(
416 const struct rte_eth_ethertype_filter *input,
417 struct i40e_ethertype_filter *filter);
418 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
419 struct i40e_ethertype_filter *filter);
421 static int i40e_tunnel_filter_convert(
422 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
423 struct i40e_tunnel_filter *tunnel_filter);
424 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
425 struct i40e_tunnel_filter *tunnel_filter);
427 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
428 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
429 static void i40e_filter_restore(struct i40e_pf *pf);
431 static const struct rte_pci_id pci_id_i40e_map[] = {
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
452 { .vendor_id = 0, /* sentinel */ },
455 static const struct eth_dev_ops i40e_eth_dev_ops = {
456 .dev_configure = i40e_dev_configure,
457 .dev_start = i40e_dev_start,
458 .dev_stop = i40e_dev_stop,
459 .dev_close = i40e_dev_close,
460 .promiscuous_enable = i40e_dev_promiscuous_enable,
461 .promiscuous_disable = i40e_dev_promiscuous_disable,
462 .allmulticast_enable = i40e_dev_allmulticast_enable,
463 .allmulticast_disable = i40e_dev_allmulticast_disable,
464 .dev_set_link_up = i40e_dev_set_link_up,
465 .dev_set_link_down = i40e_dev_set_link_down,
466 .link_update = i40e_dev_link_update,
467 .stats_get = i40e_dev_stats_get,
468 .xstats_get = i40e_dev_xstats_get,
469 .xstats_get_names = i40e_dev_xstats_get_names,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .fw_version_get = i40e_fw_version_get,
474 .dev_infos_get = i40e_dev_info_get,
475 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
476 .vlan_filter_set = i40e_vlan_filter_set,
477 .vlan_tpid_set = i40e_vlan_tpid_set,
478 .vlan_offload_set = i40e_vlan_offload_set,
479 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
480 .vlan_pvid_set = i40e_vlan_pvid_set,
481 .rx_queue_start = i40e_dev_rx_queue_start,
482 .rx_queue_stop = i40e_dev_rx_queue_stop,
483 .tx_queue_start = i40e_dev_tx_queue_start,
484 .tx_queue_stop = i40e_dev_tx_queue_stop,
485 .rx_queue_setup = i40e_dev_rx_queue_setup,
486 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
487 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
488 .rx_queue_release = i40e_dev_rx_queue_release,
489 .rx_queue_count = i40e_dev_rx_queue_count,
490 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
491 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
492 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
493 .tx_queue_setup = i40e_dev_tx_queue_setup,
494 .tx_queue_release = i40e_dev_tx_queue_release,
495 .dev_led_on = i40e_dev_led_on,
496 .dev_led_off = i40e_dev_led_off,
497 .flow_ctrl_get = i40e_flow_ctrl_get,
498 .flow_ctrl_set = i40e_flow_ctrl_set,
499 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
500 .mac_addr_add = i40e_macaddr_add,
501 .mac_addr_remove = i40e_macaddr_remove,
502 .reta_update = i40e_dev_rss_reta_update,
503 .reta_query = i40e_dev_rss_reta_query,
504 .rss_hash_update = i40e_dev_rss_hash_update,
505 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
506 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
507 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
508 .filter_ctrl = i40e_dev_filter_ctrl,
509 .rxq_info_get = i40e_rxq_info_get,
510 .txq_info_get = i40e_txq_info_get,
511 .mirror_rule_set = i40e_mirror_rule_set,
512 .mirror_rule_reset = i40e_mirror_rule_reset,
513 .timesync_enable = i40e_timesync_enable,
514 .timesync_disable = i40e_timesync_disable,
515 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
516 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
517 .get_dcb_info = i40e_dev_get_dcb_info,
518 .timesync_adjust_time = i40e_timesync_adjust_time,
519 .timesync_read_time = i40e_timesync_read_time,
520 .timesync_write_time = i40e_timesync_write_time,
521 .get_reg = i40e_get_regs,
522 .get_eeprom_length = i40e_get_eeprom_length,
523 .get_eeprom = i40e_get_eeprom,
524 .mac_addr_set = i40e_set_default_mac_addr,
525 .mtu_set = i40e_dev_mtu_set,
528 /* store statistics names and its offset in stats structure */
529 struct rte_i40e_xstats_name_off {
530 char name[RTE_ETH_XSTATS_NAME_SIZE];
534 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
535 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
536 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
537 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
538 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
539 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
540 rx_unknown_protocol)},
541 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
542 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
543 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
544 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
547 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
548 sizeof(rte_i40e_stats_strings[0]))
550 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
551 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
552 tx_dropped_link_down)},
553 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
554 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
556 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
557 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
559 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
563 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
564 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
565 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
566 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
567 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
568 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
585 mac_short_packet_dropped)},
586 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
589 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
590 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
602 {"rx_flow_director_atr_match_packets",
603 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
604 {"rx_flow_director_sb_match_packets",
605 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
606 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
608 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
610 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
617 sizeof(rte_i40e_hw_port_strings[0]))
619 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
620 {"xon_packets", offsetof(struct i40e_hw_port_stats,
622 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
627 sizeof(rte_i40e_rxq_prio_strings[0]))
629 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
630 {"xon_packets", offsetof(struct i40e_hw_port_stats,
632 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
634 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
635 priority_xon_2_xoff)},
638 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
639 sizeof(rte_i40e_txq_prio_strings[0]))
641 static struct eth_driver rte_i40e_pmd = {
643 .id_table = pci_id_i40e_map,
644 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
645 .probe = rte_eth_dev_pci_probe,
646 .remove = rte_eth_dev_pci_remove,
648 .eth_dev_init = eth_i40e_dev_init,
649 .eth_dev_uninit = eth_i40e_dev_uninit,
650 .dev_private_size = sizeof(struct i40e_adapter),
654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
655 struct rte_eth_link *link)
657 struct rte_eth_link *dst = link;
658 struct rte_eth_link *src = &(dev->data->dev_link);
660 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
661 *(uint64_t *)src) == 0)
668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
669 struct rte_eth_link *link)
671 struct rte_eth_link *dst = &(dev->data->dev_link);
672 struct rte_eth_link *src = link;
674 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
675 *(uint64_t *)src) == 0)
681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
685 #ifndef I40E_GLQF_ORT
686 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
688 #ifndef I40E_GLQF_PIT
689 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
692 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
695 * Initialize registers for flexible payload, which should be set by NVM.
696 * This should be removed from code once it is fixed in NVM.
698 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
699 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
700 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
708 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
709 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
711 /* Initialize registers for parsing packet type of QinQ */
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
713 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
716 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
719 * Add a ethertype filter to drop all flow control frames transmitted
723 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
725 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
726 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
727 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
728 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
731 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
732 I40E_FLOW_CONTROL_ETHERTYPE, flags,
733 pf->main_vsi_seid, 0,
737 "Failed to add filter to drop flow control frames from VSIs.");
741 floating_veb_list_handler(__rte_unused const char *key,
742 const char *floating_veb_value,
746 unsigned int count = 0;
749 bool *vf_floating_veb = opaque;
751 while (isblank(*floating_veb_value))
752 floating_veb_value++;
754 /* Reset floating VEB configuration for VFs */
755 for (idx = 0; idx < I40E_MAX_VF; idx++)
756 vf_floating_veb[idx] = false;
760 while (isblank(*floating_veb_value))
761 floating_veb_value++;
762 if (*floating_veb_value == '\0')
765 idx = strtoul(floating_veb_value, &end, 10);
766 if (errno || end == NULL)
768 while (isblank(*end))
772 } else if ((*end == ';') || (*end == '\0')) {
774 if (min == I40E_MAX_VF)
776 if (max >= I40E_MAX_VF)
777 max = I40E_MAX_VF - 1;
778 for (idx = min; idx <= max; idx++) {
779 vf_floating_veb[idx] = true;
786 floating_veb_value = end + 1;
787 } while (*end != '\0');
796 config_vf_floating_veb(struct rte_devargs *devargs,
797 uint16_t floating_veb,
798 bool *vf_floating_veb)
800 struct rte_kvargs *kvlist;
802 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
806 /* All the VFs attach to the floating VEB by default
807 * when the floating VEB is enabled.
809 for (i = 0; i < I40E_MAX_VF; i++)
810 vf_floating_veb[i] = true;
815 kvlist = rte_kvargs_parse(devargs->args, NULL);
819 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
820 rte_kvargs_free(kvlist);
823 /* When the floating_veb_list parameter exists, all the VFs
824 * will attach to the legacy VEB firstly, then configure VFs
825 * to the floating VEB according to the floating_veb_list.
827 if (rte_kvargs_process(kvlist, floating_veb_list,
828 floating_veb_list_handler,
829 vf_floating_veb) < 0) {
830 rte_kvargs_free(kvlist);
833 rte_kvargs_free(kvlist);
837 i40e_check_floating_handler(__rte_unused const char *key,
839 __rte_unused void *opaque)
841 if (strcmp(value, "1"))
848 is_floating_veb_supported(struct rte_devargs *devargs)
850 struct rte_kvargs *kvlist;
851 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
856 kvlist = rte_kvargs_parse(devargs->args, NULL);
860 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
861 rte_kvargs_free(kvlist);
864 /* Floating VEB is enabled when there's key-value:
865 * enable_floating_veb=1
867 if (rte_kvargs_process(kvlist, floating_veb_key,
868 i40e_check_floating_handler, NULL) < 0) {
869 rte_kvargs_free(kvlist);
872 rte_kvargs_free(kvlist);
878 config_floating_veb(struct rte_eth_dev *dev)
880 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
884 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
886 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
888 is_floating_veb_supported(pci_dev->device.devargs);
889 config_vf_floating_veb(pci_dev->device.devargs,
891 pf->floating_veb_list);
893 pf->floating_veb = false;
897 #define I40E_L2_TAGS_S_TAG_SHIFT 1
898 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
901 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
903 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
904 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
905 char ethertype_hash_name[RTE_HASH_NAMESIZE];
908 struct rte_hash_parameters ethertype_hash_params = {
909 .name = ethertype_hash_name,
910 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
911 .key_len = sizeof(struct i40e_ethertype_filter_input),
912 .hash_func = rte_hash_crc,
913 .hash_func_init_val = 0,
914 .socket_id = rte_socket_id(),
917 /* Initialize ethertype filter rule list and hash */
918 TAILQ_INIT(ðertype_rule->ethertype_list);
919 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
920 "ethertype_%s", dev->data->name);
921 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
922 if (!ethertype_rule->hash_table) {
923 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
926 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
927 sizeof(struct i40e_ethertype_filter *) *
928 I40E_MAX_ETHERTYPE_FILTER_NUM,
930 if (!ethertype_rule->hash_map) {
932 "Failed to allocate memory for ethertype hash map!");
934 goto err_ethertype_hash_map_alloc;
939 err_ethertype_hash_map_alloc:
940 rte_hash_free(ethertype_rule->hash_table);
946 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
949 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
950 char tunnel_hash_name[RTE_HASH_NAMESIZE];
953 struct rte_hash_parameters tunnel_hash_params = {
954 .name = tunnel_hash_name,
955 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
956 .key_len = sizeof(struct i40e_tunnel_filter_input),
957 .hash_func = rte_hash_crc,
958 .hash_func_init_val = 0,
959 .socket_id = rte_socket_id(),
962 /* Initialize tunnel filter rule list and hash */
963 TAILQ_INIT(&tunnel_rule->tunnel_list);
964 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
965 "tunnel_%s", dev->data->name);
966 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
967 if (!tunnel_rule->hash_table) {
968 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
971 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
972 sizeof(struct i40e_tunnel_filter *) *
973 I40E_MAX_TUNNEL_FILTER_NUM,
975 if (!tunnel_rule->hash_map) {
977 "Failed to allocate memory for tunnel hash map!");
979 goto err_tunnel_hash_map_alloc;
984 err_tunnel_hash_map_alloc:
985 rte_hash_free(tunnel_rule->hash_table);
991 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
993 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
994 struct i40e_fdir_info *fdir_info = &pf->fdir;
995 char fdir_hash_name[RTE_HASH_NAMESIZE];
998 struct rte_hash_parameters fdir_hash_params = {
999 .name = fdir_hash_name,
1000 .entries = I40E_MAX_FDIR_FILTER_NUM,
1001 .key_len = sizeof(struct rte_eth_fdir_input),
1002 .hash_func = rte_hash_crc,
1003 .hash_func_init_val = 0,
1004 .socket_id = rte_socket_id(),
1007 /* Initialize flow director filter rule list and hash */
1008 TAILQ_INIT(&fdir_info->fdir_list);
1009 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1010 "fdir_%s", dev->data->name);
1011 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1012 if (!fdir_info->hash_table) {
1013 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1016 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1017 sizeof(struct i40e_fdir_filter *) *
1018 I40E_MAX_FDIR_FILTER_NUM,
1020 if (!fdir_info->hash_map) {
1022 "Failed to allocate memory for fdir hash map!");
1024 goto err_fdir_hash_map_alloc;
1028 err_fdir_hash_map_alloc:
1029 rte_hash_free(fdir_info->hash_table);
1035 eth_i40e_dev_init(struct rte_eth_dev *dev)
1037 struct rte_pci_device *pci_dev;
1038 struct rte_intr_handle *intr_handle;
1039 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1040 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1041 struct i40e_vsi *vsi;
1044 uint8_t aq_fail = 0;
1046 PMD_INIT_FUNC_TRACE();
1048 dev->dev_ops = &i40e_eth_dev_ops;
1049 dev->rx_pkt_burst = i40e_recv_pkts;
1050 dev->tx_pkt_burst = i40e_xmit_pkts;
1051 dev->tx_pkt_prepare = i40e_prep_pkts;
1053 /* for secondary processes, we don't initialise any further as primary
1054 * has already done this work. Only check we don't need a different
1056 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1057 i40e_set_rx_function(dev);
1058 i40e_set_tx_function(dev);
1061 pci_dev = I40E_DEV_TO_PCI(dev);
1062 intr_handle = &pci_dev->intr_handle;
1064 rte_eth_copy_pci_info(dev, pci_dev);
1065 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1067 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1068 pf->adapter->eth_dev = dev;
1069 pf->dev_data = dev->data;
1071 hw->back = I40E_PF_TO_ADAPTER(pf);
1072 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1075 "Hardware is not available, as address is NULL");
1079 hw->vendor_id = pci_dev->id.vendor_id;
1080 hw->device_id = pci_dev->id.device_id;
1081 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1082 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1083 hw->bus.device = pci_dev->addr.devid;
1084 hw->bus.func = pci_dev->addr.function;
1085 hw->adapter_stopped = 0;
1087 /* Make sure all is clean before doing PF reset */
1090 /* Initialize the hardware */
1093 /* Reset here to make sure all is clean for each PF */
1094 ret = i40e_pf_reset(hw);
1096 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1100 /* Initialize the shared code (base driver) */
1101 ret = i40e_init_shared_code(hw);
1103 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108 * To work around the NVM issue, initialize registers
1109 * for flexible payload and packet type of QinQ by
1110 * software. It should be removed once issues are fixed
1113 i40e_GLQF_reg_init(hw);
1115 /* Initialize the input set for filters (hash and fd) to default value */
1116 i40e_filter_input_set_init(pf);
1118 /* Initialize the parameters for adminq */
1119 i40e_init_adminq_parameter(hw);
1120 ret = i40e_init_adminq(hw);
1121 if (ret != I40E_SUCCESS) {
1122 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1125 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1126 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1127 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1128 ((hw->nvm.version >> 12) & 0xf),
1129 ((hw->nvm.version >> 4) & 0xff),
1130 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1132 /* Need the special FW version to support floating VEB */
1133 config_floating_veb(dev);
1134 /* Clear PXE mode */
1135 i40e_clear_pxe_mode(hw);
1136 ret = i40e_dev_sync_phy_type(hw);
1138 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1139 goto err_sync_phy_type;
1142 * On X710, performance number is far from the expectation on recent
1143 * firmware versions. The fix for this issue may not be integrated in
1144 * the following firmware version. So the workaround in software driver
1145 * is needed. It needs to modify the initial values of 3 internal only
1146 * registers. Note that the workaround can be removed when it is fixed
1147 * in firmware in the future.
1149 i40e_configure_registers(hw);
1151 /* Get hw capabilities */
1152 ret = i40e_get_cap(hw);
1153 if (ret != I40E_SUCCESS) {
1154 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1155 goto err_get_capabilities;
1158 /* Initialize parameters for PF */
1159 ret = i40e_pf_parameter_init(dev);
1161 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1162 goto err_parameter_init;
1165 /* Initialize the queue management */
1166 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1168 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1169 goto err_qp_pool_init;
1171 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1172 hw->func_caps.num_msix_vectors - 1);
1174 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1175 goto err_msix_pool_init;
1178 /* Initialize lan hmc */
1179 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1180 hw->func_caps.num_rx_qp, 0, 0);
1181 if (ret != I40E_SUCCESS) {
1182 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1183 goto err_init_lan_hmc;
1186 /* Configure lan hmc */
1187 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1188 if (ret != I40E_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1190 goto err_configure_lan_hmc;
1193 /* Get and check the mac address */
1194 i40e_get_mac_addr(hw, hw->mac.addr);
1195 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1196 PMD_INIT_LOG(ERR, "mac address is not valid");
1198 goto err_get_mac_addr;
1200 /* Copy the permanent MAC address */
1201 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1202 (struct ether_addr *) hw->mac.perm_addr);
1204 /* Disable flow control */
1205 hw->fc.requested_mode = I40E_FC_NONE;
1206 i40e_set_fc(hw, &aq_fail, TRUE);
1208 /* Set the global registers with default ether type value */
1209 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1210 if (ret != I40E_SUCCESS) {
1212 "Failed to set the default outer VLAN ether type");
1213 goto err_setup_pf_switch;
1216 /* PF setup, which includes VSI setup */
1217 ret = i40e_pf_setup(pf);
1219 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220 goto err_setup_pf_switch;
1223 /* reset all stats of the device, including pf and main vsi */
1224 i40e_dev_stats_reset(dev);
1228 /* Disable double vlan by default */
1229 i40e_vsi_config_double_vlan(vsi, FALSE);
1231 /* Disable S-TAG identification when floating_veb is disabled */
1232 if (!pf->floating_veb) {
1233 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1240 if (!vsi->max_macaddrs)
1241 len = ETHER_ADDR_LEN;
1243 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1245 /* Should be after VSI initialized */
1246 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247 if (!dev->data->mac_addrs) {
1249 "Failed to allocated memory for storing mac address");
1252 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253 &dev->data->mac_addrs[0]);
1255 /* Init dcb to sw mode by default */
1256 ret = i40e_dcb_init_configure(dev, TRUE);
1257 if (ret != I40E_SUCCESS) {
1258 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1259 pf->flags &= ~I40E_FLAG_DCB;
1261 /* Update HW struct after DCB configuration */
1264 /* initialize pf host driver to setup SRIOV resource if applicable */
1265 i40e_pf_host_init(dev);
1267 /* register callback func to eal lib */
1268 rte_intr_callback_register(intr_handle,
1269 i40e_dev_interrupt_handler, dev);
1271 /* configure and enable device interrupt */
1272 i40e_pf_config_irq0(hw, TRUE);
1273 i40e_pf_enable_irq0(hw);
1275 /* enable uio intr after callback register */
1276 rte_intr_enable(intr_handle);
1278 * Add an ethertype filter to drop all flow control frames transmitted
1279 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1282 i40e_add_tx_flow_control_drop_filter(pf);
1284 /* Set the max frame size to 0x2600 by default,
1285 * in case other drivers changed the default value.
1287 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1289 /* initialize mirror rule list */
1290 TAILQ_INIT(&pf->mirror_list);
1292 ret = i40e_init_ethtype_filter_list(dev);
1294 goto err_init_ethtype_filter_list;
1295 ret = i40e_init_tunnel_filter_list(dev);
1297 goto err_init_tunnel_filter_list;
1298 ret = i40e_init_fdir_filter_list(dev);
1300 goto err_init_fdir_filter_list;
1304 err_init_fdir_filter_list:
1305 rte_free(pf->tunnel.hash_table);
1306 rte_free(pf->tunnel.hash_map);
1307 err_init_tunnel_filter_list:
1308 rte_free(pf->ethertype.hash_table);
1309 rte_free(pf->ethertype.hash_map);
1310 err_init_ethtype_filter_list:
1311 rte_free(dev->data->mac_addrs);
1313 i40e_vsi_release(pf->main_vsi);
1314 err_setup_pf_switch:
1316 err_configure_lan_hmc:
1317 (void)i40e_shutdown_lan_hmc(hw);
1319 i40e_res_pool_destroy(&pf->msix_pool);
1321 i40e_res_pool_destroy(&pf->qp_pool);
1324 err_get_capabilities:
1326 (void)i40e_shutdown_adminq(hw);
1332 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1334 struct i40e_ethertype_filter *p_ethertype;
1335 struct i40e_ethertype_rule *ethertype_rule;
1337 ethertype_rule = &pf->ethertype;
1338 /* Remove all ethertype filter rules and hash */
1339 if (ethertype_rule->hash_map)
1340 rte_free(ethertype_rule->hash_map);
1341 if (ethertype_rule->hash_table)
1342 rte_hash_free(ethertype_rule->hash_table);
1344 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1345 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1346 p_ethertype, rules);
1347 rte_free(p_ethertype);
1352 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1354 struct i40e_tunnel_filter *p_tunnel;
1355 struct i40e_tunnel_rule *tunnel_rule;
1357 tunnel_rule = &pf->tunnel;
1358 /* Remove all tunnel director rules and hash */
1359 if (tunnel_rule->hash_map)
1360 rte_free(tunnel_rule->hash_map);
1361 if (tunnel_rule->hash_table)
1362 rte_hash_free(tunnel_rule->hash_table);
1364 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1365 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1371 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1373 struct i40e_fdir_filter *p_fdir;
1374 struct i40e_fdir_info *fdir_info;
1376 fdir_info = &pf->fdir;
1377 /* Remove all flow director rules and hash */
1378 if (fdir_info->hash_map)
1379 rte_free(fdir_info->hash_map);
1380 if (fdir_info->hash_table)
1381 rte_hash_free(fdir_info->hash_table);
1383 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1384 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1390 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1393 struct rte_pci_device *pci_dev;
1394 struct rte_intr_handle *intr_handle;
1396 struct i40e_filter_control_settings settings;
1397 struct rte_flow *p_flow;
1399 uint8_t aq_fail = 0;
1401 PMD_INIT_FUNC_TRACE();
1403 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1406 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1407 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408 pci_dev = I40E_DEV_TO_PCI(dev);
1409 intr_handle = &pci_dev->intr_handle;
1411 if (hw->adapter_stopped == 0)
1412 i40e_dev_close(dev);
1414 dev->dev_ops = NULL;
1415 dev->rx_pkt_burst = NULL;
1416 dev->tx_pkt_burst = NULL;
1418 /* Clear PXE mode */
1419 i40e_clear_pxe_mode(hw);
1421 /* Unconfigure filter control */
1422 memset(&settings, 0, sizeof(settings));
1423 ret = i40e_set_filter_control(hw, &settings);
1425 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1428 /* Disable flow control */
1429 hw->fc.requested_mode = I40E_FC_NONE;
1430 i40e_set_fc(hw, &aq_fail, TRUE);
1432 /* uninitialize pf host driver */
1433 i40e_pf_host_uninit(dev);
1435 rte_free(dev->data->mac_addrs);
1436 dev->data->mac_addrs = NULL;
1438 /* disable uio intr before callback unregister */
1439 rte_intr_disable(intr_handle);
1441 /* register callback func to eal lib */
1442 rte_intr_callback_unregister(intr_handle,
1443 i40e_dev_interrupt_handler, dev);
1445 i40e_rm_ethtype_filter_list(pf);
1446 i40e_rm_tunnel_filter_list(pf);
1447 i40e_rm_fdir_filter_list(pf);
1449 /* Remove all flows */
1450 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1451 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1459 i40e_dev_configure(struct rte_eth_dev *dev)
1461 struct i40e_adapter *ad =
1462 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1464 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1467 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1468 * bulk allocation or vector Rx preconditions we will reset it.
1470 ad->rx_bulk_alloc_allowed = true;
1471 ad->rx_vec_allowed = true;
1472 ad->tx_simple_allowed = true;
1473 ad->tx_vec_allowed = true;
1475 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1476 ret = i40e_fdir_setup(pf);
1477 if (ret != I40E_SUCCESS) {
1478 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1481 ret = i40e_fdir_configure(dev);
1483 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1487 i40e_fdir_teardown(pf);
1489 ret = i40e_dev_init_vlan(dev);
1494 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1495 * RSS setting have different requirements.
1496 * General PMD driver call sequence are NIC init, configure,
1497 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1498 * will try to lookup the VSI that specific queue belongs to if VMDQ
1499 * applicable. So, VMDQ setting has to be done before
1500 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1501 * For RSS setting, it will try to calculate actual configured RX queue
1502 * number, which will be available after rx_queue_setup(). dev_start()
1503 * function is good to place RSS setup.
1505 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1506 ret = i40e_vmdq_setup(dev);
1511 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1512 ret = i40e_dcb_setup(dev);
1514 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1519 TAILQ_INIT(&pf->flow_list);
1524 /* need to release vmdq resource if exists */
1525 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1526 i40e_vsi_release(pf->vmdq[i].vsi);
1527 pf->vmdq[i].vsi = NULL;
1532 /* need to release fdir resource if exists */
1533 i40e_fdir_teardown(pf);
1538 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1540 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1541 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1542 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1544 uint16_t msix_vect = vsi->msix_intr;
1547 for (i = 0; i < vsi->nb_qps; i++) {
1548 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1549 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1553 if (vsi->type != I40E_VSI_SRIOV) {
1554 if (!rte_intr_allow_others(intr_handle)) {
1555 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1556 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1558 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1561 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1562 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1564 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1569 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1570 vsi->user_param + (msix_vect - 1);
1572 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1573 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1575 I40E_WRITE_FLUSH(hw);
1579 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1580 int base_queue, int nb_queue)
1584 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1586 /* Bind all RX queues to allocated MSIX interrupt */
1587 for (i = 0; i < nb_queue; i++) {
1588 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1589 I40E_QINT_RQCTL_ITR_INDX_MASK |
1590 ((base_queue + i + 1) <<
1591 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1592 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1593 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1595 if (i == nb_queue - 1)
1596 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1597 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1600 /* Write first RX queue to Link list register as the head element */
1601 if (vsi->type != I40E_VSI_SRIOV) {
1603 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1605 if (msix_vect == I40E_MISC_VEC_ID) {
1606 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1608 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1610 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1612 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1615 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1617 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1619 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1621 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1628 if (msix_vect == I40E_MISC_VEC_ID) {
1630 I40E_VPINT_LNKLST0(vsi->user_param),
1632 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1634 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1636 /* num_msix_vectors_vf needs to minus irq0 */
1637 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1638 vsi->user_param + (msix_vect - 1);
1640 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1642 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1644 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1648 I40E_WRITE_FLUSH(hw);
1652 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1654 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1655 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1656 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1657 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1658 uint16_t msix_vect = vsi->msix_intr;
1659 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1660 uint16_t queue_idx = 0;
1665 for (i = 0; i < vsi->nb_qps; i++) {
1666 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1667 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1670 /* INTENA flag is not auto-cleared for interrupt */
1671 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1672 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1673 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1674 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1675 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1677 /* VF bind interrupt */
1678 if (vsi->type == I40E_VSI_SRIOV) {
1679 __vsi_queues_bind_intr(vsi, msix_vect,
1680 vsi->base_queue, vsi->nb_qps);
1684 /* PF & VMDq bind interrupt */
1685 if (rte_intr_dp_is_en(intr_handle)) {
1686 if (vsi->type == I40E_VSI_MAIN) {
1689 } else if (vsi->type == I40E_VSI_VMDQ2) {
1690 struct i40e_vsi *main_vsi =
1691 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1692 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1697 for (i = 0; i < vsi->nb_used_qps; i++) {
1699 if (!rte_intr_allow_others(intr_handle))
1700 /* allow to share MISC_VEC_ID */
1701 msix_vect = I40E_MISC_VEC_ID;
1703 /* no enough msix_vect, map all to one */
1704 __vsi_queues_bind_intr(vsi, msix_vect,
1705 vsi->base_queue + i,
1706 vsi->nb_used_qps - i);
1707 for (; !!record && i < vsi->nb_used_qps; i++)
1708 intr_handle->intr_vec[queue_idx + i] =
1712 /* 1:1 queue/msix_vect mapping */
1713 __vsi_queues_bind_intr(vsi, msix_vect,
1714 vsi->base_queue + i, 1);
1716 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1724 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1726 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1727 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1728 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1729 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1730 uint16_t interval = i40e_calc_itr_interval(\
1731 RTE_LIBRTE_I40E_ITR_INTERVAL);
1732 uint16_t msix_intr, i;
1734 if (rte_intr_allow_others(intr_handle))
1735 for (i = 0; i < vsi->nb_msix; i++) {
1736 msix_intr = vsi->msix_intr + i;
1737 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1738 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1739 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1740 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1742 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1745 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1746 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1747 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1748 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1750 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1752 I40E_WRITE_FLUSH(hw);
1756 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1758 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1759 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1760 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1761 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1762 uint16_t msix_intr, i;
1764 if (rte_intr_allow_others(intr_handle))
1765 for (i = 0; i < vsi->nb_msix; i++) {
1766 msix_intr = vsi->msix_intr + i;
1767 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1771 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1773 I40E_WRITE_FLUSH(hw);
1776 static inline uint8_t
1777 i40e_parse_link_speeds(uint16_t link_speeds)
1779 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1781 if (link_speeds & ETH_LINK_SPEED_40G)
1782 link_speed |= I40E_LINK_SPEED_40GB;
1783 if (link_speeds & ETH_LINK_SPEED_25G)
1784 link_speed |= I40E_LINK_SPEED_25GB;
1785 if (link_speeds & ETH_LINK_SPEED_20G)
1786 link_speed |= I40E_LINK_SPEED_20GB;
1787 if (link_speeds & ETH_LINK_SPEED_10G)
1788 link_speed |= I40E_LINK_SPEED_10GB;
1789 if (link_speeds & ETH_LINK_SPEED_1G)
1790 link_speed |= I40E_LINK_SPEED_1GB;
1791 if (link_speeds & ETH_LINK_SPEED_100M)
1792 link_speed |= I40E_LINK_SPEED_100MB;
1798 i40e_phy_conf_link(struct i40e_hw *hw,
1800 uint8_t force_speed)
1802 enum i40e_status_code status;
1803 struct i40e_aq_get_phy_abilities_resp phy_ab;
1804 struct i40e_aq_set_phy_config phy_conf;
1805 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1806 I40E_AQ_PHY_FLAG_PAUSE_RX |
1807 I40E_AQ_PHY_FLAG_PAUSE_RX |
1808 I40E_AQ_PHY_FLAG_LOW_POWER;
1809 const uint8_t advt = I40E_LINK_SPEED_40GB |
1810 I40E_LINK_SPEED_25GB |
1811 I40E_LINK_SPEED_10GB |
1812 I40E_LINK_SPEED_1GB |
1813 I40E_LINK_SPEED_100MB;
1817 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1822 memset(&phy_conf, 0, sizeof(phy_conf));
1824 /* bits 0-2 use the values from get_phy_abilities_resp */
1826 abilities |= phy_ab.abilities & mask;
1828 /* update ablities and speed */
1829 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1830 phy_conf.link_speed = advt;
1832 phy_conf.link_speed = force_speed;
1834 phy_conf.abilities = abilities;
1836 /* use get_phy_abilities_resp value for the rest */
1837 phy_conf.phy_type = phy_ab.phy_type;
1838 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1839 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1840 phy_conf.eee_capability = phy_ab.eee_capability;
1841 phy_conf.eeer = phy_ab.eeer_val;
1842 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1844 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1845 phy_ab.abilities, phy_ab.link_speed);
1846 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1847 phy_conf.abilities, phy_conf.link_speed);
1849 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1853 return I40E_SUCCESS;
1857 i40e_apply_link_speed(struct rte_eth_dev *dev)
1860 uint8_t abilities = 0;
1861 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 struct rte_eth_conf *conf = &dev->data->dev_conf;
1864 speed = i40e_parse_link_speeds(conf->link_speeds);
1865 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1866 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1867 abilities |= I40E_AQ_PHY_AN_ENABLED;
1868 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1870 /* Skip changing speed on 40G interfaces, FW does not support */
1871 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1872 speed = I40E_LINK_SPEED_UNKNOWN;
1873 abilities |= I40E_AQ_PHY_AN_ENABLED;
1876 return i40e_phy_conf_link(hw, abilities, speed);
1880 i40e_dev_start(struct rte_eth_dev *dev)
1882 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884 struct i40e_vsi *main_vsi = pf->main_vsi;
1886 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1887 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1888 uint32_t intr_vector = 0;
1889 struct i40e_vsi *vsi;
1891 hw->adapter_stopped = 0;
1893 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1894 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1895 dev->data->port_id);
1899 rte_intr_disable(intr_handle);
1901 if ((rte_intr_cap_multiple(intr_handle) ||
1902 !RTE_ETH_DEV_SRIOV(dev).active) &&
1903 dev->data->dev_conf.intr_conf.rxq != 0) {
1904 intr_vector = dev->data->nb_rx_queues;
1905 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1910 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1911 intr_handle->intr_vec =
1912 rte_zmalloc("intr_vec",
1913 dev->data->nb_rx_queues * sizeof(int),
1915 if (!intr_handle->intr_vec) {
1917 "Failed to allocate %d rx_queues intr_vec",
1918 dev->data->nb_rx_queues);
1923 /* Initialize VSI */
1924 ret = i40e_dev_rxtx_init(pf);
1925 if (ret != I40E_SUCCESS) {
1926 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1930 /* Map queues with MSIX interrupt */
1931 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1932 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1933 i40e_vsi_queues_bind_intr(main_vsi);
1934 i40e_vsi_enable_queues_intr(main_vsi);
1936 /* Map VMDQ VSI queues with MSIX interrupt */
1937 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1938 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1939 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1940 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1943 /* enable FDIR MSIX interrupt */
1944 if (pf->fdir.fdir_vsi) {
1945 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1946 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1949 /* Enable all queues which have been configured */
1950 ret = i40e_dev_switch_queues(pf, TRUE);
1951 if (ret != I40E_SUCCESS) {
1952 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1956 /* Enable receiving broadcast packets */
1957 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1958 if (ret != I40E_SUCCESS)
1959 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1961 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1962 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1964 if (ret != I40E_SUCCESS)
1965 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1968 /* Enable the VLAN promiscuous mode. */
1970 for (i = 0; i < pf->vf_num; i++) {
1971 vsi = pf->vfs[i].vsi;
1972 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1977 /* Apply link configure */
1978 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1979 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1980 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1981 ETH_LINK_SPEED_40G)) {
1982 PMD_DRV_LOG(ERR, "Invalid link setting");
1985 ret = i40e_apply_link_speed(dev);
1986 if (I40E_SUCCESS != ret) {
1987 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1991 if (!rte_intr_allow_others(intr_handle)) {
1992 rte_intr_callback_unregister(intr_handle,
1993 i40e_dev_interrupt_handler,
1995 /* configure and enable device interrupt */
1996 i40e_pf_config_irq0(hw, FALSE);
1997 i40e_pf_enable_irq0(hw);
1999 if (dev->data->dev_conf.intr_conf.lsc != 0)
2001 "lsc won't enable because of no intr multiplex");
2002 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2003 ret = i40e_aq_set_phy_int_mask(hw,
2004 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2005 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2006 I40E_AQ_EVENT_MEDIA_NA), NULL);
2007 if (ret != I40E_SUCCESS)
2008 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2010 /* Call get_link_info aq commond to enable LSE */
2011 i40e_dev_link_update(dev, 0);
2014 /* enable uio intr after callback register */
2015 rte_intr_enable(intr_handle);
2017 i40e_filter_restore(pf);
2019 return I40E_SUCCESS;
2022 i40e_dev_switch_queues(pf, FALSE);
2023 i40e_dev_clear_queues(dev);
2029 i40e_dev_stop(struct rte_eth_dev *dev)
2031 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2032 struct i40e_vsi *main_vsi = pf->main_vsi;
2033 struct i40e_mirror_rule *p_mirror;
2034 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2035 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2038 /* Disable all queues */
2039 i40e_dev_switch_queues(pf, FALSE);
2041 /* un-map queues with interrupt registers */
2042 i40e_vsi_disable_queues_intr(main_vsi);
2043 i40e_vsi_queues_unbind_intr(main_vsi);
2045 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2046 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2047 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2050 if (pf->fdir.fdir_vsi) {
2051 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2052 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2054 /* Clear all queues and release memory */
2055 i40e_dev_clear_queues(dev);
2058 i40e_dev_set_link_down(dev);
2060 /* Remove all mirror rules */
2061 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2062 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2065 pf->nb_mirror_rule = 0;
2067 if (!rte_intr_allow_others(intr_handle))
2068 /* resume to the default handler */
2069 rte_intr_callback_register(intr_handle,
2070 i40e_dev_interrupt_handler,
2073 /* Clean datapath event and queue/vec mapping */
2074 rte_intr_efd_disable(intr_handle);
2075 if (intr_handle->intr_vec) {
2076 rte_free(intr_handle->intr_vec);
2077 intr_handle->intr_vec = NULL;
2082 i40e_dev_close(struct rte_eth_dev *dev)
2084 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2085 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2087 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2091 PMD_INIT_FUNC_TRACE();
2094 hw->adapter_stopped = 1;
2095 i40e_dev_free_queues(dev);
2097 /* Disable interrupt */
2098 i40e_pf_disable_irq0(hw);
2099 rte_intr_disable(intr_handle);
2101 /* shutdown and destroy the HMC */
2102 i40e_shutdown_lan_hmc(hw);
2104 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2105 i40e_vsi_release(pf->vmdq[i].vsi);
2106 pf->vmdq[i].vsi = NULL;
2111 /* release all the existing VSIs and VEBs */
2112 i40e_fdir_teardown(pf);
2113 i40e_vsi_release(pf->main_vsi);
2115 /* shutdown the adminq */
2116 i40e_aq_queue_shutdown(hw, true);
2117 i40e_shutdown_adminq(hw);
2119 i40e_res_pool_destroy(&pf->qp_pool);
2120 i40e_res_pool_destroy(&pf->msix_pool);
2122 /* force a PF reset to clean anything leftover */
2123 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2124 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2125 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2126 I40E_WRITE_FLUSH(hw);
2130 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 struct i40e_vsi *vsi = pf->main_vsi;
2137 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2139 if (status != I40E_SUCCESS)
2140 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2142 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2144 if (status != I40E_SUCCESS)
2145 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2150 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2152 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154 struct i40e_vsi *vsi = pf->main_vsi;
2157 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2159 if (status != I40E_SUCCESS)
2160 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2162 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2164 if (status != I40E_SUCCESS)
2165 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2169 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2171 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2172 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173 struct i40e_vsi *vsi = pf->main_vsi;
2176 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2177 if (ret != I40E_SUCCESS)
2178 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2182 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2184 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2185 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186 struct i40e_vsi *vsi = pf->main_vsi;
2189 if (dev->data->promiscuous == 1)
2190 return; /* must remain in all_multicast mode */
2192 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2193 vsi->seid, FALSE, NULL);
2194 if (ret != I40E_SUCCESS)
2195 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2199 * Set device link up.
2202 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2204 /* re-apply link speed setting */
2205 return i40e_apply_link_speed(dev);
2209 * Set device link down.
2212 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2214 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2215 uint8_t abilities = 0;
2216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2218 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2219 return i40e_phy_conf_link(hw, abilities, speed);
2223 i40e_dev_link_update(struct rte_eth_dev *dev,
2224 int wait_to_complete)
2226 #define CHECK_INTERVAL 100 /* 100ms */
2227 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2229 struct i40e_link_status link_status;
2230 struct rte_eth_link link, old;
2232 unsigned rep_cnt = MAX_REPEAT_TIME;
2233 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2235 memset(&link, 0, sizeof(link));
2236 memset(&old, 0, sizeof(old));
2237 memset(&link_status, 0, sizeof(link_status));
2238 rte_i40e_dev_atomic_read_link_status(dev, &old);
2241 /* Get link status information from hardware */
2242 status = i40e_aq_get_link_info(hw, enable_lse,
2243 &link_status, NULL);
2244 if (status != I40E_SUCCESS) {
2245 link.link_speed = ETH_SPEED_NUM_100M;
2246 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2247 PMD_DRV_LOG(ERR, "Failed to get link info");
2251 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2252 if (!wait_to_complete || link.link_status)
2255 rte_delay_ms(CHECK_INTERVAL);
2256 } while (--rep_cnt);
2258 if (!link.link_status)
2261 /* i40e uses full duplex only */
2262 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2264 /* Parse the link status */
2265 switch (link_status.link_speed) {
2266 case I40E_LINK_SPEED_100MB:
2267 link.link_speed = ETH_SPEED_NUM_100M;
2269 case I40E_LINK_SPEED_1GB:
2270 link.link_speed = ETH_SPEED_NUM_1G;
2272 case I40E_LINK_SPEED_10GB:
2273 link.link_speed = ETH_SPEED_NUM_10G;
2275 case I40E_LINK_SPEED_20GB:
2276 link.link_speed = ETH_SPEED_NUM_20G;
2278 case I40E_LINK_SPEED_25GB:
2279 link.link_speed = ETH_SPEED_NUM_25G;
2281 case I40E_LINK_SPEED_40GB:
2282 link.link_speed = ETH_SPEED_NUM_40G;
2285 link.link_speed = ETH_SPEED_NUM_100M;
2289 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2290 ETH_LINK_SPEED_FIXED);
2293 rte_i40e_dev_atomic_write_link_status(dev, &link);
2294 if (link.link_status == old.link_status)
2300 /* Get all the statistics of a VSI */
2302 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2304 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2305 struct i40e_eth_stats *nes = &vsi->eth_stats;
2306 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2307 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2309 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2310 vsi->offset_loaded, &oes->rx_bytes,
2312 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2313 vsi->offset_loaded, &oes->rx_unicast,
2315 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2316 vsi->offset_loaded, &oes->rx_multicast,
2317 &nes->rx_multicast);
2318 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2319 vsi->offset_loaded, &oes->rx_broadcast,
2320 &nes->rx_broadcast);
2321 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2322 &oes->rx_discards, &nes->rx_discards);
2323 /* GLV_REPC not supported */
2324 /* GLV_RMPC not supported */
2325 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2326 &oes->rx_unknown_protocol,
2327 &nes->rx_unknown_protocol);
2328 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2329 vsi->offset_loaded, &oes->tx_bytes,
2331 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2332 vsi->offset_loaded, &oes->tx_unicast,
2334 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2335 vsi->offset_loaded, &oes->tx_multicast,
2336 &nes->tx_multicast);
2337 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2338 vsi->offset_loaded, &oes->tx_broadcast,
2339 &nes->tx_broadcast);
2340 /* GLV_TDPC not supported */
2341 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2342 &oes->tx_errors, &nes->tx_errors);
2343 vsi->offset_loaded = true;
2345 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2347 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2348 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2349 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2350 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2351 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2352 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2353 nes->rx_unknown_protocol);
2354 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2355 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2356 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2357 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2358 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2359 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2360 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2365 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2368 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2369 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2371 /* Get statistics of struct i40e_eth_stats */
2372 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2373 I40E_GLPRT_GORCL(hw->port),
2374 pf->offset_loaded, &os->eth.rx_bytes,
2376 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2377 I40E_GLPRT_UPRCL(hw->port),
2378 pf->offset_loaded, &os->eth.rx_unicast,
2379 &ns->eth.rx_unicast);
2380 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2381 I40E_GLPRT_MPRCL(hw->port),
2382 pf->offset_loaded, &os->eth.rx_multicast,
2383 &ns->eth.rx_multicast);
2384 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2385 I40E_GLPRT_BPRCL(hw->port),
2386 pf->offset_loaded, &os->eth.rx_broadcast,
2387 &ns->eth.rx_broadcast);
2388 /* Workaround: CRC size should not be included in byte statistics,
2389 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2391 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2392 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2394 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2395 pf->offset_loaded, &os->eth.rx_discards,
2396 &ns->eth.rx_discards);
2397 /* GLPRT_REPC not supported */
2398 /* GLPRT_RMPC not supported */
2399 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2401 &os->eth.rx_unknown_protocol,
2402 &ns->eth.rx_unknown_protocol);
2403 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2404 I40E_GLPRT_GOTCL(hw->port),
2405 pf->offset_loaded, &os->eth.tx_bytes,
2407 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2408 I40E_GLPRT_UPTCL(hw->port),
2409 pf->offset_loaded, &os->eth.tx_unicast,
2410 &ns->eth.tx_unicast);
2411 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2412 I40E_GLPRT_MPTCL(hw->port),
2413 pf->offset_loaded, &os->eth.tx_multicast,
2414 &ns->eth.tx_multicast);
2415 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2416 I40E_GLPRT_BPTCL(hw->port),
2417 pf->offset_loaded, &os->eth.tx_broadcast,
2418 &ns->eth.tx_broadcast);
2419 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2420 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2421 /* GLPRT_TEPC not supported */
2423 /* additional port specific stats */
2424 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2425 pf->offset_loaded, &os->tx_dropped_link_down,
2426 &ns->tx_dropped_link_down);
2427 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2428 pf->offset_loaded, &os->crc_errors,
2430 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2431 pf->offset_loaded, &os->illegal_bytes,
2432 &ns->illegal_bytes);
2433 /* GLPRT_ERRBC not supported */
2434 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2435 pf->offset_loaded, &os->mac_local_faults,
2436 &ns->mac_local_faults);
2437 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2438 pf->offset_loaded, &os->mac_remote_faults,
2439 &ns->mac_remote_faults);
2440 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2441 pf->offset_loaded, &os->rx_length_errors,
2442 &ns->rx_length_errors);
2443 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2444 pf->offset_loaded, &os->link_xon_rx,
2446 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2447 pf->offset_loaded, &os->link_xoff_rx,
2449 for (i = 0; i < 8; i++) {
2450 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2452 &os->priority_xon_rx[i],
2453 &ns->priority_xon_rx[i]);
2454 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2456 &os->priority_xoff_rx[i],
2457 &ns->priority_xoff_rx[i]);
2459 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2460 pf->offset_loaded, &os->link_xon_tx,
2462 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2463 pf->offset_loaded, &os->link_xoff_tx,
2465 for (i = 0; i < 8; i++) {
2466 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2468 &os->priority_xon_tx[i],
2469 &ns->priority_xon_tx[i]);
2470 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2472 &os->priority_xoff_tx[i],
2473 &ns->priority_xoff_tx[i]);
2474 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2476 &os->priority_xon_2_xoff[i],
2477 &ns->priority_xon_2_xoff[i]);
2479 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2480 I40E_GLPRT_PRC64L(hw->port),
2481 pf->offset_loaded, &os->rx_size_64,
2483 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2484 I40E_GLPRT_PRC127L(hw->port),
2485 pf->offset_loaded, &os->rx_size_127,
2487 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2488 I40E_GLPRT_PRC255L(hw->port),
2489 pf->offset_loaded, &os->rx_size_255,
2491 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2492 I40E_GLPRT_PRC511L(hw->port),
2493 pf->offset_loaded, &os->rx_size_511,
2495 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2496 I40E_GLPRT_PRC1023L(hw->port),
2497 pf->offset_loaded, &os->rx_size_1023,
2499 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2500 I40E_GLPRT_PRC1522L(hw->port),
2501 pf->offset_loaded, &os->rx_size_1522,
2503 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2504 I40E_GLPRT_PRC9522L(hw->port),
2505 pf->offset_loaded, &os->rx_size_big,
2507 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2508 pf->offset_loaded, &os->rx_undersize,
2510 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2511 pf->offset_loaded, &os->rx_fragments,
2513 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2514 pf->offset_loaded, &os->rx_oversize,
2516 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2517 pf->offset_loaded, &os->rx_jabber,
2519 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2520 I40E_GLPRT_PTC64L(hw->port),
2521 pf->offset_loaded, &os->tx_size_64,
2523 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2524 I40E_GLPRT_PTC127L(hw->port),
2525 pf->offset_loaded, &os->tx_size_127,
2527 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2528 I40E_GLPRT_PTC255L(hw->port),
2529 pf->offset_loaded, &os->tx_size_255,
2531 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2532 I40E_GLPRT_PTC511L(hw->port),
2533 pf->offset_loaded, &os->tx_size_511,
2535 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2536 I40E_GLPRT_PTC1023L(hw->port),
2537 pf->offset_loaded, &os->tx_size_1023,
2539 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2540 I40E_GLPRT_PTC1522L(hw->port),
2541 pf->offset_loaded, &os->tx_size_1522,
2543 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2544 I40E_GLPRT_PTC9522L(hw->port),
2545 pf->offset_loaded, &os->tx_size_big,
2547 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2549 &os->fd_sb_match, &ns->fd_sb_match);
2550 /* GLPRT_MSPDC not supported */
2551 /* GLPRT_XEC not supported */
2553 pf->offset_loaded = true;
2556 i40e_update_vsi_stats(pf->main_vsi);
2559 /* Get all statistics of a port */
2561 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2563 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2564 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2568 /* call read registers - updates values, now write them to struct */
2569 i40e_read_stats_registers(pf, hw);
2571 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2572 pf->main_vsi->eth_stats.rx_multicast +
2573 pf->main_vsi->eth_stats.rx_broadcast -
2574 pf->main_vsi->eth_stats.rx_discards;
2575 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2576 pf->main_vsi->eth_stats.tx_multicast +
2577 pf->main_vsi->eth_stats.tx_broadcast;
2578 stats->ibytes = ns->eth.rx_bytes;
2579 stats->obytes = ns->eth.tx_bytes;
2580 stats->oerrors = ns->eth.tx_errors +
2581 pf->main_vsi->eth_stats.tx_errors;
2584 stats->imissed = ns->eth.rx_discards +
2585 pf->main_vsi->eth_stats.rx_discards;
2586 stats->ierrors = ns->crc_errors +
2587 ns->rx_length_errors + ns->rx_undersize +
2588 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2590 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2591 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2592 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2593 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2594 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2595 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2596 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2597 ns->eth.rx_unknown_protocol);
2598 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2599 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2600 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2601 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2602 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2603 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2605 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2606 ns->tx_dropped_link_down);
2607 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2608 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2610 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2611 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2612 ns->mac_local_faults);
2613 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2614 ns->mac_remote_faults);
2615 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2616 ns->rx_length_errors);
2617 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2618 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2619 for (i = 0; i < 8; i++) {
2620 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2621 i, ns->priority_xon_rx[i]);
2622 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2623 i, ns->priority_xoff_rx[i]);
2625 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2626 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2627 for (i = 0; i < 8; i++) {
2628 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2629 i, ns->priority_xon_tx[i]);
2630 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2631 i, ns->priority_xoff_tx[i]);
2632 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2633 i, ns->priority_xon_2_xoff[i]);
2635 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2636 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2637 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2638 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2639 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2640 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2641 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2642 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2643 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2644 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2645 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2646 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2647 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2648 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2649 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2650 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2651 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2652 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2653 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2654 ns->mac_short_packet_dropped);
2655 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2656 ns->checksum_error);
2657 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2658 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2661 /* Reset the statistics */
2663 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 /* Mark PF and VSI stats to update the offset, aka "reset" */
2669 pf->offset_loaded = false;
2671 pf->main_vsi->offset_loaded = false;
2673 /* read the stats, reading current register values into offset */
2674 i40e_read_stats_registers(pf, hw);
2678 i40e_xstats_calc_num(void)
2680 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2681 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2682 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2685 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2686 struct rte_eth_xstat_name *xstats_names,
2687 __rte_unused unsigned limit)
2692 if (xstats_names == NULL)
2693 return i40e_xstats_calc_num();
2695 /* Note: limit checked in rte_eth_xstats_names() */
2697 /* Get stats from i40e_eth_stats struct */
2698 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2699 snprintf(xstats_names[count].name,
2700 sizeof(xstats_names[count].name),
2701 "%s", rte_i40e_stats_strings[i].name);
2705 /* Get individiual stats from i40e_hw_port struct */
2706 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2707 snprintf(xstats_names[count].name,
2708 sizeof(xstats_names[count].name),
2709 "%s", rte_i40e_hw_port_strings[i].name);
2713 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2714 for (prio = 0; prio < 8; prio++) {
2715 snprintf(xstats_names[count].name,
2716 sizeof(xstats_names[count].name),
2717 "rx_priority%u_%s", prio,
2718 rte_i40e_rxq_prio_strings[i].name);
2723 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2724 for (prio = 0; prio < 8; prio++) {
2725 snprintf(xstats_names[count].name,
2726 sizeof(xstats_names[count].name),
2727 "tx_priority%u_%s", prio,
2728 rte_i40e_txq_prio_strings[i].name);
2736 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2739 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2740 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2741 unsigned i, count, prio;
2742 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2744 count = i40e_xstats_calc_num();
2748 i40e_read_stats_registers(pf, hw);
2755 /* Get stats from i40e_eth_stats struct */
2756 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2757 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2758 rte_i40e_stats_strings[i].offset);
2759 xstats[count].id = count;
2763 /* Get individiual stats from i40e_hw_port struct */
2764 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2765 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2766 rte_i40e_hw_port_strings[i].offset);
2767 xstats[count].id = count;
2771 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2772 for (prio = 0; prio < 8; prio++) {
2773 xstats[count].value =
2774 *(uint64_t *)(((char *)hw_stats) +
2775 rte_i40e_rxq_prio_strings[i].offset +
2776 (sizeof(uint64_t) * prio));
2777 xstats[count].id = count;
2782 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2783 for (prio = 0; prio < 8; prio++) {
2784 xstats[count].value =
2785 *(uint64_t *)(((char *)hw_stats) +
2786 rte_i40e_txq_prio_strings[i].offset +
2787 (sizeof(uint64_t) * prio));
2788 xstats[count].id = count;
2797 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2798 __rte_unused uint16_t queue_id,
2799 __rte_unused uint8_t stat_idx,
2800 __rte_unused uint8_t is_rx)
2802 PMD_INIT_FUNC_TRACE();
2808 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816 full_ver = hw->nvm.oem_ver;
2817 ver = (u8)(full_ver >> 24);
2818 build = (u16)((full_ver >> 8) & 0xffff);
2819 patch = (u8)(full_ver & 0xff);
2821 ret = snprintf(fw_version, fw_size,
2822 "%d.%d%d 0x%08x %d.%d.%d",
2823 ((hw->nvm.version >> 12) & 0xf),
2824 ((hw->nvm.version >> 4) & 0xff),
2825 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2828 ret += 1; /* add the size of '\0' */
2829 if (fw_size < (u32)ret)
2836 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2838 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840 struct i40e_vsi *vsi = pf->main_vsi;
2841 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2843 dev_info->pci_dev = pci_dev;
2844 dev_info->max_rx_queues = vsi->nb_qps;
2845 dev_info->max_tx_queues = vsi->nb_qps;
2846 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2847 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2848 dev_info->max_mac_addrs = vsi->max_macaddrs;
2849 dev_info->max_vfs = pci_dev->max_vfs;
2850 dev_info->rx_offload_capa =
2851 DEV_RX_OFFLOAD_VLAN_STRIP |
2852 DEV_RX_OFFLOAD_QINQ_STRIP |
2853 DEV_RX_OFFLOAD_IPV4_CKSUM |
2854 DEV_RX_OFFLOAD_UDP_CKSUM |
2855 DEV_RX_OFFLOAD_TCP_CKSUM;
2856 dev_info->tx_offload_capa =
2857 DEV_TX_OFFLOAD_VLAN_INSERT |
2858 DEV_TX_OFFLOAD_QINQ_INSERT |
2859 DEV_TX_OFFLOAD_IPV4_CKSUM |
2860 DEV_TX_OFFLOAD_UDP_CKSUM |
2861 DEV_TX_OFFLOAD_TCP_CKSUM |
2862 DEV_TX_OFFLOAD_SCTP_CKSUM |
2863 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2864 DEV_TX_OFFLOAD_TCP_TSO |
2865 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2866 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2867 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2868 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2869 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2871 dev_info->reta_size = pf->hash_lut_size;
2872 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2874 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2876 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2877 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2878 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2880 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2884 dev_info->default_txconf = (struct rte_eth_txconf) {
2886 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2887 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2888 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2890 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2891 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2892 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2893 ETH_TXQ_FLAGS_NOOFFLOADS,
2896 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2897 .nb_max = I40E_MAX_RING_DESC,
2898 .nb_min = I40E_MIN_RING_DESC,
2899 .nb_align = I40E_ALIGN_RING_DESC,
2902 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2903 .nb_max = I40E_MAX_RING_DESC,
2904 .nb_min = I40E_MIN_RING_DESC,
2905 .nb_align = I40E_ALIGN_RING_DESC,
2906 .nb_seg_max = I40E_TX_MAX_SEG,
2907 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2910 if (pf->flags & I40E_FLAG_VMDQ) {
2911 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2912 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2913 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2914 pf->max_nb_vmdq_vsi;
2915 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2916 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2917 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2920 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2922 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2923 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2925 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2928 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2932 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2935 struct i40e_vsi *vsi = pf->main_vsi;
2936 PMD_INIT_FUNC_TRACE();
2939 return i40e_vsi_add_vlan(vsi, vlan_id);
2941 return i40e_vsi_delete_vlan(vsi, vlan_id);
2945 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2946 enum rte_vlan_type vlan_type,
2949 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950 uint64_t reg_r = 0, reg_w = 0;
2951 uint16_t reg_id = 0;
2953 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2955 switch (vlan_type) {
2956 case ETH_VLAN_TYPE_OUTER:
2962 case ETH_VLAN_TYPE_INNER:
2968 "Unsupported vlan type in single vlan.");
2974 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2977 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2979 if (ret != I40E_SUCCESS) {
2981 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2987 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2990 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2991 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2992 if (reg_r == reg_w) {
2994 PMD_DRV_LOG(DEBUG, "No need to write");
2998 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3000 if (ret != I40E_SUCCESS) {
3003 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3008 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3015 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3018 struct i40e_vsi *vsi = pf->main_vsi;
3020 if (mask & ETH_VLAN_FILTER_MASK) {
3021 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3022 i40e_vsi_config_vlan_filter(vsi, TRUE);
3024 i40e_vsi_config_vlan_filter(vsi, FALSE);
3027 if (mask & ETH_VLAN_STRIP_MASK) {
3028 /* Enable or disable VLAN stripping */
3029 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3030 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3032 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3035 if (mask & ETH_VLAN_EXTEND_MASK) {
3036 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3037 i40e_vsi_config_double_vlan(vsi, TRUE);
3038 /* Set global registers with default ether type value */
3039 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3041 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3045 i40e_vsi_config_double_vlan(vsi, FALSE);
3050 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3051 __rte_unused uint16_t queue,
3052 __rte_unused int on)
3054 PMD_INIT_FUNC_TRACE();
3058 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3060 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3061 struct i40e_vsi *vsi = pf->main_vsi;
3062 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3063 struct i40e_vsi_vlan_pvid_info info;
3065 memset(&info, 0, sizeof(info));
3068 info.config.pvid = pvid;
3070 info.config.reject.tagged =
3071 data->dev_conf.txmode.hw_vlan_reject_tagged;
3072 info.config.reject.untagged =
3073 data->dev_conf.txmode.hw_vlan_reject_untagged;
3076 return i40e_vsi_vlan_pvid_set(vsi, &info);
3080 i40e_dev_led_on(struct rte_eth_dev *dev)
3082 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3083 uint32_t mode = i40e_led_get(hw);
3086 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3092 i40e_dev_led_off(struct rte_eth_dev *dev)
3094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095 uint32_t mode = i40e_led_get(hw);
3098 i40e_led_set(hw, 0, false);
3104 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3109 fc_conf->pause_time = pf->fc_conf.pause_time;
3110 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3111 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3113 /* Return current mode according to actual setting*/
3114 switch (hw->fc.current_mode) {
3116 fc_conf->mode = RTE_FC_FULL;
3118 case I40E_FC_TX_PAUSE:
3119 fc_conf->mode = RTE_FC_TX_PAUSE;
3121 case I40E_FC_RX_PAUSE:
3122 fc_conf->mode = RTE_FC_RX_PAUSE;
3126 fc_conf->mode = RTE_FC_NONE;
3133 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3135 uint32_t mflcn_reg, fctrl_reg, reg;
3136 uint32_t max_high_water;
3137 uint8_t i, aq_failure;
3141 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3142 [RTE_FC_NONE] = I40E_FC_NONE,
3143 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3144 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3145 [RTE_FC_FULL] = I40E_FC_FULL
3148 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3150 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3151 if ((fc_conf->high_water > max_high_water) ||
3152 (fc_conf->high_water < fc_conf->low_water)) {
3154 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3159 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3161 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3163 pf->fc_conf.pause_time = fc_conf->pause_time;
3164 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3165 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3167 PMD_INIT_FUNC_TRACE();
3169 /* All the link flow control related enable/disable register
3170 * configuration is handle by the F/W
3172 err = i40e_set_fc(hw, &aq_failure, true);
3176 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3177 /* Configure flow control refresh threshold,
3178 * the value for stat_tx_pause_refresh_timer[8]
3179 * is used for global pause operation.
3183 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3184 pf->fc_conf.pause_time);
3186 /* configure the timer value included in transmitted pause
3188 * the value for stat_tx_pause_quanta[8] is used for global
3191 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3192 pf->fc_conf.pause_time);
3194 fctrl_reg = I40E_READ_REG(hw,
3195 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3197 if (fc_conf->mac_ctrl_frame_fwd != 0)
3198 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3200 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3202 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3205 /* Configure pause time (2 TCs per register) */
3206 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3207 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3208 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3210 /* Configure flow control refresh threshold value */
3211 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3212 pf->fc_conf.pause_time / 2);
3214 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3216 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3217 *depending on configuration
3219 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3220 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3221 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3223 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3224 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3227 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3230 /* config the water marker both based on the packets and bytes */
3231 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3232 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3233 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3234 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3235 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3236 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3237 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3238 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3240 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3241 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3244 I40E_WRITE_FLUSH(hw);
3250 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3251 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3253 PMD_INIT_FUNC_TRACE();
3258 /* Add a MAC address, and update filters */
3260 i40e_macaddr_add(struct rte_eth_dev *dev,
3261 struct ether_addr *mac_addr,
3262 __rte_unused uint32_t index,
3265 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3266 struct i40e_mac_filter_info mac_filter;
3267 struct i40e_vsi *vsi;
3270 /* If VMDQ not enabled or configured, return */
3271 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3272 !pf->nb_cfg_vmdq_vsi)) {
3273 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3274 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3279 if (pool > pf->nb_cfg_vmdq_vsi) {
3280 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3281 pool, pf->nb_cfg_vmdq_vsi);
3285 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3286 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3287 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3289 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3294 vsi = pf->vmdq[pool - 1].vsi;
3296 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3297 if (ret != I40E_SUCCESS) {
3298 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3303 /* Remove a MAC address, and update filters */
3305 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3307 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308 struct i40e_vsi *vsi;
3309 struct rte_eth_dev_data *data = dev->data;
3310 struct ether_addr *macaddr;
3315 macaddr = &(data->mac_addrs[index]);
3317 pool_sel = dev->data->mac_pool_sel[index];
3319 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3320 if (pool_sel & (1ULL << i)) {
3324 /* No VMDQ pool enabled or configured */
3325 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3326 (i > pf->nb_cfg_vmdq_vsi)) {
3328 "No VMDQ pool enabled/configured");
3331 vsi = pf->vmdq[i - 1].vsi;
3333 ret = i40e_vsi_delete_mac(vsi, macaddr);
3336 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3343 /* Set perfect match or hash match of MAC and VLAN for a VF */
3345 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3346 struct rte_eth_mac_filter *filter,
3350 struct i40e_mac_filter_info mac_filter;
3351 struct ether_addr old_mac;
3352 struct ether_addr *new_mac;
3353 struct i40e_pf_vf *vf = NULL;
3358 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3361 hw = I40E_PF_TO_HW(pf);
3363 if (filter == NULL) {
3364 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3368 new_mac = &filter->mac_addr;
3370 if (is_zero_ether_addr(new_mac)) {
3371 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3375 vf_id = filter->dst_id;
3377 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3378 PMD_DRV_LOG(ERR, "Invalid argument.");
3381 vf = &pf->vfs[vf_id];
3383 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3384 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3389 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3390 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3392 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3395 mac_filter.filter_type = filter->filter_type;
3396 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3397 if (ret != I40E_SUCCESS) {
3398 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3401 ether_addr_copy(new_mac, &pf->dev_addr);
3403 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3405 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3406 if (ret != I40E_SUCCESS) {
3407 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3411 /* Clear device address as it has been removed */
3412 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3413 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3419 /* MAC filter handle */
3421 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3424 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3425 struct rte_eth_mac_filter *filter;
3426 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3427 int ret = I40E_NOT_SUPPORTED;
3429 filter = (struct rte_eth_mac_filter *)(arg);
3431 switch (filter_op) {
3432 case RTE_ETH_FILTER_NOP:
3435 case RTE_ETH_FILTER_ADD:
3436 i40e_pf_disable_irq0(hw);
3438 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3439 i40e_pf_enable_irq0(hw);
3441 case RTE_ETH_FILTER_DELETE:
3442 i40e_pf_disable_irq0(hw);
3444 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3445 i40e_pf_enable_irq0(hw);
3448 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3449 ret = I40E_ERR_PARAM;
3457 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3459 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3460 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3466 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3467 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3470 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3474 uint32_t *lut_dw = (uint32_t *)lut;
3475 uint16_t i, lut_size_dw = lut_size / 4;
3477 for (i = 0; i < lut_size_dw; i++)
3478 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3485 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3494 pf = I40E_VSI_TO_PF(vsi);
3495 hw = I40E_VSI_TO_HW(vsi);
3497 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3498 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3501 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3505 uint32_t *lut_dw = (uint32_t *)lut;
3506 uint16_t i, lut_size_dw = lut_size / 4;
3508 for (i = 0; i < lut_size_dw; i++)
3509 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3510 I40E_WRITE_FLUSH(hw);
3517 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3518 struct rte_eth_rss_reta_entry64 *reta_conf,
3521 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3522 uint16_t i, lut_size = pf->hash_lut_size;
3523 uint16_t idx, shift;
3527 if (reta_size != lut_size ||
3528 reta_size > ETH_RSS_RETA_SIZE_512) {
3530 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3531 reta_size, lut_size);
3535 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3537 PMD_DRV_LOG(ERR, "No memory can be allocated");
3540 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3543 for (i = 0; i < reta_size; i++) {
3544 idx = i / RTE_RETA_GROUP_SIZE;
3545 shift = i % RTE_RETA_GROUP_SIZE;
3546 if (reta_conf[idx].mask & (1ULL << shift))
3547 lut[i] = reta_conf[idx].reta[shift];
3549 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3558 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3559 struct rte_eth_rss_reta_entry64 *reta_conf,
3562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3563 uint16_t i, lut_size = pf->hash_lut_size;
3564 uint16_t idx, shift;
3568 if (reta_size != lut_size ||
3569 reta_size > ETH_RSS_RETA_SIZE_512) {
3571 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3572 reta_size, lut_size);
3576 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3578 PMD_DRV_LOG(ERR, "No memory can be allocated");
3582 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3585 for (i = 0; i < reta_size; i++) {
3586 idx = i / RTE_RETA_GROUP_SIZE;
3587 shift = i % RTE_RETA_GROUP_SIZE;
3588 if (reta_conf[idx].mask & (1ULL << shift))
3589 reta_conf[idx].reta[shift] = lut[i];
3599 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3600 * @hw: pointer to the HW structure
3601 * @mem: pointer to mem struct to fill out
3602 * @size: size of memory requested
3603 * @alignment: what to align the allocation to
3605 enum i40e_status_code
3606 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3607 struct i40e_dma_mem *mem,
3611 const struct rte_memzone *mz = NULL;
3612 char z_name[RTE_MEMZONE_NAMESIZE];
3615 return I40E_ERR_PARAM;
3617 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3618 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3619 alignment, RTE_PGSIZE_2M);
3621 return I40E_ERR_NO_MEMORY;
3625 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3626 mem->zone = (const void *)mz;
3628 "memzone %s allocated with physical address: %"PRIu64,
3631 return I40E_SUCCESS;
3635 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3636 * @hw: pointer to the HW structure
3637 * @mem: ptr to mem struct to free
3639 enum i40e_status_code
3640 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3641 struct i40e_dma_mem *mem)
3644 return I40E_ERR_PARAM;
3647 "memzone %s to be freed with physical address: %"PRIu64,
3648 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3649 rte_memzone_free((const struct rte_memzone *)mem->zone);
3654 return I40E_SUCCESS;
3658 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3659 * @hw: pointer to the HW structure
3660 * @mem: pointer to mem struct to fill out
3661 * @size: size of memory requested
3663 enum i40e_status_code
3664 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3665 struct i40e_virt_mem *mem,
3669 return I40E_ERR_PARAM;
3672 mem->va = rte_zmalloc("i40e", size, 0);
3675 return I40E_SUCCESS;
3677 return I40E_ERR_NO_MEMORY;
3681 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3682 * @hw: pointer to the HW structure
3683 * @mem: pointer to mem struct to free
3685 enum i40e_status_code
3686 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3687 struct i40e_virt_mem *mem)
3690 return I40E_ERR_PARAM;
3695 return I40E_SUCCESS;
3699 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3701 rte_spinlock_init(&sp->spinlock);
3705 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3707 rte_spinlock_lock(&sp->spinlock);
3711 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3713 rte_spinlock_unlock(&sp->spinlock);
3717 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3723 * Get the hardware capabilities, which will be parsed
3724 * and saved into struct i40e_hw.
3727 i40e_get_cap(struct i40e_hw *hw)
3729 struct i40e_aqc_list_capabilities_element_resp *buf;
3730 uint16_t len, size = 0;
3733 /* Calculate a huge enough buff for saving response data temporarily */
3734 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3735 I40E_MAX_CAP_ELE_NUM;
3736 buf = rte_zmalloc("i40e", len, 0);
3738 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3739 return I40E_ERR_NO_MEMORY;
3742 /* Get, parse the capabilities and save it to hw */
3743 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3744 i40e_aqc_opc_list_func_capabilities, NULL);
3745 if (ret != I40E_SUCCESS)
3746 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3748 /* Free the temporary buffer after being used */
3755 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3758 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3759 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3760 uint16_t qp_count = 0, vsi_count = 0;
3762 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3763 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3766 /* Add the parameter init for LFC */
3767 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3768 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3769 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3771 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3772 pf->max_num_vsi = hw->func_caps.num_vsis;
3773 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3774 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3775 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3777 /* FDir queue/VSI allocation */
3778 pf->fdir_qp_offset = 0;
3779 if (hw->func_caps.fd) {
3780 pf->flags |= I40E_FLAG_FDIR;
3781 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3783 pf->fdir_nb_qps = 0;
3785 qp_count += pf->fdir_nb_qps;
3788 /* LAN queue/VSI allocation */
3789 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3790 if (!hw->func_caps.rss) {
3793 pf->flags |= I40E_FLAG_RSS;
3794 if (hw->mac.type == I40E_MAC_X722)
3795 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3796 pf->lan_nb_qps = pf->lan_nb_qp_max;
3798 qp_count += pf->lan_nb_qps;
3801 /* VF queue/VSI allocation */
3802 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3803 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3804 pf->flags |= I40E_FLAG_SRIOV;
3805 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3806 pf->vf_num = pci_dev->max_vfs;
3808 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3809 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3814 qp_count += pf->vf_nb_qps * pf->vf_num;
3815 vsi_count += pf->vf_num;
3817 /* VMDq queue/VSI allocation */
3818 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3819 pf->vmdq_nb_qps = 0;
3820 pf->max_nb_vmdq_vsi = 0;
3821 if (hw->func_caps.vmdq) {
3822 if (qp_count < hw->func_caps.num_tx_qp &&
3823 vsi_count < hw->func_caps.num_vsis) {
3824 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3825 qp_count) / pf->vmdq_nb_qp_max;
3827 /* Limit the maximum number of VMDq vsi to the maximum
3828 * ethdev can support
3830 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3831 hw->func_caps.num_vsis - vsi_count);
3832 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3834 if (pf->max_nb_vmdq_vsi) {
3835 pf->flags |= I40E_FLAG_VMDQ;
3836 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3838 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3839 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3840 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3843 "No enough queues left for VMDq");
3846 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3849 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3850 vsi_count += pf->max_nb_vmdq_vsi;
3852 if (hw->func_caps.dcb)
3853 pf->flags |= I40E_FLAG_DCB;
3855 if (qp_count > hw->func_caps.num_tx_qp) {
3857 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3858 qp_count, hw->func_caps.num_tx_qp);
3861 if (vsi_count > hw->func_caps.num_vsis) {
3863 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3864 vsi_count, hw->func_caps.num_vsis);
3872 i40e_pf_get_switch_config(struct i40e_pf *pf)
3874 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3875 struct i40e_aqc_get_switch_config_resp *switch_config;
3876 struct i40e_aqc_switch_config_element_resp *element;
3877 uint16_t start_seid = 0, num_reported;
3880 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3881 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3882 if (!switch_config) {
3883 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3887 /* Get the switch configurations */
3888 ret = i40e_aq_get_switch_config(hw, switch_config,
3889 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3890 if (ret != I40E_SUCCESS) {
3891 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3894 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3895 if (num_reported != 1) { /* The number should be 1 */
3896 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3900 /* Parse the switch configuration elements */
3901 element = &(switch_config->element[0]);
3902 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3903 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3904 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3906 PMD_DRV_LOG(INFO, "Unknown element type");
3909 rte_free(switch_config);
3915 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3918 struct pool_entry *entry;
3920 if (pool == NULL || num == 0)
3923 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3924 if (entry == NULL) {
3925 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3929 /* queue heap initialize */
3930 pool->num_free = num;
3931 pool->num_alloc = 0;
3933 LIST_INIT(&pool->alloc_list);
3934 LIST_INIT(&pool->free_list);
3936 /* Initialize element */
3940 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3945 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3947 struct pool_entry *entry, *next_entry;
3952 for (entry = LIST_FIRST(&pool->alloc_list);
3953 entry && (next_entry = LIST_NEXT(entry, next), 1);
3954 entry = next_entry) {
3955 LIST_REMOVE(entry, next);
3959 for (entry = LIST_FIRST(&pool->free_list);
3960 entry && (next_entry = LIST_NEXT(entry, next), 1);
3961 entry = next_entry) {
3962 LIST_REMOVE(entry, next);
3967 pool->num_alloc = 0;
3969 LIST_INIT(&pool->alloc_list);
3970 LIST_INIT(&pool->free_list);
3974 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3977 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3978 uint32_t pool_offset;
3982 PMD_DRV_LOG(ERR, "Invalid parameter");
3986 pool_offset = base - pool->base;
3987 /* Lookup in alloc list */
3988 LIST_FOREACH(entry, &pool->alloc_list, next) {
3989 if (entry->base == pool_offset) {
3990 valid_entry = entry;
3991 LIST_REMOVE(entry, next);
3996 /* Not find, return */
3997 if (valid_entry == NULL) {
3998 PMD_DRV_LOG(ERR, "Failed to find entry");
4003 * Found it, move it to free list and try to merge.
4004 * In order to make merge easier, always sort it by qbase.
4005 * Find adjacent prev and last entries.
4008 LIST_FOREACH(entry, &pool->free_list, next) {
4009 if (entry->base > valid_entry->base) {
4017 /* Try to merge with next one*/
4019 /* Merge with next one */
4020 if (valid_entry->base + valid_entry->len == next->base) {
4021 next->base = valid_entry->base;
4022 next->len += valid_entry->len;
4023 rte_free(valid_entry);
4030 /* Merge with previous one */
4031 if (prev->base + prev->len == valid_entry->base) {
4032 prev->len += valid_entry->len;
4033 /* If it merge with next one, remove next node */
4035 LIST_REMOVE(valid_entry, next);
4036 rte_free(valid_entry);
4038 rte_free(valid_entry);
4044 /* Not find any entry to merge, insert */
4047 LIST_INSERT_AFTER(prev, valid_entry, next);
4048 else if (next != NULL)
4049 LIST_INSERT_BEFORE(next, valid_entry, next);
4050 else /* It's empty list, insert to head */
4051 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4054 pool->num_free += valid_entry->len;
4055 pool->num_alloc -= valid_entry->len;
4061 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4064 struct pool_entry *entry, *valid_entry;
4066 if (pool == NULL || num == 0) {
4067 PMD_DRV_LOG(ERR, "Invalid parameter");
4071 if (pool->num_free < num) {
4072 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4073 num, pool->num_free);
4078 /* Lookup in free list and find most fit one */
4079 LIST_FOREACH(entry, &pool->free_list, next) {
4080 if (entry->len >= num) {
4082 if (entry->len == num) {
4083 valid_entry = entry;
4086 if (valid_entry == NULL || valid_entry->len > entry->len)
4087 valid_entry = entry;
4091 /* Not find one to satisfy the request, return */
4092 if (valid_entry == NULL) {
4093 PMD_DRV_LOG(ERR, "No valid entry found");
4097 * The entry have equal queue number as requested,
4098 * remove it from alloc_list.
4100 if (valid_entry->len == num) {
4101 LIST_REMOVE(valid_entry, next);
4104 * The entry have more numbers than requested,
4105 * create a new entry for alloc_list and minus its
4106 * queue base and number in free_list.
4108 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4109 if (entry == NULL) {
4111 "Failed to allocate memory for resource pool");
4114 entry->base = valid_entry->base;
4116 valid_entry->base += num;
4117 valid_entry->len -= num;
4118 valid_entry = entry;
4121 /* Insert it into alloc list, not sorted */
4122 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4124 pool->num_free -= valid_entry->len;
4125 pool->num_alloc += valid_entry->len;
4127 return valid_entry->base + pool->base;
4131 * bitmap_is_subset - Check whether src2 is subset of src1
4134 bitmap_is_subset(uint8_t src1, uint8_t src2)
4136 return !((src1 ^ src2) & src2);
4139 static enum i40e_status_code
4140 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4142 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4144 /* If DCB is not supported, only default TC is supported */
4145 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4146 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4147 return I40E_NOT_SUPPORTED;
4150 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4152 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4153 hw->func_caps.enabled_tcmap, enabled_tcmap);
4154 return I40E_NOT_SUPPORTED;
4156 return I40E_SUCCESS;
4160 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4161 struct i40e_vsi_vlan_pvid_info *info)
4164 struct i40e_vsi_context ctxt;
4165 uint8_t vlan_flags = 0;
4168 if (vsi == NULL || info == NULL) {
4169 PMD_DRV_LOG(ERR, "invalid parameters");
4170 return I40E_ERR_PARAM;
4174 vsi->info.pvid = info->config.pvid;
4176 * If insert pvid is enabled, only tagged pkts are
4177 * allowed to be sent out.
4179 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4180 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4183 if (info->config.reject.tagged == 0)
4184 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4186 if (info->config.reject.untagged == 0)
4187 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4189 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4190 I40E_AQ_VSI_PVLAN_MODE_MASK);
4191 vsi->info.port_vlan_flags |= vlan_flags;
4192 vsi->info.valid_sections =
4193 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4194 memset(&ctxt, 0, sizeof(ctxt));
4195 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4196 ctxt.seid = vsi->seid;
4198 hw = I40E_VSI_TO_HW(vsi);
4199 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4200 if (ret != I40E_SUCCESS)
4201 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4207 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4209 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4211 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4213 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4214 if (ret != I40E_SUCCESS)
4218 PMD_DRV_LOG(ERR, "seid not valid");
4222 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4223 tc_bw_data.tc_valid_bits = enabled_tcmap;
4224 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4225 tc_bw_data.tc_bw_credits[i] =
4226 (enabled_tcmap & (1 << i)) ? 1 : 0;
4228 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4229 if (ret != I40E_SUCCESS) {
4230 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4234 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4235 sizeof(vsi->info.qs_handle));
4236 return I40E_SUCCESS;
4239 static enum i40e_status_code
4240 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4241 struct i40e_aqc_vsi_properties_data *info,
4242 uint8_t enabled_tcmap)
4244 enum i40e_status_code ret;
4245 int i, total_tc = 0;
4246 uint16_t qpnum_per_tc, bsf, qp_idx;
4248 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4249 if (ret != I40E_SUCCESS)
4252 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4253 if (enabled_tcmap & (1 << i))
4255 vsi->enabled_tc = enabled_tcmap;
4257 /* Number of queues per enabled TC */
4258 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4259 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4260 bsf = rte_bsf32(qpnum_per_tc);
4262 /* Adjust the queue number to actual queues that can be applied */
4263 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4264 vsi->nb_qps = qpnum_per_tc * total_tc;
4267 * Configure TC and queue mapping parameters, for enabled TC,
4268 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4269 * default queue will serve it.
4272 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4273 if (vsi->enabled_tc & (1 << i)) {
4274 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4275 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4276 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4277 qp_idx += qpnum_per_tc;
4279 info->tc_mapping[i] = 0;
4282 /* Associate queue number with VSI */
4283 if (vsi->type == I40E_VSI_SRIOV) {
4284 info->mapping_flags |=
4285 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4286 for (i = 0; i < vsi->nb_qps; i++)
4287 info->queue_mapping[i] =
4288 rte_cpu_to_le_16(vsi->base_queue + i);
4290 info->mapping_flags |=
4291 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4292 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4294 info->valid_sections |=
4295 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4297 return I40E_SUCCESS;
4301 i40e_veb_release(struct i40e_veb *veb)
4303 struct i40e_vsi *vsi;
4309 if (!TAILQ_EMPTY(&veb->head)) {
4310 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4313 /* associate_vsi field is NULL for floating VEB */
4314 if (veb->associate_vsi != NULL) {
4315 vsi = veb->associate_vsi;
4316 hw = I40E_VSI_TO_HW(vsi);
4318 vsi->uplink_seid = veb->uplink_seid;
4321 veb->associate_pf->main_vsi->floating_veb = NULL;
4322 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4325 i40e_aq_delete_element(hw, veb->seid, NULL);
4327 return I40E_SUCCESS;
4331 static struct i40e_veb *
4332 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4334 struct i40e_veb *veb;
4340 "veb setup failed, associated PF shouldn't null");
4343 hw = I40E_PF_TO_HW(pf);
4345 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4347 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4351 veb->associate_vsi = vsi;
4352 veb->associate_pf = pf;
4353 TAILQ_INIT(&veb->head);
4354 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4356 /* create floating veb if vsi is NULL */
4358 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4359 I40E_DEFAULT_TCMAP, false,
4360 &veb->seid, false, NULL);
4362 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4363 true, &veb->seid, false, NULL);
4366 if (ret != I40E_SUCCESS) {
4367 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4368 hw->aq.asq_last_status);
4371 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4373 /* get statistics index */
4374 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4375 &veb->stats_idx, NULL, NULL, NULL);
4376 if (ret != I40E_SUCCESS) {
4377 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4378 hw->aq.asq_last_status);
4381 /* Get VEB bandwidth, to be implemented */
4382 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4384 vsi->uplink_seid = veb->seid;
4393 i40e_vsi_release(struct i40e_vsi *vsi)
4397 struct i40e_vsi_list *vsi_list;
4400 struct i40e_mac_filter *f;
4401 uint16_t user_param;
4404 return I40E_SUCCESS;
4409 user_param = vsi->user_param;
4411 pf = I40E_VSI_TO_PF(vsi);
4412 hw = I40E_VSI_TO_HW(vsi);
4414 /* VSI has child to attach, release child first */
4416 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4417 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4420 i40e_veb_release(vsi->veb);
4423 if (vsi->floating_veb) {
4424 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4425 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4430 /* Remove all macvlan filters of the VSI */
4431 i40e_vsi_remove_all_macvlan_filter(vsi);
4432 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4435 if (vsi->type != I40E_VSI_MAIN &&
4436 ((vsi->type != I40E_VSI_SRIOV) ||
4437 !pf->floating_veb_list[user_param])) {
4438 /* Remove vsi from parent's sibling list */
4439 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4440 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4441 return I40E_ERR_PARAM;
4443 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4444 &vsi->sib_vsi_list, list);
4446 /* Remove all switch element of the VSI */
4447 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4448 if (ret != I40E_SUCCESS)
4449 PMD_DRV_LOG(ERR, "Failed to delete element");
4452 if ((vsi->type == I40E_VSI_SRIOV) &&
4453 pf->floating_veb_list[user_param]) {
4454 /* Remove vsi from parent's sibling list */
4455 if (vsi->parent_vsi == NULL ||
4456 vsi->parent_vsi->floating_veb == NULL) {
4457 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4458 return I40E_ERR_PARAM;
4460 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4461 &vsi->sib_vsi_list, list);
4463 /* Remove all switch element of the VSI */
4464 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4465 if (ret != I40E_SUCCESS)
4466 PMD_DRV_LOG(ERR, "Failed to delete element");
4469 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4471 if (vsi->type != I40E_VSI_SRIOV)
4472 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4475 return I40E_SUCCESS;
4479 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4481 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4482 struct i40e_aqc_remove_macvlan_element_data def_filter;
4483 struct i40e_mac_filter_info filter;
4486 if (vsi->type != I40E_VSI_MAIN)
4487 return I40E_ERR_CONFIG;
4488 memset(&def_filter, 0, sizeof(def_filter));
4489 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4491 def_filter.vlan_tag = 0;
4492 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4493 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4494 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4495 if (ret != I40E_SUCCESS) {
4496 struct i40e_mac_filter *f;
4497 struct ether_addr *mac;
4499 PMD_DRV_LOG(WARNING,
4500 "Cannot remove the default macvlan filter");
4501 /* It needs to add the permanent mac into mac list */
4502 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4504 PMD_DRV_LOG(ERR, "failed to allocate memory");
4505 return I40E_ERR_NO_MEMORY;
4507 mac = &f->mac_info.mac_addr;
4508 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4510 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4511 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4516 (void)rte_memcpy(&filter.mac_addr,
4517 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4518 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4519 return i40e_vsi_add_mac(vsi, &filter);
4523 * i40e_vsi_get_bw_config - Query VSI BW Information
4524 * @vsi: the VSI to be queried
4526 * Returns 0 on success, negative value on failure
4528 static enum i40e_status_code
4529 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4531 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4532 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4533 struct i40e_hw *hw = &vsi->adapter->hw;
4538 memset(&bw_config, 0, sizeof(bw_config));
4539 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4540 if (ret != I40E_SUCCESS) {
4541 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4542 hw->aq.asq_last_status);
4546 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4547 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4548 &ets_sla_config, NULL);
4549 if (ret != I40E_SUCCESS) {
4551 "VSI failed to get TC bandwdith configuration %u",
4552 hw->aq.asq_last_status);
4556 /* store and print out BW info */
4557 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4558 vsi->bw_info.bw_max = bw_config.max_bw;
4559 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4560 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4561 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4562 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4564 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4565 vsi->bw_info.bw_ets_share_credits[i] =
4566 ets_sla_config.share_credits[i];
4567 vsi->bw_info.bw_ets_credits[i] =
4568 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4569 /* 4 bits per TC, 4th bit is reserved */
4570 vsi->bw_info.bw_ets_max[i] =
4571 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4572 RTE_LEN2MASK(3, uint8_t));
4573 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4574 vsi->bw_info.bw_ets_share_credits[i]);
4575 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4576 vsi->bw_info.bw_ets_credits[i]);
4577 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4578 vsi->bw_info.bw_ets_max[i]);
4581 return I40E_SUCCESS;
4584 /* i40e_enable_pf_lb
4585 * @pf: pointer to the pf structure
4587 * allow loopback on pf
4590 i40e_enable_pf_lb(struct i40e_pf *pf)
4592 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4593 struct i40e_vsi_context ctxt;
4596 /* Use the FW API if FW >= v5.0 */
4597 if (hw->aq.fw_maj_ver < 5) {
4598 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4602 memset(&ctxt, 0, sizeof(ctxt));
4603 ctxt.seid = pf->main_vsi_seid;
4604 ctxt.pf_num = hw->pf_id;
4605 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4607 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4608 ret, hw->aq.asq_last_status);
4611 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4612 ctxt.info.valid_sections =
4613 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4614 ctxt.info.switch_id |=
4615 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4617 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4619 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4620 hw->aq.asq_last_status);
4625 i40e_vsi_setup(struct i40e_pf *pf,
4626 enum i40e_vsi_type type,
4627 struct i40e_vsi *uplink_vsi,
4628 uint16_t user_param)
4630 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4631 struct i40e_vsi *vsi;
4632 struct i40e_mac_filter_info filter;
4634 struct i40e_vsi_context ctxt;
4635 struct ether_addr broadcast =
4636 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4638 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4639 uplink_vsi == NULL) {
4641 "VSI setup failed, VSI link shouldn't be NULL");
4645 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4647 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4652 * 1.type is not MAIN and uplink vsi is not NULL
4653 * If uplink vsi didn't setup VEB, create one first under veb field
4654 * 2.type is SRIOV and the uplink is NULL
4655 * If floating VEB is NULL, create one veb under floating veb field
4658 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4659 uplink_vsi->veb == NULL) {
4660 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4662 if (uplink_vsi->veb == NULL) {
4663 PMD_DRV_LOG(ERR, "VEB setup failed");
4666 /* set ALLOWLOOPBACk on pf, when veb is created */
4667 i40e_enable_pf_lb(pf);
4670 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4671 pf->main_vsi->floating_veb == NULL) {
4672 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4674 if (pf->main_vsi->floating_veb == NULL) {
4675 PMD_DRV_LOG(ERR, "VEB setup failed");
4680 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4682 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4685 TAILQ_INIT(&vsi->mac_list);
4687 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4688 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4689 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4690 vsi->user_param = user_param;
4691 vsi->vlan_anti_spoof_on = 0;
4692 vsi->vlan_filter_on = 0;
4693 /* Allocate queues */
4694 switch (vsi->type) {
4695 case I40E_VSI_MAIN :
4696 vsi->nb_qps = pf->lan_nb_qps;
4698 case I40E_VSI_SRIOV :
4699 vsi->nb_qps = pf->vf_nb_qps;
4701 case I40E_VSI_VMDQ2:
4702 vsi->nb_qps = pf->vmdq_nb_qps;
4705 vsi->nb_qps = pf->fdir_nb_qps;
4711 * The filter status descriptor is reported in rx queue 0,
4712 * while the tx queue for fdir filter programming has no
4713 * such constraints, can be non-zero queues.
4714 * To simplify it, choose FDIR vsi use queue 0 pair.
4715 * To make sure it will use queue 0 pair, queue allocation
4716 * need be done before this function is called
4718 if (type != I40E_VSI_FDIR) {
4719 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4721 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4725 vsi->base_queue = ret;
4727 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4729 /* VF has MSIX interrupt in VF range, don't allocate here */
4730 if (type == I40E_VSI_MAIN) {
4731 ret = i40e_res_pool_alloc(&pf->msix_pool,
4732 RTE_MIN(vsi->nb_qps,
4733 RTE_MAX_RXTX_INTR_VEC_ID));
4735 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4737 goto fail_queue_alloc;
4739 vsi->msix_intr = ret;
4740 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4741 } else if (type != I40E_VSI_SRIOV) {
4742 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4744 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4745 goto fail_queue_alloc;
4747 vsi->msix_intr = ret;
4755 if (type == I40E_VSI_MAIN) {
4756 /* For main VSI, no need to add since it's default one */
4757 vsi->uplink_seid = pf->mac_seid;
4758 vsi->seid = pf->main_vsi_seid;
4759 /* Bind queues with specific MSIX interrupt */
4761 * Needs 2 interrupt at least, one for misc cause which will
4762 * enabled from OS side, Another for queues binding the
4763 * interrupt from device side only.
4766 /* Get default VSI parameters from hardware */
4767 memset(&ctxt, 0, sizeof(ctxt));
4768 ctxt.seid = vsi->seid;
4769 ctxt.pf_num = hw->pf_id;
4770 ctxt.uplink_seid = vsi->uplink_seid;
4772 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4773 if (ret != I40E_SUCCESS) {
4774 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4775 goto fail_msix_alloc;
4777 (void)rte_memcpy(&vsi->info, &ctxt.info,
4778 sizeof(struct i40e_aqc_vsi_properties_data));
4779 vsi->vsi_id = ctxt.vsi_number;
4780 vsi->info.valid_sections = 0;
4782 /* Configure tc, enabled TC0 only */
4783 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4785 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4786 goto fail_msix_alloc;
4789 /* TC, queue mapping */
4790 memset(&ctxt, 0, sizeof(ctxt));
4791 vsi->info.valid_sections |=
4792 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4793 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4794 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4795 (void)rte_memcpy(&ctxt.info, &vsi->info,
4796 sizeof(struct i40e_aqc_vsi_properties_data));
4797 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4798 I40E_DEFAULT_TCMAP);
4799 if (ret != I40E_SUCCESS) {
4801 "Failed to configure TC queue mapping");
4802 goto fail_msix_alloc;
4804 ctxt.seid = vsi->seid;
4805 ctxt.pf_num = hw->pf_id;
4806 ctxt.uplink_seid = vsi->uplink_seid;
4809 /* Update VSI parameters */
4810 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4811 if (ret != I40E_SUCCESS) {
4812 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4813 goto fail_msix_alloc;
4816 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4817 sizeof(vsi->info.tc_mapping));
4818 (void)rte_memcpy(&vsi->info.queue_mapping,
4819 &ctxt.info.queue_mapping,
4820 sizeof(vsi->info.queue_mapping));
4821 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4822 vsi->info.valid_sections = 0;
4824 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4828 * Updating default filter settings are necessary to prevent
4829 * reception of tagged packets.
4830 * Some old firmware configurations load a default macvlan
4831 * filter which accepts both tagged and untagged packets.
4832 * The updating is to use a normal filter instead if needed.
4833 * For NVM 4.2.2 or after, the updating is not needed anymore.
4834 * The firmware with correct configurations load the default
4835 * macvlan filter which is expected and cannot be removed.
4837 i40e_update_default_filter_setting(vsi);
4838 i40e_config_qinq(hw, vsi);
4839 } else if (type == I40E_VSI_SRIOV) {
4840 memset(&ctxt, 0, sizeof(ctxt));
4842 * For other VSI, the uplink_seid equals to uplink VSI's
4843 * uplink_seid since they share same VEB
4845 if (uplink_vsi == NULL)
4846 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4848 vsi->uplink_seid = uplink_vsi->uplink_seid;
4849 ctxt.pf_num = hw->pf_id;
4850 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4851 ctxt.uplink_seid = vsi->uplink_seid;
4852 ctxt.connection_type = 0x1;
4853 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4855 /* Use the VEB configuration if FW >= v5.0 */
4856 if (hw->aq.fw_maj_ver >= 5) {
4857 /* Configure switch ID */
4858 ctxt.info.valid_sections |=
4859 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4860 ctxt.info.switch_id =
4861 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4864 /* Configure port/vlan */
4865 ctxt.info.valid_sections |=
4866 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4867 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4868 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4869 hw->func_caps.enabled_tcmap);
4870 if (ret != I40E_SUCCESS) {
4872 "Failed to configure TC queue mapping");
4873 goto fail_msix_alloc;
4876 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4877 ctxt.info.valid_sections |=
4878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4880 * Since VSI is not created yet, only configure parameter,
4881 * will add vsi below.
4884 i40e_config_qinq(hw, vsi);
4885 } else if (type == I40E_VSI_VMDQ2) {
4886 memset(&ctxt, 0, sizeof(ctxt));
4888 * For other VSI, the uplink_seid equals to uplink VSI's
4889 * uplink_seid since they share same VEB
4891 vsi->uplink_seid = uplink_vsi->uplink_seid;
4892 ctxt.pf_num = hw->pf_id;
4894 ctxt.uplink_seid = vsi->uplink_seid;
4895 ctxt.connection_type = 0x1;
4896 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4898 ctxt.info.valid_sections |=
4899 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4900 /* user_param carries flag to enable loop back */
4902 ctxt.info.switch_id =
4903 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4904 ctxt.info.switch_id |=
4905 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4908 /* Configure port/vlan */
4909 ctxt.info.valid_sections |=
4910 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4911 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4912 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4913 I40E_DEFAULT_TCMAP);
4914 if (ret != I40E_SUCCESS) {
4916 "Failed to configure TC queue mapping");
4917 goto fail_msix_alloc;
4919 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4920 ctxt.info.valid_sections |=
4921 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4922 } else if (type == I40E_VSI_FDIR) {
4923 memset(&ctxt, 0, sizeof(ctxt));
4924 vsi->uplink_seid = uplink_vsi->uplink_seid;
4925 ctxt.pf_num = hw->pf_id;
4927 ctxt.uplink_seid = vsi->uplink_seid;
4928 ctxt.connection_type = 0x1; /* regular data port */
4929 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4930 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4931 I40E_DEFAULT_TCMAP);
4932 if (ret != I40E_SUCCESS) {
4934 "Failed to configure TC queue mapping.");
4935 goto fail_msix_alloc;
4937 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4938 ctxt.info.valid_sections |=
4939 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4941 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4942 goto fail_msix_alloc;
4945 if (vsi->type != I40E_VSI_MAIN) {
4946 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4947 if (ret != I40E_SUCCESS) {
4948 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4949 hw->aq.asq_last_status);
4950 goto fail_msix_alloc;
4952 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4953 vsi->info.valid_sections = 0;
4954 vsi->seid = ctxt.seid;
4955 vsi->vsi_id = ctxt.vsi_number;
4956 vsi->sib_vsi_list.vsi = vsi;
4957 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4958 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4959 &vsi->sib_vsi_list, list);
4961 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4962 &vsi->sib_vsi_list, list);
4966 /* MAC/VLAN configuration */
4967 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4968 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4970 ret = i40e_vsi_add_mac(vsi, &filter);
4971 if (ret != I40E_SUCCESS) {
4972 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4973 goto fail_msix_alloc;
4976 /* Get VSI BW information */
4977 i40e_vsi_get_bw_config(vsi);
4980 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4982 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4988 /* Configure vlan filter on or off */
4990 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4993 struct i40e_mac_filter *f;
4995 struct i40e_mac_filter_info *mac_filter;
4996 enum rte_mac_filter_type desired_filter;
4997 int ret = I40E_SUCCESS;
5000 /* Filter to match MAC and VLAN */
5001 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5003 /* Filter to match only MAC */
5004 desired_filter = RTE_MAC_PERFECT_MATCH;
5009 mac_filter = rte_zmalloc("mac_filter_info_data",
5010 num * sizeof(*mac_filter), 0);
5011 if (mac_filter == NULL) {
5012 PMD_DRV_LOG(ERR, "failed to allocate memory");
5013 return I40E_ERR_NO_MEMORY;
5018 /* Remove all existing mac */
5019 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5020 mac_filter[i] = f->mac_info;
5021 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5023 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5024 on ? "enable" : "disable");
5030 /* Override with new filter */
5031 for (i = 0; i < num; i++) {
5032 mac_filter[i].filter_type = desired_filter;
5033 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5035 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5036 on ? "enable" : "disable");
5042 rte_free(mac_filter);
5046 /* Configure vlan stripping on or off */
5048 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5050 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5051 struct i40e_vsi_context ctxt;
5053 int ret = I40E_SUCCESS;
5055 /* Check if it has been already on or off */
5056 if (vsi->info.valid_sections &
5057 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5059 if ((vsi->info.port_vlan_flags &
5060 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5061 return 0; /* already on */
5063 if ((vsi->info.port_vlan_flags &
5064 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5065 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5066 return 0; /* already off */
5071 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5073 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5074 vsi->info.valid_sections =
5075 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5076 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5077 vsi->info.port_vlan_flags |= vlan_flags;
5078 ctxt.seid = vsi->seid;
5079 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5080 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5082 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5083 on ? "enable" : "disable");
5089 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5091 struct rte_eth_dev_data *data = dev->data;
5095 /* Apply vlan offload setting */
5096 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5097 i40e_vlan_offload_set(dev, mask);
5099 /* Apply double-vlan setting, not implemented yet */
5101 /* Apply pvid setting */
5102 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5103 data->dev_conf.txmode.hw_vlan_insert_pvid);
5105 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5111 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5113 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5115 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5119 i40e_update_flow_control(struct i40e_hw *hw)
5121 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5122 struct i40e_link_status link_status;
5123 uint32_t rxfc = 0, txfc = 0, reg;
5127 memset(&link_status, 0, sizeof(link_status));
5128 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5129 if (ret != I40E_SUCCESS) {
5130 PMD_DRV_LOG(ERR, "Failed to get link status information");
5131 goto write_reg; /* Disable flow control */
5134 an_info = hw->phy.link_info.an_info;
5135 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5136 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5137 ret = I40E_ERR_NOT_READY;
5138 goto write_reg; /* Disable flow control */
5141 * If link auto negotiation is enabled, flow control needs to
5142 * be configured according to it
5144 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5145 case I40E_LINK_PAUSE_RXTX:
5148 hw->fc.current_mode = I40E_FC_FULL;
5150 case I40E_AQ_LINK_PAUSE_RX:
5152 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5154 case I40E_AQ_LINK_PAUSE_TX:
5156 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5159 hw->fc.current_mode = I40E_FC_NONE;
5164 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5165 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5166 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5167 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5168 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5169 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5176 i40e_pf_setup(struct i40e_pf *pf)
5178 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5179 struct i40e_filter_control_settings settings;
5180 struct i40e_vsi *vsi;
5183 /* Clear all stats counters */
5184 pf->offset_loaded = FALSE;
5185 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5186 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5188 ret = i40e_pf_get_switch_config(pf);
5189 if (ret != I40E_SUCCESS) {
5190 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5193 if (pf->flags & I40E_FLAG_FDIR) {
5194 /* make queue allocated first, let FDIR use queue pair 0*/
5195 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5196 if (ret != I40E_FDIR_QUEUE_ID) {
5198 "queue allocation fails for FDIR: ret =%d",
5200 pf->flags &= ~I40E_FLAG_FDIR;
5203 /* main VSI setup */
5204 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5206 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5207 return I40E_ERR_NOT_READY;
5211 /* Configure filter control */
5212 memset(&settings, 0, sizeof(settings));
5213 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5214 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5215 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5216 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5218 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5219 hw->func_caps.rss_table_size);
5220 return I40E_ERR_PARAM;
5222 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5223 hw->func_caps.rss_table_size);
5224 pf->hash_lut_size = hw->func_caps.rss_table_size;
5226 /* Enable ethtype and macvlan filters */
5227 settings.enable_ethtype = TRUE;
5228 settings.enable_macvlan = TRUE;
5229 ret = i40e_set_filter_control(hw, &settings);
5231 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5234 /* Update flow control according to the auto negotiation */
5235 i40e_update_flow_control(hw);
5237 return I40E_SUCCESS;
5241 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5247 * Set or clear TX Queue Disable flags,
5248 * which is required by hardware.
5250 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5251 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5253 /* Wait until the request is finished */
5254 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5255 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5256 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5257 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5258 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5264 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5265 return I40E_SUCCESS; /* already on, skip next steps */
5267 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5268 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5270 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5271 return I40E_SUCCESS; /* already off, skip next steps */
5272 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5274 /* Write the register */
5275 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5276 /* Check the result */
5277 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5278 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5279 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5281 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5282 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5285 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5286 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5290 /* Check if it is timeout */
5291 if (j >= I40E_CHK_Q_ENA_COUNT) {
5292 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5293 (on ? "enable" : "disable"), q_idx);
5294 return I40E_ERR_TIMEOUT;
5297 return I40E_SUCCESS;
5300 /* Swith on or off the tx queues */
5302 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5304 struct rte_eth_dev_data *dev_data = pf->dev_data;
5305 struct i40e_tx_queue *txq;
5306 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5310 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5311 txq = dev_data->tx_queues[i];
5312 /* Don't operate the queue if not configured or
5313 * if starting only per queue */
5314 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5317 ret = i40e_dev_tx_queue_start(dev, i);
5319 ret = i40e_dev_tx_queue_stop(dev, i);
5320 if ( ret != I40E_SUCCESS)
5324 return I40E_SUCCESS;
5328 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5333 /* Wait until the request is finished */
5334 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5335 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5336 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5337 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5338 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5343 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5344 return I40E_SUCCESS; /* Already on, skip next steps */
5345 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5347 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5348 return I40E_SUCCESS; /* Already off, skip next steps */
5349 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5352 /* Write the register */
5353 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5354 /* Check the result */
5355 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5356 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5357 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5359 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5360 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5363 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5364 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5369 /* Check if it is timeout */
5370 if (j >= I40E_CHK_Q_ENA_COUNT) {
5371 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5372 (on ? "enable" : "disable"), q_idx);
5373 return I40E_ERR_TIMEOUT;
5376 return I40E_SUCCESS;
5378 /* Switch on or off the rx queues */
5380 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5382 struct rte_eth_dev_data *dev_data = pf->dev_data;
5383 struct i40e_rx_queue *rxq;
5384 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5388 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5389 rxq = dev_data->rx_queues[i];
5390 /* Don't operate the queue if not configured or
5391 * if starting only per queue */
5392 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5395 ret = i40e_dev_rx_queue_start(dev, i);
5397 ret = i40e_dev_rx_queue_stop(dev, i);
5398 if (ret != I40E_SUCCESS)
5402 return I40E_SUCCESS;
5405 /* Switch on or off all the rx/tx queues */
5407 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5412 /* enable rx queues before enabling tx queues */
5413 ret = i40e_dev_switch_rx_queues(pf, on);
5415 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5418 ret = i40e_dev_switch_tx_queues(pf, on);
5420 /* Stop tx queues before stopping rx queues */
5421 ret = i40e_dev_switch_tx_queues(pf, on);
5423 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5426 ret = i40e_dev_switch_rx_queues(pf, on);
5432 /* Initialize VSI for TX */
5434 i40e_dev_tx_init(struct i40e_pf *pf)
5436 struct rte_eth_dev_data *data = pf->dev_data;
5438 uint32_t ret = I40E_SUCCESS;
5439 struct i40e_tx_queue *txq;
5441 for (i = 0; i < data->nb_tx_queues; i++) {
5442 txq = data->tx_queues[i];
5443 if (!txq || !txq->q_set)
5445 ret = i40e_tx_queue_init(txq);
5446 if (ret != I40E_SUCCESS)
5449 if (ret == I40E_SUCCESS)
5450 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5456 /* Initialize VSI for RX */
5458 i40e_dev_rx_init(struct i40e_pf *pf)
5460 struct rte_eth_dev_data *data = pf->dev_data;
5461 int ret = I40E_SUCCESS;
5463 struct i40e_rx_queue *rxq;
5465 i40e_pf_config_mq_rx(pf);
5466 for (i = 0; i < data->nb_rx_queues; i++) {
5467 rxq = data->rx_queues[i];
5468 if (!rxq || !rxq->q_set)
5471 ret = i40e_rx_queue_init(rxq);
5472 if (ret != I40E_SUCCESS) {
5474 "Failed to do RX queue initialization");
5478 if (ret == I40E_SUCCESS)
5479 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5486 i40e_dev_rxtx_init(struct i40e_pf *pf)
5490 err = i40e_dev_tx_init(pf);
5492 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5495 err = i40e_dev_rx_init(pf);
5497 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5505 i40e_vmdq_setup(struct rte_eth_dev *dev)
5507 struct rte_eth_conf *conf = &dev->data->dev_conf;
5508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5509 int i, err, conf_vsis, j, loop;
5510 struct i40e_vsi *vsi;
5511 struct i40e_vmdq_info *vmdq_info;
5512 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5513 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5516 * Disable interrupt to avoid message from VF. Furthermore, it will
5517 * avoid race condition in VSI creation/destroy.
5519 i40e_pf_disable_irq0(hw);
5521 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5522 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5526 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5527 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5528 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5529 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5530 pf->max_nb_vmdq_vsi);
5534 if (pf->vmdq != NULL) {
5535 PMD_INIT_LOG(INFO, "VMDQ already configured");
5539 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5540 sizeof(*vmdq_info) * conf_vsis, 0);
5542 if (pf->vmdq == NULL) {
5543 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5547 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5549 /* Create VMDQ VSI */
5550 for (i = 0; i < conf_vsis; i++) {
5551 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5552 vmdq_conf->enable_loop_back);
5554 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5558 vmdq_info = &pf->vmdq[i];
5560 vmdq_info->vsi = vsi;
5562 pf->nb_cfg_vmdq_vsi = conf_vsis;
5564 /* Configure Vlan */
5565 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5566 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5567 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5568 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5569 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5570 vmdq_conf->pool_map[i].vlan_id, j);
5572 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5573 vmdq_conf->pool_map[i].vlan_id);
5575 PMD_INIT_LOG(ERR, "Failed to add vlan");
5583 i40e_pf_enable_irq0(hw);
5588 for (i = 0; i < conf_vsis; i++)
5589 if (pf->vmdq[i].vsi == NULL)
5592 i40e_vsi_release(pf->vmdq[i].vsi);
5596 i40e_pf_enable_irq0(hw);
5601 i40e_stat_update_32(struct i40e_hw *hw,
5609 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5613 if (new_data >= *offset)
5614 *stat = (uint64_t)(new_data - *offset);
5616 *stat = (uint64_t)((new_data +
5617 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5621 i40e_stat_update_48(struct i40e_hw *hw,
5630 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5631 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5632 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5637 if (new_data >= *offset)
5638 *stat = new_data - *offset;
5640 *stat = (uint64_t)((new_data +
5641 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5643 *stat &= I40E_48_BIT_MASK;
5648 i40e_pf_disable_irq0(struct i40e_hw *hw)
5650 /* Disable all interrupt types */
5651 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5652 I40E_WRITE_FLUSH(hw);
5657 i40e_pf_enable_irq0(struct i40e_hw *hw)
5659 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5660 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5661 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5662 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5663 I40E_WRITE_FLUSH(hw);
5667 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5669 /* read pending request and disable first */
5670 i40e_pf_disable_irq0(hw);
5671 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5672 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5673 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5676 /* Link no queues with irq0 */
5677 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5678 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5682 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5685 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5688 uint32_t index, offset, val;
5693 * Try to find which VF trigger a reset, use absolute VF id to access
5694 * since the reg is global register.
5696 for (i = 0; i < pf->vf_num; i++) {
5697 abs_vf_id = hw->func_caps.vf_base_id + i;
5698 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5699 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5700 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5701 /* VFR event occured */
5702 if (val & (0x1 << offset)) {
5705 /* Clear the event first */
5706 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5708 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5710 * Only notify a VF reset event occured,
5711 * don't trigger another SW reset
5713 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5714 if (ret != I40E_SUCCESS)
5715 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5721 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5723 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5724 struct i40e_virtchnl_pf_event event;
5727 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5728 event.event_data.link_event.link_status =
5729 dev->data->dev_link.link_status;
5730 event.event_data.link_event.link_speed =
5731 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5733 for (i = 0; i < pf->vf_num; i++)
5734 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5735 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5739 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5741 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742 struct i40e_arq_event_info info;
5743 uint16_t pending, opcode;
5746 info.buf_len = I40E_AQ_BUF_SZ;
5747 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5748 if (!info.msg_buf) {
5749 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5755 ret = i40e_clean_arq_element(hw, &info, &pending);
5757 if (ret != I40E_SUCCESS) {
5759 "Failed to read msg from AdminQ, aq_err: %u",
5760 hw->aq.asq_last_status);
5763 opcode = rte_le_to_cpu_16(info.desc.opcode);
5766 case i40e_aqc_opc_send_msg_to_pf:
5767 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5768 i40e_pf_host_handle_vf_msg(dev,
5769 rte_le_to_cpu_16(info.desc.retval),
5770 rte_le_to_cpu_32(info.desc.cookie_high),
5771 rte_le_to_cpu_32(info.desc.cookie_low),
5775 case i40e_aqc_opc_get_link_status:
5776 ret = i40e_dev_link_update(dev, 0);
5778 i40e_notify_all_vfs_link_status(dev);
5779 _rte_eth_dev_callback_process(dev,
5780 RTE_ETH_EVENT_INTR_LSC, NULL);
5784 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5789 rte_free(info.msg_buf);
5793 * Interrupt handler triggered by NIC for handling
5794 * specific interrupt.
5797 * Pointer to interrupt handle.
5799 * The address of parameter (struct rte_eth_dev *) regsitered before.
5805 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5808 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5812 /* Disable interrupt */
5813 i40e_pf_disable_irq0(hw);
5815 /* read out interrupt causes */
5816 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5818 /* No interrupt event indicated */
5819 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5820 PMD_DRV_LOG(INFO, "No interrupt event");
5823 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5824 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5825 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5826 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5827 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5828 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5829 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5830 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5831 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5832 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5833 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5834 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5835 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5836 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5837 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5838 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5840 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5841 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5842 i40e_dev_handle_vfr_event(dev);
5844 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5845 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5846 i40e_dev_handle_aq_msg(dev);
5850 /* Enable interrupt */
5851 i40e_pf_enable_irq0(hw);
5852 rte_intr_enable(intr_handle);
5856 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5857 struct i40e_macvlan_filter *filter,
5860 int ele_num, ele_buff_size;
5861 int num, actual_num, i;
5863 int ret = I40E_SUCCESS;
5864 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5865 struct i40e_aqc_add_macvlan_element_data *req_list;
5867 if (filter == NULL || total == 0)
5868 return I40E_ERR_PARAM;
5869 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5870 ele_buff_size = hw->aq.asq_buf_size;
5872 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5873 if (req_list == NULL) {
5874 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5875 return I40E_ERR_NO_MEMORY;
5880 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5881 memset(req_list, 0, ele_buff_size);
5883 for (i = 0; i < actual_num; i++) {
5884 (void)rte_memcpy(req_list[i].mac_addr,
5885 &filter[num + i].macaddr, ETH_ADDR_LEN);
5886 req_list[i].vlan_tag =
5887 rte_cpu_to_le_16(filter[num + i].vlan_id);
5889 switch (filter[num + i].filter_type) {
5890 case RTE_MAC_PERFECT_MATCH:
5891 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5892 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5894 case RTE_MACVLAN_PERFECT_MATCH:
5895 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5897 case RTE_MAC_HASH_MATCH:
5898 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5899 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5901 case RTE_MACVLAN_HASH_MATCH:
5902 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5905 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5906 ret = I40E_ERR_PARAM;
5910 req_list[i].queue_number = 0;
5912 req_list[i].flags = rte_cpu_to_le_16(flags);
5915 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5917 if (ret != I40E_SUCCESS) {
5918 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5922 } while (num < total);
5930 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5931 struct i40e_macvlan_filter *filter,
5934 int ele_num, ele_buff_size;
5935 int num, actual_num, i;
5937 int ret = I40E_SUCCESS;
5938 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5939 struct i40e_aqc_remove_macvlan_element_data *req_list;
5941 if (filter == NULL || total == 0)
5942 return I40E_ERR_PARAM;
5944 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5945 ele_buff_size = hw->aq.asq_buf_size;
5947 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5948 if (req_list == NULL) {
5949 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5950 return I40E_ERR_NO_MEMORY;
5955 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5956 memset(req_list, 0, ele_buff_size);
5958 for (i = 0; i < actual_num; i++) {
5959 (void)rte_memcpy(req_list[i].mac_addr,
5960 &filter[num + i].macaddr, ETH_ADDR_LEN);
5961 req_list[i].vlan_tag =
5962 rte_cpu_to_le_16(filter[num + i].vlan_id);
5964 switch (filter[num + i].filter_type) {
5965 case RTE_MAC_PERFECT_MATCH:
5966 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5967 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5969 case RTE_MACVLAN_PERFECT_MATCH:
5970 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5972 case RTE_MAC_HASH_MATCH:
5973 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5974 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5976 case RTE_MACVLAN_HASH_MATCH:
5977 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5980 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5981 ret = I40E_ERR_PARAM;
5984 req_list[i].flags = rte_cpu_to_le_16(flags);
5987 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5989 if (ret != I40E_SUCCESS) {
5990 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5994 } while (num < total);
6001 /* Find out specific MAC filter */
6002 static struct i40e_mac_filter *
6003 i40e_find_mac_filter(struct i40e_vsi *vsi,
6004 struct ether_addr *macaddr)
6006 struct i40e_mac_filter *f;
6008 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6009 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6017 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6020 uint32_t vid_idx, vid_bit;
6022 if (vlan_id > ETH_VLAN_ID_MAX)
6025 vid_idx = I40E_VFTA_IDX(vlan_id);
6026 vid_bit = I40E_VFTA_BIT(vlan_id);
6028 if (vsi->vfta[vid_idx] & vid_bit)
6035 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6036 uint16_t vlan_id, bool on)
6038 uint32_t vid_idx, vid_bit;
6040 vid_idx = I40E_VFTA_IDX(vlan_id);
6041 vid_bit = I40E_VFTA_BIT(vlan_id);
6044 vsi->vfta[vid_idx] |= vid_bit;
6046 vsi->vfta[vid_idx] &= ~vid_bit;
6050 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6051 uint16_t vlan_id, bool on)
6053 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6054 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6057 if (vlan_id > ETH_VLAN_ID_MAX)
6060 i40e_store_vlan_filter(vsi, vlan_id, on);
6062 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6065 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6068 ret = i40e_aq_add_vlan(hw, vsi->seid,
6069 &vlan_data, 1, NULL);
6070 if (ret != I40E_SUCCESS)
6071 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6073 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6074 &vlan_data, 1, NULL);
6075 if (ret != I40E_SUCCESS)
6077 "Failed to remove vlan filter");
6082 * Find all vlan options for specific mac addr,
6083 * return with actual vlan found.
6086 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6087 struct i40e_macvlan_filter *mv_f,
6088 int num, struct ether_addr *addr)
6094 * Not to use i40e_find_vlan_filter to decrease the loop time,
6095 * although the code looks complex.
6097 if (num < vsi->vlan_num)
6098 return I40E_ERR_PARAM;
6101 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6103 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6104 if (vsi->vfta[j] & (1 << k)) {
6107 "vlan number doesn't match");
6108 return I40E_ERR_PARAM;
6110 (void)rte_memcpy(&mv_f[i].macaddr,
6111 addr, ETH_ADDR_LEN);
6113 j * I40E_UINT32_BIT_SIZE + k;
6119 return I40E_SUCCESS;
6123 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6124 struct i40e_macvlan_filter *mv_f,
6129 struct i40e_mac_filter *f;
6131 if (num < vsi->mac_num)
6132 return I40E_ERR_PARAM;
6134 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6136 PMD_DRV_LOG(ERR, "buffer number not match");
6137 return I40E_ERR_PARAM;
6139 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6141 mv_f[i].vlan_id = vlan;
6142 mv_f[i].filter_type = f->mac_info.filter_type;
6146 return I40E_SUCCESS;
6150 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6153 struct i40e_mac_filter *f;
6154 struct i40e_macvlan_filter *mv_f;
6155 int ret = I40E_SUCCESS;
6157 if (vsi == NULL || vsi->mac_num == 0)
6158 return I40E_ERR_PARAM;
6160 /* Case that no vlan is set */
6161 if (vsi->vlan_num == 0)
6164 num = vsi->mac_num * vsi->vlan_num;
6166 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6168 PMD_DRV_LOG(ERR, "failed to allocate memory");
6169 return I40E_ERR_NO_MEMORY;
6173 if (vsi->vlan_num == 0) {
6174 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6175 (void)rte_memcpy(&mv_f[i].macaddr,
6176 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6177 mv_f[i].filter_type = f->mac_info.filter_type;
6178 mv_f[i].vlan_id = 0;
6182 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6183 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6184 vsi->vlan_num, &f->mac_info.mac_addr);
6185 if (ret != I40E_SUCCESS)
6187 for (j = i; j < i + vsi->vlan_num; j++)
6188 mv_f[j].filter_type = f->mac_info.filter_type;
6193 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6201 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6203 struct i40e_macvlan_filter *mv_f;
6205 int ret = I40E_SUCCESS;
6207 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6208 return I40E_ERR_PARAM;
6210 /* If it's already set, just return */
6211 if (i40e_find_vlan_filter(vsi,vlan))
6212 return I40E_SUCCESS;
6214 mac_num = vsi->mac_num;
6217 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6218 return I40E_ERR_PARAM;
6221 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6224 PMD_DRV_LOG(ERR, "failed to allocate memory");
6225 return I40E_ERR_NO_MEMORY;
6228 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6230 if (ret != I40E_SUCCESS)
6233 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6235 if (ret != I40E_SUCCESS)
6238 i40e_set_vlan_filter(vsi, vlan, 1);
6248 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6250 struct i40e_macvlan_filter *mv_f;
6252 int ret = I40E_SUCCESS;
6255 * Vlan 0 is the generic filter for untagged packets
6256 * and can't be removed.
6258 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6259 return I40E_ERR_PARAM;
6261 /* If can't find it, just return */
6262 if (!i40e_find_vlan_filter(vsi, vlan))
6263 return I40E_ERR_PARAM;
6265 mac_num = vsi->mac_num;
6268 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6269 return I40E_ERR_PARAM;
6272 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6275 PMD_DRV_LOG(ERR, "failed to allocate memory");
6276 return I40E_ERR_NO_MEMORY;
6279 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6281 if (ret != I40E_SUCCESS)
6284 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6286 if (ret != I40E_SUCCESS)
6289 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6290 if (vsi->vlan_num == 1) {
6291 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6292 if (ret != I40E_SUCCESS)
6295 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6296 if (ret != I40E_SUCCESS)
6300 i40e_set_vlan_filter(vsi, vlan, 0);
6310 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6312 struct i40e_mac_filter *f;
6313 struct i40e_macvlan_filter *mv_f;
6314 int i, vlan_num = 0;
6315 int ret = I40E_SUCCESS;
6317 /* If it's add and we've config it, return */
6318 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6320 return I40E_SUCCESS;
6321 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6322 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6325 * If vlan_num is 0, that's the first time to add mac,
6326 * set mask for vlan_id 0.
6328 if (vsi->vlan_num == 0) {
6329 i40e_set_vlan_filter(vsi, 0, 1);
6332 vlan_num = vsi->vlan_num;
6333 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6334 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6337 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6339 PMD_DRV_LOG(ERR, "failed to allocate memory");
6340 return I40E_ERR_NO_MEMORY;
6343 for (i = 0; i < vlan_num; i++) {
6344 mv_f[i].filter_type = mac_filter->filter_type;
6345 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6349 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6350 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6351 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6352 &mac_filter->mac_addr);
6353 if (ret != I40E_SUCCESS)
6357 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6358 if (ret != I40E_SUCCESS)
6361 /* Add the mac addr into mac list */
6362 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6364 PMD_DRV_LOG(ERR, "failed to allocate memory");
6365 ret = I40E_ERR_NO_MEMORY;
6368 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6370 f->mac_info.filter_type = mac_filter->filter_type;
6371 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6382 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6384 struct i40e_mac_filter *f;
6385 struct i40e_macvlan_filter *mv_f;
6387 enum rte_mac_filter_type filter_type;
6388 int ret = I40E_SUCCESS;
6390 /* Can't find it, return an error */
6391 f = i40e_find_mac_filter(vsi, addr);
6393 return I40E_ERR_PARAM;
6395 vlan_num = vsi->vlan_num;
6396 filter_type = f->mac_info.filter_type;
6397 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6398 filter_type == RTE_MACVLAN_HASH_MATCH) {
6399 if (vlan_num == 0) {
6400 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6401 return I40E_ERR_PARAM;
6403 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6404 filter_type == RTE_MAC_HASH_MATCH)
6407 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6409 PMD_DRV_LOG(ERR, "failed to allocate memory");
6410 return I40E_ERR_NO_MEMORY;
6413 for (i = 0; i < vlan_num; i++) {
6414 mv_f[i].filter_type = filter_type;
6415 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6418 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6419 filter_type == RTE_MACVLAN_HASH_MATCH) {
6420 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6421 if (ret != I40E_SUCCESS)
6425 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6426 if (ret != I40E_SUCCESS)
6429 /* Remove the mac addr into mac list */
6430 TAILQ_REMOVE(&vsi->mac_list, f, next);
6440 /* Configure hash enable flags for RSS */
6442 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6449 if (flags & ETH_RSS_FRAG_IPV4)
6450 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6451 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6452 if (type == I40E_MAC_X722) {
6453 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6454 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6456 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6458 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6459 if (type == I40E_MAC_X722) {
6460 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6461 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6462 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6464 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6466 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6467 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6468 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6469 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6470 if (flags & ETH_RSS_FRAG_IPV6)
6471 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6472 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6473 if (type == I40E_MAC_X722) {
6474 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6475 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6477 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6479 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6480 if (type == I40E_MAC_X722) {
6481 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6482 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6483 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6485 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6487 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6488 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6489 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6490 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6491 if (flags & ETH_RSS_L2_PAYLOAD)
6492 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6497 /* Parse the hash enable flags */
6499 i40e_parse_hena(uint64_t flags)
6501 uint64_t rss_hf = 0;
6505 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6506 rss_hf |= ETH_RSS_FRAG_IPV4;
6507 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6508 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6509 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6510 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6511 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6512 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6513 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6514 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6515 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6516 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6518 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6519 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6520 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6521 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6522 rss_hf |= ETH_RSS_FRAG_IPV6;
6523 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6524 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6525 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6526 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6527 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6528 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6529 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6530 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6531 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6532 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6533 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6534 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6535 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6536 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6537 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6538 rss_hf |= ETH_RSS_L2_PAYLOAD;
6545 i40e_pf_disable_rss(struct i40e_pf *pf)
6547 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6550 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6551 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6552 if (hw->mac.type == I40E_MAC_X722)
6553 hena &= ~I40E_RSS_HENA_ALL_X722;
6555 hena &= ~I40E_RSS_HENA_ALL;
6556 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6557 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6558 I40E_WRITE_FLUSH(hw);
6562 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6564 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6565 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6568 if (!key || key_len == 0) {
6569 PMD_DRV_LOG(DEBUG, "No key to be configured");
6571 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6573 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6577 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6578 struct i40e_aqc_get_set_rss_key_data *key_dw =
6579 (struct i40e_aqc_get_set_rss_key_data *)key;
6581 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6583 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6585 uint32_t *hash_key = (uint32_t *)key;
6588 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6589 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6590 I40E_WRITE_FLUSH(hw);
6597 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6599 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6600 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6603 if (!key || !key_len)
6606 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6607 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6608 (struct i40e_aqc_get_set_rss_key_data *)key);
6610 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6614 uint32_t *key_dw = (uint32_t *)key;
6617 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6618 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6620 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6626 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6628 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6633 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6634 rss_conf->rss_key_len);
6638 rss_hf = rss_conf->rss_hf;
6639 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6640 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6641 if (hw->mac.type == I40E_MAC_X722)
6642 hena &= ~I40E_RSS_HENA_ALL_X722;
6644 hena &= ~I40E_RSS_HENA_ALL;
6645 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6646 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6647 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6648 I40E_WRITE_FLUSH(hw);
6654 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6655 struct rte_eth_rss_conf *rss_conf)
6657 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6659 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6662 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6663 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6664 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6665 ? I40E_RSS_HENA_ALL_X722
6666 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6667 if (rss_hf != 0) /* Enable RSS */
6669 return 0; /* Nothing to do */
6672 if (rss_hf == 0) /* Disable RSS */
6675 return i40e_hw_rss_hash_set(pf, rss_conf);
6679 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6680 struct rte_eth_rss_conf *rss_conf)
6682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6686 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6687 &rss_conf->rss_key_len);
6689 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6690 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6691 rss_conf->rss_hf = i40e_parse_hena(hena);
6697 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6699 switch (filter_type) {
6700 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6701 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6703 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6704 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6706 case RTE_TUNNEL_FILTER_IMAC_TENID:
6707 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6709 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6710 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6712 case ETH_TUNNEL_FILTER_IMAC:
6713 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6715 case ETH_TUNNEL_FILTER_OIP:
6716 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6718 case ETH_TUNNEL_FILTER_IIP:
6719 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6722 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6729 /* Convert tunnel filter structure */
6731 i40e_tunnel_filter_convert(
6732 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6733 struct i40e_tunnel_filter *tunnel_filter)
6735 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6736 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6737 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6738 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6739 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6740 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6741 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6742 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6743 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6745 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6746 tunnel_filter->input.flags = cld_filter->element.flags;
6747 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6748 tunnel_filter->queue = cld_filter->element.queue_number;
6749 rte_memcpy(tunnel_filter->input.general_fields,
6750 cld_filter->general_fields,
6751 sizeof(cld_filter->general_fields));
6756 /* Check if there exists the tunnel filter */
6757 struct i40e_tunnel_filter *
6758 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6759 const struct i40e_tunnel_filter_input *input)
6763 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6767 return tunnel_rule->hash_map[ret];
6770 /* Add a tunnel filter into the SW list */
6772 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6773 struct i40e_tunnel_filter *tunnel_filter)
6775 struct i40e_tunnel_rule *rule = &pf->tunnel;
6778 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6781 "Failed to insert tunnel filter to hash table %d!",
6785 rule->hash_map[ret] = tunnel_filter;
6787 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6792 /* Delete a tunnel filter from the SW list */
6794 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6795 struct i40e_tunnel_filter_input *input)
6797 struct i40e_tunnel_rule *rule = &pf->tunnel;
6798 struct i40e_tunnel_filter *tunnel_filter;
6801 ret = rte_hash_del_key(rule->hash_table, input);
6804 "Failed to delete tunnel filter to hash table %d!",
6808 tunnel_filter = rule->hash_map[ret];
6809 rule->hash_map[ret] = NULL;
6811 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6812 rte_free(tunnel_filter);
6818 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6819 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6824 uint8_t i, tun_type = 0;
6825 /* internal varialbe to convert ipv6 byte order */
6826 uint32_t convert_ipv6[4];
6828 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6829 struct i40e_vsi *vsi = pf->main_vsi;
6830 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6831 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6832 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6833 struct i40e_tunnel_filter *tunnel, *node;
6834 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6836 cld_filter = rte_zmalloc("tunnel_filter",
6837 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6840 if (NULL == cld_filter) {
6841 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6844 pfilter = cld_filter;
6846 ether_addr_copy(&tunnel_filter->outer_mac,
6847 (struct ether_addr *)&pfilter->element.outer_mac);
6848 ether_addr_copy(&tunnel_filter->inner_mac,
6849 (struct ether_addr *)&pfilter->element.inner_mac);
6851 pfilter->element.inner_vlan =
6852 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6853 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6854 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6855 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6856 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6857 &rte_cpu_to_le_32(ipv4_addr),
6858 sizeof(pfilter->element.ipaddr.v4.data));
6860 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6861 for (i = 0; i < 4; i++) {
6863 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6865 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6867 sizeof(pfilter->element.ipaddr.v6.data));
6870 /* check tunneled type */
6871 switch (tunnel_filter->tunnel_type) {
6872 case RTE_TUNNEL_TYPE_VXLAN:
6873 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6875 case RTE_TUNNEL_TYPE_NVGRE:
6876 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6878 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6879 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6882 /* Other tunnel types is not supported. */
6883 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6884 rte_free(cld_filter);
6888 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6889 &pfilter->element.flags);
6891 rte_free(cld_filter);
6895 pfilter->element.flags |= rte_cpu_to_le_16(
6896 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6897 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6898 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6899 pfilter->element.queue_number =
6900 rte_cpu_to_le_16(tunnel_filter->queue_id);
6902 /* Check if there is the filter in SW list */
6903 memset(&check_filter, 0, sizeof(check_filter));
6904 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6905 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6907 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6911 if (!add && !node) {
6912 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6917 ret = i40e_aq_add_cloud_filters(hw,
6918 vsi->seid, &cld_filter->element, 1);
6920 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6923 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6924 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6925 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6927 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6928 &cld_filter->element, 1);
6930 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6933 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6936 rte_free(cld_filter);
6940 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6941 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6942 #define I40E_TR_GENEVE_KEY_MASK 0x8
6943 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6944 #define I40E_TR_GRE_KEY_MASK 0x400
6945 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6946 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6949 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6951 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6952 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6953 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6954 enum i40e_status_code status = I40E_SUCCESS;
6956 memset(&filter_replace, 0,
6957 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6958 memset(&filter_replace_buf, 0,
6959 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6961 /* create L1 filter */
6962 filter_replace.old_filter_type =
6963 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6964 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6965 filter_replace.tr_bit = 0;
6967 /* Prepare the buffer, 3 entries */
6968 filter_replace_buf.data[0] =
6969 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6970 filter_replace_buf.data[0] |=
6971 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6972 filter_replace_buf.data[2] = 0xFF;
6973 filter_replace_buf.data[3] = 0xFF;
6974 filter_replace_buf.data[4] =
6975 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6976 filter_replace_buf.data[4] |=
6977 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6978 filter_replace_buf.data[7] = 0xF0;
6979 filter_replace_buf.data[8]
6980 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6981 filter_replace_buf.data[8] |=
6982 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6983 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6984 I40E_TR_GENEVE_KEY_MASK |
6985 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6986 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6987 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6988 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6990 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
6991 &filter_replace_buf);
6996 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
6998 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6999 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7000 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7001 enum i40e_status_code status = I40E_SUCCESS;
7004 memset(&filter_replace, 0,
7005 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7006 memset(&filter_replace_buf, 0,
7007 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7008 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7009 I40E_AQC_MIRROR_CLOUD_FILTER;
7010 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7011 filter_replace.new_filter_type =
7012 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7013 /* Prepare the buffer, 2 entries */
7014 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7015 filter_replace_buf.data[0] |=
7016 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7017 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7018 filter_replace_buf.data[4] |=
7019 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7020 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7021 &filter_replace_buf);
7026 memset(&filter_replace, 0,
7027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7028 memset(&filter_replace_buf, 0,
7029 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7031 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7032 I40E_AQC_MIRROR_CLOUD_FILTER;
7033 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7034 filter_replace.new_filter_type =
7035 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7036 /* Prepare the buffer, 2 entries */
7037 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7038 filter_replace_buf.data[0] |=
7039 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7040 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7041 filter_replace_buf.data[4] |=
7042 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7044 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7045 &filter_replace_buf);
7050 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7051 struct i40e_tunnel_filter_conf *tunnel_filter,
7056 uint8_t i, tun_type = 0;
7057 /* internal variable to convert ipv6 byte order */
7058 uint32_t convert_ipv6[4];
7060 struct i40e_pf_vf *vf = NULL;
7061 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7062 struct i40e_vsi *vsi;
7063 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7064 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7065 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7066 struct i40e_tunnel_filter *tunnel, *node;
7067 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7069 bool big_buffer = 0;
7071 cld_filter = rte_zmalloc("tunnel_filter",
7072 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7075 if (cld_filter == NULL) {
7076 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7079 pfilter = cld_filter;
7081 ether_addr_copy(&tunnel_filter->outer_mac,
7082 (struct ether_addr *)&pfilter->element.outer_mac);
7083 ether_addr_copy(&tunnel_filter->inner_mac,
7084 (struct ether_addr *)&pfilter->element.inner_mac);
7086 pfilter->element.inner_vlan =
7087 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7088 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7089 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7090 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7091 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7092 &rte_cpu_to_le_32(ipv4_addr),
7093 sizeof(pfilter->element.ipaddr.v4.data));
7095 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7096 for (i = 0; i < 4; i++) {
7098 rte_cpu_to_le_32(rte_be_to_cpu_32(
7099 tunnel_filter->ip_addr.ipv6_addr[i]));
7101 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7103 sizeof(pfilter->element.ipaddr.v6.data));
7106 /* check tunneled type */
7107 switch (tunnel_filter->tunnel_type) {
7108 case I40E_TUNNEL_TYPE_VXLAN:
7109 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7111 case I40E_TUNNEL_TYPE_NVGRE:
7112 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7114 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7115 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7117 case I40E_TUNNEL_TYPE_MPLSoUDP:
7118 if (!pf->mpls_replace_flag) {
7119 i40e_replace_mpls_l1_filter(pf);
7120 i40e_replace_mpls_cloud_filter(pf);
7121 pf->mpls_replace_flag = 1;
7123 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7124 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7126 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7127 (teid_le & 0xF) << 12;
7128 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7131 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7133 case I40E_TUNNEL_TYPE_MPLSoGRE:
7134 if (!pf->mpls_replace_flag) {
7135 i40e_replace_mpls_l1_filter(pf);
7136 i40e_replace_mpls_cloud_filter(pf);
7137 pf->mpls_replace_flag = 1;
7139 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7140 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7142 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7143 (teid_le & 0xF) << 12;
7144 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7147 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7150 /* Other tunnel types is not supported. */
7151 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7152 rte_free(cld_filter);
7156 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7157 pfilter->element.flags =
7158 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7159 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7160 pfilter->element.flags =
7161 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7163 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7164 &pfilter->element.flags);
7166 rte_free(cld_filter);
7171 pfilter->element.flags |= rte_cpu_to_le_16(
7172 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7173 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7174 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7175 pfilter->element.queue_number =
7176 rte_cpu_to_le_16(tunnel_filter->queue_id);
7178 if (!tunnel_filter->is_to_vf)
7181 if (tunnel_filter->vf_id >= pf->vf_num) {
7182 PMD_DRV_LOG(ERR, "Invalid argument.");
7185 vf = &pf->vfs[tunnel_filter->vf_id];
7189 /* Check if there is the filter in SW list */
7190 memset(&check_filter, 0, sizeof(check_filter));
7191 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7192 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7194 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7198 if (!add && !node) {
7199 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7205 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7206 vsi->seid, cld_filter, 1);
7208 ret = i40e_aq_add_cloud_filters(hw,
7209 vsi->seid, &cld_filter->element, 1);
7211 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7214 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7215 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7216 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7219 ret = i40e_aq_remove_cloud_filters_big_buffer(
7220 hw, vsi->seid, cld_filter, 1);
7222 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7223 &cld_filter->element, 1);
7225 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7228 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7231 rte_free(cld_filter);
7236 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7240 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7241 if (pf->vxlan_ports[i] == port)
7249 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7253 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7255 idx = i40e_get_vxlan_port_idx(pf, port);
7257 /* Check if port already exists */
7259 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7263 /* Now check if there is space to add the new port */
7264 idx = i40e_get_vxlan_port_idx(pf, 0);
7267 "Maximum number of UDP ports reached, not adding port %d",
7272 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7275 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7279 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7282 /* New port: add it and mark its index in the bitmap */
7283 pf->vxlan_ports[idx] = port;
7284 pf->vxlan_bitmap |= (1 << idx);
7286 if (!(pf->flags & I40E_FLAG_VXLAN))
7287 pf->flags |= I40E_FLAG_VXLAN;
7293 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7296 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7298 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7299 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7303 idx = i40e_get_vxlan_port_idx(pf, port);
7306 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7310 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7311 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7315 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7318 pf->vxlan_ports[idx] = 0;
7319 pf->vxlan_bitmap &= ~(1 << idx);
7321 if (!pf->vxlan_bitmap)
7322 pf->flags &= ~I40E_FLAG_VXLAN;
7327 /* Add UDP tunneling port */
7329 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7330 struct rte_eth_udp_tunnel *udp_tunnel)
7333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7335 if (udp_tunnel == NULL)
7338 switch (udp_tunnel->prot_type) {
7339 case RTE_TUNNEL_TYPE_VXLAN:
7340 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7343 case RTE_TUNNEL_TYPE_GENEVE:
7344 case RTE_TUNNEL_TYPE_TEREDO:
7345 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7350 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7358 /* Remove UDP tunneling port */
7360 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7361 struct rte_eth_udp_tunnel *udp_tunnel)
7364 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7366 if (udp_tunnel == NULL)
7369 switch (udp_tunnel->prot_type) {
7370 case RTE_TUNNEL_TYPE_VXLAN:
7371 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7373 case RTE_TUNNEL_TYPE_GENEVE:
7374 case RTE_TUNNEL_TYPE_TEREDO:
7375 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7379 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7387 /* Calculate the maximum number of contiguous PF queues that are configured */
7389 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7391 struct rte_eth_dev_data *data = pf->dev_data;
7393 struct i40e_rx_queue *rxq;
7396 for (i = 0; i < pf->lan_nb_qps; i++) {
7397 rxq = data->rx_queues[i];
7398 if (rxq && rxq->q_set)
7409 i40e_pf_config_rss(struct i40e_pf *pf)
7411 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7412 struct rte_eth_rss_conf rss_conf;
7413 uint32_t i, lut = 0;
7417 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7418 * It's necessary to calulate the actual PF queues that are configured.
7420 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7421 num = i40e_pf_calc_configured_queues_num(pf);
7423 num = pf->dev_data->nb_rx_queues;
7425 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7426 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7430 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7434 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7437 lut = (lut << 8) | (j & ((0x1 <<
7438 hw->func_caps.rss_table_entry_width) - 1));
7440 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7443 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7444 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7445 i40e_pf_disable_rss(pf);
7448 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7449 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7450 /* Random default keys */
7451 static uint32_t rss_key_default[] = {0x6b793944,
7452 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7453 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7454 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7456 rss_conf.rss_key = (uint8_t *)rss_key_default;
7457 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7461 return i40e_hw_rss_hash_set(pf, &rss_conf);
7465 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7466 struct rte_eth_tunnel_filter_conf *filter)
7468 if (pf == NULL || filter == NULL) {
7469 PMD_DRV_LOG(ERR, "Invalid parameter");
7473 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7474 PMD_DRV_LOG(ERR, "Invalid queue ID");
7478 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7479 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7483 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7484 (is_zero_ether_addr(&filter->outer_mac))) {
7485 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7489 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7490 (is_zero_ether_addr(&filter->inner_mac))) {
7491 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7498 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7499 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7501 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7506 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7507 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7510 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7511 } else if (len == 4) {
7512 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7514 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7519 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7526 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7527 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7533 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7540 switch (cfg->cfg_type) {
7541 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7542 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7545 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7553 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7554 enum rte_filter_op filter_op,
7557 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7558 int ret = I40E_ERR_PARAM;
7560 switch (filter_op) {
7561 case RTE_ETH_FILTER_SET:
7562 ret = i40e_dev_global_config_set(hw,
7563 (struct rte_eth_global_cfg *)arg);
7566 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7574 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7575 enum rte_filter_op filter_op,
7578 struct rte_eth_tunnel_filter_conf *filter;
7579 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7580 int ret = I40E_SUCCESS;
7582 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7584 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7585 return I40E_ERR_PARAM;
7587 switch (filter_op) {
7588 case RTE_ETH_FILTER_NOP:
7589 if (!(pf->flags & I40E_FLAG_VXLAN))
7590 ret = I40E_NOT_SUPPORTED;
7592 case RTE_ETH_FILTER_ADD:
7593 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7595 case RTE_ETH_FILTER_DELETE:
7596 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7599 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7600 ret = I40E_ERR_PARAM;
7608 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7611 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7614 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7615 ret = i40e_pf_config_rss(pf);
7617 i40e_pf_disable_rss(pf);
7622 /* Get the symmetric hash enable configurations per port */
7624 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7626 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7628 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7631 /* Set the symmetric hash enable configurations per port */
7633 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7635 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7638 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7640 "Symmetric hash has already been enabled");
7643 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7645 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7647 "Symmetric hash has already been disabled");
7650 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7652 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7653 I40E_WRITE_FLUSH(hw);
7657 * Get global configurations of hash function type and symmetric hash enable
7658 * per flow type (pctype). Note that global configuration means it affects all
7659 * the ports on the same NIC.
7662 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7663 struct rte_eth_hash_global_conf *g_cfg)
7665 uint32_t reg, mask = I40E_FLOW_TYPES;
7667 enum i40e_filter_pctype pctype;
7669 memset(g_cfg, 0, sizeof(*g_cfg));
7670 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7671 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7672 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7674 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7675 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7676 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7678 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7679 if (!(mask & (1UL << i)))
7681 mask &= ~(1UL << i);
7682 /* Bit set indicats the coresponding flow type is supported */
7683 g_cfg->valid_bit_mask[0] |= (1UL << i);
7684 /* if flowtype is invalid, continue */
7685 if (!I40E_VALID_FLOW(i))
7687 pctype = i40e_flowtype_to_pctype(i);
7688 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7689 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7690 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7697 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7700 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7702 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7703 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7704 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7705 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7711 * As i40e supports less than 32 flow types, only first 32 bits need to
7714 mask0 = g_cfg->valid_bit_mask[0];
7715 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7717 /* Check if any unsupported flow type configured */
7718 if ((mask0 | i40e_mask) ^ i40e_mask)
7721 if (g_cfg->valid_bit_mask[i])
7729 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7735 * Set global configurations of hash function type and symmetric hash enable
7736 * per flow type (pctype). Note any modifying global configuration will affect
7737 * all the ports on the same NIC.
7740 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7741 struct rte_eth_hash_global_conf *g_cfg)
7746 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7747 enum i40e_filter_pctype pctype;
7749 /* Check the input parameters */
7750 ret = i40e_hash_global_config_check(g_cfg);
7754 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7755 if (!(mask0 & (1UL << i)))
7757 mask0 &= ~(1UL << i);
7758 /* if flowtype is invalid, continue */
7759 if (!I40E_VALID_FLOW(i))
7761 pctype = i40e_flowtype_to_pctype(i);
7762 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7763 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7764 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7767 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7768 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7770 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7772 "Hash function already set to Toeplitz");
7775 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7776 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7778 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7780 "Hash function already set to Simple XOR");
7783 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7785 /* Use the default, and keep it as it is */
7788 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7791 I40E_WRITE_FLUSH(hw);
7797 * Valid input sets for hash and flow director filters per PCTYPE
7800 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7801 enum rte_filter_type filter)
7805 static const uint64_t valid_hash_inset_table[] = {
7806 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7807 I40E_INSET_DMAC | I40E_INSET_SMAC |
7808 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7809 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7810 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7811 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7812 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7813 I40E_INSET_FLEX_PAYLOAD,
7814 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7815 I40E_INSET_DMAC | I40E_INSET_SMAC |
7816 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7817 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7818 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7819 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7820 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7821 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7822 I40E_INSET_FLEX_PAYLOAD,
7823 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7824 I40E_INSET_DMAC | I40E_INSET_SMAC |
7825 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7826 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7827 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7828 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7829 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7830 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7831 I40E_INSET_FLEX_PAYLOAD,
7832 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7833 I40E_INSET_DMAC | I40E_INSET_SMAC |
7834 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7835 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7836 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7837 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7838 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7839 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7840 I40E_INSET_FLEX_PAYLOAD,
7841 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7842 I40E_INSET_DMAC | I40E_INSET_SMAC |
7843 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7844 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7845 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7846 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7847 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7848 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7849 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7850 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7851 I40E_INSET_DMAC | I40E_INSET_SMAC |
7852 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7853 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7854 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7855 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7856 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7857 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7858 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7859 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7860 I40E_INSET_DMAC | I40E_INSET_SMAC |
7861 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7862 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7863 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7864 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7865 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7866 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7867 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7868 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7869 I40E_INSET_DMAC | I40E_INSET_SMAC |
7870 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7871 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7872 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7873 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7874 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7875 I40E_INSET_FLEX_PAYLOAD,
7876 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7877 I40E_INSET_DMAC | I40E_INSET_SMAC |
7878 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7879 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7880 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7881 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7882 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7883 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7884 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7885 I40E_INSET_DMAC | I40E_INSET_SMAC |
7886 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7887 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7888 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7889 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7890 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7891 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7892 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7893 I40E_INSET_DMAC | I40E_INSET_SMAC |
7894 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7895 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7896 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7897 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7898 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7899 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7900 I40E_INSET_FLEX_PAYLOAD,
7901 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7902 I40E_INSET_DMAC | I40E_INSET_SMAC |
7903 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7904 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7905 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7906 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7907 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7908 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7909 I40E_INSET_FLEX_PAYLOAD,
7910 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7911 I40E_INSET_DMAC | I40E_INSET_SMAC |
7912 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7913 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7914 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7915 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7916 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7917 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7918 I40E_INSET_FLEX_PAYLOAD,
7919 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7920 I40E_INSET_DMAC | I40E_INSET_SMAC |
7921 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7922 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7923 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7924 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7925 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7926 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7927 I40E_INSET_FLEX_PAYLOAD,
7928 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7929 I40E_INSET_DMAC | I40E_INSET_SMAC |
7930 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7931 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7932 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7933 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7934 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7935 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7936 I40E_INSET_FLEX_PAYLOAD,
7937 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7938 I40E_INSET_DMAC | I40E_INSET_SMAC |
7939 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7940 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7941 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7942 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7943 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7944 I40E_INSET_FLEX_PAYLOAD,
7945 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7946 I40E_INSET_DMAC | I40E_INSET_SMAC |
7947 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7948 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7949 I40E_INSET_FLEX_PAYLOAD,
7953 * Flow director supports only fields defined in
7954 * union rte_eth_fdir_flow.
7956 static const uint64_t valid_fdir_inset_table[] = {
7957 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7958 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7959 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7960 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7961 I40E_INSET_IPV4_TTL,
7962 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7963 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7964 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7965 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7966 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7967 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7968 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7969 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7970 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7971 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7972 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7973 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7974 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7975 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7976 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7977 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7978 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7979 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7980 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7981 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7982 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7983 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7984 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7985 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7986 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7987 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7988 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7989 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7990 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7991 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7993 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7994 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7995 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7996 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7997 I40E_INSET_IPV4_TTL,
7998 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7999 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8000 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8001 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8002 I40E_INSET_IPV6_HOP_LIMIT,
8003 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8004 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8005 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8006 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8007 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8008 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8009 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8010 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8011 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8012 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8013 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8014 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8015 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8016 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8017 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8018 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8019 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8020 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8021 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8022 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8023 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8024 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8025 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8026 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8027 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8028 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8031 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8032 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8034 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8036 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8037 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8038 I40E_INSET_IPV6_HOP_LIMIT,
8039 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8040 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8041 I40E_INSET_LAST_ETHER_TYPE,
8044 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8046 if (filter == RTE_ETH_FILTER_HASH)
8047 valid = valid_hash_inset_table[pctype];
8049 valid = valid_fdir_inset_table[pctype];
8055 * Validate if the input set is allowed for a specific PCTYPE
8058 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8059 enum rte_filter_type filter, uint64_t inset)
8063 valid = i40e_get_valid_input_set(pctype, filter);
8064 if (inset & (~valid))
8070 /* default input set fields combination per pctype */
8072 i40e_get_default_input_set(uint16_t pctype)
8074 static const uint64_t default_inset_table[] = {
8075 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8076 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8077 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8078 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8079 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8080 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8081 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8082 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8083 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8084 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8085 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8086 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8087 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8088 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8089 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8090 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8091 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8092 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8093 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8094 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8096 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8097 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8098 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8099 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8100 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8101 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8102 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8103 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8104 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8105 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8106 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8107 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8108 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8109 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8110 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8111 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8112 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8113 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8115 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8116 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8117 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8119 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8120 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8121 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8122 I40E_INSET_LAST_ETHER_TYPE,
8125 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8128 return default_inset_table[pctype];
8132 * Parse the input set from index to logical bit masks
8135 i40e_parse_input_set(uint64_t *inset,
8136 enum i40e_filter_pctype pctype,
8137 enum rte_eth_input_set_field *field,
8143 static const struct {
8144 enum rte_eth_input_set_field field;
8146 } inset_convert_table[] = {
8147 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8148 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8149 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8150 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8151 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8152 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8153 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8154 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8155 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8156 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8157 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8158 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8159 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8160 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8161 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8162 I40E_INSET_IPV6_NEXT_HDR},
8163 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8164 I40E_INSET_IPV6_HOP_LIMIT},
8165 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8166 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8167 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8168 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8169 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8170 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8171 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8172 I40E_INSET_SCTP_VT},
8173 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8174 I40E_INSET_TUNNEL_DMAC},
8175 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8176 I40E_INSET_VLAN_TUNNEL},
8177 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8178 I40E_INSET_TUNNEL_ID},
8179 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8180 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8181 I40E_INSET_FLEX_PAYLOAD_W1},
8182 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8183 I40E_INSET_FLEX_PAYLOAD_W2},
8184 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8185 I40E_INSET_FLEX_PAYLOAD_W3},
8186 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8187 I40E_INSET_FLEX_PAYLOAD_W4},
8188 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8189 I40E_INSET_FLEX_PAYLOAD_W5},
8190 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8191 I40E_INSET_FLEX_PAYLOAD_W6},
8192 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8193 I40E_INSET_FLEX_PAYLOAD_W7},
8194 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8195 I40E_INSET_FLEX_PAYLOAD_W8},
8198 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8201 /* Only one item allowed for default or all */
8203 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8204 *inset = i40e_get_default_input_set(pctype);
8206 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8207 *inset = I40E_INSET_NONE;
8212 for (i = 0, *inset = 0; i < size; i++) {
8213 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8214 if (field[i] == inset_convert_table[j].field) {
8215 *inset |= inset_convert_table[j].inset;
8220 /* It contains unsupported input set, return immediately */
8221 if (j == RTE_DIM(inset_convert_table))
8229 * Translate the input set from bit masks to register aware bit masks
8233 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8243 static const struct inset_map inset_map_common[] = {
8244 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8245 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8246 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8247 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8248 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8249 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8250 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8251 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8252 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8253 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8254 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8255 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8256 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8257 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8258 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8259 {I40E_INSET_TUNNEL_DMAC,
8260 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8261 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8262 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8263 {I40E_INSET_TUNNEL_SRC_PORT,
8264 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8265 {I40E_INSET_TUNNEL_DST_PORT,
8266 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8267 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8268 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8269 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8270 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8271 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8272 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8273 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8274 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8275 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8278 /* some different registers map in x722*/
8279 static const struct inset_map inset_map_diff_x722[] = {
8280 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8281 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8282 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8283 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8286 static const struct inset_map inset_map_diff_not_x722[] = {
8287 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8288 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8289 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8290 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8296 /* Translate input set to register aware inset */
8297 if (type == I40E_MAC_X722) {
8298 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8299 if (input & inset_map_diff_x722[i].inset)
8300 val |= inset_map_diff_x722[i].inset_reg;
8303 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8304 if (input & inset_map_diff_not_x722[i].inset)
8305 val |= inset_map_diff_not_x722[i].inset_reg;
8309 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8310 if (input & inset_map_common[i].inset)
8311 val |= inset_map_common[i].inset_reg;
8318 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8321 uint64_t inset_need_mask = inset;
8323 static const struct {
8326 } inset_mask_map[] = {
8327 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8328 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8329 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8330 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8331 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8332 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8333 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8334 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8337 if (!inset || !mask || !nb_elem)
8340 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8341 /* Clear the inset bit, if no MASK is required,
8342 * for example proto + ttl
8344 if ((inset & inset_mask_map[i].inset) ==
8345 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8346 inset_need_mask &= ~inset_mask_map[i].inset;
8347 if (!inset_need_mask)
8350 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8351 if ((inset_need_mask & inset_mask_map[i].inset) ==
8352 inset_mask_map[i].inset) {
8353 if (idx >= nb_elem) {
8354 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8357 mask[idx] = inset_mask_map[i].mask;
8366 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8368 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8370 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8372 i40e_write_rx_ctl(hw, addr, val);
8373 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8374 (uint32_t)i40e_read_rx_ctl(hw, addr));
8378 i40e_filter_input_set_init(struct i40e_pf *pf)
8380 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8381 enum i40e_filter_pctype pctype;
8382 uint64_t input_set, inset_reg;
8383 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8386 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8387 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8388 if (hw->mac.type == I40E_MAC_X722) {
8389 if (!I40E_VALID_PCTYPE_X722(pctype))
8392 if (!I40E_VALID_PCTYPE(pctype))
8396 input_set = i40e_get_default_input_set(pctype);
8398 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8399 I40E_INSET_MASK_NUM_REG);
8402 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8405 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8406 (uint32_t)(inset_reg & UINT32_MAX));
8407 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8408 (uint32_t)((inset_reg >>
8409 I40E_32_BIT_WIDTH) & UINT32_MAX));
8410 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8411 (uint32_t)(inset_reg & UINT32_MAX));
8412 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8413 (uint32_t)((inset_reg >>
8414 I40E_32_BIT_WIDTH) & UINT32_MAX));
8416 for (i = 0; i < num; i++) {
8417 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8419 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8422 /*clear unused mask registers of the pctype */
8423 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8424 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8426 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8429 I40E_WRITE_FLUSH(hw);
8431 /* store the default input set */
8432 pf->hash_input_set[pctype] = input_set;
8433 pf->fdir.input_set[pctype] = input_set;
8438 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8439 struct rte_eth_input_set_conf *conf)
8441 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8442 enum i40e_filter_pctype pctype;
8443 uint64_t input_set, inset_reg = 0;
8444 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8448 PMD_DRV_LOG(ERR, "Invalid pointer");
8451 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8452 conf->op != RTE_ETH_INPUT_SET_ADD) {
8453 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8457 if (!I40E_VALID_FLOW(conf->flow_type)) {
8458 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8462 if (hw->mac.type == I40E_MAC_X722) {
8463 /* get translated pctype value in fd pctype register */
8464 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8465 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8468 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8470 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8473 PMD_DRV_LOG(ERR, "Failed to parse input set");
8476 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8478 PMD_DRV_LOG(ERR, "Invalid input set");
8481 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8482 /* get inset value in register */
8483 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8484 inset_reg <<= I40E_32_BIT_WIDTH;
8485 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8486 input_set |= pf->hash_input_set[pctype];
8488 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8489 I40E_INSET_MASK_NUM_REG);
8493 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8495 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8496 (uint32_t)(inset_reg & UINT32_MAX));
8497 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8498 (uint32_t)((inset_reg >>
8499 I40E_32_BIT_WIDTH) & UINT32_MAX));
8501 for (i = 0; i < num; i++)
8502 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8504 /*clear unused mask registers of the pctype */
8505 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8506 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8508 I40E_WRITE_FLUSH(hw);
8510 pf->hash_input_set[pctype] = input_set;
8515 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8516 struct rte_eth_input_set_conf *conf)
8518 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8519 enum i40e_filter_pctype pctype;
8520 uint64_t input_set, inset_reg = 0;
8521 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8525 PMD_DRV_LOG(ERR, "Invalid pointer");
8528 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8529 conf->op != RTE_ETH_INPUT_SET_ADD) {
8530 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8534 if (!I40E_VALID_FLOW(conf->flow_type)) {
8535 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8539 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8541 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8544 PMD_DRV_LOG(ERR, "Failed to parse input set");
8547 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8549 PMD_DRV_LOG(ERR, "Invalid input set");
8553 /* get inset value in register */
8554 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8555 inset_reg <<= I40E_32_BIT_WIDTH;
8556 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8558 /* Can not change the inset reg for flex payload for fdir,
8559 * it is done by writing I40E_PRTQF_FD_FLXINSET
8560 * in i40e_set_flex_mask_on_pctype.
8562 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8563 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8565 input_set |= pf->fdir.input_set[pctype];
8566 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8567 I40E_INSET_MASK_NUM_REG);
8571 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8573 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8574 (uint32_t)(inset_reg & UINT32_MAX));
8575 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8576 (uint32_t)((inset_reg >>
8577 I40E_32_BIT_WIDTH) & UINT32_MAX));
8579 for (i = 0; i < num; i++)
8580 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8582 /*clear unused mask registers of the pctype */
8583 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8584 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8586 I40E_WRITE_FLUSH(hw);
8588 pf->fdir.input_set[pctype] = input_set;
8593 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8598 PMD_DRV_LOG(ERR, "Invalid pointer");
8602 switch (info->info_type) {
8603 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8604 i40e_get_symmetric_hash_enable_per_port(hw,
8605 &(info->info.enable));
8607 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8608 ret = i40e_get_hash_filter_global_config(hw,
8609 &(info->info.global_conf));
8612 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8622 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8627 PMD_DRV_LOG(ERR, "Invalid pointer");
8631 switch (info->info_type) {
8632 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8633 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8635 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8636 ret = i40e_set_hash_filter_global_config(hw,
8637 &(info->info.global_conf));
8639 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8640 ret = i40e_hash_filter_inset_select(hw,
8641 &(info->info.input_set_conf));
8645 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8654 /* Operations for hash function */
8656 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8657 enum rte_filter_op filter_op,
8660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8663 switch (filter_op) {
8664 case RTE_ETH_FILTER_NOP:
8666 case RTE_ETH_FILTER_GET:
8667 ret = i40e_hash_filter_get(hw,
8668 (struct rte_eth_hash_filter_info *)arg);
8670 case RTE_ETH_FILTER_SET:
8671 ret = i40e_hash_filter_set(hw,
8672 (struct rte_eth_hash_filter_info *)arg);
8675 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8684 /* Convert ethertype filter structure */
8686 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8687 struct i40e_ethertype_filter *filter)
8689 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8690 filter->input.ether_type = input->ether_type;
8691 filter->flags = input->flags;
8692 filter->queue = input->queue;
8697 /* Check if there exists the ehtertype filter */
8698 struct i40e_ethertype_filter *
8699 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8700 const struct i40e_ethertype_filter_input *input)
8704 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8708 return ethertype_rule->hash_map[ret];
8711 /* Add ethertype filter in SW list */
8713 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8714 struct i40e_ethertype_filter *filter)
8716 struct i40e_ethertype_rule *rule = &pf->ethertype;
8719 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8722 "Failed to insert ethertype filter"
8723 " to hash table %d!",
8727 rule->hash_map[ret] = filter;
8729 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8734 /* Delete ethertype filter in SW list */
8736 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8737 struct i40e_ethertype_filter_input *input)
8739 struct i40e_ethertype_rule *rule = &pf->ethertype;
8740 struct i40e_ethertype_filter *filter;
8743 ret = rte_hash_del_key(rule->hash_table, input);
8746 "Failed to delete ethertype filter"
8747 " to hash table %d!",
8751 filter = rule->hash_map[ret];
8752 rule->hash_map[ret] = NULL;
8754 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8761 * Configure ethertype filter, which can director packet by filtering
8762 * with mac address and ether_type or only ether_type
8765 i40e_ethertype_filter_set(struct i40e_pf *pf,
8766 struct rte_eth_ethertype_filter *filter,
8769 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8770 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8771 struct i40e_ethertype_filter *ethertype_filter, *node;
8772 struct i40e_ethertype_filter check_filter;
8773 struct i40e_control_filter_stats stats;
8777 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8778 PMD_DRV_LOG(ERR, "Invalid queue ID");
8781 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8782 filter->ether_type == ETHER_TYPE_IPv6) {
8784 "unsupported ether_type(0x%04x) in control packet filter.",
8785 filter->ether_type);
8788 if (filter->ether_type == ETHER_TYPE_VLAN)
8789 PMD_DRV_LOG(WARNING,
8790 "filter vlan ether_type in first tag is not supported.");
8792 /* Check if there is the filter in SW list */
8793 memset(&check_filter, 0, sizeof(check_filter));
8794 i40e_ethertype_filter_convert(filter, &check_filter);
8795 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8796 &check_filter.input);
8798 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8802 if (!add && !node) {
8803 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8807 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8808 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8809 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8810 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8811 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8813 memset(&stats, 0, sizeof(stats));
8814 ret = i40e_aq_add_rem_control_packet_filter(hw,
8815 filter->mac_addr.addr_bytes,
8816 filter->ether_type, flags,
8818 filter->queue, add, &stats, NULL);
8821 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8822 ret, stats.mac_etype_used, stats.etype_used,
8823 stats.mac_etype_free, stats.etype_free);
8827 /* Add or delete a filter in SW list */
8829 ethertype_filter = rte_zmalloc("ethertype_filter",
8830 sizeof(*ethertype_filter), 0);
8831 rte_memcpy(ethertype_filter, &check_filter,
8832 sizeof(check_filter));
8833 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8835 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8842 * Handle operations for ethertype filter.
8845 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8846 enum rte_filter_op filter_op,
8849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8852 if (filter_op == RTE_ETH_FILTER_NOP)
8856 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8861 switch (filter_op) {
8862 case RTE_ETH_FILTER_ADD:
8863 ret = i40e_ethertype_filter_set(pf,
8864 (struct rte_eth_ethertype_filter *)arg,
8867 case RTE_ETH_FILTER_DELETE:
8868 ret = i40e_ethertype_filter_set(pf,
8869 (struct rte_eth_ethertype_filter *)arg,
8873 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8881 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8882 enum rte_filter_type filter_type,
8883 enum rte_filter_op filter_op,
8891 switch (filter_type) {
8892 case RTE_ETH_FILTER_NONE:
8893 /* For global configuration */
8894 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8896 case RTE_ETH_FILTER_HASH:
8897 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8899 case RTE_ETH_FILTER_MACVLAN:
8900 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8902 case RTE_ETH_FILTER_ETHERTYPE:
8903 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8905 case RTE_ETH_FILTER_TUNNEL:
8906 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8908 case RTE_ETH_FILTER_FDIR:
8909 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8911 case RTE_ETH_FILTER_GENERIC:
8912 if (filter_op != RTE_ETH_FILTER_GET)
8914 *(const void **)arg = &i40e_flow_ops;
8917 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8927 * Check and enable Extended Tag.
8928 * Enabling Extended Tag is important for 40G performance.
8931 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8933 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8937 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8940 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8944 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8945 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8950 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8953 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8957 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8958 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8961 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8962 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8965 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8972 * As some registers wouldn't be reset unless a global hardware reset,
8973 * hardware initialization is needed to put those registers into an
8974 * expected initial state.
8977 i40e_hw_init(struct rte_eth_dev *dev)
8979 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8981 i40e_enable_extended_tag(dev);
8983 /* clear the PF Queue Filter control register */
8984 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8986 /* Disable symmetric hash per port */
8987 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8990 enum i40e_filter_pctype
8991 i40e_flowtype_to_pctype(uint16_t flow_type)
8993 static const enum i40e_filter_pctype pctype_table[] = {
8994 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8995 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8996 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8997 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8998 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8999 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9000 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9001 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9002 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9003 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9004 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9005 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9006 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9007 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9008 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9009 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9010 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9011 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9012 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9015 return pctype_table[flow_type];
9019 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9021 static const uint16_t flowtype_table[] = {
9022 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9023 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9024 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9025 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9026 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9027 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9028 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9029 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9030 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9031 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9032 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9033 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9034 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9035 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9036 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9037 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9038 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9039 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9040 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9041 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9042 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9043 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9044 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9045 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9046 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9047 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9048 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9049 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9050 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9051 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9052 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9055 return flowtype_table[pctype];
9059 * On X710, performance number is far from the expectation on recent firmware
9060 * versions; on XL710, performance number is also far from the expectation on
9061 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9062 * mode is enabled and port MAC address is equal to the packet destination MAC
9063 * address. The fix for this issue may not be integrated in the following
9064 * firmware version. So the workaround in software driver is needed. It needs
9065 * to modify the initial values of 3 internal only registers for both X710 and
9066 * XL710. Note that the values for X710 or XL710 could be different, and the
9067 * workaround can be removed when it is fixed in firmware in the future.
9070 /* For both X710 and XL710 */
9071 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9072 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9074 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9075 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9078 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9079 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9082 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9084 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9085 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9088 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9090 enum i40e_status_code status;
9091 struct i40e_aq_get_phy_abilities_resp phy_ab;
9094 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9104 i40e_configure_registers(struct i40e_hw *hw)
9110 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9111 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9112 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9118 for (i = 0; i < RTE_DIM(reg_table); i++) {
9119 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9120 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9122 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9123 else /* For X710/XL710/XXV710 */
9125 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9128 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9129 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9131 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9132 else /* For X710/XL710/XXV710 */
9134 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9137 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9138 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9139 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9141 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9144 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9147 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9150 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9154 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9155 reg_table[i].addr, reg);
9156 if (reg == reg_table[i].val)
9159 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9160 reg_table[i].val, NULL);
9163 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9164 reg_table[i].val, reg_table[i].addr);
9167 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9168 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9172 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9173 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9174 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9175 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9177 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9182 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9183 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9187 /* Configure for double VLAN RX stripping */
9188 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9189 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9190 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9191 ret = i40e_aq_debug_write_register(hw,
9192 I40E_VSI_TSR(vsi->vsi_id),
9195 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9197 return I40E_ERR_CONFIG;
9201 /* Configure for double VLAN TX insertion */
9202 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9203 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9204 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9205 ret = i40e_aq_debug_write_register(hw,
9206 I40E_VSI_L2TAGSTXVALID(
9207 vsi->vsi_id), reg, NULL);
9210 "Failed to update VSI_L2TAGSTXVALID[%d]",
9212 return I40E_ERR_CONFIG;
9220 * i40e_aq_add_mirror_rule
9221 * @hw: pointer to the hardware structure
9222 * @seid: VEB seid to add mirror rule to
9223 * @dst_id: destination vsi seid
9224 * @entries: Buffer which contains the entities to be mirrored
9225 * @count: number of entities contained in the buffer
9226 * @rule_id:the rule_id of the rule to be added
9228 * Add a mirror rule for a given veb.
9231 static enum i40e_status_code
9232 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9233 uint16_t seid, uint16_t dst_id,
9234 uint16_t rule_type, uint16_t *entries,
9235 uint16_t count, uint16_t *rule_id)
9237 struct i40e_aq_desc desc;
9238 struct i40e_aqc_add_delete_mirror_rule cmd;
9239 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9240 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9243 enum i40e_status_code status;
9245 i40e_fill_default_direct_cmd_desc(&desc,
9246 i40e_aqc_opc_add_mirror_rule);
9247 memset(&cmd, 0, sizeof(cmd));
9249 buff_len = sizeof(uint16_t) * count;
9250 desc.datalen = rte_cpu_to_le_16(buff_len);
9252 desc.flags |= rte_cpu_to_le_16(
9253 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9254 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9255 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9256 cmd.num_entries = rte_cpu_to_le_16(count);
9257 cmd.seid = rte_cpu_to_le_16(seid);
9258 cmd.destination = rte_cpu_to_le_16(dst_id);
9260 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9261 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9263 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9264 hw->aq.asq_last_status, resp->rule_id,
9265 resp->mirror_rules_used, resp->mirror_rules_free);
9266 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9272 * i40e_aq_del_mirror_rule
9273 * @hw: pointer to the hardware structure
9274 * @seid: VEB seid to add mirror rule to
9275 * @entries: Buffer which contains the entities to be mirrored
9276 * @count: number of entities contained in the buffer
9277 * @rule_id:the rule_id of the rule to be delete
9279 * Delete a mirror rule for a given veb.
9282 static enum i40e_status_code
9283 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9284 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9285 uint16_t count, uint16_t rule_id)
9287 struct i40e_aq_desc desc;
9288 struct i40e_aqc_add_delete_mirror_rule cmd;
9289 uint16_t buff_len = 0;
9290 enum i40e_status_code status;
9293 i40e_fill_default_direct_cmd_desc(&desc,
9294 i40e_aqc_opc_delete_mirror_rule);
9295 memset(&cmd, 0, sizeof(cmd));
9296 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9297 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9299 cmd.num_entries = count;
9300 buff_len = sizeof(uint16_t) * count;
9301 desc.datalen = rte_cpu_to_le_16(buff_len);
9302 buff = (void *)entries;
9304 /* rule id is filled in destination field for deleting mirror rule */
9305 cmd.destination = rte_cpu_to_le_16(rule_id);
9307 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9308 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9309 cmd.seid = rte_cpu_to_le_16(seid);
9311 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9312 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9318 * i40e_mirror_rule_set
9319 * @dev: pointer to the hardware structure
9320 * @mirror_conf: mirror rule info
9321 * @sw_id: mirror rule's sw_id
9322 * @on: enable/disable
9324 * set a mirror rule.
9328 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9329 struct rte_eth_mirror_conf *mirror_conf,
9330 uint8_t sw_id, uint8_t on)
9332 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9333 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9334 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9335 struct i40e_mirror_rule *parent = NULL;
9336 uint16_t seid, dst_seid, rule_id;
9340 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9342 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9344 "mirror rule can not be configured without veb or vfs.");
9347 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9348 PMD_DRV_LOG(ERR, "mirror table is full.");
9351 if (mirror_conf->dst_pool > pf->vf_num) {
9352 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9353 mirror_conf->dst_pool);
9357 seid = pf->main_vsi->veb->seid;
9359 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9360 if (sw_id <= it->index) {
9366 if (mirr_rule && sw_id == mirr_rule->index) {
9368 PMD_DRV_LOG(ERR, "mirror rule exists.");
9371 ret = i40e_aq_del_mirror_rule(hw, seid,
9372 mirr_rule->rule_type,
9374 mirr_rule->num_entries, mirr_rule->id);
9377 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9378 ret, hw->aq.asq_last_status);
9381 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9382 rte_free(mirr_rule);
9383 pf->nb_mirror_rule--;
9387 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9391 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9392 sizeof(struct i40e_mirror_rule) , 0);
9394 PMD_DRV_LOG(ERR, "failed to allocate memory");
9395 return I40E_ERR_NO_MEMORY;
9397 switch (mirror_conf->rule_type) {
9398 case ETH_MIRROR_VLAN:
9399 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9400 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9401 mirr_rule->entries[j] =
9402 mirror_conf->vlan.vlan_id[i];
9407 PMD_DRV_LOG(ERR, "vlan is not specified.");
9408 rte_free(mirr_rule);
9411 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9413 case ETH_MIRROR_VIRTUAL_POOL_UP:
9414 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9415 /* check if the specified pool bit is out of range */
9416 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9417 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9418 rte_free(mirr_rule);
9421 for (i = 0, j = 0; i < pf->vf_num; i++) {
9422 if (mirror_conf->pool_mask & (1ULL << i)) {
9423 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9427 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9428 /* add pf vsi to entries */
9429 mirr_rule->entries[j] = pf->main_vsi_seid;
9433 PMD_DRV_LOG(ERR, "pool is not specified.");
9434 rte_free(mirr_rule);
9437 /* egress and ingress in aq commands means from switch but not port */
9438 mirr_rule->rule_type =
9439 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9440 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9441 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9443 case ETH_MIRROR_UPLINK_PORT:
9444 /* egress and ingress in aq commands means from switch but not port*/
9445 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9447 case ETH_MIRROR_DOWNLINK_PORT:
9448 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9451 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9452 mirror_conf->rule_type);
9453 rte_free(mirr_rule);
9457 /* If the dst_pool is equal to vf_num, consider it as PF */
9458 if (mirror_conf->dst_pool == pf->vf_num)
9459 dst_seid = pf->main_vsi_seid;
9461 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9463 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9464 mirr_rule->rule_type, mirr_rule->entries,
9468 "failed to add mirror rule: ret = %d, aq_err = %d.",
9469 ret, hw->aq.asq_last_status);
9470 rte_free(mirr_rule);
9474 mirr_rule->index = sw_id;
9475 mirr_rule->num_entries = j;
9476 mirr_rule->id = rule_id;
9477 mirr_rule->dst_vsi_seid = dst_seid;
9480 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9482 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9484 pf->nb_mirror_rule++;
9489 * i40e_mirror_rule_reset
9490 * @dev: pointer to the device
9491 * @sw_id: mirror rule's sw_id
9493 * reset a mirror rule.
9497 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9499 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9500 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9501 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9505 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9507 seid = pf->main_vsi->veb->seid;
9509 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9510 if (sw_id == it->index) {
9516 ret = i40e_aq_del_mirror_rule(hw, seid,
9517 mirr_rule->rule_type,
9519 mirr_rule->num_entries, mirr_rule->id);
9522 "failed to remove mirror rule: status = %d, aq_err = %d.",
9523 ret, hw->aq.asq_last_status);
9526 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9527 rte_free(mirr_rule);
9528 pf->nb_mirror_rule--;
9530 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9537 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9539 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9540 uint64_t systim_cycles;
9542 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9543 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9546 return systim_cycles;
9550 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9552 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9555 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9556 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9563 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9565 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9568 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9569 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9576 i40e_start_timecounters(struct rte_eth_dev *dev)
9578 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9579 struct i40e_adapter *adapter =
9580 (struct i40e_adapter *)dev->data->dev_private;
9581 struct rte_eth_link link;
9582 uint32_t tsync_inc_l;
9583 uint32_t tsync_inc_h;
9585 /* Get current link speed. */
9586 memset(&link, 0, sizeof(link));
9587 i40e_dev_link_update(dev, 1);
9588 rte_i40e_dev_atomic_read_link_status(dev, &link);
9590 switch (link.link_speed) {
9591 case ETH_SPEED_NUM_40G:
9592 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9593 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9595 case ETH_SPEED_NUM_10G:
9596 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9597 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9599 case ETH_SPEED_NUM_1G:
9600 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9601 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9608 /* Set the timesync increment value. */
9609 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9610 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9612 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9613 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9614 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9616 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9617 adapter->systime_tc.cc_shift = 0;
9618 adapter->systime_tc.nsec_mask = 0;
9620 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9621 adapter->rx_tstamp_tc.cc_shift = 0;
9622 adapter->rx_tstamp_tc.nsec_mask = 0;
9624 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9625 adapter->tx_tstamp_tc.cc_shift = 0;
9626 adapter->tx_tstamp_tc.nsec_mask = 0;
9630 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9632 struct i40e_adapter *adapter =
9633 (struct i40e_adapter *)dev->data->dev_private;
9635 adapter->systime_tc.nsec += delta;
9636 adapter->rx_tstamp_tc.nsec += delta;
9637 adapter->tx_tstamp_tc.nsec += delta;
9643 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9646 struct i40e_adapter *adapter =
9647 (struct i40e_adapter *)dev->data->dev_private;
9649 ns = rte_timespec_to_ns(ts);
9651 /* Set the timecounters to a new value. */
9652 adapter->systime_tc.nsec = ns;
9653 adapter->rx_tstamp_tc.nsec = ns;
9654 adapter->tx_tstamp_tc.nsec = ns;
9660 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9662 uint64_t ns, systime_cycles;
9663 struct i40e_adapter *adapter =
9664 (struct i40e_adapter *)dev->data->dev_private;
9666 systime_cycles = i40e_read_systime_cyclecounter(dev);
9667 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9668 *ts = rte_ns_to_timespec(ns);
9674 i40e_timesync_enable(struct rte_eth_dev *dev)
9676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9677 uint32_t tsync_ctl_l;
9678 uint32_t tsync_ctl_h;
9680 /* Stop the timesync system time. */
9681 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9682 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9683 /* Reset the timesync system time value. */
9684 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9685 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9687 i40e_start_timecounters(dev);
9689 /* Clear timesync registers. */
9690 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9691 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9692 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9693 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9694 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9695 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9697 /* Enable timestamping of PTP packets. */
9698 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9699 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9701 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9702 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9703 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9705 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9706 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9712 i40e_timesync_disable(struct rte_eth_dev *dev)
9714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9715 uint32_t tsync_ctl_l;
9716 uint32_t tsync_ctl_h;
9718 /* Disable timestamping of transmitted PTP packets. */
9719 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9720 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9722 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9723 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9725 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9726 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9728 /* Reset the timesync increment value. */
9729 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9730 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9736 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9737 struct timespec *timestamp, uint32_t flags)
9739 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9740 struct i40e_adapter *adapter =
9741 (struct i40e_adapter *)dev->data->dev_private;
9743 uint32_t sync_status;
9744 uint32_t index = flags & 0x03;
9745 uint64_t rx_tstamp_cycles;
9748 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9749 if ((sync_status & (1 << index)) == 0)
9752 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9753 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9754 *timestamp = rte_ns_to_timespec(ns);
9760 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9761 struct timespec *timestamp)
9763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9764 struct i40e_adapter *adapter =
9765 (struct i40e_adapter *)dev->data->dev_private;
9767 uint32_t sync_status;
9768 uint64_t tx_tstamp_cycles;
9771 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9772 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9775 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9776 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9777 *timestamp = rte_ns_to_timespec(ns);
9783 * i40e_parse_dcb_configure - parse dcb configure from user
9784 * @dev: the device being configured
9785 * @dcb_cfg: pointer of the result of parse
9786 * @*tc_map: bit map of enabled traffic classes
9788 * Returns 0 on success, negative value on failure
9791 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9792 struct i40e_dcbx_config *dcb_cfg,
9795 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9796 uint8_t i, tc_bw, bw_lf;
9798 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9800 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9801 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9802 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9806 /* assume each tc has the same bw */
9807 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9808 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9809 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9810 /* to ensure the sum of tcbw is equal to 100 */
9811 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9812 for (i = 0; i < bw_lf; i++)
9813 dcb_cfg->etscfg.tcbwtable[i]++;
9815 /* assume each tc has the same Transmission Selection Algorithm */
9816 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9817 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9819 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9820 dcb_cfg->etscfg.prioritytable[i] =
9821 dcb_rx_conf->dcb_tc[i];
9823 /* FW needs one App to configure HW */
9824 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9825 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9826 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9827 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9829 if (dcb_rx_conf->nb_tcs == 0)
9830 *tc_map = 1; /* tc0 only */
9832 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9834 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9835 dcb_cfg->pfc.willing = 0;
9836 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9837 dcb_cfg->pfc.pfcenable = *tc_map;
9843 static enum i40e_status_code
9844 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9845 struct i40e_aqc_vsi_properties_data *info,
9846 uint8_t enabled_tcmap)
9848 enum i40e_status_code ret;
9849 int i, total_tc = 0;
9850 uint16_t qpnum_per_tc, bsf, qp_idx;
9851 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9852 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9853 uint16_t used_queues;
9855 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9856 if (ret != I40E_SUCCESS)
9859 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9860 if (enabled_tcmap & (1 << i))
9865 vsi->enabled_tc = enabled_tcmap;
9867 /* different VSI has different queues assigned */
9868 if (vsi->type == I40E_VSI_MAIN)
9869 used_queues = dev_data->nb_rx_queues -
9870 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9871 else if (vsi->type == I40E_VSI_VMDQ2)
9872 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9874 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9875 return I40E_ERR_NO_AVAILABLE_VSI;
9878 qpnum_per_tc = used_queues / total_tc;
9879 /* Number of queues per enabled TC */
9880 if (qpnum_per_tc == 0) {
9881 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9882 return I40E_ERR_INVALID_QP_ID;
9884 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9886 bsf = rte_bsf32(qpnum_per_tc);
9889 * Configure TC and queue mapping parameters, for enabled TC,
9890 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9891 * default queue will serve it.
9894 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9895 if (vsi->enabled_tc & (1 << i)) {
9896 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9897 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9898 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9899 qp_idx += qpnum_per_tc;
9901 info->tc_mapping[i] = 0;
9904 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9905 if (vsi->type == I40E_VSI_SRIOV) {
9906 info->mapping_flags |=
9907 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9908 for (i = 0; i < vsi->nb_qps; i++)
9909 info->queue_mapping[i] =
9910 rte_cpu_to_le_16(vsi->base_queue + i);
9912 info->mapping_flags |=
9913 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9914 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9916 info->valid_sections |=
9917 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9919 return I40E_SUCCESS;
9923 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9924 * @veb: VEB to be configured
9925 * @tc_map: enabled TC bitmap
9927 * Returns 0 on success, negative value on failure
9929 static enum i40e_status_code
9930 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9932 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9933 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9934 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9935 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9936 enum i40e_status_code ret = I40E_SUCCESS;
9940 /* Check if enabled_tc is same as existing or new TCs */
9941 if (veb->enabled_tc == tc_map)
9944 /* configure tc bandwidth */
9945 memset(&veb_bw, 0, sizeof(veb_bw));
9946 veb_bw.tc_valid_bits = tc_map;
9947 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9948 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9949 if (tc_map & BIT_ULL(i))
9950 veb_bw.tc_bw_share_credits[i] = 1;
9952 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9956 "AQ command Config switch_comp BW allocation per TC failed = %d",
9957 hw->aq.asq_last_status);
9961 memset(&ets_query, 0, sizeof(ets_query));
9962 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9964 if (ret != I40E_SUCCESS) {
9966 "Failed to get switch_comp ETS configuration %u",
9967 hw->aq.asq_last_status);
9970 memset(&bw_query, 0, sizeof(bw_query));
9971 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9973 if (ret != I40E_SUCCESS) {
9975 "Failed to get switch_comp bandwidth configuration %u",
9976 hw->aq.asq_last_status);
9980 /* store and print out BW info */
9981 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9982 veb->bw_info.bw_max = ets_query.tc_bw_max;
9983 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9984 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9985 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9986 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9988 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9989 veb->bw_info.bw_ets_share_credits[i] =
9990 bw_query.tc_bw_share_credits[i];
9991 veb->bw_info.bw_ets_credits[i] =
9992 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9993 /* 4 bits per TC, 4th bit is reserved */
9994 veb->bw_info.bw_ets_max[i] =
9995 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9996 RTE_LEN2MASK(3, uint8_t));
9997 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9998 veb->bw_info.bw_ets_share_credits[i]);
9999 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10000 veb->bw_info.bw_ets_credits[i]);
10001 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10002 veb->bw_info.bw_ets_max[i]);
10005 veb->enabled_tc = tc_map;
10012 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10013 * @vsi: VSI to be configured
10014 * @tc_map: enabled TC bitmap
10016 * Returns 0 on success, negative value on failure
10018 static enum i40e_status_code
10019 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10021 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10022 struct i40e_vsi_context ctxt;
10023 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10024 enum i40e_status_code ret = I40E_SUCCESS;
10027 /* Check if enabled_tc is same as existing or new TCs */
10028 if (vsi->enabled_tc == tc_map)
10031 /* configure tc bandwidth */
10032 memset(&bw_data, 0, sizeof(bw_data));
10033 bw_data.tc_valid_bits = tc_map;
10034 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10035 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10036 if (tc_map & BIT_ULL(i))
10037 bw_data.tc_bw_credits[i] = 1;
10039 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10042 "AQ command Config VSI BW allocation per TC failed = %d",
10043 hw->aq.asq_last_status);
10046 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10047 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10049 /* Update Queue Pairs Mapping for currently enabled UPs */
10050 ctxt.seid = vsi->seid;
10051 ctxt.pf_num = hw->pf_id;
10053 ctxt.uplink_seid = vsi->uplink_seid;
10054 ctxt.info = vsi->info;
10056 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10060 /* Update the VSI after updating the VSI queue-mapping information */
10061 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10063 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10064 hw->aq.asq_last_status);
10067 /* update the local VSI info with updated queue map */
10068 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10069 sizeof(vsi->info.tc_mapping));
10070 (void)rte_memcpy(&vsi->info.queue_mapping,
10071 &ctxt.info.queue_mapping,
10072 sizeof(vsi->info.queue_mapping));
10073 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10074 vsi->info.valid_sections = 0;
10076 /* query and update current VSI BW information */
10077 ret = i40e_vsi_get_bw_config(vsi);
10080 "Failed updating vsi bw info, err %s aq_err %s",
10081 i40e_stat_str(hw, ret),
10082 i40e_aq_str(hw, hw->aq.asq_last_status));
10086 vsi->enabled_tc = tc_map;
10093 * i40e_dcb_hw_configure - program the dcb setting to hw
10094 * @pf: pf the configuration is taken on
10095 * @new_cfg: new configuration
10096 * @tc_map: enabled TC bitmap
10098 * Returns 0 on success, negative value on failure
10100 static enum i40e_status_code
10101 i40e_dcb_hw_configure(struct i40e_pf *pf,
10102 struct i40e_dcbx_config *new_cfg,
10105 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10106 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10107 struct i40e_vsi *main_vsi = pf->main_vsi;
10108 struct i40e_vsi_list *vsi_list;
10109 enum i40e_status_code ret;
10113 /* Use the FW API if FW > v4.4*/
10114 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10115 (hw->aq.fw_maj_ver >= 5))) {
10117 "FW < v4.4, can not use FW LLDP API to configure DCB");
10118 return I40E_ERR_FIRMWARE_API_VERSION;
10121 /* Check if need reconfiguration */
10122 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10123 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10124 return I40E_SUCCESS;
10127 /* Copy the new config to the current config */
10128 *old_cfg = *new_cfg;
10129 old_cfg->etsrec = old_cfg->etscfg;
10130 ret = i40e_set_dcb_config(hw);
10132 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10133 i40e_stat_str(hw, ret),
10134 i40e_aq_str(hw, hw->aq.asq_last_status));
10137 /* set receive Arbiter to RR mode and ETS scheme by default */
10138 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10139 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10140 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10141 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10142 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10143 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10144 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10145 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10146 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10147 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10148 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10149 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10150 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10152 /* get local mib to check whether it is configured correctly */
10154 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10155 /* Get Local DCB Config */
10156 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10157 &hw->local_dcbx_config);
10159 /* if Veb is created, need to update TC of it at first */
10160 if (main_vsi->veb) {
10161 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10163 PMD_INIT_LOG(WARNING,
10164 "Failed configuring TC for VEB seid=%d",
10165 main_vsi->veb->seid);
10167 /* Update each VSI */
10168 i40e_vsi_config_tc(main_vsi, tc_map);
10169 if (main_vsi->veb) {
10170 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10171 /* Beside main VSI and VMDQ VSIs, only enable default
10172 * TC for other VSIs
10174 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10175 ret = i40e_vsi_config_tc(vsi_list->vsi,
10178 ret = i40e_vsi_config_tc(vsi_list->vsi,
10179 I40E_DEFAULT_TCMAP);
10181 PMD_INIT_LOG(WARNING,
10182 "Failed configuring TC for VSI seid=%d",
10183 vsi_list->vsi->seid);
10187 return I40E_SUCCESS;
10191 * i40e_dcb_init_configure - initial dcb config
10192 * @dev: device being configured
10193 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10195 * Returns 0 on success, negative value on failure
10198 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10204 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10205 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10209 /* DCB initialization:
10210 * Update DCB configuration from the Firmware and configure
10211 * LLDP MIB change event.
10213 if (sw_dcb == TRUE) {
10214 ret = i40e_init_dcb(hw);
10215 /* If lldp agent is stopped, the return value from
10216 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10217 * adminq status. Otherwise, it should return success.
10219 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10220 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10221 memset(&hw->local_dcbx_config, 0,
10222 sizeof(struct i40e_dcbx_config));
10223 /* set dcb default configuration */
10224 hw->local_dcbx_config.etscfg.willing = 0;
10225 hw->local_dcbx_config.etscfg.maxtcs = 0;
10226 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10227 hw->local_dcbx_config.etscfg.tsatable[0] =
10229 /* all UPs mapping to TC0 */
10230 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10231 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10232 hw->local_dcbx_config.etsrec =
10233 hw->local_dcbx_config.etscfg;
10234 hw->local_dcbx_config.pfc.willing = 0;
10235 hw->local_dcbx_config.pfc.pfccap =
10236 I40E_MAX_TRAFFIC_CLASS;
10237 hw->local_dcbx_config.pfc.pfcenable =
10238 I40E_DEFAULT_TCMAP;
10239 /* FW needs one App to configure HW */
10240 hw->local_dcbx_config.numapps = 1;
10241 hw->local_dcbx_config.app[0].selector =
10242 I40E_APP_SEL_ETHTYPE;
10243 hw->local_dcbx_config.app[0].priority = 3;
10244 hw->local_dcbx_config.app[0].protocolid =
10245 I40E_APP_PROTOID_FCOE;
10246 ret = i40e_set_dcb_config(hw);
10249 "default dcb config fails. err = %d, aq_err = %d.",
10250 ret, hw->aq.asq_last_status);
10255 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10256 ret, hw->aq.asq_last_status);
10260 ret = i40e_aq_start_lldp(hw, NULL);
10261 if (ret != I40E_SUCCESS)
10262 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10264 ret = i40e_init_dcb(hw);
10266 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10268 "HW doesn't support DCBX offload.");
10273 "DCBX configuration failed, err = %d, aq_err = %d.",
10274 ret, hw->aq.asq_last_status);
10282 * i40e_dcb_setup - setup dcb related config
10283 * @dev: device being configured
10285 * Returns 0 on success, negative value on failure
10288 i40e_dcb_setup(struct rte_eth_dev *dev)
10290 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10291 struct i40e_dcbx_config dcb_cfg;
10292 uint8_t tc_map = 0;
10295 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10296 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10300 if (pf->vf_num != 0)
10301 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10303 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10305 PMD_INIT_LOG(ERR, "invalid dcb config");
10308 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10310 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10318 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10319 struct rte_eth_dcb_info *dcb_info)
10321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10323 struct i40e_vsi *vsi = pf->main_vsi;
10324 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10325 uint16_t bsf, tc_mapping;
10328 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10329 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10331 dcb_info->nb_tcs = 1;
10332 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10333 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10334 for (i = 0; i < dcb_info->nb_tcs; i++)
10335 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10337 /* get queue mapping if vmdq is disabled */
10338 if (!pf->nb_cfg_vmdq_vsi) {
10339 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10340 if (!(vsi->enabled_tc & (1 << i)))
10342 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10343 dcb_info->tc_queue.tc_rxq[j][i].base =
10344 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10345 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10346 dcb_info->tc_queue.tc_txq[j][i].base =
10347 dcb_info->tc_queue.tc_rxq[j][i].base;
10348 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10349 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10350 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10351 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10352 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10357 /* get queue mapping if vmdq is enabled */
10359 vsi = pf->vmdq[j].vsi;
10360 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10361 if (!(vsi->enabled_tc & (1 << i)))
10363 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10364 dcb_info->tc_queue.tc_rxq[j][i].base =
10365 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10366 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10367 dcb_info->tc_queue.tc_txq[j][i].base =
10368 dcb_info->tc_queue.tc_rxq[j][i].base;
10369 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10370 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10371 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10372 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10373 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10376 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10381 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10383 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10384 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10385 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10386 uint16_t interval =
10387 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10388 uint16_t msix_intr;
10390 msix_intr = intr_handle->intr_vec[queue_id];
10391 if (msix_intr == I40E_MISC_VEC_ID)
10392 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10393 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10394 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10395 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10397 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10400 I40E_PFINT_DYN_CTLN(msix_intr -
10401 I40E_RX_VEC_START),
10402 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10403 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10404 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10406 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10408 I40E_WRITE_FLUSH(hw);
10409 rte_intr_enable(&pci_dev->intr_handle);
10415 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10417 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10418 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10419 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10420 uint16_t msix_intr;
10422 msix_intr = intr_handle->intr_vec[queue_id];
10423 if (msix_intr == I40E_MISC_VEC_ID)
10424 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10427 I40E_PFINT_DYN_CTLN(msix_intr -
10428 I40E_RX_VEC_START),
10430 I40E_WRITE_FLUSH(hw);
10435 static int i40e_get_regs(struct rte_eth_dev *dev,
10436 struct rte_dev_reg_info *regs)
10438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10439 uint32_t *ptr_data = regs->data;
10440 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10441 const struct i40e_reg_info *reg_info;
10443 if (ptr_data == NULL) {
10444 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10445 regs->width = sizeof(uint32_t);
10449 /* The first few registers have to be read using AQ operations */
10451 while (i40e_regs_adminq[reg_idx].name) {
10452 reg_info = &i40e_regs_adminq[reg_idx++];
10453 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10455 arr_idx2 <= reg_info->count2;
10457 reg_offset = arr_idx * reg_info->stride1 +
10458 arr_idx2 * reg_info->stride2;
10459 reg_offset += reg_info->base_addr;
10460 ptr_data[reg_offset >> 2] =
10461 i40e_read_rx_ctl(hw, reg_offset);
10465 /* The remaining registers can be read using primitives */
10467 while (i40e_regs_others[reg_idx].name) {
10468 reg_info = &i40e_regs_others[reg_idx++];
10469 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10471 arr_idx2 <= reg_info->count2;
10473 reg_offset = arr_idx * reg_info->stride1 +
10474 arr_idx2 * reg_info->stride2;
10475 reg_offset += reg_info->base_addr;
10476 ptr_data[reg_offset >> 2] =
10477 I40E_READ_REG(hw, reg_offset);
10484 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10486 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10488 /* Convert word count to byte count */
10489 return hw->nvm.sr_size << 1;
10492 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10493 struct rte_dev_eeprom_info *eeprom)
10495 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10496 uint16_t *data = eeprom->data;
10497 uint16_t offset, length, cnt_words;
10500 offset = eeprom->offset >> 1;
10501 length = eeprom->length >> 1;
10502 cnt_words = length;
10504 if (offset > hw->nvm.sr_size ||
10505 offset + length > hw->nvm.sr_size) {
10506 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10510 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10512 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10513 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10514 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10521 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10522 struct ether_addr *mac_addr)
10524 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10526 if (!is_valid_assigned_ether_addr(mac_addr)) {
10527 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10531 /* Flags: 0x3 updates port address */
10532 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10536 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10538 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10539 struct rte_eth_dev_data *dev_data = pf->dev_data;
10540 uint32_t frame_size = mtu + ETHER_HDR_LEN
10541 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10544 /* check if mtu is within the allowed range */
10545 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10548 /* mtu setting is forbidden if port is start */
10549 if (dev_data->dev_started) {
10550 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10551 dev_data->port_id);
10555 if (frame_size > ETHER_MAX_LEN)
10556 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10558 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10560 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10565 /* Restore ethertype filter */
10567 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10569 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10570 struct i40e_ethertype_filter_list
10571 *ethertype_list = &pf->ethertype.ethertype_list;
10572 struct i40e_ethertype_filter *f;
10573 struct i40e_control_filter_stats stats;
10576 TAILQ_FOREACH(f, ethertype_list, rules) {
10578 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10579 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10580 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10581 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10582 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10584 memset(&stats, 0, sizeof(stats));
10585 i40e_aq_add_rem_control_packet_filter(hw,
10586 f->input.mac_addr.addr_bytes,
10587 f->input.ether_type,
10588 flags, pf->main_vsi->seid,
10589 f->queue, 1, &stats, NULL);
10591 PMD_DRV_LOG(INFO, "Ethertype filter:"
10592 " mac_etype_used = %u, etype_used = %u,"
10593 " mac_etype_free = %u, etype_free = %u",
10594 stats.mac_etype_used, stats.etype_used,
10595 stats.mac_etype_free, stats.etype_free);
10598 /* Restore tunnel filter */
10600 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10602 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10603 struct i40e_vsi *vsi = pf->main_vsi;
10604 struct i40e_tunnel_filter_list
10605 *tunnel_list = &pf->tunnel.tunnel_list;
10606 struct i40e_tunnel_filter *f;
10607 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10608 bool big_buffer = 0;
10610 TAILQ_FOREACH(f, tunnel_list, rules) {
10611 memset(&cld_filter, 0, sizeof(cld_filter));
10612 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10613 (struct ether_addr *)&cld_filter.element.outer_mac);
10614 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10615 (struct ether_addr *)&cld_filter.element.inner_mac);
10616 cld_filter.element.inner_vlan = f->input.inner_vlan;
10617 cld_filter.element.flags = f->input.flags;
10618 cld_filter.element.tenant_id = f->input.tenant_id;
10619 cld_filter.element.queue_number = f->queue;
10620 rte_memcpy(cld_filter.general_fields,
10621 f->input.general_fields,
10622 sizeof(f->input.general_fields));
10624 if (((f->input.flags &
10625 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10626 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10628 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10629 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE))
10633 i40e_aq_add_cloud_filters_big_buffer(hw,
10634 vsi->seid, &cld_filter, 1);
10636 i40e_aq_add_cloud_filters(hw, vsi->seid,
10637 &cld_filter.element, 1);
10642 i40e_filter_restore(struct i40e_pf *pf)
10644 i40e_ethertype_filter_restore(pf);
10645 i40e_tunnel_filter_restore(pf);
10646 i40e_fdir_filter_restore(pf);
10650 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10652 if (strcmp(dev->driver->pci_drv.driver.name,
10653 drv->pci_drv.driver.name))
10660 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10662 struct rte_eth_dev *dev;
10663 struct i40e_pf *pf;
10665 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10667 dev = &rte_eth_devices[port];
10669 if (!is_device_supported(dev, &rte_i40e_pmd))
10672 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10674 if (vf >= pf->vf_num || !pf->vfs) {
10675 PMD_DRV_LOG(ERR, "Invalid argument.");
10679 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10685 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10687 struct rte_eth_dev *dev;
10688 struct i40e_pf *pf;
10689 struct i40e_vsi *vsi;
10690 struct i40e_hw *hw;
10691 struct i40e_vsi_context ctxt;
10694 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10696 dev = &rte_eth_devices[port];
10698 if (!is_device_supported(dev, &rte_i40e_pmd))
10701 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10703 if (vf_id >= pf->vf_num || !pf->vfs) {
10704 PMD_DRV_LOG(ERR, "Invalid argument.");
10708 vsi = pf->vfs[vf_id].vsi;
10710 PMD_DRV_LOG(ERR, "Invalid VSI.");
10714 /* Check if it has been already on or off */
10715 if (vsi->info.valid_sections &
10716 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10718 if ((vsi->info.sec_flags &
10719 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10720 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10721 return 0; /* already on */
10723 if ((vsi->info.sec_flags &
10724 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10725 return 0; /* already off */
10729 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10731 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10733 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10735 memset(&ctxt, 0, sizeof(ctxt));
10736 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10737 ctxt.seid = vsi->seid;
10739 hw = I40E_VSI_TO_HW(vsi);
10740 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10741 if (ret != I40E_SUCCESS) {
10743 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10750 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10754 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10755 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10758 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10762 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10763 if (!(vsi->vfta[j] & (1 << k)))
10766 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10770 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10772 ret = i40e_aq_add_vlan(hw, vsi->seid,
10773 &vlan_data, 1, NULL);
10775 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10776 &vlan_data, 1, NULL);
10777 if (ret != I40E_SUCCESS) {
10779 "Failed to add/rm vlan filter");
10785 return I40E_SUCCESS;
10789 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10791 struct rte_eth_dev *dev;
10792 struct i40e_pf *pf;
10793 struct i40e_vsi *vsi;
10794 struct i40e_hw *hw;
10795 struct i40e_vsi_context ctxt;
10798 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10800 dev = &rte_eth_devices[port];
10802 if (!is_device_supported(dev, &rte_i40e_pmd))
10805 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10807 if (vf_id >= pf->vf_num || !pf->vfs) {
10808 PMD_DRV_LOG(ERR, "Invalid argument.");
10812 vsi = pf->vfs[vf_id].vsi;
10814 PMD_DRV_LOG(ERR, "Invalid VSI.");
10818 /* Check if it has been already on or off */
10819 if (vsi->vlan_anti_spoof_on == on)
10820 return 0; /* already on or off */
10822 vsi->vlan_anti_spoof_on = on;
10823 if (!vsi->vlan_filter_on) {
10824 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10826 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10831 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10833 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10835 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10837 memset(&ctxt, 0, sizeof(ctxt));
10838 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10839 ctxt.seid = vsi->seid;
10841 hw = I40E_VSI_TO_HW(vsi);
10842 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10843 if (ret != I40E_SUCCESS) {
10845 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10852 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10854 struct i40e_mac_filter *f;
10855 struct i40e_macvlan_filter *mv_f;
10857 enum rte_mac_filter_type filter_type;
10858 int ret = I40E_SUCCESS;
10861 /* remove all the MACs */
10862 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10863 vlan_num = vsi->vlan_num;
10864 filter_type = f->mac_info.filter_type;
10865 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10866 filter_type == RTE_MACVLAN_HASH_MATCH) {
10867 if (vlan_num == 0) {
10868 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10869 return I40E_ERR_PARAM;
10871 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10872 filter_type == RTE_MAC_HASH_MATCH)
10875 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10877 PMD_DRV_LOG(ERR, "failed to allocate memory");
10878 return I40E_ERR_NO_MEMORY;
10881 for (i = 0; i < vlan_num; i++) {
10882 mv_f[i].filter_type = filter_type;
10883 (void)rte_memcpy(&mv_f[i].macaddr,
10884 &f->mac_info.mac_addr,
10887 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10888 filter_type == RTE_MACVLAN_HASH_MATCH) {
10889 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10890 &f->mac_info.mac_addr);
10891 if (ret != I40E_SUCCESS) {
10897 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10898 if (ret != I40E_SUCCESS) {
10904 ret = I40E_SUCCESS;
10911 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10913 struct i40e_mac_filter *f;
10914 struct i40e_macvlan_filter *mv_f;
10915 int i, vlan_num = 0;
10916 int ret = I40E_SUCCESS;
10919 /* restore all the MACs */
10920 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10921 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10922 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10924 * If vlan_num is 0, that's the first time to add mac,
10925 * set mask for vlan_id 0.
10927 if (vsi->vlan_num == 0) {
10928 i40e_set_vlan_filter(vsi, 0, 1);
10931 vlan_num = vsi->vlan_num;
10932 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10933 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10936 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10938 PMD_DRV_LOG(ERR, "failed to allocate memory");
10939 return I40E_ERR_NO_MEMORY;
10942 for (i = 0; i < vlan_num; i++) {
10943 mv_f[i].filter_type = f->mac_info.filter_type;
10944 (void)rte_memcpy(&mv_f[i].macaddr,
10945 &f->mac_info.mac_addr,
10949 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10950 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10951 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10952 &f->mac_info.mac_addr);
10953 if (ret != I40E_SUCCESS) {
10959 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10960 if (ret != I40E_SUCCESS) {
10966 ret = I40E_SUCCESS;
10973 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10975 struct i40e_vsi_context ctxt;
10976 struct i40e_hw *hw;
10982 hw = I40E_VSI_TO_HW(vsi);
10984 /* Use the FW API if FW >= v5.0 */
10985 if (hw->aq.fw_maj_ver < 5) {
10986 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10990 /* Check if it has been already on or off */
10991 if (vsi->info.valid_sections &
10992 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10994 if ((vsi->info.switch_id &
10995 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10996 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10997 return 0; /* already on */
10999 if ((vsi->info.switch_id &
11000 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11001 return 0; /* already off */
11005 /* remove all the MAC and VLAN first */
11006 ret = i40e_vsi_rm_mac_filter(vsi);
11008 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11011 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11012 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11014 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11019 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11021 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11023 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11025 memset(&ctxt, 0, sizeof(ctxt));
11026 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11027 ctxt.seid = vsi->seid;
11029 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11030 if (ret != I40E_SUCCESS) {
11031 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11035 /* add all the MAC and VLAN back */
11036 ret = i40e_vsi_restore_mac_filter(vsi);
11039 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11040 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11049 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11051 struct rte_eth_dev *dev;
11052 struct i40e_pf *pf;
11053 struct i40e_pf_vf *vf;
11054 struct i40e_vsi *vsi;
11058 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11060 dev = &rte_eth_devices[port];
11062 if (!is_device_supported(dev, &rte_i40e_pmd))
11065 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11067 /* setup PF TX loopback */
11068 vsi = pf->main_vsi;
11069 ret = i40e_vsi_set_tx_loopback(vsi, on);
11073 /* setup TX loopback for all the VFs */
11075 /* if no VF, do nothing. */
11079 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11080 vf = &pf->vfs[vf_id];
11083 ret = i40e_vsi_set_tx_loopback(vsi, on);
11092 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11094 struct rte_eth_dev *dev;
11095 struct i40e_pf *pf;
11096 struct i40e_vsi *vsi;
11097 struct i40e_hw *hw;
11100 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11102 dev = &rte_eth_devices[port];
11104 if (!is_device_supported(dev, &rte_i40e_pmd))
11107 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11109 if (vf_id >= pf->vf_num || !pf->vfs) {
11110 PMD_DRV_LOG(ERR, "Invalid argument.");
11114 vsi = pf->vfs[vf_id].vsi;
11116 PMD_DRV_LOG(ERR, "Invalid VSI.");
11120 hw = I40E_VSI_TO_HW(vsi);
11122 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11124 if (ret != I40E_SUCCESS) {
11126 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11133 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11135 struct rte_eth_dev *dev;
11136 struct i40e_pf *pf;
11137 struct i40e_vsi *vsi;
11138 struct i40e_hw *hw;
11141 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11143 dev = &rte_eth_devices[port];
11145 if (!is_device_supported(dev, &rte_i40e_pmd))
11148 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11150 if (vf_id >= pf->vf_num || !pf->vfs) {
11151 PMD_DRV_LOG(ERR, "Invalid argument.");
11155 vsi = pf->vfs[vf_id].vsi;
11157 PMD_DRV_LOG(ERR, "Invalid VSI.");
11161 hw = I40E_VSI_TO_HW(vsi);
11163 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11165 if (ret != I40E_SUCCESS) {
11167 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11174 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11175 struct ether_addr *mac_addr)
11177 struct i40e_mac_filter *f;
11178 struct rte_eth_dev *dev;
11179 struct i40e_pf_vf *vf;
11180 struct i40e_vsi *vsi;
11181 struct i40e_pf *pf;
11184 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11187 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11189 dev = &rte_eth_devices[port];
11191 if (!is_device_supported(dev, &rte_i40e_pmd))
11194 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11196 if (vf_id >= pf->vf_num || !pf->vfs)
11199 vf = &pf->vfs[vf_id];
11202 PMD_DRV_LOG(ERR, "Invalid VSI.");
11206 ether_addr_copy(mac_addr, &vf->mac_addr);
11208 /* Remove all existing mac */
11209 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11210 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11215 /* Set vlan strip on/off for specific VF from host */
11217 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11219 struct rte_eth_dev *dev;
11220 struct i40e_pf *pf;
11221 struct i40e_vsi *vsi;
11224 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11226 dev = &rte_eth_devices[port];
11228 if (!is_device_supported(dev, &rte_i40e_pmd))
11231 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11233 if (vf_id >= pf->vf_num || !pf->vfs) {
11234 PMD_DRV_LOG(ERR, "Invalid argument.");
11238 vsi = pf->vfs[vf_id].vsi;
11243 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11244 if (ret != I40E_SUCCESS) {
11246 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11252 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11255 struct rte_eth_dev *dev;
11256 struct i40e_pf *pf;
11257 struct i40e_hw *hw;
11258 struct i40e_vsi *vsi;
11259 struct i40e_vsi_context ctxt;
11262 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11264 if (vlan_id > ETHER_MAX_VLAN_ID) {
11265 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11269 dev = &rte_eth_devices[port];
11271 if (!is_device_supported(dev, &rte_i40e_pmd))
11274 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11275 hw = I40E_PF_TO_HW(pf);
11278 * return -ENODEV if SRIOV not enabled, VF number not configured
11279 * or no queue assigned.
11281 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11282 pf->vf_nb_qps == 0)
11285 if (vf_id >= pf->vf_num || !pf->vfs) {
11286 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11290 vsi = pf->vfs[vf_id].vsi;
11292 PMD_DRV_LOG(ERR, "Invalid VSI.");
11296 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11297 vsi->info.pvid = vlan_id;
11299 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11301 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11303 memset(&ctxt, 0, sizeof(ctxt));
11304 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11305 ctxt.seid = vsi->seid;
11307 hw = I40E_VSI_TO_HW(vsi);
11308 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11309 if (ret != I40E_SUCCESS) {
11311 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11317 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11320 struct rte_eth_dev *dev;
11321 struct i40e_pf *pf;
11322 struct i40e_vsi *vsi;
11323 struct i40e_hw *hw;
11324 struct i40e_mac_filter_info filter;
11325 struct ether_addr broadcast = {
11326 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11329 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11332 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11336 dev = &rte_eth_devices[port];
11338 if (!is_device_supported(dev, &rte_i40e_pmd))
11341 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11342 hw = I40E_PF_TO_HW(pf);
11344 if (vf_id >= pf->vf_num || !pf->vfs) {
11345 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11350 * return -ENODEV if SRIOV not enabled, VF number not configured
11351 * or no queue assigned.
11353 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11354 pf->vf_nb_qps == 0) {
11355 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11359 vsi = pf->vfs[vf_id].vsi;
11361 PMD_DRV_LOG(ERR, "Invalid VSI.");
11366 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11367 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11368 ret = i40e_vsi_add_mac(vsi, &filter);
11370 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11373 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11375 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11383 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11385 struct rte_eth_dev *dev;
11386 struct i40e_pf *pf;
11387 struct i40e_hw *hw;
11388 struct i40e_vsi *vsi;
11389 struct i40e_vsi_context ctxt;
11392 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11395 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11399 dev = &rte_eth_devices[port];
11401 if (!is_device_supported(dev, &rte_i40e_pmd))
11404 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11405 hw = I40E_PF_TO_HW(pf);
11408 * return -ENODEV if SRIOV not enabled, VF number not configured
11409 * or no queue assigned.
11411 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11412 pf->vf_nb_qps == 0) {
11413 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11417 if (vf_id >= pf->vf_num || !pf->vfs) {
11418 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11422 vsi = pf->vfs[vf_id].vsi;
11424 PMD_DRV_LOG(ERR, "Invalid VSI.");
11428 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11430 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11431 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11433 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11434 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11437 memset(&ctxt, 0, sizeof(ctxt));
11438 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11439 ctxt.seid = vsi->seid;
11441 hw = I40E_VSI_TO_HW(vsi);
11442 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11443 if (ret != I40E_SUCCESS) {
11445 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11451 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11452 uint64_t vf_mask, uint8_t on)
11454 struct rte_eth_dev *dev;
11455 struct i40e_pf *pf;
11456 struct i40e_hw *hw;
11457 struct i40e_vsi *vsi;
11459 int ret = I40E_SUCCESS;
11461 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11463 dev = &rte_eth_devices[port];
11465 if (!is_device_supported(dev, &rte_i40e_pmd))
11468 if (vlan_id > ETHER_MAX_VLAN_ID) {
11469 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11473 if (vf_mask == 0) {
11474 PMD_DRV_LOG(ERR, "No VF.");
11479 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11483 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11484 hw = I40E_PF_TO_HW(pf);
11487 * return -ENODEV if SRIOV not enabled, VF number not configured
11488 * or no queue assigned.
11490 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11491 pf->vf_nb_qps == 0) {
11492 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11496 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11497 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11498 vsi = pf->vfs[vf_idx].vsi;
11500 if (!vsi->vlan_filter_on) {
11501 vsi->vlan_filter_on = true;
11502 if (!vsi->vlan_anti_spoof_on)
11503 i40e_add_rm_all_vlan_filter(
11506 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
11508 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11510 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11515 if (ret != I40E_SUCCESS) {
11517 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11524 rte_pmd_i40e_get_vf_stats(uint8_t port,
11526 struct rte_eth_stats *stats)
11528 struct rte_eth_dev *dev;
11529 struct i40e_pf *pf;
11530 struct i40e_vsi *vsi;
11532 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11534 dev = &rte_eth_devices[port];
11536 if (!is_device_supported(dev, &rte_i40e_pmd))
11539 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11541 if (vf_id >= pf->vf_num || !pf->vfs) {
11542 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11546 vsi = pf->vfs[vf_id].vsi;
11548 PMD_DRV_LOG(ERR, "Invalid VSI.");
11552 i40e_update_vsi_stats(vsi);
11554 stats->ipackets = vsi->eth_stats.rx_unicast +
11555 vsi->eth_stats.rx_multicast +
11556 vsi->eth_stats.rx_broadcast;
11557 stats->opackets = vsi->eth_stats.tx_unicast +
11558 vsi->eth_stats.tx_multicast +
11559 vsi->eth_stats.tx_broadcast;
11560 stats->ibytes = vsi->eth_stats.rx_bytes;
11561 stats->obytes = vsi->eth_stats.tx_bytes;
11562 stats->ierrors = vsi->eth_stats.rx_discards;
11563 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11569 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11572 struct rte_eth_dev *dev;
11573 struct i40e_pf *pf;
11574 struct i40e_vsi *vsi;
11576 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11578 dev = &rte_eth_devices[port];
11580 if (!is_device_supported(dev, &rte_i40e_pmd))
11583 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11585 if (vf_id >= pf->vf_num || !pf->vfs) {
11586 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11590 vsi = pf->vfs[vf_id].vsi;
11592 PMD_DRV_LOG(ERR, "Invalid VSI.");
11596 vsi->offset_loaded = false;
11597 i40e_update_vsi_stats(vsi);
11603 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11605 struct rte_eth_dev *dev;
11606 struct i40e_pf *pf;
11607 struct i40e_vsi *vsi;
11608 struct i40e_hw *hw;
11612 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11614 dev = &rte_eth_devices[port];
11616 if (!is_device_supported(dev, &rte_i40e_pmd))
11619 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11621 if (vf_id >= pf->vf_num || !pf->vfs) {
11622 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11626 vsi = pf->vfs[vf_id].vsi;
11628 PMD_DRV_LOG(ERR, "Invalid VSI.");
11632 if (bw > I40E_QOS_BW_MAX) {
11633 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11638 if (bw % I40E_QOS_BW_GRANULARITY) {
11639 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11640 I40E_QOS_BW_GRANULARITY);
11644 bw /= I40E_QOS_BW_GRANULARITY;
11646 hw = I40E_VSI_TO_HW(vsi);
11649 if (bw == vsi->bw_info.bw_limit) {
11651 "No change for VF max bandwidth. Nothing to do.");
11656 * VF bandwidth limitation and TC bandwidth limitation cannot be
11657 * enabled in parallel, quit if TC bandwidth limitation is enabled.
11659 * If bw is 0, means disable bandwidth limitation. Then no need to
11660 * check TC bandwidth limitation.
11663 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11664 if ((vsi->enabled_tc & BIT_ULL(i)) &&
11665 vsi->bw_info.bw_ets_credits[i])
11668 if (i != I40E_MAX_TRAFFIC_CLASS) {
11670 "TC max bandwidth has been set on this VF,"
11671 " please disable it first.");
11676 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11679 "Failed to set VF %d bandwidth, err(%d).",
11684 /* Store the configuration. */
11685 vsi->bw_info.bw_limit = (uint16_t)bw;
11686 vsi->bw_info.bw_max = 0;
11692 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11693 uint8_t tc_num, uint8_t *bw_weight)
11695 struct rte_eth_dev *dev;
11696 struct i40e_pf *pf;
11697 struct i40e_vsi *vsi;
11698 struct i40e_hw *hw;
11699 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11703 bool b_change = false;
11705 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11707 dev = &rte_eth_devices[port];
11709 if (!is_device_supported(dev, &rte_i40e_pmd))
11712 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11714 if (vf_id >= pf->vf_num || !pf->vfs) {
11715 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11719 vsi = pf->vfs[vf_id].vsi;
11721 PMD_DRV_LOG(ERR, "Invalid VSI.");
11725 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11726 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11727 I40E_MAX_TRAFFIC_CLASS);
11732 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11733 if (vsi->enabled_tc & BIT_ULL(i))
11736 if (sum != tc_num) {
11738 "Weight should be set for all %d enabled TCs.",
11744 for (i = 0; i < tc_num; i++) {
11745 if (!bw_weight[i]) {
11747 "The weight should be 1 at least.");
11750 sum += bw_weight[i];
11754 "The summary of the TC weight should be 100.");
11759 * Create the configuration for all the TCs.
11761 memset(&tc_bw, 0, sizeof(tc_bw));
11762 tc_bw.tc_valid_bits = vsi->enabled_tc;
11764 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11765 if (vsi->enabled_tc & BIT_ULL(i)) {
11766 if (bw_weight[j] !=
11767 vsi->bw_info.bw_ets_share_credits[i])
11770 tc_bw.tc_bw_credits[i] = bw_weight[j];
11778 "No change for TC allocated bandwidth."
11779 " Nothing to do.");
11783 hw = I40E_VSI_TO_HW(vsi);
11785 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11788 "Failed to set VF %d TC bandwidth weight, err(%d).",
11793 /* Store the configuration. */
11795 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11796 if (vsi->enabled_tc & BIT_ULL(i)) {
11797 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11806 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11807 uint8_t tc_no, uint32_t bw)
11809 struct rte_eth_dev *dev;
11810 struct i40e_pf *pf;
11811 struct i40e_vsi *vsi;
11812 struct i40e_hw *hw;
11813 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11817 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11819 dev = &rte_eth_devices[port];
11821 if (!is_device_supported(dev, &rte_i40e_pmd))
11824 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11826 if (vf_id >= pf->vf_num || !pf->vfs) {
11827 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11831 vsi = pf->vfs[vf_id].vsi;
11833 PMD_DRV_LOG(ERR, "Invalid VSI.");
11837 if (bw > I40E_QOS_BW_MAX) {
11838 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11843 if (bw % I40E_QOS_BW_GRANULARITY) {
11844 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11845 I40E_QOS_BW_GRANULARITY);
11849 bw /= I40E_QOS_BW_GRANULARITY;
11851 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11852 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11853 I40E_MAX_TRAFFIC_CLASS);
11857 hw = I40E_VSI_TO_HW(vsi);
11859 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11860 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11866 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11868 "No change for TC max bandwidth. Nothing to do.");
11873 * VF bandwidth limitation and TC bandwidth limitation cannot be
11874 * enabled in parallel, disable VF bandwidth limitation if it's
11876 * If bw is 0, means disable bandwidth limitation. Then no need to
11877 * care about VF bandwidth limitation configuration.
11879 if (bw && vsi->bw_info.bw_limit) {
11880 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11883 "Failed to disable VF(%d)"
11884 " bandwidth limitation, err(%d).",
11890 "VF max bandwidth is disabled according"
11891 " to TC max bandwidth setting.");
11895 * Get all the TCs' info to create a whole picture.
11896 * Because the incremental change isn't permitted.
11898 memset(&tc_bw, 0, sizeof(tc_bw));
11899 tc_bw.tc_valid_bits = vsi->enabled_tc;
11900 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11901 if (vsi->enabled_tc & BIT_ULL(i)) {
11902 tc_bw.tc_bw_credits[i] =
11904 vsi->bw_info.bw_ets_credits[i]);
11907 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11909 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11912 "Failed to set VF %d TC %d max bandwidth, err(%d).",
11913 vf_id, tc_no, ret);
11917 /* Store the configuration. */
11918 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
11924 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
11926 struct rte_eth_dev *dev;
11927 struct i40e_pf *pf;
11928 struct i40e_vsi *vsi;
11929 struct i40e_veb *veb;
11930 struct i40e_hw *hw;
11931 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
11935 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11937 dev = &rte_eth_devices[port];
11939 if (!is_device_supported(dev, &rte_i40e_pmd))
11942 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11944 vsi = pf->main_vsi;
11946 PMD_DRV_LOG(ERR, "Invalid VSI.");
11952 PMD_DRV_LOG(ERR, "Invalid VEB.");
11956 if ((tc_map & veb->enabled_tc) != tc_map) {
11958 "TC bitmap isn't the subset of enabled TCs 0x%x.",
11963 if (tc_map == veb->strict_prio_tc) {
11964 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
11968 hw = I40E_VSI_TO_HW(vsi);
11970 /* Disable DCBx if it's the first time to set strict priority. */
11971 if (!veb->strict_prio_tc) {
11972 ret = i40e_aq_stop_lldp(hw, true, NULL);
11975 "Failed to disable DCBx as it's already"
11979 "DCBx is disabled according to strict"
11980 " priority setting.");
11983 memset(&ets_data, 0, sizeof(ets_data));
11984 ets_data.tc_valid_bits = veb->enabled_tc;
11985 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
11986 ets_data.tc_strict_priority_flags = tc_map;
11987 /* Get all TCs' bandwidth. */
11988 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11989 if (veb->enabled_tc & BIT_ULL(i)) {
11990 /* For rubust, if bandwidth is 0, use 1 instead. */
11991 if (veb->bw_info.bw_ets_share_credits[i])
11992 ets_data.tc_bw_share_credits[i] =
11993 veb->bw_info.bw_ets_share_credits[i];
11995 ets_data.tc_bw_share_credits[i] =
11996 I40E_QOS_BW_WEIGHT_MIN;
12000 if (!veb->strict_prio_tc)
12001 ret = i40e_aq_config_switch_comp_ets(
12002 hw, veb->uplink_seid,
12003 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12006 ret = i40e_aq_config_switch_comp_ets(
12007 hw, veb->uplink_seid,
12008 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12011 ret = i40e_aq_config_switch_comp_ets(
12012 hw, veb->uplink_seid,
12013 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12018 "Failed to set TCs' strict priority mode."
12023 veb->strict_prio_tc = tc_map;
12025 /* Enable DCBx again, if all the TCs' strict priority disabled. */
12027 ret = i40e_aq_start_lldp(hw, NULL);
12030 "Failed to enable DCBx, err(%d).", ret);
12035 "DCBx is enabled again according to strict"
12036 " priority setting.");
12042 #define I40E_PROFILE_INFO_SIZE 48
12043 #define I40E_MAX_PROFILE_NUM 16
12046 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12047 uint32_t track_id, uint8_t *profile_info_sec,
12050 struct i40e_profile_section_header *sec = NULL;
12051 struct i40e_profile_info *pinfo;
12053 sec = (struct i40e_profile_section_header *)profile_info_sec;
12055 sec->data_end = sizeof(struct i40e_profile_section_header) +
12056 sizeof(struct i40e_profile_info);
12057 sec->section.type = SECTION_TYPE_INFO;
12058 sec->section.offset = sizeof(struct i40e_profile_section_header);
12059 sec->section.size = sizeof(struct i40e_profile_info);
12060 pinfo = (struct i40e_profile_info *)(profile_info_sec +
12061 sec->section.offset);
12062 pinfo->track_id = track_id;
12063 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12064 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12066 pinfo->op = I40E_DDP_ADD_TRACKID;
12068 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12071 static enum i40e_status_code
12072 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12074 enum i40e_status_code status = I40E_SUCCESS;
12075 struct i40e_profile_section_header *sec;
12077 uint32_t offset = 0;
12080 sec = (struct i40e_profile_section_header *)profile_info_sec;
12081 track_id = ((struct i40e_profile_info *)(profile_info_sec +
12082 sec->section.offset))->track_id;
12084 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12085 track_id, &offset, &info, NULL);
12087 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12088 "offset %d, info %d",
12094 #define I40E_PROFILE_INFO_SIZE 48
12095 #define I40E_MAX_PROFILE_NUM 16
12097 /* Check if the profile info exists */
12099 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12101 struct rte_eth_dev *dev = &rte_eth_devices[port];
12102 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12104 struct rte_pmd_i40e_profile_list *p_list;
12105 struct rte_pmd_i40e_profile_info *pinfo, *p;
12109 buff = rte_zmalloc("pinfo_list",
12110 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12113 PMD_DRV_LOG(ERR, "failed to allocate memory");
12117 ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12118 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12121 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12125 p_list = (struct rte_pmd_i40e_profile_list *)buff;
12126 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12127 sizeof(struct i40e_profile_section_header));
12128 for (i = 0; i < p_list->p_count; i++) {
12129 p = &p_list->p_info[i];
12130 if ((pinfo->track_id == p->track_id) &&
12131 !memcmp(&pinfo->version, &p->version,
12132 sizeof(struct i40e_ddp_version)) &&
12133 !memcmp(&pinfo->name, &p->name,
12134 I40E_DDP_NAME_SIZE)) {
12135 PMD_DRV_LOG(INFO, "Profile exists.");
12146 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12148 enum rte_pmd_i40e_package_op op)
12150 struct rte_eth_dev *dev;
12151 struct i40e_hw *hw;
12152 struct i40e_package_header *pkg_hdr;
12153 struct i40e_generic_seg_header *profile_seg_hdr;
12154 struct i40e_generic_seg_header *metadata_seg_hdr;
12156 uint8_t *profile_info_sec;
12158 enum i40e_status_code status = I40E_SUCCESS;
12160 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12162 dev = &rte_eth_devices[port];
12164 if (!is_device_supported(dev, &rte_i40e_pmd))
12167 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12169 if (size < (sizeof(struct i40e_package_header) +
12170 sizeof(struct i40e_metadata_segment) +
12171 sizeof(uint32_t) * 2)) {
12172 PMD_DRV_LOG(ERR, "Buff is invalid.");
12176 pkg_hdr = (struct i40e_package_header *)buff;
12179 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12183 if (pkg_hdr->segment_count < 2) {
12184 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12188 /* Find metadata segment */
12189 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12191 if (!metadata_seg_hdr) {
12192 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12195 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12197 /* Find profile segment */
12198 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12200 if (!profile_seg_hdr) {
12201 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12205 profile_info_sec = rte_zmalloc("i40e_profile_info",
12206 sizeof(struct i40e_profile_section_header) +
12207 sizeof(struct i40e_profile_info),
12209 if (!profile_info_sec) {
12210 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12214 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12215 /* Check if the profile exists */
12216 i40e_generate_profile_info_sec(
12217 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12218 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12219 track_id, profile_info_sec, 1);
12220 is_exist = i40e_check_profile_info(port, profile_info_sec);
12221 if (is_exist > 0) {
12222 PMD_DRV_LOG(ERR, "Profile already exists.");
12223 rte_free(profile_info_sec);
12225 } else if (is_exist < 0) {
12226 PMD_DRV_LOG(ERR, "Failed to check profile.");
12227 rte_free(profile_info_sec);
12231 /* Write profile to HW */
12232 status = i40e_write_profile(hw,
12233 (struct i40e_profile_segment *)profile_seg_hdr,
12236 PMD_DRV_LOG(ERR, "Failed to write profile.");
12237 rte_free(profile_info_sec);
12241 /* Add profile info to info list */
12242 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12244 PMD_DRV_LOG(ERR, "Failed to add profile info.");
12246 PMD_DRV_LOG(ERR, "Operation not supported.");
12248 rte_free(profile_info_sec);
12253 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12255 struct rte_eth_dev *dev;
12256 struct i40e_hw *hw;
12257 enum i40e_status_code status = I40E_SUCCESS;
12259 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12261 dev = &rte_eth_devices[port];
12263 if (!is_device_supported(dev, &rte_i40e_pmd))
12266 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12269 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12271 status = i40e_aq_get_ddp_list(hw, (void *)buff,