drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30 #include <rte_os_shim.h>
  31
  32 #include "i40e_logs.h"
  33 #include "base/i40e_prototype.h"
  34 #include "base/i40e_adminq_cmd.h"
  35 #include "base/i40e_type.h"
  36 #include "base/i40e_register.h"
  37 #include "base/i40e_dcb.h"
  38 #include "i40e_ethdev.h"
  39 #include "i40e_rxtx.h"
  40 #include "i40e_pf.h"
  41 #include "i40e_regs.h"
  42 #include "rte_pmd_i40e.h"
  43 #include "i40e_hash.h"
  44
  45 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  46 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  47 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  49 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  50
  51 #define I40E_CLEAR_PXE_WAIT_MS     200
  52 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  53 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  54
  55 /* Maximun number of capability elements */
  56 #define I40E_MAX_CAP_ELE_NUM       128
  57
  58 /* Wait count and interval */
  59 #define I40E_CHK_Q_ENA_COUNT       1000
  60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  61
  62 /* Maximun number of VSI */
  63 #define I40E_MAX_NUM_VSIS          (384UL)
  64
  65 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  66
  67 /* Flow control default timer */
  68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  69
  70 /* Flow control enable fwd bit */
  71 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  72
  73 /* Receive Packet Buffer size */
  74 #define I40E_RXPBSIZE (968 * 1024)
  75
  76 /* Kilobytes shift */
  77 #define I40E_KILOSHIFT 10
  78
  79 /* Flow control default high water */
  80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Flow control default low water */
  83 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  84
  85 /* Receive Average Packet Size in Byte*/
  86 #define I40E_PACKET_AVERAGE_SIZE 128
  87
  88 /* Mask of PF interrupt causes */
  89 #define I40E_PFINT_ICR0_ENA_MASK ( \
  90                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  94                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  95                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  98                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  99
 100 #define I40E_FLOW_TYPES ( \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 110         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 111         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 112
 113 /* Additional timesync values. */
 114 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 115 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 116 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 117 #define I40E_PRTTSYN_TSYNENA     0x80000000
 118 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 119 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 120
 121 /**
 122  * Below are values for writing un-exposed registers suggested
 123  * by silicon experts
 124  */
 125 /* Destination MAC address */
 126 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 127 /* Source MAC address */
 128 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 130 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 132 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 133 /* Single VLAN tag in the inner L2 header */
 134 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 135 /* Source IPv4 address */
 136 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 137 /* Destination IPv4 address */
 138 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 139 /* Source IPv4 address for X722 */
 140 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 141 /* Destination IPv4 address for X722 */
 142 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 143 /* IPv4 Protocol for X722 */
 144 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 145 /* IPv4 Time to Live for X722 */
 146 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 147 /* IPv4 Type of Service (TOS) */
 148 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 149 /* IPv4 Protocol */
 150 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 151 /* IPv4 Time to Live */
 152 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 153 /* Source IPv6 address */
 154 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 155 /* Destination IPv6 address */
 156 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 157 /* IPv6 Traffic Class (TC) */
 158 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 159 /* IPv6 Next Header */
 160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 161 /* IPv6 Hop Limit */
 162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 163 /* Source L4 port */
 164 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 165 /* Destination L4 port */
 166 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 167 /* SCTP verification tag */
 168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 171 /* Source port of tunneling UDP */
 172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 173 /* Destination port of tunneling UDP */
 174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 175 /* UDP Tunneling ID, NVGRE/GRE key */
 176 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 177 /* Last ether type */
 178 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 179 /* Tunneling outer destination IPv4 address */
 180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 181 /* Tunneling outer destination IPv6 address */
 182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 183 /* 1st word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 185 /* 2nd word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 187 /* 3rd word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 189 /* 4th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 191 /* 5th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 193 /* 6th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 195 /* 7th word of flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 197 /* 8th word of flex payload */
 198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 199 /* all 8 words flex payload */
 200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 201 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 202
 203 #define I40E_TRANSLATE_INSET 0
 204 #define I40E_TRANSLATE_REG   1
 205
 206 #define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
 207 #define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
 208 #define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
 209 #define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
 210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
 211 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 212
 213 /* PCI offset for querying capability */
 214 #define PCI_DEV_CAP_REG            0xA4
 215 /* PCI offset for enabling/disabling Extended Tag */
 216 #define PCI_DEV_CTRL_REG           0xA8
 217 /* Bit mask of Extended Tag capability */
 218 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 219 /* Bit shift of Extended Tag enable/disable */
 220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 221 /* Bit mask of Extended Tag enable/disable */
 222 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 223
 224 #define I40E_GLQF_PIT_IPV4_START        2
 225 #define I40E_GLQF_PIT_IPV4_COUNT        2
 226 #define I40E_GLQF_PIT_IPV6_START        4
 227 #define I40E_GLQF_PIT_IPV6_COUNT        2
 228
 229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
 230                                 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
 231                                  I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
 232
 233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
 234                                 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
 235                                  I40E_GLQF_PIT_DEST_OFF_SHIFT)
 236
 237 #define I40E_GLQF_PIT_FSIZE_GET(a)      (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
 238                                          I40E_GLQF_PIT_FSIZE_SHIFT)
 239
 240 #define I40E_GLQF_PIT_BUILD(off, mask)  (((off) << 16) | (mask))
 241 #define I40E_FDIR_FIELD_OFFSET(a)       ((a) >> 1)
 242
 243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 245 static int i40e_dev_configure(struct rte_eth_dev *dev);
 246 static int i40e_dev_start(struct rte_eth_dev *dev);
 247 static int i40e_dev_stop(struct rte_eth_dev *dev);
 248 static int i40e_dev_close(struct rte_eth_dev *dev);
 249 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 257                                struct rte_eth_stats *stats);
 258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_xstat *xstats, unsigned n);
 260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 261                                      struct rte_eth_xstat_name *xstats_names,
 262                                      unsigned limit);
 263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 265                                 char *fw_version, size_t fw_size);
 266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 267                              struct rte_eth_dev_info *dev_info);
 268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 269                                 uint16_t vlan_id,
 270                                 int on);
 271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 272                               enum rte_vlan_type vlan_type,
 273                               uint16_t tpid);
 274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 276                                       uint16_t queue,
 277                                       int on);
 278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 282                               struct rte_eth_fc_conf *fc_conf);
 283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 284                               struct rte_eth_fc_conf *fc_conf);
 285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 286                                        struct rte_eth_pfc_conf *pfc_conf);
 287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 288                             struct rte_ether_addr *mac_addr,
 289                             uint32_t index,
 290                             uint32_t pool);
 291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 293                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 294                                     uint16_t reta_size);
 295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 296                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 297                                    uint16_t reta_size);
 298
 299 static int i40e_get_cap(struct i40e_hw *hw);
 300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 301 static int i40e_pf_setup(struct i40e_pf *pf);
 302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 306                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 307 static void i40e_stat_update_48(struct i40e_hw *hw,
 308                                uint32_t hireg,
 309                                uint32_t loreg,
 310                                bool offset_loaded,
 311                                uint64_t *offset,
 312                                uint64_t *stat);
 313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 314 static void i40e_dev_interrupt_handler(void *param);
 315 static void i40e_dev_alarm_handler(void *param);
 316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 317                                 uint32_t base, uint32_t num);
 318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 320                         uint32_t base);
 321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 322                         uint16_t num);
 323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 324 static int i40e_veb_release(struct i40e_veb *veb);
 325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 326                                                 struct i40e_vsi *vsi);
 327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 329                                              struct i40e_macvlan_filter *mv_f,
 330                                              int num,
 331                                              uint16_t vlan);
 332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 334                                     struct rte_eth_rss_conf *rss_conf);
 335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 336                                       struct rte_eth_rss_conf *rss_conf);
 337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 338                                         struct rte_eth_udp_tunnel *udp_tunnel);
 339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 340                                         struct rte_eth_udp_tunnel *udp_tunnel);
 341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
 343                                  const struct rte_flow_ops **ops);
 344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                   struct rte_eth_dcb_info *dcb_info);
 346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 347 static void i40e_configure_registers(struct i40e_hw *hw);
 348 static void i40e_hw_init(struct rte_eth_dev *dev);
 349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 350
 351 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 352 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 353 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp,
 355                                            uint32_t flags);
 356 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                            struct timespec *timestamp);
 358 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 359
 360 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 361
 362 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 363                                    struct timespec *timestamp);
 364 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 365                                     const struct timespec *timestamp);
 366
 367 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 368                                          uint16_t queue_id);
 369 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 370                                           uint16_t queue_id);
 371
 372 static int i40e_get_regs(struct rte_eth_dev *dev,
 373                          struct rte_dev_reg_info *regs);
 374
 375 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 376
 377 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 378                            struct rte_dev_eeprom_info *eeprom);
 379
 380 static int i40e_get_module_info(struct rte_eth_dev *dev,
 381                                 struct rte_eth_dev_module_info *modinfo);
 382 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 383                                   struct rte_dev_eeprom_info *info);
 384
 385 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 386                                       struct rte_ether_addr *mac_addr);
 387
 388 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 389
 390 static int i40e_ethertype_filter_convert(
 391         const struct rte_eth_ethertype_filter *input,
 392         struct i40e_ethertype_filter *filter);
 393 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 394                                    struct i40e_ethertype_filter *filter);
 395
 396 static int i40e_tunnel_filter_convert(
 397         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 398         struct i40e_tunnel_filter *tunnel_filter);
 399 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 400                                 struct i40e_tunnel_filter *tunnel_filter);
 401 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 402
 403 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 404 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 405 static void i40e_filter_restore(struct i40e_pf *pf);
 406 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 407
 408 static const char *const valid_keys[] = {
 409         ETH_I40E_FLOATING_VEB_ARG,
 410         ETH_I40E_FLOATING_VEB_LIST_ARG,
 411         ETH_I40E_SUPPORT_MULTI_DRIVER,
 412         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 413         ETH_I40E_VF_MSG_CFG,
 414         NULL};
 415
 416 static const struct rte_pci_id pci_id_i40e_map[] = {
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .dev_reset                    = i40e_dev_reset,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 481         .tx_queue_release             = i40e_dev_tx_queue_release,
 482         .dev_led_on                   = i40e_dev_led_on,
 483         .dev_led_off                  = i40e_dev_led_off,
 484         .flow_ctrl_get                = i40e_flow_ctrl_get,
 485         .flow_ctrl_set                = i40e_flow_ctrl_set,
 486         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 487         .mac_addr_add                 = i40e_macaddr_add,
 488         .mac_addr_remove              = i40e_macaddr_remove,
 489         .reta_update                  = i40e_dev_rss_reta_update,
 490         .reta_query                   = i40e_dev_rss_reta_query,
 491         .rss_hash_update              = i40e_dev_rss_hash_update,
 492         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 493         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 494         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 495         .flow_ops_get                 = i40e_dev_flow_ops_get,
 496         .rxq_info_get                 = i40e_rxq_info_get,
 497         .txq_info_get                 = i40e_txq_info_get,
 498         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 499         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 500         .timesync_enable              = i40e_timesync_enable,
 501         .timesync_disable             = i40e_timesync_disable,
 502         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 503         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 504         .get_dcb_info                 = i40e_dev_get_dcb_info,
 505         .timesync_adjust_time         = i40e_timesync_adjust_time,
 506         .timesync_read_time           = i40e_timesync_read_time,
 507         .timesync_write_time          = i40e_timesync_write_time,
 508         .get_reg                      = i40e_get_regs,
 509         .get_eeprom_length            = i40e_get_eeprom_length,
 510         .get_eeprom                   = i40e_get_eeprom,
 511         .get_module_info              = i40e_get_module_info,
 512         .get_module_eeprom            = i40e_get_module_eeprom,
 513         .mac_addr_set                 = i40e_set_default_mac_addr,
 514         .mtu_set                      = i40e_dev_mtu_set,
 515         .tm_ops_get                   = i40e_tm_ops_get,
 516         .tx_done_cleanup              = i40e_tx_done_cleanup,
 517         .get_monitor_addr             = i40e_get_monitor_addr,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         int offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"rx_size_error_packets", offsetof(struct i40e_pf, rx_err1) -
 534                                   offsetof(struct i40e_pf, stats)},
 535         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 536         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 537         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 538         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 539 };
 540
 541 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 542                 sizeof(rte_i40e_stats_strings[0]))
 543
 544 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 545         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 546                 tx_dropped_link_down)},
 547         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 548         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 549                 illegal_bytes)},
 550         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 551         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_local_faults)},
 553         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 554                 mac_remote_faults)},
 555         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_length_errors)},
 557         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 558         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 559         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 560         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 561         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 562         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_127)},
 564         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_255)},
 566         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_511)},
 568         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1023)},
 570         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_1522)},
 572         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_big)},
 574         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_undersize)},
 576         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 577                 rx_oversize)},
 578         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 579                 mac_short_packet_dropped)},
 580         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 581                 rx_fragments)},
 582         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 583         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 584         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_127)},
 586         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_255)},
 588         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_511)},
 590         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1023)},
 592         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_1522)},
 594         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_big)},
 596         {"rx_flow_director_atr_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 598         {"rx_flow_director_sb_match_packets",
 599                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 600         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 tx_lpi_status)},
 602         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 603                 rx_lpi_status)},
 604         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 tx_lpi_count)},
 606         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 607                 rx_lpi_count)},
 608 };
 609
 610 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 611                 sizeof(rte_i40e_hw_port_strings[0]))
 612
 613 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 614         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xon_rx)},
 616         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 617                 priority_xoff_rx)},
 618 };
 619
 620 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 621                 sizeof(rte_i40e_rxq_prio_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_tx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_tx)},
 628         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 629                 priority_xon_2_xoff)},
 630 };
 631
 632 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 633                 sizeof(rte_i40e_txq_prio_strings[0]))
 634
 635 static int
 636 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 637         struct rte_pci_device *pci_dev)
 638 {
 639         char name[RTE_ETH_NAME_MAX_LEN];
 640         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 641         int i, retval;
 642
 643         if (pci_dev->device.devargs) {
 644                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 645                                 &eth_da);
 646                 if (retval)
 647                         return retval;
 648         }
 649
 650         if (eth_da.nb_representor_ports > 0 &&
 651             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
 652                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
 653                             pci_dev->device.devargs->args);
 654                 return -ENOTSUP;
 655         }
 656
 657         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 658                 sizeof(struct i40e_adapter),
 659                 eth_dev_pci_specific_init, pci_dev,
 660                 eth_i40e_dev_init, NULL);
 661
 662         if (retval || eth_da.nb_representor_ports < 1)
 663                 return retval;
 664
 665         /* probe VF representor ports */
 666         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 667                 pci_dev->device.name);
 668
 669         if (pf_ethdev == NULL)
 670                 return -ENODEV;
 671
 672         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 673                 struct i40e_vf_representor representor = {
 674                         .vf_id = eth_da.representor_ports[i],
 675                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 676                                 pf_ethdev->data->dev_private)->switch_domain_id,
 677                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 678                                 pf_ethdev->data->dev_private)
 679                 };
 680
 681                 /* representor port net_bdf_port */
 682                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 683                         pci_dev->device.name, eth_da.representor_ports[i]);
 684
 685                 retval = rte_eth_dev_create(&pci_dev->device, name,
 686                         sizeof(struct i40e_vf_representor), NULL, NULL,
 687                         i40e_vf_representor_init, &representor);
 688
 689                 if (retval)
 690                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 691                                 "representor %s.", name);
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 698 {
 699         struct rte_eth_dev *ethdev;
 700
 701         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 702         if (!ethdev)
 703                 return 0;
 704
 705         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 706                 return rte_eth_dev_pci_generic_remove(pci_dev,
 707                                         i40e_vf_representor_uninit);
 708         else
 709                 return rte_eth_dev_pci_generic_remove(pci_dev,
 710                                                 eth_i40e_dev_uninit);
 711 }
 712
 713 static struct rte_pci_driver rte_i40e_pmd = {
 714         .id_table = pci_id_i40e_map,
 715         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 716         .probe = eth_i40e_pci_probe,
 717         .remove = eth_i40e_pci_remove,
 718 };
 719
 720 static inline void
 721 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 722                          uint32_t reg_val)
 723 {
 724         uint32_t ori_reg_val;
 725         struct rte_eth_dev_data *dev_data =
 726                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
 727         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
 728
 729         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 730         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 731         if (ori_reg_val != reg_val)
 732                 PMD_DRV_LOG(WARNING,
 733                             "i40e device %s changed global register [0x%08x]."
 734                             " original: 0x%08x, new: 0x%08x",
 735                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 736 }
 737
 738 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 739 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 740 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 741
 742 #ifndef I40E_GLQF_ORT
 743 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 744 #endif
 745 #ifndef I40E_GLQF_PIT
 746 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 747 #endif
 748 #ifndef I40E_GLQF_L3_MAP
 749 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 750 #endif
 751
 752 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 753 {
 754         /*
 755          * Initialize registers for parsing packet type of QinQ
 756          * This should be removed from code once proper
 757          * configuration API is added to avoid configuration conflicts
 758          * between ports of the same device.
 759          */
 760         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 762 }
 763
 764 static inline void i40e_config_automask(struct i40e_pf *pf)
 765 {
 766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 767         uint32_t val;
 768
 769         /* INTENA flag is not auto-cleared for interrupt */
 770         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 771         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 772                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 773
 774         /* If support multi-driver, PF will use INT0. */
 775         if (!pf->support_multi_driver)
 776                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 777
 778         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 779 }
 780
 781 static inline void i40e_clear_automask(struct i40e_pf *pf)
 782 {
 783         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 784         uint32_t val;
 785
 786         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 787         val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 788                  I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
 789
 790         if (!pf->support_multi_driver)
 791                 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 792
 793         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 794 }
 795
 796 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 797
 798 /*
 799  * Add a ethertype filter to drop all flow control frames transmitted
 800  * from VSIs.
 801 */
 802 static void
 803 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 804 {
 805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 806         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 807                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 808                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 809         int ret;
 810
 811         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 812                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 813                                 pf->main_vsi_seid, 0,
 814                                 TRUE, NULL, NULL);
 815         if (ret)
 816                 PMD_INIT_LOG(ERR,
 817                         "Failed to add filter to drop flow control frames from VSIs.");
 818 }
 819
 820 static int
 821 floating_veb_list_handler(__rte_unused const char *key,
 822                           const char *floating_veb_value,
 823                           void *opaque)
 824 {
 825         int idx = 0;
 826         unsigned int count = 0;
 827         char *end = NULL;
 828         int min, max;
 829         bool *vf_floating_veb = opaque;
 830
 831         while (isblank(*floating_veb_value))
 832                 floating_veb_value++;
 833
 834         /* Reset floating VEB configuration for VFs */
 835         for (idx = 0; idx < I40E_MAX_VF; idx++)
 836                 vf_floating_veb[idx] = false;
 837
 838         min = I40E_MAX_VF;
 839         do {
 840                 while (isblank(*floating_veb_value))
 841                         floating_veb_value++;
 842                 if (*floating_veb_value == '\0')
 843                         return -1;
 844                 errno = 0;
 845                 idx = strtoul(floating_veb_value, &end, 10);
 846                 if (errno || end == NULL)
 847                         return -1;
 848                 if (idx < 0)
 849                         return -1;
 850                 while (isblank(*end))
 851                         end++;
 852                 if (*end == '-') {
 853                         min = idx;
 854                 } else if ((*end == ';') || (*end == '\0')) {
 855                         max = idx;
 856                         if (min == I40E_MAX_VF)
 857                                 min = idx;
 858                         if (max >= I40E_MAX_VF)
 859                                 max = I40E_MAX_VF - 1;
 860                         for (idx = min; idx <= max; idx++) {
 861                                 vf_floating_veb[idx] = true;
 862                                 count++;
 863                         }
 864                         min = I40E_MAX_VF;
 865                 } else {
 866                         return -1;
 867                 }
 868                 floating_veb_value = end + 1;
 869         } while (*end != '\0');
 870
 871         if (count == 0)
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 static void
 878 config_vf_floating_veb(struct rte_devargs *devargs,
 879                        uint16_t floating_veb,
 880                        bool *vf_floating_veb)
 881 {
 882         struct rte_kvargs *kvlist;
 883         int i;
 884         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 885
 886         if (!floating_veb)
 887                 return;
 888         /* All the VFs attach to the floating VEB by default
 889          * when the floating VEB is enabled.
 890          */
 891         for (i = 0; i < I40E_MAX_VF; i++)
 892                 vf_floating_veb[i] = true;
 893
 894         if (devargs == NULL)
 895                 return;
 896
 897         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 898         if (kvlist == NULL)
 899                 return;
 900
 901         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 902                 rte_kvargs_free(kvlist);
 903                 return;
 904         }
 905         /* When the floating_veb_list parameter exists, all the VFs
 906          * will attach to the legacy VEB firstly, then configure VFs
 907          * to the floating VEB according to the floating_veb_list.
 908          */
 909         if (rte_kvargs_process(kvlist, floating_veb_list,
 910                                floating_veb_list_handler,
 911                                vf_floating_veb) < 0) {
 912                 rte_kvargs_free(kvlist);
 913                 return;
 914         }
 915         rte_kvargs_free(kvlist);
 916 }
 917
 918 static int
 919 i40e_check_floating_handler(__rte_unused const char *key,
 920                             const char *value,
 921                             __rte_unused void *opaque)
 922 {
 923         if (strcmp(value, "1"))
 924                 return -1;
 925
 926         return 0;
 927 }
 928
 929 static int
 930 is_floating_veb_supported(struct rte_devargs *devargs)
 931 {
 932         struct rte_kvargs *kvlist;
 933         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 934
 935         if (devargs == NULL)
 936                 return 0;
 937
 938         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 939         if (kvlist == NULL)
 940                 return 0;
 941
 942         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 943                 rte_kvargs_free(kvlist);
 944                 return 0;
 945         }
 946         /* Floating VEB is enabled when there's key-value:
 947          * enable_floating_veb=1
 948          */
 949         if (rte_kvargs_process(kvlist, floating_veb_key,
 950                                i40e_check_floating_handler, NULL) < 0) {
 951                 rte_kvargs_free(kvlist);
 952                 return 0;
 953         }
 954         rte_kvargs_free(kvlist);
 955
 956         return 1;
 957 }
 958
 959 static void
 960 config_floating_veb(struct rte_eth_dev *dev)
 961 {
 962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 963         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 965
 966         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 967
 968         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 969                 pf->floating_veb =
 970                         is_floating_veb_supported(pci_dev->device.devargs);
 971                 config_vf_floating_veb(pci_dev->device.devargs,
 972                                        pf->floating_veb,
 973                                        pf->floating_veb_list);
 974         } else {
 975                 pf->floating_veb = false;
 976         }
 977 }
 978
 979 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 980 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 981
 982 static int
 983 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 984 {
 985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 986         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 987         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 988         int ret;
 989
 990         struct rte_hash_parameters ethertype_hash_params = {
 991                 .name = ethertype_hash_name,
 992                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 993                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 994                 .hash_func = rte_hash_crc,
 995                 .hash_func_init_val = 0,
 996                 .socket_id = rte_socket_id(),
 997         };
 998
 999         /* Initialize ethertype filter rule list and hash */
1000         TAILQ_INIT(&ethertype_rule->ethertype_list);
1001         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1002                  "ethertype_%s", dev->device->name);
1003         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
1004         if (!ethertype_rule->hash_table) {
1005                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1006                 return -EINVAL;
1007         }
1008         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1009                                        sizeof(struct i40e_ethertype_filter *) *
1010                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
1011                                        0);
1012         if (!ethertype_rule->hash_map) {
1013                 PMD_INIT_LOG(ERR,
1014                              "Failed to allocate memory for ethertype hash map!");
1015                 ret = -ENOMEM;
1016                 goto err_ethertype_hash_map_alloc;
1017         }
1018
1019         return 0;
1020
1021 err_ethertype_hash_map_alloc:
1022         rte_hash_free(ethertype_rule->hash_table);
1023
1024         return ret;
1025 }
1026
1027 static int
1028 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1029 {
1030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1032         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1033         int ret;
1034
1035         struct rte_hash_parameters tunnel_hash_params = {
1036                 .name = tunnel_hash_name,
1037                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1038                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1039                 .hash_func = rte_hash_crc,
1040                 .hash_func_init_val = 0,
1041                 .socket_id = rte_socket_id(),
1042         };
1043
1044         /* Initialize tunnel filter rule list and hash */
1045         TAILQ_INIT(&tunnel_rule->tunnel_list);
1046         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1047                  "tunnel_%s", dev->device->name);
1048         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1049         if (!tunnel_rule->hash_table) {
1050                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1051                 return -EINVAL;
1052         }
1053         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1054                                     sizeof(struct i40e_tunnel_filter *) *
1055                                     I40E_MAX_TUNNEL_FILTER_NUM,
1056                                     0);
1057         if (!tunnel_rule->hash_map) {
1058                 PMD_INIT_LOG(ERR,
1059                              "Failed to allocate memory for tunnel hash map!");
1060                 ret = -ENOMEM;
1061                 goto err_tunnel_hash_map_alloc;
1062         }
1063
1064         return 0;
1065
1066 err_tunnel_hash_map_alloc:
1067         rte_hash_free(tunnel_rule->hash_table);
1068
1069         return ret;
1070 }
1071
1072 static int
1073 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1074 {
1075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1077         struct i40e_fdir_info *fdir_info = &pf->fdir;
1078         char fdir_hash_name[RTE_HASH_NAMESIZE];
1079         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1080         uint32_t best = hw->func_caps.fd_filters_best_effort;
1081         enum i40e_filter_pctype pctype;
1082         struct rte_bitmap *bmp = NULL;
1083         uint32_t bmp_size;
1084         void *mem = NULL;
1085         uint32_t i = 0;
1086         int ret;
1087
1088         struct rte_hash_parameters fdir_hash_params = {
1089                 .name = fdir_hash_name,
1090                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1091                 .key_len = sizeof(struct i40e_fdir_input),
1092                 .hash_func = rte_hash_crc,
1093                 .hash_func_init_val = 0,
1094                 .socket_id = rte_socket_id(),
1095         };
1096
1097         /* Initialize flow director filter rule list and hash */
1098         TAILQ_INIT(&fdir_info->fdir_list);
1099         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1100                  "fdir_%s", dev->device->name);
1101         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1102         if (!fdir_info->hash_table) {
1103                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1104                 return -EINVAL;
1105         }
1106
1107         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1108                                           sizeof(struct i40e_fdir_filter *) *
1109                                           I40E_MAX_FDIR_FILTER_NUM,
1110                                           0);
1111         if (!fdir_info->hash_map) {
1112                 PMD_INIT_LOG(ERR,
1113                              "Failed to allocate memory for fdir hash map!");
1114                 ret = -ENOMEM;
1115                 goto err_fdir_hash_map_alloc;
1116         }
1117
1118         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1119                         sizeof(struct i40e_fdir_filter) *
1120                         I40E_MAX_FDIR_FILTER_NUM,
1121                         0);
1122
1123         if (!fdir_info->fdir_filter_array) {
1124                 PMD_INIT_LOG(ERR,
1125                              "Failed to allocate memory for fdir filter array!");
1126                 ret = -ENOMEM;
1127                 goto err_fdir_filter_array_alloc;
1128         }
1129
1130         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1131              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1132                 pf->fdir.flow_count[pctype] = 0;
1133
1134         fdir_info->fdir_space_size = alloc + best;
1135         fdir_info->fdir_actual_cnt = 0;
1136         fdir_info->fdir_guarantee_total_space = alloc;
1137         fdir_info->fdir_guarantee_free_space =
1138                 fdir_info->fdir_guarantee_total_space;
1139
1140         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1141
1142         fdir_info->fdir_flow_pool.pool =
1143                         rte_zmalloc("i40e_fdir_entry",
1144                                 sizeof(struct i40e_fdir_entry) *
1145                                 fdir_info->fdir_space_size,
1146                                 0);
1147
1148         if (!fdir_info->fdir_flow_pool.pool) {
1149                 PMD_INIT_LOG(ERR,
1150                              "Failed to allocate memory for bitmap flow!");
1151                 ret = -ENOMEM;
1152                 goto err_fdir_bitmap_flow_alloc;
1153         }
1154
1155         for (i = 0; i < fdir_info->fdir_space_size; i++)
1156                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1157
1158         bmp_size =
1159                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1160         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1161         if (mem == NULL) {
1162                 PMD_INIT_LOG(ERR,
1163                              "Failed to allocate memory for fdir bitmap!");
1164                 ret = -ENOMEM;
1165                 goto err_fdir_mem_alloc;
1166         }
1167         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1168         if (bmp == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                              "Failed to initialization fdir bitmap!");
1171                 ret = -ENOMEM;
1172                 goto err_fdir_bmp_alloc;
1173         }
1174         for (i = 0; i < fdir_info->fdir_space_size; i++)
1175                 rte_bitmap_set(bmp, i);
1176
1177         fdir_info->fdir_flow_pool.bitmap = bmp;
1178
1179         return 0;
1180
1181 err_fdir_bmp_alloc:
1182         rte_free(mem);
1183 err_fdir_mem_alloc:
1184         rte_free(fdir_info->fdir_flow_pool.pool);
1185 err_fdir_bitmap_flow_alloc:
1186         rte_free(fdir_info->fdir_filter_array);
1187 err_fdir_filter_array_alloc:
1188         rte_free(fdir_info->hash_map);
1189 err_fdir_hash_map_alloc:
1190         rte_hash_free(fdir_info->hash_table);
1191
1192         return ret;
1193 }
1194
1195 static void
1196 i40e_init_customized_info(struct i40e_pf *pf)
1197 {
1198         int i;
1199
1200         /* Initialize customized pctype */
1201         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1202                 pf->customized_pctype[i].index = i;
1203                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1204                 pf->customized_pctype[i].valid = false;
1205         }
1206
1207         pf->gtp_support = false;
1208         pf->esp_support = false;
1209 }
1210
1211 static void
1212 i40e_init_filter_invalidation(struct i40e_pf *pf)
1213 {
1214         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1215         struct i40e_fdir_info *fdir_info = &pf->fdir;
1216         uint32_t glqf_ctl_reg = 0;
1217
1218         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1219         if (!pf->support_multi_driver) {
1220                 fdir_info->fdir_invalprio = 1;
1221                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1222                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1223                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1224         } else {
1225                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1226                         fdir_info->fdir_invalprio = 1;
1227                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1228                 } else {
1229                         fdir_info->fdir_invalprio = 0;
1230                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1231                 }
1232         }
1233 }
1234
1235 void
1236 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1237 {
1238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240         struct i40e_queue_regions *info = &pf->queue_region;
1241         uint16_t i;
1242
1243         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1244                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1245
1246         memset(info, 0, sizeof(struct i40e_queue_regions));
1247 }
1248
1249 static int
1250 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1251                                const char *value,
1252                                void *opaque)
1253 {
1254         struct i40e_pf *pf;
1255         unsigned long support_multi_driver;
1256         char *end;
1257
1258         pf = (struct i40e_pf *)opaque;
1259
1260         errno = 0;
1261         support_multi_driver = strtoul(value, &end, 10);
1262         if (errno != 0 || end == value || *end != 0) {
1263                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1264                 return -(EINVAL);
1265         }
1266
1267         if (support_multi_driver == 1 || support_multi_driver == 0)
1268                 pf->support_multi_driver = (bool)support_multi_driver;
1269         else
1270                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1271                             "enable global configuration by default."
1272                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1273         return 0;
1274 }
1275
1276 static int
1277 i40e_support_multi_driver(struct rte_eth_dev *dev)
1278 {
1279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1280         struct rte_kvargs *kvlist;
1281         int kvargs_count;
1282
1283         /* Enable global configuration by default */
1284         pf->support_multi_driver = false;
1285
1286         if (!dev->device->devargs)
1287                 return 0;
1288
1289         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1290         if (!kvlist)
1291                 return -EINVAL;
1292
1293         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1294         if (!kvargs_count) {
1295                 rte_kvargs_free(kvlist);
1296                 return 0;
1297         }
1298
1299         if (kvargs_count > 1)
1300                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1301                             "the first invalid or last valid one is used !",
1302                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1303
1304         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1305                                i40e_parse_multi_drv_handler, pf) < 0) {
1306                 rte_kvargs_free(kvlist);
1307                 return -EINVAL;
1308         }
1309
1310         rte_kvargs_free(kvlist);
1311         return 0;
1312 }
1313
1314 static int
1315 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1316                                     uint32_t reg_addr, uint64_t reg_val,
1317                                     struct i40e_asq_cmd_details *cmd_details)
1318 {
1319         uint64_t ori_reg_val;
1320         struct rte_eth_dev_data *dev_data =
1321                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
1322         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
1323         int ret;
1324
1325         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1326         if (ret != I40E_SUCCESS) {
1327                 PMD_DRV_LOG(ERR,
1328                             "Fail to debug read from 0x%08x",
1329                             reg_addr);
1330                 return -EIO;
1331         }
1332
1333         if (ori_reg_val != reg_val)
1334                 PMD_DRV_LOG(WARNING,
1335                             "i40e device %s changed global register [0x%08x]."
1336                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1337                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1338
1339         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1340 }
1341
1342 static int
1343 read_vf_msg_config(__rte_unused const char *key,
1344                                const char *value,
1345                                void *opaque)
1346 {
1347         struct i40e_vf_msg_cfg *cfg = opaque;
1348
1349         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1350                         &cfg->ignore_second) != 3) {
1351                 memset(cfg, 0, sizeof(*cfg));
1352                 PMD_DRV_LOG(ERR, "format error! example: "
1353                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1354                 return -EINVAL;
1355         }
1356
1357         /*
1358          * If the message validation function been enabled, the 'period'
1359          * and 'ignore_second' must greater than 0.
1360          */
1361         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1362                 memset(cfg, 0, sizeof(*cfg));
1363                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1364                                 " number must be greater than 0!",
1365                                 ETH_I40E_VF_MSG_CFG);
1366                 return -EINVAL;
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int
1373 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1374                 struct i40e_vf_msg_cfg *msg_cfg)
1375 {
1376         struct rte_kvargs *kvlist;
1377         int kvargs_count;
1378         int ret = 0;
1379
1380         memset(msg_cfg, 0, sizeof(*msg_cfg));
1381
1382         if (!dev->device->devargs)
1383                 return ret;
1384
1385         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1386         if (!kvlist)
1387                 return -EINVAL;
1388
1389         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1390         if (!kvargs_count)
1391                 goto free_end;
1392
1393         if (kvargs_count > 1) {
1394                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1395                                 ETH_I40E_VF_MSG_CFG);
1396                 ret = -EINVAL;
1397                 goto free_end;
1398         }
1399
1400         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1401                         read_vf_msg_config, msg_cfg) < 0)
1402                 ret = -EINVAL;
1403
1404 free_end:
1405         rte_kvargs_free(kvlist);
1406         return ret;
1407 }
1408
1409 #define I40E_ALARM_INTERVAL 50000 /* us */
1410
1411 static int
1412 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1413 {
1414         struct rte_pci_device *pci_dev;
1415         struct rte_intr_handle *intr_handle;
1416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418         struct i40e_vsi *vsi;
1419         int ret;
1420         uint32_t len, val;
1421         uint8_t aq_fail = 0;
1422
1423         PMD_INIT_FUNC_TRACE();
1424
1425         dev->dev_ops = &i40e_eth_dev_ops;
1426         dev->rx_queue_count = i40e_dev_rx_queue_count;
1427         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1428         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1429         dev->rx_pkt_burst = i40e_recv_pkts;
1430         dev->tx_pkt_burst = i40e_xmit_pkts;
1431         dev->tx_pkt_prepare = i40e_prep_pkts;
1432
1433         /* for secondary processes, we don't initialise any further as primary
1434          * has already done this work. Only check we don't need a different
1435          * RX function */
1436         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1437                 i40e_set_rx_function(dev);
1438                 i40e_set_tx_function(dev);
1439                 return 0;
1440         }
1441         i40e_set_default_ptype_table(dev);
1442         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1443         intr_handle = &pci_dev->intr_handle;
1444
1445         rte_eth_copy_pci_info(dev, pci_dev);
1446         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1447
1448         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1449         pf->dev_data = dev->data;
1450
1451         hw->back = I40E_PF_TO_ADAPTER(pf);
1452         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1453         if (!hw->hw_addr) {
1454                 PMD_INIT_LOG(ERR,
1455                         "Hardware is not available, as address is NULL");
1456                 return -ENODEV;
1457         }
1458
1459         hw->vendor_id = pci_dev->id.vendor_id;
1460         hw->device_id = pci_dev->id.device_id;
1461         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1462         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1463         hw->bus.device = pci_dev->addr.devid;
1464         hw->bus.func = pci_dev->addr.function;
1465         hw->adapter_stopped = 0;
1466         hw->adapter_closed = 0;
1467
1468         /* Init switch device pointer */
1469         hw->switch_dev = NULL;
1470
1471         /*
1472          * Switch Tag value should not be identical to either the First Tag
1473          * or Second Tag values. So set something other than common Ethertype
1474          * for internal switching.
1475          */
1476         hw->switch_tag = 0xffff;
1477
1478         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1479         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1480                 PMD_INIT_LOG(ERR, "\nERROR: "
1481                         "Firmware recovery mode detected. Limiting functionality.\n"
1482                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1483                         "User Guide for details on firmware recovery mode.");
1484                 return -EIO;
1485         }
1486
1487         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1488         /* Check if need to support multi-driver */
1489         i40e_support_multi_driver(dev);
1490
1491         /* Make sure all is clean before doing PF reset */
1492         i40e_clear_hw(hw);
1493
1494         /* Reset here to make sure all is clean for each PF */
1495         ret = i40e_pf_reset(hw);
1496         if (ret) {
1497                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1498                 return ret;
1499         }
1500
1501         /* Initialize the shared code (base driver) */
1502         ret = i40e_init_shared_code(hw);
1503         if (ret) {
1504                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1505                 return ret;
1506         }
1507
1508         /* Initialize the parameters for adminq */
1509         i40e_init_adminq_parameter(hw);
1510         ret = i40e_init_adminq(hw);
1511         if (ret != I40E_SUCCESS) {
1512                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1513                 return -EIO;
1514         }
1515         /* Firmware of SFP x722 does not support 802.1ad frames ability */
1516         if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1517                 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1518                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1519
1520         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1521                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1522                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1523                      ((hw->nvm.version >> 12) & 0xf),
1524                      ((hw->nvm.version >> 4) & 0xff),
1525                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1526
1527         /* Initialize the hardware */
1528         i40e_hw_init(dev);
1529
1530         i40e_config_automask(pf);
1531
1532         i40e_set_default_pctype_table(dev);
1533
1534         /*
1535          * To work around the NVM issue, initialize registers
1536          * for packet type of QinQ by software.
1537          * It should be removed once issues are fixed in NVM.
1538          */
1539         if (!pf->support_multi_driver)
1540                 i40e_GLQF_reg_init(hw);
1541
1542         /* Initialize the input set for filters (hash and fd) to default value */
1543         i40e_filter_input_set_init(pf);
1544
1545         /* initialise the L3_MAP register */
1546         if (!pf->support_multi_driver) {
1547                 ret = i40e_aq_debug_write_global_register(hw,
1548                                                    I40E_GLQF_L3_MAP(40),
1549                                                    0x00000028,  NULL);
1550                 if (ret)
1551                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1552                                      ret);
1553                 PMD_INIT_LOG(DEBUG,
1554                              "Global register 0x%08x is changed with 0x28",
1555                              I40E_GLQF_L3_MAP(40));
1556         }
1557
1558         /* Need the special FW version to support floating VEB */
1559         config_floating_veb(dev);
1560         /* Clear PXE mode */
1561         i40e_clear_pxe_mode(hw);
1562         i40e_dev_sync_phy_type(hw);
1563
1564         /*
1565          * On X710, performance number is far from the expectation on recent
1566          * firmware versions. The fix for this issue may not be integrated in
1567          * the following firmware version. So the workaround in software driver
1568          * is needed. It needs to modify the initial values of 3 internal only
1569          * registers. Note that the workaround can be removed when it is fixed
1570          * in firmware in the future.
1571          */
1572         i40e_configure_registers(hw);
1573
1574         /* Get hw capabilities */
1575         ret = i40e_get_cap(hw);
1576         if (ret != I40E_SUCCESS) {
1577                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1578                 goto err_get_capabilities;
1579         }
1580
1581         /* Initialize parameters for PF */
1582         ret = i40e_pf_parameter_init(dev);
1583         if (ret != 0) {
1584                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1585                 goto err_parameter_init;
1586         }
1587
1588         /* Initialize the queue management */
1589         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1590         if (ret < 0) {
1591                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1592                 goto err_qp_pool_init;
1593         }
1594         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1595                                 hw->func_caps.num_msix_vectors - 1);
1596         if (ret < 0) {
1597                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1598                 goto err_msix_pool_init;
1599         }
1600
1601         /* Initialize lan hmc */
1602         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1603                                 hw->func_caps.num_rx_qp, 0, 0);
1604         if (ret != I40E_SUCCESS) {
1605                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1606                 goto err_init_lan_hmc;
1607         }
1608
1609         /* Configure lan hmc */
1610         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1611         if (ret != I40E_SUCCESS) {
1612                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1613                 goto err_configure_lan_hmc;
1614         }
1615
1616         /* Get and check the mac address */
1617         i40e_get_mac_addr(hw, hw->mac.addr);
1618         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1619                 PMD_INIT_LOG(ERR, "mac address is not valid");
1620                 ret = -EIO;
1621                 goto err_get_mac_addr;
1622         }
1623         /* Copy the permanent MAC address */
1624         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1625                         (struct rte_ether_addr *)hw->mac.perm_addr);
1626
1627         /* Disable flow control */
1628         hw->fc.requested_mode = I40E_FC_NONE;
1629         i40e_set_fc(hw, &aq_fail, TRUE);
1630
1631         /* Set the global registers with default ether type value */
1632         if (!pf->support_multi_driver) {
1633                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1634                                          RTE_ETHER_TYPE_VLAN);
1635                 if (ret != I40E_SUCCESS) {
1636                         PMD_INIT_LOG(ERR,
1637                                      "Failed to set the default outer "
1638                                      "VLAN ether type");
1639                         goto err_setup_pf_switch;
1640                 }
1641         }
1642
1643         /* PF setup, which includes VSI setup */
1644         ret = i40e_pf_setup(pf);
1645         if (ret) {
1646                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1647                 goto err_setup_pf_switch;
1648         }
1649
1650         vsi = pf->main_vsi;
1651
1652         /* Disable double vlan by default */
1653         i40e_vsi_config_double_vlan(vsi, FALSE);
1654
1655         /* Disable S-TAG identification when floating_veb is disabled */
1656         if (!pf->floating_veb) {
1657                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1658                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1659                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1660                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1661                 }
1662         }
1663
1664         if (!vsi->max_macaddrs)
1665                 len = RTE_ETHER_ADDR_LEN;
1666         else
1667                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1668
1669         /* Should be after VSI initialized */
1670         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1671         if (!dev->data->mac_addrs) {
1672                 PMD_INIT_LOG(ERR,
1673                         "Failed to allocated memory for storing mac address");
1674                 goto err_mac_alloc;
1675         }
1676         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1677                                         &dev->data->mac_addrs[0]);
1678
1679         /* Init dcb to sw mode by default */
1680         ret = i40e_dcb_init_configure(dev, TRUE);
1681         if (ret != I40E_SUCCESS) {
1682                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1683                 pf->flags &= ~I40E_FLAG_DCB;
1684         }
1685         /* Update HW struct after DCB configuration */
1686         i40e_get_cap(hw);
1687
1688         /* initialize pf host driver to setup SRIOV resource if applicable */
1689         i40e_pf_host_init(dev);
1690
1691         /* register callback func to eal lib */
1692         rte_intr_callback_register(intr_handle,
1693                                    i40e_dev_interrupt_handler, dev);
1694
1695         /* configure and enable device interrupt */
1696         i40e_pf_config_irq0(hw, TRUE);
1697         i40e_pf_enable_irq0(hw);
1698
1699         /* enable uio intr after callback register */
1700         rte_intr_enable(intr_handle);
1701
1702         /* By default disable flexible payload in global configuration */
1703         if (!pf->support_multi_driver)
1704                 i40e_flex_payload_reg_set_default(hw);
1705
1706         /*
1707          * Add an ethertype filter to drop all flow control frames transmitted
1708          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1709          * frames to wire.
1710          */
1711         i40e_add_tx_flow_control_drop_filter(pf);
1712
1713         /* Set the max frame size to 0x2600 by default,
1714          * in case other drivers changed the default value.
1715          */
1716         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1717
1718         /* initialize RSS rule list */
1719         TAILQ_INIT(&pf->rss_config_list);
1720
1721         /* initialize Traffic Manager configuration */
1722         i40e_tm_conf_init(dev);
1723
1724         /* Initialize customized information */
1725         i40e_init_customized_info(pf);
1726
1727         /* Initialize the filter invalidation configuration */
1728         i40e_init_filter_invalidation(pf);
1729
1730         ret = i40e_init_ethtype_filter_list(dev);
1731         if (ret < 0)
1732                 goto err_init_ethtype_filter_list;
1733         ret = i40e_init_tunnel_filter_list(dev);
1734         if (ret < 0)
1735                 goto err_init_tunnel_filter_list;
1736         ret = i40e_init_fdir_filter_list(dev);
1737         if (ret < 0)
1738                 goto err_init_fdir_filter_list;
1739
1740         /* initialize queue region configuration */
1741         i40e_init_queue_region_conf(dev);
1742
1743         /* reset all stats of the device, including pf and main vsi */
1744         i40e_dev_stats_reset(dev);
1745
1746         return 0;
1747
1748 err_init_fdir_filter_list:
1749         rte_hash_free(pf->tunnel.hash_table);
1750         rte_free(pf->tunnel.hash_map);
1751 err_init_tunnel_filter_list:
1752         rte_hash_free(pf->ethertype.hash_table);
1753         rte_free(pf->ethertype.hash_map);
1754 err_init_ethtype_filter_list:
1755         rte_intr_callback_unregister(intr_handle,
1756                 i40e_dev_interrupt_handler, dev);
1757         rte_free(dev->data->mac_addrs);
1758         dev->data->mac_addrs = NULL;
1759 err_mac_alloc:
1760         i40e_vsi_release(pf->main_vsi);
1761 err_setup_pf_switch:
1762 err_get_mac_addr:
1763 err_configure_lan_hmc:
1764         (void)i40e_shutdown_lan_hmc(hw);
1765 err_init_lan_hmc:
1766         i40e_res_pool_destroy(&pf->msix_pool);
1767 err_msix_pool_init:
1768         i40e_res_pool_destroy(&pf->qp_pool);
1769 err_qp_pool_init:
1770 err_parameter_init:
1771 err_get_capabilities:
1772         (void)i40e_shutdown_adminq(hw);
1773
1774         return ret;
1775 }
1776
1777 static void
1778 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1779 {
1780         struct i40e_ethertype_filter *p_ethertype;
1781         struct i40e_ethertype_rule *ethertype_rule;
1782
1783         ethertype_rule = &pf->ethertype;
1784         /* Remove all ethertype filter rules and hash */
1785         if (ethertype_rule->hash_map)
1786                 rte_free(ethertype_rule->hash_map);
1787         if (ethertype_rule->hash_table)
1788                 rte_hash_free(ethertype_rule->hash_table);
1789
1790         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1791                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1792                              p_ethertype, rules);
1793                 rte_free(p_ethertype);
1794         }
1795 }
1796
1797 static void
1798 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1799 {
1800         struct i40e_tunnel_filter *p_tunnel;
1801         struct i40e_tunnel_rule *tunnel_rule;
1802
1803         tunnel_rule = &pf->tunnel;
1804         /* Remove all tunnel director rules and hash */
1805         if (tunnel_rule->hash_map)
1806                 rte_free(tunnel_rule->hash_map);
1807         if (tunnel_rule->hash_table)
1808                 rte_hash_free(tunnel_rule->hash_table);
1809
1810         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1811                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1812                 rte_free(p_tunnel);
1813         }
1814 }
1815
1816 static void
1817 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1818 {
1819         struct i40e_fdir_filter *p_fdir;
1820         struct i40e_fdir_info *fdir_info;
1821
1822         fdir_info = &pf->fdir;
1823
1824         /* Remove all flow director rules */
1825         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1826                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1827 }
1828
1829 static void
1830 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1831 {
1832         struct i40e_fdir_info *fdir_info;
1833
1834         fdir_info = &pf->fdir;
1835
1836         /* flow director memory cleanup */
1837         if (fdir_info->hash_map)
1838                 rte_free(fdir_info->hash_map);
1839         if (fdir_info->hash_table)
1840                 rte_hash_free(fdir_info->hash_table);
1841         if (fdir_info->fdir_flow_pool.bitmap)
1842                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1843         if (fdir_info->fdir_flow_pool.pool)
1844                 rte_free(fdir_info->fdir_flow_pool.pool);
1845         if (fdir_info->fdir_filter_array)
1846                 rte_free(fdir_info->fdir_filter_array);
1847 }
1848
1849 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1850 {
1851         /*
1852          * Disable by default flexible payload
1853          * for corresponding L2/L3/L4 layers.
1854          */
1855         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1856         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1857         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1858 }
1859
1860 static int
1861 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1862 {
1863         struct i40e_hw *hw;
1864
1865         PMD_INIT_FUNC_TRACE();
1866
1867         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1868                 return 0;
1869
1870         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871
1872         if (hw->adapter_closed == 0)
1873                 i40e_dev_close(dev);
1874
1875         return 0;
1876 }
1877
1878 static int
1879 i40e_dev_configure(struct rte_eth_dev *dev)
1880 {
1881         struct i40e_adapter *ad =
1882                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1886         int i, ret;
1887
1888         ret = i40e_dev_sync_phy_type(hw);
1889         if (ret)
1890                 return ret;
1891
1892         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1893          * bulk allocation or vector Rx preconditions we will reset it.
1894          */
1895         ad->rx_bulk_alloc_allowed = true;
1896         ad->rx_vec_allowed = true;
1897         ad->tx_simple_allowed = true;
1898         ad->tx_vec_allowed = true;
1899
1900         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1901                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1902
1903         /* Only legacy filter API needs the following fdir config. So when the
1904          * legacy filter API is deprecated, the following codes should also be
1905          * removed.
1906          */
1907         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1908                 ret = i40e_fdir_setup(pf);
1909                 if (ret != I40E_SUCCESS) {
1910                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1911                         return -ENOTSUP;
1912                 }
1913                 ret = i40e_fdir_configure(dev);
1914                 if (ret < 0) {
1915                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1916                         goto err;
1917                 }
1918         } else
1919                 i40e_fdir_teardown(pf);
1920
1921         ret = i40e_dev_init_vlan(dev);
1922         if (ret < 0)
1923                 goto err;
1924
1925         /* VMDQ setup.
1926          *  General PMD driver call sequence are NIC init, configure,
1927          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1928          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1929          *  applicable. So, VMDQ setting has to be done before
1930          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1931          *  For RSS setting, it will try to calculate actual configured RX queue
1932          *  number, which will be available after rx_queue_setup(). dev_start()
1933          *  function is good to place RSS setup.
1934          */
1935         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1936                 ret = i40e_vmdq_setup(dev);
1937                 if (ret)
1938                         goto err;
1939         }
1940
1941         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1942                 ret = i40e_dcb_setup(dev);
1943                 if (ret) {
1944                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1945                         goto err_dcb;
1946                 }
1947         }
1948
1949         TAILQ_INIT(&pf->flow_list);
1950
1951         return 0;
1952
1953 err_dcb:
1954         /* need to release vmdq resource if exists */
1955         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1956                 i40e_vsi_release(pf->vmdq[i].vsi);
1957                 pf->vmdq[i].vsi = NULL;
1958         }
1959         rte_free(pf->vmdq);
1960         pf->vmdq = NULL;
1961 err:
1962         /* Need to release fdir resource if exists.
1963          * Only legacy filter API needs the following fdir config. So when the
1964          * legacy filter API is deprecated, the following code should also be
1965          * removed.
1966          */
1967         i40e_fdir_teardown(pf);
1968         return ret;
1969 }
1970
1971 void
1972 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1973 {
1974         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
1975         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1976         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1977         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1978         uint16_t msix_vect = vsi->msix_intr;
1979         uint16_t i;
1980
1981         for (i = 0; i < vsi->nb_qps; i++) {
1982                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1983                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1984                 rte_wmb();
1985         }
1986
1987         if (vsi->type != I40E_VSI_SRIOV) {
1988                 if (!rte_intr_allow_others(intr_handle)) {
1989                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1990                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1991                         I40E_WRITE_REG(hw,
1992                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1993                                        0);
1994                 } else {
1995                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1996                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1997                         I40E_WRITE_REG(hw,
1998                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1999                                                        msix_vect - 1), 0);
2000                 }
2001         } else {
2002                 uint32_t reg;
2003                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2004                         vsi->user_param + (msix_vect - 1);
2005
2006                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2007                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2008         }
2009         I40E_WRITE_FLUSH(hw);
2010 }
2011
2012 static void
2013 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2014                        int base_queue, int nb_queue,
2015                        uint16_t itr_idx)
2016 {
2017         int i;
2018         uint32_t val;
2019         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2020         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2021
2022         /* Bind all RX queues to allocated MSIX interrupt */
2023         for (i = 0; i < nb_queue; i++) {
2024                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2025                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2026                         ((base_queue + i + 1) <<
2027                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2028                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2029                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2030
2031                 if (i == nb_queue - 1)
2032                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2033                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2034         }
2035
2036         /* Write first RX queue to Link list register as the head element */
2037         if (vsi->type != I40E_VSI_SRIOV) {
2038                 uint16_t interval =
2039                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2040
2041                 if (msix_vect == I40E_MISC_VEC_ID) {
2042                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2043                                        (base_queue <<
2044                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2045                                        (0x0 <<
2046                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2047                         I40E_WRITE_REG(hw,
2048                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2049                                        interval);
2050                 } else {
2051                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2052                                        (base_queue <<
2053                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2054                                        (0x0 <<
2055                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2056                         I40E_WRITE_REG(hw,
2057                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2058                                                        msix_vect - 1),
2059                                        interval);
2060                 }
2061         } else {
2062                 uint32_t reg;
2063
2064                 if (msix_vect == I40E_MISC_VEC_ID) {
2065                         I40E_WRITE_REG(hw,
2066                                        I40E_VPINT_LNKLST0(vsi->user_param),
2067                                        (base_queue <<
2068                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2069                                        (0x0 <<
2070                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2071                 } else {
2072                         /* num_msix_vectors_vf needs to minus irq0 */
2073                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2074                                 vsi->user_param + (msix_vect - 1);
2075
2076                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2077                                        (base_queue <<
2078                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2079                                        (0x0 <<
2080                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2081                 }
2082         }
2083
2084         I40E_WRITE_FLUSH(hw);
2085 }
2086
2087 int
2088 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2089 {
2090         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2091         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2092         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2094         uint16_t msix_vect = vsi->msix_intr;
2095         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2096         uint16_t queue_idx = 0;
2097         int record = 0;
2098         int i;
2099
2100         for (i = 0; i < vsi->nb_qps; i++) {
2101                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2102                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2103         }
2104
2105         /* VF bind interrupt */
2106         if (vsi->type == I40E_VSI_SRIOV) {
2107                 if (vsi->nb_msix == 0) {
2108                         PMD_DRV_LOG(ERR, "No msix resource");
2109                         return -EINVAL;
2110                 }
2111                 __vsi_queues_bind_intr(vsi, msix_vect,
2112                                        vsi->base_queue, vsi->nb_qps,
2113                                        itr_idx);
2114                 return 0;
2115         }
2116
2117         /* PF & VMDq bind interrupt */
2118         if (rte_intr_dp_is_en(intr_handle)) {
2119                 if (vsi->type == I40E_VSI_MAIN) {
2120                         queue_idx = 0;
2121                         record = 1;
2122                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2123                         struct i40e_vsi *main_vsi =
2124                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2125                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2126                         record = 1;
2127                 }
2128         }
2129
2130         for (i = 0; i < vsi->nb_used_qps; i++) {
2131                 if (vsi->nb_msix == 0) {
2132                         PMD_DRV_LOG(ERR, "No msix resource");
2133                         return -EINVAL;
2134                 } else if (nb_msix <= 1) {
2135                         if (!rte_intr_allow_others(intr_handle))
2136                                 /* allow to share MISC_VEC_ID */
2137                                 msix_vect = I40E_MISC_VEC_ID;
2138
2139                         /* no enough msix_vect, map all to one */
2140                         __vsi_queues_bind_intr(vsi, msix_vect,
2141                                                vsi->base_queue + i,
2142                                                vsi->nb_used_qps - i,
2143                                                itr_idx);
2144                         for (; !!record && i < vsi->nb_used_qps; i++)
2145                                 intr_handle->intr_vec[queue_idx + i] =
2146                                         msix_vect;
2147                         break;
2148                 }
2149                 /* 1:1 queue/msix_vect mapping */
2150                 __vsi_queues_bind_intr(vsi, msix_vect,
2151                                        vsi->base_queue + i, 1,
2152                                        itr_idx);
2153                 if (!!record)
2154                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2155
2156                 msix_vect++;
2157                 nb_msix--;
2158         }
2159
2160         return 0;
2161 }
2162
2163 void
2164 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2165 {
2166         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2167         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2168         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2169         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2170         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2171         uint16_t msix_intr, i;
2172
2173         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2174                 for (i = 0; i < vsi->nb_msix; i++) {
2175                         msix_intr = vsi->msix_intr + i;
2176                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2177                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2178                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2179                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2180                 }
2181         else
2182                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2183                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2184                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2185                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2186
2187         I40E_WRITE_FLUSH(hw);
2188 }
2189
2190 void
2191 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2192 {
2193         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2194         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2195         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2196         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2197         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2198         uint16_t msix_intr, i;
2199
2200         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2201                 for (i = 0; i < vsi->nb_msix; i++) {
2202                         msix_intr = vsi->msix_intr + i;
2203                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2204                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2205                 }
2206         else
2207                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2208                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2209
2210         I40E_WRITE_FLUSH(hw);
2211 }
2212
2213 static inline uint8_t
2214 i40e_parse_link_speeds(uint16_t link_speeds)
2215 {
2216         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2217
2218         if (link_speeds & ETH_LINK_SPEED_40G)
2219                 link_speed |= I40E_LINK_SPEED_40GB;
2220         if (link_speeds & ETH_LINK_SPEED_25G)
2221                 link_speed |= I40E_LINK_SPEED_25GB;
2222         if (link_speeds & ETH_LINK_SPEED_20G)
2223                 link_speed |= I40E_LINK_SPEED_20GB;
2224         if (link_speeds & ETH_LINK_SPEED_10G)
2225                 link_speed |= I40E_LINK_SPEED_10GB;
2226         if (link_speeds & ETH_LINK_SPEED_1G)
2227                 link_speed |= I40E_LINK_SPEED_1GB;
2228         if (link_speeds & ETH_LINK_SPEED_100M)
2229                 link_speed |= I40E_LINK_SPEED_100MB;
2230
2231         return link_speed;
2232 }
2233
2234 static int
2235 i40e_phy_conf_link(struct i40e_hw *hw,
2236                    uint8_t abilities,
2237                    uint8_t force_speed,
2238                    bool is_up)
2239 {
2240         enum i40e_status_code status;
2241         struct i40e_aq_get_phy_abilities_resp phy_ab;
2242         struct i40e_aq_set_phy_config phy_conf;
2243         enum i40e_aq_phy_type cnt;
2244         uint8_t avail_speed;
2245         uint32_t phy_type_mask = 0;
2246
2247         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2248                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2249                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2250                         I40E_AQ_PHY_FLAG_LOW_POWER;
2251         int ret = -ENOTSUP;
2252
2253         /* To get phy capabilities of available speeds. */
2254         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2255                                               NULL);
2256         if (status) {
2257                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2258                                 status);
2259                 return ret;
2260         }
2261         avail_speed = phy_ab.link_speed;
2262
2263         /* To get the current phy config. */
2264         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2265                                               NULL);
2266         if (status) {
2267                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2268                                 status);
2269                 return ret;
2270         }
2271
2272         /* If link needs to go up and it is in autoneg mode the speed is OK,
2273          * no need to set up again.
2274          */
2275         if (is_up && phy_ab.phy_type != 0 &&
2276                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2277                      phy_ab.link_speed != 0)
2278                 return I40E_SUCCESS;
2279
2280         memset(&phy_conf, 0, sizeof(phy_conf));
2281
2282         /* bits 0-2 use the values from get_phy_abilities_resp */
2283         abilities &= ~mask;
2284         abilities |= phy_ab.abilities & mask;
2285
2286         phy_conf.abilities = abilities;
2287
2288         /* If link needs to go up, but the force speed is not supported,
2289          * Warn users and config the default available speeds.
2290          */
2291         if (is_up && !(force_speed & avail_speed)) {
2292                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2293                 phy_conf.link_speed = avail_speed;
2294         } else {
2295                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2296         }
2297
2298         /* PHY type mask needs to include each type except PHY type extension */
2299         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2300                 phy_type_mask |= 1 << cnt;
2301
2302         /* use get_phy_abilities_resp value for the rest */
2303         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2304         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2305                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2306                 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2307                 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2308         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2309         phy_conf.eee_capability = phy_ab.eee_capability;
2310         phy_conf.eeer = phy_ab.eeer_val;
2311         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2312
2313         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2314                     phy_ab.abilities, phy_ab.link_speed);
2315         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2316                     phy_conf.abilities, phy_conf.link_speed);
2317
2318         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2319         if (status)
2320                 return ret;
2321
2322         return I40E_SUCCESS;
2323 }
2324
2325 static int
2326 i40e_apply_link_speed(struct rte_eth_dev *dev)
2327 {
2328         uint8_t speed;
2329         uint8_t abilities = 0;
2330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331         struct rte_eth_conf *conf = &dev->data->dev_conf;
2332
2333         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2334                      I40E_AQ_PHY_LINK_ENABLED;
2335
2336         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2337                 conf->link_speeds = ETH_LINK_SPEED_40G |
2338                                     ETH_LINK_SPEED_25G |
2339                                     ETH_LINK_SPEED_20G |
2340                                     ETH_LINK_SPEED_10G |
2341                                     ETH_LINK_SPEED_1G |
2342                                     ETH_LINK_SPEED_100M;
2343
2344                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2345         } else {
2346                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2347         }
2348         speed = i40e_parse_link_speeds(conf->link_speeds);
2349
2350         return i40e_phy_conf_link(hw, abilities, speed, true);
2351 }
2352
2353 static int
2354 i40e_dev_start(struct rte_eth_dev *dev)
2355 {
2356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358         struct i40e_vsi *main_vsi = pf->main_vsi;
2359         int ret, i;
2360         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2362         uint32_t intr_vector = 0;
2363         struct i40e_vsi *vsi;
2364         uint16_t nb_rxq, nb_txq;
2365
2366         hw->adapter_stopped = 0;
2367
2368         rte_intr_disable(intr_handle);
2369
2370         if ((rte_intr_cap_multiple(intr_handle) ||
2371              !RTE_ETH_DEV_SRIOV(dev).active) &&
2372             dev->data->dev_conf.intr_conf.rxq != 0) {
2373                 intr_vector = dev->data->nb_rx_queues;
2374                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2375                 if (ret)
2376                         return ret;
2377         }
2378
2379         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2380                 intr_handle->intr_vec =
2381                         rte_zmalloc("intr_vec",
2382                                     dev->data->nb_rx_queues * sizeof(int),
2383                                     0);
2384                 if (!intr_handle->intr_vec) {
2385                         PMD_INIT_LOG(ERR,
2386                                 "Failed to allocate %d rx_queues intr_vec",
2387                                 dev->data->nb_rx_queues);
2388                         return -ENOMEM;
2389                 }
2390         }
2391
2392         /* Initialize VSI */
2393         ret = i40e_dev_rxtx_init(pf);
2394         if (ret != I40E_SUCCESS) {
2395                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2396                 return ret;
2397         }
2398
2399         /* Map queues with MSIX interrupt */
2400         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2401                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2402         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2403         if (ret < 0)
2404                 return ret;
2405         i40e_vsi_enable_queues_intr(main_vsi);
2406
2407         /* Map VMDQ VSI queues with MSIX interrupt */
2408         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2409                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2410                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2411                                                 I40E_ITR_INDEX_DEFAULT);
2412                 if (ret < 0)
2413                         return ret;
2414                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2415         }
2416
2417         /* Enable all queues which have been configured */
2418         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2419                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2420                 if (ret)
2421                         goto rx_err;
2422         }
2423
2424         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2425                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2426                 if (ret)
2427                         goto tx_err;
2428         }
2429
2430         /* Enable receiving broadcast packets */
2431         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2432         if (ret != I40E_SUCCESS)
2433                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2434
2435         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2436                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2437                                                 true, NULL);
2438                 if (ret != I40E_SUCCESS)
2439                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2440         }
2441
2442         /* Enable the VLAN promiscuous mode. */
2443         if (pf->vfs) {
2444                 for (i = 0; i < pf->vf_num; i++) {
2445                         vsi = pf->vfs[i].vsi;
2446                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2447                                                      true, NULL);
2448                 }
2449         }
2450
2451         /* Enable mac loopback mode */
2452         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2453             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2454                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2455                 if (ret != I40E_SUCCESS) {
2456                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2457                         goto tx_err;
2458                 }
2459         }
2460
2461         /* Apply link configure */
2462         ret = i40e_apply_link_speed(dev);
2463         if (I40E_SUCCESS != ret) {
2464                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2465                 goto tx_err;
2466         }
2467
2468         if (!rte_intr_allow_others(intr_handle)) {
2469                 rte_intr_callback_unregister(intr_handle,
2470                                              i40e_dev_interrupt_handler,
2471                                              (void *)dev);
2472                 /* configure and enable device interrupt */
2473                 i40e_pf_config_irq0(hw, FALSE);
2474                 i40e_pf_enable_irq0(hw);
2475
2476                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2477                         PMD_INIT_LOG(INFO,
2478                                 "lsc won't enable because of no intr multiplex");
2479         } else {
2480                 ret = i40e_aq_set_phy_int_mask(hw,
2481                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2482                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2483                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2484                 if (ret != I40E_SUCCESS)
2485                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2486
2487                 /* Call get_link_info aq commond to enable/disable LSE */
2488                 i40e_dev_link_update(dev, 0);
2489         }
2490
2491         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2492                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2493                                   i40e_dev_alarm_handler, dev);
2494         } else {
2495                 /* enable uio intr after callback register */
2496                 rte_intr_enable(intr_handle);
2497         }
2498
2499         i40e_filter_restore(pf);
2500
2501         if (pf->tm_conf.root && !pf->tm_conf.committed)
2502                 PMD_DRV_LOG(WARNING,
2503                             "please call hierarchy_commit() "
2504                             "before starting the port");
2505
2506         return I40E_SUCCESS;
2507
2508 tx_err:
2509         for (i = 0; i < nb_txq; i++)
2510                 i40e_dev_tx_queue_stop(dev, i);
2511 rx_err:
2512         for (i = 0; i < nb_rxq; i++)
2513                 i40e_dev_rx_queue_stop(dev, i);
2514
2515         return ret;
2516 }
2517
2518 static int
2519 i40e_dev_stop(struct rte_eth_dev *dev)
2520 {
2521         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2522         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         struct i40e_vsi *main_vsi = pf->main_vsi;
2524         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2525         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2526         int i;
2527
2528         if (hw->adapter_stopped == 1)
2529                 return 0;
2530
2531         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2532                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2533                 rte_intr_enable(intr_handle);
2534         }
2535
2536         /* Disable all queues */
2537         for (i = 0; i < dev->data->nb_tx_queues; i++)
2538                 i40e_dev_tx_queue_stop(dev, i);
2539
2540         for (i = 0; i < dev->data->nb_rx_queues; i++)
2541                 i40e_dev_rx_queue_stop(dev, i);
2542
2543         /* un-map queues with interrupt registers */
2544         i40e_vsi_disable_queues_intr(main_vsi);
2545         i40e_vsi_queues_unbind_intr(main_vsi);
2546
2547         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2548                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2549                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2550         }
2551
2552         /* Clear all queues and release memory */
2553         i40e_dev_clear_queues(dev);
2554
2555         /* Set link down */
2556         i40e_dev_set_link_down(dev);
2557
2558         if (!rte_intr_allow_others(intr_handle))
2559                 /* resume to the default handler */
2560                 rte_intr_callback_register(intr_handle,
2561                                            i40e_dev_interrupt_handler,
2562                                            (void *)dev);
2563
2564         /* Clean datapath event and queue/vec mapping */
2565         rte_intr_efd_disable(intr_handle);
2566         if (intr_handle->intr_vec) {
2567                 rte_free(intr_handle->intr_vec);
2568                 intr_handle->intr_vec = NULL;
2569         }
2570
2571         /* reset hierarchy commit */
2572         pf->tm_conf.committed = false;
2573
2574         hw->adapter_stopped = 1;
2575         dev->data->dev_started = 0;
2576
2577         pf->adapter->rss_reta_updated = 0;
2578
2579         return 0;
2580 }
2581
2582 static int
2583 i40e_dev_close(struct rte_eth_dev *dev)
2584 {
2585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2586         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2588         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2589         struct i40e_filter_control_settings settings;
2590         struct rte_flow *p_flow;
2591         uint32_t reg;
2592         int i;
2593         int ret;
2594         uint8_t aq_fail = 0;
2595         int retries = 0;
2596
2597         PMD_INIT_FUNC_TRACE();
2598         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2599                 return 0;
2600
2601         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2602         if (ret)
2603                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2604
2605
2606         ret = i40e_dev_stop(dev);
2607
2608         i40e_dev_free_queues(dev);
2609
2610         /* Disable interrupt */
2611         i40e_pf_disable_irq0(hw);
2612         rte_intr_disable(intr_handle);
2613
2614         /*
2615          * Only legacy filter API needs the following fdir config. So when the
2616          * legacy filter API is deprecated, the following code should also be
2617          * removed.
2618          */
2619         i40e_fdir_teardown(pf);
2620
2621         /* shutdown and destroy the HMC */
2622         i40e_shutdown_lan_hmc(hw);
2623
2624         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2625                 i40e_vsi_release(pf->vmdq[i].vsi);
2626                 pf->vmdq[i].vsi = NULL;
2627         }
2628         rte_free(pf->vmdq);
2629         pf->vmdq = NULL;
2630
2631         /* release all the existing VSIs and VEBs */
2632         i40e_vsi_release(pf->main_vsi);
2633
2634         /* shutdown the adminq */
2635         i40e_aq_queue_shutdown(hw, true);
2636         i40e_shutdown_adminq(hw);
2637
2638         i40e_res_pool_destroy(&pf->qp_pool);
2639         i40e_res_pool_destroy(&pf->msix_pool);
2640
2641         /* Disable flexible payload in global configuration */
2642         if (!pf->support_multi_driver)
2643                 i40e_flex_payload_reg_set_default(hw);
2644
2645         /* force a PF reset to clean anything leftover */
2646         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2647         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2648                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2649         I40E_WRITE_FLUSH(hw);
2650
2651         /* Clear PXE mode */
2652         i40e_clear_pxe_mode(hw);
2653
2654         /* Unconfigure filter control */
2655         memset(&settings, 0, sizeof(settings));
2656         ret = i40e_set_filter_control(hw, &settings);
2657         if (ret)
2658                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2659                                         ret);
2660
2661         /* Disable flow control */
2662         hw->fc.requested_mode = I40E_FC_NONE;
2663         i40e_set_fc(hw, &aq_fail, TRUE);
2664
2665         /* uninitialize pf host driver */
2666         i40e_pf_host_uninit(dev);
2667
2668         do {
2669                 ret = rte_intr_callback_unregister(intr_handle,
2670                                 i40e_dev_interrupt_handler, dev);
2671                 if (ret >= 0 || ret == -ENOENT) {
2672                         break;
2673                 } else if (ret != -EAGAIN) {
2674                         PMD_INIT_LOG(ERR,
2675                                  "intr callback unregister failed: %d",
2676                                  ret);
2677                 }
2678                 i40e_msec_delay(500);
2679         } while (retries++ < 5);
2680
2681         i40e_rm_ethtype_filter_list(pf);
2682         i40e_rm_tunnel_filter_list(pf);
2683         i40e_rm_fdir_filter_list(pf);
2684
2685         /* Remove all flows */
2686         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2687                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2688                 /* Do not free FDIR flows since they are static allocated */
2689                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2690                         rte_free(p_flow);
2691         }
2692
2693         /* release the fdir static allocated memory */
2694         i40e_fdir_memory_cleanup(pf);
2695
2696         /* Remove all Traffic Manager configuration */
2697         i40e_tm_conf_uninit(dev);
2698
2699         i40e_clear_automask(pf);
2700
2701         hw->adapter_closed = 1;
2702         return ret;
2703 }
2704
2705 /*
2706  * Reset PF device only to re-initialize resources in PMD layer
2707  */
2708 static int
2709 i40e_dev_reset(struct rte_eth_dev *dev)
2710 {
2711         int ret;
2712
2713         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2714          * its VF to make them align with it. The detailed notification
2715          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2716          * To avoid unexpected behavior in VF, currently reset of PF with
2717          * SR-IOV activation is not supported. It might be supported later.
2718          */
2719         if (dev->data->sriov.active)
2720                 return -ENOTSUP;
2721
2722         ret = eth_i40e_dev_uninit(dev);
2723         if (ret)
2724                 return ret;
2725
2726         ret = eth_i40e_dev_init(dev, NULL);
2727
2728         return ret;
2729 }
2730
2731 static int
2732 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2733 {
2734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct i40e_vsi *vsi = pf->main_vsi;
2737         int status;
2738
2739         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2740                                                      true, NULL, true);
2741         if (status != I40E_SUCCESS) {
2742                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2743                 return -EAGAIN;
2744         }
2745
2746         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2747                                                         TRUE, NULL);
2748         if (status != I40E_SUCCESS) {
2749                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2750                 /* Rollback unicast promiscuous mode */
2751                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2752                                                     false, NULL, true);
2753                 return -EAGAIN;
2754         }
2755
2756         return 0;
2757 }
2758
2759 static int
2760 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2761 {
2762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2764         struct i40e_vsi *vsi = pf->main_vsi;
2765         int status;
2766
2767         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2768                                                      false, NULL, true);
2769         if (status != I40E_SUCCESS) {
2770                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2771                 return -EAGAIN;
2772         }
2773
2774         /* must remain in all_multicast mode */
2775         if (dev->data->all_multicast == 1)
2776                 return 0;
2777
2778         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2779                                                         false, NULL);
2780         if (status != I40E_SUCCESS) {
2781                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2782                 /* Rollback unicast promiscuous mode */
2783                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2784                                                     true, NULL, true);
2785                 return -EAGAIN;
2786         }
2787
2788         return 0;
2789 }
2790
2791 static int
2792 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2793 {
2794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796         struct i40e_vsi *vsi = pf->main_vsi;
2797         int ret;
2798
2799         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2800         if (ret != I40E_SUCCESS) {
2801                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2802                 return -EAGAIN;
2803         }
2804
2805         return 0;
2806 }
2807
2808 static int
2809 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2810 {
2811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct i40e_vsi *vsi = pf->main_vsi;
2814         int ret;
2815
2816         if (dev->data->promiscuous == 1)
2817                 return 0; /* must remain in all_multicast mode */
2818
2819         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2820                                 vsi->seid, FALSE, NULL);
2821         if (ret != I40E_SUCCESS) {
2822                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2823                 return -EAGAIN;
2824         }
2825
2826         return 0;
2827 }
2828
2829 /*
2830  * Set device link up.
2831  */
2832 static int
2833 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2834 {
2835         /* re-apply link speed setting */
2836         return i40e_apply_link_speed(dev);
2837 }
2838
2839 /*
2840  * Set device link down.
2841  */
2842 static int
2843 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2844 {
2845         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2846         uint8_t abilities = 0;
2847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848
2849         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2850         return i40e_phy_conf_link(hw, abilities, speed, false);
2851 }
2852
2853 static __rte_always_inline void
2854 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2855 {
2856 /* Link status registers and values*/
2857 #define I40E_PRTMAC_LINKSTA             0x001E2420
2858 #define I40E_REG_LINK_UP                0x40000080
2859 #define I40E_PRTMAC_MACC                0x001E24E0
2860 #define I40E_REG_MACC_25GB              0x00020000
2861 #define I40E_REG_SPEED_MASK             0x38000000
2862 #define I40E_REG_SPEED_0                0x00000000
2863 #define I40E_REG_SPEED_1                0x08000000
2864 #define I40E_REG_SPEED_2                0x10000000
2865 #define I40E_REG_SPEED_3                0x18000000
2866 #define I40E_REG_SPEED_4                0x20000000
2867         uint32_t link_speed;
2868         uint32_t reg_val;
2869
2870         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2871         link_speed = reg_val & I40E_REG_SPEED_MASK;
2872         reg_val &= I40E_REG_LINK_UP;
2873         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2874
2875         if (unlikely(link->link_status == 0))
2876                 return;
2877
2878         /* Parse the link status */
2879         switch (link_speed) {
2880         case I40E_REG_SPEED_0:
2881                 link->link_speed = ETH_SPEED_NUM_100M;
2882                 break;
2883         case I40E_REG_SPEED_1:
2884                 link->link_speed = ETH_SPEED_NUM_1G;
2885                 break;
2886         case I40E_REG_SPEED_2:
2887                 if (hw->mac.type == I40E_MAC_X722)
2888                         link->link_speed = ETH_SPEED_NUM_2_5G;
2889                 else
2890                         link->link_speed = ETH_SPEED_NUM_10G;
2891                 break;
2892         case I40E_REG_SPEED_3:
2893                 if (hw->mac.type == I40E_MAC_X722) {
2894                         link->link_speed = ETH_SPEED_NUM_5G;
2895                 } else {
2896                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2897
2898                         if (reg_val & I40E_REG_MACC_25GB)
2899                                 link->link_speed = ETH_SPEED_NUM_25G;
2900                         else
2901                                 link->link_speed = ETH_SPEED_NUM_40G;
2902                 }
2903                 break;
2904         case I40E_REG_SPEED_4:
2905                 if (hw->mac.type == I40E_MAC_X722)
2906                         link->link_speed = ETH_SPEED_NUM_10G;
2907                 else
2908                         link->link_speed = ETH_SPEED_NUM_20G;
2909                 break;
2910         default:
2911                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2912                 break;
2913         }
2914 }
2915
2916 static __rte_always_inline void
2917 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2918         bool enable_lse, int wait_to_complete)
2919 {
2920 #define CHECK_INTERVAL             100  /* 100ms */
2921 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2922         uint32_t rep_cnt = MAX_REPEAT_TIME;
2923         struct i40e_link_status link_status;
2924         int status;
2925
2926         memset(&link_status, 0, sizeof(link_status));
2927
2928         do {
2929                 memset(&link_status, 0, sizeof(link_status));
2930
2931                 /* Get link status information from hardware */
2932                 status = i40e_aq_get_link_info(hw, enable_lse,
2933                                                 &link_status, NULL);
2934                 if (unlikely(status != I40E_SUCCESS)) {
2935                         link->link_speed = ETH_SPEED_NUM_NONE;
2936                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2937                         PMD_DRV_LOG(ERR, "Failed to get link info");
2938                         return;
2939                 }
2940
2941                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2942                 if (!wait_to_complete || link->link_status)
2943                         break;
2944
2945                 rte_delay_ms(CHECK_INTERVAL);
2946         } while (--rep_cnt);
2947
2948         /* Parse the link status */
2949         switch (link_status.link_speed) {
2950         case I40E_LINK_SPEED_100MB:
2951                 link->link_speed = ETH_SPEED_NUM_100M;
2952                 break;
2953         case I40E_LINK_SPEED_1GB:
2954                 link->link_speed = ETH_SPEED_NUM_1G;
2955                 break;
2956         case I40E_LINK_SPEED_10GB:
2957                 link->link_speed = ETH_SPEED_NUM_10G;
2958                 break;
2959         case I40E_LINK_SPEED_20GB:
2960                 link->link_speed = ETH_SPEED_NUM_20G;
2961                 break;
2962         case I40E_LINK_SPEED_25GB:
2963                 link->link_speed = ETH_SPEED_NUM_25G;
2964                 break;
2965         case I40E_LINK_SPEED_40GB:
2966                 link->link_speed = ETH_SPEED_NUM_40G;
2967                 break;
2968         default:
2969                 if (link->link_status)
2970                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2971                 else
2972                         link->link_speed = ETH_SPEED_NUM_NONE;
2973                 break;
2974         }
2975 }
2976
2977 int
2978 i40e_dev_link_update(struct rte_eth_dev *dev,
2979                      int wait_to_complete)
2980 {
2981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982         struct rte_eth_link link;
2983         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2984         int ret;
2985
2986         memset(&link, 0, sizeof(link));
2987
2988         /* i40e uses full duplex only */
2989         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2990         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2991                         ETH_LINK_SPEED_FIXED);
2992
2993         if (!wait_to_complete && !enable_lse)
2994                 update_link_reg(hw, &link);
2995         else
2996                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2997
2998         if (hw->switch_dev)
2999                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3000
3001         ret = rte_eth_linkstatus_set(dev, &link);
3002         i40e_notify_all_vfs_link_status(dev);
3003
3004         return ret;
3005 }
3006
3007 static void
3008 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3009                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3010                           uint64_t *stat, uint64_t *prev_stat)
3011 {
3012         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3013         /* enlarge the limitation when statistics counters overflowed */
3014         if (offset_loaded) {
3015                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3016                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3017                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3018         }
3019         *prev_stat = *stat;
3020 }
3021
3022 /* Get all the statistics of a VSI */
3023 void
3024 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3025 {
3026         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3027         struct i40e_eth_stats *nes = &vsi->eth_stats;
3028         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3029         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3030
3031         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3032                                   vsi->offset_loaded, &oes->rx_bytes,
3033                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3034         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3035                             vsi->offset_loaded, &oes->rx_unicast,
3036                             &nes->rx_unicast);
3037         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3038                             vsi->offset_loaded, &oes->rx_multicast,
3039                             &nes->rx_multicast);
3040         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3041                             vsi->offset_loaded, &oes->rx_broadcast,
3042                             &nes->rx_broadcast);
3043         /* exclude CRC bytes */
3044         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3045                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3046
3047         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3048                             &oes->rx_discards, &nes->rx_discards);
3049         /* GLV_REPC not supported */
3050         /* GLV_RMPC not supported */
3051         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3052                             &oes->rx_unknown_protocol,
3053                             &nes->rx_unknown_protocol);
3054         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3055                                   vsi->offset_loaded, &oes->tx_bytes,
3056                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3057         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3058                             vsi->offset_loaded, &oes->tx_unicast,
3059                             &nes->tx_unicast);
3060         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3061                             vsi->offset_loaded, &oes->tx_multicast,
3062                             &nes->tx_multicast);
3063         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3064                             vsi->offset_loaded,  &oes->tx_broadcast,
3065                             &nes->tx_broadcast);
3066         /* GLV_TDPC not supported */
3067         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3068                             &oes->tx_errors, &nes->tx_errors);
3069         vsi->offset_loaded = true;
3070
3071         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3072                     vsi->vsi_id);
3073         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3074         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3075         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3076         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3077         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3078         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3079                     nes->rx_unknown_protocol);
3080         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3081         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3082         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3083         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3084         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3085         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3086         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3087                     vsi->vsi_id);
3088 }
3089
3090 static void
3091 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3092 {
3093         unsigned int i;
3094         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3095         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3096
3097         /* Get rx/tx bytes of internal transfer packets */
3098         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3099                                   I40E_GLV_GORCL(hw->port),
3100                                   pf->offset_loaded,
3101                                   &pf->internal_stats_offset.rx_bytes,
3102                                   &pf->internal_stats.rx_bytes,
3103                                   &pf->internal_prev_rx_bytes);
3104         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3105                                   I40E_GLV_GOTCL(hw->port),
3106                                   pf->offset_loaded,
3107                                   &pf->internal_stats_offset.tx_bytes,
3108                                   &pf->internal_stats.tx_bytes,
3109                                   &pf->internal_prev_tx_bytes);
3110         /* Get total internal rx packet count */
3111         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3112                             I40E_GLV_UPRCL(hw->port),
3113                             pf->offset_loaded,
3114                             &pf->internal_stats_offset.rx_unicast,
3115                             &pf->internal_stats.rx_unicast);
3116         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3117                             I40E_GLV_MPRCL(hw->port),
3118                             pf->offset_loaded,
3119                             &pf->internal_stats_offset.rx_multicast,
3120                             &pf->internal_stats.rx_multicast);
3121         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3122                             I40E_GLV_BPRCL(hw->port),
3123                             pf->offset_loaded,
3124                             &pf->internal_stats_offset.rx_broadcast,
3125                             &pf->internal_stats.rx_broadcast);
3126         /* Get total internal tx packet count */
3127         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3128                             I40E_GLV_UPTCL(hw->port),
3129                             pf->offset_loaded,
3130                             &pf->internal_stats_offset.tx_unicast,
3131                             &pf->internal_stats.tx_unicast);
3132         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3133                             I40E_GLV_MPTCL(hw->port),
3134                             pf->offset_loaded,
3135                             &pf->internal_stats_offset.tx_multicast,
3136                             &pf->internal_stats.tx_multicast);
3137         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3138                             I40E_GLV_BPTCL(hw->port),
3139                             pf->offset_loaded,
3140                             &pf->internal_stats_offset.tx_broadcast,
3141                             &pf->internal_stats.tx_broadcast);
3142
3143         /* exclude CRC size */
3144         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3145                 pf->internal_stats.rx_multicast +
3146                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3147
3148         /* Get statistics of struct i40e_eth_stats */
3149         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3150                                   I40E_GLPRT_GORCL(hw->port),
3151                                   pf->offset_loaded, &os->eth.rx_bytes,
3152                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3153         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3154                             I40E_GLPRT_UPRCL(hw->port),
3155                             pf->offset_loaded, &os->eth.rx_unicast,
3156                             &ns->eth.rx_unicast);
3157         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3158                             I40E_GLPRT_MPRCL(hw->port),
3159                             pf->offset_loaded, &os->eth.rx_multicast,
3160                             &ns->eth.rx_multicast);
3161         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3162                             I40E_GLPRT_BPRCL(hw->port),
3163                             pf->offset_loaded, &os->eth.rx_broadcast,
3164                             &ns->eth.rx_broadcast);
3165         /* Workaround: CRC size should not be included in byte statistics,
3166          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3167          * packet.
3168          */
3169         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3170                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3171
3172         /* exclude internal rx bytes
3173          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3174          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3175          * value.
3176          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3177          */
3178         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3179                 ns->eth.rx_bytes = 0;
3180         else
3181                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3182
3183         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3184                 ns->eth.rx_unicast = 0;
3185         else
3186                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3187
3188         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3189                 ns->eth.rx_multicast = 0;
3190         else
3191                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3192
3193         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3194                 ns->eth.rx_broadcast = 0;
3195         else
3196                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3197
3198         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3199                             pf->offset_loaded, &os->eth.rx_discards,
3200                             &ns->eth.rx_discards);
3201         /* GLPRT_REPC not supported */
3202         /* GLPRT_RMPC not supported */
3203         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3204                             pf->offset_loaded,
3205                             &os->eth.rx_unknown_protocol,
3206                             &ns->eth.rx_unknown_protocol);
3207         i40e_stat_update_48(hw, I40E_GL_RXERR1_H(hw->pf_id + I40E_MAX_VF),
3208                             I40E_GL_RXERR1_L(hw->pf_id + I40E_MAX_VF),
3209                             pf->offset_loaded, &pf->rx_err1_offset,
3210                             &pf->rx_err1);
3211         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3212                                   I40E_GLPRT_GOTCL(hw->port),
3213                                   pf->offset_loaded, &os->eth.tx_bytes,
3214                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3215         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3216                             I40E_GLPRT_UPTCL(hw->port),
3217                             pf->offset_loaded, &os->eth.tx_unicast,
3218                             &ns->eth.tx_unicast);
3219         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3220                             I40E_GLPRT_MPTCL(hw->port),
3221                             pf->offset_loaded, &os->eth.tx_multicast,
3222                             &ns->eth.tx_multicast);
3223         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3224                             I40E_GLPRT_BPTCL(hw->port),
3225                             pf->offset_loaded, &os->eth.tx_broadcast,
3226                             &ns->eth.tx_broadcast);
3227         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3228                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3229
3230         /* exclude internal tx bytes
3231          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3232          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3233          * value.
3234          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3235          */
3236         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3237                 ns->eth.tx_bytes = 0;
3238         else
3239                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3240
3241         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3242                 ns->eth.tx_unicast = 0;
3243         else
3244                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3245
3246         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3247                 ns->eth.tx_multicast = 0;
3248         else
3249                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3250
3251         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3252                 ns->eth.tx_broadcast = 0;
3253         else
3254                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3255
3256         /* GLPRT_TEPC not supported */
3257
3258         /* additional port specific stats */
3259         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3260                             pf->offset_loaded, &os->tx_dropped_link_down,
3261                             &ns->tx_dropped_link_down);
3262         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3263                             pf->offset_loaded, &os->crc_errors,
3264                             &ns->crc_errors);
3265         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3266                             pf->offset_loaded, &os->illegal_bytes,
3267                             &ns->illegal_bytes);
3268         /* GLPRT_ERRBC not supported */
3269         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3270                             pf->offset_loaded, &os->mac_local_faults,
3271                             &ns->mac_local_faults);
3272         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3273                             pf->offset_loaded, &os->mac_remote_faults,
3274                             &ns->mac_remote_faults);
3275         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3276                             pf->offset_loaded, &os->rx_length_errors,
3277                             &ns->rx_length_errors);
3278         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3279                             pf->offset_loaded, &os->link_xon_rx,
3280                             &ns->link_xon_rx);
3281         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3282                             pf->offset_loaded, &os->link_xoff_rx,
3283                             &ns->link_xoff_rx);
3284         for (i = 0; i < 8; i++) {
3285                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3286                                     pf->offset_loaded,
3287                                     &os->priority_xon_rx[i],
3288                                     &ns->priority_xon_rx[i]);
3289                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3290                                     pf->offset_loaded,
3291                                     &os->priority_xoff_rx[i],
3292                                     &ns->priority_xoff_rx[i]);
3293         }
3294         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3295                             pf->offset_loaded, &os->link_xon_tx,
3296                             &ns->link_xon_tx);
3297         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3298                             pf->offset_loaded, &os->link_xoff_tx,
3299                             &ns->link_xoff_tx);
3300         for (i = 0; i < 8; i++) {
3301                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3302                                     pf->offset_loaded,
3303                                     &os->priority_xon_tx[i],
3304                                     &ns->priority_xon_tx[i]);
3305                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3306                                     pf->offset_loaded,
3307                                     &os->priority_xoff_tx[i],
3308                                     &ns->priority_xoff_tx[i]);
3309                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3310                                     pf->offset_loaded,
3311                                     &os->priority_xon_2_xoff[i],
3312                                     &ns->priority_xon_2_xoff[i]);
3313         }
3314         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3315                             I40E_GLPRT_PRC64L(hw->port),
3316                             pf->offset_loaded, &os->rx_size_64,
3317                             &ns->rx_size_64);
3318         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3319                             I40E_GLPRT_PRC127L(hw->port),
3320                             pf->offset_loaded, &os->rx_size_127,
3321                             &ns->rx_size_127);
3322         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3323                             I40E_GLPRT_PRC255L(hw->port),
3324                             pf->offset_loaded, &os->rx_size_255,
3325                             &ns->rx_size_255);
3326         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3327                             I40E_GLPRT_PRC511L(hw->port),
3328                             pf->offset_loaded, &os->rx_size_511,
3329                             &ns->rx_size_511);
3330         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3331                             I40E_GLPRT_PRC1023L(hw->port),
3332                             pf->offset_loaded, &os->rx_size_1023,
3333                             &ns->rx_size_1023);
3334         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3335                             I40E_GLPRT_PRC1522L(hw->port),
3336                             pf->offset_loaded, &os->rx_size_1522,
3337                             &ns->rx_size_1522);
3338         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3339                             I40E_GLPRT_PRC9522L(hw->port),
3340                             pf->offset_loaded, &os->rx_size_big,
3341                             &ns->rx_size_big);
3342         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3343                             pf->offset_loaded, &os->rx_undersize,
3344                             &ns->rx_undersize);
3345         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3346                             pf->offset_loaded, &os->rx_fragments,
3347                             &ns->rx_fragments);
3348         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3349                             pf->offset_loaded, &os->rx_oversize,
3350                             &ns->rx_oversize);
3351         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3352                             pf->offset_loaded, &os->rx_jabber,
3353                             &ns->rx_jabber);
3354         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3355                             I40E_GLPRT_PTC64L(hw->port),
3356                             pf->offset_loaded, &os->tx_size_64,
3357                             &ns->tx_size_64);
3358         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3359                             I40E_GLPRT_PTC127L(hw->port),
3360                             pf->offset_loaded, &os->tx_size_127,
3361                             &ns->tx_size_127);
3362         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3363                             I40E_GLPRT_PTC255L(hw->port),
3364                             pf->offset_loaded, &os->tx_size_255,
3365                             &ns->tx_size_255);
3366         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3367                             I40E_GLPRT_PTC511L(hw->port),
3368                             pf->offset_loaded, &os->tx_size_511,
3369                             &ns->tx_size_511);
3370         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3371                             I40E_GLPRT_PTC1023L(hw->port),
3372                             pf->offset_loaded, &os->tx_size_1023,
3373                             &ns->tx_size_1023);
3374         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3375                             I40E_GLPRT_PTC1522L(hw->port),
3376                             pf->offset_loaded, &os->tx_size_1522,
3377                             &ns->tx_size_1522);
3378         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3379                             I40E_GLPRT_PTC9522L(hw->port),
3380                             pf->offset_loaded, &os->tx_size_big,
3381                             &ns->tx_size_big);
3382         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3383                            pf->offset_loaded,
3384                            &os->fd_sb_match, &ns->fd_sb_match);
3385         /* GLPRT_MSPDC not supported */
3386         /* GLPRT_XEC not supported */
3387
3388         pf->offset_loaded = true;
3389
3390         if (pf->main_vsi)
3391                 i40e_update_vsi_stats(pf->main_vsi);
3392 }
3393
3394 /* Get all statistics of a port */
3395 static int
3396 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3397 {
3398         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3401         struct i40e_vsi *vsi;
3402         unsigned i;
3403
3404         /* call read registers - updates values, now write them to struct */
3405         i40e_read_stats_registers(pf, hw);
3406
3407         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3408                         pf->main_vsi->eth_stats.rx_multicast +
3409                         pf->main_vsi->eth_stats.rx_broadcast -
3410                         pf->main_vsi->eth_stats.rx_discards -
3411                         pf->rx_err1;
3412         stats->opackets = ns->eth.tx_unicast +
3413                         ns->eth.tx_multicast +
3414                         ns->eth.tx_broadcast;
3415         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3416         stats->obytes   = ns->eth.tx_bytes;
3417         stats->oerrors  = ns->eth.tx_errors +
3418                         pf->main_vsi->eth_stats.tx_errors;
3419
3420         /* Rx Errors */
3421         stats->imissed  = ns->eth.rx_discards +
3422                         pf->main_vsi->eth_stats.rx_discards;
3423         stats->ierrors  = ns->crc_errors +
3424                         ns->rx_length_errors + ns->rx_undersize +
3425                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
3426                         pf->rx_err1;
3427
3428         if (pf->vfs) {
3429                 for (i = 0; i < pf->vf_num; i++) {
3430                         vsi = pf->vfs[i].vsi;
3431                         i40e_update_vsi_stats(vsi);
3432
3433                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3434                                         vsi->eth_stats.rx_multicast +
3435                                         vsi->eth_stats.rx_broadcast -
3436                                         vsi->eth_stats.rx_discards);
3437                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3438                         stats->oerrors  += vsi->eth_stats.tx_errors;
3439                         stats->imissed  += vsi->eth_stats.rx_discards;
3440                 }
3441         }
3442
3443         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3444         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3445         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3446         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3447         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3448         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3449         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3450                     ns->eth.rx_unknown_protocol);
3451         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3452         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3453         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3454         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3455         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3456         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3457
3458         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3459                     ns->tx_dropped_link_down);
3460         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3461         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3462                     ns->illegal_bytes);
3463         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3464         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3465                     ns->mac_local_faults);
3466         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3467                     ns->mac_remote_faults);
3468         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3469                     ns->rx_length_errors);
3470         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3471         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3472         for (i = 0; i < 8; i++) {
3473                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3474                                 i, ns->priority_xon_rx[i]);
3475                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3476                                 i, ns->priority_xoff_rx[i]);
3477         }
3478         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3479         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3480         for (i = 0; i < 8; i++) {
3481                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3482                                 i, ns->priority_xon_tx[i]);
3483                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3484                                 i, ns->priority_xoff_tx[i]);
3485                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3486                                 i, ns->priority_xon_2_xoff[i]);
3487         }
3488         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3489         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3490         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3491         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3492         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3493         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3494         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3495         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3496         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3497         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3498         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3499         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3500         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3501         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3502         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3503         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3504         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3505         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3506         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3507                         ns->mac_short_packet_dropped);
3508         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3509                     ns->checksum_error);
3510         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3511         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3512         return 0;
3513 }
3514
3515 /* Reset the statistics */
3516 static int
3517 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3518 {
3519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3520         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521
3522         /* Mark PF and VSI stats to update the offset, aka "reset" */
3523         pf->offset_loaded = false;
3524         if (pf->main_vsi)
3525                 pf->main_vsi->offset_loaded = false;
3526
3527         /* read the stats, reading current register values into offset */
3528         i40e_read_stats_registers(pf, hw);
3529
3530         return 0;
3531 }
3532
3533 static uint32_t
3534 i40e_xstats_calc_num(void)
3535 {
3536         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3537                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3538                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3539 }
3540
3541 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3542                                      struct rte_eth_xstat_name *xstats_names,
3543                                      __rte_unused unsigned limit)
3544 {
3545         unsigned count = 0;
3546         unsigned i, prio;
3547
3548         if (xstats_names == NULL)
3549                 return i40e_xstats_calc_num();
3550
3551         /* Note: limit checked in rte_eth_xstats_names() */
3552
3553         /* Get stats from i40e_eth_stats struct */
3554         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3555                 strlcpy(xstats_names[count].name,
3556                         rte_i40e_stats_strings[i].name,
3557                         sizeof(xstats_names[count].name));
3558                 count++;
3559         }
3560
3561         /* Get individiual stats from i40e_hw_port struct */
3562         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3563                 strlcpy(xstats_names[count].name,
3564                         rte_i40e_hw_port_strings[i].name,
3565                         sizeof(xstats_names[count].name));
3566                 count++;
3567         }
3568
3569         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3570                 for (prio = 0; prio < 8; prio++) {
3571                         snprintf(xstats_names[count].name,
3572                                  sizeof(xstats_names[count].name),
3573                                  "rx_priority%u_%s", prio,
3574                                  rte_i40e_rxq_prio_strings[i].name);
3575                         count++;
3576                 }
3577         }
3578
3579         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3580                 for (prio = 0; prio < 8; prio++) {
3581                         snprintf(xstats_names[count].name,
3582                                  sizeof(xstats_names[count].name),
3583                                  "tx_priority%u_%s", prio,
3584                                  rte_i40e_txq_prio_strings[i].name);
3585                         count++;
3586                 }
3587         }
3588         return count;
3589 }
3590
3591 static int
3592 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3593                     unsigned n)
3594 {
3595         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597         unsigned i, count, prio;
3598         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3599
3600         count = i40e_xstats_calc_num();
3601         if (n < count)
3602                 return count;
3603
3604         i40e_read_stats_registers(pf, hw);
3605
3606         if (xstats == NULL)
3607                 return 0;
3608
3609         count = 0;
3610
3611         /* Get stats from i40e_eth_stats struct */
3612         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3613                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3614                         rte_i40e_stats_strings[i].offset);
3615                 xstats[count].id = count;
3616                 count++;
3617         }
3618
3619         /* Get individiual stats from i40e_hw_port struct */
3620         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3621                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3622                         rte_i40e_hw_port_strings[i].offset);
3623                 xstats[count].id = count;
3624                 count++;
3625         }
3626
3627         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3628                 for (prio = 0; prio < 8; prio++) {
3629                         xstats[count].value =
3630                                 *(uint64_t *)(((char *)hw_stats) +
3631                                 rte_i40e_rxq_prio_strings[i].offset +
3632                                 (sizeof(uint64_t) * prio));
3633                         xstats[count].id = count;
3634                         count++;
3635                 }
3636         }
3637
3638         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3639                 for (prio = 0; prio < 8; prio++) {
3640                         xstats[count].value =
3641                                 *(uint64_t *)(((char *)hw_stats) +
3642                                 rte_i40e_txq_prio_strings[i].offset +
3643                                 (sizeof(uint64_t) * prio));
3644                         xstats[count].id = count;
3645                         count++;
3646                 }
3647         }
3648
3649         return count;
3650 }
3651
3652 static int
3653 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3654 {
3655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656         u32 full_ver;
3657         u8 ver, patch;
3658         u16 build;
3659         int ret;
3660
3661         full_ver = hw->nvm.oem_ver;
3662         ver = (u8)(full_ver >> 24);
3663         build = (u16)((full_ver >> 8) & 0xffff);
3664         patch = (u8)(full_ver & 0xff);
3665
3666         ret = snprintf(fw_version, fw_size,
3667                  "%d.%d%d 0x%08x %d.%d.%d",
3668                  ((hw->nvm.version >> 12) & 0xf),
3669                  ((hw->nvm.version >> 4) & 0xff),
3670                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3671                  ver, build, patch);
3672         if (ret < 0)
3673                 return -EINVAL;
3674
3675         ret += 1; /* add the size of '\0' */
3676         if (fw_size < (size_t)ret)
3677                 return ret;
3678         else
3679                 return 0;
3680 }
3681
3682 /*
3683  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3684  * the Rx data path does not hang if the FW LLDP is stopped.
3685  * return true if lldp need to stop
3686  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3687  */
3688 static bool
3689 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3690 {
3691         double nvm_ver;
3692         char ver_str[64] = {0};
3693         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694
3695         i40e_fw_version_get(dev, ver_str, 64);
3696         nvm_ver = atof(ver_str);
3697         if ((hw->mac.type == I40E_MAC_X722 ||
3698              hw->mac.type == I40E_MAC_X722_VF) &&
3699              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3700                 return true;
3701         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3702                 return true;
3703
3704         return false;
3705 }
3706
3707 static int
3708 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3709 {
3710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3712         struct i40e_vsi *vsi = pf->main_vsi;
3713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3714
3715         dev_info->max_rx_queues = vsi->nb_qps;
3716         dev_info->max_tx_queues = vsi->nb_qps;
3717         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3718         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3719         dev_info->max_mac_addrs = vsi->max_macaddrs;
3720         dev_info->max_vfs = pci_dev->max_vfs;
3721         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3722         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3723         dev_info->rx_queue_offload_capa = 0;
3724         dev_info->rx_offload_capa =
3725                 DEV_RX_OFFLOAD_VLAN_STRIP |
3726                 DEV_RX_OFFLOAD_QINQ_STRIP |
3727                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3728                 DEV_RX_OFFLOAD_UDP_CKSUM |
3729                 DEV_RX_OFFLOAD_TCP_CKSUM |
3730                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3731                 DEV_RX_OFFLOAD_KEEP_CRC |
3732                 DEV_RX_OFFLOAD_SCATTER |
3733                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3734                 DEV_RX_OFFLOAD_VLAN_FILTER |
3735                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3736                 DEV_RX_OFFLOAD_RSS_HASH;
3737
3738         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3739         dev_info->tx_offload_capa =
3740                 DEV_TX_OFFLOAD_VLAN_INSERT |
3741                 DEV_TX_OFFLOAD_QINQ_INSERT |
3742                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3743                 DEV_TX_OFFLOAD_UDP_CKSUM |
3744                 DEV_TX_OFFLOAD_TCP_CKSUM |
3745                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3746                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3747                 DEV_TX_OFFLOAD_TCP_TSO |
3748                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3749                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3750                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3751                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3752                 DEV_TX_OFFLOAD_MULTI_SEGS |
3753                 dev_info->tx_queue_offload_capa;
3754         dev_info->dev_capa =
3755                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3756                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3757
3758         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3759                                                 sizeof(uint32_t);
3760         dev_info->reta_size = pf->hash_lut_size;
3761         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3762
3763         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3764                 .rx_thresh = {
3765                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3766                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3767                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3768                 },
3769                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3770                 .rx_drop_en = 0,
3771                 .offloads = 0,
3772         };
3773
3774         dev_info->default_txconf = (struct rte_eth_txconf) {
3775                 .tx_thresh = {
3776                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3777                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3778                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3779                 },
3780                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3781                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3782                 .offloads = 0,
3783         };
3784
3785         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3786                 .nb_max = I40E_MAX_RING_DESC,
3787                 .nb_min = I40E_MIN_RING_DESC,
3788                 .nb_align = I40E_ALIGN_RING_DESC,
3789         };
3790
3791         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3792                 .nb_max = I40E_MAX_RING_DESC,
3793                 .nb_min = I40E_MIN_RING_DESC,
3794                 .nb_align = I40E_ALIGN_RING_DESC,
3795                 .nb_seg_max = I40E_TX_MAX_SEG,
3796                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3797         };
3798
3799         if (pf->flags & I40E_FLAG_VMDQ) {
3800                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3801                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3802                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3803                                                 pf->max_nb_vmdq_vsi;
3804                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3805                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3806                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3807         }
3808
3809         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3810                 /* For XL710 */
3811                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3812                 dev_info->default_rxportconf.nb_queues = 2;
3813                 dev_info->default_txportconf.nb_queues = 2;
3814                 if (dev->data->nb_rx_queues == 1)
3815                         dev_info->default_rxportconf.ring_size = 2048;
3816                 else
3817                         dev_info->default_rxportconf.ring_size = 1024;
3818                 if (dev->data->nb_tx_queues == 1)
3819                         dev_info->default_txportconf.ring_size = 1024;
3820                 else
3821                         dev_info->default_txportconf.ring_size = 512;
3822
3823         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3824                 /* For XXV710 */
3825                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3826                 dev_info->default_rxportconf.nb_queues = 1;
3827                 dev_info->default_txportconf.nb_queues = 1;
3828                 dev_info->default_rxportconf.ring_size = 256;
3829                 dev_info->default_txportconf.ring_size = 256;
3830         } else {
3831                 /* For X710 */
3832                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3833                 dev_info->default_rxportconf.nb_queues = 1;
3834                 dev_info->default_txportconf.nb_queues = 1;
3835                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3836                         dev_info->default_rxportconf.ring_size = 512;
3837                         dev_info->default_txportconf.ring_size = 256;
3838                 } else {
3839                         dev_info->default_rxportconf.ring_size = 256;
3840                         dev_info->default_txportconf.ring_size = 256;
3841                 }
3842         }
3843         dev_info->default_rxportconf.burst_size = 32;
3844         dev_info->default_txportconf.burst_size = 32;
3845
3846         return 0;
3847 }
3848
3849 static int
3850 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3851 {
3852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3853         struct i40e_vsi *vsi = pf->main_vsi;
3854         PMD_INIT_FUNC_TRACE();
3855
3856         if (on)
3857                 return i40e_vsi_add_vlan(vsi, vlan_id);
3858         else
3859                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3860 }
3861
3862 static int
3863 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3864                                 enum rte_vlan_type vlan_type,
3865                                 uint16_t tpid, int qinq)
3866 {
3867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868         uint64_t reg_r = 0;
3869         uint64_t reg_w = 0;
3870         uint16_t reg_id = 3;
3871         int ret;
3872
3873         if (qinq) {
3874                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3875                         reg_id = 2;
3876         }
3877
3878         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3879                                           &reg_r, NULL);
3880         if (ret != I40E_SUCCESS) {
3881                 PMD_DRV_LOG(ERR,
3882                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3883                            reg_id);
3884                 return -EIO;
3885         }
3886         PMD_DRV_LOG(DEBUG,
3887                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3888                     reg_id, reg_r);
3889
3890         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3891         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3892         if (reg_r == reg_w) {
3893                 PMD_DRV_LOG(DEBUG, "No need to write");
3894                 return 0;
3895         }
3896
3897         ret = i40e_aq_debug_write_global_register(hw,
3898                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3899                                            reg_w, NULL);
3900         if (ret != I40E_SUCCESS) {
3901                 PMD_DRV_LOG(ERR,
3902                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3903                             reg_id);
3904                 return -EIO;
3905         }
3906         PMD_DRV_LOG(DEBUG,
3907                     "Global register 0x%08x is changed with value 0x%08x",
3908                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3909
3910         return 0;
3911 }
3912
3913 static int
3914 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3915                    enum rte_vlan_type vlan_type,
3916                    uint16_t tpid)
3917 {
3918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3920         int qinq = dev->data->dev_conf.rxmode.offloads &
3921                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3922         int ret = 0;
3923
3924         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3925              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3926             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3927                 PMD_DRV_LOG(ERR,
3928                             "Unsupported vlan type.");
3929                 return -EINVAL;
3930         }
3931
3932         if (pf->support_multi_driver) {
3933                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3934                 return -ENOTSUP;
3935         }
3936
3937         /* 802.1ad frames ability is added in NVM API 1.7*/
3938         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3939                 if (qinq) {
3940                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3941                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3942                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3943                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3944                 } else {
3945                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3946                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3947                 }
3948                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3949                 if (ret != I40E_SUCCESS) {
3950                         PMD_DRV_LOG(ERR,
3951                                     "Set switch config failed aq_err: %d",
3952                                     hw->aq.asq_last_status);
3953                         ret = -EIO;
3954                 }
3955         } else
3956                 /* If NVM API < 1.7, keep the register setting */
3957                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3958                                                       tpid, qinq);
3959
3960         return ret;
3961 }
3962
3963 /* Configure outer vlan stripping on or off in QinQ mode */
3964 static int
3965 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3966 {
3967         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3968         int ret = I40E_SUCCESS;
3969         uint32_t reg;
3970
3971         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3972                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3973                 return -EINVAL;
3974         }
3975
3976         /* Configure for outer VLAN RX stripping */
3977         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
3978
3979         if (on)
3980                 reg |= I40E_VSI_TSR_QINQ_STRIP;
3981         else
3982                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
3983
3984         ret = i40e_aq_debug_write_register(hw,
3985                                                    I40E_VSI_TSR(vsi->vsi_id),
3986                                                    reg, NULL);
3987         if (ret < 0) {
3988                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
3989                                     vsi->vsi_id);
3990                 return I40E_ERR_CONFIG;
3991         }
3992
3993         return ret;
3994 }
3995
3996 static int
3997 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3998 {
3999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4000         struct i40e_vsi *vsi = pf->main_vsi;
4001         struct rte_eth_rxmode *rxmode;
4002
4003         rxmode = &dev->data->dev_conf.rxmode;
4004         if (mask & ETH_VLAN_FILTER_MASK) {
4005                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4006                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4007                 else
4008                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4009         }
4010
4011         if (mask & ETH_VLAN_STRIP_MASK) {
4012                 /* Enable or disable VLAN stripping */
4013                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4014                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4015                 else
4016                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4017         }
4018
4019         if (mask & ETH_VLAN_EXTEND_MASK) {
4020                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4021                         i40e_vsi_config_double_vlan(vsi, TRUE);
4022                         /* Set global registers with default ethertype. */
4023                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4024                                            RTE_ETHER_TYPE_VLAN);
4025                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4026                                            RTE_ETHER_TYPE_VLAN);
4027                 }
4028                 else
4029                         i40e_vsi_config_double_vlan(vsi, FALSE);
4030         }
4031
4032         if (mask & ETH_QINQ_STRIP_MASK) {
4033                 /* Enable or disable outer VLAN stripping */
4034                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4035                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4036                 else
4037                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4038         }
4039
4040         return 0;
4041 }
4042
4043 static void
4044 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4045                           __rte_unused uint16_t queue,
4046                           __rte_unused int on)
4047 {
4048         PMD_INIT_FUNC_TRACE();
4049 }
4050
4051 static int
4052 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4053 {
4054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4055         struct i40e_vsi *vsi = pf->main_vsi;
4056         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4057         struct i40e_vsi_vlan_pvid_info info;
4058
4059         memset(&info, 0, sizeof(info));
4060         info.on = on;
4061         if (info.on)
4062                 info.config.pvid = pvid;
4063         else {
4064                 info.config.reject.tagged =
4065                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4066                 info.config.reject.untagged =
4067                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4068         }
4069
4070         return i40e_vsi_vlan_pvid_set(vsi, &info);
4071 }
4072
4073 static int
4074 i40e_dev_led_on(struct rte_eth_dev *dev)
4075 {
4076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         uint32_t mode = i40e_led_get(hw);
4078
4079         if (mode == 0)
4080                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4081
4082         return 0;
4083 }
4084
4085 static int
4086 i40e_dev_led_off(struct rte_eth_dev *dev)
4087 {
4088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089         uint32_t mode = i40e_led_get(hw);
4090
4091         if (mode != 0)
4092                 i40e_led_set(hw, 0, false);
4093
4094         return 0;
4095 }
4096
4097 static int
4098 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4099 {
4100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4102
4103         fc_conf->pause_time = pf->fc_conf.pause_time;
4104
4105         /* read out from register, in case they are modified by other port */
4106         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4107                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4108         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4109                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4110
4111         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4112         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4113
4114          /* Return current mode according to actual setting*/
4115         switch (hw->fc.current_mode) {
4116         case I40E_FC_FULL:
4117                 fc_conf->mode = RTE_FC_FULL;
4118                 break;
4119         case I40E_FC_TX_PAUSE:
4120                 fc_conf->mode = RTE_FC_TX_PAUSE;
4121                 break;
4122         case I40E_FC_RX_PAUSE:
4123                 fc_conf->mode = RTE_FC_RX_PAUSE;
4124                 break;
4125         case I40E_FC_NONE:
4126         default:
4127                 fc_conf->mode = RTE_FC_NONE;
4128         };
4129
4130         return 0;
4131 }
4132
4133 static int
4134 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4135 {
4136         uint32_t mflcn_reg, fctrl_reg, reg;
4137         uint32_t max_high_water;
4138         uint8_t i, aq_failure;
4139         int err;
4140         struct i40e_hw *hw;
4141         struct i40e_pf *pf;
4142         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4143                 [RTE_FC_NONE] = I40E_FC_NONE,
4144                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4145                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4146                 [RTE_FC_FULL] = I40E_FC_FULL
4147         };
4148
4149         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4150
4151         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4152         if ((fc_conf->high_water > max_high_water) ||
4153                         (fc_conf->high_water < fc_conf->low_water)) {
4154                 PMD_INIT_LOG(ERR,
4155                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4156                         max_high_water);
4157                 return -EINVAL;
4158         }
4159
4160         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4161         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4162         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4163
4164         pf->fc_conf.pause_time = fc_conf->pause_time;
4165         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4166         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4167
4168         PMD_INIT_FUNC_TRACE();
4169
4170         /* All the link flow control related enable/disable register
4171          * configuration is handle by the F/W
4172          */
4173         err = i40e_set_fc(hw, &aq_failure, true);
4174         if (err < 0)
4175                 return -ENOSYS;
4176
4177         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4178                 /* Configure flow control refresh threshold,
4179                  * the value for stat_tx_pause_refresh_timer[8]
4180                  * is used for global pause operation.
4181                  */
4182
4183                 I40E_WRITE_REG(hw,
4184                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4185                                pf->fc_conf.pause_time);
4186
4187                 /* configure the timer value included in transmitted pause
4188                  * frame,
4189                  * the value for stat_tx_pause_quanta[8] is used for global
4190                  * pause operation
4191                  */
4192                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4193                                pf->fc_conf.pause_time);
4194
4195                 fctrl_reg = I40E_READ_REG(hw,
4196                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4197
4198                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4199                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4200                 else
4201                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4202
4203                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4204                                fctrl_reg);
4205         } else {
4206                 /* Configure pause time (2 TCs per register) */
4207                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4208                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4209                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4210
4211                 /* Configure flow control refresh threshold value */
4212                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4213                                pf->fc_conf.pause_time / 2);
4214
4215                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4216
4217                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4218                  *depending on configuration
4219                  */
4220                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4221                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4222                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4223                 } else {
4224                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4225                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4226                 }
4227
4228                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4229         }
4230
4231         if (!pf->support_multi_driver) {
4232                 /* config water marker both based on the packets and bytes */
4233                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4234                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4235                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4236                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4237                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4238                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4239                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4240                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4241                                   << I40E_KILOSHIFT);
4242                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4243                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4244                                    << I40E_KILOSHIFT);
4245         } else {
4246                 PMD_DRV_LOG(ERR,
4247                             "Water marker configuration is not supported.");
4248         }
4249
4250         I40E_WRITE_FLUSH(hw);
4251
4252         return 0;
4253 }
4254
4255 static int
4256 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4257                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4258 {
4259         PMD_INIT_FUNC_TRACE();
4260
4261         return -ENOSYS;
4262 }
4263
4264 /* Add a MAC address, and update filters */
4265 static int
4266 i40e_macaddr_add(struct rte_eth_dev *dev,
4267                  struct rte_ether_addr *mac_addr,
4268                  __rte_unused uint32_t index,
4269                  uint32_t pool)
4270 {
4271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4272         struct i40e_mac_filter_info mac_filter;
4273         struct i40e_vsi *vsi;
4274         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4275         int ret;
4276
4277         /* If VMDQ not enabled or configured, return */
4278         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4279                           !pf->nb_cfg_vmdq_vsi)) {
4280                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4281                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4282                         pool);
4283                 return -ENOTSUP;
4284         }
4285
4286         if (pool > pf->nb_cfg_vmdq_vsi) {
4287                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4288                                 pool, pf->nb_cfg_vmdq_vsi);
4289                 return -EINVAL;
4290         }
4291
4292         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4293         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4294                 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4295         else
4296                 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4297
4298         if (pool == 0)
4299                 vsi = pf->main_vsi;
4300         else
4301                 vsi = pf->vmdq[pool - 1].vsi;
4302
4303         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4304         if (ret != I40E_SUCCESS) {
4305                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4306                 return -ENODEV;
4307         }
4308         return 0;
4309 }
4310
4311 /* Remove a MAC address, and update filters */
4312 static void
4313 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4314 {
4315         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4316         struct i40e_vsi *vsi;
4317         struct rte_eth_dev_data *data = dev->data;
4318         struct rte_ether_addr *macaddr;
4319         int ret;
4320         uint32_t i;
4321         uint64_t pool_sel;
4322
4323         macaddr = &(data->mac_addrs[index]);
4324
4325         pool_sel = dev->data->mac_pool_sel[index];
4326
4327         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4328                 if (pool_sel & (1ULL << i)) {
4329                         if (i == 0)
4330                                 vsi = pf->main_vsi;
4331                         else {
4332                                 /* No VMDQ pool enabled or configured */
4333                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4334                                         (i > pf->nb_cfg_vmdq_vsi)) {
4335                                         PMD_DRV_LOG(ERR,
4336                                                 "No VMDQ pool enabled/configured");
4337                                         return;
4338                                 }
4339                                 vsi = pf->vmdq[i - 1].vsi;
4340                         }
4341                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4342
4343                         if (ret) {
4344                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4345                                 return;
4346                         }
4347                 }
4348         }
4349 }
4350
4351 static int
4352 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4353 {
4354         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4355         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4356         uint32_t reg;
4357         int ret;
4358
4359         if (!lut)
4360                 return -EINVAL;
4361
4362         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4363                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4364                                           vsi->type != I40E_VSI_SRIOV,
4365                                           lut, lut_size);
4366                 if (ret) {
4367                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4368                         return ret;
4369                 }
4370         } else {
4371                 uint32_t *lut_dw = (uint32_t *)lut;
4372                 uint16_t i, lut_size_dw = lut_size / 4;
4373
4374                 if (vsi->type == I40E_VSI_SRIOV) {
4375                         for (i = 0; i <= lut_size_dw; i++) {
4376                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4377                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4378                         }
4379                 } else {
4380                         for (i = 0; i < lut_size_dw; i++)
4381                                 lut_dw[i] = I40E_READ_REG(hw,
4382                                                           I40E_PFQF_HLUT(i));
4383                 }
4384         }
4385
4386         return 0;
4387 }
4388
4389 int
4390 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4391 {
4392         struct i40e_pf *pf;
4393         struct i40e_hw *hw;
4394
4395         if (!vsi || !lut)
4396                 return -EINVAL;
4397
4398         pf = I40E_VSI_TO_PF(vsi);
4399         hw = I40E_VSI_TO_HW(vsi);
4400
4401         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4402                 enum i40e_status_code status;
4403
4404                 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4405                                              vsi->type != I40E_VSI_SRIOV,
4406                                              lut, lut_size);
4407                 if (status) {
4408                         PMD_DRV_LOG(ERR,
4409                                     "Failed to update RSS lookup table, error status: %d",
4410                                     status);
4411                         return -EIO;
4412                 }
4413         } else {
4414                 uint32_t *lut_dw = (uint32_t *)lut;
4415                 uint16_t i, lut_size_dw = lut_size / 4;
4416
4417                 if (vsi->type == I40E_VSI_SRIOV) {
4418                         for (i = 0; i < lut_size_dw; i++)
4419                                 I40E_WRITE_REG(
4420                                         hw,
4421                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4422                                         lut_dw[i]);
4423                 } else {
4424                         for (i = 0; i < lut_size_dw; i++)
4425                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4426                                                lut_dw[i]);
4427                 }
4428                 I40E_WRITE_FLUSH(hw);
4429         }
4430
4431         return 0;
4432 }
4433
4434 static int
4435 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4436                          struct rte_eth_rss_reta_entry64 *reta_conf,
4437                          uint16_t reta_size)
4438 {
4439         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4440         uint16_t i, lut_size = pf->hash_lut_size;
4441         uint16_t idx, shift;
4442         uint8_t *lut;
4443         int ret;
4444
4445         if (reta_size != lut_size ||
4446                 reta_size > ETH_RSS_RETA_SIZE_512) {
4447                 PMD_DRV_LOG(ERR,
4448                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4449                         reta_size, lut_size);
4450                 return -EINVAL;
4451         }
4452
4453         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4454         if (!lut) {
4455                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4456                 return -ENOMEM;
4457         }
4458         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4459         if (ret)
4460                 goto out;
4461         for (i = 0; i < reta_size; i++) {
4462                 idx = i / RTE_RETA_GROUP_SIZE;
4463                 shift = i % RTE_RETA_GROUP_SIZE;
4464                 if (reta_conf[idx].mask & (1ULL << shift))
4465                         lut[i] = reta_conf[idx].reta[shift];
4466         }
4467         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4468
4469         pf->adapter->rss_reta_updated = 1;
4470
4471 out:
4472         rte_free(lut);
4473
4474         return ret;
4475 }
4476
4477 static int
4478 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4479                         struct rte_eth_rss_reta_entry64 *reta_conf,
4480                         uint16_t reta_size)
4481 {
4482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4483         uint16_t i, lut_size = pf->hash_lut_size;
4484         uint16_t idx, shift;
4485         uint8_t *lut;
4486         int ret;
4487
4488         if (reta_size != lut_size ||
4489                 reta_size > ETH_RSS_RETA_SIZE_512) {
4490                 PMD_DRV_LOG(ERR,
4491                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4492                         reta_size, lut_size);
4493                 return -EINVAL;
4494         }
4495
4496         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4497         if (!lut) {
4498                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4499                 return -ENOMEM;
4500         }
4501
4502         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4503         if (ret)
4504                 goto out;
4505         for (i = 0; i < reta_size; i++) {
4506                 idx = i / RTE_RETA_GROUP_SIZE;
4507                 shift = i % RTE_RETA_GROUP_SIZE;
4508                 if (reta_conf[idx].mask & (1ULL << shift))
4509                         reta_conf[idx].reta[shift] = lut[i];
4510         }
4511
4512 out:
4513         rte_free(lut);
4514
4515         return ret;
4516 }
4517
4518 /**
4519  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4520  * @hw:   pointer to the HW structure
4521  * @mem:  pointer to mem struct to fill out
4522  * @size: size of memory requested
4523  * @alignment: what to align the allocation to
4524  **/
4525 enum i40e_status_code
4526 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4527                         struct i40e_dma_mem *mem,
4528                         u64 size,
4529                         u32 alignment)
4530 {
4531         static uint64_t i40e_dma_memzone_id;
4532         const struct rte_memzone *mz = NULL;
4533         char z_name[RTE_MEMZONE_NAMESIZE];
4534
4535         if (!mem)
4536                 return I40E_ERR_PARAM;
4537
4538         snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
4539                 __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
4540         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4541                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4542         if (!mz)
4543                 return I40E_ERR_NO_MEMORY;
4544
4545         mem->size = size;
4546         mem->va = mz->addr;
4547         mem->pa = mz->iova;
4548         mem->zone = (const void *)mz;
4549         PMD_DRV_LOG(DEBUG,
4550                 "memzone %s allocated with physical address: %"PRIu64,
4551                 mz->name, mem->pa);
4552
4553         return I40E_SUCCESS;
4554 }
4555
4556 /**
4557  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4558  * @hw:   pointer to the HW structure
4559  * @mem:  ptr to mem struct to free
4560  **/
4561 enum i40e_status_code
4562 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4563                     struct i40e_dma_mem *mem)
4564 {
4565         if (!mem)
4566                 return I40E_ERR_PARAM;
4567
4568         PMD_DRV_LOG(DEBUG,
4569                 "memzone %s to be freed with physical address: %"PRIu64,
4570                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4571         rte_memzone_free((const struct rte_memzone *)mem->zone);
4572         mem->zone = NULL;
4573         mem->va = NULL;
4574         mem->pa = (u64)0;
4575
4576         return I40E_SUCCESS;
4577 }
4578
4579 /**
4580  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4581  * @hw:   pointer to the HW structure
4582  * @mem:  pointer to mem struct to fill out
4583  * @size: size of memory requested
4584  **/
4585 enum i40e_status_code
4586 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4587                          struct i40e_virt_mem *mem,
4588                          u32 size)
4589 {
4590         if (!mem)
4591                 return I40E_ERR_PARAM;
4592
4593         mem->size = size;
4594         mem->va = rte_zmalloc("i40e", size, 0);
4595
4596         if (mem->va)
4597                 return I40E_SUCCESS;
4598         else
4599                 return I40E_ERR_NO_MEMORY;
4600 }
4601
4602 /**
4603  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4604  * @hw:   pointer to the HW structure
4605  * @mem:  pointer to mem struct to free
4606  **/
4607 enum i40e_status_code
4608 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4609                      struct i40e_virt_mem *mem)
4610 {
4611         if (!mem)
4612                 return I40E_ERR_PARAM;
4613
4614         rte_free(mem->va);
4615         mem->va = NULL;
4616
4617         return I40E_SUCCESS;
4618 }
4619
4620 void
4621 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4622 {
4623         rte_spinlock_init(&sp->spinlock);
4624 }
4625
4626 void
4627 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4628 {
4629         rte_spinlock_lock(&sp->spinlock);
4630 }
4631
4632 void
4633 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4634 {
4635         rte_spinlock_unlock(&sp->spinlock);
4636 }
4637
4638 void
4639 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4640 {
4641         return;
4642 }
4643
4644 /**
4645  * Get the hardware capabilities, which will be parsed
4646  * and saved into struct i40e_hw.
4647  */
4648 static int
4649 i40e_get_cap(struct i40e_hw *hw)
4650 {
4651         struct i40e_aqc_list_capabilities_element_resp *buf;
4652         uint16_t len, size = 0;
4653         int ret;
4654
4655         /* Calculate a huge enough buff for saving response data temporarily */
4656         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4657                                                 I40E_MAX_CAP_ELE_NUM;
4658         buf = rte_zmalloc("i40e", len, 0);
4659         if (!buf) {
4660                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4661                 return I40E_ERR_NO_MEMORY;
4662         }
4663
4664         /* Get, parse the capabilities and save it to hw */
4665         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4666                         i40e_aqc_opc_list_func_capabilities, NULL);
4667         if (ret != I40E_SUCCESS)
4668                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4669
4670         /* Free the temporary buffer after being used */
4671         rte_free(buf);
4672
4673         return ret;
4674 }
4675
4676 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4677
4678 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4679                 const char *value,
4680                 void *opaque)
4681 {
4682         struct i40e_pf *pf;
4683         unsigned long num;
4684         char *end;
4685
4686         pf = (struct i40e_pf *)opaque;
4687         RTE_SET_USED(key);
4688
4689         errno = 0;
4690         num = strtoul(value, &end, 0);
4691         if (errno != 0 || end == value || *end != 0) {
4692                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4693                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4694                 return -(EINVAL);
4695         }
4696
4697         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4698                 pf->vf_nb_qp_max = (uint16_t)num;
4699         else
4700                 /* here return 0 to make next valid same argument work */
4701                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4702                             "power of 2 and equal or less than 16 !, Now it is "
4703                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4704
4705         return 0;
4706 }
4707
4708 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4709 {
4710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4711         struct rte_kvargs *kvlist;
4712         int kvargs_count;
4713
4714         /* set default queue number per VF as 4 */
4715         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4716
4717         if (dev->device->devargs == NULL)
4718                 return 0;
4719
4720         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4721         if (kvlist == NULL)
4722                 return -(EINVAL);
4723
4724         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4725         if (!kvargs_count) {
4726                 rte_kvargs_free(kvlist);
4727                 return 0;
4728         }
4729
4730         if (kvargs_count > 1)
4731                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4732                             "the first invalid or last valid one is used !",
4733                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4734
4735         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4736                            i40e_pf_parse_vf_queue_number_handler, pf);
4737
4738         rte_kvargs_free(kvlist);
4739
4740         return 0;
4741 }
4742
4743 static int
4744 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4745 {
4746         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4747         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4748         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4749         uint16_t qp_count = 0, vsi_count = 0;
4750
4751         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4752                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4753                 return -EINVAL;
4754         }
4755
4756         i40e_pf_config_vf_rxq_number(dev);
4757
4758         /* Add the parameter init for LFC */
4759         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4760         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4761         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4762
4763         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4764         pf->max_num_vsi = hw->func_caps.num_vsis;
4765         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4766         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4767
4768         /* FDir queue/VSI allocation */
4769         pf->fdir_qp_offset = 0;
4770         if (hw->func_caps.fd) {
4771                 pf->flags |= I40E_FLAG_FDIR;
4772                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4773         } else {
4774                 pf->fdir_nb_qps = 0;
4775         }
4776         qp_count += pf->fdir_nb_qps;
4777         vsi_count += 1;
4778
4779         /* LAN queue/VSI allocation */
4780         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4781         if (!hw->func_caps.rss) {
4782                 pf->lan_nb_qps = 1;
4783         } else {
4784                 pf->flags |= I40E_FLAG_RSS;
4785                 if (hw->mac.type == I40E_MAC_X722)
4786                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4787                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4788         }
4789         qp_count += pf->lan_nb_qps;
4790         vsi_count += 1;
4791
4792         /* VF queue/VSI allocation */
4793         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4794         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4795                 pf->flags |= I40E_FLAG_SRIOV;
4796                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4797                 pf->vf_num = pci_dev->max_vfs;
4798                 PMD_DRV_LOG(DEBUG,
4799                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4800                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4801         } else {
4802                 pf->vf_nb_qps = 0;
4803                 pf->vf_num = 0;
4804         }
4805         qp_count += pf->vf_nb_qps * pf->vf_num;
4806         vsi_count += pf->vf_num;
4807
4808         /* VMDq queue/VSI allocation */
4809         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4810         pf->vmdq_nb_qps = 0;
4811         pf->max_nb_vmdq_vsi = 0;
4812         if (hw->func_caps.vmdq) {
4813                 if (qp_count < hw->func_caps.num_tx_qp &&
4814                         vsi_count < hw->func_caps.num_vsis) {
4815                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4816                                 qp_count) / pf->vmdq_nb_qp_max;
4817
4818                         /* Limit the maximum number of VMDq vsi to the maximum
4819                          * ethdev can support
4820                          */
4821                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4822                                 hw->func_caps.num_vsis - vsi_count);
4823                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4824                                 ETH_64_POOLS);
4825                         if (pf->max_nb_vmdq_vsi) {
4826                                 pf->flags |= I40E_FLAG_VMDQ;
4827                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4828                                 PMD_DRV_LOG(DEBUG,
4829                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4830                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4831                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4832                         } else {
4833                                 PMD_DRV_LOG(INFO,
4834                                         "No enough queues left for VMDq");
4835                         }
4836                 } else {
4837                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4838                 }
4839         }
4840         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4841         vsi_count += pf->max_nb_vmdq_vsi;
4842
4843         if (hw->func_caps.dcb)
4844                 pf->flags |= I40E_FLAG_DCB;
4845
4846         if (qp_count > hw->func_caps.num_tx_qp) {
4847                 PMD_DRV_LOG(ERR,
4848                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4849                         qp_count, hw->func_caps.num_tx_qp);
4850                 return -EINVAL;
4851         }
4852         if (vsi_count > hw->func_caps.num_vsis) {
4853                 PMD_DRV_LOG(ERR,
4854                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4855                         vsi_count, hw->func_caps.num_vsis);
4856                 return -EINVAL;
4857         }
4858
4859         return 0;
4860 }
4861
4862 static int
4863 i40e_pf_get_switch_config(struct i40e_pf *pf)
4864 {
4865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4866         struct i40e_aqc_get_switch_config_resp *switch_config;
4867         struct i40e_aqc_switch_config_element_resp *element;
4868         uint16_t start_seid = 0, num_reported;
4869         int ret;
4870
4871         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4872                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4873         if (!switch_config) {
4874                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4875                 return -ENOMEM;
4876         }
4877
4878         /* Get the switch configurations */
4879         ret = i40e_aq_get_switch_config(hw, switch_config,
4880                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4881         if (ret != I40E_SUCCESS) {
4882                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4883                 goto fail;
4884         }
4885         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4886         if (num_reported != 1) { /* The number should be 1 */
4887                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4888                 goto fail;
4889         }
4890
4891         /* Parse the switch configuration elements */
4892         element = &(switch_config->element[0]);
4893         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4894                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4895                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4896         } else
4897                 PMD_DRV_LOG(INFO, "Unknown element type");
4898
4899 fail:
4900         rte_free(switch_config);
4901
4902         return ret;
4903 }
4904
4905 static int
4906 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4907                         uint32_t num)
4908 {
4909         struct pool_entry *entry;
4910
4911         if (pool == NULL || num == 0)
4912                 return -EINVAL;
4913
4914         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4915         if (entry == NULL) {
4916                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4917                 return -ENOMEM;
4918         }
4919
4920         /* queue heap initialize */
4921         pool->num_free = num;
4922         pool->num_alloc = 0;
4923         pool->base = base;
4924         LIST_INIT(&pool->alloc_list);
4925         LIST_INIT(&pool->free_list);
4926
4927         /* Initialize element  */
4928         entry->base = 0;
4929         entry->len = num;
4930
4931         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4932         return 0;
4933 }
4934
4935 static void
4936 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4937 {
4938         struct pool_entry *entry, *next_entry;
4939
4940         if (pool == NULL)
4941                 return;
4942
4943         for (entry = LIST_FIRST(&pool->alloc_list);
4944                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4945                         entry = next_entry) {
4946                 LIST_REMOVE(entry, next);
4947                 rte_free(entry);
4948         }
4949
4950         for (entry = LIST_FIRST(&pool->free_list);
4951                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4952                         entry = next_entry) {
4953                 LIST_REMOVE(entry, next);
4954                 rte_free(entry);
4955         }
4956
4957         pool->num_free = 0;
4958         pool->num_alloc = 0;
4959         pool->base = 0;
4960         LIST_INIT(&pool->alloc_list);
4961         LIST_INIT(&pool->free_list);
4962 }
4963
4964 static int
4965 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4966                        uint32_t base)
4967 {
4968         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4969         uint32_t pool_offset;
4970         uint16_t len;
4971         int insert;
4972
4973         if (pool == NULL) {
4974                 PMD_DRV_LOG(ERR, "Invalid parameter");
4975                 return -EINVAL;
4976         }
4977
4978         pool_offset = base - pool->base;
4979         /* Lookup in alloc list */
4980         LIST_FOREACH(entry, &pool->alloc_list, next) {
4981                 if (entry->base == pool_offset) {
4982                         valid_entry = entry;
4983                         LIST_REMOVE(entry, next);
4984                         break;
4985                 }
4986         }
4987
4988         /* Not find, return */
4989         if (valid_entry == NULL) {
4990                 PMD_DRV_LOG(ERR, "Failed to find entry");
4991                 return -EINVAL;
4992         }
4993
4994         /**
4995          * Found it, move it to free list  and try to merge.
4996          * In order to make merge easier, always sort it by qbase.
4997          * Find adjacent prev and last entries.
4998          */
4999         prev = next = NULL;
5000         LIST_FOREACH(entry, &pool->free_list, next) {
5001                 if (entry->base > valid_entry->base) {
5002                         next = entry;
5003                         break;
5004                 }
5005                 prev = entry;
5006         }
5007
5008         insert = 0;
5009         len = valid_entry->len;
5010         /* Try to merge with next one*/
5011         if (next != NULL) {
5012                 /* Merge with next one */
5013                 if (valid_entry->base + len == next->base) {
5014                         next->base = valid_entry->base;
5015                         next->len += len;
5016                         rte_free(valid_entry);
5017                         valid_entry = next;
5018                         insert = 1;
5019                 }
5020         }
5021
5022         if (prev != NULL) {
5023                 /* Merge with previous one */
5024                 if (prev->base + prev->len == valid_entry->base) {
5025                         prev->len += len;
5026                         /* If it merge with next one, remove next node */
5027                         if (insert == 1) {
5028                                 LIST_REMOVE(valid_entry, next);
5029                                 rte_free(valid_entry);
5030                                 valid_entry = NULL;
5031                         } else {
5032                                 rte_free(valid_entry);
5033                                 valid_entry = NULL;
5034                                 insert = 1;
5035                         }
5036                 }
5037         }
5038
5039         /* Not find any entry to merge, insert */
5040         if (insert == 0) {
5041                 if (prev != NULL)
5042                         LIST_INSERT_AFTER(prev, valid_entry, next);
5043                 else if (next != NULL)
5044                         LIST_INSERT_BEFORE(next, valid_entry, next);
5045                 else /* It's empty list, insert to head */
5046                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5047         }
5048
5049         pool->num_free += len;
5050         pool->num_alloc -= len;
5051
5052         return 0;
5053 }
5054
5055 static int
5056 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5057                        uint16_t num)
5058 {
5059         struct pool_entry *entry, *valid_entry;
5060
5061         if (pool == NULL || num == 0) {
5062                 PMD_DRV_LOG(ERR, "Invalid parameter");
5063                 return -EINVAL;
5064         }
5065
5066         if (pool->num_free < num) {
5067                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5068                             num, pool->num_free);
5069                 return -ENOMEM;
5070         }
5071
5072         valid_entry = NULL;
5073         /* Lookup  in free list and find most fit one */
5074         LIST_FOREACH(entry, &pool->free_list, next) {
5075                 if (entry->len >= num) {
5076                         /* Find best one */
5077                         if (entry->len == num) {
5078                                 valid_entry = entry;
5079                                 break;
5080                         }
5081                         if (valid_entry == NULL || valid_entry->len > entry->len)
5082                                 valid_entry = entry;
5083                 }
5084         }
5085
5086         /* Not find one to satisfy the request, return */
5087         if (valid_entry == NULL) {
5088                 PMD_DRV_LOG(ERR, "No valid entry found");
5089                 return -ENOMEM;
5090         }
5091         /**
5092          * The entry have equal queue number as requested,
5093          * remove it from alloc_list.
5094          */
5095         if (valid_entry->len == num) {
5096                 LIST_REMOVE(valid_entry, next);
5097         } else {
5098                 /**
5099                  * The entry have more numbers than requested,
5100                  * create a new entry for alloc_list and minus its
5101                  * queue base and number in free_list.
5102                  */
5103                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5104                 if (entry == NULL) {
5105                         PMD_DRV_LOG(ERR,
5106                                 "Failed to allocate memory for resource pool");
5107                         return -ENOMEM;
5108                 }
5109                 entry->base = valid_entry->base;
5110                 entry->len = num;
5111                 valid_entry->base += num;
5112                 valid_entry->len -= num;
5113                 valid_entry = entry;
5114         }
5115
5116         /* Insert it into alloc list, not sorted */
5117         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5118
5119         pool->num_free -= valid_entry->len;
5120         pool->num_alloc += valid_entry->len;
5121
5122         return valid_entry->base + pool->base;
5123 }
5124
5125 /**
5126  * bitmap_is_subset - Check whether src2 is subset of src1
5127  **/
5128 static inline int
5129 bitmap_is_subset(uint8_t src1, uint8_t src2)
5130 {
5131         return !((src1 ^ src2) & src2);
5132 }
5133
5134 static enum i40e_status_code
5135 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5136 {
5137         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5138
5139         /* If DCB is not supported, only default TC is supported */
5140         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5141                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5142                 return I40E_NOT_SUPPORTED;
5143         }
5144
5145         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5146                 PMD_DRV_LOG(ERR,
5147                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5148                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5149                 return I40E_NOT_SUPPORTED;
5150         }
5151         return I40E_SUCCESS;
5152 }
5153
5154 int
5155 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5156                                 struct i40e_vsi_vlan_pvid_info *info)
5157 {
5158         struct i40e_hw *hw;
5159         struct i40e_vsi_context ctxt;
5160         uint8_t vlan_flags = 0;
5161         int ret;
5162
5163         if (vsi == NULL || info == NULL) {
5164                 PMD_DRV_LOG(ERR, "invalid parameters");
5165                 return I40E_ERR_PARAM;
5166         }
5167
5168         if (info->on) {
5169                 vsi->info.pvid = info->config.pvid;
5170                 /**
5171                  * If insert pvid is enabled, only tagged pkts are
5172                  * allowed to be sent out.
5173                  */
5174                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5175                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5176         } else {
5177                 vsi->info.pvid = 0;
5178                 if (info->config.reject.tagged == 0)
5179                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5180
5181                 if (info->config.reject.untagged == 0)
5182                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5183         }
5184         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5185                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5186         vsi->info.port_vlan_flags |= vlan_flags;
5187         vsi->info.valid_sections =
5188                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5189         memset(&ctxt, 0, sizeof(ctxt));
5190         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5191         ctxt.seid = vsi->seid;
5192
5193         hw = I40E_VSI_TO_HW(vsi);
5194         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5195         if (ret != I40E_SUCCESS)
5196                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5197
5198         return ret;
5199 }
5200
5201 static int
5202 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5203 {
5204         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5205         int i, ret;
5206         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5207
5208         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5209         if (ret != I40E_SUCCESS)
5210                 return ret;
5211
5212         if (!vsi->seid) {
5213                 PMD_DRV_LOG(ERR, "seid not valid");
5214                 return -EINVAL;
5215         }
5216
5217         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5218         tc_bw_data.tc_valid_bits = enabled_tcmap;
5219         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5220                 tc_bw_data.tc_bw_credits[i] =
5221                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5222
5223         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5224         if (ret != I40E_SUCCESS) {
5225                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5226                 return ret;
5227         }
5228
5229         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5230                                         sizeof(vsi->info.qs_handle));
5231         return I40E_SUCCESS;
5232 }
5233
5234 static enum i40e_status_code
5235 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5236                                  struct i40e_aqc_vsi_properties_data *info,
5237                                  uint8_t enabled_tcmap)
5238 {
5239         enum i40e_status_code ret;
5240         int i, total_tc = 0;
5241         uint16_t qpnum_per_tc, bsf, qp_idx;
5242
5243         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5244         if (ret != I40E_SUCCESS)
5245                 return ret;
5246
5247         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5248                 if (enabled_tcmap & (1 << i))
5249                         total_tc++;
5250         if (total_tc == 0)
5251                 total_tc = 1;
5252         vsi->enabled_tc = enabled_tcmap;
5253
5254         /* Number of queues per enabled TC */
5255         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5256         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5257         bsf = rte_bsf32(qpnum_per_tc);
5258
5259         /* Adjust the queue number to actual queues that can be applied */
5260         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5261                 vsi->nb_qps = qpnum_per_tc * total_tc;
5262
5263         /**
5264          * Configure TC and queue mapping parameters, for enabled TC,
5265          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5266          * default queue will serve it.
5267          */
5268         qp_idx = 0;
5269         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5270                 if (vsi->enabled_tc & (1 << i)) {
5271                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5272                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5273                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5274                         qp_idx += qpnum_per_tc;
5275                 } else
5276                         info->tc_mapping[i] = 0;
5277         }
5278
5279         /* Associate queue number with VSI */
5280         if (vsi->type == I40E_VSI_SRIOV) {
5281                 info->mapping_flags |=
5282                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5283                 for (i = 0; i < vsi->nb_qps; i++)
5284                         info->queue_mapping[i] =
5285                                 rte_cpu_to_le_16(vsi->base_queue + i);
5286         } else {
5287                 info->mapping_flags |=
5288                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5289                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5290         }
5291         info->valid_sections |=
5292                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5293
5294         return I40E_SUCCESS;
5295 }
5296
5297 static int
5298 i40e_veb_release(struct i40e_veb *veb)
5299 {
5300         struct i40e_vsi *vsi;
5301         struct i40e_hw *hw;
5302
5303         if (veb == NULL)
5304                 return -EINVAL;
5305
5306         if (!TAILQ_EMPTY(&veb->head)) {
5307                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5308                 return -EACCES;
5309         }
5310         /* associate_vsi field is NULL for floating VEB */
5311         if (veb->associate_vsi != NULL) {
5312                 vsi = veb->associate_vsi;
5313                 hw = I40E_VSI_TO_HW(vsi);
5314
5315                 vsi->uplink_seid = veb->uplink_seid;
5316                 vsi->veb = NULL;
5317         } else {
5318                 veb->associate_pf->main_vsi->floating_veb = NULL;
5319                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5320         }
5321
5322         i40e_aq_delete_element(hw, veb->seid, NULL);
5323         rte_free(veb);
5324         return I40E_SUCCESS;
5325 }
5326
5327 /* Setup a veb */
5328 static struct i40e_veb *
5329 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5330 {
5331         struct i40e_veb *veb;
5332         int ret;
5333         struct i40e_hw *hw;
5334
5335         if (pf == NULL) {
5336                 PMD_DRV_LOG(ERR,
5337                             "veb setup failed, associated PF shouldn't null");
5338                 return NULL;
5339         }
5340         hw = I40E_PF_TO_HW(pf);
5341
5342         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5343         if (!veb) {
5344                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5345                 goto fail;
5346         }
5347
5348         veb->associate_vsi = vsi;
5349         veb->associate_pf = pf;
5350         TAILQ_INIT(&veb->head);
5351         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5352
5353         /* create floating veb if vsi is NULL */
5354         if (vsi != NULL) {
5355                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5356                                       I40E_DEFAULT_TCMAP, false,
5357                                       &veb->seid, false, NULL);
5358         } else {
5359                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5360                                       true, &veb->seid, false, NULL);
5361         }
5362
5363         if (ret != I40E_SUCCESS) {
5364                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5365                             hw->aq.asq_last_status);
5366                 goto fail;
5367         }
5368         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5369
5370         /* get statistics index */
5371         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5372                                 &veb->stats_idx, NULL, NULL, NULL);
5373         if (ret != I40E_SUCCESS) {
5374                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5375                             hw->aq.asq_last_status);
5376                 goto fail;
5377         }
5378         /* Get VEB bandwidth, to be implemented */
5379         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5380         if (vsi)
5381                 vsi->uplink_seid = veb->seid;
5382
5383         return veb;
5384 fail:
5385         rte_free(veb);
5386         return NULL;
5387 }
5388
5389 int
5390 i40e_vsi_release(struct i40e_vsi *vsi)
5391 {
5392         struct i40e_pf *pf;
5393         struct i40e_hw *hw;
5394         struct i40e_vsi_list *vsi_list;
5395         void *temp;
5396         int ret;
5397         struct i40e_mac_filter *f;
5398         uint16_t user_param;
5399
5400         if (!vsi)
5401                 return I40E_SUCCESS;
5402
5403         if (!vsi->adapter)
5404                 return -EFAULT;
5405
5406         user_param = vsi->user_param;
5407
5408         pf = I40E_VSI_TO_PF(vsi);
5409         hw = I40E_VSI_TO_HW(vsi);
5410
5411         /* VSI has child to attach, release child first */
5412         if (vsi->veb) {
5413                 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5414                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5415                                 return -1;
5416                 }
5417                 i40e_veb_release(vsi->veb);
5418         }
5419
5420         if (vsi->floating_veb) {
5421                 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head,
5422                         list, temp) {
5423                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5424                                 return -1;
5425                 }
5426         }
5427
5428         /* Remove all macvlan filters of the VSI */
5429         i40e_vsi_remove_all_macvlan_filter(vsi);
5430         RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5431                 rte_free(f);
5432
5433         if (vsi->type != I40E_VSI_MAIN &&
5434             ((vsi->type != I40E_VSI_SRIOV) ||
5435             !pf->floating_veb_list[user_param])) {
5436                 /* Remove vsi from parent's sibling list */
5437                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5438                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5439                         return I40E_ERR_PARAM;
5440                 }
5441                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5442                                 &vsi->sib_vsi_list, list);
5443
5444                 /* Remove all switch element of the VSI */
5445                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5446                 if (ret != I40E_SUCCESS)
5447                         PMD_DRV_LOG(ERR, "Failed to delete element");
5448         }
5449
5450         if ((vsi->type == I40E_VSI_SRIOV) &&
5451             pf->floating_veb_list[user_param]) {
5452                 /* Remove vsi from parent's sibling list */
5453                 if (vsi->parent_vsi == NULL ||
5454                     vsi->parent_vsi->floating_veb == NULL) {
5455                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5456                         return I40E_ERR_PARAM;
5457                 }
5458                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5459                              &vsi->sib_vsi_list, list);
5460
5461                 /* Remove all switch element of the VSI */
5462                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5463                 if (ret != I40E_SUCCESS)
5464                         PMD_DRV_LOG(ERR, "Failed to delete element");
5465         }
5466
5467         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5468
5469         if (vsi->type != I40E_VSI_SRIOV)
5470                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5471         rte_free(vsi);
5472
5473         return I40E_SUCCESS;
5474 }
5475
5476 static int
5477 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5478 {
5479         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5480         struct i40e_aqc_remove_macvlan_element_data def_filter;
5481         struct i40e_mac_filter_info filter;
5482         int ret;
5483
5484         if (vsi->type != I40E_VSI_MAIN)
5485                 return I40E_ERR_CONFIG;
5486         memset(&def_filter, 0, sizeof(def_filter));
5487         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5488                                         ETH_ADDR_LEN);
5489         def_filter.vlan_tag = 0;
5490         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5491                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5492         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5493         if (ret != I40E_SUCCESS) {
5494                 struct i40e_mac_filter *f;
5495                 struct rte_ether_addr *mac;
5496
5497                 PMD_DRV_LOG(DEBUG,
5498                             "Cannot remove the default macvlan filter");
5499                 /* It needs to add the permanent mac into mac list */
5500                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5501                 if (f == NULL) {
5502                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5503                         return I40E_ERR_NO_MEMORY;
5504                 }
5505                 mac = &f->mac_info.mac_addr;
5506                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5507                                 ETH_ADDR_LEN);
5508                 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5509                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5510                 vsi->mac_num++;
5511
5512                 return ret;
5513         }
5514         rte_memcpy(&filter.mac_addr,
5515                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5516         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5517         return i40e_vsi_add_mac(vsi, &filter);
5518 }
5519
5520 /*
5521  * i40e_vsi_get_bw_config - Query VSI BW Information
5522  * @vsi: the VSI to be queried
5523  *
5524  * Returns 0 on success, negative value on failure
5525  */
5526 static enum i40e_status_code
5527 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5528 {
5529         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5530         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5531         struct i40e_hw *hw = &vsi->adapter->hw;
5532         i40e_status ret;
5533         int i;
5534         uint32_t bw_max;
5535
5536         memset(&bw_config, 0, sizeof(bw_config));
5537         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5538         if (ret != I40E_SUCCESS) {
5539                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5540                             hw->aq.asq_last_status);
5541                 return ret;
5542         }
5543
5544         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5545         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5546                                         &ets_sla_config, NULL);
5547         if (ret != I40E_SUCCESS) {
5548                 PMD_DRV_LOG(ERR,
5549                         "VSI failed to get TC bandwdith configuration %u",
5550                         hw->aq.asq_last_status);
5551                 return ret;
5552         }
5553
5554         /* store and print out BW info */
5555         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5556         vsi->bw_info.bw_max = bw_config.max_bw;
5557         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5558         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5559         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5560                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5561                      I40E_16_BIT_WIDTH);
5562         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5563                 vsi->bw_info.bw_ets_share_credits[i] =
5564                                 ets_sla_config.share_credits[i];
5565                 vsi->bw_info.bw_ets_credits[i] =
5566                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5567                 /* 4 bits per TC, 4th bit is reserved */
5568                 vsi->bw_info.bw_ets_max[i] =
5569                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5570                                   RTE_LEN2MASK(3, uint8_t));
5571                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5572                             vsi->bw_info.bw_ets_share_credits[i]);
5573                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5574                             vsi->bw_info.bw_ets_credits[i]);
5575                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5576                             vsi->bw_info.bw_ets_max[i]);
5577         }
5578
5579         return I40E_SUCCESS;
5580 }
5581
5582 /* i40e_enable_pf_lb
5583  * @pf: pointer to the pf structure
5584  *
5585  * allow loopback on pf
5586  */
5587 static inline void
5588 i40e_enable_pf_lb(struct i40e_pf *pf)
5589 {
5590         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5591         struct i40e_vsi_context ctxt;
5592         int ret;
5593
5594         /* Use the FW API if FW >= v5.0 */
5595         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5596                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5597                 return;
5598         }
5599
5600         memset(&ctxt, 0, sizeof(ctxt));
5601         ctxt.seid = pf->main_vsi_seid;
5602         ctxt.pf_num = hw->pf_id;
5603         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5604         if (ret) {
5605                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5606                             ret, hw->aq.asq_last_status);
5607                 return;
5608         }
5609         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5610         ctxt.info.valid_sections =
5611                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5612         ctxt.info.switch_id |=
5613                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5614
5615         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5616         if (ret)
5617                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5618                             hw->aq.asq_last_status);
5619 }
5620
5621 /* Setup a VSI */
5622 struct i40e_vsi *
5623 i40e_vsi_setup(struct i40e_pf *pf,
5624                enum i40e_vsi_type type,
5625                struct i40e_vsi *uplink_vsi,
5626                uint16_t user_param)
5627 {
5628         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5629         struct i40e_vsi *vsi;
5630         struct i40e_mac_filter_info filter;
5631         int ret;
5632         struct i40e_vsi_context ctxt;
5633         struct rte_ether_addr broadcast =
5634                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5635
5636         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5637             uplink_vsi == NULL) {
5638                 PMD_DRV_LOG(ERR,
5639                         "VSI setup failed, VSI link shouldn't be NULL");
5640                 return NULL;
5641         }
5642
5643         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5644                 PMD_DRV_LOG(ERR,
5645                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5646                 return NULL;
5647         }
5648
5649         /* two situations
5650          * 1.type is not MAIN and uplink vsi is not NULL
5651          * If uplink vsi didn't setup VEB, create one first under veb field
5652          * 2.type is SRIOV and the uplink is NULL
5653          * If floating VEB is NULL, create one veb under floating veb field
5654          */
5655
5656         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5657             uplink_vsi->veb == NULL) {
5658                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5659
5660                 if (uplink_vsi->veb == NULL) {
5661                         PMD_DRV_LOG(ERR, "VEB setup failed");
5662                         return NULL;
5663                 }
5664                 /* set ALLOWLOOPBACk on pf, when veb is created */
5665                 i40e_enable_pf_lb(pf);
5666         }
5667
5668         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5669             pf->main_vsi->floating_veb == NULL) {
5670                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5671
5672                 if (pf->main_vsi->floating_veb == NULL) {
5673                         PMD_DRV_LOG(ERR, "VEB setup failed");
5674                         return NULL;
5675                 }
5676         }
5677
5678         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5679         if (!vsi) {
5680                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5681                 return NULL;
5682         }
5683         TAILQ_INIT(&vsi->mac_list);
5684         vsi->type = type;
5685         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5686         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5687         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5688         vsi->user_param = user_param;
5689         vsi->vlan_anti_spoof_on = 0;
5690         vsi->vlan_filter_on = 0;
5691         /* Allocate queues */
5692         switch (vsi->type) {
5693         case I40E_VSI_MAIN  :
5694                 vsi->nb_qps = pf->lan_nb_qps;
5695                 break;
5696         case I40E_VSI_SRIOV :
5697                 vsi->nb_qps = pf->vf_nb_qps;
5698                 break;
5699         case I40E_VSI_VMDQ2:
5700                 vsi->nb_qps = pf->vmdq_nb_qps;
5701                 break;
5702         case I40E_VSI_FDIR:
5703                 vsi->nb_qps = pf->fdir_nb_qps;
5704                 break;
5705         default:
5706                 goto fail_mem;
5707         }
5708         /*
5709          * The filter status descriptor is reported in rx queue 0,
5710          * while the tx queue for fdir filter programming has no
5711          * such constraints, can be non-zero queues.
5712          * To simplify it, choose FDIR vsi use queue 0 pair.
5713          * To make sure it will use queue 0 pair, queue allocation
5714          * need be done before this function is called
5715          */
5716         if (type != I40E_VSI_FDIR) {
5717                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5718                         if (ret < 0) {
5719                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5720                                                 vsi->seid, ret);
5721                                 goto fail_mem;
5722                         }
5723                         vsi->base_queue = ret;
5724         } else
5725                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5726
5727         /* VF has MSIX interrupt in VF range, don't allocate here */
5728         if (type == I40E_VSI_MAIN) {
5729                 if (pf->support_multi_driver) {
5730                         /* If support multi-driver, need to use INT0 instead of
5731                          * allocating from msix pool. The Msix pool is init from
5732                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5733                          * to 1 without calling i40e_res_pool_alloc.
5734                          */
5735                         vsi->msix_intr = 0;
5736                         vsi->nb_msix = 1;
5737                 } else {
5738                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5739                                                   RTE_MIN(vsi->nb_qps,
5740                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5741                         if (ret < 0) {
5742                                 PMD_DRV_LOG(ERR,
5743                                             "VSI MAIN %d get heap failed %d",
5744                                             vsi->seid, ret);
5745                                 goto fail_queue_alloc;
5746                         }
5747                         vsi->msix_intr = ret;
5748                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5749                                                RTE_MAX_RXTX_INTR_VEC_ID);
5750                 }
5751         } else if (type != I40E_VSI_SRIOV) {
5752                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5753                 if (ret < 0) {
5754                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5755                         if (type != I40E_VSI_FDIR)
5756                                 goto fail_queue_alloc;
5757                         vsi->msix_intr = 0;
5758                         vsi->nb_msix = 0;
5759                 } else {
5760                         vsi->msix_intr = ret;
5761                         vsi->nb_msix = 1;
5762                 }
5763         } else {
5764                 vsi->msix_intr = 0;
5765                 vsi->nb_msix = 0;
5766         }
5767
5768         /* Add VSI */
5769         if (type == I40E_VSI_MAIN) {
5770                 /* For main VSI, no need to add since it's default one */
5771                 vsi->uplink_seid = pf->mac_seid;
5772                 vsi->seid = pf->main_vsi_seid;
5773                 /* Bind queues with specific MSIX interrupt */
5774                 /**
5775                  * Needs 2 interrupt at least, one for misc cause which will
5776                  * enabled from OS side, Another for queues binding the
5777                  * interrupt from device side only.
5778                  */
5779
5780                 /* Get default VSI parameters from hardware */
5781                 memset(&ctxt, 0, sizeof(ctxt));
5782                 ctxt.seid = vsi->seid;
5783                 ctxt.pf_num = hw->pf_id;
5784                 ctxt.uplink_seid = vsi->uplink_seid;
5785                 ctxt.vf_num = 0;
5786                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5787                 if (ret != I40E_SUCCESS) {
5788                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5789                         goto fail_msix_alloc;
5790                 }
5791                 rte_memcpy(&vsi->info, &ctxt.info,
5792                         sizeof(struct i40e_aqc_vsi_properties_data));
5793                 vsi->vsi_id = ctxt.vsi_number;
5794                 vsi->info.valid_sections = 0;
5795
5796                 /* Configure tc, enabled TC0 only */
5797                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5798                         I40E_SUCCESS) {
5799                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5800                         goto fail_msix_alloc;
5801                 }
5802
5803                 /* TC, queue mapping */
5804                 memset(&ctxt, 0, sizeof(ctxt));
5805                 vsi->info.valid_sections |=
5806                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5807                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5808                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5809                 rte_memcpy(&ctxt.info, &vsi->info,
5810                         sizeof(struct i40e_aqc_vsi_properties_data));
5811                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5812                                                 I40E_DEFAULT_TCMAP);
5813                 if (ret != I40E_SUCCESS) {
5814                         PMD_DRV_LOG(ERR,
5815                                 "Failed to configure TC queue mapping");
5816                         goto fail_msix_alloc;
5817                 }
5818                 ctxt.seid = vsi->seid;
5819                 ctxt.pf_num = hw->pf_id;
5820                 ctxt.uplink_seid = vsi->uplink_seid;
5821                 ctxt.vf_num = 0;
5822
5823                 /* Update VSI parameters */
5824                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5825                 if (ret != I40E_SUCCESS) {
5826                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5827                         goto fail_msix_alloc;
5828                 }
5829
5830                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5831                                                 sizeof(vsi->info.tc_mapping));
5832                 rte_memcpy(&vsi->info.queue_mapping,
5833                                 &ctxt.info.queue_mapping,
5834                         sizeof(vsi->info.queue_mapping));
5835                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5836                 vsi->info.valid_sections = 0;
5837
5838                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5839                                 ETH_ADDR_LEN);
5840
5841                 /**
5842                  * Updating default filter settings are necessary to prevent
5843                  * reception of tagged packets.
5844                  * Some old firmware configurations load a default macvlan
5845                  * filter which accepts both tagged and untagged packets.
5846                  * The updating is to use a normal filter instead if needed.
5847                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5848                  * The firmware with correct configurations load the default
5849                  * macvlan filter which is expected and cannot be removed.
5850                  */
5851                 i40e_update_default_filter_setting(vsi);
5852                 i40e_config_qinq(hw, vsi);
5853         } else if (type == I40E_VSI_SRIOV) {
5854                 memset(&ctxt, 0, sizeof(ctxt));
5855                 /**
5856                  * For other VSI, the uplink_seid equals to uplink VSI's
5857                  * uplink_seid since they share same VEB
5858                  */
5859                 if (uplink_vsi == NULL)
5860                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5861                 else
5862                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5863                 ctxt.pf_num = hw->pf_id;
5864                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5865                 ctxt.uplink_seid = vsi->uplink_seid;
5866                 ctxt.connection_type = 0x1;
5867                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5868
5869                 /* Use the VEB configuration if FW >= v5.0 */
5870                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5871                         /* Configure switch ID */
5872                         ctxt.info.valid_sections |=
5873                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5874                         ctxt.info.switch_id =
5875                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5876                 }
5877
5878                 /* Configure port/vlan */
5879                 ctxt.info.valid_sections |=
5880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5881                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5882                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5883                                                 hw->func_caps.enabled_tcmap);
5884                 if (ret != I40E_SUCCESS) {
5885                         PMD_DRV_LOG(ERR,
5886                                 "Failed to configure TC queue mapping");
5887                         goto fail_msix_alloc;
5888                 }
5889
5890                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5891                 ctxt.info.valid_sections |=
5892                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5893                 /**
5894                  * Since VSI is not created yet, only configure parameter,
5895                  * will add vsi below.
5896                  */
5897
5898                 i40e_config_qinq(hw, vsi);
5899         } else if (type == I40E_VSI_VMDQ2) {
5900                 memset(&ctxt, 0, sizeof(ctxt));
5901                 /*
5902                  * For other VSI, the uplink_seid equals to uplink VSI's
5903                  * uplink_seid since they share same VEB
5904                  */
5905                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5906                 ctxt.pf_num = hw->pf_id;
5907                 ctxt.vf_num = 0;
5908                 ctxt.uplink_seid = vsi->uplink_seid;
5909                 ctxt.connection_type = 0x1;
5910                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5911
5912                 ctxt.info.valid_sections |=
5913                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5914                 /* user_param carries flag to enable loop back */
5915                 if (user_param) {
5916                         ctxt.info.switch_id =
5917                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5918                         ctxt.info.switch_id |=
5919                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5920                 }
5921
5922                 /* Configure port/vlan */
5923                 ctxt.info.valid_sections |=
5924                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5925                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5926                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5927                                                 I40E_DEFAULT_TCMAP);
5928                 if (ret != I40E_SUCCESS) {
5929                         PMD_DRV_LOG(ERR,
5930                                 "Failed to configure TC queue mapping");
5931                         goto fail_msix_alloc;
5932                 }
5933                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5934                 ctxt.info.valid_sections |=
5935                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5936         } else if (type == I40E_VSI_FDIR) {
5937                 memset(&ctxt, 0, sizeof(ctxt));
5938                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5939                 ctxt.pf_num = hw->pf_id;
5940                 ctxt.vf_num = 0;
5941                 ctxt.uplink_seid = vsi->uplink_seid;
5942                 ctxt.connection_type = 0x1;     /* regular data port */
5943                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5944                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5945                                                 I40E_DEFAULT_TCMAP);
5946                 if (ret != I40E_SUCCESS) {
5947                         PMD_DRV_LOG(ERR,
5948                                 "Failed to configure TC queue mapping.");
5949                         goto fail_msix_alloc;
5950                 }
5951                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5952                 ctxt.info.valid_sections |=
5953                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5954         } else {
5955                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5956                 goto fail_msix_alloc;
5957         }
5958
5959         if (vsi->type != I40E_VSI_MAIN) {
5960                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5961                 if (ret != I40E_SUCCESS) {
5962                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5963                                     hw->aq.asq_last_status);
5964                         goto fail_msix_alloc;
5965                 }
5966                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5967                 vsi->info.valid_sections = 0;
5968                 vsi->seid = ctxt.seid;
5969                 vsi->vsi_id = ctxt.vsi_number;
5970                 vsi->sib_vsi_list.vsi = vsi;
5971                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5972                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5973                                           &vsi->sib_vsi_list, list);
5974                 } else {
5975                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5976                                           &vsi->sib_vsi_list, list);
5977                 }
5978         }
5979
5980         /* MAC/VLAN configuration */
5981         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5982         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5983
5984         ret = i40e_vsi_add_mac(vsi, &filter);
5985         if (ret != I40E_SUCCESS) {
5986                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5987                 goto fail_msix_alloc;
5988         }
5989
5990         /* Get VSI BW information */
5991         i40e_vsi_get_bw_config(vsi);
5992         return vsi;
5993 fail_msix_alloc:
5994         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5995 fail_queue_alloc:
5996         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5997 fail_mem:
5998         rte_free(vsi);
5999         return NULL;
6000 }
6001
6002 /* Configure vlan filter on or off */
6003 int
6004 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6005 {
6006         int i, num;
6007         struct i40e_mac_filter *f;
6008         void *temp;
6009         struct i40e_mac_filter_info *mac_filter;
6010         enum i40e_mac_filter_type desired_filter;
6011         int ret = I40E_SUCCESS;
6012
6013         if (on) {
6014                 /* Filter to match MAC and VLAN */
6015                 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6016         } else {
6017                 /* Filter to match only MAC */
6018                 desired_filter = I40E_MAC_PERFECT_MATCH;
6019         }
6020
6021         num = vsi->mac_num;
6022
6023         mac_filter = rte_zmalloc("mac_filter_info_data",
6024                                  num * sizeof(*mac_filter), 0);
6025         if (mac_filter == NULL) {
6026                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6027                 return I40E_ERR_NO_MEMORY;
6028         }
6029
6030         i = 0;
6031
6032         /* Remove all existing mac */
6033         RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6034                 mac_filter[i] = f->mac_info;
6035                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6036                 if (ret) {
6037                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6038                                     on ? "enable" : "disable");
6039                         goto DONE;
6040                 }
6041                 i++;
6042         }
6043
6044         /* Override with new filter */
6045         for (i = 0; i < num; i++) {
6046                 mac_filter[i].filter_type = desired_filter;
6047                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6048                 if (ret) {
6049                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6050                                     on ? "enable" : "disable");
6051                         goto DONE;
6052                 }
6053         }
6054
6055 DONE:
6056         rte_free(mac_filter);
6057         return ret;
6058 }
6059
6060 /* Configure vlan stripping on or off */
6061 int
6062 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6063 {
6064         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6065         struct i40e_vsi_context ctxt;
6066         uint8_t vlan_flags;
6067         int ret = I40E_SUCCESS;
6068
6069         /* Check if it has been already on or off */
6070         if (vsi->info.valid_sections &
6071                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6072                 if (on) {
6073                         if ((vsi->info.port_vlan_flags &
6074                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6075                                 return 0; /* already on */
6076                 } else {
6077                         if ((vsi->info.port_vlan_flags &
6078                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6079                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6080                                 return 0; /* already off */
6081                 }
6082         }
6083
6084         if (on)
6085                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6086         else
6087                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6088         vsi->info.valid_sections =
6089                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6090         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6091         vsi->info.port_vlan_flags |= vlan_flags;
6092         ctxt.seid = vsi->seid;
6093         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6094         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6095         if (ret)
6096                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6097                             on ? "enable" : "disable");
6098
6099         return ret;
6100 }
6101
6102 static int
6103 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6104 {
6105         struct rte_eth_dev_data *data = dev->data;
6106         int ret;
6107         int mask = 0;
6108
6109         /* Apply vlan offload setting */
6110         mask = ETH_VLAN_STRIP_MASK |
6111                ETH_QINQ_STRIP_MASK |
6112                ETH_VLAN_FILTER_MASK |
6113                ETH_VLAN_EXTEND_MASK;
6114         ret = i40e_vlan_offload_set(dev, mask);
6115         if (ret) {
6116                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6117                 return ret;
6118         }
6119
6120         /* Apply pvid setting */
6121         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6122                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6123         if (ret)
6124                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6125
6126         return ret;
6127 }
6128
6129 static int
6130 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6131 {
6132         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6133
6134         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6135 }
6136
6137 static int
6138 i40e_update_flow_control(struct i40e_hw *hw)
6139 {
6140 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6141         struct i40e_link_status link_status;
6142         uint32_t rxfc = 0, txfc = 0, reg;
6143         uint8_t an_info;
6144         int ret;
6145
6146         memset(&link_status, 0, sizeof(link_status));
6147         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6148         if (ret != I40E_SUCCESS) {
6149                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6150                 goto write_reg; /* Disable flow control */
6151         }
6152
6153         an_info = hw->phy.link_info.an_info;
6154         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6155                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6156                 ret = I40E_ERR_NOT_READY;
6157                 goto write_reg; /* Disable flow control */
6158         }
6159         /**
6160          * If link auto negotiation is enabled, flow control needs to
6161          * be configured according to it
6162          */
6163         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6164         case I40E_LINK_PAUSE_RXTX:
6165                 rxfc = 1;
6166                 txfc = 1;
6167                 hw->fc.current_mode = I40E_FC_FULL;
6168                 break;
6169         case I40E_AQ_LINK_PAUSE_RX:
6170                 rxfc = 1;
6171                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6172                 break;
6173         case I40E_AQ_LINK_PAUSE_TX:
6174                 txfc = 1;
6175                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6176                 break;
6177         default:
6178                 hw->fc.current_mode = I40E_FC_NONE;
6179                 break;
6180         }
6181
6182 write_reg:
6183         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6184                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6185         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6186         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6187         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6188         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6189
6190         return ret;
6191 }
6192
6193 /* PF setup */
6194 static int
6195 i40e_pf_setup(struct i40e_pf *pf)
6196 {
6197         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6198         struct i40e_filter_control_settings settings;
6199         struct i40e_vsi *vsi;
6200         int ret;
6201
6202         /* Clear all stats counters */
6203         pf->offset_loaded = FALSE;
6204         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6205         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6206         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6207         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6208         pf->rx_err1 = 0;
6209         pf->rx_err1_offset = 0;
6210
6211         ret = i40e_pf_get_switch_config(pf);
6212         if (ret != I40E_SUCCESS) {
6213                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6214                 return ret;
6215         }
6216
6217         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6218         if (ret)
6219                 PMD_INIT_LOG(WARNING,
6220                         "failed to allocate switch domain for device %d", ret);
6221
6222         if (pf->flags & I40E_FLAG_FDIR) {
6223                 /* make queue allocated first, let FDIR use queue pair 0*/
6224                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6225                 if (ret != I40E_FDIR_QUEUE_ID) {
6226                         PMD_DRV_LOG(ERR,
6227                                 "queue allocation fails for FDIR: ret =%d",
6228                                 ret);
6229                         pf->flags &= ~I40E_FLAG_FDIR;
6230                 }
6231         }
6232         /*  main VSI setup */
6233         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6234         if (!vsi) {
6235                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6236                 return I40E_ERR_NOT_READY;
6237         }
6238         pf->main_vsi = vsi;
6239
6240         /* Configure filter control */
6241         memset(&settings, 0, sizeof(settings));
6242         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6243                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6244         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6245                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6246         else {
6247                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6248                         hw->func_caps.rss_table_size);
6249                 return I40E_ERR_PARAM;
6250         }
6251         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6252                 hw->func_caps.rss_table_size);
6253         pf->hash_lut_size = hw->func_caps.rss_table_size;
6254
6255         /* Enable ethtype and macvlan filters */
6256         settings.enable_ethtype = TRUE;
6257         settings.enable_macvlan = TRUE;
6258         ret = i40e_set_filter_control(hw, &settings);
6259         if (ret)
6260                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6261                                                                 ret);
6262
6263         /* Update flow control according to the auto negotiation */
6264         i40e_update_flow_control(hw);
6265
6266         return I40E_SUCCESS;
6267 }
6268
6269 int
6270 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6271 {
6272         uint32_t reg;
6273         uint16_t j;
6274
6275         /**
6276          * Set or clear TX Queue Disable flags,
6277          * which is required by hardware.
6278          */
6279         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6280         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6281
6282         /* Wait until the request is finished */
6283         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6284                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6285                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6286                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6287                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6288                                                         & 0x1))) {
6289                         break;
6290                 }
6291         }
6292         if (on) {
6293                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6294                         return I40E_SUCCESS; /* already on, skip next steps */
6295
6296                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6297                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6298         } else {
6299                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6300                         return I40E_SUCCESS; /* already off, skip next steps */
6301                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6302         }
6303         /* Write the register */
6304         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6305         /* Check the result */
6306         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6307                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6308                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6309                 if (on) {
6310                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6311                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6312                                 break;
6313                 } else {
6314                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6315                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6316                                 break;
6317                 }
6318         }
6319         /* Check if it is timeout */
6320         if (j >= I40E_CHK_Q_ENA_COUNT) {
6321                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6322                             (on ? "enable" : "disable"), q_idx);
6323                 return I40E_ERR_TIMEOUT;
6324         }
6325
6326         return I40E_SUCCESS;
6327 }
6328
6329 int
6330 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6331 {
6332         uint32_t reg;
6333         uint16_t j;
6334
6335         /* Wait until the request is finished */
6336         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6337                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6338                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6339                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6340                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6341                         break;
6342         }
6343
6344         if (on) {
6345                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6346                         return I40E_SUCCESS; /* Already on, skip next steps */
6347                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6348         } else {
6349                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6350                         return I40E_SUCCESS; /* Already off, skip next steps */
6351                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6352         }
6353
6354         /* Write the register */
6355         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6356         /* Check the result */
6357         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6358                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6359                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6360                 if (on) {
6361                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6362                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6363                                 break;
6364                 } else {
6365                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6366                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6367                                 break;
6368                 }
6369         }
6370
6371         /* Check if it is timeout */
6372         if (j >= I40E_CHK_Q_ENA_COUNT) {
6373                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6374                             (on ? "enable" : "disable"), q_idx);
6375                 return I40E_ERR_TIMEOUT;
6376         }
6377
6378         return I40E_SUCCESS;
6379 }
6380
6381 /* Initialize VSI for TX */
6382 static int
6383 i40e_dev_tx_init(struct i40e_pf *pf)
6384 {
6385         struct rte_eth_dev_data *data = pf->dev_data;
6386         uint16_t i;
6387         uint32_t ret = I40E_SUCCESS;
6388         struct i40e_tx_queue *txq;
6389
6390         for (i = 0; i < data->nb_tx_queues; i++) {
6391                 txq = data->tx_queues[i];
6392                 if (!txq || !txq->q_set)
6393                         continue;
6394                 ret = i40e_tx_queue_init(txq);
6395                 if (ret != I40E_SUCCESS)
6396                         break;
6397         }
6398         if (ret == I40E_SUCCESS)
6399                 i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
6400
6401         return ret;
6402 }
6403
6404 /* Initialize VSI for RX */
6405 static int
6406 i40e_dev_rx_init(struct i40e_pf *pf)
6407 {
6408         struct rte_eth_dev_data *data = pf->dev_data;
6409         int ret = I40E_SUCCESS;
6410         uint16_t i;
6411         struct i40e_rx_queue *rxq;
6412
6413         i40e_pf_config_rss(pf);
6414         for (i = 0; i < data->nb_rx_queues; i++) {
6415                 rxq = data->rx_queues[i];
6416                 if (!rxq || !rxq->q_set)
6417                         continue;
6418
6419                 ret = i40e_rx_queue_init(rxq);
6420                 if (ret != I40E_SUCCESS) {
6421                         PMD_DRV_LOG(ERR,
6422                                 "Failed to do RX queue initialization");
6423                         break;
6424                 }
6425         }
6426         if (ret == I40E_SUCCESS)
6427                 i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
6428
6429         return ret;
6430 }
6431
6432 static int
6433 i40e_dev_rxtx_init(struct i40e_pf *pf)
6434 {
6435         int err;
6436
6437         err = i40e_dev_tx_init(pf);
6438         if (err) {
6439                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6440                 return err;
6441         }
6442         err = i40e_dev_rx_init(pf);
6443         if (err) {
6444                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6445                 return err;
6446         }
6447
6448         return err;
6449 }
6450
6451 static int
6452 i40e_vmdq_setup(struct rte_eth_dev *dev)
6453 {
6454         struct rte_eth_conf *conf = &dev->data->dev_conf;
6455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6456         int i, err, conf_vsis, j, loop;
6457         struct i40e_vsi *vsi;
6458         struct i40e_vmdq_info *vmdq_info;
6459         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6460         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6461
6462         /*
6463          * Disable interrupt to avoid message from VF. Furthermore, it will
6464          * avoid race condition in VSI creation/destroy.
6465          */
6466         i40e_pf_disable_irq0(hw);
6467
6468         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6469                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6470                 return -ENOTSUP;
6471         }
6472
6473         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6474         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6475                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6476                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6477                         pf->max_nb_vmdq_vsi);
6478                 return -ENOTSUP;
6479         }
6480
6481         if (pf->vmdq != NULL) {
6482                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6483                 return 0;
6484         }
6485
6486         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6487                                 sizeof(*vmdq_info) * conf_vsis, 0);
6488
6489         if (pf->vmdq == NULL) {
6490                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6491                 return -ENOMEM;
6492         }
6493
6494         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6495
6496         /* Create VMDQ VSI */
6497         for (i = 0; i < conf_vsis; i++) {
6498                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6499                                 vmdq_conf->enable_loop_back);
6500                 if (vsi == NULL) {
6501                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6502                         err = -1;
6503                         goto err_vsi_setup;
6504                 }
6505                 vmdq_info = &pf->vmdq[i];
6506                 vmdq_info->pf = pf;
6507                 vmdq_info->vsi = vsi;
6508         }
6509         pf->nb_cfg_vmdq_vsi = conf_vsis;
6510
6511         /* Configure Vlan */
6512         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6513         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6514                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6515                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6516                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6517                                         vmdq_conf->pool_map[i].vlan_id, j);
6518
6519                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6520                                                 vmdq_conf->pool_map[i].vlan_id);
6521                                 if (err) {
6522                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6523                                         err = -1;
6524                                         goto err_vsi_setup;
6525                                 }
6526                         }
6527                 }
6528         }
6529
6530         i40e_pf_enable_irq0(hw);
6531
6532         return 0;
6533
6534 err_vsi_setup:
6535         for (i = 0; i < conf_vsis; i++)
6536                 if (pf->vmdq[i].vsi == NULL)
6537                         break;
6538                 else
6539                         i40e_vsi_release(pf->vmdq[i].vsi);
6540
6541         rte_free(pf->vmdq);
6542         pf->vmdq = NULL;
6543         i40e_pf_enable_irq0(hw);
6544         return err;
6545 }
6546
6547 static void
6548 i40e_stat_update_32(struct i40e_hw *hw,
6549                    uint32_t reg,
6550                    bool offset_loaded,
6551                    uint64_t *offset,
6552                    uint64_t *stat)
6553 {
6554         uint64_t new_data;
6555
6556         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6557         if (!offset_loaded)
6558                 *offset = new_data;
6559
6560         if (new_data >= *offset)
6561                 *stat = (uint64_t)(new_data - *offset);
6562         else
6563                 *stat = (uint64_t)((new_data +
6564                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6565 }
6566
6567 static void
6568 i40e_stat_update_48(struct i40e_hw *hw,
6569                    uint32_t hireg,
6570                    uint32_t loreg,
6571                    bool offset_loaded,
6572                    uint64_t *offset,
6573                    uint64_t *stat)
6574 {
6575         uint64_t new_data;
6576
6577         if (hw->device_id == I40E_DEV_ID_QEMU) {
6578                 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6579                 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6580                                 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6581         } else {
6582                 new_data = I40E_READ_REG64(hw, loreg);
6583         }
6584
6585         if (!offset_loaded)
6586                 *offset = new_data;
6587
6588         if (new_data >= *offset)
6589                 *stat = new_data - *offset;
6590         else
6591                 *stat = (uint64_t)((new_data +
6592                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6593
6594         *stat &= I40E_48_BIT_MASK;
6595 }
6596
6597 /* Disable IRQ0 */
6598 void
6599 i40e_pf_disable_irq0(struct i40e_hw *hw)
6600 {
6601         /* Disable all interrupt types */
6602         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6603                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6604         I40E_WRITE_FLUSH(hw);
6605 }
6606
6607 /* Enable IRQ0 */
6608 void
6609 i40e_pf_enable_irq0(struct i40e_hw *hw)
6610 {
6611         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6612                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6613                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6614                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6615         I40E_WRITE_FLUSH(hw);
6616 }
6617
6618 static void
6619 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6620 {
6621         /* read pending request and disable first */
6622         i40e_pf_disable_irq0(hw);
6623         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6624         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6625                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6626
6627         if (no_queue)
6628                 /* Link no queues with irq0 */
6629                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6630                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6631 }
6632
6633 static void
6634 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6635 {
6636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6638         int i;
6639         uint16_t abs_vf_id;
6640         uint32_t index, offset, val;
6641
6642         if (!pf->vfs)
6643                 return;
6644         /**
6645          * Try to find which VF trigger a reset, use absolute VF id to access
6646          * since the reg is global register.
6647          */
6648         for (i = 0; i < pf->vf_num; i++) {
6649                 abs_vf_id = hw->func_caps.vf_base_id + i;
6650                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6651                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6652                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6653                 /* VFR event occurred */
6654                 if (val & (0x1 << offset)) {
6655                         int ret;
6656
6657                         /* Clear the event first */
6658                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6659                                                         (0x1 << offset));
6660                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6661                         /**
6662                          * Only notify a VF reset event occurred,
6663                          * don't trigger another SW reset
6664                          */
6665                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6666                         if (ret != I40E_SUCCESS)
6667                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6668                 }
6669         }
6670 }
6671
6672 static void
6673 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6674 {
6675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6676         int i;
6677
6678         for (i = 0; i < pf->vf_num; i++)
6679                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6680 }
6681
6682 static void
6683 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6684 {
6685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6686         struct i40e_arq_event_info info;
6687         uint16_t pending, opcode;
6688         int ret;
6689
6690         info.buf_len = I40E_AQ_BUF_SZ;
6691         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6692         if (!info.msg_buf) {
6693                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6694                 return;
6695         }
6696
6697         pending = 1;
6698         while (pending) {
6699                 ret = i40e_clean_arq_element(hw, &info, &pending);
6700
6701                 if (ret != I40E_SUCCESS) {
6702                         PMD_DRV_LOG(INFO,
6703                                 "Failed to read msg from AdminQ, aq_err: %u",
6704                                 hw->aq.asq_last_status);
6705                         break;
6706                 }
6707                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6708
6709                 switch (opcode) {
6710                 case i40e_aqc_opc_send_msg_to_pf:
6711                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6712                         i40e_pf_host_handle_vf_msg(dev,
6713                                         rte_le_to_cpu_16(info.desc.retval),
6714                                         rte_le_to_cpu_32(info.desc.cookie_high),
6715                                         rte_le_to_cpu_32(info.desc.cookie_low),
6716                                         info.msg_buf,
6717                                         info.msg_len);
6718                         break;
6719                 case i40e_aqc_opc_get_link_status:
6720                         ret = i40e_dev_link_update(dev, 0);
6721                         if (!ret)
6722                                 rte_eth_dev_callback_process(dev,
6723                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6724                         break;
6725                 default:
6726                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6727                                     opcode);
6728                         break;
6729                 }
6730         }
6731         rte_free(info.msg_buf);
6732 }
6733
6734 static void
6735 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6736 {
6737 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6738 #define I40E_MDD_CLEAR16 0xFFFF
6739         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6740         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6741         bool mdd_detected = false;
6742         struct i40e_pf_vf *vf;
6743         uint32_t reg;
6744         int i;
6745
6746         /* find what triggered the MDD event */
6747         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6748         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6749                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6750                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6751                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6752                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6753                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6754                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6755                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6756                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6757                                         hw->func_caps.base_queue;
6758                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6759                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6760                                 event, queue, pf_num, vf_num, dev->data->name);
6761                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6762                 mdd_detected = true;
6763         }
6764         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6765         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6766                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6767                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6768                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6769                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6770                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6771                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6772                                         hw->func_caps.base_queue;
6773
6774                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6775                                 "queue %d of function 0x%02x device %s\n",
6776                                         event, queue, func, dev->data->name);
6777                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6778                 mdd_detected = true;
6779         }
6780
6781         if (mdd_detected) {
6782                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6783                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6784                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6785                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6786                 }
6787                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6788                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6789                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6790                                         I40E_MDD_CLEAR16);
6791                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6792                 }
6793         }
6794
6795         /* see if one of the VFs needs its hand slapped */
6796         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6797                 vf = &pf->vfs[i];
6798                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6799                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6800                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6801                                         I40E_MDD_CLEAR16);
6802                         vf->num_mdd_events++;
6803                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6804                                         PRIu64 "times\n",
6805                                         i, vf->num_mdd_events);
6806                 }
6807
6808                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6809                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6810                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6811                                         I40E_MDD_CLEAR16);
6812                         vf->num_mdd_events++;
6813                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6814                                         PRIu64 "times\n",
6815                                         i, vf->num_mdd_events);
6816                 }
6817         }
6818 }
6819
6820 /**
6821  * Interrupt handler triggered by NIC  for handling
6822  * specific interrupt.
6823  *
6824  * @param handle
6825  *  Pointer to interrupt handle.
6826  * @param param
6827  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6828  *
6829  * @return
6830  *  void
6831  */
6832 static void
6833 i40e_dev_interrupt_handler(void *param)
6834 {
6835         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837         uint32_t icr0;
6838
6839         /* Disable interrupt */
6840         i40e_pf_disable_irq0(hw);
6841
6842         /* read out interrupt causes */
6843         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6844
6845         /* No interrupt event indicated */
6846         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6847                 PMD_DRV_LOG(INFO, "No interrupt event");
6848                 goto done;
6849         }
6850         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6851                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6852         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6853                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6854                 i40e_handle_mdd_event(dev);
6855         }
6856         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6857                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6858         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6859                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6860         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6861                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6862         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6863                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6864         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6865                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6866
6867         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6868                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6869                 i40e_dev_handle_vfr_event(dev);
6870         }
6871         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6872                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6873                 i40e_dev_handle_aq_msg(dev);
6874         }
6875
6876 done:
6877         /* Enable interrupt */
6878         i40e_pf_enable_irq0(hw);
6879 }
6880
6881 static void
6882 i40e_dev_alarm_handler(void *param)
6883 {
6884         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886         uint32_t icr0;
6887
6888         /* Disable interrupt */
6889         i40e_pf_disable_irq0(hw);
6890
6891         /* read out interrupt causes */
6892         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6893
6894         /* No interrupt event indicated */
6895         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6896                 goto done;
6897         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6898                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6899         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6900                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6901                 i40e_handle_mdd_event(dev);
6902         }
6903         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6904                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6905         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6906                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6907         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6908                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6909         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6910                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6911         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6912                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6913
6914         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6915                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6916                 i40e_dev_handle_vfr_event(dev);
6917         }
6918         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6919                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6920                 i40e_dev_handle_aq_msg(dev);
6921         }
6922
6923 done:
6924         /* Enable interrupt */
6925         i40e_pf_enable_irq0(hw);
6926         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6927                           i40e_dev_alarm_handler, dev);
6928 }
6929
6930 int
6931 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6932                          struct i40e_macvlan_filter *filter,
6933                          int total)
6934 {
6935         int ele_num, ele_buff_size;
6936         int num, actual_num, i;
6937         uint16_t flags;
6938         int ret = I40E_SUCCESS;
6939         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6940         struct i40e_aqc_add_macvlan_element_data *req_list;
6941
6942         if (filter == NULL  || total == 0)
6943                 return I40E_ERR_PARAM;
6944         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6945         ele_buff_size = hw->aq.asq_buf_size;
6946
6947         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6948         if (req_list == NULL) {
6949                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6950                 return I40E_ERR_NO_MEMORY;
6951         }
6952
6953         num = 0;
6954         do {
6955                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6956                 memset(req_list, 0, ele_buff_size);
6957
6958                 for (i = 0; i < actual_num; i++) {
6959                         rte_memcpy(req_list[i].mac_addr,
6960                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6961                         req_list[i].vlan_tag =
6962                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6963
6964                         switch (filter[num + i].filter_type) {
6965                         case I40E_MAC_PERFECT_MATCH:
6966                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6967                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6968                                 break;
6969                         case I40E_MACVLAN_PERFECT_MATCH:
6970                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6971                                 break;
6972                         case I40E_MAC_HASH_MATCH:
6973                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6974                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6975                                 break;
6976                         case I40E_MACVLAN_HASH_MATCH:
6977                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6978                                 break;
6979                         default:
6980                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6981                                 ret = I40E_ERR_PARAM;
6982                                 goto DONE;
6983                         }
6984
6985                         req_list[i].queue_number = 0;
6986
6987                         req_list[i].flags = rte_cpu_to_le_16(flags);
6988                 }
6989
6990                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6991                                                 actual_num, NULL);
6992                 if (ret != I40E_SUCCESS) {
6993                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6994                         goto DONE;
6995                 }
6996                 num += actual_num;
6997         } while (num < total);
6998
6999 DONE:
7000         rte_free(req_list);
7001         return ret;
7002 }
7003
7004 int
7005 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7006                             struct i40e_macvlan_filter *filter,
7007                             int total)
7008 {
7009         int ele_num, ele_buff_size;
7010         int num, actual_num, i;
7011         uint16_t flags;
7012         int ret = I40E_SUCCESS;
7013         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7014         struct i40e_aqc_remove_macvlan_element_data *req_list;
7015
7016         if (filter == NULL  || total == 0)
7017                 return I40E_ERR_PARAM;
7018
7019         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7020         ele_buff_size = hw->aq.asq_buf_size;
7021
7022         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7023         if (req_list == NULL) {
7024                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7025                 return I40E_ERR_NO_MEMORY;
7026         }
7027
7028         num = 0;
7029         do {
7030                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7031                 memset(req_list, 0, ele_buff_size);
7032
7033                 for (i = 0; i < actual_num; i++) {
7034                         rte_memcpy(req_list[i].mac_addr,
7035                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7036                         req_list[i].vlan_tag =
7037                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7038
7039                         switch (filter[num + i].filter_type) {
7040                         case I40E_MAC_PERFECT_MATCH:
7041                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7042                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7043                                 break;
7044                         case I40E_MACVLAN_PERFECT_MATCH:
7045                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7046                                 break;
7047                         case I40E_MAC_HASH_MATCH:
7048                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7049                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7050                                 break;
7051                         case I40E_MACVLAN_HASH_MATCH:
7052                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7053                                 break;
7054                         default:
7055                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7056                                 ret = I40E_ERR_PARAM;
7057                                 goto DONE;
7058                         }
7059                         req_list[i].flags = rte_cpu_to_le_16(flags);
7060                 }
7061
7062                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7063                                                 actual_num, NULL);
7064                 if (ret != I40E_SUCCESS) {
7065                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7066                         goto DONE;
7067                 }
7068                 num += actual_num;
7069         } while (num < total);
7070
7071 DONE:
7072         rte_free(req_list);
7073         return ret;
7074 }
7075
7076 /* Find out specific MAC filter */
7077 static struct i40e_mac_filter *
7078 i40e_find_mac_filter(struct i40e_vsi *vsi,
7079                          struct rte_ether_addr *macaddr)
7080 {
7081         struct i40e_mac_filter *f;
7082
7083         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7084                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7085                         return f;
7086         }
7087
7088         return NULL;
7089 }
7090
7091 static bool
7092 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7093                          uint16_t vlan_id)
7094 {
7095         uint32_t vid_idx, vid_bit;
7096
7097         if (vlan_id > ETH_VLAN_ID_MAX)
7098                 return 0;
7099
7100         vid_idx = I40E_VFTA_IDX(vlan_id);
7101         vid_bit = I40E_VFTA_BIT(vlan_id);
7102
7103         if (vsi->vfta[vid_idx] & vid_bit)
7104                 return 1;
7105         else
7106                 return 0;
7107 }
7108
7109 static void
7110 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7111                        uint16_t vlan_id, bool on)
7112 {
7113         uint32_t vid_idx, vid_bit;
7114
7115         vid_idx = I40E_VFTA_IDX(vlan_id);
7116         vid_bit = I40E_VFTA_BIT(vlan_id);
7117
7118         if (on)
7119                 vsi->vfta[vid_idx] |= vid_bit;
7120         else
7121                 vsi->vfta[vid_idx] &= ~vid_bit;
7122 }
7123
7124 void
7125 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7126                      uint16_t vlan_id, bool on)
7127 {
7128         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7129         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7130         int ret;
7131
7132         if (vlan_id > ETH_VLAN_ID_MAX)
7133                 return;
7134
7135         i40e_store_vlan_filter(vsi, vlan_id, on);
7136
7137         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7138                 return;
7139
7140         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7141
7142         if (on) {
7143                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7144                                        &vlan_data, 1, NULL);
7145                 if (ret != I40E_SUCCESS)
7146                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7147         } else {
7148                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7149                                           &vlan_data, 1, NULL);
7150                 if (ret != I40E_SUCCESS)
7151                         PMD_DRV_LOG(ERR,
7152                                     "Failed to remove vlan filter");
7153         }
7154 }
7155
7156 /**
7157  * Find all vlan options for specific mac addr,
7158  * return with actual vlan found.
7159  */
7160 int
7161 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7162                            struct i40e_macvlan_filter *mv_f,
7163                            int num, struct rte_ether_addr *addr)
7164 {
7165         int i;
7166         uint32_t j, k;
7167
7168         /**
7169          * Not to use i40e_find_vlan_filter to decrease the loop time,
7170          * although the code looks complex.
7171           */
7172         if (num < vsi->vlan_num)
7173                 return I40E_ERR_PARAM;
7174
7175         i = 0;
7176         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7177                 if (vsi->vfta[j]) {
7178                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7179                                 if (vsi->vfta[j] & (1 << k)) {
7180                                         if (i > num - 1) {
7181                                                 PMD_DRV_LOG(ERR,
7182                                                         "vlan number doesn't match");
7183                                                 return I40E_ERR_PARAM;
7184                                         }
7185                                         rte_memcpy(&mv_f[i].macaddr,
7186                                                         addr, ETH_ADDR_LEN);
7187                                         mv_f[i].vlan_id =
7188                                                 j * I40E_UINT32_BIT_SIZE + k;
7189                                         i++;
7190                                 }
7191                         }
7192                 }
7193         }
7194         return I40E_SUCCESS;
7195 }
7196
7197 static inline int
7198 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7199                            struct i40e_macvlan_filter *mv_f,
7200                            int num,
7201                            uint16_t vlan)
7202 {
7203         int i = 0;
7204         struct i40e_mac_filter *f;
7205
7206         if (num < vsi->mac_num)
7207                 return I40E_ERR_PARAM;
7208
7209         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7210                 if (i > num - 1) {
7211                         PMD_DRV_LOG(ERR, "buffer number not match");
7212                         return I40E_ERR_PARAM;
7213                 }
7214                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7215                                 ETH_ADDR_LEN);
7216                 mv_f[i].vlan_id = vlan;
7217                 mv_f[i].filter_type = f->mac_info.filter_type;
7218                 i++;
7219         }
7220
7221         return I40E_SUCCESS;
7222 }
7223
7224 static int
7225 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7226 {
7227         int i, j, num;
7228         struct i40e_mac_filter *f;
7229         struct i40e_macvlan_filter *mv_f;
7230         int ret = I40E_SUCCESS;
7231
7232         if (vsi == NULL || vsi->mac_num == 0)
7233                 return I40E_ERR_PARAM;
7234
7235         /* Case that no vlan is set */
7236         if (vsi->vlan_num == 0)
7237                 num = vsi->mac_num;
7238         else
7239                 num = vsi->mac_num * vsi->vlan_num;
7240
7241         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7242         if (mv_f == NULL) {
7243                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7244                 return I40E_ERR_NO_MEMORY;
7245         }
7246
7247         i = 0;
7248         if (vsi->vlan_num == 0) {
7249                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7250                         rte_memcpy(&mv_f[i].macaddr,
7251                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7252                         mv_f[i].filter_type = f->mac_info.filter_type;
7253                         mv_f[i].vlan_id = 0;
7254                         i++;
7255                 }
7256         } else {
7257                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7258                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7259                                         vsi->vlan_num, &f->mac_info.mac_addr);
7260                         if (ret != I40E_SUCCESS)
7261                                 goto DONE;
7262                         for (j = i; j < i + vsi->vlan_num; j++)
7263                                 mv_f[j].filter_type = f->mac_info.filter_type;
7264                         i += vsi->vlan_num;
7265                 }
7266         }
7267
7268         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7269 DONE:
7270         rte_free(mv_f);
7271
7272         return ret;
7273 }
7274
7275 int
7276 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7277 {
7278         struct i40e_macvlan_filter *mv_f;
7279         int mac_num;
7280         int ret = I40E_SUCCESS;
7281
7282         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7283                 return I40E_ERR_PARAM;
7284
7285         /* If it's already set, just return */
7286         if (i40e_find_vlan_filter(vsi,vlan))
7287                 return I40E_SUCCESS;
7288
7289         mac_num = vsi->mac_num;
7290
7291         if (mac_num == 0) {
7292                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7293                 return I40E_ERR_PARAM;
7294         }
7295
7296         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7297
7298         if (mv_f == NULL) {
7299                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7300                 return I40E_ERR_NO_MEMORY;
7301         }
7302
7303         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7304
7305         if (ret != I40E_SUCCESS)
7306                 goto DONE;
7307
7308         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7309
7310         if (ret != I40E_SUCCESS)
7311                 goto DONE;
7312
7313         i40e_set_vlan_filter(vsi, vlan, 1);
7314
7315         vsi->vlan_num++;
7316         ret = I40E_SUCCESS;
7317 DONE:
7318         rte_free(mv_f);
7319         return ret;
7320 }
7321
7322 int
7323 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7324 {
7325         struct i40e_macvlan_filter *mv_f;
7326         int mac_num;
7327         int ret = I40E_SUCCESS;
7328
7329         /**
7330          * Vlan 0 is the generic filter for untagged packets
7331          * and can't be removed.
7332          */
7333         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7334                 return I40E_ERR_PARAM;
7335
7336         /* If can't find it, just return */
7337         if (!i40e_find_vlan_filter(vsi, vlan))
7338                 return I40E_ERR_PARAM;
7339
7340         mac_num = vsi->mac_num;
7341
7342         if (mac_num == 0) {
7343                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7344                 return I40E_ERR_PARAM;
7345         }
7346
7347         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7348
7349         if (mv_f == NULL) {
7350                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7351                 return I40E_ERR_NO_MEMORY;
7352         }
7353
7354         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7355
7356         if (ret != I40E_SUCCESS)
7357                 goto DONE;
7358
7359         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7360
7361         if (ret != I40E_SUCCESS)
7362                 goto DONE;
7363
7364         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7365         if (vsi->vlan_num == 1) {
7366                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7367                 if (ret != I40E_SUCCESS)
7368                         goto DONE;
7369
7370                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7371                 if (ret != I40E_SUCCESS)
7372                         goto DONE;
7373         }
7374
7375         i40e_set_vlan_filter(vsi, vlan, 0);
7376
7377         vsi->vlan_num--;
7378         ret = I40E_SUCCESS;
7379 DONE:
7380         rte_free(mv_f);
7381         return ret;
7382 }
7383
7384 int
7385 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7386 {
7387         struct i40e_mac_filter *f;
7388         struct i40e_macvlan_filter *mv_f;
7389         int i, vlan_num = 0;
7390         int ret = I40E_SUCCESS;
7391
7392         /* If it's add and we've config it, return */
7393         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7394         if (f != NULL)
7395                 return I40E_SUCCESS;
7396         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7397                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7398
7399                 /**
7400                  * If vlan_num is 0, that's the first time to add mac,
7401                  * set mask for vlan_id 0.
7402                  */
7403                 if (vsi->vlan_num == 0) {
7404                         i40e_set_vlan_filter(vsi, 0, 1);
7405                         vsi->vlan_num = 1;
7406                 }
7407                 vlan_num = vsi->vlan_num;
7408         } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7409                         mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7410                 vlan_num = 1;
7411
7412         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7413         if (mv_f == NULL) {
7414                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7415                 return I40E_ERR_NO_MEMORY;
7416         }
7417
7418         for (i = 0; i < vlan_num; i++) {
7419                 mv_f[i].filter_type = mac_filter->filter_type;
7420                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7421                                 ETH_ADDR_LEN);
7422         }
7423
7424         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7425                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7426                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7427                                         &mac_filter->mac_addr);
7428                 if (ret != I40E_SUCCESS)
7429                         goto DONE;
7430         }
7431
7432         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7433         if (ret != I40E_SUCCESS)
7434                 goto DONE;
7435
7436         /* Add the mac addr into mac list */
7437         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7438         if (f == NULL) {
7439                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7440                 ret = I40E_ERR_NO_MEMORY;
7441                 goto DONE;
7442         }
7443         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7444                         ETH_ADDR_LEN);
7445         f->mac_info.filter_type = mac_filter->filter_type;
7446         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7447         vsi->mac_num++;
7448
7449         ret = I40E_SUCCESS;
7450 DONE:
7451         rte_free(mv_f);
7452
7453         return ret;
7454 }
7455
7456 int
7457 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7458 {
7459         struct i40e_mac_filter *f;
7460         struct i40e_macvlan_filter *mv_f;
7461         int i, vlan_num;
7462         enum i40e_mac_filter_type filter_type;
7463         int ret = I40E_SUCCESS;
7464
7465         /* Can't find it, return an error */
7466         f = i40e_find_mac_filter(vsi, addr);
7467         if (f == NULL)
7468                 return I40E_ERR_PARAM;
7469
7470         vlan_num = vsi->vlan_num;
7471         filter_type = f->mac_info.filter_type;
7472         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7473                 filter_type == I40E_MACVLAN_HASH_MATCH) {
7474                 if (vlan_num == 0) {
7475                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7476                         return I40E_ERR_PARAM;
7477                 }
7478         } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7479                         filter_type == I40E_MAC_HASH_MATCH)
7480                 vlan_num = 1;
7481
7482         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7483         if (mv_f == NULL) {
7484                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7485                 return I40E_ERR_NO_MEMORY;
7486         }
7487
7488         for (i = 0; i < vlan_num; i++) {
7489                 mv_f[i].filter_type = filter_type;
7490                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7491                                 ETH_ADDR_LEN);
7492         }
7493         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7494                         filter_type == I40E_MACVLAN_HASH_MATCH) {
7495                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7496                 if (ret != I40E_SUCCESS)
7497                         goto DONE;
7498         }
7499
7500         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7501         if (ret != I40E_SUCCESS)
7502                 goto DONE;
7503
7504         /* Remove the mac addr into mac list */
7505         TAILQ_REMOVE(&vsi->mac_list, f, next);
7506         rte_free(f);
7507         vsi->mac_num--;
7508
7509         ret = I40E_SUCCESS;
7510 DONE:
7511         rte_free(mv_f);
7512         return ret;
7513 }
7514
7515 /* Configure hash enable flags for RSS */
7516 uint64_t
7517 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7518 {
7519         uint64_t hena = 0;
7520         int i;
7521
7522         if (!flags)
7523                 return hena;
7524
7525         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7526                 if (flags & (1ULL << i))
7527                         hena |= adapter->pctypes_tbl[i];
7528         }
7529
7530         return hena;
7531 }
7532
7533 /* Parse the hash enable flags */
7534 uint64_t
7535 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7536 {
7537         uint64_t rss_hf = 0;
7538
7539         if (!flags)
7540                 return rss_hf;
7541         int i;
7542
7543         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7544                 if (flags & adapter->pctypes_tbl[i])
7545                         rss_hf |= (1ULL << i);
7546         }
7547         return rss_hf;
7548 }
7549
7550 /* Disable RSS */
7551 void
7552 i40e_pf_disable_rss(struct i40e_pf *pf)
7553 {
7554         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7555
7556         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7557         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7558         I40E_WRITE_FLUSH(hw);
7559 }
7560
7561 int
7562 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7563 {
7564         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7565         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7566         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7567                            I40E_VFQF_HKEY_MAX_INDEX :
7568                            I40E_PFQF_HKEY_MAX_INDEX;
7569
7570         if (!key || key_len == 0) {
7571                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7572                 return 0;
7573         } else if (key_len != (key_idx + 1) *
7574                 sizeof(uint32_t)) {
7575                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7576                 return -EINVAL;
7577         }
7578
7579         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7580                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7581                                 (struct i40e_aqc_get_set_rss_key_data *)key;
7582                 enum i40e_status_code status =
7583                                 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7584
7585                 if (status) {
7586                         PMD_DRV_LOG(ERR,
7587                                     "Failed to configure RSS key via AQ, error status: %d",
7588                                     status);
7589                         return -EIO;
7590                 }
7591         } else {
7592                 uint32_t *hash_key = (uint32_t *)key;
7593                 uint16_t i;
7594
7595                 if (vsi->type == I40E_VSI_SRIOV) {
7596                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7597                                 I40E_WRITE_REG(
7598                                         hw,
7599                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7600                                         hash_key[i]);
7601
7602                 } else {
7603                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7604                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7605                                                hash_key[i]);
7606                 }
7607                 I40E_WRITE_FLUSH(hw);
7608         }
7609
7610         return 0;
7611 }
7612
7613 static int
7614 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7615 {
7616         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7617         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7618         uint32_t reg;
7619         int ret;
7620
7621         if (!key || !key_len)
7622                 return 0;
7623
7624         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7625                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7626                         (struct i40e_aqc_get_set_rss_key_data *)key);
7627                 if (ret) {
7628                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7629                         return ret;
7630                 }
7631         } else {
7632                 uint32_t *key_dw = (uint32_t *)key;
7633                 uint16_t i;
7634
7635                 if (vsi->type == I40E_VSI_SRIOV) {
7636                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7637                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7638                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7639                         }
7640                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7641                                    sizeof(uint32_t);
7642                 } else {
7643                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7644                                 reg = I40E_PFQF_HKEY(i);
7645                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7646                         }
7647                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7648                                    sizeof(uint32_t);
7649                 }
7650         }
7651         return 0;
7652 }
7653
7654 static int
7655 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7656 {
7657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7658         uint64_t hena;
7659         int ret;
7660
7661         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7662                                rss_conf->rss_key_len);
7663         if (ret)
7664                 return ret;
7665
7666         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7667         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7668         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7669         I40E_WRITE_FLUSH(hw);
7670
7671         return 0;
7672 }
7673
7674 static int
7675 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7676                          struct rte_eth_rss_conf *rss_conf)
7677 {
7678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7681         uint64_t hena;
7682
7683         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7684         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7685
7686         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7687                 if (rss_hf != 0) /* Enable RSS */
7688                         return -EINVAL;
7689                 return 0; /* Nothing to do */
7690         }
7691         /* RSS enabled */
7692         if (rss_hf == 0) /* Disable RSS */
7693                 return -EINVAL;
7694
7695         return i40e_hw_rss_hash_set(pf, rss_conf);
7696 }
7697
7698 static int
7699 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7700                            struct rte_eth_rss_conf *rss_conf)
7701 {
7702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7704         uint64_t hena;
7705         int ret;
7706
7707         if (!rss_conf)
7708                 return -EINVAL;
7709
7710         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7711                          &rss_conf->rss_key_len);
7712         if (ret)
7713                 return ret;
7714
7715         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7716         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7717         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7718
7719         return 0;
7720 }
7721
7722 static int
7723 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7724 {
7725         switch (filter_type) {
7726         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7727                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7728                 break;
7729         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7730                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7731                 break;
7732         case RTE_TUNNEL_FILTER_IMAC_TENID:
7733                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7734                 break;
7735         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7736                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7737                 break;
7738         case ETH_TUNNEL_FILTER_IMAC:
7739                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7740                 break;
7741         case ETH_TUNNEL_FILTER_OIP:
7742                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7743                 break;
7744         case ETH_TUNNEL_FILTER_IIP:
7745                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7746                 break;
7747         default:
7748                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7749                 return -EINVAL;
7750         }
7751
7752         return 0;
7753 }
7754
7755 /* Convert tunnel filter structure */
7756 static int
7757 i40e_tunnel_filter_convert(
7758         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7759         struct i40e_tunnel_filter *tunnel_filter)
7760 {
7761         rte_ether_addr_copy((struct rte_ether_addr *)
7762                         &cld_filter->element.outer_mac,
7763                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7764         rte_ether_addr_copy((struct rte_ether_addr *)
7765                         &cld_filter->element.inner_mac,
7766                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7767         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7768         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7769              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7770             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7771                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7772         else
7773                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7774         tunnel_filter->input.flags = cld_filter->element.flags;
7775         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7776         tunnel_filter->queue = cld_filter->element.queue_number;
7777         rte_memcpy(tunnel_filter->input.general_fields,
7778                    cld_filter->general_fields,
7779                    sizeof(cld_filter->general_fields));
7780
7781         return 0;
7782 }
7783
7784 /* Check if there exists the tunnel filter */
7785 struct i40e_tunnel_filter *
7786 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7787                              const struct i40e_tunnel_filter_input *input)
7788 {
7789         int ret;
7790
7791         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7792         if (ret < 0)
7793                 return NULL;
7794
7795         return tunnel_rule->hash_map[ret];
7796 }
7797
7798 /* Add a tunnel filter into the SW list */
7799 static int
7800 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7801                              struct i40e_tunnel_filter *tunnel_filter)
7802 {
7803         struct i40e_tunnel_rule *rule = &pf->tunnel;
7804         int ret;
7805
7806         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7807         if (ret < 0) {
7808                 PMD_DRV_LOG(ERR,
7809                             "Failed to insert tunnel filter to hash table %d!",
7810                             ret);
7811                 return ret;
7812         }
7813         rule->hash_map[ret] = tunnel_filter;
7814
7815         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7816
7817         return 0;
7818 }
7819
7820 /* Delete a tunnel filter from the SW list */
7821 int
7822 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7823                           struct i40e_tunnel_filter_input *input)
7824 {
7825         struct i40e_tunnel_rule *rule = &pf->tunnel;
7826         struct i40e_tunnel_filter *tunnel_filter;
7827         int ret;
7828
7829         ret = rte_hash_del_key(rule->hash_table, input);
7830         if (ret < 0) {
7831                 PMD_DRV_LOG(ERR,
7832                             "Failed to delete tunnel filter to hash table %d!",
7833                             ret);
7834                 return ret;
7835         }
7836         tunnel_filter = rule->hash_map[ret];
7837         rule->hash_map[ret] = NULL;
7838
7839         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7840         rte_free(tunnel_filter);
7841
7842         return 0;
7843 }
7844
7845 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7846 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7847 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7848 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7849 #define I40E_TR_GRE_KEY_MASK                    0x400
7850 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7851 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7852 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7853 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7854 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7855 #define I40E_DIRECTION_INGRESS_KEY              0x8000
7856 #define I40E_TR_L4_TYPE_TCP                     0x2
7857 #define I40E_TR_L4_TYPE_UDP                     0x4
7858 #define I40E_TR_L4_TYPE_SCTP                    0x8
7859
7860 static enum
7861 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7862 {
7863         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7864         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7866         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7867         enum i40e_status_code status = I40E_SUCCESS;
7868
7869         if (pf->support_multi_driver) {
7870                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7871                 return I40E_NOT_SUPPORTED;
7872         }
7873
7874         memset(&filter_replace, 0,
7875                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7876         memset(&filter_replace_buf, 0,
7877                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7878
7879         /* create L1 filter */
7880         filter_replace.old_filter_type =
7881                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7882         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7883         filter_replace.tr_bit = 0;
7884
7885         /* Prepare the buffer, 3 entries */
7886         filter_replace_buf.data[0] =
7887                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7888         filter_replace_buf.data[0] |=
7889                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7890         filter_replace_buf.data[2] = 0xFF;
7891         filter_replace_buf.data[3] = 0xFF;
7892         filter_replace_buf.data[4] =
7893                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7894         filter_replace_buf.data[4] |=
7895                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7896         filter_replace_buf.data[7] = 0xF0;
7897         filter_replace_buf.data[8]
7898                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7899         filter_replace_buf.data[8] |=
7900                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7901         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7902                 I40E_TR_GENEVE_KEY_MASK |
7903                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7904         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7905                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7906                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7907
7908         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7909                                                &filter_replace_buf);
7910         if (!status && (filter_replace.old_filter_type !=
7911                         filter_replace.new_filter_type))
7912                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7913                             " original: 0x%x, new: 0x%x",
7914                             dev->device->name,
7915                             filter_replace.old_filter_type,
7916                             filter_replace.new_filter_type);
7917
7918         return status;
7919 }
7920
7921 static enum
7922 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7923 {
7924         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7925         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7926         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7927         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7928         enum i40e_status_code status = I40E_SUCCESS;
7929
7930         if (pf->support_multi_driver) {
7931                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7932                 return I40E_NOT_SUPPORTED;
7933         }
7934
7935         /* For MPLSoUDP */
7936         memset(&filter_replace, 0,
7937                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7938         memset(&filter_replace_buf, 0,
7939                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7940         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7941                 I40E_AQC_MIRROR_CLOUD_FILTER;
7942         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7943         filter_replace.new_filter_type =
7944                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7945         /* Prepare the buffer, 2 entries */
7946         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7947         filter_replace_buf.data[0] |=
7948                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7949         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7950         filter_replace_buf.data[4] |=
7951                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7952         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7953                                                &filter_replace_buf);
7954         if (status < 0)
7955                 return status;
7956         if (filter_replace.old_filter_type !=
7957             filter_replace.new_filter_type)
7958                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7959                             " original: 0x%x, new: 0x%x",
7960                             dev->device->name,
7961                             filter_replace.old_filter_type,
7962                             filter_replace.new_filter_type);
7963
7964         /* For MPLSoGRE */
7965         memset(&filter_replace, 0,
7966                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7967         memset(&filter_replace_buf, 0,
7968                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7969
7970         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7971                 I40E_AQC_MIRROR_CLOUD_FILTER;
7972         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7973         filter_replace.new_filter_type =
7974                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7975         /* Prepare the buffer, 2 entries */
7976         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7977         filter_replace_buf.data[0] |=
7978                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7979         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7980         filter_replace_buf.data[4] |=
7981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7982
7983         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7984                                                &filter_replace_buf);
7985         if (!status && (filter_replace.old_filter_type !=
7986                         filter_replace.new_filter_type))
7987                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7988                             " original: 0x%x, new: 0x%x",
7989                             dev->device->name,
7990                             filter_replace.old_filter_type,
7991                             filter_replace.new_filter_type);
7992
7993         return status;
7994 }
7995
7996 static enum i40e_status_code
7997 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7998 {
7999         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8000         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8001         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8002         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8003         enum i40e_status_code status = I40E_SUCCESS;
8004
8005         if (pf->support_multi_driver) {
8006                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8007                 return I40E_NOT_SUPPORTED;
8008         }
8009
8010         /* For GTP-C */
8011         memset(&filter_replace, 0,
8012                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8013         memset(&filter_replace_buf, 0,
8014                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8015         /* create L1 filter */
8016         filter_replace.old_filter_type =
8017                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8018         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8019         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8020                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8021         /* Prepare the buffer, 2 entries */
8022         filter_replace_buf.data[0] =
8023                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8024         filter_replace_buf.data[0] |=
8025                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8026         filter_replace_buf.data[2] = 0xFF;
8027         filter_replace_buf.data[3] = 0xFF;
8028         filter_replace_buf.data[4] =
8029                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8030         filter_replace_buf.data[4] |=
8031                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8032         filter_replace_buf.data[6] = 0xFF;
8033         filter_replace_buf.data[7] = 0xFF;
8034         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8035                                                &filter_replace_buf);
8036         if (status < 0)
8037                 return status;
8038         if (filter_replace.old_filter_type !=
8039             filter_replace.new_filter_type)
8040                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8041                             " original: 0x%x, new: 0x%x",
8042                             dev->device->name,
8043                             filter_replace.old_filter_type,
8044                             filter_replace.new_filter_type);
8045
8046         /* for GTP-U */
8047         memset(&filter_replace, 0,
8048                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8049         memset(&filter_replace_buf, 0,
8050                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8051         /* create L1 filter */
8052         filter_replace.old_filter_type =
8053                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8054         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8055         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8056                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8057         /* Prepare the buffer, 2 entries */
8058         filter_replace_buf.data[0] =
8059                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8060         filter_replace_buf.data[0] |=
8061                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8062         filter_replace_buf.data[2] = 0xFF;
8063         filter_replace_buf.data[3] = 0xFF;
8064         filter_replace_buf.data[4] =
8065                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8066         filter_replace_buf.data[4] |=
8067                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8068         filter_replace_buf.data[6] = 0xFF;
8069         filter_replace_buf.data[7] = 0xFF;
8070
8071         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8072                                                &filter_replace_buf);
8073         if (!status && (filter_replace.old_filter_type !=
8074                         filter_replace.new_filter_type))
8075                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8076                             " original: 0x%x, new: 0x%x",
8077                             dev->device->name,
8078                             filter_replace.old_filter_type,
8079                             filter_replace.new_filter_type);
8080
8081         return status;
8082 }
8083
8084 static enum
8085 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8086 {
8087         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8088         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8089         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8090         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8091         enum i40e_status_code status = I40E_SUCCESS;
8092
8093         if (pf->support_multi_driver) {
8094                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8095                 return I40E_NOT_SUPPORTED;
8096         }
8097
8098         /* for GTP-C */
8099         memset(&filter_replace, 0,
8100                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8101         memset(&filter_replace_buf, 0,
8102                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8103         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8104         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8105         filter_replace.new_filter_type =
8106                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8107         /* Prepare the buffer, 2 entries */
8108         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8109         filter_replace_buf.data[0] |=
8110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8111         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8112         filter_replace_buf.data[4] |=
8113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8115                                                &filter_replace_buf);
8116         if (status < 0)
8117                 return status;
8118         if (filter_replace.old_filter_type !=
8119             filter_replace.new_filter_type)
8120                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8121                             " original: 0x%x, new: 0x%x",
8122                             dev->device->name,
8123                             filter_replace.old_filter_type,
8124                             filter_replace.new_filter_type);
8125
8126         /* for GTP-U */
8127         memset(&filter_replace, 0,
8128                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8129         memset(&filter_replace_buf, 0,
8130                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8131         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8132         filter_replace.old_filter_type =
8133                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8134         filter_replace.new_filter_type =
8135                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8136         /* Prepare the buffer, 2 entries */
8137         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8138         filter_replace_buf.data[0] |=
8139                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8140         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8141         filter_replace_buf.data[4] |=
8142                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8143
8144         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8145                                                &filter_replace_buf);
8146         if (!status && (filter_replace.old_filter_type !=
8147                         filter_replace.new_filter_type))
8148                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8149                             " original: 0x%x, new: 0x%x",
8150                             dev->device->name,
8151                             filter_replace.old_filter_type,
8152                             filter_replace.new_filter_type);
8153
8154         return status;
8155 }
8156
8157 static enum i40e_status_code
8158 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8159                             enum i40e_l4_port_type l4_port_type)
8160 {
8161         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8162         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8163         enum i40e_status_code status = I40E_SUCCESS;
8164         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8165         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8166
8167         if (pf->support_multi_driver) {
8168                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8169                 return I40E_NOT_SUPPORTED;
8170         }
8171
8172         memset(&filter_replace, 0,
8173                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8174         memset(&filter_replace_buf, 0,
8175                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8176
8177         /* create L1 filter */
8178         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8179                 filter_replace.old_filter_type =
8180                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8181                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8182                 filter_replace_buf.data[8] =
8183                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8184         } else {
8185                 filter_replace.old_filter_type =
8186                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8187                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8188                 filter_replace_buf.data[8] =
8189                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8190         }
8191
8192         filter_replace.tr_bit = 0;
8193         /* Prepare the buffer, 3 entries */
8194         filter_replace_buf.data[0] =
8195                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8196         filter_replace_buf.data[0] |=
8197                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8198         filter_replace_buf.data[2] = 0x00;
8199         filter_replace_buf.data[3] =
8200                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8201         filter_replace_buf.data[4] =
8202                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8203         filter_replace_buf.data[4] |=
8204                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8205         filter_replace_buf.data[5] = 0x00;
8206         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8207                 I40E_TR_L4_TYPE_TCP |
8208                 I40E_TR_L4_TYPE_SCTP;
8209         filter_replace_buf.data[7] = 0x00;
8210         filter_replace_buf.data[8] |=
8211                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8212         filter_replace_buf.data[9] = 0x00;
8213         filter_replace_buf.data[10] = 0xFF;
8214         filter_replace_buf.data[11] = 0xFF;
8215
8216         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8217                                                &filter_replace_buf);
8218         if (!status && filter_replace.old_filter_type !=
8219             filter_replace.new_filter_type)
8220                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8221                             " original: 0x%x, new: 0x%x",
8222                             dev->device->name,
8223                             filter_replace.old_filter_type,
8224                             filter_replace.new_filter_type);
8225
8226         return status;
8227 }
8228
8229 static enum i40e_status_code
8230 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8231                                enum i40e_l4_port_type l4_port_type)
8232 {
8233         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8234         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8235         enum i40e_status_code status = I40E_SUCCESS;
8236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8237         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8238
8239         if (pf->support_multi_driver) {
8240                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8241                 return I40E_NOT_SUPPORTED;
8242         }
8243
8244         memset(&filter_replace, 0,
8245                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8246         memset(&filter_replace_buf, 0,
8247                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8248
8249         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8250                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8251                 filter_replace.new_filter_type =
8252                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8253                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8254         } else {
8255                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8256                 filter_replace.new_filter_type =
8257                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8258                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8259         }
8260
8261         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8262         filter_replace.tr_bit = 0;
8263         /* Prepare the buffer, 2 entries */
8264         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8265         filter_replace_buf.data[0] |=
8266                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8267         filter_replace_buf.data[4] |=
8268                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8269         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8270                                                &filter_replace_buf);
8271
8272         if (!status && filter_replace.old_filter_type !=
8273             filter_replace.new_filter_type)
8274                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8275                             " original: 0x%x, new: 0x%x",
8276                             dev->device->name,
8277                             filter_replace.old_filter_type,
8278                             filter_replace.new_filter_type);
8279
8280         return status;
8281 }
8282
8283 int
8284 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8285                       struct i40e_tunnel_filter_conf *tunnel_filter,
8286                       uint8_t add)
8287 {
8288         uint16_t ip_type;
8289         uint32_t ipv4_addr, ipv4_addr_le;
8290         uint8_t i, tun_type = 0;
8291         /* internal variable to convert ipv6 byte order */
8292         uint32_t convert_ipv6[4];
8293         int val, ret = 0;
8294         struct i40e_pf_vf *vf = NULL;
8295         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8296         struct i40e_vsi *vsi;
8297         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8298         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8299         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8300         struct i40e_tunnel_filter *tunnel, *node;
8301         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8302         uint32_t teid_le;
8303         bool big_buffer = 0;
8304
8305         cld_filter = rte_zmalloc("tunnel_filter",
8306                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8307                          0);
8308
8309         if (cld_filter == NULL) {
8310                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8311                 return -ENOMEM;
8312         }
8313         pfilter = cld_filter;
8314
8315         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8316                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8317         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8318                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8319
8320         pfilter->element.inner_vlan =
8321                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8322         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8323                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8324                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8325                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8326                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8327                                 &ipv4_addr_le,
8328                                 sizeof(pfilter->element.ipaddr.v4.data));
8329         } else {
8330                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8331                 for (i = 0; i < 4; i++) {
8332                         convert_ipv6[i] =
8333                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8334                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8335                 }
8336                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8337                            &convert_ipv6,
8338                            sizeof(pfilter->element.ipaddr.v6.data));
8339         }
8340
8341         /* check tunneled type */
8342         switch (tunnel_filter->tunnel_type) {
8343         case I40E_TUNNEL_TYPE_VXLAN:
8344                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8345                 break;
8346         case I40E_TUNNEL_TYPE_NVGRE:
8347                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8348                 break;
8349         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8350                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8351                 break;
8352         case I40E_TUNNEL_TYPE_MPLSoUDP:
8353                 if (!pf->mpls_replace_flag) {
8354                         i40e_replace_mpls_l1_filter(pf);
8355                         i40e_replace_mpls_cloud_filter(pf);
8356                         pf->mpls_replace_flag = 1;
8357                 }
8358                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8359                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8360                         teid_le >> 4;
8361                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8362                         (teid_le & 0xF) << 12;
8363                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8364                         0x40;
8365                 big_buffer = 1;
8366                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8367                 break;
8368         case I40E_TUNNEL_TYPE_MPLSoGRE:
8369                 if (!pf->mpls_replace_flag) {
8370                         i40e_replace_mpls_l1_filter(pf);
8371                         i40e_replace_mpls_cloud_filter(pf);
8372                         pf->mpls_replace_flag = 1;
8373                 }
8374                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8375                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8376                         teid_le >> 4;
8377                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8378                         (teid_le & 0xF) << 12;
8379                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8380                         0x0;
8381                 big_buffer = 1;
8382                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8383                 break;
8384         case I40E_TUNNEL_TYPE_GTPC:
8385                 if (!pf->gtp_replace_flag) {
8386                         i40e_replace_gtp_l1_filter(pf);
8387                         i40e_replace_gtp_cloud_filter(pf);
8388                         pf->gtp_replace_flag = 1;
8389                 }
8390                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8391                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8392                         (teid_le >> 16) & 0xFFFF;
8393                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8394                         teid_le & 0xFFFF;
8395                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8396                         0x0;
8397                 big_buffer = 1;
8398                 break;
8399         case I40E_TUNNEL_TYPE_GTPU:
8400                 if (!pf->gtp_replace_flag) {
8401                         i40e_replace_gtp_l1_filter(pf);
8402                         i40e_replace_gtp_cloud_filter(pf);
8403                         pf->gtp_replace_flag = 1;
8404                 }
8405                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8406                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8407                         (teid_le >> 16) & 0xFFFF;
8408                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8409                         teid_le & 0xFFFF;
8410                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8411                         0x0;
8412                 big_buffer = 1;
8413                 break;
8414         case I40E_TUNNEL_TYPE_QINQ:
8415                 if (!pf->qinq_replace_flag) {
8416                         ret = i40e_cloud_filter_qinq_create(pf);
8417                         if (ret < 0)
8418                                 PMD_DRV_LOG(DEBUG,
8419                                             "QinQ tunnel filter already created.");
8420                         pf->qinq_replace_flag = 1;
8421                 }
8422                 /*      Add in the General fields the values of
8423                  *      the Outer and Inner VLAN
8424                  *      Big Buffer should be set, see changes in
8425                  *      i40e_aq_add_cloud_filters
8426                  */
8427                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8428                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8429                 big_buffer = 1;
8430                 break;
8431         case I40E_CLOUD_TYPE_UDP:
8432         case I40E_CLOUD_TYPE_TCP:
8433         case I40E_CLOUD_TYPE_SCTP:
8434                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8435                         if (!pf->sport_replace_flag) {
8436                                 i40e_replace_port_l1_filter(pf,
8437                                                 tunnel_filter->l4_port_type);
8438                                 i40e_replace_port_cloud_filter(pf,
8439                                                 tunnel_filter->l4_port_type);
8440                                 pf->sport_replace_flag = 1;
8441                         }
8442                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8443                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8444                                 I40E_DIRECTION_INGRESS_KEY;
8445
8446                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8447                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8448                                         I40E_TR_L4_TYPE_UDP;
8449                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8450                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8451                                         I40E_TR_L4_TYPE_TCP;
8452                         else
8453                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8454                                         I40E_TR_L4_TYPE_SCTP;
8455
8456                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8457                                 (teid_le >> 16) & 0xFFFF;
8458                         big_buffer = 1;
8459                 } else {
8460                         if (!pf->dport_replace_flag) {
8461                                 i40e_replace_port_l1_filter(pf,
8462                                                 tunnel_filter->l4_port_type);
8463                                 i40e_replace_port_cloud_filter(pf,
8464                                                 tunnel_filter->l4_port_type);
8465                                 pf->dport_replace_flag = 1;
8466                         }
8467                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8468                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8469                                 I40E_DIRECTION_INGRESS_KEY;
8470
8471                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8472                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8473                                         I40E_TR_L4_TYPE_UDP;
8474                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8475                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8476                                         I40E_TR_L4_TYPE_TCP;
8477                         else
8478                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8479                                         I40E_TR_L4_TYPE_SCTP;
8480
8481                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8482                                 (teid_le >> 16) & 0xFFFF;
8483                         big_buffer = 1;
8484                 }
8485
8486                 break;
8487         default:
8488                 /* Other tunnel types is not supported. */
8489                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8490                 rte_free(cld_filter);
8491                 return -EINVAL;
8492         }
8493
8494         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8495                 pfilter->element.flags =
8496                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8497         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8498                 pfilter->element.flags =
8499                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8500         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8501                 pfilter->element.flags =
8502                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8503         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8504                 pfilter->element.flags =
8505                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8506         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8507                 pfilter->element.flags |=
8508                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8509         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8510                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8511                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8512                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8513                         pfilter->element.flags |=
8514                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8515                 else
8516                         pfilter->element.flags |=
8517                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8518         } else {
8519                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8520                                                 &pfilter->element.flags);
8521                 if (val < 0) {
8522                         rte_free(cld_filter);
8523                         return -EINVAL;
8524                 }
8525         }
8526
8527         pfilter->element.flags |= rte_cpu_to_le_16(
8528                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8529                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8530         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8531         pfilter->element.queue_number =
8532                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8533
8534         if (!tunnel_filter->is_to_vf)
8535                 vsi = pf->main_vsi;
8536         else {
8537                 if (tunnel_filter->vf_id >= pf->vf_num) {
8538                         PMD_DRV_LOG(ERR, "Invalid argument.");
8539                         rte_free(cld_filter);
8540                         return -EINVAL;
8541                 }
8542                 vf = &pf->vfs[tunnel_filter->vf_id];
8543                 vsi = vf->vsi;
8544         }
8545
8546         /* Check if there is the filter in SW list */
8547         memset(&check_filter, 0, sizeof(check_filter));
8548         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8549         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8550         check_filter.vf_id = tunnel_filter->vf_id;
8551         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8552         if (add && node) {
8553                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8554                 rte_free(cld_filter);
8555                 return -EINVAL;
8556         }
8557
8558         if (!add && !node) {
8559                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8560                 rte_free(cld_filter);
8561                 return -EINVAL;
8562         }
8563
8564         if (add) {
8565                 if (big_buffer)
8566                         ret = i40e_aq_add_cloud_filters_bb(hw,
8567                                                    vsi->seid, cld_filter, 1);
8568                 else
8569                         ret = i40e_aq_add_cloud_filters(hw,
8570                                         vsi->seid, &cld_filter->element, 1);
8571                 if (ret < 0) {
8572                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8573                         rte_free(cld_filter);
8574                         return -ENOTSUP;
8575                 }
8576                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8577                 if (tunnel == NULL) {
8578                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8579                         rte_free(cld_filter);
8580                         return -ENOMEM;
8581                 }
8582
8583                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8584                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8585                 if (ret < 0)
8586                         rte_free(tunnel);
8587         } else {
8588                 if (big_buffer)
8589                         ret = i40e_aq_rem_cloud_filters_bb(
8590                                 hw, vsi->seid, cld_filter, 1);
8591                 else
8592                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8593                                                 &cld_filter->element, 1);
8594                 if (ret < 0) {
8595                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8596                         rte_free(cld_filter);
8597                         return -ENOTSUP;
8598                 }
8599                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8600         }
8601
8602         rte_free(cld_filter);
8603         return ret;
8604 }
8605
8606 static int
8607 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8608 {
8609         uint8_t i;
8610
8611         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8612                 if (pf->vxlan_ports[i] == port)
8613                         return i;
8614         }
8615
8616         return -1;
8617 }
8618
8619 static int
8620 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8621 {
8622         int  idx, ret;
8623         uint8_t filter_idx = 0;
8624         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8625
8626         idx = i40e_get_vxlan_port_idx(pf, port);
8627
8628         /* Check if port already exists */
8629         if (idx >= 0) {
8630                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8631                 return -EINVAL;
8632         }
8633
8634         /* Now check if there is space to add the new port */
8635         idx = i40e_get_vxlan_port_idx(pf, 0);
8636         if (idx < 0) {
8637                 PMD_DRV_LOG(ERR,
8638                         "Maximum number of UDP ports reached, not adding port %d",
8639                         port);
8640                 return -ENOSPC;
8641         }
8642
8643         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8644                                         &filter_idx, NULL);
8645         if (ret < 0) {
8646                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8647                 return -1;
8648         }
8649
8650         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8651                          port,  filter_idx);
8652
8653         /* New port: add it and mark its index in the bitmap */
8654         pf->vxlan_ports[idx] = port;
8655         pf->vxlan_bitmap |= (1 << idx);
8656
8657         if (!(pf->flags & I40E_FLAG_VXLAN))
8658                 pf->flags |= I40E_FLAG_VXLAN;
8659
8660         return 0;
8661 }
8662
8663 static int
8664 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8665 {
8666         int idx;
8667         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8668
8669         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8670                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8671                 return -EINVAL;
8672         }
8673
8674         idx = i40e_get_vxlan_port_idx(pf, port);
8675
8676         if (idx < 0) {
8677                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8678                 return -EINVAL;
8679         }
8680
8681         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8682                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8683                 return -1;
8684         }
8685
8686         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8687                         port, idx);
8688
8689         pf->vxlan_ports[idx] = 0;
8690         pf->vxlan_bitmap &= ~(1 << idx);
8691
8692         if (!pf->vxlan_bitmap)
8693                 pf->flags &= ~I40E_FLAG_VXLAN;
8694
8695         return 0;
8696 }
8697
8698 /* Add UDP tunneling port */
8699 static int
8700 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8701                              struct rte_eth_udp_tunnel *udp_tunnel)
8702 {
8703         int ret = 0;
8704         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8705
8706         if (udp_tunnel == NULL)
8707                 return -EINVAL;
8708
8709         switch (udp_tunnel->prot_type) {
8710         case RTE_TUNNEL_TYPE_VXLAN:
8711                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8712                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8713                 break;
8714         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8715                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8716                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8717                 break;
8718         case RTE_TUNNEL_TYPE_GENEVE:
8719         case RTE_TUNNEL_TYPE_TEREDO:
8720                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8721                 ret = -1;
8722                 break;
8723
8724         default:
8725                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8726                 ret = -1;
8727                 break;
8728         }
8729
8730         return ret;
8731 }
8732
8733 /* Remove UDP tunneling port */
8734 static int
8735 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8736                              struct rte_eth_udp_tunnel *udp_tunnel)
8737 {
8738         int ret = 0;
8739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8740
8741         if (udp_tunnel == NULL)
8742                 return -EINVAL;
8743
8744         switch (udp_tunnel->prot_type) {
8745         case RTE_TUNNEL_TYPE_VXLAN:
8746         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8747                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8748                 break;
8749         case RTE_TUNNEL_TYPE_GENEVE:
8750         case RTE_TUNNEL_TYPE_TEREDO:
8751                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8752                 ret = -1;
8753                 break;
8754         default:
8755                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8756                 ret = -1;
8757                 break;
8758         }
8759
8760         return ret;
8761 }
8762
8763 /* Calculate the maximum number of contiguous PF queues that are configured */
8764 int
8765 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8766 {
8767         struct rte_eth_dev_data *data = pf->dev_data;
8768         int i, num;
8769         struct i40e_rx_queue *rxq;
8770
8771         num = 0;
8772         for (i = 0; i < pf->lan_nb_qps; i++) {
8773                 rxq = data->rx_queues[i];
8774                 if (rxq && rxq->q_set)
8775                         num++;
8776                 else
8777                         break;
8778         }
8779
8780         return num;
8781 }
8782
8783 /* Reset the global configure of hash function and input sets */
8784 static void
8785 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8786 {
8787         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8788         uint32_t reg, reg_val;
8789         int i;
8790
8791         /* Reset global RSS function sets */
8792         reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8793         if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8794                 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8795                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8796         }
8797
8798         for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8799                 uint64_t inset;
8800                 int j, pctype;
8801
8802                 if (hw->mac.type == I40E_MAC_X722)
8803                         pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8804                 else
8805                         pctype = i;
8806
8807                 /* Reset pctype insets */
8808                 inset = i40e_get_default_input_set(i);
8809                 if (inset) {
8810                         pf->hash_input_set[pctype] = inset;
8811                         inset = i40e_translate_input_set_reg(hw->mac.type,
8812                                                              inset);
8813
8814                         reg = I40E_GLQF_HASH_INSET(0, pctype);
8815                         i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8816                         reg = I40E_GLQF_HASH_INSET(1, pctype);
8817                         i40e_check_write_global_reg(hw, reg,
8818                                                     (uint32_t)(inset >> 32));
8819
8820                         /* Clear unused mask registers of the pctype */
8821                         for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8822                                 reg = I40E_GLQF_HASH_MSK(j, pctype);
8823                                 i40e_check_write_global_reg(hw, reg, 0);
8824                         }
8825                 }
8826
8827                 /* Reset pctype symmetric sets */
8828                 reg = I40E_GLQF_HSYM(pctype);
8829                 reg_val = i40e_read_rx_ctl(hw, reg);
8830                 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8831                         reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8832                         i40e_write_global_rx_ctl(hw, reg, reg_val);
8833                 }
8834         }
8835         I40E_WRITE_FLUSH(hw);
8836 }
8837
8838 int
8839 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8840 {
8841         struct i40e_hw *hw = &pf->adapter->hw;
8842         uint8_t lut[ETH_RSS_RETA_SIZE_512];
8843         uint32_t i;
8844         int num;
8845
8846         /* If both VMDQ and RSS enabled, not all of PF queues are
8847          * configured. It's necessary to calculate the actual PF
8848          * queues that are configured.
8849          */
8850         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8851                 num = i40e_pf_calc_configured_queues_num(pf);
8852         else
8853                 num = pf->dev_data->nb_rx_queues;
8854
8855         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8856         if (num <= 0)
8857                 return 0;
8858
8859         for (i = 0; i < hw->func_caps.rss_table_size; i++)
8860                 lut[i] = (uint8_t)(i % (uint32_t)num);
8861
8862         return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8863 }
8864
8865 int
8866 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8867 {
8868         const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8869                         sizeof(uint32_t);
8870         uint8_t *rss_key;
8871
8872         /* Reset key */
8873         rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8874         if (!rss_key ||
8875             pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8876                 static uint32_t rss_key_default[] = {0x6b793944,
8877                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8878                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8879                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8880
8881                 rss_key = (uint8_t *)rss_key_default;
8882         }
8883
8884         return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8885 }
8886
8887 static int
8888 i40e_pf_rss_reset(struct i40e_pf *pf)
8889 {
8890         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8891
8892         int ret;
8893
8894         pf->hash_filter_enabled = 0;
8895         i40e_pf_disable_rss(pf);
8896         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8897
8898         if (!pf->support_multi_driver)
8899                 i40e_pf_global_rss_reset(pf);
8900
8901         /* Reset RETA table */
8902         if (pf->adapter->rss_reta_updated == 0) {
8903                 ret = i40e_pf_reset_rss_reta(pf);
8904                 if (ret)
8905                         return ret;
8906         }
8907
8908         return i40e_pf_reset_rss_key(pf);
8909 }
8910
8911 /* Configure RSS */
8912 int
8913 i40e_pf_config_rss(struct i40e_pf *pf)
8914 {
8915         struct i40e_hw *hw;
8916         enum rte_eth_rx_mq_mode mq_mode;
8917         uint64_t rss_hf, hena;
8918         int ret;
8919
8920         ret = i40e_pf_rss_reset(pf);
8921         if (ret) {
8922                 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8923                 return ret;
8924         }
8925
8926         rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8927         mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8928         if (!(rss_hf & pf->adapter->flow_types_mask) ||
8929             !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8930                 return 0;
8931
8932         hw = I40E_PF_TO_HW(pf);
8933         hena = i40e_config_hena(pf->adapter, rss_hf);
8934         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8935         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8936         I40E_WRITE_FLUSH(hw);
8937
8938         return 0;
8939 }
8940
8941 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8942 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8943 int
8944 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8945 {
8946         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8947         uint32_t val, reg;
8948         int ret = -EINVAL;
8949
8950         if (pf->support_multi_driver) {
8951                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8952                 return -ENOTSUP;
8953         }
8954
8955         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8956         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8957
8958         if (len == 3) {
8959                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8960         } else if (len == 4) {
8961                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8962         } else {
8963                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8964                 return ret;
8965         }
8966
8967         if (reg != val) {
8968                 ret = i40e_aq_debug_write_global_register(hw,
8969                                                    I40E_GL_PRS_FVBM(2),
8970                                                    reg, NULL);
8971                 if (ret != 0)
8972                         return ret;
8973                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8974                             "with value 0x%08x",
8975                             I40E_GL_PRS_FVBM(2), reg);
8976         } else {
8977                 ret = 0;
8978         }
8979         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8980                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8981
8982         return ret;
8983 }
8984
8985 /* Set the symmetric hash enable configurations per port */
8986 void
8987 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8988 {
8989         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8990
8991         if (enable > 0) {
8992                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
8993                         return;
8994
8995                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8996         } else {
8997                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
8998                         return;
8999
9000                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9001         }
9002         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9003         I40E_WRITE_FLUSH(hw);
9004 }
9005
9006 /**
9007  * Valid input sets for hash and flow director filters per PCTYPE
9008  */
9009 static uint64_t
9010 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9011                 enum rte_filter_type filter)
9012 {
9013         uint64_t valid;
9014
9015         static const uint64_t valid_hash_inset_table[] = {
9016                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9017                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9018                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9019                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9020                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9021                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9022                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9023                         I40E_INSET_FLEX_PAYLOAD,
9024                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9025                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9026                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9027                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9028                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9029                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9030                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9031                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9032                         I40E_INSET_FLEX_PAYLOAD,
9033                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9034                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9035                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9036                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9037                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9038                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9039                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9040                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9041                         I40E_INSET_FLEX_PAYLOAD,
9042                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9043                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9044                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9045                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9046                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9047                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9048                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9049                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9050                         I40E_INSET_FLEX_PAYLOAD,
9051                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9052                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9053                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9055                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9056                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9057                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9058                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9059                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9060                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9061                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9062                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9063                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9064                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9065                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9066                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9067                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9068                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9069                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9070                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9071                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9072                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9073                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9074                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9075                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9076                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9077                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9078                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9079                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9080                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9081                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9082                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9083                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9084                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9085                         I40E_INSET_FLEX_PAYLOAD,
9086                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9087                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9088                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9089                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9090                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9091                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9092                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9093                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9094                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9095                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9096                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9097                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9098                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9099                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9100                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9101                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9102                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9103                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9104                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9105                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9106                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9107                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9108                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9109                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9110                         I40E_INSET_FLEX_PAYLOAD,
9111                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9115                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9116                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9117                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9118                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9119                         I40E_INSET_FLEX_PAYLOAD,
9120                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9121                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9122                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9123                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9124                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9125                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9126                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9127                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9128                         I40E_INSET_FLEX_PAYLOAD,
9129                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9130                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9131                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9132                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9133                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9134                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9135                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9136                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9137                         I40E_INSET_FLEX_PAYLOAD,
9138                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9139                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9140                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9141                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9142                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9143                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9144                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9145                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9146                         I40E_INSET_FLEX_PAYLOAD,
9147                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9148                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9149                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9151                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9152                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9153                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9154                         I40E_INSET_FLEX_PAYLOAD,
9155                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9156                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9157                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9158                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9159                         I40E_INSET_FLEX_PAYLOAD,
9160         };
9161
9162         /**
9163          * Flow director supports only fields defined in
9164          * union rte_eth_fdir_flow.
9165          */
9166         static const uint64_t valid_fdir_inset_table[] = {
9167                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9169                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9170                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9171                 I40E_INSET_IPV4_TTL,
9172                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9173                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9174                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9175                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9176                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9177                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9178                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9179                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9180                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9181                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9182                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9183                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9184                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9185                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9186                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9187                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9188                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9189                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9190                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9192                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9193                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9195                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9197                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9198                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9199                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9200                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9201                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9202                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9203                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9204                 I40E_INSET_SCTP_VT,
9205                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9206                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9207                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9209                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9210                 I40E_INSET_IPV4_TTL,
9211                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9212                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9214                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9215                 I40E_INSET_IPV6_HOP_LIMIT,
9216                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9217                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9219                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9220                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9221                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9222                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9223                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9224                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9225                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9226                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9227                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9228                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9229                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9230                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9231                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9232                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9233                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9234                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9235                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9236                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9237                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9238                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9239                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9240                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9241                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9242                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9243                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9244                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9245                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9246                 I40E_INSET_SCTP_VT,
9247                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9248                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9249                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9250                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9251                 I40E_INSET_IPV6_HOP_LIMIT,
9252                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9253                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9254                 I40E_INSET_LAST_ETHER_TYPE,
9255         };
9256
9257         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9258                 return 0;
9259         if (filter == RTE_ETH_FILTER_HASH)
9260                 valid = valid_hash_inset_table[pctype];
9261         else
9262                 valid = valid_fdir_inset_table[pctype];
9263
9264         return valid;
9265 }
9266
9267 /**
9268  * Validate if the input set is allowed for a specific PCTYPE
9269  */
9270 int
9271 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9272                 enum rte_filter_type filter, uint64_t inset)
9273 {
9274         uint64_t valid;
9275
9276         valid = i40e_get_valid_input_set(pctype, filter);
9277         if (inset & (~valid))
9278                 return -EINVAL;
9279
9280         return 0;
9281 }
9282
9283 /* default input set fields combination per pctype */
9284 uint64_t
9285 i40e_get_default_input_set(uint16_t pctype)
9286 {
9287         static const uint64_t default_inset_table[] = {
9288                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9289                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9290                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9291                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9292                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9293                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9294                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9295                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9297                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9299                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9300                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9301                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9302                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9303                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9304                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9305                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9306                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9307                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9308                         I40E_INSET_SCTP_VT,
9309                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9310                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9311                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9312                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9313                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9314                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9315                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9316                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9317                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9318                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9319                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9320                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9321                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9322                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9323                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9324                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9325                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9326                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9327                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9328                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9329                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9330                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9331                         I40E_INSET_SCTP_VT,
9332                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9333                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9334                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9335                         I40E_INSET_LAST_ETHER_TYPE,
9336         };
9337
9338         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9339                 return 0;
9340
9341         return default_inset_table[pctype];
9342 }
9343
9344 /**
9345  * Translate the input set from bit masks to register aware bit masks
9346  * and vice versa
9347  */
9348 uint64_t
9349 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9350 {
9351         uint64_t val = 0;
9352         uint16_t i;
9353
9354         struct inset_map {
9355                 uint64_t inset;
9356                 uint64_t inset_reg;
9357         };
9358
9359         static const struct inset_map inset_map_common[] = {
9360                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9361                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9362                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9363                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9364                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9365                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9366                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9367                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9368                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9369                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9370                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9371                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9372                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9373                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9374                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9375                 {I40E_INSET_TUNNEL_DMAC,
9376                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9377                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9378                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9379                 {I40E_INSET_TUNNEL_SRC_PORT,
9380                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9381                 {I40E_INSET_TUNNEL_DST_PORT,
9382                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9383                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9384                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9385                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9386                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9387                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9388                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9389                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9390                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9391                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9392         };
9393
9394     /* some different registers map in x722*/
9395         static const struct inset_map inset_map_diff_x722[] = {
9396                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9397                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9398                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9399                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9400         };
9401
9402         static const struct inset_map inset_map_diff_not_x722[] = {
9403                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9404                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9405                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9406                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9407         };
9408
9409         if (input == 0)
9410                 return val;
9411
9412         /* Translate input set to register aware inset */
9413         if (type == I40E_MAC_X722) {
9414                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9415                         if (input & inset_map_diff_x722[i].inset)
9416                                 val |= inset_map_diff_x722[i].inset_reg;
9417                 }
9418         } else {
9419                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9420                         if (input & inset_map_diff_not_x722[i].inset)
9421                                 val |= inset_map_diff_not_x722[i].inset_reg;
9422                 }
9423         }
9424
9425         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9426                 if (input & inset_map_common[i].inset)
9427                         val |= inset_map_common[i].inset_reg;
9428         }
9429
9430         return val;
9431 }
9432
9433 static int
9434 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9435                             uint32_t pit_reg_count, uint32_t hdr_off)
9436 {
9437         const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9438         uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9439         uint32_t i, reg_val, src_off, count;
9440
9441         for (i = pit_reg_start; i < pit_reg_end; i++) {
9442                 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9443
9444                 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9445                 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9446
9447                 if (src_off <= field_off && (src_off + count) > field_off)
9448                         break;
9449         }
9450
9451         if (i >= pit_reg_end) {
9452                 PMD_DRV_LOG(ERR,
9453                             "Hardware GLQF_PIT configuration does not support this field mask");
9454                 return -1;
9455         }
9456
9457         return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9458 }
9459
9460 int
9461 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9462                              uint32_t *mask, uint8_t nb_elem)
9463 {
9464         static const uint64_t mask_inset[] = {
9465                 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9466                 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9467
9468         static const struct {
9469                 uint64_t inset;
9470                 uint32_t mask;
9471                 uint32_t offset;
9472         } inset_mask_offset_map[] = {
9473                 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9474                   offsetof(struct rte_ipv4_hdr, type_of_service) },
9475
9476                 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9477                   offsetof(struct rte_ipv4_hdr, next_proto_id) },
9478
9479                 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9480                   offsetof(struct rte_ipv4_hdr, time_to_live) },
9481
9482                 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9483                   offsetof(struct rte_ipv6_hdr, vtc_flow) },
9484
9485                 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9486                   offsetof(struct rte_ipv6_hdr, proto) },
9487
9488                 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9489                   offsetof(struct rte_ipv6_hdr, hop_limits) },
9490         };
9491
9492         uint32_t i;
9493         int idx = 0;
9494
9495         assert(mask);
9496         if (!inset)
9497                 return 0;
9498
9499         for (i = 0; i < RTE_DIM(mask_inset); i++) {
9500                 /* Clear the inset bit, if no MASK is required,
9501                  * for example proto + ttl
9502                  */
9503                 if ((mask_inset[i] & inset) == mask_inset[i]) {
9504                         inset &= ~mask_inset[i];
9505                         if (!inset)
9506                                 return 0;
9507                 }
9508         }
9509
9510         for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9511                 uint32_t pit_start, pit_count;
9512                 int offset;
9513
9514                 if (!(inset_mask_offset_map[i].inset & inset))
9515                         continue;
9516
9517                 if (inset_mask_offset_map[i].inset &
9518                     (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9519                      I40E_INSET_IPV4_TTL)) {
9520                         pit_start = I40E_GLQF_PIT_IPV4_START;
9521                         pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9522                 } else {
9523                         pit_start = I40E_GLQF_PIT_IPV6_START;
9524                         pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9525                 }
9526
9527                 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9528                                 inset_mask_offset_map[i].offset);
9529
9530                 if (offset < 0)
9531                         return -EINVAL;
9532
9533                 if (idx >= nb_elem) {
9534                         PMD_DRV_LOG(ERR,
9535                                     "Configuration of inset mask out of range %u",
9536                                     nb_elem);
9537                         return -ERANGE;
9538                 }
9539
9540                 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9541                                                 inset_mask_offset_map[i].mask);
9542                 idx++;
9543         }
9544
9545         return idx;
9546 }
9547
9548 void
9549 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9550 {
9551         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9552
9553         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9554         if (reg != val)
9555                 i40e_write_rx_ctl(hw, addr, val);
9556         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9557                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9558 }
9559
9560 void
9561 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9562 {
9563         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9564         struct rte_eth_dev_data *dev_data =
9565                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
9566         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
9567
9568         if (reg != val) {
9569                 i40e_write_rx_ctl(hw, addr, val);
9570                 PMD_DRV_LOG(WARNING,
9571                             "i40e device %s changed global register [0x%08x]."
9572                             " original: 0x%08x, new: 0x%08x",
9573                             dev->device->name, addr, reg,
9574                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9575         }
9576 }
9577
9578 static void
9579 i40e_filter_input_set_init(struct i40e_pf *pf)
9580 {
9581         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9582         enum i40e_filter_pctype pctype;
9583         uint64_t input_set, inset_reg;
9584         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9585         int num, i;
9586         uint16_t flow_type;
9587
9588         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9589              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9590                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9591
9592                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9593                         continue;
9594
9595                 input_set = i40e_get_default_input_set(pctype);
9596
9597                 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9598                                                    I40E_INSET_MASK_NUM_REG);
9599                 if (num < 0)
9600                         return;
9601                 if (pf->support_multi_driver && num > 0) {
9602                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9603                         return;
9604                 }
9605                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9606                                         input_set);
9607
9608                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9609                                       (uint32_t)(inset_reg & UINT32_MAX));
9610                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9611                                      (uint32_t)((inset_reg >>
9612                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9613                 if (!pf->support_multi_driver) {
9614                         i40e_check_write_global_reg(hw,
9615                                             I40E_GLQF_HASH_INSET(0, pctype),
9616                                             (uint32_t)(inset_reg & UINT32_MAX));
9617                         i40e_check_write_global_reg(hw,
9618                                              I40E_GLQF_HASH_INSET(1, pctype),
9619                                              (uint32_t)((inset_reg >>
9620                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9621
9622                         for (i = 0; i < num; i++) {
9623                                 i40e_check_write_global_reg(hw,
9624                                                     I40E_GLQF_FD_MSK(i, pctype),
9625                                                     mask_reg[i]);
9626                                 i40e_check_write_global_reg(hw,
9627                                                   I40E_GLQF_HASH_MSK(i, pctype),
9628                                                   mask_reg[i]);
9629                         }
9630                         /*clear unused mask registers of the pctype */
9631                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9632                                 i40e_check_write_global_reg(hw,
9633                                                     I40E_GLQF_FD_MSK(i, pctype),
9634                                                     0);
9635                                 i40e_check_write_global_reg(hw,
9636                                                   I40E_GLQF_HASH_MSK(i, pctype),
9637                                                   0);
9638                         }
9639                 } else {
9640                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9641                 }
9642                 I40E_WRITE_FLUSH(hw);
9643
9644                 /* store the default input set */
9645                 if (!pf->support_multi_driver)
9646                         pf->hash_input_set[pctype] = input_set;
9647                 pf->fdir.input_set[pctype] = input_set;
9648         }
9649 }
9650
9651 int
9652 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9653                     uint32_t pctype, bool add)
9654 {
9655         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9656         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9657         uint64_t inset_reg = 0;
9658         int num, i;
9659
9660         if (pf->support_multi_driver) {
9661                 PMD_DRV_LOG(ERR,
9662                             "Modify input set is not permitted when multi-driver enabled.");
9663                 return -EPERM;
9664         }
9665
9666         /* For X722, get translated pctype in fd pctype register */
9667         if (hw->mac.type == I40E_MAC_X722)
9668                 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9669
9670         if (add) {
9671                 /* get inset value in register */
9672                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9673                 inset_reg <<= I40E_32_BIT_WIDTH;
9674                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9675                 input_set |= pf->hash_input_set[pctype];
9676         }
9677         num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9678                                            I40E_INSET_MASK_NUM_REG);
9679         if (num < 0)
9680                 return -EINVAL;
9681
9682         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9683
9684         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9685                                     (uint32_t)(inset_reg & UINT32_MAX));
9686         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9687                                     (uint32_t)((inset_reg >>
9688                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9689
9690         for (i = 0; i < num; i++)
9691                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9692                                             mask_reg[i]);
9693         /*clear unused mask registers of the pctype */
9694         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9695                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9696                                             0);
9697         I40E_WRITE_FLUSH(hw);
9698
9699         pf->hash_input_set[pctype] = input_set;
9700         return 0;
9701 }
9702
9703 /* Convert ethertype filter structure */
9704 static int
9705 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9706                               struct i40e_ethertype_filter *filter)
9707 {
9708         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9709                 RTE_ETHER_ADDR_LEN);
9710         filter->input.ether_type = input->ether_type;
9711         filter->flags = input->flags;
9712         filter->queue = input->queue;
9713
9714         return 0;
9715 }
9716
9717 /* Check if there exists the ehtertype filter */
9718 struct i40e_ethertype_filter *
9719 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9720                                 const struct i40e_ethertype_filter_input *input)
9721 {
9722         int ret;
9723
9724         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9725         if (ret < 0)
9726                 return NULL;
9727
9728         return ethertype_rule->hash_map[ret];
9729 }
9730
9731 /* Add ethertype filter in SW list */
9732 static int
9733 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9734                                 struct i40e_ethertype_filter *filter)
9735 {
9736         struct i40e_ethertype_rule *rule = &pf->ethertype;
9737         int ret;
9738
9739         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9740         if (ret < 0) {
9741                 PMD_DRV_LOG(ERR,
9742                             "Failed to insert ethertype filter"
9743                             " to hash table %d!",
9744                             ret);
9745                 return ret;
9746         }
9747         rule->hash_map[ret] = filter;
9748
9749         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9750
9751         return 0;
9752 }
9753
9754 /* Delete ethertype filter in SW list */
9755 int
9756 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9757                              struct i40e_ethertype_filter_input *input)
9758 {
9759         struct i40e_ethertype_rule *rule = &pf->ethertype;
9760         struct i40e_ethertype_filter *filter;
9761         int ret;
9762
9763         ret = rte_hash_del_key(rule->hash_table, input);
9764         if (ret < 0) {
9765                 PMD_DRV_LOG(ERR,
9766                             "Failed to delete ethertype filter"
9767                             " to hash table %d!",
9768                             ret);
9769                 return ret;
9770         }
9771         filter = rule->hash_map[ret];
9772         rule->hash_map[ret] = NULL;
9773
9774         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9775         rte_free(filter);
9776
9777         return 0;
9778 }
9779
9780 /*
9781  * Configure ethertype filter, which can director packet by filtering
9782  * with mac address and ether_type or only ether_type
9783  */
9784 int
9785 i40e_ethertype_filter_set(struct i40e_pf *pf,
9786                         struct rte_eth_ethertype_filter *filter,
9787                         bool add)
9788 {
9789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9790         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9791         struct i40e_ethertype_filter *ethertype_filter, *node;
9792         struct i40e_ethertype_filter check_filter;
9793         struct i40e_control_filter_stats stats;
9794         uint16_t flags = 0;
9795         int ret;
9796
9797         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9798                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9799                 return -EINVAL;
9800         }
9801         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9802                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9803                 PMD_DRV_LOG(ERR,
9804                         "unsupported ether_type(0x%04x) in control packet filter.",
9805                         filter->ether_type);
9806                 return -EINVAL;
9807         }
9808         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9809                 PMD_DRV_LOG(WARNING,
9810                         "filter vlan ether_type in first tag is not supported.");
9811
9812         /* Check if there is the filter in SW list */
9813         memset(&check_filter, 0, sizeof(check_filter));
9814         i40e_ethertype_filter_convert(filter, &check_filter);
9815         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9816                                                &check_filter.input);
9817         if (add && node) {
9818                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9819                 return -EINVAL;
9820         }
9821
9822         if (!add && !node) {
9823                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9824                 return -EINVAL;
9825         }
9826
9827         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9828                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9829         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9830                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9831         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9832
9833         memset(&stats, 0, sizeof(stats));
9834         ret = i40e_aq_add_rem_control_packet_filter(hw,
9835                         filter->mac_addr.addr_bytes,
9836                         filter->ether_type, flags,
9837                         pf->main_vsi->seid,
9838                         filter->queue, add, &stats, NULL);
9839
9840         PMD_DRV_LOG(INFO,
9841                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9842                 ret, stats.mac_etype_used, stats.etype_used,
9843                 stats.mac_etype_free, stats.etype_free);
9844         if (ret < 0)
9845                 return -ENOSYS;
9846
9847         /* Add or delete a filter in SW list */
9848         if (add) {
9849                 ethertype_filter = rte_zmalloc("ethertype_filter",
9850                                        sizeof(*ethertype_filter), 0);
9851                 if (ethertype_filter == NULL) {
9852                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9853                         return -ENOMEM;
9854                 }
9855
9856                 rte_memcpy(ethertype_filter, &check_filter,
9857                            sizeof(check_filter));
9858                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9859                 if (ret < 0)
9860                         rte_free(ethertype_filter);
9861         } else {
9862                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9863         }
9864
9865         return ret;
9866 }
9867
9868 static int
9869 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9870                       const struct rte_flow_ops **ops)
9871 {
9872         if (dev == NULL)
9873                 return -EINVAL;
9874
9875         *ops = &i40e_flow_ops;
9876         return 0;
9877 }
9878
9879 /*
9880  * Check and enable Extended Tag.
9881  * Enabling Extended Tag is important for 40G performance.
9882  */
9883 static void
9884 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9885 {
9886         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9887         uint32_t buf = 0;
9888         int ret;
9889
9890         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9891                                       PCI_DEV_CAP_REG);
9892         if (ret < 0) {
9893                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9894                             PCI_DEV_CAP_REG);
9895                 return;
9896         }
9897         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9898                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9899                 return;
9900         }
9901
9902         buf = 0;
9903         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9904                                       PCI_DEV_CTRL_REG);
9905         if (ret < 0) {
9906                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9907                             PCI_DEV_CTRL_REG);
9908                 return;
9909         }
9910         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9911                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9912                 return;
9913         }
9914         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9915         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9916                                        PCI_DEV_CTRL_REG);
9917         if (ret < 0) {
9918                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9919                             PCI_DEV_CTRL_REG);
9920                 return;
9921         }
9922 }
9923
9924 /*
9925  * As some registers wouldn't be reset unless a global hardware reset,
9926  * hardware initialization is needed to put those registers into an
9927  * expected initial state.
9928  */
9929 static void
9930 i40e_hw_init(struct rte_eth_dev *dev)
9931 {
9932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9933
9934         i40e_enable_extended_tag(dev);
9935
9936         /* clear the PF Queue Filter control register */
9937         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9938
9939         /* Disable symmetric hash per port */
9940         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9941 }
9942
9943 /*
9944  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9945  * however this function will return only one highest pctype index,
9946  * which is not quite correct. This is known problem of i40e driver
9947  * and needs to be fixed later.
9948  */
9949 enum i40e_filter_pctype
9950 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9951 {
9952         int i;
9953         uint64_t pctype_mask;
9954
9955         if (flow_type < I40E_FLOW_TYPE_MAX) {
9956                 pctype_mask = adapter->pctypes_tbl[flow_type];
9957                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9958                         if (pctype_mask & (1ULL << i))
9959                                 return (enum i40e_filter_pctype)i;
9960                 }
9961         }
9962         return I40E_FILTER_PCTYPE_INVALID;
9963 }
9964
9965 uint16_t
9966 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9967                         enum i40e_filter_pctype pctype)
9968 {
9969         uint16_t flowtype;
9970         uint64_t pctype_mask = 1ULL << pctype;
9971
9972         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9973              flowtype++) {
9974                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9975                         return flowtype;
9976         }
9977
9978         return RTE_ETH_FLOW_UNKNOWN;
9979 }
9980
9981 /*
9982  * On X710, performance number is far from the expectation on recent firmware
9983  * versions; on XL710, performance number is also far from the expectation on
9984  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9985  * mode is enabled and port MAC address is equal to the packet destination MAC
9986  * address. The fix for this issue may not be integrated in the following
9987  * firmware version. So the workaround in software driver is needed. It needs
9988  * to modify the initial values of 3 internal only registers for both X710 and
9989  * XL710. Note that the values for X710 or XL710 could be different, and the
9990  * workaround can be removed when it is fixed in firmware in the future.
9991  */
9992
9993 /* For both X710 and XL710 */
9994 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9995 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9996 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9997
9998 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9999 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10000
10001 /* For X722 */
10002 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10003 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10004
10005 /* For X710 */
10006 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10007 /* For XL710 */
10008 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10009 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10010
10011 /*
10012  * GL_SWR_PM_UP_THR:
10013  * The value is not impacted from the link speed, its value is set according
10014  * to the total number of ports for a better pipe-monitor configuration.
10015  */
10016 static bool
10017 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10018 {
10019 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10020                 .device_id = (dev),   \
10021                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10022
10023 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10024                 .device_id = (dev),   \
10025                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10026
10027         static const struct {
10028                 uint16_t device_id;
10029                 uint32_t val;
10030         } swr_pm_table[] = {
10031                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10032                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10033                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10034                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10035                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10036
10037                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10038                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10039                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10040                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10041                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10042                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10043                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10044         };
10045         uint32_t i;
10046
10047         if (value == NULL) {
10048                 PMD_DRV_LOG(ERR, "value is NULL");
10049                 return false;
10050         }
10051
10052         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10053                 if (hw->device_id == swr_pm_table[i].device_id) {
10054                         *value = swr_pm_table[i].val;
10055
10056                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10057                                     "value - 0x%08x",
10058                                     hw->device_id, *value);
10059                         return true;
10060                 }
10061         }
10062
10063         return false;
10064 }
10065
10066 static int
10067 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10068 {
10069         enum i40e_status_code status;
10070         struct i40e_aq_get_phy_abilities_resp phy_ab;
10071         int ret = -ENOTSUP;
10072         int retries = 0;
10073
10074         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10075                                               NULL);
10076
10077         while (status) {
10078                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10079                         status);
10080                 retries++;
10081                 rte_delay_us(100000);
10082                 if  (retries < 5)
10083                         status = i40e_aq_get_phy_capabilities(hw, false,
10084                                         true, &phy_ab, NULL);
10085                 else
10086                         return ret;
10087         }
10088         return 0;
10089 }
10090
10091 static void
10092 i40e_configure_registers(struct i40e_hw *hw)
10093 {
10094         static struct {
10095                 uint32_t addr;
10096                 uint64_t val;
10097         } reg_table[] = {
10098                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10099                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10100                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10101         };
10102         uint64_t reg;
10103         uint32_t i;
10104         int ret;
10105
10106         for (i = 0; i < RTE_DIM(reg_table); i++) {
10107                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10108                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10109                                 reg_table[i].val =
10110                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10111                         else /* For X710/XL710/XXV710 */
10112                                 if (hw->aq.fw_maj_ver < 6)
10113                                         reg_table[i].val =
10114                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10115                                 else
10116                                         reg_table[i].val =
10117                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10118                 }
10119
10120                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10121                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10122                                 reg_table[i].val =
10123                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10124                         else /* For X710/XL710/XXV710 */
10125                                 reg_table[i].val =
10126                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10127                 }
10128
10129                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10130                         uint32_t cfg_val;
10131
10132                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10133                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10134                                             "GL_SWR_PM_UP_THR value fixup",
10135                                             hw->device_id);
10136                                 continue;
10137                         }
10138
10139                         reg_table[i].val = cfg_val;
10140                 }
10141
10142                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10143                                                         &reg, NULL);
10144                 if (ret < 0) {
10145                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10146                                                         reg_table[i].addr);
10147                         break;
10148                 }
10149                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10150                                                 reg_table[i].addr, reg);
10151                 if (reg == reg_table[i].val)
10152                         continue;
10153
10154                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10155                                                 reg_table[i].val, NULL);
10156                 if (ret < 0) {
10157                         PMD_DRV_LOG(ERR,
10158                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10159                                 reg_table[i].val, reg_table[i].addr);
10160                         break;
10161                 }
10162                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10163                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10164         }
10165 }
10166
10167 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10168 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10169 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10170 static int
10171 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10172 {
10173         uint32_t reg;
10174         int ret;
10175
10176         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10177                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10178                 return -EINVAL;
10179         }
10180
10181         /* Configure for double VLAN RX stripping */
10182         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10183         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10184                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10185                 ret = i40e_aq_debug_write_register(hw,
10186                                                    I40E_VSI_TSR(vsi->vsi_id),
10187                                                    reg, NULL);
10188                 if (ret < 0) {
10189                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10190                                     vsi->vsi_id);
10191                         return I40E_ERR_CONFIG;
10192                 }
10193         }
10194
10195         /* Configure for double VLAN TX insertion */
10196         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10197         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10198                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10199                 ret = i40e_aq_debug_write_register(hw,
10200                                                    I40E_VSI_L2TAGSTXVALID(
10201                                                    vsi->vsi_id), reg, NULL);
10202                 if (ret < 0) {
10203                         PMD_DRV_LOG(ERR,
10204                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10205                                 vsi->vsi_id);
10206                         return I40E_ERR_CONFIG;
10207                 }
10208         }
10209
10210         return 0;
10211 }
10212
10213 static uint64_t
10214 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10215 {
10216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10217         uint64_t systim_cycles;
10218
10219         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10220         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10221                         << 32;
10222
10223         return systim_cycles;
10224 }
10225
10226 static uint64_t
10227 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10228 {
10229         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10230         uint64_t rx_tstamp;
10231
10232         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10233         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10234                         << 32;
10235
10236         return rx_tstamp;
10237 }
10238
10239 static uint64_t
10240 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10241 {
10242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10243         uint64_t tx_tstamp;
10244
10245         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10246         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10247                         << 32;
10248
10249         return tx_tstamp;
10250 }
10251
10252 static void
10253 i40e_start_timecounters(struct rte_eth_dev *dev)
10254 {
10255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10256         struct i40e_adapter *adapter = dev->data->dev_private;
10257         struct rte_eth_link link;
10258         uint32_t tsync_inc_l;
10259         uint32_t tsync_inc_h;
10260
10261         /* Get current link speed. */
10262         i40e_dev_link_update(dev, 1);
10263         rte_eth_linkstatus_get(dev, &link);
10264
10265         switch (link.link_speed) {
10266         case ETH_SPEED_NUM_40G:
10267         case ETH_SPEED_NUM_25G:
10268                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10269                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10270                 break;
10271         case ETH_SPEED_NUM_10G:
10272                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10273                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10274                 break;
10275         case ETH_SPEED_NUM_1G:
10276                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10277                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10278                 break;
10279         default:
10280                 tsync_inc_l = 0x0;
10281                 tsync_inc_h = 0x0;
10282         }
10283
10284         /* Set the timesync increment value. */
10285         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10286         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10287
10288         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10289         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10290         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10291
10292         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10293         adapter->systime_tc.cc_shift = 0;
10294         adapter->systime_tc.nsec_mask = 0;
10295
10296         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10297         adapter->rx_tstamp_tc.cc_shift = 0;
10298         adapter->rx_tstamp_tc.nsec_mask = 0;
10299
10300         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10301         adapter->tx_tstamp_tc.cc_shift = 0;
10302         adapter->tx_tstamp_tc.nsec_mask = 0;
10303 }
10304
10305 static int
10306 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10307 {
10308         struct i40e_adapter *adapter = dev->data->dev_private;
10309
10310         adapter->systime_tc.nsec += delta;
10311         adapter->rx_tstamp_tc.nsec += delta;
10312         adapter->tx_tstamp_tc.nsec += delta;
10313
10314         return 0;
10315 }
10316
10317 static int
10318 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10319 {
10320         uint64_t ns;
10321         struct i40e_adapter *adapter = dev->data->dev_private;
10322
10323         ns = rte_timespec_to_ns(ts);
10324
10325         /* Set the timecounters to a new value. */
10326         adapter->systime_tc.nsec = ns;
10327         adapter->rx_tstamp_tc.nsec = ns;
10328         adapter->tx_tstamp_tc.nsec = ns;
10329
10330         return 0;
10331 }
10332
10333 static int
10334 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10335 {
10336         uint64_t ns, systime_cycles;
10337         struct i40e_adapter *adapter = dev->data->dev_private;
10338
10339         systime_cycles = i40e_read_systime_cyclecounter(dev);
10340         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10341         *ts = rte_ns_to_timespec(ns);
10342
10343         return 0;
10344 }
10345
10346 static int
10347 i40e_timesync_enable(struct rte_eth_dev *dev)
10348 {
10349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10350         uint32_t tsync_ctl_l;
10351         uint32_t tsync_ctl_h;
10352
10353         /* Stop the timesync system time. */
10354         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10355         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10356         /* Reset the timesync system time value. */
10357         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10358         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10359
10360         i40e_start_timecounters(dev);
10361
10362         /* Clear timesync registers. */
10363         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10364         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10365         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10366         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10367         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10368         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10369
10370         /* Enable timestamping of PTP packets. */
10371         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10372         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10373
10374         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10375         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10376         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10377
10378         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10379         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10380
10381         return 0;
10382 }
10383
10384 static int
10385 i40e_timesync_disable(struct rte_eth_dev *dev)
10386 {
10387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10388         uint32_t tsync_ctl_l;
10389         uint32_t tsync_ctl_h;
10390
10391         /* Disable timestamping of transmitted PTP packets. */
10392         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10393         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10394
10395         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10396         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10397
10398         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10399         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10400
10401         /* Reset the timesync increment value. */
10402         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10403         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10404
10405         return 0;
10406 }
10407
10408 static int
10409 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10410                                 struct timespec *timestamp, uint32_t flags)
10411 {
10412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10413         struct i40e_adapter *adapter = dev->data->dev_private;
10414         uint32_t sync_status;
10415         uint32_t index = flags & 0x03;
10416         uint64_t rx_tstamp_cycles;
10417         uint64_t ns;
10418
10419         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10420         if ((sync_status & (1 << index)) == 0)
10421                 return -EINVAL;
10422
10423         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10424         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10425         *timestamp = rte_ns_to_timespec(ns);
10426
10427         return 0;
10428 }
10429
10430 static int
10431 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10432                                 struct timespec *timestamp)
10433 {
10434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10435         struct i40e_adapter *adapter = dev->data->dev_private;
10436         uint32_t sync_status;
10437         uint64_t tx_tstamp_cycles;
10438         uint64_t ns;
10439
10440         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10441         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10442                 return -EINVAL;
10443
10444         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10445         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10446         *timestamp = rte_ns_to_timespec(ns);
10447
10448         return 0;
10449 }
10450
10451 /*
10452  * i40e_parse_dcb_configure - parse dcb configure from user
10453  * @dev: the device being configured
10454  * @dcb_cfg: pointer of the result of parse
10455  * @*tc_map: bit map of enabled traffic classes
10456  *
10457  * Returns 0 on success, negative value on failure
10458  */
10459 static int
10460 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10461                          struct i40e_dcbx_config *dcb_cfg,
10462                          uint8_t *tc_map)
10463 {
10464         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10465         uint8_t i, tc_bw, bw_lf;
10466
10467         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10468
10469         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10470         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10471                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10472                 return -EINVAL;
10473         }
10474
10475         /* assume each tc has the same bw */
10476         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10477         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10478                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10479         /* to ensure the sum of tcbw is equal to 100 */
10480         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10481         for (i = 0; i < bw_lf; i++)
10482                 dcb_cfg->etscfg.tcbwtable[i]++;
10483
10484         /* assume each tc has the same Transmission Selection Algorithm */
10485         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10486                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10487
10488         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10489                 dcb_cfg->etscfg.prioritytable[i] =
10490                                 dcb_rx_conf->dcb_tc[i];
10491
10492         /* FW needs one App to configure HW */
10493         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10494         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10495         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10496         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10497
10498         if (dcb_rx_conf->nb_tcs == 0)
10499                 *tc_map = 1; /* tc0 only */
10500         else
10501                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10502
10503         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10504                 dcb_cfg->pfc.willing = 0;
10505                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10506                 dcb_cfg->pfc.pfcenable = *tc_map;
10507         }
10508         return 0;
10509 }
10510
10511
10512 static enum i40e_status_code
10513 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10514                               struct i40e_aqc_vsi_properties_data *info,
10515                               uint8_t enabled_tcmap)
10516 {
10517         enum i40e_status_code ret;
10518         int i, total_tc = 0;
10519         uint16_t qpnum_per_tc, bsf, qp_idx;
10520         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10521         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10522         uint16_t used_queues;
10523
10524         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10525         if (ret != I40E_SUCCESS)
10526                 return ret;
10527
10528         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10529                 if (enabled_tcmap & (1 << i))
10530                         total_tc++;
10531         }
10532         if (total_tc == 0)
10533                 total_tc = 1;
10534         vsi->enabled_tc = enabled_tcmap;
10535
10536         /* different VSI has different queues assigned */
10537         if (vsi->type == I40E_VSI_MAIN)
10538                 used_queues = dev_data->nb_rx_queues -
10539                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10540         else if (vsi->type == I40E_VSI_VMDQ2)
10541                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10542         else {
10543                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10544                 return I40E_ERR_NO_AVAILABLE_VSI;
10545         }
10546
10547         qpnum_per_tc = used_queues / total_tc;
10548         /* Number of queues per enabled TC */
10549         if (qpnum_per_tc == 0) {
10550                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10551                 return I40E_ERR_INVALID_QP_ID;
10552         }
10553         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10554                                 I40E_MAX_Q_PER_TC);
10555         bsf = rte_bsf32(qpnum_per_tc);
10556
10557         /**
10558          * Configure TC and queue mapping parameters, for enabled TC,
10559          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10560          * default queue will serve it.
10561          */
10562         qp_idx = 0;
10563         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10564                 if (vsi->enabled_tc & (1 << i)) {
10565                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10566                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10567                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10568                         qp_idx += qpnum_per_tc;
10569                 } else
10570                         info->tc_mapping[i] = 0;
10571         }
10572
10573         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10574         if (vsi->type == I40E_VSI_SRIOV) {
10575                 info->mapping_flags |=
10576                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10577                 for (i = 0; i < vsi->nb_qps; i++)
10578                         info->queue_mapping[i] =
10579                                 rte_cpu_to_le_16(vsi->base_queue + i);
10580         } else {
10581                 info->mapping_flags |=
10582                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10583                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10584         }
10585         info->valid_sections |=
10586                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10587
10588         return I40E_SUCCESS;
10589 }
10590
10591 /*
10592  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10593  * @veb: VEB to be configured
10594  * @tc_map: enabled TC bitmap
10595  *
10596  * Returns 0 on success, negative value on failure
10597  */
10598 static enum i40e_status_code
10599 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10600 {
10601         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10602         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10603         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10604         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10605         enum i40e_status_code ret = I40E_SUCCESS;
10606         int i;
10607         uint32_t bw_max;
10608
10609         /* Check if enabled_tc is same as existing or new TCs */
10610         if (veb->enabled_tc == tc_map)
10611                 return ret;
10612
10613         /* configure tc bandwidth */
10614         memset(&veb_bw, 0, sizeof(veb_bw));
10615         veb_bw.tc_valid_bits = tc_map;
10616         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10617         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10618                 if (tc_map & BIT_ULL(i))
10619                         veb_bw.tc_bw_share_credits[i] = 1;
10620         }
10621         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10622                                                    &veb_bw, NULL);
10623         if (ret) {
10624                 PMD_INIT_LOG(ERR,
10625                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10626                         hw->aq.asq_last_status);
10627                 return ret;
10628         }
10629
10630         memset(&ets_query, 0, sizeof(ets_query));
10631         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10632                                                    &ets_query, NULL);
10633         if (ret != I40E_SUCCESS) {
10634                 PMD_DRV_LOG(ERR,
10635                         "Failed to get switch_comp ETS configuration %u",
10636                         hw->aq.asq_last_status);
10637                 return ret;
10638         }
10639         memset(&bw_query, 0, sizeof(bw_query));
10640         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10641                                                   &bw_query, NULL);
10642         if (ret != I40E_SUCCESS) {
10643                 PMD_DRV_LOG(ERR,
10644                         "Failed to get switch_comp bandwidth configuration %u",
10645                         hw->aq.asq_last_status);
10646                 return ret;
10647         }
10648
10649         /* store and print out BW info */
10650         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10651         veb->bw_info.bw_max = ets_query.tc_bw_max;
10652         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10653         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10654         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10655                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10656                      I40E_16_BIT_WIDTH);
10657         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10658                 veb->bw_info.bw_ets_share_credits[i] =
10659                                 bw_query.tc_bw_share_credits[i];
10660                 veb->bw_info.bw_ets_credits[i] =
10661                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10662                 /* 4 bits per TC, 4th bit is reserved */
10663                 veb->bw_info.bw_ets_max[i] =
10664                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10665                                   RTE_LEN2MASK(3, uint8_t));
10666                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10667                             veb->bw_info.bw_ets_share_credits[i]);
10668                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10669                             veb->bw_info.bw_ets_credits[i]);
10670                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10671                             veb->bw_info.bw_ets_max[i]);
10672         }
10673
10674         veb->enabled_tc = tc_map;
10675
10676         return ret;
10677 }
10678
10679
10680 /*
10681  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10682  * @vsi: VSI to be configured
10683  * @tc_map: enabled TC bitmap
10684  *
10685  * Returns 0 on success, negative value on failure
10686  */
10687 static enum i40e_status_code
10688 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10689 {
10690         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10691         struct i40e_vsi_context ctxt;
10692         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10693         enum i40e_status_code ret = I40E_SUCCESS;
10694         int i;
10695
10696         /* Check if enabled_tc is same as existing or new TCs */
10697         if (vsi->enabled_tc == tc_map)
10698                 return ret;
10699
10700         /* configure tc bandwidth */
10701         memset(&bw_data, 0, sizeof(bw_data));
10702         bw_data.tc_valid_bits = tc_map;
10703         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10704         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10705                 if (tc_map & BIT_ULL(i))
10706                         bw_data.tc_bw_credits[i] = 1;
10707         }
10708         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10709         if (ret) {
10710                 PMD_INIT_LOG(ERR,
10711                         "AQ command Config VSI BW allocation per TC failed = %d",
10712                         hw->aq.asq_last_status);
10713                 goto out;
10714         }
10715         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10716                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10717
10718         /* Update Queue Pairs Mapping for currently enabled UPs */
10719         ctxt.seid = vsi->seid;
10720         ctxt.pf_num = hw->pf_id;
10721         ctxt.vf_num = 0;
10722         ctxt.uplink_seid = vsi->uplink_seid;
10723         ctxt.info = vsi->info;
10724         i40e_get_cap(hw);
10725         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10726         if (ret)
10727                 goto out;
10728
10729         /* Update the VSI after updating the VSI queue-mapping information */
10730         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10731         if (ret) {
10732                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10733                         hw->aq.asq_last_status);
10734                 goto out;
10735         }
10736         /* update the local VSI info with updated queue map */
10737         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10738                                         sizeof(vsi->info.tc_mapping));
10739         rte_memcpy(&vsi->info.queue_mapping,
10740                         &ctxt.info.queue_mapping,
10741                 sizeof(vsi->info.queue_mapping));
10742         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10743         vsi->info.valid_sections = 0;
10744
10745         /* query and update current VSI BW information */
10746         ret = i40e_vsi_get_bw_config(vsi);
10747         if (ret) {
10748                 PMD_INIT_LOG(ERR,
10749                          "Failed updating vsi bw info, err %s aq_err %s",
10750                          i40e_stat_str(hw, ret),
10751                          i40e_aq_str(hw, hw->aq.asq_last_status));
10752                 goto out;
10753         }
10754
10755         vsi->enabled_tc = tc_map;
10756
10757 out:
10758         return ret;
10759 }
10760
10761 /*
10762  * i40e_dcb_hw_configure - program the dcb setting to hw
10763  * @pf: pf the configuration is taken on
10764  * @new_cfg: new configuration
10765  * @tc_map: enabled TC bitmap
10766  *
10767  * Returns 0 on success, negative value on failure
10768  */
10769 static enum i40e_status_code
10770 i40e_dcb_hw_configure(struct i40e_pf *pf,
10771                       struct i40e_dcbx_config *new_cfg,
10772                       uint8_t tc_map)
10773 {
10774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10775         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10776         struct i40e_vsi *main_vsi = pf->main_vsi;
10777         struct i40e_vsi_list *vsi_list;
10778         enum i40e_status_code ret;
10779         int i;
10780         uint32_t val;
10781
10782         /* Use the FW API if FW > v4.4*/
10783         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10784               (hw->aq.fw_maj_ver >= 5))) {
10785                 PMD_INIT_LOG(ERR,
10786                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10787                 return I40E_ERR_FIRMWARE_API_VERSION;
10788         }
10789
10790         /* Check if need reconfiguration */
10791         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10792                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10793                 return I40E_SUCCESS;
10794         }
10795
10796         /* Copy the new config to the current config */
10797         *old_cfg = *new_cfg;
10798         old_cfg->etsrec = old_cfg->etscfg;
10799         ret = i40e_set_dcb_config(hw);
10800         if (ret) {
10801                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10802                          i40e_stat_str(hw, ret),
10803                          i40e_aq_str(hw, hw->aq.asq_last_status));
10804                 return ret;
10805         }
10806         /* set receive Arbiter to RR mode and ETS scheme by default */
10807         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10808                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10809                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10810                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10811                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10812                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10813                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10814                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10815                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10816                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10817                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10818                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10819                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10820         }
10821         /* get local mib to check whether it is configured correctly */
10822         /* IEEE mode */
10823         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10824         /* Get Local DCB Config */
10825         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10826                                      &hw->local_dcbx_config);
10827
10828         /* if Veb is created, need to update TC of it at first */
10829         if (main_vsi->veb) {
10830                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10831                 if (ret)
10832                         PMD_INIT_LOG(WARNING,
10833                                  "Failed configuring TC for VEB seid=%d",
10834                                  main_vsi->veb->seid);
10835         }
10836         /* Update each VSI */
10837         i40e_vsi_config_tc(main_vsi, tc_map);
10838         if (main_vsi->veb) {
10839                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10840                         /* Beside main VSI and VMDQ VSIs, only enable default
10841                          * TC for other VSIs
10842                          */
10843                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10844                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10845                                                          tc_map);
10846                         else
10847                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10848                                                          I40E_DEFAULT_TCMAP);
10849                         if (ret)
10850                                 PMD_INIT_LOG(WARNING,
10851                                         "Failed configuring TC for VSI seid=%d",
10852                                         vsi_list->vsi->seid);
10853                         /* continue */
10854                 }
10855         }
10856         return I40E_SUCCESS;
10857 }
10858
10859 /*
10860  * i40e_dcb_init_configure - initial dcb config
10861  * @dev: device being configured
10862  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10863  *
10864  * Returns 0 on success, negative value on failure
10865  */
10866 int
10867 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10868 {
10869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10871         int i, ret = 0;
10872
10873         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10874                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10875                 return -ENOTSUP;
10876         }
10877
10878         /* DCB initialization:
10879          * Update DCB configuration from the Firmware and configure
10880          * LLDP MIB change event.
10881          */
10882         if (sw_dcb == TRUE) {
10883                 /* Stopping lldp is necessary for DPDK, but it will cause
10884                  * DCB init failed. For i40e_init_dcb(), the prerequisite
10885                  * for successful initialization of DCB is that LLDP is
10886                  * enabled. So it is needed to start lldp before DCB init
10887                  * and stop it after initialization.
10888                  */
10889                 ret = i40e_aq_start_lldp(hw, true, NULL);
10890                 if (ret != I40E_SUCCESS)
10891                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10892
10893                 ret = i40e_init_dcb(hw, true);
10894                 /* If lldp agent is stopped, the return value from
10895                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10896                  * adminq status. Otherwise, it should return success.
10897                  */
10898                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10899                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10900                         memset(&hw->local_dcbx_config, 0,
10901                                 sizeof(struct i40e_dcbx_config));
10902                         /* set dcb default configuration */
10903                         hw->local_dcbx_config.etscfg.willing = 0;
10904                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10905                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10906                         hw->local_dcbx_config.etscfg.tsatable[0] =
10907                                                 I40E_IEEE_TSA_ETS;
10908                         /* all UPs mapping to TC0 */
10909                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10910                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10911                         hw->local_dcbx_config.etsrec =
10912                                 hw->local_dcbx_config.etscfg;
10913                         hw->local_dcbx_config.pfc.willing = 0;
10914                         hw->local_dcbx_config.pfc.pfccap =
10915                                                 I40E_MAX_TRAFFIC_CLASS;
10916                         /* FW needs one App to configure HW */
10917                         hw->local_dcbx_config.numapps = 1;
10918                         hw->local_dcbx_config.app[0].selector =
10919                                                 I40E_APP_SEL_ETHTYPE;
10920                         hw->local_dcbx_config.app[0].priority = 3;
10921                         hw->local_dcbx_config.app[0].protocolid =
10922                                                 I40E_APP_PROTOID_FCOE;
10923                         ret = i40e_set_dcb_config(hw);
10924                         if (ret) {
10925                                 PMD_INIT_LOG(ERR,
10926                                         "default dcb config fails. err = %d, aq_err = %d.",
10927                                         ret, hw->aq.asq_last_status);
10928                                 return -ENOSYS;
10929                         }
10930                 } else {
10931                         PMD_INIT_LOG(ERR,
10932                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10933                                 ret, hw->aq.asq_last_status);
10934                         return -ENOTSUP;
10935                 }
10936
10937                 if (i40e_need_stop_lldp(dev)) {
10938                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
10939                         if (ret != I40E_SUCCESS)
10940                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
10941                 }
10942         } else {
10943                 ret = i40e_aq_start_lldp(hw, true, NULL);
10944                 if (ret != I40E_SUCCESS)
10945                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10946
10947                 ret = i40e_init_dcb(hw, true);
10948                 if (!ret) {
10949                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10950                                 PMD_INIT_LOG(ERR,
10951                                         "HW doesn't support DCBX offload.");
10952                                 return -ENOTSUP;
10953                         }
10954                 } else {
10955                         PMD_INIT_LOG(ERR,
10956                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10957                                 ret, hw->aq.asq_last_status);
10958                         return -ENOTSUP;
10959                 }
10960         }
10961         return 0;
10962 }
10963
10964 /*
10965  * i40e_dcb_setup - setup dcb related config
10966  * @dev: device being configured
10967  *
10968  * Returns 0 on success, negative value on failure
10969  */
10970 static int
10971 i40e_dcb_setup(struct rte_eth_dev *dev)
10972 {
10973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10974         struct i40e_dcbx_config dcb_cfg;
10975         uint8_t tc_map = 0;
10976         int ret = 0;
10977
10978         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10979                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10980                 return -ENOTSUP;
10981         }
10982
10983         if (pf->vf_num != 0)
10984                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10985
10986         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10987         if (ret) {
10988                 PMD_INIT_LOG(ERR, "invalid dcb config");
10989                 return -EINVAL;
10990         }
10991         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10992         if (ret) {
10993                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10994                 return -ENOSYS;
10995         }
10996
10997         return 0;
10998 }
10999
11000 static int
11001 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11002                       struct rte_eth_dcb_info *dcb_info)
11003 {
11004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11006         struct i40e_vsi *vsi = pf->main_vsi;
11007         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11008         uint16_t bsf, tc_mapping;
11009         int i, j = 0;
11010
11011         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11012                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11013         else
11014                 dcb_info->nb_tcs = 1;
11015         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11016                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11017         for (i = 0; i < dcb_info->nb_tcs; i++)
11018                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11019
11020         /* get queue mapping if vmdq is disabled */
11021         if (!pf->nb_cfg_vmdq_vsi) {
11022                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11023                         if (!(vsi->enabled_tc & (1 << i)))
11024                                 continue;
11025                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11026                         dcb_info->tc_queue.tc_rxq[j][i].base =
11027                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11028                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11029                         dcb_info->tc_queue.tc_txq[j][i].base =
11030                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11031                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11032                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11033                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11034                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11035                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11036                 }
11037                 return 0;
11038         }
11039
11040         /* get queue mapping if vmdq is enabled */
11041         do {
11042                 vsi = pf->vmdq[j].vsi;
11043                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11044                         if (!(vsi->enabled_tc & (1 << i)))
11045                                 continue;
11046                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11047                         dcb_info->tc_queue.tc_rxq[j][i].base =
11048                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11049                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11050                         dcb_info->tc_queue.tc_txq[j][i].base =
11051                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11052                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11053                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11054                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11055                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11056                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11057                 }
11058                 j++;
11059         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11060         return 0;
11061 }
11062
11063 static int
11064 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11065 {
11066         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11067         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11069         uint16_t msix_intr;
11070
11071         msix_intr = intr_handle->intr_vec[queue_id];
11072         if (msix_intr == I40E_MISC_VEC_ID)
11073                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11074                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11075                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11076                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11077         else
11078                 I40E_WRITE_REG(hw,
11079                                I40E_PFINT_DYN_CTLN(msix_intr -
11080                                                    I40E_RX_VEC_START),
11081                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11082                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11083                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11084
11085         I40E_WRITE_FLUSH(hw);
11086         rte_intr_ack(&pci_dev->intr_handle);
11087
11088         return 0;
11089 }
11090
11091 static int
11092 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11093 {
11094         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11095         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11097         uint16_t msix_intr;
11098
11099         msix_intr = intr_handle->intr_vec[queue_id];
11100         if (msix_intr == I40E_MISC_VEC_ID)
11101                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11102                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11103         else
11104                 I40E_WRITE_REG(hw,
11105                                I40E_PFINT_DYN_CTLN(msix_intr -
11106                                                    I40E_RX_VEC_START),
11107                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11108         I40E_WRITE_FLUSH(hw);
11109
11110         return 0;
11111 }
11112
11113 /**
11114  * This function is used to check if the register is valid.
11115  * Below is the valid registers list for X722 only:
11116  * 0x2b800--0x2bb00
11117  * 0x38700--0x38a00
11118  * 0x3d800--0x3db00
11119  * 0x208e00--0x209000
11120  * 0x20be00--0x20c000
11121  * 0x263c00--0x264000
11122  * 0x265c00--0x266000
11123  */
11124 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11125 {
11126         if ((type != I40E_MAC_X722) &&
11127             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11128              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11129              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11130              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11131              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11132              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11133              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11134                 return 0;
11135         else
11136                 return 1;
11137 }
11138
11139 static int i40e_get_regs(struct rte_eth_dev *dev,
11140                          struct rte_dev_reg_info *regs)
11141 {
11142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11143         uint32_t *ptr_data = regs->data;
11144         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11145         const struct i40e_reg_info *reg_info;
11146
11147         if (ptr_data == NULL) {
11148                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11149                 regs->width = sizeof(uint32_t);
11150                 return 0;
11151         }
11152
11153         /* The first few registers have to be read using AQ operations */
11154         reg_idx = 0;
11155         while (i40e_regs_adminq[reg_idx].name) {
11156                 reg_info = &i40e_regs_adminq[reg_idx++];
11157                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11158                         for (arr_idx2 = 0;
11159                                         arr_idx2 <= reg_info->count2;
11160                                         arr_idx2++) {
11161                                 reg_offset = arr_idx * reg_info->stride1 +
11162                                         arr_idx2 * reg_info->stride2;
11163                                 reg_offset += reg_info->base_addr;
11164                                 ptr_data[reg_offset >> 2] =
11165                                         i40e_read_rx_ctl(hw, reg_offset);
11166                         }
11167         }
11168
11169         /* The remaining registers can be read using primitives */
11170         reg_idx = 0;
11171         while (i40e_regs_others[reg_idx].name) {
11172                 reg_info = &i40e_regs_others[reg_idx++];
11173                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11174                         for (arr_idx2 = 0;
11175                                         arr_idx2 <= reg_info->count2;
11176                                         arr_idx2++) {
11177                                 reg_offset = arr_idx * reg_info->stride1 +
11178                                         arr_idx2 * reg_info->stride2;
11179                                 reg_offset += reg_info->base_addr;
11180                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11181                                         ptr_data[reg_offset >> 2] = 0;
11182                                 else
11183                                         ptr_data[reg_offset >> 2] =
11184                                                 I40E_READ_REG(hw, reg_offset);
11185                         }
11186         }
11187
11188         return 0;
11189 }
11190
11191 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11192 {
11193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11194
11195         /* Convert word count to byte count */
11196         return hw->nvm.sr_size << 1;
11197 }
11198
11199 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11200                            struct rte_dev_eeprom_info *eeprom)
11201 {
11202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11203         uint16_t *data = eeprom->data;
11204         uint16_t offset, length, cnt_words;
11205         int ret_code;
11206
11207         offset = eeprom->offset >> 1;
11208         length = eeprom->length >> 1;
11209         cnt_words = length;
11210
11211         if (offset > hw->nvm.sr_size ||
11212                 offset + length > hw->nvm.sr_size) {
11213                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11214                 return -EINVAL;
11215         }
11216
11217         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11218
11219         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11220         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11221                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11222                 return -EIO;
11223         }
11224
11225         return 0;
11226 }
11227
11228 static int i40e_get_module_info(struct rte_eth_dev *dev,
11229                                 struct rte_eth_dev_module_info *modinfo)
11230 {
11231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11232         uint32_t sff8472_comp = 0;
11233         uint32_t sff8472_swap = 0;
11234         uint32_t sff8636_rev = 0;
11235         i40e_status status;
11236         uint32_t type = 0;
11237
11238         /* Check if firmware supports reading module EEPROM. */
11239         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11240                 PMD_DRV_LOG(ERR,
11241                             "Module EEPROM memory read not supported. "
11242                             "Please update the NVM image.\n");
11243                 return -EINVAL;
11244         }
11245
11246         status = i40e_update_link_info(hw);
11247         if (status)
11248                 return -EIO;
11249
11250         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11251                 PMD_DRV_LOG(ERR,
11252                             "Cannot read module EEPROM memory. "
11253                             "No module connected.\n");
11254                 return -EINVAL;
11255         }
11256
11257         type = hw->phy.link_info.module_type[0];
11258
11259         switch (type) {
11260         case I40E_MODULE_TYPE_SFP:
11261                 status = i40e_aq_get_phy_register(hw,
11262                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11263                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11264                                 I40E_MODULE_SFF_8472_COMP,
11265                                 &sff8472_comp, NULL);
11266                 if (status)
11267                         return -EIO;
11268
11269                 status = i40e_aq_get_phy_register(hw,
11270                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11271                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11272                                 I40E_MODULE_SFF_8472_SWAP,
11273                                 &sff8472_swap, NULL);
11274                 if (status)
11275                         return -EIO;
11276
11277                 /* Check if the module requires address swap to access
11278                  * the other EEPROM memory page.
11279                  */
11280                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11281                         PMD_DRV_LOG(WARNING,
11282                                     "Module address swap to access "
11283                                     "page 0xA2 is not supported.\n");
11284                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11285                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11286                 } else if (sff8472_comp == 0x00) {
11287                         /* Module is not SFF-8472 compliant */
11288                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11289                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11290                 } else {
11291                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11292                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11293                 }
11294                 break;
11295         case I40E_MODULE_TYPE_QSFP_PLUS:
11296                 /* Read from memory page 0. */
11297                 status = i40e_aq_get_phy_register(hw,
11298                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11299                                 0, 1,
11300                                 I40E_MODULE_REVISION_ADDR,
11301                                 &sff8636_rev, NULL);
11302                 if (status)
11303                         return -EIO;
11304                 /* Determine revision compliance byte */
11305                 if (sff8636_rev > 0x02) {
11306                         /* Module is SFF-8636 compliant */
11307                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11308                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11309                 } else {
11310                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11311                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11312                 }
11313                 break;
11314         case I40E_MODULE_TYPE_QSFP28:
11315                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11316                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11317                 break;
11318         default:
11319                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11320                 return -EINVAL;
11321         }
11322         return 0;
11323 }
11324
11325 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11326                                   struct rte_dev_eeprom_info *info)
11327 {
11328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11329         bool is_sfp = false;
11330         i40e_status status;
11331         uint8_t *data;
11332         uint32_t value = 0;
11333         uint32_t i;
11334
11335         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11336                 is_sfp = true;
11337
11338         data = info->data;
11339         for (i = 0; i < info->length; i++) {
11340                 u32 offset = i + info->offset;
11341                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11342
11343                 /* Check if we need to access the other memory page */
11344                 if (is_sfp) {
11345                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11346                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11347                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11348                         }
11349                 } else {
11350                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11351                                 /* Compute memory page number and offset. */
11352                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11353                                 addr++;
11354                         }
11355                 }
11356                 status = i40e_aq_get_phy_register(hw,
11357                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11358                                 addr, 1, offset, &value, NULL);
11359                 if (status)
11360                         return -EIO;
11361                 data[i] = (uint8_t)value;
11362         }
11363         return 0;
11364 }
11365
11366 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11367                                      struct rte_ether_addr *mac_addr)
11368 {
11369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11371         struct i40e_vsi *vsi = pf->main_vsi;
11372         struct i40e_mac_filter_info mac_filter;
11373         struct i40e_mac_filter *f;
11374         int ret;
11375
11376         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11377                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11378                 return -EINVAL;
11379         }
11380
11381         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11382                 if (rte_is_same_ether_addr(&pf->dev_addr,
11383                                                 &f->mac_info.mac_addr))
11384                         break;
11385         }
11386
11387         if (f == NULL) {
11388                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11389                 return -EIO;
11390         }
11391
11392         mac_filter = f->mac_info;
11393         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11394         if (ret != I40E_SUCCESS) {
11395                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11396                 return -EIO;
11397         }
11398         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11399         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11400         if (ret != I40E_SUCCESS) {
11401                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11402                 return -EIO;
11403         }
11404         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11405
11406         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11407                                         mac_addr->addr_bytes, NULL);
11408         if (ret != I40E_SUCCESS) {
11409                 PMD_DRV_LOG(ERR, "Failed to change mac");
11410                 return -EIO;
11411         }
11412
11413         return 0;
11414 }
11415
11416 static int
11417 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11418 {
11419         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11420         struct rte_eth_dev_data *dev_data = pf->dev_data;
11421         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11422         int ret = 0;
11423
11424         /* check if mtu is within the allowed range */
11425         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11426                 return -EINVAL;
11427
11428         /* mtu setting is forbidden if port is start */
11429         if (dev_data->dev_started) {
11430                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11431                             dev_data->port_id);
11432                 return -EBUSY;
11433         }
11434
11435         if (frame_size > I40E_ETH_MAX_LEN)
11436                 dev_data->dev_conf.rxmode.offloads |=
11437                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11438         else
11439                 dev_data->dev_conf.rxmode.offloads &=
11440                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11441
11442         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11443
11444         return ret;
11445 }
11446
11447 /* Restore ethertype filter */
11448 static void
11449 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11450 {
11451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11452         struct i40e_ethertype_filter_list
11453                 *ethertype_list = &pf->ethertype.ethertype_list;
11454         struct i40e_ethertype_filter *f;
11455         struct i40e_control_filter_stats stats;
11456         uint16_t flags;
11457
11458         TAILQ_FOREACH(f, ethertype_list, rules) {
11459                 flags = 0;
11460                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11461                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11462                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11463                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11464                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11465
11466                 memset(&stats, 0, sizeof(stats));
11467                 i40e_aq_add_rem_control_packet_filter(hw,
11468                                             f->input.mac_addr.addr_bytes,
11469                                             f->input.ether_type,
11470                                             flags, pf->main_vsi->seid,
11471                                             f->queue, 1, &stats, NULL);
11472         }
11473         PMD_DRV_LOG(INFO, "Ethertype filter:"
11474                     " mac_etype_used = %u, etype_used = %u,"
11475                     " mac_etype_free = %u, etype_free = %u",
11476                     stats.mac_etype_used, stats.etype_used,
11477                     stats.mac_etype_free, stats.etype_free);
11478 }
11479
11480 /* Restore tunnel filter */
11481 static void
11482 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11483 {
11484         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11485         struct i40e_vsi *vsi;
11486         struct i40e_pf_vf *vf;
11487         struct i40e_tunnel_filter_list
11488                 *tunnel_list = &pf->tunnel.tunnel_list;
11489         struct i40e_tunnel_filter *f;
11490         struct i40e_aqc_cloud_filters_element_bb cld_filter;
11491         bool big_buffer = 0;
11492
11493         TAILQ_FOREACH(f, tunnel_list, rules) {
11494                 if (!f->is_to_vf)
11495                         vsi = pf->main_vsi;
11496                 else {
11497                         vf = &pf->vfs[f->vf_id];
11498                         vsi = vf->vsi;
11499                 }
11500                 memset(&cld_filter, 0, sizeof(cld_filter));
11501                 rte_ether_addr_copy((struct rte_ether_addr *)
11502                                 &f->input.outer_mac,
11503                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11504                 rte_ether_addr_copy((struct rte_ether_addr *)
11505                                 &f->input.inner_mac,
11506                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11507                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11508                 cld_filter.element.flags = f->input.flags;
11509                 cld_filter.element.tenant_id = f->input.tenant_id;
11510                 cld_filter.element.queue_number = f->queue;
11511                 rte_memcpy(cld_filter.general_fields,
11512                            f->input.general_fields,
11513                            sizeof(f->input.general_fields));
11514
11515                 if (((f->input.flags &
11516                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11517                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11518                     ((f->input.flags &
11519                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11520                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11521                     ((f->input.flags &
11522                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11523                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11524                         big_buffer = 1;
11525
11526                 if (big_buffer)
11527                         i40e_aq_add_cloud_filters_bb(hw,
11528                                         vsi->seid, &cld_filter, 1);
11529                 else
11530                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11531                                                   &cld_filter.element, 1);
11532         }
11533 }
11534
11535 static void
11536 i40e_filter_restore(struct i40e_pf *pf)
11537 {
11538         i40e_ethertype_filter_restore(pf);
11539         i40e_tunnel_filter_restore(pf);
11540         i40e_fdir_filter_restore(pf);
11541         (void)i40e_hash_filter_restore(pf);
11542 }
11543
11544 bool
11545 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11546 {
11547         if (strcmp(dev->device->driver->name, drv->driver.name))
11548                 return false;
11549
11550         return true;
11551 }
11552
11553 bool
11554 is_i40e_supported(struct rte_eth_dev *dev)
11555 {
11556         return is_device_supported(dev, &rte_i40e_pmd);
11557 }
11558
11559 struct i40e_customized_pctype*
11560 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11561 {
11562         int i;
11563
11564         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11565                 if (pf->customized_pctype[i].index == index)
11566                         return &pf->customized_pctype[i];
11567         }
11568         return NULL;
11569 }
11570
11571 static int
11572 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11573                               uint32_t pkg_size, uint32_t proto_num,
11574                               struct rte_pmd_i40e_proto_info *proto,
11575                               enum rte_pmd_i40e_package_op op)
11576 {
11577         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11578         uint32_t pctype_num;
11579         struct rte_pmd_i40e_ptype_info *pctype;
11580         uint32_t buff_size;
11581         struct i40e_customized_pctype *new_pctype = NULL;
11582         uint8_t proto_id;
11583         uint8_t pctype_value;
11584         char name[64];
11585         uint32_t i, j, n;
11586         int ret;
11587
11588         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11589             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11590                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11591                 return -1;
11592         }
11593
11594         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11595                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11596                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11597         if (ret) {
11598                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11599                 return -1;
11600         }
11601         if (!pctype_num) {
11602                 PMD_DRV_LOG(INFO, "No new pctype added");
11603                 return -1;
11604         }
11605
11606         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11607         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11608         if (!pctype) {
11609                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11610                 return -1;
11611         }
11612         /* get information about new pctype list */
11613         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11614                                         (uint8_t *)pctype, buff_size,
11615                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11616         if (ret) {
11617                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11618                 rte_free(pctype);
11619                 return -1;
11620         }
11621
11622         /* Update customized pctype. */
11623         for (i = 0; i < pctype_num; i++) {
11624                 pctype_value = pctype[i].ptype_id;
11625                 memset(name, 0, sizeof(name));
11626                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11627                         proto_id = pctype[i].protocols[j];
11628                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11629                                 continue;
11630                         for (n = 0; n < proto_num; n++) {
11631                                 if (proto[n].proto_id != proto_id)
11632                                         continue;
11633                                 strlcat(name, proto[n].name, sizeof(name));
11634                                 strlcat(name, "_", sizeof(name));
11635                                 break;
11636                         }
11637                 }
11638                 name[strlen(name) - 1] = '\0';
11639                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11640                 if (!strcmp(name, "GTPC"))
11641                         new_pctype =
11642                                 i40e_find_customized_pctype(pf,
11643                                                       I40E_CUSTOMIZED_GTPC);
11644                 else if (!strcmp(name, "GTPU_IPV4"))
11645                         new_pctype =
11646                                 i40e_find_customized_pctype(pf,
11647                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11648                 else if (!strcmp(name, "GTPU_IPV6"))
11649                         new_pctype =
11650                                 i40e_find_customized_pctype(pf,
11651                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11652                 else if (!strcmp(name, "GTPU"))
11653                         new_pctype =
11654                                 i40e_find_customized_pctype(pf,
11655                                                       I40E_CUSTOMIZED_GTPU);
11656                 else if (!strcmp(name, "IPV4_L2TPV3"))
11657                         new_pctype =
11658                                 i40e_find_customized_pctype(pf,
11659                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
11660                 else if (!strcmp(name, "IPV6_L2TPV3"))
11661                         new_pctype =
11662                                 i40e_find_customized_pctype(pf,
11663                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
11664                 else if (!strcmp(name, "IPV4_ESP"))
11665                         new_pctype =
11666                                 i40e_find_customized_pctype(pf,
11667                                                 I40E_CUSTOMIZED_ESP_IPV4);
11668                 else if (!strcmp(name, "IPV6_ESP"))
11669                         new_pctype =
11670                                 i40e_find_customized_pctype(pf,
11671                                                 I40E_CUSTOMIZED_ESP_IPV6);
11672                 else if (!strcmp(name, "IPV4_UDP_ESP"))
11673                         new_pctype =
11674                                 i40e_find_customized_pctype(pf,
11675                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
11676                 else if (!strcmp(name, "IPV6_UDP_ESP"))
11677                         new_pctype =
11678                                 i40e_find_customized_pctype(pf,
11679                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
11680                 else if (!strcmp(name, "IPV4_AH"))
11681                         new_pctype =
11682                                 i40e_find_customized_pctype(pf,
11683                                                 I40E_CUSTOMIZED_AH_IPV4);
11684                 else if (!strcmp(name, "IPV6_AH"))
11685                         new_pctype =
11686                                 i40e_find_customized_pctype(pf,
11687                                                 I40E_CUSTOMIZED_AH_IPV6);
11688                 if (new_pctype) {
11689                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11690                                 new_pctype->pctype = pctype_value;
11691                                 new_pctype->valid = true;
11692                         } else {
11693                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11694                                 new_pctype->valid = false;
11695                         }
11696                 }
11697         }
11698
11699         rte_free(pctype);
11700         return 0;
11701 }
11702
11703 static int
11704 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11705                              uint32_t pkg_size, uint32_t proto_num,
11706                              struct rte_pmd_i40e_proto_info *proto,
11707                              enum rte_pmd_i40e_package_op op)
11708 {
11709         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11710         uint16_t port_id = dev->data->port_id;
11711         uint32_t ptype_num;
11712         struct rte_pmd_i40e_ptype_info *ptype;
11713         uint32_t buff_size;
11714         uint8_t proto_id;
11715         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11716         uint32_t i, j, n;
11717         bool in_tunnel;
11718         int ret;
11719
11720         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11721             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11722                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11723                 return -1;
11724         }
11725
11726         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11727                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11728                 return 0;
11729         }
11730
11731         /* get information about new ptype num */
11732         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11733                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11734                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11735         if (ret) {
11736                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11737                 return ret;
11738         }
11739         if (!ptype_num) {
11740                 PMD_DRV_LOG(INFO, "No new ptype added");
11741                 return -1;
11742         }
11743
11744         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11745         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11746         if (!ptype) {
11747                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11748                 return -1;
11749         }
11750
11751         /* get information about new ptype list */
11752         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11753                                         (uint8_t *)ptype, buff_size,
11754                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11755         if (ret) {
11756                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11757                 rte_free(ptype);
11758                 return ret;
11759         }
11760
11761         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11762         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11763         if (!ptype_mapping) {
11764                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11765                 rte_free(ptype);
11766                 return -1;
11767         }
11768
11769         /* Update ptype mapping table. */
11770         for (i = 0; i < ptype_num; i++) {
11771                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11772                 ptype_mapping[i].sw_ptype = 0;
11773                 in_tunnel = false;
11774                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11775                         proto_id = ptype[i].protocols[j];
11776                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11777                                 continue;
11778                         for (n = 0; n < proto_num; n++) {
11779                                 if (proto[n].proto_id != proto_id)
11780                                         continue;
11781                                 memset(name, 0, sizeof(name));
11782                                 strcpy(name, proto[n].name);
11783                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11784                                 if (!strncasecmp(name, "PPPOE", 5))
11785                                         ptype_mapping[i].sw_ptype |=
11786                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11787                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11788                                          !in_tunnel) {
11789                                         ptype_mapping[i].sw_ptype |=
11790                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11791                                         ptype_mapping[i].sw_ptype |=
11792                                                 RTE_PTYPE_L4_FRAG;
11793                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11794                                            in_tunnel) {
11795                                         ptype_mapping[i].sw_ptype |=
11796                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11797                                         ptype_mapping[i].sw_ptype |=
11798                                                 RTE_PTYPE_INNER_L4_FRAG;
11799                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11800                                         ptype_mapping[i].sw_ptype |=
11801                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11802                                         in_tunnel = true;
11803                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11804                                            !in_tunnel)
11805                                         ptype_mapping[i].sw_ptype |=
11806                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11807                                 else if (!strncasecmp(name, "IPV4", 4) &&
11808                                          in_tunnel)
11809                                         ptype_mapping[i].sw_ptype |=
11810                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11811                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11812                                          !in_tunnel) {
11813                                         ptype_mapping[i].sw_ptype |=
11814                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11815                                         ptype_mapping[i].sw_ptype |=
11816                                                 RTE_PTYPE_L4_FRAG;
11817                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11818                                            in_tunnel) {
11819                                         ptype_mapping[i].sw_ptype |=
11820                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11821                                         ptype_mapping[i].sw_ptype |=
11822                                                 RTE_PTYPE_INNER_L4_FRAG;
11823                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11824                                         ptype_mapping[i].sw_ptype |=
11825                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11826                                         in_tunnel = true;
11827                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11828                                            !in_tunnel)
11829                                         ptype_mapping[i].sw_ptype |=
11830                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11831                                 else if (!strncasecmp(name, "IPV6", 4) &&
11832                                          in_tunnel)
11833                                         ptype_mapping[i].sw_ptype |=
11834                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11835                                 else if (!strncasecmp(name, "UDP", 3) &&
11836                                          !in_tunnel)
11837                                         ptype_mapping[i].sw_ptype |=
11838                                                 RTE_PTYPE_L4_UDP;
11839                                 else if (!strncasecmp(name, "UDP", 3) &&
11840                                          in_tunnel)
11841                                         ptype_mapping[i].sw_ptype |=
11842                                                 RTE_PTYPE_INNER_L4_UDP;
11843                                 else if (!strncasecmp(name, "TCP", 3) &&
11844                                          !in_tunnel)
11845                                         ptype_mapping[i].sw_ptype |=
11846                                                 RTE_PTYPE_L4_TCP;
11847                                 else if (!strncasecmp(name, "TCP", 3) &&
11848                                          in_tunnel)
11849                                         ptype_mapping[i].sw_ptype |=
11850                                                 RTE_PTYPE_INNER_L4_TCP;
11851                                 else if (!strncasecmp(name, "SCTP", 4) &&
11852                                          !in_tunnel)
11853                                         ptype_mapping[i].sw_ptype |=
11854                                                 RTE_PTYPE_L4_SCTP;
11855                                 else if (!strncasecmp(name, "SCTP", 4) &&
11856                                          in_tunnel)
11857                                         ptype_mapping[i].sw_ptype |=
11858                                                 RTE_PTYPE_INNER_L4_SCTP;
11859                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11860                                           !strncasecmp(name, "ICMPV6", 6)) &&
11861                                          !in_tunnel)
11862                                         ptype_mapping[i].sw_ptype |=
11863                                                 RTE_PTYPE_L4_ICMP;
11864                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11865                                           !strncasecmp(name, "ICMPV6", 6)) &&
11866                                          in_tunnel)
11867                                         ptype_mapping[i].sw_ptype |=
11868                                                 RTE_PTYPE_INNER_L4_ICMP;
11869                                 else if (!strncasecmp(name, "GTPC", 4)) {
11870                                         ptype_mapping[i].sw_ptype |=
11871                                                 RTE_PTYPE_TUNNEL_GTPC;
11872                                         in_tunnel = true;
11873                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11874                                         ptype_mapping[i].sw_ptype |=
11875                                                 RTE_PTYPE_TUNNEL_GTPU;
11876                                         in_tunnel = true;
11877                                 } else if (!strncasecmp(name, "ESP", 3)) {
11878                                         ptype_mapping[i].sw_ptype |=
11879                                                 RTE_PTYPE_TUNNEL_ESP;
11880                                         in_tunnel = true;
11881                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11882                                         ptype_mapping[i].sw_ptype |=
11883                                                 RTE_PTYPE_TUNNEL_GRENAT;
11884                                         in_tunnel = true;
11885                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
11886                                            !strncasecmp(name, "L2TPV2", 6) ||
11887                                            !strncasecmp(name, "L2TPV3", 6)) {
11888                                         ptype_mapping[i].sw_ptype |=
11889                                                 RTE_PTYPE_TUNNEL_L2TP;
11890                                         in_tunnel = true;
11891                                 }
11892
11893                                 break;
11894                         }
11895                 }
11896         }
11897
11898         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11899                                                 ptype_num, 0);
11900         if (ret)
11901                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
11902
11903         rte_free(ptype_mapping);
11904         rte_free(ptype);
11905         return ret;
11906 }
11907
11908 void
11909 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11910                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11911 {
11912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11913         uint32_t proto_num;
11914         struct rte_pmd_i40e_proto_info *proto;
11915         uint32_t buff_size;
11916         uint32_t i;
11917         int ret;
11918
11919         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11920             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11921                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11922                 return;
11923         }
11924
11925         /* get information about protocol number */
11926         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11927                                        (uint8_t *)&proto_num, sizeof(proto_num),
11928                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11929         if (ret) {
11930                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11931                 return;
11932         }
11933         if (!proto_num) {
11934                 PMD_DRV_LOG(INFO, "No new protocol added");
11935                 return;
11936         }
11937
11938         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11939         proto = rte_zmalloc("new_proto", buff_size, 0);
11940         if (!proto) {
11941                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11942                 return;
11943         }
11944
11945         /* get information about protocol list */
11946         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11947                                         (uint8_t *)proto, buff_size,
11948                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11949         if (ret) {
11950                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11951                 rte_free(proto);
11952                 return;
11953         }
11954
11955         /* Check if GTP is supported. */
11956         for (i = 0; i < proto_num; i++) {
11957                 if (!strncmp(proto[i].name, "GTP", 3)) {
11958                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11959                                 pf->gtp_support = true;
11960                         else
11961                                 pf->gtp_support = false;
11962                         break;
11963                 }
11964         }
11965
11966         /* Check if ESP is supported. */
11967         for (i = 0; i < proto_num; i++) {
11968                 if (!strncmp(proto[i].name, "ESP", 3)) {
11969                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11970                                 pf->esp_support = true;
11971                         else
11972                                 pf->esp_support = false;
11973                         break;
11974                 }
11975         }
11976
11977         /* Update customized pctype info */
11978         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11979                                             proto_num, proto, op);
11980         if (ret)
11981                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11982
11983         /* Update customized ptype info */
11984         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11985                                            proto_num, proto, op);
11986         if (ret)
11987                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11988
11989         rte_free(proto);
11990 }
11991
11992 /* Create a QinQ cloud filter
11993  *
11994  * The Fortville NIC has limited resources for tunnel filters,
11995  * so we can only reuse existing filters.
11996  *
11997  * In step 1 we define which Field Vector fields can be used for
11998  * filter types.
11999  * As we do not have the inner tag defined as a field,
12000  * we have to define it first, by reusing one of L1 entries.
12001  *
12002  * In step 2 we are replacing one of existing filter types with
12003  * a new one for QinQ.
12004  * As we reusing L1 and replacing L2, some of the default filter
12005  * types will disappear,which depends on L1 and L2 entries we reuse.
12006  *
12007  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12008  *
12009  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12010  *              later when we define the cloud filter.
12011  *      a.      Valid_flags.replace_cloud = 0
12012  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12013  *      c.      New_filter = 0x10
12014  *      d.      TR bit = 0xff (optional, not used here)
12015  *      e.      Buffer – 2 entries:
12016  *              i.      Byte 0 = 8 (outer vlan FV index).
12017  *                      Byte 1 = 0 (rsv)
12018  *                      Byte 2-3 = 0x0fff
12019  *              ii.     Byte 0 = 37 (inner vlan FV index).
12020  *                      Byte 1 =0 (rsv)
12021  *                      Byte 2-3 = 0x0fff
12022  *
12023  * Step 2:
12024  * 2.   Create cloud filter using two L1 filters entries: stag and
12025  *              new filter(outer vlan+ inner vlan)
12026  *      a.      Valid_flags.replace_cloud = 1
12027  *      b.      Old_filter = 1 (instead of outer IP)
12028  *      c.      New_filter = 0x10
12029  *      d.      Buffer – 2 entries:
12030  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12031  *                      Byte 1-3 = 0 (rsv)
12032  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12033  *                      Byte 9-11 = 0 (rsv)
12034  */
12035 static int
12036 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12037 {
12038         int ret = -ENOTSUP;
12039         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12040         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12041         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12042         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
12043
12044         if (pf->support_multi_driver) {
12045                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12046                 return ret;
12047         }
12048
12049         /* Init */
12050         memset(&filter_replace, 0,
12051                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12052         memset(&filter_replace_buf, 0,
12053                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12054
12055         /* create L1 filter */
12056         filter_replace.old_filter_type =
12057                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12058         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12059         filter_replace.tr_bit = 0;
12060
12061         /* Prepare the buffer, 2 entries */
12062         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12063         filter_replace_buf.data[0] |=
12064                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12065         /* Field Vector 12b mask */
12066         filter_replace_buf.data[2] = 0xff;
12067         filter_replace_buf.data[3] = 0x0f;
12068         filter_replace_buf.data[4] =
12069                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12070         filter_replace_buf.data[4] |=
12071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12072         /* Field Vector 12b mask */
12073         filter_replace_buf.data[6] = 0xff;
12074         filter_replace_buf.data[7] = 0x0f;
12075         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12076                         &filter_replace_buf);
12077         if (ret != I40E_SUCCESS)
12078                 return ret;
12079
12080         if (filter_replace.old_filter_type !=
12081             filter_replace.new_filter_type)
12082                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12083                             " original: 0x%x, new: 0x%x",
12084                             dev->device->name,
12085                             filter_replace.old_filter_type,
12086                             filter_replace.new_filter_type);
12087
12088         /* Apply the second L2 cloud filter */
12089         memset(&filter_replace, 0,
12090                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12091         memset(&filter_replace_buf, 0,
12092                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12093
12094         /* create L2 filter, input for L2 filter will be L1 filter  */
12095         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12096         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12097         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12098
12099         /* Prepare the buffer, 2 entries */
12100         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12101         filter_replace_buf.data[0] |=
12102                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12103         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12104         filter_replace_buf.data[4] |=
12105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12106         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12107                         &filter_replace_buf);
12108         if (!ret && (filter_replace.old_filter_type !=
12109                      filter_replace.new_filter_type))
12110                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12111                             " original: 0x%x, new: 0x%x",
12112                             dev->device->name,
12113                             filter_replace.old_filter_type,
12114                             filter_replace.new_filter_type);
12115
12116         return ret;
12117 }
12118
12119 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12120 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12121 #ifdef RTE_ETHDEV_DEBUG_RX
12122 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12123 #endif
12124 #ifdef RTE_ETHDEV_DEBUG_TX
12125 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12126 #endif
12127
12128 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12129                               ETH_I40E_FLOATING_VEB_ARG "=1"
12130                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12131                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12132                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");