drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518         .tm_ops_get                   = i40e_tm_ops_get,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         unsigned offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 535         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 536         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 537         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 538 };
 539
 540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 541                 sizeof(rte_i40e_stats_strings[0]))
 542
 543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 544         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 545                 tx_dropped_link_down)},
 546         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 547         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 548                 illegal_bytes)},
 549         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 550         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_local_faults)},
 552         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_remote_faults)},
 554         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_length_errors)},
 556         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 557         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 558         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 559         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 560         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 561         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_127)},
 563         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_255)},
 565         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_511)},
 567         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1023)},
 569         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1522)},
 571         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_big)},
 573         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_undersize)},
 575         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_oversize)},
 577         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 578                 mac_short_packet_dropped)},
 579         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_fragments)},
 581         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 582         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 583         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_127)},
 585         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_255)},
 587         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_511)},
 589         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1023)},
 591         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1522)},
 593         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_big)},
 595         {"rx_flow_director_atr_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 597         {"rx_flow_director_sb_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 599         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_status)},
 601         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_status)},
 603         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_count)},
 605         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_count)},
 607 };
 608
 609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 610                 sizeof(rte_i40e_hw_port_strings[0]))
 611
 612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 613         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xon_rx)},
 615         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xoff_rx)},
 617 };
 618
 619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 620                 sizeof(rte_i40e_rxq_prio_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_tx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_tx)},
 627         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_2_xoff)},
 629 };
 630
 631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 632                 sizeof(rte_i40e_txq_prio_strings[0]))
 633
 634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         return rte_eth_dev_pci_generic_probe(pci_dev,
 638                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 639 }
 640
 641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 642 {
 643         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 644 }
 645
 646 static struct rte_pci_driver rte_i40e_pmd = {
 647         .id_table = pci_id_i40e_map,
 648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 649         .probe = eth_i40e_pci_probe,
 650         .remove = eth_i40e_pci_remove,
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691 #ifndef I40E_GLQF_L3_MAP
 692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 693 #endif
 694
 695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 696 {
 697         /*
 698          * Initialize registers for flexible payload, which should be set by NVM.
 699          * This should be removed from code once it is fixed in NVM.
 700          */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 712         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 713
 714         /* Initialize registers for parsing packet type of QinQ */
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 717 }
 718
 719 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 720
 721 /*
 722  * Add a ethertype filter to drop all flow control frames transmitted
 723  * from VSIs.
 724 */
 725 static void
 726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 727 {
 728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 729         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 731                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 732         int ret;
 733
 734         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 735                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 736                                 pf->main_vsi_seid, 0,
 737                                 TRUE, NULL, NULL);
 738         if (ret)
 739                 PMD_INIT_LOG(ERR,
 740                         "Failed to add filter to drop flow control frames from VSIs.");
 741 }
 742
 743 static int
 744 floating_veb_list_handler(__rte_unused const char *key,
 745                           const char *floating_veb_value,
 746                           void *opaque)
 747 {
 748         int idx = 0;
 749         unsigned int count = 0;
 750         char *end = NULL;
 751         int min, max;
 752         bool *vf_floating_veb = opaque;
 753
 754         while (isblank(*floating_veb_value))
 755                 floating_veb_value++;
 756
 757         /* Reset floating VEB configuration for VFs */
 758         for (idx = 0; idx < I40E_MAX_VF; idx++)
 759                 vf_floating_veb[idx] = false;
 760
 761         min = I40E_MAX_VF;
 762         do {
 763                 while (isblank(*floating_veb_value))
 764                         floating_veb_value++;
 765                 if (*floating_veb_value == '\0')
 766                         return -1;
 767                 errno = 0;
 768                 idx = strtoul(floating_veb_value, &end, 10);
 769                 if (errno || end == NULL)
 770                         return -1;
 771                 while (isblank(*end))
 772                         end++;
 773                 if (*end == '-') {
 774                         min = idx;
 775                 } else if ((*end == ';') || (*end == '\0')) {
 776                         max = idx;
 777                         if (min == I40E_MAX_VF)
 778                                 min = idx;
 779                         if (max >= I40E_MAX_VF)
 780                                 max = I40E_MAX_VF - 1;
 781                         for (idx = min; idx <= max; idx++) {
 782                                 vf_floating_veb[idx] = true;
 783                                 count++;
 784                         }
 785                         min = I40E_MAX_VF;
 786                 } else {
 787                         return -1;
 788                 }
 789                 floating_veb_value = end + 1;
 790         } while (*end != '\0');
 791
 792         if (count == 0)
 793                 return -1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 config_vf_floating_veb(struct rte_devargs *devargs,
 800                        uint16_t floating_veb,
 801                        bool *vf_floating_veb)
 802 {
 803         struct rte_kvargs *kvlist;
 804         int i;
 805         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 806
 807         if (!floating_veb)
 808                 return;
 809         /* All the VFs attach to the floating VEB by default
 810          * when the floating VEB is enabled.
 811          */
 812         for (i = 0; i < I40E_MAX_VF; i++)
 813                 vf_floating_veb[i] = true;
 814
 815         if (devargs == NULL)
 816                 return;
 817
 818         kvlist = rte_kvargs_parse(devargs->args, NULL);
 819         if (kvlist == NULL)
 820                 return;
 821
 822         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 823                 rte_kvargs_free(kvlist);
 824                 return;
 825         }
 826         /* When the floating_veb_list parameter exists, all the VFs
 827          * will attach to the legacy VEB firstly, then configure VFs
 828          * to the floating VEB according to the floating_veb_list.
 829          */
 830         if (rte_kvargs_process(kvlist, floating_veb_list,
 831                                floating_veb_list_handler,
 832                                vf_floating_veb) < 0) {
 833                 rte_kvargs_free(kvlist);
 834                 return;
 835         }
 836         rte_kvargs_free(kvlist);
 837 }
 838
 839 static int
 840 i40e_check_floating_handler(__rte_unused const char *key,
 841                             const char *value,
 842                             __rte_unused void *opaque)
 843 {
 844         if (strcmp(value, "1"))
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static int
 851 is_floating_veb_supported(struct rte_devargs *devargs)
 852 {
 853         struct rte_kvargs *kvlist;
 854         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 855
 856         if (devargs == NULL)
 857                 return 0;
 858
 859         kvlist = rte_kvargs_parse(devargs->args, NULL);
 860         if (kvlist == NULL)
 861                 return 0;
 862
 863         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         /* Floating VEB is enabled when there's key-value:
 868          * enable_floating_veb=1
 869          */
 870         if (rte_kvargs_process(kvlist, floating_veb_key,
 871                                i40e_check_floating_handler, NULL) < 0) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         rte_kvargs_free(kvlist);
 876
 877         return 1;
 878 }
 879
 880 static void
 881 config_floating_veb(struct rte_eth_dev *dev)
 882 {
 883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886
 887         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 888
 889         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 890                 pf->floating_veb =
 891                         is_floating_veb_supported(pci_dev->device.devargs);
 892                 config_vf_floating_veb(pci_dev->device.devargs,
 893                                        pf->floating_veb,
 894                                        pf->floating_veb_list);
 895         } else {
 896                 pf->floating_veb = false;
 897         }
 898 }
 899
 900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 902
 903 static int
 904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 908         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 909         int ret;
 910
 911         struct rte_hash_parameters ethertype_hash_params = {
 912                 .name = ethertype_hash_name,
 913                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 914                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 915                 .hash_func = rte_hash_crc,
 916                 .hash_func_init_val = 0,
 917                 .socket_id = rte_socket_id(),
 918         };
 919
 920         /* Initialize ethertype filter rule list and hash */
 921         TAILQ_INIT(&ethertype_rule->ethertype_list);
 922         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 923                  "ethertype_%s", dev->device->name);
 924         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 925         if (!ethertype_rule->hash_table) {
 926                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 927                 return -EINVAL;
 928         }
 929         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 930                                        sizeof(struct i40e_ethertype_filter *) *
 931                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 932                                        0);
 933         if (!ethertype_rule->hash_map) {
 934                 PMD_INIT_LOG(ERR,
 935                              "Failed to allocate memory for ethertype hash map!");
 936                 ret = -ENOMEM;
 937                 goto err_ethertype_hash_map_alloc;
 938         }
 939
 940         return 0;
 941
 942 err_ethertype_hash_map_alloc:
 943         rte_hash_free(ethertype_rule->hash_table);
 944
 945         return ret;
 946 }
 947
 948 static int
 949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 953         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters tunnel_hash_params = {
 957                 .name = tunnel_hash_name,
 958                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize tunnel filter rule list and hash */
 966         TAILQ_INIT(&tunnel_rule->tunnel_list);
 967         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 968                  "tunnel_%s", dev->device->name);
 969         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 970         if (!tunnel_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 972                 return -EINVAL;
 973         }
 974         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 975                                     sizeof(struct i40e_tunnel_filter *) *
 976                                     I40E_MAX_TUNNEL_FILTER_NUM,
 977                                     0);
 978         if (!tunnel_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for tunnel hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_tunnel_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_tunnel_hash_map_alloc:
 988         rte_hash_free(tunnel_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_fdir_info *fdir_info = &pf->fdir;
 998         char fdir_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters fdir_hash_params = {
1002                 .name = fdir_hash_name,
1003                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004                 .key_len = sizeof(struct rte_eth_fdir_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize flow director filter rule list and hash */
1011         TAILQ_INIT(&fdir_info->fdir_list);
1012         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013                  "fdir_%s", dev->device->name);
1014         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015         if (!fdir_info->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1017                 return -EINVAL;
1018         }
1019         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020                                           sizeof(struct i40e_fdir_filter *) *
1021                                           I40E_MAX_FDIR_FILTER_NUM,
1022                                           0);
1023         if (!fdir_info->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for fdir hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_fdir_hash_map_alloc;
1028         }
1029         return 0;
1030
1031 err_fdir_hash_map_alloc:
1032         rte_hash_free(fdir_info->hash_table);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 {
1040         struct rte_pci_device *pci_dev;
1041         struct rte_intr_handle *intr_handle;
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         struct i40e_vsi *vsi;
1045         int ret;
1046         uint32_t len;
1047         uint8_t aq_fail = 0;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         dev->dev_ops = &i40e_eth_dev_ops;
1052         dev->rx_pkt_burst = i40e_recv_pkts;
1053         dev->tx_pkt_burst = i40e_xmit_pkts;
1054         dev->tx_pkt_prepare = i40e_prep_pkts;
1055
1056         /* for secondary processes, we don't initialise any further as primary
1057          * has already done this work. Only check we don't need a different
1058          * RX function */
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060                 i40e_set_rx_function(dev);
1061                 i40e_set_tx_function(dev);
1062                 return 0;
1063         }
1064         i40e_set_default_ptype_table(dev);
1065         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         intr_handle = &pci_dev->intr_handle;
1067
1068         rte_eth_copy_pci_info(dev, pci_dev);
1069         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070
1071         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         pf->adapter->eth_dev = dev;
1073         pf->dev_data = dev->data;
1074
1075         hw->back = I40E_PF_TO_ADAPTER(pf);
1076         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1077         if (!hw->hw_addr) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Hardware is not available, as address is NULL");
1080                 return -ENODEV;
1081         }
1082
1083         hw->vendor_id = pci_dev->id.vendor_id;
1084         hw->device_id = pci_dev->id.device_id;
1085         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087         hw->bus.device = pci_dev->addr.devid;
1088         hw->bus.func = pci_dev->addr.function;
1089         hw->adapter_stopped = 0;
1090
1091         /* Make sure all is clean before doing PF reset */
1092         i40e_clear_hw(hw);
1093
1094         /* Initialize the hardware */
1095         i40e_hw_init(dev);
1096
1097         /* Reset here to make sure all is clean for each PF */
1098         ret = i40e_pf_reset(hw);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1101                 return ret;
1102         }
1103
1104         /* Initialize the shared code (base driver) */
1105         ret = i40e_init_shared_code(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108                 return ret;
1109         }
1110
1111         /*
1112          * To work around the NVM issue, initialize registers
1113          * for flexible payload and packet type of QinQ by
1114          * software. It should be removed once issues are fixed
1115          * in NVM.
1116          */
1117         i40e_GLQF_reg_init(hw);
1118
1119         /* Initialize the input set for filters (hash and fd) to default value */
1120         i40e_filter_input_set_init(pf);
1121
1122         /* Initialize the parameters for adminq */
1123         i40e_init_adminq_parameter(hw);
1124         ret = i40e_init_adminq(hw);
1125         if (ret != I40E_SUCCESS) {
1126                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1127                 return -EIO;
1128         }
1129         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132                      ((hw->nvm.version >> 12) & 0xf),
1133                      ((hw->nvm.version >> 4) & 0xff),
1134                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135
1136         /* initialise the L3_MAP register */
1137         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1138                                    0x00000028,  NULL);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141
1142         /* Need the special FW version to support floating VEB */
1143         config_floating_veb(dev);
1144         /* Clear PXE mode */
1145         i40e_clear_pxe_mode(hw);
1146         i40e_dev_sync_phy_type(hw);
1147
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         /* initialize Traffic Manager configuration */
1300         i40e_tm_conf_init(dev);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         return 0;
1313
1314 err_init_fdir_filter_list:
1315         rte_free(pf->tunnel.hash_table);
1316         rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318         rte_free(pf->ethertype.hash_table);
1319         rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321         rte_free(dev->data->mac_addrs);
1322 err_mac_alloc:
1323         i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1325 err_get_mac_addr:
1326 err_configure_lan_hmc:
1327         (void)i40e_shutdown_lan_hmc(hw);
1328 err_init_lan_hmc:
1329         i40e_res_pool_destroy(&pf->msix_pool);
1330 err_msix_pool_init:
1331         i40e_res_pool_destroy(&pf->qp_pool);
1332 err_qp_pool_init:
1333 err_parameter_init:
1334 err_get_capabilities:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         /* Remove all Traffic Manager configuration */
1465         i40e_tm_conf_uninit(dev);
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1472 {
1473         struct i40e_adapter *ad =
1474                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1478         int i, ret;
1479
1480         ret = i40e_dev_sync_phy_type(hw);
1481         if (ret)
1482                 return ret;
1483
1484         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485          * bulk allocation or vector Rx preconditions we will reset it.
1486          */
1487         ad->rx_bulk_alloc_allowed = true;
1488         ad->rx_vec_allowed = true;
1489         ad->tx_simple_allowed = true;
1490         ad->tx_vec_allowed = true;
1491
1492         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493                 ret = i40e_fdir_setup(pf);
1494                 if (ret != I40E_SUCCESS) {
1495                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1496                         return -ENOTSUP;
1497                 }
1498                 ret = i40e_fdir_configure(dev);
1499                 if (ret < 0) {
1500                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501                         goto err;
1502                 }
1503         } else
1504                 i40e_fdir_teardown(pf);
1505
1506         ret = i40e_dev_init_vlan(dev);
1507         if (ret < 0)
1508                 goto err;
1509
1510         /* VMDQ setup.
1511          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512          *  RSS setting have different requirements.
1513          *  General PMD driver call sequence are NIC init, configure,
1514          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1516          *  applicable. So, VMDQ setting has to be done before
1517          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1518          *  For RSS setting, it will try to calculate actual configured RX queue
1519          *  number, which will be available after rx_queue_setup(). dev_start()
1520          *  function is good to place RSS setup.
1521          */
1522         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523                 ret = i40e_vmdq_setup(dev);
1524                 if (ret)
1525                         goto err;
1526         }
1527
1528         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529                 ret = i40e_dcb_setup(dev);
1530                 if (ret) {
1531                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532                         goto err_dcb;
1533                 }
1534         }
1535
1536         TAILQ_INIT(&pf->flow_list);
1537
1538         return 0;
1539
1540 err_dcb:
1541         /* need to release vmdq resource if exists */
1542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543                 i40e_vsi_release(pf->vmdq[i].vsi);
1544                 pf->vmdq[i].vsi = NULL;
1545         }
1546         rte_free(pf->vmdq);
1547         pf->vmdq = NULL;
1548 err:
1549         /* need to release fdir resource if exists */
1550         i40e_fdir_teardown(pf);
1551         return ret;
1552 }
1553
1554 void
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1556 {
1557         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_vect = vsi->msix_intr;
1562         uint16_t i;
1563
1564         for (i = 0; i < vsi->nb_qps; i++) {
1565                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567                 rte_wmb();
1568         }
1569
1570         if (vsi->type != I40E_VSI_SRIOV) {
1571                 if (!rte_intr_allow_others(intr_handle)) {
1572                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1574                         I40E_WRITE_REG(hw,
1575                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1576                                        0);
1577                 } else {
1578                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1580                         I40E_WRITE_REG(hw,
1581                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582                                                        msix_vect - 1), 0);
1583                 }
1584         } else {
1585                 uint32_t reg;
1586                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587                         vsi->user_param + (msix_vect - 1);
1588
1589                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591         }
1592         I40E_WRITE_FLUSH(hw);
1593 }
1594
1595 static void
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597                        int base_queue, int nb_queue)
1598 {
1599         int i;
1600         uint32_t val;
1601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1602
1603         /* Bind all RX queues to allocated MSIX interrupt */
1604         for (i = 0; i < nb_queue; i++) {
1605                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1607                         ((base_queue + i + 1) <<
1608                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1611
1612                 if (i == nb_queue - 1)
1613                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1615         }
1616
1617         /* Write first RX queue to Link list register as the head element */
1618         if (vsi->type != I40E_VSI_SRIOV) {
1619                 uint16_t interval =
1620                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1621
1622                 if (msix_vect == I40E_MISC_VEC_ID) {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1630                                        interval);
1631                 } else {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1639                                                        msix_vect - 1),
1640                                        interval);
1641                 }
1642         } else {
1643                 uint32_t reg;
1644
1645                 if (msix_vect == I40E_MISC_VEC_ID) {
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_VPINT_LNKLST0(vsi->user_param),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1652                 } else {
1653                         /* num_msix_vectors_vf needs to minus irq0 */
1654                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655                                 vsi->user_param + (msix_vect - 1);
1656
1657                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1658                                        (base_queue <<
1659                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660                                        (0x0 <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662                 }
1663         }
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 void
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1670 {
1671         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675         uint16_t msix_vect = vsi->msix_intr;
1676         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677         uint16_t queue_idx = 0;
1678         int record = 0;
1679         uint32_t val;
1680         int i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685         }
1686
1687         /* INTENA flag is not auto-cleared for interrupt */
1688         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1693
1694         /* VF bind interrupt */
1695         if (vsi->type == I40E_VSI_SRIOV) {
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue, vsi->nb_qps);
1698                 return;
1699         }
1700
1701         /* PF & VMDq bind interrupt */
1702         if (rte_intr_dp_is_en(intr_handle)) {
1703                 if (vsi->type == I40E_VSI_MAIN) {
1704                         queue_idx = 0;
1705                         record = 1;
1706                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707                         struct i40e_vsi *main_vsi =
1708                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710                         record = 1;
1711                 }
1712         }
1713
1714         for (i = 0; i < vsi->nb_used_qps; i++) {
1715                 if (nb_msix <= 1) {
1716                         if (!rte_intr_allow_others(intr_handle))
1717                                 /* allow to share MISC_VEC_ID */
1718                                 msix_vect = I40E_MISC_VEC_ID;
1719
1720                         /* no enough msix_vect, map all to one */
1721                         __vsi_queues_bind_intr(vsi, msix_vect,
1722                                                vsi->base_queue + i,
1723                                                vsi->nb_used_qps - i);
1724                         for (; !!record && i < vsi->nb_used_qps; i++)
1725                                 intr_handle->intr_vec[queue_idx + i] =
1726                                         msix_vect;
1727                         break;
1728                 }
1729                 /* 1:1 queue/msix_vect mapping */
1730                 __vsi_queues_bind_intr(vsi, msix_vect,
1731                                        vsi->base_queue + i, 1);
1732                 if (!!record)
1733                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734
1735                 msix_vect++;
1736                 nb_msix--;
1737         }
1738 }
1739
1740 static void
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1742 {
1743         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747         uint16_t interval = i40e_calc_itr_interval(\
1748                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749         uint16_t msix_intr, i;
1750
1751         if (rte_intr_allow_others(intr_handle))
1752                 for (i = 0; i < vsi->nb_msix; i++) {
1753                         msix_intr = vsi->msix_intr + i;
1754                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1758                                 (interval <<
1759                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1766                                (interval <<
1767                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static void
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t msix_intr, i;
1780
1781         if (rte_intr_allow_others(intr_handle))
1782                 for (i = 0; i < vsi->nb_msix; i++) {
1783                         msix_intr = vsi->msix_intr + i;
1784                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785                                        0);
1786                 }
1787         else
1788                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1789
1790         I40E_WRITE_FLUSH(hw);
1791 }
1792
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1795 {
1796         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1797
1798         if (link_speeds & ETH_LINK_SPEED_40G)
1799                 link_speed |= I40E_LINK_SPEED_40GB;
1800         if (link_speeds & ETH_LINK_SPEED_25G)
1801                 link_speed |= I40E_LINK_SPEED_25GB;
1802         if (link_speeds & ETH_LINK_SPEED_20G)
1803                 link_speed |= I40E_LINK_SPEED_20GB;
1804         if (link_speeds & ETH_LINK_SPEED_10G)
1805                 link_speed |= I40E_LINK_SPEED_10GB;
1806         if (link_speeds & ETH_LINK_SPEED_1G)
1807                 link_speed |= I40E_LINK_SPEED_1GB;
1808         if (link_speeds & ETH_LINK_SPEED_100M)
1809                 link_speed |= I40E_LINK_SPEED_100MB;
1810
1811         return link_speed;
1812 }
1813
1814 static int
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1816                    uint8_t abilities,
1817                    uint8_t force_speed)
1818 {
1819         enum i40e_status_code status;
1820         struct i40e_aq_get_phy_abilities_resp phy_ab;
1821         struct i40e_aq_set_phy_config phy_conf;
1822         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1823                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1824                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1825                         I40E_AQ_PHY_FLAG_LOW_POWER;
1826         const uint8_t advt = I40E_LINK_SPEED_40GB |
1827                         I40E_LINK_SPEED_25GB |
1828                         I40E_LINK_SPEED_10GB |
1829                         I40E_LINK_SPEED_1GB |
1830                         I40E_LINK_SPEED_100MB;
1831         int ret = -ENOTSUP;
1832
1833
1834         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1835                                               NULL);
1836         if (status)
1837                 return ret;
1838
1839         memset(&phy_conf, 0, sizeof(phy_conf));
1840
1841         /* bits 0-2 use the values from get_phy_abilities_resp */
1842         abilities &= ~mask;
1843         abilities |= phy_ab.abilities & mask;
1844
1845         /* update ablities and speed */
1846         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847                 phy_conf.link_speed = advt;
1848         else
1849                 phy_conf.link_speed = force_speed;
1850
1851         phy_conf.abilities = abilities;
1852
1853         /* use get_phy_abilities_resp value for the rest */
1854         phy_conf.phy_type = phy_ab.phy_type;
1855         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1856         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1857         phy_conf.eee_capability = phy_ab.eee_capability;
1858         phy_conf.eeer = phy_ab.eeer_val;
1859         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1860
1861         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1862                     phy_ab.abilities, phy_ab.link_speed);
1863         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1864                     phy_conf.abilities, phy_conf.link_speed);
1865
1866         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1867         if (status)
1868                 return ret;
1869
1870         return I40E_SUCCESS;
1871 }
1872
1873 static int
1874 i40e_apply_link_speed(struct rte_eth_dev *dev)
1875 {
1876         uint8_t speed;
1877         uint8_t abilities = 0;
1878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct rte_eth_conf *conf = &dev->data->dev_conf;
1880
1881         speed = i40e_parse_link_speeds(conf->link_speeds);
1882         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1883         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1884                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1886
1887         /* Skip changing speed on 40G interfaces, FW does not support */
1888         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1889                 speed =  I40E_LINK_SPEED_UNKNOWN;
1890                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1891         }
1892
1893         return i40e_phy_conf_link(hw, abilities, speed);
1894 }
1895
1896 static int
1897 i40e_dev_start(struct rte_eth_dev *dev)
1898 {
1899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct i40e_vsi *main_vsi = pf->main_vsi;
1902         int ret, i;
1903         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1904         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1905         uint32_t intr_vector = 0;
1906         struct i40e_vsi *vsi;
1907
1908         hw->adapter_stopped = 0;
1909
1910         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1911                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1912                              dev->data->port_id);
1913                 return -EINVAL;
1914         }
1915
1916         rte_intr_disable(intr_handle);
1917
1918         if ((rte_intr_cap_multiple(intr_handle) ||
1919              !RTE_ETH_DEV_SRIOV(dev).active) &&
1920             dev->data->dev_conf.intr_conf.rxq != 0) {
1921                 intr_vector = dev->data->nb_rx_queues;
1922                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1923                 if (ret)
1924                         return ret;
1925         }
1926
1927         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1928                 intr_handle->intr_vec =
1929                         rte_zmalloc("intr_vec",
1930                                     dev->data->nb_rx_queues * sizeof(int),
1931                                     0);
1932                 if (!intr_handle->intr_vec) {
1933                         PMD_INIT_LOG(ERR,
1934                                 "Failed to allocate %d rx_queues intr_vec",
1935                                 dev->data->nb_rx_queues);
1936                         return -ENOMEM;
1937                 }
1938         }
1939
1940         /* Initialize VSI */
1941         ret = i40e_dev_rxtx_init(pf);
1942         if (ret != I40E_SUCCESS) {
1943                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1944                 goto err_up;
1945         }
1946
1947         /* Map queues with MSIX interrupt */
1948         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1949                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1950         i40e_vsi_queues_bind_intr(main_vsi);
1951         i40e_vsi_enable_queues_intr(main_vsi);
1952
1953         /* Map VMDQ VSI queues with MSIX interrupt */
1954         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1956                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1957                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1958         }
1959
1960         /* enable FDIR MSIX interrupt */
1961         if (pf->fdir.fdir_vsi) {
1962                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1963                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1964         }
1965
1966         /* Enable all queues which have been configured */
1967         ret = i40e_dev_switch_queues(pf, TRUE);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1970                 goto err_up;
1971         }
1972
1973         /* Enable receiving broadcast packets */
1974         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1975         if (ret != I40E_SUCCESS)
1976                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977
1978         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1979                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1980                                                 true, NULL);
1981                 if (ret != I40E_SUCCESS)
1982                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1983         }
1984
1985         /* Enable the VLAN promiscuous mode. */
1986         if (pf->vfs) {
1987                 for (i = 0; i < pf->vf_num; i++) {
1988                         vsi = pf->vfs[i].vsi;
1989                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1990                                                      true, NULL);
1991                 }
1992         }
1993
1994         /* Apply link configure */
1995         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998                                 ETH_LINK_SPEED_40G)) {
1999                 PMD_DRV_LOG(ERR, "Invalid link setting");
2000                 goto err_up;
2001         }
2002         ret = i40e_apply_link_speed(dev);
2003         if (I40E_SUCCESS != ret) {
2004                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2005                 goto err_up;
2006         }
2007
2008         if (!rte_intr_allow_others(intr_handle)) {
2009                 rte_intr_callback_unregister(intr_handle,
2010                                              i40e_dev_interrupt_handler,
2011                                              (void *)dev);
2012                 /* configure and enable device interrupt */
2013                 i40e_pf_config_irq0(hw, FALSE);
2014                 i40e_pf_enable_irq0(hw);
2015
2016                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2017                         PMD_INIT_LOG(INFO,
2018                                 "lsc won't enable because of no intr multiplex");
2019         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2020                 ret = i40e_aq_set_phy_int_mask(hw,
2021                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2024                 if (ret != I40E_SUCCESS)
2025                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2026
2027                 /* Call get_link_info aq commond to enable LSE */
2028                 i40e_dev_link_update(dev, 0);
2029         }
2030
2031         /* enable uio intr after callback register */
2032         rte_intr_enable(intr_handle);
2033
2034         i40e_filter_restore(pf);
2035
2036         return I40E_SUCCESS;
2037
2038 err_up:
2039         i40e_dev_switch_queues(pf, FALSE);
2040         i40e_dev_clear_queues(dev);
2041
2042         return ret;
2043 }
2044
2045 static void
2046 i40e_dev_stop(struct rte_eth_dev *dev)
2047 {
2048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2049         struct i40e_vsi *main_vsi = pf->main_vsi;
2050         struct i40e_mirror_rule *p_mirror;
2051         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2052         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2053         int i;
2054
2055         /* Disable all queues */
2056         i40e_dev_switch_queues(pf, FALSE);
2057
2058         /* un-map queues with interrupt registers */
2059         i40e_vsi_disable_queues_intr(main_vsi);
2060         i40e_vsi_queues_unbind_intr(main_vsi);
2061
2062         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2063                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2064                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2065         }
2066
2067         if (pf->fdir.fdir_vsi) {
2068                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2069                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2070         }
2071         /* Clear all queues and release memory */
2072         i40e_dev_clear_queues(dev);
2073
2074         /* Set link down */
2075         i40e_dev_set_link_down(dev);
2076
2077         /* Remove all mirror rules */
2078         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2079                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2080                 rte_free(p_mirror);
2081         }
2082         pf->nb_mirror_rule = 0;
2083
2084         if (!rte_intr_allow_others(intr_handle))
2085                 /* resume to the default handler */
2086                 rte_intr_callback_register(intr_handle,
2087                                            i40e_dev_interrupt_handler,
2088                                            (void *)dev);
2089
2090         /* Clean datapath event and queue/vec mapping */
2091         rte_intr_efd_disable(intr_handle);
2092         if (intr_handle->intr_vec) {
2093                 rte_free(intr_handle->intr_vec);
2094                 intr_handle->intr_vec = NULL;
2095         }
2096
2097         /* reset hierarchy commit */
2098         pf->tm_conf.committed = false;
2099 }
2100
2101 static void
2102 i40e_dev_close(struct rte_eth_dev *dev)
2103 {
2104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2107         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2108         uint32_t reg;
2109         int i;
2110
2111         PMD_INIT_FUNC_TRACE();
2112
2113         i40e_dev_stop(dev);
2114         hw->adapter_stopped = 1;
2115         i40e_dev_free_queues(dev);
2116
2117         /* Disable interrupt */
2118         i40e_pf_disable_irq0(hw);
2119         rte_intr_disable(intr_handle);
2120
2121         /* shutdown and destroy the HMC */
2122         i40e_shutdown_lan_hmc(hw);
2123
2124         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2125                 i40e_vsi_release(pf->vmdq[i].vsi);
2126                 pf->vmdq[i].vsi = NULL;
2127         }
2128         rte_free(pf->vmdq);
2129         pf->vmdq = NULL;
2130
2131         /* release all the existing VSIs and VEBs */
2132         i40e_fdir_teardown(pf);
2133         i40e_vsi_release(pf->main_vsi);
2134
2135         /* shutdown the adminq */
2136         i40e_aq_queue_shutdown(hw, true);
2137         i40e_shutdown_adminq(hw);
2138
2139         i40e_res_pool_destroy(&pf->qp_pool);
2140         i40e_res_pool_destroy(&pf->msix_pool);
2141
2142         /* force a PF reset to clean anything leftover */
2143         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2144         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2145                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2146         I40E_WRITE_FLUSH(hw);
2147 }
2148
2149 static void
2150 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2151 {
2152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         struct i40e_vsi *vsi = pf->main_vsi;
2155         int status;
2156
2157         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2158                                                      true, NULL, true);
2159         if (status != I40E_SUCCESS)
2160                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2161
2162         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2163                                                         TRUE, NULL);
2164         if (status != I40E_SUCCESS)
2165                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2166
2167 }
2168
2169 static void
2170 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2171 {
2172         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         struct i40e_vsi *vsi = pf->main_vsi;
2175         int status;
2176
2177         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2178                                                      false, NULL, true);
2179         if (status != I40E_SUCCESS)
2180                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2181
2182         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2183                                                         false, NULL);
2184         if (status != I40E_SUCCESS)
2185                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2186 }
2187
2188 static void
2189 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2190 {
2191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         struct i40e_vsi *vsi = pf->main_vsi;
2194         int ret;
2195
2196         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2197         if (ret != I40E_SUCCESS)
2198                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2199 }
2200
2201 static void
2202 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2203 {
2204         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206         struct i40e_vsi *vsi = pf->main_vsi;
2207         int ret;
2208
2209         if (dev->data->promiscuous == 1)
2210                 return; /* must remain in all_multicast mode */
2211
2212         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2213                                 vsi->seid, FALSE, NULL);
2214         if (ret != I40E_SUCCESS)
2215                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2216 }
2217
2218 /*
2219  * Set device link up.
2220  */
2221 static int
2222 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2223 {
2224         /* re-apply link speed setting */
2225         return i40e_apply_link_speed(dev);
2226 }
2227
2228 /*
2229  * Set device link down.
2230  */
2231 static int
2232 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2233 {
2234         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2235         uint8_t abilities = 0;
2236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237
2238         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2239         return i40e_phy_conf_link(hw, abilities, speed);
2240 }
2241
2242 int
2243 i40e_dev_link_update(struct rte_eth_dev *dev,
2244                      int wait_to_complete)
2245 {
2246 #define CHECK_INTERVAL 100  /* 100ms */
2247 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2248         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2249         struct i40e_link_status link_status;
2250         struct rte_eth_link link, old;
2251         int status;
2252         unsigned rep_cnt = MAX_REPEAT_TIME;
2253         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2254
2255         memset(&link, 0, sizeof(link));
2256         memset(&old, 0, sizeof(old));
2257         memset(&link_status, 0, sizeof(link_status));
2258         rte_i40e_dev_atomic_read_link_status(dev, &old);
2259
2260         do {
2261                 /* Get link status information from hardware */
2262                 status = i40e_aq_get_link_info(hw, enable_lse,
2263                                                 &link_status, NULL);
2264                 if (status != I40E_SUCCESS) {
2265                         link.link_speed = ETH_SPEED_NUM_100M;
2266                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2267                         PMD_DRV_LOG(ERR, "Failed to get link info");
2268                         goto out;
2269                 }
2270
2271                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2272                 if (!wait_to_complete || link.link_status)
2273                         break;
2274
2275                 rte_delay_ms(CHECK_INTERVAL);
2276         } while (--rep_cnt);
2277
2278         if (!link.link_status)
2279                 goto out;
2280
2281         /* i40e uses full duplex only */
2282         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2283
2284         /* Parse the link status */
2285         switch (link_status.link_speed) {
2286         case I40E_LINK_SPEED_100MB:
2287                 link.link_speed = ETH_SPEED_NUM_100M;
2288                 break;
2289         case I40E_LINK_SPEED_1GB:
2290                 link.link_speed = ETH_SPEED_NUM_1G;
2291                 break;
2292         case I40E_LINK_SPEED_10GB:
2293                 link.link_speed = ETH_SPEED_NUM_10G;
2294                 break;
2295         case I40E_LINK_SPEED_20GB:
2296                 link.link_speed = ETH_SPEED_NUM_20G;
2297                 break;
2298         case I40E_LINK_SPEED_25GB:
2299                 link.link_speed = ETH_SPEED_NUM_25G;
2300                 break;
2301         case I40E_LINK_SPEED_40GB:
2302                 link.link_speed = ETH_SPEED_NUM_40G;
2303                 break;
2304         default:
2305                 link.link_speed = ETH_SPEED_NUM_100M;
2306                 break;
2307         }
2308
2309         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2310                         ETH_LINK_SPEED_FIXED);
2311
2312 out:
2313         rte_i40e_dev_atomic_write_link_status(dev, &link);
2314         if (link.link_status == old.link_status)
2315                 return -1;
2316
2317         i40e_notify_all_vfs_link_status(dev);
2318
2319         return 0;
2320 }
2321
2322 /* Get all the statistics of a VSI */
2323 void
2324 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2325 {
2326         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2327         struct i40e_eth_stats *nes = &vsi->eth_stats;
2328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2329         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2330
2331         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2332                             vsi->offset_loaded, &oes->rx_bytes,
2333                             &nes->rx_bytes);
2334         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2335                             vsi->offset_loaded, &oes->rx_unicast,
2336                             &nes->rx_unicast);
2337         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2338                             vsi->offset_loaded, &oes->rx_multicast,
2339                             &nes->rx_multicast);
2340         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2341                             vsi->offset_loaded, &oes->rx_broadcast,
2342                             &nes->rx_broadcast);
2343         /* exclude CRC bytes */
2344         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2345                 nes->rx_broadcast) * ETHER_CRC_LEN;
2346
2347         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2348                             &oes->rx_discards, &nes->rx_discards);
2349         /* GLV_REPC not supported */
2350         /* GLV_RMPC not supported */
2351         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2352                             &oes->rx_unknown_protocol,
2353                             &nes->rx_unknown_protocol);
2354         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2355                             vsi->offset_loaded, &oes->tx_bytes,
2356                             &nes->tx_bytes);
2357         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2358                             vsi->offset_loaded, &oes->tx_unicast,
2359                             &nes->tx_unicast);
2360         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2361                             vsi->offset_loaded, &oes->tx_multicast,
2362                             &nes->tx_multicast);
2363         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2364                             vsi->offset_loaded,  &oes->tx_broadcast,
2365                             &nes->tx_broadcast);
2366         /* exclude CRC bytes */
2367         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2368                 nes->tx_broadcast) * ETHER_CRC_LEN;
2369         /* GLV_TDPC not supported */
2370         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2371                             &oes->tx_errors, &nes->tx_errors);
2372         vsi->offset_loaded = true;
2373
2374         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2375                     vsi->vsi_id);
2376         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2377         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2378         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2379         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2380         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2381         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2382                     nes->rx_unknown_protocol);
2383         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2384         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2385         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2386         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2387         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2388         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2389         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2390                     vsi->vsi_id);
2391 }
2392
2393 static void
2394 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2395 {
2396         unsigned int i;
2397         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2398         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2399
2400         /* Get rx/tx bytes of internal transfer packets */
2401         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2402                         I40E_GLV_GORCL(hw->port),
2403                         pf->offset_loaded,
2404                         &pf->internal_stats_offset.rx_bytes,
2405                         &pf->internal_stats.rx_bytes);
2406
2407         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2408                         I40E_GLV_GOTCL(hw->port),
2409                         pf->offset_loaded,
2410                         &pf->internal_stats_offset.tx_bytes,
2411                         &pf->internal_stats.tx_bytes);
2412         /* Get total internal rx packet count */
2413         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2414                             I40E_GLV_UPRCL(hw->port),
2415                             pf->offset_loaded,
2416                             &pf->internal_stats_offset.rx_unicast,
2417                             &pf->internal_stats.rx_unicast);
2418         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2419                             I40E_GLV_MPRCL(hw->port),
2420                             pf->offset_loaded,
2421                             &pf->internal_stats_offset.rx_multicast,
2422                             &pf->internal_stats.rx_multicast);
2423         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2424                             I40E_GLV_BPRCL(hw->port),
2425                             pf->offset_loaded,
2426                             &pf->internal_stats_offset.rx_broadcast,
2427                             &pf->internal_stats.rx_broadcast);
2428
2429         /* exclude CRC size */
2430         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2431                 pf->internal_stats.rx_multicast +
2432                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2433
2434         /* Get statistics of struct i40e_eth_stats */
2435         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2436                             I40E_GLPRT_GORCL(hw->port),
2437                             pf->offset_loaded, &os->eth.rx_bytes,
2438                             &ns->eth.rx_bytes);
2439         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2440                             I40E_GLPRT_UPRCL(hw->port),
2441                             pf->offset_loaded, &os->eth.rx_unicast,
2442                             &ns->eth.rx_unicast);
2443         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2444                             I40E_GLPRT_MPRCL(hw->port),
2445                             pf->offset_loaded, &os->eth.rx_multicast,
2446                             &ns->eth.rx_multicast);
2447         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2448                             I40E_GLPRT_BPRCL(hw->port),
2449                             pf->offset_loaded, &os->eth.rx_broadcast,
2450                             &ns->eth.rx_broadcast);
2451         /* Workaround: CRC size should not be included in byte statistics,
2452          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2453          */
2454         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2455                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2456
2457         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2458          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2459          * value.
2460          */
2461         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2462                 ns->eth.rx_bytes = 0;
2463         /* exlude internal rx bytes */
2464         else
2465                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2466
2467         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2468                             pf->offset_loaded, &os->eth.rx_discards,
2469                             &ns->eth.rx_discards);
2470         /* GLPRT_REPC not supported */
2471         /* GLPRT_RMPC not supported */
2472         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2473                             pf->offset_loaded,
2474                             &os->eth.rx_unknown_protocol,
2475                             &ns->eth.rx_unknown_protocol);
2476         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2477                             I40E_GLPRT_GOTCL(hw->port),
2478                             pf->offset_loaded, &os->eth.tx_bytes,
2479                             &ns->eth.tx_bytes);
2480         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2481                             I40E_GLPRT_UPTCL(hw->port),
2482                             pf->offset_loaded, &os->eth.tx_unicast,
2483                             &ns->eth.tx_unicast);
2484         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2485                             I40E_GLPRT_MPTCL(hw->port),
2486                             pf->offset_loaded, &os->eth.tx_multicast,
2487                             &ns->eth.tx_multicast);
2488         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2489                             I40E_GLPRT_BPTCL(hw->port),
2490                             pf->offset_loaded, &os->eth.tx_broadcast,
2491                             &ns->eth.tx_broadcast);
2492         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2493                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2494
2495         /* exclude internal tx bytes */
2496         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2497                 ns->eth.tx_bytes = 0;
2498         else
2499                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2500
2501         /* GLPRT_TEPC not supported */
2502
2503         /* additional port specific stats */
2504         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2505                             pf->offset_loaded, &os->tx_dropped_link_down,
2506                             &ns->tx_dropped_link_down);
2507         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2508                             pf->offset_loaded, &os->crc_errors,
2509                             &ns->crc_errors);
2510         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2511                             pf->offset_loaded, &os->illegal_bytes,
2512                             &ns->illegal_bytes);
2513         /* GLPRT_ERRBC not supported */
2514         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2515                             pf->offset_loaded, &os->mac_local_faults,
2516                             &ns->mac_local_faults);
2517         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2518                             pf->offset_loaded, &os->mac_remote_faults,
2519                             &ns->mac_remote_faults);
2520         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2521                             pf->offset_loaded, &os->rx_length_errors,
2522                             &ns->rx_length_errors);
2523         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2524                             pf->offset_loaded, &os->link_xon_rx,
2525                             &ns->link_xon_rx);
2526         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2527                             pf->offset_loaded, &os->link_xoff_rx,
2528                             &ns->link_xoff_rx);
2529         for (i = 0; i < 8; i++) {
2530                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2531                                     pf->offset_loaded,
2532                                     &os->priority_xon_rx[i],
2533                                     &ns->priority_xon_rx[i]);
2534                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2535                                     pf->offset_loaded,
2536                                     &os->priority_xoff_rx[i],
2537                                     &ns->priority_xoff_rx[i]);
2538         }
2539         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2540                             pf->offset_loaded, &os->link_xon_tx,
2541                             &ns->link_xon_tx);
2542         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2543                             pf->offset_loaded, &os->link_xoff_tx,
2544                             &ns->link_xoff_tx);
2545         for (i = 0; i < 8; i++) {
2546                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2547                                     pf->offset_loaded,
2548                                     &os->priority_xon_tx[i],
2549                                     &ns->priority_xon_tx[i]);
2550                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2551                                     pf->offset_loaded,
2552                                     &os->priority_xoff_tx[i],
2553                                     &ns->priority_xoff_tx[i]);
2554                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2555                                     pf->offset_loaded,
2556                                     &os->priority_xon_2_xoff[i],
2557                                     &ns->priority_xon_2_xoff[i]);
2558         }
2559         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2560                             I40E_GLPRT_PRC64L(hw->port),
2561                             pf->offset_loaded, &os->rx_size_64,
2562                             &ns->rx_size_64);
2563         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2564                             I40E_GLPRT_PRC127L(hw->port),
2565                             pf->offset_loaded, &os->rx_size_127,
2566                             &ns->rx_size_127);
2567         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2568                             I40E_GLPRT_PRC255L(hw->port),
2569                             pf->offset_loaded, &os->rx_size_255,
2570                             &ns->rx_size_255);
2571         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2572                             I40E_GLPRT_PRC511L(hw->port),
2573                             pf->offset_loaded, &os->rx_size_511,
2574                             &ns->rx_size_511);
2575         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2576                             I40E_GLPRT_PRC1023L(hw->port),
2577                             pf->offset_loaded, &os->rx_size_1023,
2578                             &ns->rx_size_1023);
2579         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2580                             I40E_GLPRT_PRC1522L(hw->port),
2581                             pf->offset_loaded, &os->rx_size_1522,
2582                             &ns->rx_size_1522);
2583         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2584                             I40E_GLPRT_PRC9522L(hw->port),
2585                             pf->offset_loaded, &os->rx_size_big,
2586                             &ns->rx_size_big);
2587         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2588                             pf->offset_loaded, &os->rx_undersize,
2589                             &ns->rx_undersize);
2590         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2591                             pf->offset_loaded, &os->rx_fragments,
2592                             &ns->rx_fragments);
2593         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2594                             pf->offset_loaded, &os->rx_oversize,
2595                             &ns->rx_oversize);
2596         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2597                             pf->offset_loaded, &os->rx_jabber,
2598                             &ns->rx_jabber);
2599         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2600                             I40E_GLPRT_PTC64L(hw->port),
2601                             pf->offset_loaded, &os->tx_size_64,
2602                             &ns->tx_size_64);
2603         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2604                             I40E_GLPRT_PTC127L(hw->port),
2605                             pf->offset_loaded, &os->tx_size_127,
2606                             &ns->tx_size_127);
2607         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2608                             I40E_GLPRT_PTC255L(hw->port),
2609                             pf->offset_loaded, &os->tx_size_255,
2610                             &ns->tx_size_255);
2611         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2612                             I40E_GLPRT_PTC511L(hw->port),
2613                             pf->offset_loaded, &os->tx_size_511,
2614                             &ns->tx_size_511);
2615         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2616                             I40E_GLPRT_PTC1023L(hw->port),
2617                             pf->offset_loaded, &os->tx_size_1023,
2618                             &ns->tx_size_1023);
2619         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2620                             I40E_GLPRT_PTC1522L(hw->port),
2621                             pf->offset_loaded, &os->tx_size_1522,
2622                             &ns->tx_size_1522);
2623         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2624                             I40E_GLPRT_PTC9522L(hw->port),
2625                             pf->offset_loaded, &os->tx_size_big,
2626                             &ns->tx_size_big);
2627         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2628                            pf->offset_loaded,
2629                            &os->fd_sb_match, &ns->fd_sb_match);
2630         /* GLPRT_MSPDC not supported */
2631         /* GLPRT_XEC not supported */
2632
2633         pf->offset_loaded = true;
2634
2635         if (pf->main_vsi)
2636                 i40e_update_vsi_stats(pf->main_vsi);
2637 }
2638
2639 /* Get all statistics of a port */
2640 static void
2641 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2642 {
2643         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2646         unsigned i;
2647
2648         /* call read registers - updates values, now write them to struct */
2649         i40e_read_stats_registers(pf, hw);
2650
2651         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2652                         pf->main_vsi->eth_stats.rx_multicast +
2653                         pf->main_vsi->eth_stats.rx_broadcast -
2654                         pf->main_vsi->eth_stats.rx_discards;
2655         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2656                         pf->main_vsi->eth_stats.tx_multicast +
2657                         pf->main_vsi->eth_stats.tx_broadcast;
2658         stats->ibytes   = ns->eth.rx_bytes;
2659         stats->obytes   = ns->eth.tx_bytes;
2660         stats->oerrors  = ns->eth.tx_errors +
2661                         pf->main_vsi->eth_stats.tx_errors;
2662
2663         /* Rx Errors */
2664         stats->imissed  = ns->eth.rx_discards +
2665                         pf->main_vsi->eth_stats.rx_discards;
2666         stats->ierrors  = ns->crc_errors +
2667                         ns->rx_length_errors + ns->rx_undersize +
2668                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2669
2670         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2671         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2672         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2673         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2674         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2675         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2676         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2677                     ns->eth.rx_unknown_protocol);
2678         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2679         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2680         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2681         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2682         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2683         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2684
2685         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2686                     ns->tx_dropped_link_down);
2687         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2688         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2689                     ns->illegal_bytes);
2690         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2691         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2692                     ns->mac_local_faults);
2693         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2694                     ns->mac_remote_faults);
2695         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2696                     ns->rx_length_errors);
2697         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2698         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2699         for (i = 0; i < 8; i++) {
2700                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2701                                 i, ns->priority_xon_rx[i]);
2702                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2703                                 i, ns->priority_xoff_rx[i]);
2704         }
2705         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2706         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2707         for (i = 0; i < 8; i++) {
2708                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2709                                 i, ns->priority_xon_tx[i]);
2710                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2711                                 i, ns->priority_xoff_tx[i]);
2712                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2713                                 i, ns->priority_xon_2_xoff[i]);
2714         }
2715         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2716         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2717         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2718         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2719         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2720         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2721         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2722         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2723         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2724         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2725         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2726         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2727         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2728         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2729         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2730         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2731         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2732         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2733         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2734                         ns->mac_short_packet_dropped);
2735         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2736                     ns->checksum_error);
2737         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2738         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2739 }
2740
2741 /* Reset the statistics */
2742 static void
2743 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2744 {
2745         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747
2748         /* Mark PF and VSI stats to update the offset, aka "reset" */
2749         pf->offset_loaded = false;
2750         if (pf->main_vsi)
2751                 pf->main_vsi->offset_loaded = false;
2752
2753         /* read the stats, reading current register values into offset */
2754         i40e_read_stats_registers(pf, hw);
2755 }
2756
2757 static uint32_t
2758 i40e_xstats_calc_num(void)
2759 {
2760         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2761                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2762                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2763 }
2764
2765 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2766                                      struct rte_eth_xstat_name *xstats_names,
2767                                      __rte_unused unsigned limit)
2768 {
2769         unsigned count = 0;
2770         unsigned i, prio;
2771
2772         if (xstats_names == NULL)
2773                 return i40e_xstats_calc_num();
2774
2775         /* Note: limit checked in rte_eth_xstats_names() */
2776
2777         /* Get stats from i40e_eth_stats struct */
2778         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2779                 snprintf(xstats_names[count].name,
2780                          sizeof(xstats_names[count].name),
2781                          "%s", rte_i40e_stats_strings[i].name);
2782                 count++;
2783         }
2784
2785         /* Get individiual stats from i40e_hw_port struct */
2786         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2787                 snprintf(xstats_names[count].name,
2788                         sizeof(xstats_names[count].name),
2789                          "%s", rte_i40e_hw_port_strings[i].name);
2790                 count++;
2791         }
2792
2793         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2794                 for (prio = 0; prio < 8; prio++) {
2795                         snprintf(xstats_names[count].name,
2796                                  sizeof(xstats_names[count].name),
2797                                  "rx_priority%u_%s", prio,
2798                                  rte_i40e_rxq_prio_strings[i].name);
2799                         count++;
2800                 }
2801         }
2802
2803         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2804                 for (prio = 0; prio < 8; prio++) {
2805                         snprintf(xstats_names[count].name,
2806                                  sizeof(xstats_names[count].name),
2807                                  "tx_priority%u_%s", prio,
2808                                  rte_i40e_txq_prio_strings[i].name);
2809                         count++;
2810                 }
2811         }
2812         return count;
2813 }
2814
2815 static int
2816 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2817                     unsigned n)
2818 {
2819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821         unsigned i, count, prio;
2822         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2823
2824         count = i40e_xstats_calc_num();
2825         if (n < count)
2826                 return count;
2827
2828         i40e_read_stats_registers(pf, hw);
2829
2830         if (xstats == NULL)
2831                 return 0;
2832
2833         count = 0;
2834
2835         /* Get stats from i40e_eth_stats struct */
2836         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2837                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2838                         rte_i40e_stats_strings[i].offset);
2839                 xstats[count].id = count;
2840                 count++;
2841         }
2842
2843         /* Get individiual stats from i40e_hw_port struct */
2844         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2845                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2846                         rte_i40e_hw_port_strings[i].offset);
2847                 xstats[count].id = count;
2848                 count++;
2849         }
2850
2851         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2852                 for (prio = 0; prio < 8; prio++) {
2853                         xstats[count].value =
2854                                 *(uint64_t *)(((char *)hw_stats) +
2855                                 rte_i40e_rxq_prio_strings[i].offset +
2856                                 (sizeof(uint64_t) * prio));
2857                         xstats[count].id = count;
2858                         count++;
2859                 }
2860         }
2861
2862         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2863                 for (prio = 0; prio < 8; prio++) {
2864                         xstats[count].value =
2865                                 *(uint64_t *)(((char *)hw_stats) +
2866                                 rte_i40e_txq_prio_strings[i].offset +
2867                                 (sizeof(uint64_t) * prio));
2868                         xstats[count].id = count;
2869                         count++;
2870                 }
2871         }
2872
2873         return count;
2874 }
2875
2876 static int
2877 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2878                                  __rte_unused uint16_t queue_id,
2879                                  __rte_unused uint8_t stat_idx,
2880                                  __rte_unused uint8_t is_rx)
2881 {
2882         PMD_INIT_FUNC_TRACE();
2883
2884         return -ENOSYS;
2885 }
2886
2887 static int
2888 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2889 {
2890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891         u32 full_ver;
2892         u8 ver, patch;
2893         u16 build;
2894         int ret;
2895
2896         full_ver = hw->nvm.oem_ver;
2897         ver = (u8)(full_ver >> 24);
2898         build = (u16)((full_ver >> 8) & 0xffff);
2899         patch = (u8)(full_ver & 0xff);
2900
2901         ret = snprintf(fw_version, fw_size,
2902                  "%d.%d%d 0x%08x %d.%d.%d",
2903                  ((hw->nvm.version >> 12) & 0xf),
2904                  ((hw->nvm.version >> 4) & 0xff),
2905                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2906                  ver, build, patch);
2907
2908         ret += 1; /* add the size of '\0' */
2909         if (fw_size < (u32)ret)
2910                 return ret;
2911         else
2912                 return 0;
2913 }
2914
2915 static void
2916 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2917 {
2918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920         struct i40e_vsi *vsi = pf->main_vsi;
2921         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2922
2923         dev_info->pci_dev = pci_dev;
2924         dev_info->max_rx_queues = vsi->nb_qps;
2925         dev_info->max_tx_queues = vsi->nb_qps;
2926         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2927         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2928         dev_info->max_mac_addrs = vsi->max_macaddrs;
2929         dev_info->max_vfs = pci_dev->max_vfs;
2930         dev_info->rx_offload_capa =
2931                 DEV_RX_OFFLOAD_VLAN_STRIP |
2932                 DEV_RX_OFFLOAD_QINQ_STRIP |
2933                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2934                 DEV_RX_OFFLOAD_UDP_CKSUM |
2935                 DEV_RX_OFFLOAD_TCP_CKSUM;
2936         dev_info->tx_offload_capa =
2937                 DEV_TX_OFFLOAD_VLAN_INSERT |
2938                 DEV_TX_OFFLOAD_QINQ_INSERT |
2939                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2940                 DEV_TX_OFFLOAD_UDP_CKSUM |
2941                 DEV_TX_OFFLOAD_TCP_CKSUM |
2942                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2943                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2944                 DEV_TX_OFFLOAD_TCP_TSO |
2945                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2946                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2947                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2948                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2949         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2950                                                 sizeof(uint32_t);
2951         dev_info->reta_size = pf->hash_lut_size;
2952         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2953
2954         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2955                 .rx_thresh = {
2956                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2957                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2958                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2959                 },
2960                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2961                 .rx_drop_en = 0,
2962         };
2963
2964         dev_info->default_txconf = (struct rte_eth_txconf) {
2965                 .tx_thresh = {
2966                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2967                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2968                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2969                 },
2970                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2971                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2972                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2973                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2974         };
2975
2976         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2977                 .nb_max = I40E_MAX_RING_DESC,
2978                 .nb_min = I40E_MIN_RING_DESC,
2979                 .nb_align = I40E_ALIGN_RING_DESC,
2980         };
2981
2982         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2983                 .nb_max = I40E_MAX_RING_DESC,
2984                 .nb_min = I40E_MIN_RING_DESC,
2985                 .nb_align = I40E_ALIGN_RING_DESC,
2986                 .nb_seg_max = I40E_TX_MAX_SEG,
2987                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2988         };
2989
2990         if (pf->flags & I40E_FLAG_VMDQ) {
2991                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2992                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2993                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2994                                                 pf->max_nb_vmdq_vsi;
2995                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2996                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2997                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2998         }
2999
3000         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3001                 /* For XL710 */
3002                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3003         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3004                 /* For XXV710 */
3005                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3006         else
3007                 /* For X710 */
3008                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3009 }
3010
3011 static int
3012 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3013 {
3014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3015         struct i40e_vsi *vsi = pf->main_vsi;
3016         PMD_INIT_FUNC_TRACE();
3017
3018         if (on)
3019                 return i40e_vsi_add_vlan(vsi, vlan_id);
3020         else
3021                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3022 }
3023
3024 static int
3025 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3026                                 enum rte_vlan_type vlan_type,
3027                                 uint16_t tpid, int qinq)
3028 {
3029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         uint64_t reg_r = 0;
3031         uint64_t reg_w = 0;
3032         uint16_t reg_id = 3;
3033         int ret;
3034
3035         if (qinq) {
3036                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3037                         reg_id = 2;
3038         }
3039
3040         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3041                                           &reg_r, NULL);
3042         if (ret != I40E_SUCCESS) {
3043                 PMD_DRV_LOG(ERR,
3044                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3045                            reg_id);
3046                 return -EIO;
3047         }
3048         PMD_DRV_LOG(DEBUG,
3049                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3050                     reg_id, reg_r);
3051
3052         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3053         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3054         if (reg_r == reg_w) {
3055                 PMD_DRV_LOG(DEBUG, "No need to write");
3056                 return 0;
3057         }
3058
3059         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3060                                            reg_w, NULL);
3061         if (ret != I40E_SUCCESS) {
3062                 PMD_DRV_LOG(ERR,
3063                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3064                             reg_id);
3065                 return -EIO;
3066         }
3067         PMD_DRV_LOG(DEBUG,
3068                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3069                     reg_w, reg_id);
3070
3071         return 0;
3072 }
3073
3074 static int
3075 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3076                    enum rte_vlan_type vlan_type,
3077                    uint16_t tpid)
3078 {
3079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3081         int ret = 0;
3082
3083         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3084              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3085             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3086                 PMD_DRV_LOG(ERR,
3087                             "Unsupported vlan type.");
3088                 return -EINVAL;
3089         }
3090         /* 802.1ad frames ability is added in NVM API 1.7*/
3091         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3092                 if (qinq) {
3093                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3094                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3095                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3096                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3097                 } else {
3098                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3099                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3100                 }
3101                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3102                 if (ret != I40E_SUCCESS) {
3103                         PMD_DRV_LOG(ERR,
3104                                     "Set switch config failed aq_err: %d",
3105                                     hw->aq.asq_last_status);
3106                         ret = -EIO;
3107                 }
3108         } else
3109                 /* If NVM API < 1.7, keep the register setting */
3110                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3111                                                       tpid, qinq);
3112
3113         return ret;
3114 }
3115
3116 static void
3117 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3118 {
3119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3120         struct i40e_vsi *vsi = pf->main_vsi;
3121
3122         if (mask & ETH_VLAN_FILTER_MASK) {
3123                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3124                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3125                 else
3126                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3127         }
3128
3129         if (mask & ETH_VLAN_STRIP_MASK) {
3130                 /* Enable or disable VLAN stripping */
3131                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3132                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3133                 else
3134                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3135         }
3136
3137         if (mask & ETH_VLAN_EXTEND_MASK) {
3138                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3139                         i40e_vsi_config_double_vlan(vsi, TRUE);
3140                         /* Set global registers with default ethertype. */
3141                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3142                                            ETHER_TYPE_VLAN);
3143                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3144                                            ETHER_TYPE_VLAN);
3145                 }
3146                 else
3147                         i40e_vsi_config_double_vlan(vsi, FALSE);
3148         }
3149 }
3150
3151 static void
3152 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3153                           __rte_unused uint16_t queue,
3154                           __rte_unused int on)
3155 {
3156         PMD_INIT_FUNC_TRACE();
3157 }
3158
3159 static int
3160 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3161 {
3162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3163         struct i40e_vsi *vsi = pf->main_vsi;
3164         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3165         struct i40e_vsi_vlan_pvid_info info;
3166
3167         memset(&info, 0, sizeof(info));
3168         info.on = on;
3169         if (info.on)
3170                 info.config.pvid = pvid;
3171         else {
3172                 info.config.reject.tagged =
3173                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3174                 info.config.reject.untagged =
3175                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3176         }
3177
3178         return i40e_vsi_vlan_pvid_set(vsi, &info);
3179 }
3180
3181 static int
3182 i40e_dev_led_on(struct rte_eth_dev *dev)
3183 {
3184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185         uint32_t mode = i40e_led_get(hw);
3186
3187         if (mode == 0)
3188                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3189
3190         return 0;
3191 }
3192
3193 static int
3194 i40e_dev_led_off(struct rte_eth_dev *dev)
3195 {
3196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197         uint32_t mode = i40e_led_get(hw);
3198
3199         if (mode != 0)
3200                 i40e_led_set(hw, 0, false);
3201
3202         return 0;
3203 }
3204
3205 static int
3206 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3207 {
3208         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3210
3211         fc_conf->pause_time = pf->fc_conf.pause_time;
3212         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3213         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3214
3215          /* Return current mode according to actual setting*/
3216         switch (hw->fc.current_mode) {
3217         case I40E_FC_FULL:
3218                 fc_conf->mode = RTE_FC_FULL;
3219                 break;
3220         case I40E_FC_TX_PAUSE:
3221                 fc_conf->mode = RTE_FC_TX_PAUSE;
3222                 break;
3223         case I40E_FC_RX_PAUSE:
3224                 fc_conf->mode = RTE_FC_RX_PAUSE;
3225                 break;
3226         case I40E_FC_NONE:
3227         default:
3228                 fc_conf->mode = RTE_FC_NONE;
3229         };
3230
3231         return 0;
3232 }
3233
3234 static int
3235 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3236 {
3237         uint32_t mflcn_reg, fctrl_reg, reg;
3238         uint32_t max_high_water;
3239         uint8_t i, aq_failure;
3240         int err;
3241         struct i40e_hw *hw;
3242         struct i40e_pf *pf;
3243         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3244                 [RTE_FC_NONE] = I40E_FC_NONE,
3245                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3246                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3247                 [RTE_FC_FULL] = I40E_FC_FULL
3248         };
3249
3250         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3251
3252         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3253         if ((fc_conf->high_water > max_high_water) ||
3254                         (fc_conf->high_water < fc_conf->low_water)) {
3255                 PMD_INIT_LOG(ERR,
3256                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3257                         max_high_water);
3258                 return -EINVAL;
3259         }
3260
3261         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3262         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3263         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3264
3265         pf->fc_conf.pause_time = fc_conf->pause_time;
3266         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3267         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3268
3269         PMD_INIT_FUNC_TRACE();
3270
3271         /* All the link flow control related enable/disable register
3272          * configuration is handle by the F/W
3273          */
3274         err = i40e_set_fc(hw, &aq_failure, true);
3275         if (err < 0)
3276                 return -ENOSYS;
3277
3278         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3279                 /* Configure flow control refresh threshold,
3280                  * the value for stat_tx_pause_refresh_timer[8]
3281                  * is used for global pause operation.
3282                  */
3283
3284                 I40E_WRITE_REG(hw,
3285                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3286                                pf->fc_conf.pause_time);
3287
3288                 /* configure the timer value included in transmitted pause
3289                  * frame,
3290                  * the value for stat_tx_pause_quanta[8] is used for global
3291                  * pause operation
3292                  */
3293                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3294                                pf->fc_conf.pause_time);
3295
3296                 fctrl_reg = I40E_READ_REG(hw,
3297                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3298
3299                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3300                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3301                 else
3302                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3303
3304                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3305                                fctrl_reg);
3306         } else {
3307                 /* Configure pause time (2 TCs per register) */
3308                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3309                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3310                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3311
3312                 /* Configure flow control refresh threshold value */
3313                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3314                                pf->fc_conf.pause_time / 2);
3315
3316                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3317
3318                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3319                  *depending on configuration
3320                  */
3321                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3322                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3323                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3324                 } else {
3325                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3326                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3327                 }
3328
3329                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3330         }
3331
3332         /* config the water marker both based on the packets and bytes */
3333         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3334                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3335                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3336         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3337                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3338                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3339         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3340                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3341                        << I40E_KILOSHIFT);
3342         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3343                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3344                        << I40E_KILOSHIFT);
3345
3346         I40E_WRITE_FLUSH(hw);
3347
3348         return 0;
3349 }
3350
3351 static int
3352 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3353                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3354 {
3355         PMD_INIT_FUNC_TRACE();
3356
3357         return -ENOSYS;
3358 }
3359
3360 /* Add a MAC address, and update filters */
3361 static int
3362 i40e_macaddr_add(struct rte_eth_dev *dev,
3363                  struct ether_addr *mac_addr,
3364                  __rte_unused uint32_t index,
3365                  uint32_t pool)
3366 {
3367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368         struct i40e_mac_filter_info mac_filter;
3369         struct i40e_vsi *vsi;
3370         int ret;
3371
3372         /* If VMDQ not enabled or configured, return */
3373         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3374                           !pf->nb_cfg_vmdq_vsi)) {
3375                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3376                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3377                         pool);
3378                 return -ENOTSUP;
3379         }
3380
3381         if (pool > pf->nb_cfg_vmdq_vsi) {
3382                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3383                                 pool, pf->nb_cfg_vmdq_vsi);
3384                 return -EINVAL;
3385         }
3386
3387         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3388         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3389                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3390         else
3391                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3392
3393         if (pool == 0)
3394                 vsi = pf->main_vsi;
3395         else
3396                 vsi = pf->vmdq[pool - 1].vsi;
3397
3398         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3399         if (ret != I40E_SUCCESS) {
3400                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3401                 return -ENODEV;
3402         }
3403         return 0;
3404 }
3405
3406 /* Remove a MAC address, and update filters */
3407 static void
3408 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3409 {
3410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3411         struct i40e_vsi *vsi;
3412         struct rte_eth_dev_data *data = dev->data;
3413         struct ether_addr *macaddr;
3414         int ret;
3415         uint32_t i;
3416         uint64_t pool_sel;
3417
3418         macaddr = &(data->mac_addrs[index]);
3419
3420         pool_sel = dev->data->mac_pool_sel[index];
3421
3422         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3423                 if (pool_sel & (1ULL << i)) {
3424                         if (i == 0)
3425                                 vsi = pf->main_vsi;
3426                         else {
3427                                 /* No VMDQ pool enabled or configured */
3428                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3429                                         (i > pf->nb_cfg_vmdq_vsi)) {
3430                                         PMD_DRV_LOG(ERR,
3431                                                 "No VMDQ pool enabled/configured");
3432                                         return;
3433                                 }
3434                                 vsi = pf->vmdq[i - 1].vsi;
3435                         }
3436                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3437
3438                         if (ret) {
3439                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3440                                 return;
3441                         }
3442                 }
3443         }
3444 }
3445
3446 /* Set perfect match or hash match of MAC and VLAN for a VF */
3447 static int
3448 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3449                  struct rte_eth_mac_filter *filter,
3450                  bool add)
3451 {
3452         struct i40e_hw *hw;
3453         struct i40e_mac_filter_info mac_filter;
3454         struct ether_addr old_mac;
3455         struct ether_addr *new_mac;
3456         struct i40e_pf_vf *vf = NULL;
3457         uint16_t vf_id;
3458         int ret;
3459
3460         if (pf == NULL) {
3461                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3462                 return -EINVAL;
3463         }
3464         hw = I40E_PF_TO_HW(pf);
3465
3466         if (filter == NULL) {
3467                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3468                 return -EINVAL;
3469         }
3470
3471         new_mac = &filter->mac_addr;
3472
3473         if (is_zero_ether_addr(new_mac)) {
3474                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3475                 return -EINVAL;
3476         }
3477
3478         vf_id = filter->dst_id;
3479
3480         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3481                 PMD_DRV_LOG(ERR, "Invalid argument.");
3482                 return -EINVAL;
3483         }
3484         vf = &pf->vfs[vf_id];
3485
3486         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3487                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3488                 return -EINVAL;
3489         }
3490
3491         if (add) {
3492                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3493                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3494                                 ETHER_ADDR_LEN);
3495                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3496                                  ETHER_ADDR_LEN);
3497
3498                 mac_filter.filter_type = filter->filter_type;
3499                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3500                 if (ret != I40E_SUCCESS) {
3501                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3502                         return -1;
3503                 }
3504                 ether_addr_copy(new_mac, &pf->dev_addr);
3505         } else {
3506                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3507                                 ETHER_ADDR_LEN);
3508                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3509                 if (ret != I40E_SUCCESS) {
3510                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3511                         return -1;
3512                 }
3513
3514                 /* Clear device address as it has been removed */
3515                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3516                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3517         }
3518
3519         return 0;
3520 }
3521
3522 /* MAC filter handle */
3523 static int
3524 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3525                 void *arg)
3526 {
3527         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3528         struct rte_eth_mac_filter *filter;
3529         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3530         int ret = I40E_NOT_SUPPORTED;
3531
3532         filter = (struct rte_eth_mac_filter *)(arg);
3533
3534         switch (filter_op) {
3535         case RTE_ETH_FILTER_NOP:
3536                 ret = I40E_SUCCESS;
3537                 break;
3538         case RTE_ETH_FILTER_ADD:
3539                 i40e_pf_disable_irq0(hw);
3540                 if (filter->is_vf)
3541                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3542                 i40e_pf_enable_irq0(hw);
3543                 break;
3544         case RTE_ETH_FILTER_DELETE:
3545                 i40e_pf_disable_irq0(hw);
3546                 if (filter->is_vf)
3547                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3548                 i40e_pf_enable_irq0(hw);
3549                 break;
3550         default:
3551                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3552                 ret = I40E_ERR_PARAM;
3553                 break;
3554         }
3555
3556         return ret;
3557 }
3558
3559 static int
3560 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3561 {
3562         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3563         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3564         int ret;
3565
3566         if (!lut)
3567                 return -EINVAL;
3568
3569         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3570                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3571                                           lut, lut_size);
3572                 if (ret) {
3573                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3574                         return ret;
3575                 }
3576         } else {
3577                 uint32_t *lut_dw = (uint32_t *)lut;
3578                 uint16_t i, lut_size_dw = lut_size / 4;
3579
3580                 for (i = 0; i < lut_size_dw; i++)
3581                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3582         }
3583
3584         return 0;
3585 }
3586
3587 static int
3588 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3589 {
3590         struct i40e_pf *pf;
3591         struct i40e_hw *hw;
3592         int ret;
3593
3594         if (!vsi || !lut)
3595                 return -EINVAL;
3596
3597         pf = I40E_VSI_TO_PF(vsi);
3598         hw = I40E_VSI_TO_HW(vsi);
3599
3600         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3601                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3602                                           lut, lut_size);
3603                 if (ret) {
3604                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3605                         return ret;
3606                 }
3607         } else {
3608                 uint32_t *lut_dw = (uint32_t *)lut;
3609                 uint16_t i, lut_size_dw = lut_size / 4;
3610
3611                 for (i = 0; i < lut_size_dw; i++)
3612                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3613                 I40E_WRITE_FLUSH(hw);
3614         }
3615
3616         return 0;
3617 }
3618
3619 static int
3620 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3621                          struct rte_eth_rss_reta_entry64 *reta_conf,
3622                          uint16_t reta_size)
3623 {
3624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3625         uint16_t i, lut_size = pf->hash_lut_size;
3626         uint16_t idx, shift;
3627         uint8_t *lut;
3628         int ret;
3629
3630         if (reta_size != lut_size ||
3631                 reta_size > ETH_RSS_RETA_SIZE_512) {
3632                 PMD_DRV_LOG(ERR,
3633                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3634                         reta_size, lut_size);
3635                 return -EINVAL;
3636         }
3637
3638         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3639         if (!lut) {
3640                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3641                 return -ENOMEM;
3642         }
3643         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3644         if (ret)
3645                 goto out;
3646         for (i = 0; i < reta_size; i++) {
3647                 idx = i / RTE_RETA_GROUP_SIZE;
3648                 shift = i % RTE_RETA_GROUP_SIZE;
3649                 if (reta_conf[idx].mask & (1ULL << shift))
3650                         lut[i] = reta_conf[idx].reta[shift];
3651         }
3652         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3653
3654 out:
3655         rte_free(lut);
3656
3657         return ret;
3658 }
3659
3660 static int
3661 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3662                         struct rte_eth_rss_reta_entry64 *reta_conf,
3663                         uint16_t reta_size)
3664 {
3665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3666         uint16_t i, lut_size = pf->hash_lut_size;
3667         uint16_t idx, shift;
3668         uint8_t *lut;
3669         int ret;
3670
3671         if (reta_size != lut_size ||
3672                 reta_size > ETH_RSS_RETA_SIZE_512) {
3673                 PMD_DRV_LOG(ERR,
3674                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3675                         reta_size, lut_size);
3676                 return -EINVAL;
3677         }
3678
3679         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3680         if (!lut) {
3681                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3682                 return -ENOMEM;
3683         }
3684
3685         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3686         if (ret)
3687                 goto out;
3688         for (i = 0; i < reta_size; i++) {
3689                 idx = i / RTE_RETA_GROUP_SIZE;
3690                 shift = i % RTE_RETA_GROUP_SIZE;
3691                 if (reta_conf[idx].mask & (1ULL << shift))
3692                         reta_conf[idx].reta[shift] = lut[i];
3693         }
3694
3695 out:
3696         rte_free(lut);
3697
3698         return ret;
3699 }
3700
3701 /**
3702  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3703  * @hw:   pointer to the HW structure
3704  * @mem:  pointer to mem struct to fill out
3705  * @size: size of memory requested
3706  * @alignment: what to align the allocation to
3707  **/
3708 enum i40e_status_code
3709 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3710                         struct i40e_dma_mem *mem,
3711                         u64 size,
3712                         u32 alignment)
3713 {
3714         const struct rte_memzone *mz = NULL;
3715         char z_name[RTE_MEMZONE_NAMESIZE];
3716
3717         if (!mem)
3718                 return I40E_ERR_PARAM;
3719
3720         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3721         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3722                                          alignment, RTE_PGSIZE_2M);
3723         if (!mz)
3724                 return I40E_ERR_NO_MEMORY;
3725
3726         mem->size = size;
3727         mem->va = mz->addr;
3728         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3729         mem->zone = (const void *)mz;
3730         PMD_DRV_LOG(DEBUG,
3731                 "memzone %s allocated with physical address: %"PRIu64,
3732                 mz->name, mem->pa);
3733
3734         return I40E_SUCCESS;
3735 }
3736
3737 /**
3738  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3739  * @hw:   pointer to the HW structure
3740  * @mem:  ptr to mem struct to free
3741  **/
3742 enum i40e_status_code
3743 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3744                     struct i40e_dma_mem *mem)
3745 {
3746         if (!mem)
3747                 return I40E_ERR_PARAM;
3748
3749         PMD_DRV_LOG(DEBUG,
3750                 "memzone %s to be freed with physical address: %"PRIu64,
3751                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3752         rte_memzone_free((const struct rte_memzone *)mem->zone);
3753         mem->zone = NULL;
3754         mem->va = NULL;
3755         mem->pa = (u64)0;
3756
3757         return I40E_SUCCESS;
3758 }
3759
3760 /**
3761  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3762  * @hw:   pointer to the HW structure
3763  * @mem:  pointer to mem struct to fill out
3764  * @size: size of memory requested
3765  **/
3766 enum i40e_status_code
3767 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3768                          struct i40e_virt_mem *mem,
3769                          u32 size)
3770 {
3771         if (!mem)
3772                 return I40E_ERR_PARAM;
3773
3774         mem->size = size;
3775         mem->va = rte_zmalloc("i40e", size, 0);
3776
3777         if (mem->va)
3778                 return I40E_SUCCESS;
3779         else
3780                 return I40E_ERR_NO_MEMORY;
3781 }
3782
3783 /**
3784  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3785  * @hw:   pointer to the HW structure
3786  * @mem:  pointer to mem struct to free
3787  **/
3788 enum i40e_status_code
3789 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3790                      struct i40e_virt_mem *mem)
3791 {
3792         if (!mem)
3793                 return I40E_ERR_PARAM;
3794
3795         rte_free(mem->va);
3796         mem->va = NULL;
3797
3798         return I40E_SUCCESS;
3799 }
3800
3801 void
3802 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3803 {
3804         rte_spinlock_init(&sp->spinlock);
3805 }
3806
3807 void
3808 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3809 {
3810         rte_spinlock_lock(&sp->spinlock);
3811 }
3812
3813 void
3814 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3815 {
3816         rte_spinlock_unlock(&sp->spinlock);
3817 }
3818
3819 void
3820 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3821 {
3822         return;
3823 }
3824
3825 /**
3826  * Get the hardware capabilities, which will be parsed
3827  * and saved into struct i40e_hw.
3828  */
3829 static int
3830 i40e_get_cap(struct i40e_hw *hw)
3831 {
3832         struct i40e_aqc_list_capabilities_element_resp *buf;
3833         uint16_t len, size = 0;
3834         int ret;
3835
3836         /* Calculate a huge enough buff for saving response data temporarily */
3837         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3838                                                 I40E_MAX_CAP_ELE_NUM;
3839         buf = rte_zmalloc("i40e", len, 0);
3840         if (!buf) {
3841                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3842                 return I40E_ERR_NO_MEMORY;
3843         }
3844
3845         /* Get, parse the capabilities and save it to hw */
3846         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3847                         i40e_aqc_opc_list_func_capabilities, NULL);
3848         if (ret != I40E_SUCCESS)
3849                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3850
3851         /* Free the temporary buffer after being used */
3852         rte_free(buf);
3853
3854         return ret;
3855 }
3856
3857 static int
3858 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3859 {
3860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3861         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3862         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3863         uint16_t qp_count = 0, vsi_count = 0;
3864
3865         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3866                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3867                 return -EINVAL;
3868         }
3869         /* Add the parameter init for LFC */
3870         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3871         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3872         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3873
3874         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3875         pf->max_num_vsi = hw->func_caps.num_vsis;
3876         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3877         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3878         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3879
3880         /* FDir queue/VSI allocation */
3881         pf->fdir_qp_offset = 0;
3882         if (hw->func_caps.fd) {
3883                 pf->flags |= I40E_FLAG_FDIR;
3884                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3885         } else {
3886                 pf->fdir_nb_qps = 0;
3887         }
3888         qp_count += pf->fdir_nb_qps;
3889         vsi_count += 1;
3890
3891         /* LAN queue/VSI allocation */
3892         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3893         if (!hw->func_caps.rss) {
3894                 pf->lan_nb_qps = 1;
3895         } else {
3896                 pf->flags |= I40E_FLAG_RSS;
3897                 if (hw->mac.type == I40E_MAC_X722)
3898                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3899                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3900         }
3901         qp_count += pf->lan_nb_qps;
3902         vsi_count += 1;
3903
3904         /* VF queue/VSI allocation */
3905         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3906         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3907                 pf->flags |= I40E_FLAG_SRIOV;
3908                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3909                 pf->vf_num = pci_dev->max_vfs;
3910                 PMD_DRV_LOG(DEBUG,
3911                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3912                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3913         } else {
3914                 pf->vf_nb_qps = 0;
3915                 pf->vf_num = 0;
3916         }
3917         qp_count += pf->vf_nb_qps * pf->vf_num;
3918         vsi_count += pf->vf_num;
3919
3920         /* VMDq queue/VSI allocation */
3921         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3922         pf->vmdq_nb_qps = 0;
3923         pf->max_nb_vmdq_vsi = 0;
3924         if (hw->func_caps.vmdq) {
3925                 if (qp_count < hw->func_caps.num_tx_qp &&
3926                         vsi_count < hw->func_caps.num_vsis) {
3927                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3928                                 qp_count) / pf->vmdq_nb_qp_max;
3929
3930                         /* Limit the maximum number of VMDq vsi to the maximum
3931                          * ethdev can support
3932                          */
3933                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3934                                 hw->func_caps.num_vsis - vsi_count);
3935                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3936                                 ETH_64_POOLS);
3937                         if (pf->max_nb_vmdq_vsi) {
3938                                 pf->flags |= I40E_FLAG_VMDQ;
3939                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3940                                 PMD_DRV_LOG(DEBUG,
3941                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3942                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3943                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3944                         } else {
3945                                 PMD_DRV_LOG(INFO,
3946                                         "No enough queues left for VMDq");
3947                         }
3948                 } else {
3949                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3950                 }
3951         }
3952         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3953         vsi_count += pf->max_nb_vmdq_vsi;
3954
3955         if (hw->func_caps.dcb)
3956                 pf->flags |= I40E_FLAG_DCB;
3957
3958         if (qp_count > hw->func_caps.num_tx_qp) {
3959                 PMD_DRV_LOG(ERR,
3960                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3961                         qp_count, hw->func_caps.num_tx_qp);
3962                 return -EINVAL;
3963         }
3964         if (vsi_count > hw->func_caps.num_vsis) {
3965                 PMD_DRV_LOG(ERR,
3966                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3967                         vsi_count, hw->func_caps.num_vsis);
3968                 return -EINVAL;
3969         }
3970
3971         return 0;
3972 }
3973
3974 static int
3975 i40e_pf_get_switch_config(struct i40e_pf *pf)
3976 {
3977         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3978         struct i40e_aqc_get_switch_config_resp *switch_config;
3979         struct i40e_aqc_switch_config_element_resp *element;
3980         uint16_t start_seid = 0, num_reported;
3981         int ret;
3982
3983         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3984                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3985         if (!switch_config) {
3986                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3987                 return -ENOMEM;
3988         }
3989
3990         /* Get the switch configurations */
3991         ret = i40e_aq_get_switch_config(hw, switch_config,
3992                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3993         if (ret != I40E_SUCCESS) {
3994                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3995                 goto fail;
3996         }
3997         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3998         if (num_reported != 1) { /* The number should be 1 */
3999                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4000                 goto fail;
4001         }
4002
4003         /* Parse the switch configuration elements */
4004         element = &(switch_config->element[0]);
4005         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4006                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4007                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4008         } else
4009                 PMD_DRV_LOG(INFO, "Unknown element type");
4010
4011 fail:
4012         rte_free(switch_config);
4013
4014         return ret;
4015 }
4016
4017 static int
4018 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4019                         uint32_t num)
4020 {
4021         struct pool_entry *entry;
4022
4023         if (pool == NULL || num == 0)
4024                 return -EINVAL;
4025
4026         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4027         if (entry == NULL) {
4028                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4029                 return -ENOMEM;
4030         }
4031
4032         /* queue heap initialize */
4033         pool->num_free = num;
4034         pool->num_alloc = 0;
4035         pool->base = base;
4036         LIST_INIT(&pool->alloc_list);
4037         LIST_INIT(&pool->free_list);
4038
4039         /* Initialize element  */
4040         entry->base = 0;
4041         entry->len = num;
4042
4043         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4044         return 0;
4045 }
4046
4047 static void
4048 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4049 {
4050         struct pool_entry *entry, *next_entry;
4051
4052         if (pool == NULL)
4053                 return;
4054
4055         for (entry = LIST_FIRST(&pool->alloc_list);
4056                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4057                         entry = next_entry) {
4058                 LIST_REMOVE(entry, next);
4059                 rte_free(entry);
4060         }
4061
4062         for (entry = LIST_FIRST(&pool->free_list);
4063                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4064                         entry = next_entry) {
4065                 LIST_REMOVE(entry, next);
4066                 rte_free(entry);
4067         }
4068
4069         pool->num_free = 0;
4070         pool->num_alloc = 0;
4071         pool->base = 0;
4072         LIST_INIT(&pool->alloc_list);
4073         LIST_INIT(&pool->free_list);
4074 }
4075
4076 static int
4077 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4078                        uint32_t base)
4079 {
4080         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4081         uint32_t pool_offset;
4082         int insert;
4083
4084         if (pool == NULL) {
4085                 PMD_DRV_LOG(ERR, "Invalid parameter");
4086                 return -EINVAL;
4087         }
4088
4089         pool_offset = base - pool->base;
4090         /* Lookup in alloc list */
4091         LIST_FOREACH(entry, &pool->alloc_list, next) {
4092                 if (entry->base == pool_offset) {
4093                         valid_entry = entry;
4094                         LIST_REMOVE(entry, next);
4095                         break;
4096                 }
4097         }
4098
4099         /* Not find, return */
4100         if (valid_entry == NULL) {
4101                 PMD_DRV_LOG(ERR, "Failed to find entry");
4102                 return -EINVAL;
4103         }
4104
4105         /**
4106          * Found it, move it to free list  and try to merge.
4107          * In order to make merge easier, always sort it by qbase.
4108          * Find adjacent prev and last entries.
4109          */
4110         prev = next = NULL;
4111         LIST_FOREACH(entry, &pool->free_list, next) {
4112                 if (entry->base > valid_entry->base) {
4113                         next = entry;
4114                         break;
4115                 }
4116                 prev = entry;
4117         }
4118
4119         insert = 0;
4120         /* Try to merge with next one*/
4121         if (next != NULL) {
4122                 /* Merge with next one */
4123                 if (valid_entry->base + valid_entry->len == next->base) {
4124                         next->base = valid_entry->base;
4125                         next->len += valid_entry->len;
4126                         rte_free(valid_entry);
4127                         valid_entry = next;
4128                         insert = 1;
4129                 }
4130         }
4131
4132         if (prev != NULL) {
4133                 /* Merge with previous one */
4134                 if (prev->base + prev->len == valid_entry->base) {
4135                         prev->len += valid_entry->len;
4136                         /* If it merge with next one, remove next node */
4137                         if (insert == 1) {
4138                                 LIST_REMOVE(valid_entry, next);
4139                                 rte_free(valid_entry);
4140                         } else {
4141                                 rte_free(valid_entry);
4142                                 insert = 1;
4143                         }
4144                 }
4145         }
4146
4147         /* Not find any entry to merge, insert */
4148         if (insert == 0) {
4149                 if (prev != NULL)
4150                         LIST_INSERT_AFTER(prev, valid_entry, next);
4151                 else if (next != NULL)
4152                         LIST_INSERT_BEFORE(next, valid_entry, next);
4153                 else /* It's empty list, insert to head */
4154                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4155         }
4156
4157         pool->num_free += valid_entry->len;
4158         pool->num_alloc -= valid_entry->len;
4159
4160         return 0;
4161 }
4162
4163 static int
4164 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4165                        uint16_t num)
4166 {
4167         struct pool_entry *entry, *valid_entry;
4168
4169         if (pool == NULL || num == 0) {
4170                 PMD_DRV_LOG(ERR, "Invalid parameter");
4171                 return -EINVAL;
4172         }
4173
4174         if (pool->num_free < num) {
4175                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4176                             num, pool->num_free);
4177                 return -ENOMEM;
4178         }
4179
4180         valid_entry = NULL;
4181         /* Lookup  in free list and find most fit one */
4182         LIST_FOREACH(entry, &pool->free_list, next) {
4183                 if (entry->len >= num) {
4184                         /* Find best one */
4185                         if (entry->len == num) {
4186                                 valid_entry = entry;
4187                                 break;
4188                         }
4189                         if (valid_entry == NULL || valid_entry->len > entry->len)
4190                                 valid_entry = entry;
4191                 }
4192         }
4193
4194         /* Not find one to satisfy the request, return */
4195         if (valid_entry == NULL) {
4196                 PMD_DRV_LOG(ERR, "No valid entry found");
4197                 return -ENOMEM;
4198         }
4199         /**
4200          * The entry have equal queue number as requested,
4201          * remove it from alloc_list.
4202          */
4203         if (valid_entry->len == num) {
4204                 LIST_REMOVE(valid_entry, next);
4205         } else {
4206                 /**
4207                  * The entry have more numbers than requested,
4208                  * create a new entry for alloc_list and minus its
4209                  * queue base and number in free_list.
4210                  */
4211                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4212                 if (entry == NULL) {
4213                         PMD_DRV_LOG(ERR,
4214                                 "Failed to allocate memory for resource pool");
4215                         return -ENOMEM;
4216                 }
4217                 entry->base = valid_entry->base;
4218                 entry->len = num;
4219                 valid_entry->base += num;
4220                 valid_entry->len -= num;
4221                 valid_entry = entry;
4222         }
4223
4224         /* Insert it into alloc list, not sorted */
4225         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4226
4227         pool->num_free -= valid_entry->len;
4228         pool->num_alloc += valid_entry->len;
4229
4230         return valid_entry->base + pool->base;
4231 }
4232
4233 /**
4234  * bitmap_is_subset - Check whether src2 is subset of src1
4235  **/
4236 static inline int
4237 bitmap_is_subset(uint8_t src1, uint8_t src2)
4238 {
4239         return !((src1 ^ src2) & src2);
4240 }
4241
4242 static enum i40e_status_code
4243 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4244 {
4245         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4246
4247         /* If DCB is not supported, only default TC is supported */
4248         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4249                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4250                 return I40E_NOT_SUPPORTED;
4251         }
4252
4253         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4254                 PMD_DRV_LOG(ERR,
4255                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4256                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4257                 return I40E_NOT_SUPPORTED;
4258         }
4259         return I40E_SUCCESS;
4260 }
4261
4262 int
4263 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4264                                 struct i40e_vsi_vlan_pvid_info *info)
4265 {
4266         struct i40e_hw *hw;
4267         struct i40e_vsi_context ctxt;
4268         uint8_t vlan_flags = 0;
4269         int ret;
4270
4271         if (vsi == NULL || info == NULL) {
4272                 PMD_DRV_LOG(ERR, "invalid parameters");
4273                 return I40E_ERR_PARAM;
4274         }
4275
4276         if (info->on) {
4277                 vsi->info.pvid = info->config.pvid;
4278                 /**
4279                  * If insert pvid is enabled, only tagged pkts are
4280                  * allowed to be sent out.
4281                  */
4282                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4283                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4284         } else {
4285                 vsi->info.pvid = 0;
4286                 if (info->config.reject.tagged == 0)
4287                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4288
4289                 if (info->config.reject.untagged == 0)
4290                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4291         }
4292         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4293                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4294         vsi->info.port_vlan_flags |= vlan_flags;
4295         vsi->info.valid_sections =
4296                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4297         memset(&ctxt, 0, sizeof(ctxt));
4298         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4299         ctxt.seid = vsi->seid;
4300
4301         hw = I40E_VSI_TO_HW(vsi);
4302         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4303         if (ret != I40E_SUCCESS)
4304                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4305
4306         return ret;
4307 }
4308
4309 static int
4310 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4311 {
4312         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4313         int i, ret;
4314         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4315
4316         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4317         if (ret != I40E_SUCCESS)
4318                 return ret;
4319
4320         if (!vsi->seid) {
4321                 PMD_DRV_LOG(ERR, "seid not valid");
4322                 return -EINVAL;
4323         }
4324
4325         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4326         tc_bw_data.tc_valid_bits = enabled_tcmap;
4327         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4328                 tc_bw_data.tc_bw_credits[i] =
4329                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4330
4331         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4332         if (ret != I40E_SUCCESS) {
4333                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4334                 return ret;
4335         }
4336
4337         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4338                                         sizeof(vsi->info.qs_handle));
4339         return I40E_SUCCESS;
4340 }
4341
4342 static enum i40e_status_code
4343 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4344                                  struct i40e_aqc_vsi_properties_data *info,
4345                                  uint8_t enabled_tcmap)
4346 {
4347         enum i40e_status_code ret;
4348         int i, total_tc = 0;
4349         uint16_t qpnum_per_tc, bsf, qp_idx;
4350
4351         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4352         if (ret != I40E_SUCCESS)
4353                 return ret;
4354
4355         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4356                 if (enabled_tcmap & (1 << i))
4357                         total_tc++;
4358         if (total_tc == 0)
4359                 total_tc = 1;
4360         vsi->enabled_tc = enabled_tcmap;
4361
4362         /* Number of queues per enabled TC */
4363         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4364         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4365         bsf = rte_bsf32(qpnum_per_tc);
4366
4367         /* Adjust the queue number to actual queues that can be applied */
4368         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4369                 vsi->nb_qps = qpnum_per_tc * total_tc;
4370
4371         /**
4372          * Configure TC and queue mapping parameters, for enabled TC,
4373          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4374          * default queue will serve it.
4375          */
4376         qp_idx = 0;
4377         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4378                 if (vsi->enabled_tc & (1 << i)) {
4379                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4380                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4381                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4382                         qp_idx += qpnum_per_tc;
4383                 } else
4384                         info->tc_mapping[i] = 0;
4385         }
4386
4387         /* Associate queue number with VSI */
4388         if (vsi->type == I40E_VSI_SRIOV) {
4389                 info->mapping_flags |=
4390                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4391                 for (i = 0; i < vsi->nb_qps; i++)
4392                         info->queue_mapping[i] =
4393                                 rte_cpu_to_le_16(vsi->base_queue + i);
4394         } else {
4395                 info->mapping_flags |=
4396                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4397                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4398         }
4399         info->valid_sections |=
4400                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4401
4402         return I40E_SUCCESS;
4403 }
4404
4405 static int
4406 i40e_veb_release(struct i40e_veb *veb)
4407 {
4408         struct i40e_vsi *vsi;
4409         struct i40e_hw *hw;
4410
4411         if (veb == NULL)
4412                 return -EINVAL;
4413
4414         if (!TAILQ_EMPTY(&veb->head)) {
4415                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4416                 return -EACCES;
4417         }
4418         /* associate_vsi field is NULL for floating VEB */
4419         if (veb->associate_vsi != NULL) {
4420                 vsi = veb->associate_vsi;
4421                 hw = I40E_VSI_TO_HW(vsi);
4422
4423                 vsi->uplink_seid = veb->uplink_seid;
4424                 vsi->veb = NULL;
4425         } else {
4426                 veb->associate_pf->main_vsi->floating_veb = NULL;
4427                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4428         }
4429
4430         i40e_aq_delete_element(hw, veb->seid, NULL);
4431         rte_free(veb);
4432         return I40E_SUCCESS;
4433 }
4434
4435 /* Setup a veb */
4436 static struct i40e_veb *
4437 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4438 {
4439         struct i40e_veb *veb;
4440         int ret;
4441         struct i40e_hw *hw;
4442
4443         if (pf == NULL) {
4444                 PMD_DRV_LOG(ERR,
4445                             "veb setup failed, associated PF shouldn't null");
4446                 return NULL;
4447         }
4448         hw = I40E_PF_TO_HW(pf);
4449
4450         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4451         if (!veb) {
4452                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4453                 goto fail;
4454         }
4455
4456         veb->associate_vsi = vsi;
4457         veb->associate_pf = pf;
4458         TAILQ_INIT(&veb->head);
4459         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4460
4461         /* create floating veb if vsi is NULL */
4462         if (vsi != NULL) {
4463                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4464                                       I40E_DEFAULT_TCMAP, false,
4465                                       &veb->seid, false, NULL);
4466         } else {
4467                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4468                                       true, &veb->seid, false, NULL);
4469         }
4470
4471         if (ret != I40E_SUCCESS) {
4472                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4473                             hw->aq.asq_last_status);
4474                 goto fail;
4475         }
4476         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4477
4478         /* get statistics index */
4479         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4480                                 &veb->stats_idx, NULL, NULL, NULL);
4481         if (ret != I40E_SUCCESS) {
4482                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4483                             hw->aq.asq_last_status);
4484                 goto fail;
4485         }
4486         /* Get VEB bandwidth, to be implemented */
4487         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4488         if (vsi)
4489                 vsi->uplink_seid = veb->seid;
4490
4491         return veb;
4492 fail:
4493         rte_free(veb);
4494         return NULL;
4495 }
4496
4497 int
4498 i40e_vsi_release(struct i40e_vsi *vsi)
4499 {
4500         struct i40e_pf *pf;
4501         struct i40e_hw *hw;
4502         struct i40e_vsi_list *vsi_list;
4503         void *temp;
4504         int ret;
4505         struct i40e_mac_filter *f;
4506         uint16_t user_param;
4507
4508         if (!vsi)
4509                 return I40E_SUCCESS;
4510
4511         if (!vsi->adapter)
4512                 return -EFAULT;
4513
4514         user_param = vsi->user_param;
4515
4516         pf = I40E_VSI_TO_PF(vsi);
4517         hw = I40E_VSI_TO_HW(vsi);
4518
4519         /* VSI has child to attach, release child first */
4520         if (vsi->veb) {
4521                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4522                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4523                                 return -1;
4524                 }
4525                 i40e_veb_release(vsi->veb);
4526         }
4527
4528         if (vsi->floating_veb) {
4529                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4530                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4531                                 return -1;
4532                 }
4533         }
4534
4535         /* Remove all macvlan filters of the VSI */
4536         i40e_vsi_remove_all_macvlan_filter(vsi);
4537         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4538                 rte_free(f);
4539
4540         if (vsi->type != I40E_VSI_MAIN &&
4541             ((vsi->type != I40E_VSI_SRIOV) ||
4542             !pf->floating_veb_list[user_param])) {
4543                 /* Remove vsi from parent's sibling list */
4544                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4545                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4546                         return I40E_ERR_PARAM;
4547                 }
4548                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4549                                 &vsi->sib_vsi_list, list);
4550
4551                 /* Remove all switch element of the VSI */
4552                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4553                 if (ret != I40E_SUCCESS)
4554                         PMD_DRV_LOG(ERR, "Failed to delete element");
4555         }
4556
4557         if ((vsi->type == I40E_VSI_SRIOV) &&
4558             pf->floating_veb_list[user_param]) {
4559                 /* Remove vsi from parent's sibling list */
4560                 if (vsi->parent_vsi == NULL ||
4561                     vsi->parent_vsi->floating_veb == NULL) {
4562                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4563                         return I40E_ERR_PARAM;
4564                 }
4565                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4566                              &vsi->sib_vsi_list, list);
4567
4568                 /* Remove all switch element of the VSI */
4569                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4570                 if (ret != I40E_SUCCESS)
4571                         PMD_DRV_LOG(ERR, "Failed to delete element");
4572         }
4573
4574         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4575
4576         if (vsi->type != I40E_VSI_SRIOV)
4577                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4578         rte_free(vsi);
4579
4580         return I40E_SUCCESS;
4581 }
4582
4583 static int
4584 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4585 {
4586         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4587         struct i40e_aqc_remove_macvlan_element_data def_filter;
4588         struct i40e_mac_filter_info filter;
4589         int ret;
4590
4591         if (vsi->type != I40E_VSI_MAIN)
4592                 return I40E_ERR_CONFIG;
4593         memset(&def_filter, 0, sizeof(def_filter));
4594         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4595                                         ETH_ADDR_LEN);
4596         def_filter.vlan_tag = 0;
4597         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4598                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4599         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4600         if (ret != I40E_SUCCESS) {
4601                 struct i40e_mac_filter *f;
4602                 struct ether_addr *mac;
4603
4604                 PMD_DRV_LOG(DEBUG,
4605                             "Cannot remove the default macvlan filter");
4606                 /* It needs to add the permanent mac into mac list */
4607                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4608                 if (f == NULL) {
4609                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4610                         return I40E_ERR_NO_MEMORY;
4611                 }
4612                 mac = &f->mac_info.mac_addr;
4613                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4614                                 ETH_ADDR_LEN);
4615                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4616                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4617                 vsi->mac_num++;
4618
4619                 return ret;
4620         }
4621         (void)rte_memcpy(&filter.mac_addr,
4622                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4623         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4624         return i40e_vsi_add_mac(vsi, &filter);
4625 }
4626
4627 /*
4628  * i40e_vsi_get_bw_config - Query VSI BW Information
4629  * @vsi: the VSI to be queried
4630  *
4631  * Returns 0 on success, negative value on failure
4632  */
4633 static enum i40e_status_code
4634 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4635 {
4636         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4637         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4638         struct i40e_hw *hw = &vsi->adapter->hw;
4639         i40e_status ret;
4640         int i;
4641         uint32_t bw_max;
4642
4643         memset(&bw_config, 0, sizeof(bw_config));
4644         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4645         if (ret != I40E_SUCCESS) {
4646                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4647                             hw->aq.asq_last_status);
4648                 return ret;
4649         }
4650
4651         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4652         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4653                                         &ets_sla_config, NULL);
4654         if (ret != I40E_SUCCESS) {
4655                 PMD_DRV_LOG(ERR,
4656                         "VSI failed to get TC bandwdith configuration %u",
4657                         hw->aq.asq_last_status);
4658                 return ret;
4659         }
4660
4661         /* store and print out BW info */
4662         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4663         vsi->bw_info.bw_max = bw_config.max_bw;
4664         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4665         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4666         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4667                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4668                      I40E_16_BIT_WIDTH);
4669         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4670                 vsi->bw_info.bw_ets_share_credits[i] =
4671                                 ets_sla_config.share_credits[i];
4672                 vsi->bw_info.bw_ets_credits[i] =
4673                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4674                 /* 4 bits per TC, 4th bit is reserved */
4675                 vsi->bw_info.bw_ets_max[i] =
4676                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4677                                   RTE_LEN2MASK(3, uint8_t));
4678                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4679                             vsi->bw_info.bw_ets_share_credits[i]);
4680                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4681                             vsi->bw_info.bw_ets_credits[i]);
4682                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4683                             vsi->bw_info.bw_ets_max[i]);
4684         }
4685
4686         return I40E_SUCCESS;
4687 }
4688
4689 /* i40e_enable_pf_lb
4690  * @pf: pointer to the pf structure
4691  *
4692  * allow loopback on pf
4693  */
4694 static inline void
4695 i40e_enable_pf_lb(struct i40e_pf *pf)
4696 {
4697         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4698         struct i40e_vsi_context ctxt;
4699         int ret;
4700
4701         /* Use the FW API if FW >= v5.0 */
4702         if (hw->aq.fw_maj_ver < 5) {
4703                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4704                 return;
4705         }
4706
4707         memset(&ctxt, 0, sizeof(ctxt));
4708         ctxt.seid = pf->main_vsi_seid;
4709         ctxt.pf_num = hw->pf_id;
4710         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4711         if (ret) {
4712                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4713                             ret, hw->aq.asq_last_status);
4714                 return;
4715         }
4716         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4717         ctxt.info.valid_sections =
4718                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4719         ctxt.info.switch_id |=
4720                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4721
4722         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4723         if (ret)
4724                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4725                             hw->aq.asq_last_status);
4726 }
4727
4728 /* Setup a VSI */
4729 struct i40e_vsi *
4730 i40e_vsi_setup(struct i40e_pf *pf,
4731                enum i40e_vsi_type type,
4732                struct i40e_vsi *uplink_vsi,
4733                uint16_t user_param)
4734 {
4735         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4736         struct i40e_vsi *vsi;
4737         struct i40e_mac_filter_info filter;
4738         int ret;
4739         struct i40e_vsi_context ctxt;
4740         struct ether_addr broadcast =
4741                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4742
4743         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4744             uplink_vsi == NULL) {
4745                 PMD_DRV_LOG(ERR,
4746                         "VSI setup failed, VSI link shouldn't be NULL");
4747                 return NULL;
4748         }
4749
4750         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4751                 PMD_DRV_LOG(ERR,
4752                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4753                 return NULL;
4754         }
4755
4756         /* two situations
4757          * 1.type is not MAIN and uplink vsi is not NULL
4758          * If uplink vsi didn't setup VEB, create one first under veb field
4759          * 2.type is SRIOV and the uplink is NULL
4760          * If floating VEB is NULL, create one veb under floating veb field
4761          */
4762
4763         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4764             uplink_vsi->veb == NULL) {
4765                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4766
4767                 if (uplink_vsi->veb == NULL) {
4768                         PMD_DRV_LOG(ERR, "VEB setup failed");
4769                         return NULL;
4770                 }
4771                 /* set ALLOWLOOPBACk on pf, when veb is created */
4772                 i40e_enable_pf_lb(pf);
4773         }
4774
4775         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4776             pf->main_vsi->floating_veb == NULL) {
4777                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4778
4779                 if (pf->main_vsi->floating_veb == NULL) {
4780                         PMD_DRV_LOG(ERR, "VEB setup failed");
4781                         return NULL;
4782                 }
4783         }
4784
4785         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4786         if (!vsi) {
4787                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4788                 return NULL;
4789         }
4790         TAILQ_INIT(&vsi->mac_list);
4791         vsi->type = type;
4792         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4793         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4794         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4795         vsi->user_param = user_param;
4796         vsi->vlan_anti_spoof_on = 0;
4797         vsi->vlan_filter_on = 0;
4798         /* Allocate queues */
4799         switch (vsi->type) {
4800         case I40E_VSI_MAIN  :
4801                 vsi->nb_qps = pf->lan_nb_qps;
4802                 break;
4803         case I40E_VSI_SRIOV :
4804                 vsi->nb_qps = pf->vf_nb_qps;
4805                 break;
4806         case I40E_VSI_VMDQ2:
4807                 vsi->nb_qps = pf->vmdq_nb_qps;
4808                 break;
4809         case I40E_VSI_FDIR:
4810                 vsi->nb_qps = pf->fdir_nb_qps;
4811                 break;
4812         default:
4813                 goto fail_mem;
4814         }
4815         /*
4816          * The filter status descriptor is reported in rx queue 0,
4817          * while the tx queue for fdir filter programming has no
4818          * such constraints, can be non-zero queues.
4819          * To simplify it, choose FDIR vsi use queue 0 pair.
4820          * To make sure it will use queue 0 pair, queue allocation
4821          * need be done before this function is called
4822          */
4823         if (type != I40E_VSI_FDIR) {
4824                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4825                         if (ret < 0) {
4826                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4827                                                 vsi->seid, ret);
4828                                 goto fail_mem;
4829                         }
4830                         vsi->base_queue = ret;
4831         } else
4832                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4833
4834         /* VF has MSIX interrupt in VF range, don't allocate here */
4835         if (type == I40E_VSI_MAIN) {
4836                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4837                                           RTE_MIN(vsi->nb_qps,
4838                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4839                 if (ret < 0) {
4840                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4841                                     vsi->seid, ret);
4842                         goto fail_queue_alloc;
4843                 }
4844                 vsi->msix_intr = ret;
4845                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4846         } else if (type != I40E_VSI_SRIOV) {
4847                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4848                 if (ret < 0) {
4849                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4850                         goto fail_queue_alloc;
4851                 }
4852                 vsi->msix_intr = ret;
4853                 vsi->nb_msix = 1;
4854         } else {
4855                 vsi->msix_intr = 0;
4856                 vsi->nb_msix = 0;
4857         }
4858
4859         /* Add VSI */
4860         if (type == I40E_VSI_MAIN) {
4861                 /* For main VSI, no need to add since it's default one */
4862                 vsi->uplink_seid = pf->mac_seid;
4863                 vsi->seid = pf->main_vsi_seid;
4864                 /* Bind queues with specific MSIX interrupt */
4865                 /**
4866                  * Needs 2 interrupt at least, one for misc cause which will
4867                  * enabled from OS side, Another for queues binding the
4868                  * interrupt from device side only.
4869                  */
4870
4871                 /* Get default VSI parameters from hardware */
4872                 memset(&ctxt, 0, sizeof(ctxt));
4873                 ctxt.seid = vsi->seid;
4874                 ctxt.pf_num = hw->pf_id;
4875                 ctxt.uplink_seid = vsi->uplink_seid;
4876                 ctxt.vf_num = 0;
4877                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4878                 if (ret != I40E_SUCCESS) {
4879                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4880                         goto fail_msix_alloc;
4881                 }
4882                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4883                         sizeof(struct i40e_aqc_vsi_properties_data));
4884                 vsi->vsi_id = ctxt.vsi_number;
4885                 vsi->info.valid_sections = 0;
4886
4887                 /* Configure tc, enabled TC0 only */
4888                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4889                         I40E_SUCCESS) {
4890                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4891                         goto fail_msix_alloc;
4892                 }
4893
4894                 /* TC, queue mapping */
4895                 memset(&ctxt, 0, sizeof(ctxt));
4896                 vsi->info.valid_sections |=
4897                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4898                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4899                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4900                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4901                         sizeof(struct i40e_aqc_vsi_properties_data));
4902                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4903                                                 I40E_DEFAULT_TCMAP);
4904                 if (ret != I40E_SUCCESS) {
4905                         PMD_DRV_LOG(ERR,
4906                                 "Failed to configure TC queue mapping");
4907                         goto fail_msix_alloc;
4908                 }
4909                 ctxt.seid = vsi->seid;
4910                 ctxt.pf_num = hw->pf_id;
4911                 ctxt.uplink_seid = vsi->uplink_seid;
4912                 ctxt.vf_num = 0;
4913
4914                 /* Update VSI parameters */
4915                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4916                 if (ret != I40E_SUCCESS) {
4917                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4918                         goto fail_msix_alloc;
4919                 }
4920
4921                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4922                                                 sizeof(vsi->info.tc_mapping));
4923                 (void)rte_memcpy(&vsi->info.queue_mapping,
4924                                 &ctxt.info.queue_mapping,
4925                         sizeof(vsi->info.queue_mapping));
4926                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4927                 vsi->info.valid_sections = 0;
4928
4929                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4930                                 ETH_ADDR_LEN);
4931
4932                 /**
4933                  * Updating default filter settings are necessary to prevent
4934                  * reception of tagged packets.
4935                  * Some old firmware configurations load a default macvlan
4936                  * filter which accepts both tagged and untagged packets.
4937                  * The updating is to use a normal filter instead if needed.
4938                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4939                  * The firmware with correct configurations load the default
4940                  * macvlan filter which is expected and cannot be removed.
4941                  */
4942                 i40e_update_default_filter_setting(vsi);
4943                 i40e_config_qinq(hw, vsi);
4944         } else if (type == I40E_VSI_SRIOV) {
4945                 memset(&ctxt, 0, sizeof(ctxt));
4946                 /**
4947                  * For other VSI, the uplink_seid equals to uplink VSI's
4948                  * uplink_seid since they share same VEB
4949                  */
4950                 if (uplink_vsi == NULL)
4951                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4952                 else
4953                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4954                 ctxt.pf_num = hw->pf_id;
4955                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4956                 ctxt.uplink_seid = vsi->uplink_seid;
4957                 ctxt.connection_type = 0x1;
4958                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4959
4960                 /* Use the VEB configuration if FW >= v5.0 */
4961                 if (hw->aq.fw_maj_ver >= 5) {
4962                         /* Configure switch ID */
4963                         ctxt.info.valid_sections |=
4964                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4965                         ctxt.info.switch_id =
4966                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4967                 }
4968
4969                 /* Configure port/vlan */
4970                 ctxt.info.valid_sections |=
4971                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4972                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4973                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4974                                                 hw->func_caps.enabled_tcmap);
4975                 if (ret != I40E_SUCCESS) {
4976                         PMD_DRV_LOG(ERR,
4977                                 "Failed to configure TC queue mapping");
4978                         goto fail_msix_alloc;
4979                 }
4980
4981                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4982                 ctxt.info.valid_sections |=
4983                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4984                 /**
4985                  * Since VSI is not created yet, only configure parameter,
4986                  * will add vsi below.
4987                  */
4988
4989                 i40e_config_qinq(hw, vsi);
4990         } else if (type == I40E_VSI_VMDQ2) {
4991                 memset(&ctxt, 0, sizeof(ctxt));
4992                 /*
4993                  * For other VSI, the uplink_seid equals to uplink VSI's
4994                  * uplink_seid since they share same VEB
4995                  */
4996                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4997                 ctxt.pf_num = hw->pf_id;
4998                 ctxt.vf_num = 0;
4999                 ctxt.uplink_seid = vsi->uplink_seid;
5000                 ctxt.connection_type = 0x1;
5001                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5002
5003                 ctxt.info.valid_sections |=
5004                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5005                 /* user_param carries flag to enable loop back */
5006                 if (user_param) {
5007                         ctxt.info.switch_id =
5008                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5009                         ctxt.info.switch_id |=
5010                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5011                 }
5012
5013                 /* Configure port/vlan */
5014                 ctxt.info.valid_sections |=
5015                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5016                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5017                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5018                                                 I40E_DEFAULT_TCMAP);
5019                 if (ret != I40E_SUCCESS) {
5020                         PMD_DRV_LOG(ERR,
5021                                 "Failed to configure TC queue mapping");
5022                         goto fail_msix_alloc;
5023                 }
5024                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5025                 ctxt.info.valid_sections |=
5026                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5027         } else if (type == I40E_VSI_FDIR) {
5028                 memset(&ctxt, 0, sizeof(ctxt));
5029                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5030                 ctxt.pf_num = hw->pf_id;
5031                 ctxt.vf_num = 0;
5032                 ctxt.uplink_seid = vsi->uplink_seid;
5033                 ctxt.connection_type = 0x1;     /* regular data port */
5034                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5035                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5036                                                 I40E_DEFAULT_TCMAP);
5037                 if (ret != I40E_SUCCESS) {
5038                         PMD_DRV_LOG(ERR,
5039                                 "Failed to configure TC queue mapping.");
5040                         goto fail_msix_alloc;
5041                 }
5042                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5043                 ctxt.info.valid_sections |=
5044                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5045         } else {
5046                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5047                 goto fail_msix_alloc;
5048         }
5049
5050         if (vsi->type != I40E_VSI_MAIN) {
5051                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5052                 if (ret != I40E_SUCCESS) {
5053                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5054                                     hw->aq.asq_last_status);
5055                         goto fail_msix_alloc;
5056                 }
5057                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5058                 vsi->info.valid_sections = 0;
5059                 vsi->seid = ctxt.seid;
5060                 vsi->vsi_id = ctxt.vsi_number;
5061                 vsi->sib_vsi_list.vsi = vsi;
5062                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5063                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5064                                           &vsi->sib_vsi_list, list);
5065                 } else {
5066                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5067                                           &vsi->sib_vsi_list, list);
5068                 }
5069         }
5070
5071         /* MAC/VLAN configuration */
5072         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5073         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5074
5075         ret = i40e_vsi_add_mac(vsi, &filter);
5076         if (ret != I40E_SUCCESS) {
5077                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5078                 goto fail_msix_alloc;
5079         }
5080
5081         /* Get VSI BW information */
5082         i40e_vsi_get_bw_config(vsi);
5083         return vsi;
5084 fail_msix_alloc:
5085         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5086 fail_queue_alloc:
5087         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5088 fail_mem:
5089         rte_free(vsi);
5090         return NULL;
5091 }
5092
5093 /* Configure vlan filter on or off */
5094 int
5095 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5096 {
5097         int i, num;
5098         struct i40e_mac_filter *f;
5099         void *temp;
5100         struct i40e_mac_filter_info *mac_filter;
5101         enum rte_mac_filter_type desired_filter;
5102         int ret = I40E_SUCCESS;
5103
5104         if (on) {
5105                 /* Filter to match MAC and VLAN */
5106                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5107         } else {
5108                 /* Filter to match only MAC */
5109                 desired_filter = RTE_MAC_PERFECT_MATCH;
5110         }
5111
5112         num = vsi->mac_num;
5113
5114         mac_filter = rte_zmalloc("mac_filter_info_data",
5115                                  num * sizeof(*mac_filter), 0);
5116         if (mac_filter == NULL) {
5117                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5118                 return I40E_ERR_NO_MEMORY;
5119         }
5120
5121         i = 0;
5122
5123         /* Remove all existing mac */
5124         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5125                 mac_filter[i] = f->mac_info;
5126                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5127                 if (ret) {
5128                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5129                                     on ? "enable" : "disable");
5130                         goto DONE;
5131                 }
5132                 i++;
5133         }
5134
5135         /* Override with new filter */
5136         for (i = 0; i < num; i++) {
5137                 mac_filter[i].filter_type = desired_filter;
5138                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5139                 if (ret) {
5140                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5141                                     on ? "enable" : "disable");
5142                         goto DONE;
5143                 }
5144         }
5145
5146 DONE:
5147         rte_free(mac_filter);
5148         return ret;
5149 }
5150
5151 /* Configure vlan stripping on or off */
5152 int
5153 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5154 {
5155         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5156         struct i40e_vsi_context ctxt;
5157         uint8_t vlan_flags;
5158         int ret = I40E_SUCCESS;
5159
5160         /* Check if it has been already on or off */
5161         if (vsi->info.valid_sections &
5162                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5163                 if (on) {
5164                         if ((vsi->info.port_vlan_flags &
5165                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5166                                 return 0; /* already on */
5167                 } else {
5168                         if ((vsi->info.port_vlan_flags &
5169                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5170                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5171                                 return 0; /* already off */
5172                 }
5173         }
5174
5175         if (on)
5176                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5177         else
5178                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5179         vsi->info.valid_sections =
5180                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5181         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5182         vsi->info.port_vlan_flags |= vlan_flags;
5183         ctxt.seid = vsi->seid;
5184         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5185         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5186         if (ret)
5187                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5188                             on ? "enable" : "disable");
5189
5190         return ret;
5191 }
5192
5193 static int
5194 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5195 {
5196         struct rte_eth_dev_data *data = dev->data;
5197         int ret;
5198         int mask = 0;
5199
5200         /* Apply vlan offload setting */
5201         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5202         i40e_vlan_offload_set(dev, mask);
5203
5204         /* Apply double-vlan setting, not implemented yet */
5205
5206         /* Apply pvid setting */
5207         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5208                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5209         if (ret)
5210                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5211
5212         return ret;
5213 }
5214
5215 static int
5216 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5217 {
5218         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5219
5220         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5221 }
5222
5223 static int
5224 i40e_update_flow_control(struct i40e_hw *hw)
5225 {
5226 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5227         struct i40e_link_status link_status;
5228         uint32_t rxfc = 0, txfc = 0, reg;
5229         uint8_t an_info;
5230         int ret;
5231
5232         memset(&link_status, 0, sizeof(link_status));
5233         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5234         if (ret != I40E_SUCCESS) {
5235                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5236                 goto write_reg; /* Disable flow control */
5237         }
5238
5239         an_info = hw->phy.link_info.an_info;
5240         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5241                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5242                 ret = I40E_ERR_NOT_READY;
5243                 goto write_reg; /* Disable flow control */
5244         }
5245         /**
5246          * If link auto negotiation is enabled, flow control needs to
5247          * be configured according to it
5248          */
5249         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5250         case I40E_LINK_PAUSE_RXTX:
5251                 rxfc = 1;
5252                 txfc = 1;
5253                 hw->fc.current_mode = I40E_FC_FULL;
5254                 break;
5255         case I40E_AQ_LINK_PAUSE_RX:
5256                 rxfc = 1;
5257                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5258                 break;
5259         case I40E_AQ_LINK_PAUSE_TX:
5260                 txfc = 1;
5261                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5262                 break;
5263         default:
5264                 hw->fc.current_mode = I40E_FC_NONE;
5265                 break;
5266         }
5267
5268 write_reg:
5269         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5270                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5271         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5272         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5273         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5274         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5275
5276         return ret;
5277 }
5278
5279 /* PF setup */
5280 static int
5281 i40e_pf_setup(struct i40e_pf *pf)
5282 {
5283         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5284         struct i40e_filter_control_settings settings;
5285         struct i40e_vsi *vsi;
5286         int ret;
5287
5288         /* Clear all stats counters */
5289         pf->offset_loaded = FALSE;
5290         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5291         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5292         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5293         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5294
5295         ret = i40e_pf_get_switch_config(pf);
5296         if (ret != I40E_SUCCESS) {
5297                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5298                 return ret;
5299         }
5300         if (pf->flags & I40E_FLAG_FDIR) {
5301                 /* make queue allocated first, let FDIR use queue pair 0*/
5302                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5303                 if (ret != I40E_FDIR_QUEUE_ID) {
5304                         PMD_DRV_LOG(ERR,
5305                                 "queue allocation fails for FDIR: ret =%d",
5306                                 ret);
5307                         pf->flags &= ~I40E_FLAG_FDIR;
5308                 }
5309         }
5310         /*  main VSI setup */
5311         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5312         if (!vsi) {
5313                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5314                 return I40E_ERR_NOT_READY;
5315         }
5316         pf->main_vsi = vsi;
5317
5318         /* Configure filter control */
5319         memset(&settings, 0, sizeof(settings));
5320         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5321                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5322         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5323                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5324         else {
5325                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5326                         hw->func_caps.rss_table_size);
5327                 return I40E_ERR_PARAM;
5328         }
5329         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5330                 hw->func_caps.rss_table_size);
5331         pf->hash_lut_size = hw->func_caps.rss_table_size;
5332
5333         /* Enable ethtype and macvlan filters */
5334         settings.enable_ethtype = TRUE;
5335         settings.enable_macvlan = TRUE;
5336         ret = i40e_set_filter_control(hw, &settings);
5337         if (ret)
5338                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5339                                                                 ret);
5340
5341         /* Update flow control according to the auto negotiation */
5342         i40e_update_flow_control(hw);
5343
5344         return I40E_SUCCESS;
5345 }
5346
5347 int
5348 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5349 {
5350         uint32_t reg;
5351         uint16_t j;
5352
5353         /**
5354          * Set or clear TX Queue Disable flags,
5355          * which is required by hardware.
5356          */
5357         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5358         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5359
5360         /* Wait until the request is finished */
5361         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5362                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5363                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5364                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5365                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5366                                                         & 0x1))) {
5367                         break;
5368                 }
5369         }
5370         if (on) {
5371                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5372                         return I40E_SUCCESS; /* already on, skip next steps */
5373
5374                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5375                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5376         } else {
5377                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5378                         return I40E_SUCCESS; /* already off, skip next steps */
5379                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5380         }
5381         /* Write the register */
5382         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5383         /* Check the result */
5384         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5385                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5386                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5387                 if (on) {
5388                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5389                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5390                                 break;
5391                 } else {
5392                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5393                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5394                                 break;
5395                 }
5396         }
5397         /* Check if it is timeout */
5398         if (j >= I40E_CHK_Q_ENA_COUNT) {
5399                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5400                             (on ? "enable" : "disable"), q_idx);
5401                 return I40E_ERR_TIMEOUT;
5402         }
5403
5404         return I40E_SUCCESS;
5405 }
5406
5407 /* Swith on or off the tx queues */
5408 static int
5409 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5410 {
5411         struct rte_eth_dev_data *dev_data = pf->dev_data;
5412         struct i40e_tx_queue *txq;
5413         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5414         uint16_t i;
5415         int ret;
5416
5417         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5418                 txq = dev_data->tx_queues[i];
5419                 /* Don't operate the queue if not configured or
5420                  * if starting only per queue */
5421                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5422                         continue;
5423                 if (on)
5424                         ret = i40e_dev_tx_queue_start(dev, i);
5425                 else
5426                         ret = i40e_dev_tx_queue_stop(dev, i);
5427                 if ( ret != I40E_SUCCESS)
5428                         return ret;
5429         }
5430
5431         return I40E_SUCCESS;
5432 }
5433
5434 int
5435 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5436 {
5437         uint32_t reg;
5438         uint16_t j;
5439
5440         /* Wait until the request is finished */
5441         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5442                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5443                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5444                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5445                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5446                         break;
5447         }
5448
5449         if (on) {
5450                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5451                         return I40E_SUCCESS; /* Already on, skip next steps */
5452                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5453         } else {
5454                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5455                         return I40E_SUCCESS; /* Already off, skip next steps */
5456                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5457         }
5458
5459         /* Write the register */
5460         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5461         /* Check the result */
5462         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5463                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5464                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5465                 if (on) {
5466                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5467                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5468                                 break;
5469                 } else {
5470                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5471                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5472                                 break;
5473                 }
5474         }
5475
5476         /* Check if it is timeout */
5477         if (j >= I40E_CHK_Q_ENA_COUNT) {
5478                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5479                             (on ? "enable" : "disable"), q_idx);
5480                 return I40E_ERR_TIMEOUT;
5481         }
5482
5483         return I40E_SUCCESS;
5484 }
5485 /* Switch on or off the rx queues */
5486 static int
5487 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5488 {
5489         struct rte_eth_dev_data *dev_data = pf->dev_data;
5490         struct i40e_rx_queue *rxq;
5491         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5492         uint16_t i;
5493         int ret;
5494
5495         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5496                 rxq = dev_data->rx_queues[i];
5497                 /* Don't operate the queue if not configured or
5498                  * if starting only per queue */
5499                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5500                         continue;
5501                 if (on)
5502                         ret = i40e_dev_rx_queue_start(dev, i);
5503                 else
5504                         ret = i40e_dev_rx_queue_stop(dev, i);
5505                 if (ret != I40E_SUCCESS)
5506                         return ret;
5507         }
5508
5509         return I40E_SUCCESS;
5510 }
5511
5512 /* Switch on or off all the rx/tx queues */
5513 int
5514 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5515 {
5516         int ret;
5517
5518         if (on) {
5519                 /* enable rx queues before enabling tx queues */
5520                 ret = i40e_dev_switch_rx_queues(pf, on);
5521                 if (ret) {
5522                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5523                         return ret;
5524                 }
5525                 ret = i40e_dev_switch_tx_queues(pf, on);
5526         } else {
5527                 /* Stop tx queues before stopping rx queues */
5528                 ret = i40e_dev_switch_tx_queues(pf, on);
5529                 if (ret) {
5530                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5531                         return ret;
5532                 }
5533                 ret = i40e_dev_switch_rx_queues(pf, on);
5534         }
5535
5536         return ret;
5537 }
5538
5539 /* Initialize VSI for TX */
5540 static int
5541 i40e_dev_tx_init(struct i40e_pf *pf)
5542 {
5543         struct rte_eth_dev_data *data = pf->dev_data;
5544         uint16_t i;
5545         uint32_t ret = I40E_SUCCESS;
5546         struct i40e_tx_queue *txq;
5547
5548         for (i = 0; i < data->nb_tx_queues; i++) {
5549                 txq = data->tx_queues[i];
5550                 if (!txq || !txq->q_set)
5551                         continue;
5552                 ret = i40e_tx_queue_init(txq);
5553                 if (ret != I40E_SUCCESS)
5554                         break;
5555         }
5556         if (ret == I40E_SUCCESS)
5557                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5558                                      ->eth_dev);
5559
5560         return ret;
5561 }
5562
5563 /* Initialize VSI for RX */
5564 static int
5565 i40e_dev_rx_init(struct i40e_pf *pf)
5566 {
5567         struct rte_eth_dev_data *data = pf->dev_data;
5568         int ret = I40E_SUCCESS;
5569         uint16_t i;
5570         struct i40e_rx_queue *rxq;
5571
5572         i40e_pf_config_mq_rx(pf);
5573         for (i = 0; i < data->nb_rx_queues; i++) {
5574                 rxq = data->rx_queues[i];
5575                 if (!rxq || !rxq->q_set)
5576                         continue;
5577
5578                 ret = i40e_rx_queue_init(rxq);
5579                 if (ret != I40E_SUCCESS) {
5580                         PMD_DRV_LOG(ERR,
5581                                 "Failed to do RX queue initialization");
5582                         break;
5583                 }
5584         }
5585         if (ret == I40E_SUCCESS)
5586                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5587                                      ->eth_dev);
5588
5589         return ret;
5590 }
5591
5592 static int
5593 i40e_dev_rxtx_init(struct i40e_pf *pf)
5594 {
5595         int err;
5596
5597         err = i40e_dev_tx_init(pf);
5598         if (err) {
5599                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5600                 return err;
5601         }
5602         err = i40e_dev_rx_init(pf);
5603         if (err) {
5604                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5605                 return err;
5606         }
5607
5608         return err;
5609 }
5610
5611 static int
5612 i40e_vmdq_setup(struct rte_eth_dev *dev)
5613 {
5614         struct rte_eth_conf *conf = &dev->data->dev_conf;
5615         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5616         int i, err, conf_vsis, j, loop;
5617         struct i40e_vsi *vsi;
5618         struct i40e_vmdq_info *vmdq_info;
5619         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5620         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5621
5622         /*
5623          * Disable interrupt to avoid message from VF. Furthermore, it will
5624          * avoid race condition in VSI creation/destroy.
5625          */
5626         i40e_pf_disable_irq0(hw);
5627
5628         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5629                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5630                 return -ENOTSUP;
5631         }
5632
5633         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5634         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5635                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5636                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5637                         pf->max_nb_vmdq_vsi);
5638                 return -ENOTSUP;
5639         }
5640
5641         if (pf->vmdq != NULL) {
5642                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5643                 return 0;
5644         }
5645
5646         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5647                                 sizeof(*vmdq_info) * conf_vsis, 0);
5648
5649         if (pf->vmdq == NULL) {
5650                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5651                 return -ENOMEM;
5652         }
5653
5654         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5655
5656         /* Create VMDQ VSI */
5657         for (i = 0; i < conf_vsis; i++) {
5658                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5659                                 vmdq_conf->enable_loop_back);
5660                 if (vsi == NULL) {
5661                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5662                         err = -1;
5663                         goto err_vsi_setup;
5664                 }
5665                 vmdq_info = &pf->vmdq[i];
5666                 vmdq_info->pf = pf;
5667                 vmdq_info->vsi = vsi;
5668         }
5669         pf->nb_cfg_vmdq_vsi = conf_vsis;
5670
5671         /* Configure Vlan */
5672         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5673         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5674                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5675                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5676                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5677                                         vmdq_conf->pool_map[i].vlan_id, j);
5678
5679                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5680                                                 vmdq_conf->pool_map[i].vlan_id);
5681                                 if (err) {
5682                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5683                                         err = -1;
5684                                         goto err_vsi_setup;
5685                                 }
5686                         }
5687                 }
5688         }
5689
5690         i40e_pf_enable_irq0(hw);
5691
5692         return 0;
5693
5694 err_vsi_setup:
5695         for (i = 0; i < conf_vsis; i++)
5696                 if (pf->vmdq[i].vsi == NULL)
5697                         break;
5698                 else
5699                         i40e_vsi_release(pf->vmdq[i].vsi);
5700
5701         rte_free(pf->vmdq);
5702         pf->vmdq = NULL;
5703         i40e_pf_enable_irq0(hw);
5704         return err;
5705 }
5706
5707 static void
5708 i40e_stat_update_32(struct i40e_hw *hw,
5709                    uint32_t reg,
5710                    bool offset_loaded,
5711                    uint64_t *offset,
5712                    uint64_t *stat)
5713 {
5714         uint64_t new_data;
5715
5716         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5717         if (!offset_loaded)
5718                 *offset = new_data;
5719
5720         if (new_data >= *offset)
5721                 *stat = (uint64_t)(new_data - *offset);
5722         else
5723                 *stat = (uint64_t)((new_data +
5724                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5725 }
5726
5727 static void
5728 i40e_stat_update_48(struct i40e_hw *hw,
5729                    uint32_t hireg,
5730                    uint32_t loreg,
5731                    bool offset_loaded,
5732                    uint64_t *offset,
5733                    uint64_t *stat)
5734 {
5735         uint64_t new_data;
5736
5737         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5738         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5739                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5740
5741         if (!offset_loaded)
5742                 *offset = new_data;
5743
5744         if (new_data >= *offset)
5745                 *stat = new_data - *offset;
5746         else
5747                 *stat = (uint64_t)((new_data +
5748                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5749
5750         *stat &= I40E_48_BIT_MASK;
5751 }
5752
5753 /* Disable IRQ0 */
5754 void
5755 i40e_pf_disable_irq0(struct i40e_hw *hw)
5756 {
5757         /* Disable all interrupt types */
5758         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5759         I40E_WRITE_FLUSH(hw);
5760 }
5761
5762 /* Enable IRQ0 */
5763 void
5764 i40e_pf_enable_irq0(struct i40e_hw *hw)
5765 {
5766         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5767                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5768                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5769                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5770         I40E_WRITE_FLUSH(hw);
5771 }
5772
5773 static void
5774 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5775 {
5776         /* read pending request and disable first */
5777         i40e_pf_disable_irq0(hw);
5778         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5779         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5780                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5781
5782         if (no_queue)
5783                 /* Link no queues with irq0 */
5784                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5785                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5786 }
5787
5788 static void
5789 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5790 {
5791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5793         int i;
5794         uint16_t abs_vf_id;
5795         uint32_t index, offset, val;
5796
5797         if (!pf->vfs)
5798                 return;
5799         /**
5800          * Try to find which VF trigger a reset, use absolute VF id to access
5801          * since the reg is global register.
5802          */
5803         for (i = 0; i < pf->vf_num; i++) {
5804                 abs_vf_id = hw->func_caps.vf_base_id + i;
5805                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5806                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5807                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5808                 /* VFR event occurred */
5809                 if (val & (0x1 << offset)) {
5810                         int ret;
5811
5812                         /* Clear the event first */
5813                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5814                                                         (0x1 << offset));
5815                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5816                         /**
5817                          * Only notify a VF reset event occurred,
5818                          * don't trigger another SW reset
5819                          */
5820                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5821                         if (ret != I40E_SUCCESS)
5822                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5823                 }
5824         }
5825 }
5826
5827 static void
5828 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5829 {
5830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5831         int i;
5832
5833         for (i = 0; i < pf->vf_num; i++)
5834                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5835 }
5836
5837 static void
5838 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5839 {
5840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5841         struct i40e_arq_event_info info;
5842         uint16_t pending, opcode;
5843         int ret;
5844
5845         info.buf_len = I40E_AQ_BUF_SZ;
5846         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5847         if (!info.msg_buf) {
5848                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5849                 return;
5850         }
5851
5852         pending = 1;
5853         while (pending) {
5854                 ret = i40e_clean_arq_element(hw, &info, &pending);
5855
5856                 if (ret != I40E_SUCCESS) {
5857                         PMD_DRV_LOG(INFO,
5858                                 "Failed to read msg from AdminQ, aq_err: %u",
5859                                 hw->aq.asq_last_status);
5860                         break;
5861                 }
5862                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5863
5864                 switch (opcode) {
5865                 case i40e_aqc_opc_send_msg_to_pf:
5866                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5867                         i40e_pf_host_handle_vf_msg(dev,
5868                                         rte_le_to_cpu_16(info.desc.retval),
5869                                         rte_le_to_cpu_32(info.desc.cookie_high),
5870                                         rte_le_to_cpu_32(info.desc.cookie_low),
5871                                         info.msg_buf,
5872                                         info.msg_len);
5873                         break;
5874                 case i40e_aqc_opc_get_link_status:
5875                         ret = i40e_dev_link_update(dev, 0);
5876                         if (!ret)
5877                                 _rte_eth_dev_callback_process(dev,
5878                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5879                         break;
5880                 default:
5881                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5882                                     opcode);
5883                         break;
5884                 }
5885         }
5886         rte_free(info.msg_buf);
5887 }
5888
5889 /**
5890  * Interrupt handler triggered by NIC  for handling
5891  * specific interrupt.
5892  *
5893  * @param handle
5894  *  Pointer to interrupt handle.
5895  * @param param
5896  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5897  *
5898  * @return
5899  *  void
5900  */
5901 static void
5902 i40e_dev_interrupt_handler(void *param)
5903 {
5904         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         uint32_t icr0;
5907
5908         /* Disable interrupt */
5909         i40e_pf_disable_irq0(hw);
5910
5911         /* read out interrupt causes */
5912         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5913
5914         /* No interrupt event indicated */
5915         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5916                 PMD_DRV_LOG(INFO, "No interrupt event");
5917                 goto done;
5918         }
5919         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5920                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5921         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5922                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5923         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5924                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5925         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5926                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5927         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5928                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5929         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5930                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5931         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5932                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5933
5934         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5935                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5936                 i40e_dev_handle_vfr_event(dev);
5937         }
5938         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5939                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5940                 i40e_dev_handle_aq_msg(dev);
5941         }
5942
5943 done:
5944         /* Enable interrupt */
5945         i40e_pf_enable_irq0(hw);
5946         rte_intr_enable(dev->intr_handle);
5947 }
5948
5949 int
5950 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5951                          struct i40e_macvlan_filter *filter,
5952                          int total)
5953 {
5954         int ele_num, ele_buff_size;
5955         int num, actual_num, i;
5956         uint16_t flags;
5957         int ret = I40E_SUCCESS;
5958         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5959         struct i40e_aqc_add_macvlan_element_data *req_list;
5960
5961         if (filter == NULL  || total == 0)
5962                 return I40E_ERR_PARAM;
5963         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5964         ele_buff_size = hw->aq.asq_buf_size;
5965
5966         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5967         if (req_list == NULL) {
5968                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5969                 return I40E_ERR_NO_MEMORY;
5970         }
5971
5972         num = 0;
5973         do {
5974                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5975                 memset(req_list, 0, ele_buff_size);
5976
5977                 for (i = 0; i < actual_num; i++) {
5978                         (void)rte_memcpy(req_list[i].mac_addr,
5979                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5980                         req_list[i].vlan_tag =
5981                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5982
5983                         switch (filter[num + i].filter_type) {
5984                         case RTE_MAC_PERFECT_MATCH:
5985                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5986                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5987                                 break;
5988                         case RTE_MACVLAN_PERFECT_MATCH:
5989                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5990                                 break;
5991                         case RTE_MAC_HASH_MATCH:
5992                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5993                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5994                                 break;
5995                         case RTE_MACVLAN_HASH_MATCH:
5996                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5997                                 break;
5998                         default:
5999                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6000                                 ret = I40E_ERR_PARAM;
6001                                 goto DONE;
6002                         }
6003
6004                         req_list[i].queue_number = 0;
6005
6006                         req_list[i].flags = rte_cpu_to_le_16(flags);
6007                 }
6008
6009                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6010                                                 actual_num, NULL);
6011                 if (ret != I40E_SUCCESS) {
6012                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6013                         goto DONE;
6014                 }
6015                 num += actual_num;
6016         } while (num < total);
6017
6018 DONE:
6019         rte_free(req_list);
6020         return ret;
6021 }
6022
6023 int
6024 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6025                             struct i40e_macvlan_filter *filter,
6026                             int total)
6027 {
6028         int ele_num, ele_buff_size;
6029         int num, actual_num, i;
6030         uint16_t flags;
6031         int ret = I40E_SUCCESS;
6032         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6033         struct i40e_aqc_remove_macvlan_element_data *req_list;
6034
6035         if (filter == NULL  || total == 0)
6036                 return I40E_ERR_PARAM;
6037
6038         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6039         ele_buff_size = hw->aq.asq_buf_size;
6040
6041         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6042         if (req_list == NULL) {
6043                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6044                 return I40E_ERR_NO_MEMORY;
6045         }
6046
6047         num = 0;
6048         do {
6049                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6050                 memset(req_list, 0, ele_buff_size);
6051
6052                 for (i = 0; i < actual_num; i++) {
6053                         (void)rte_memcpy(req_list[i].mac_addr,
6054                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6055                         req_list[i].vlan_tag =
6056                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6057
6058                         switch (filter[num + i].filter_type) {
6059                         case RTE_MAC_PERFECT_MATCH:
6060                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6061                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6062                                 break;
6063                         case RTE_MACVLAN_PERFECT_MATCH:
6064                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6065                                 break;
6066                         case RTE_MAC_HASH_MATCH:
6067                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6068                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6069                                 break;
6070                         case RTE_MACVLAN_HASH_MATCH:
6071                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6072                                 break;
6073                         default:
6074                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6075                                 ret = I40E_ERR_PARAM;
6076                                 goto DONE;
6077                         }
6078                         req_list[i].flags = rte_cpu_to_le_16(flags);
6079                 }
6080
6081                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6082                                                 actual_num, NULL);
6083                 if (ret != I40E_SUCCESS) {
6084                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6085                         goto DONE;
6086                 }
6087                 num += actual_num;
6088         } while (num < total);
6089
6090 DONE:
6091         rte_free(req_list);
6092         return ret;
6093 }
6094
6095 /* Find out specific MAC filter */
6096 static struct i40e_mac_filter *
6097 i40e_find_mac_filter(struct i40e_vsi *vsi,
6098                          struct ether_addr *macaddr)
6099 {
6100         struct i40e_mac_filter *f;
6101
6102         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6103                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6104                         return f;
6105         }
6106
6107         return NULL;
6108 }
6109
6110 static bool
6111 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6112                          uint16_t vlan_id)
6113 {
6114         uint32_t vid_idx, vid_bit;
6115
6116         if (vlan_id > ETH_VLAN_ID_MAX)
6117                 return 0;
6118
6119         vid_idx = I40E_VFTA_IDX(vlan_id);
6120         vid_bit = I40E_VFTA_BIT(vlan_id);
6121
6122         if (vsi->vfta[vid_idx] & vid_bit)
6123                 return 1;
6124         else
6125                 return 0;
6126 }
6127
6128 static void
6129 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6130                        uint16_t vlan_id, bool on)
6131 {
6132         uint32_t vid_idx, vid_bit;
6133
6134         vid_idx = I40E_VFTA_IDX(vlan_id);
6135         vid_bit = I40E_VFTA_BIT(vlan_id);
6136
6137         if (on)
6138                 vsi->vfta[vid_idx] |= vid_bit;
6139         else
6140                 vsi->vfta[vid_idx] &= ~vid_bit;
6141 }
6142
6143 void
6144 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6145                      uint16_t vlan_id, bool on)
6146 {
6147         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6148         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6149         int ret;
6150
6151         if (vlan_id > ETH_VLAN_ID_MAX)
6152                 return;
6153
6154         i40e_store_vlan_filter(vsi, vlan_id, on);
6155
6156         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6157                 return;
6158
6159         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6160
6161         if (on) {
6162                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6163                                        &vlan_data, 1, NULL);
6164                 if (ret != I40E_SUCCESS)
6165                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6166         } else {
6167                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6168                                           &vlan_data, 1, NULL);
6169                 if (ret != I40E_SUCCESS)
6170                         PMD_DRV_LOG(ERR,
6171                                     "Failed to remove vlan filter");
6172         }
6173 }
6174
6175 /**
6176  * Find all vlan options for specific mac addr,
6177  * return with actual vlan found.
6178  */
6179 int
6180 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6181                            struct i40e_macvlan_filter *mv_f,
6182                            int num, struct ether_addr *addr)
6183 {
6184         int i;
6185         uint32_t j, k;
6186
6187         /**
6188          * Not to use i40e_find_vlan_filter to decrease the loop time,
6189          * although the code looks complex.
6190           */
6191         if (num < vsi->vlan_num)
6192                 return I40E_ERR_PARAM;
6193
6194         i = 0;
6195         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6196                 if (vsi->vfta[j]) {
6197                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6198                                 if (vsi->vfta[j] & (1 << k)) {
6199                                         if (i > num - 1) {
6200                                                 PMD_DRV_LOG(ERR,
6201                                                         "vlan number doesn't match");
6202                                                 return I40E_ERR_PARAM;
6203                                         }
6204                                         (void)rte_memcpy(&mv_f[i].macaddr,
6205                                                         addr, ETH_ADDR_LEN);
6206                                         mv_f[i].vlan_id =
6207                                                 j * I40E_UINT32_BIT_SIZE + k;
6208                                         i++;
6209                                 }
6210                         }
6211                 }
6212         }
6213         return I40E_SUCCESS;
6214 }
6215
6216 static inline int
6217 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6218                            struct i40e_macvlan_filter *mv_f,
6219                            int num,
6220                            uint16_t vlan)
6221 {
6222         int i = 0;
6223         struct i40e_mac_filter *f;
6224
6225         if (num < vsi->mac_num)
6226                 return I40E_ERR_PARAM;
6227
6228         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6229                 if (i > num - 1) {
6230                         PMD_DRV_LOG(ERR, "buffer number not match");
6231                         return I40E_ERR_PARAM;
6232                 }
6233                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6234                                 ETH_ADDR_LEN);
6235                 mv_f[i].vlan_id = vlan;
6236                 mv_f[i].filter_type = f->mac_info.filter_type;
6237                 i++;
6238         }
6239
6240         return I40E_SUCCESS;
6241 }
6242
6243 static int
6244 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6245 {
6246         int i, j, num;
6247         struct i40e_mac_filter *f;
6248         struct i40e_macvlan_filter *mv_f;
6249         int ret = I40E_SUCCESS;
6250
6251         if (vsi == NULL || vsi->mac_num == 0)
6252                 return I40E_ERR_PARAM;
6253
6254         /* Case that no vlan is set */
6255         if (vsi->vlan_num == 0)
6256                 num = vsi->mac_num;
6257         else
6258                 num = vsi->mac_num * vsi->vlan_num;
6259
6260         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6261         if (mv_f == NULL) {
6262                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6263                 return I40E_ERR_NO_MEMORY;
6264         }
6265
6266         i = 0;
6267         if (vsi->vlan_num == 0) {
6268                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6269                         (void)rte_memcpy(&mv_f[i].macaddr,
6270                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6271                         mv_f[i].filter_type = f->mac_info.filter_type;
6272                         mv_f[i].vlan_id = 0;
6273                         i++;
6274                 }
6275         } else {
6276                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6277                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6278                                         vsi->vlan_num, &f->mac_info.mac_addr);
6279                         if (ret != I40E_SUCCESS)
6280                                 goto DONE;
6281                         for (j = i; j < i + vsi->vlan_num; j++)
6282                                 mv_f[j].filter_type = f->mac_info.filter_type;
6283                         i += vsi->vlan_num;
6284                 }
6285         }
6286
6287         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6288 DONE:
6289         rte_free(mv_f);
6290
6291         return ret;
6292 }
6293
6294 int
6295 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6296 {
6297         struct i40e_macvlan_filter *mv_f;
6298         int mac_num;
6299         int ret = I40E_SUCCESS;
6300
6301         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6302                 return I40E_ERR_PARAM;
6303
6304         /* If it's already set, just return */
6305         if (i40e_find_vlan_filter(vsi,vlan))
6306                 return I40E_SUCCESS;
6307
6308         mac_num = vsi->mac_num;
6309
6310         if (mac_num == 0) {
6311                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6312                 return I40E_ERR_PARAM;
6313         }
6314
6315         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6316
6317         if (mv_f == NULL) {
6318                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6319                 return I40E_ERR_NO_MEMORY;
6320         }
6321
6322         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6323
6324         if (ret != I40E_SUCCESS)
6325                 goto DONE;
6326
6327         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6328
6329         if (ret != I40E_SUCCESS)
6330                 goto DONE;
6331
6332         i40e_set_vlan_filter(vsi, vlan, 1);
6333
6334         vsi->vlan_num++;
6335         ret = I40E_SUCCESS;
6336 DONE:
6337         rte_free(mv_f);
6338         return ret;
6339 }
6340
6341 int
6342 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6343 {
6344         struct i40e_macvlan_filter *mv_f;
6345         int mac_num;
6346         int ret = I40E_SUCCESS;
6347
6348         /**
6349          * Vlan 0 is the generic filter for untagged packets
6350          * and can't be removed.
6351          */
6352         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6353                 return I40E_ERR_PARAM;
6354
6355         /* If can't find it, just return */
6356         if (!i40e_find_vlan_filter(vsi, vlan))
6357                 return I40E_ERR_PARAM;
6358
6359         mac_num = vsi->mac_num;
6360
6361         if (mac_num == 0) {
6362                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6363                 return I40E_ERR_PARAM;
6364         }
6365
6366         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6367
6368         if (mv_f == NULL) {
6369                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6370                 return I40E_ERR_NO_MEMORY;
6371         }
6372
6373         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6374
6375         if (ret != I40E_SUCCESS)
6376                 goto DONE;
6377
6378         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6379
6380         if (ret != I40E_SUCCESS)
6381                 goto DONE;
6382
6383         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6384         if (vsi->vlan_num == 1) {
6385                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6386                 if (ret != I40E_SUCCESS)
6387                         goto DONE;
6388
6389                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6390                 if (ret != I40E_SUCCESS)
6391                         goto DONE;
6392         }
6393
6394         i40e_set_vlan_filter(vsi, vlan, 0);
6395
6396         vsi->vlan_num--;
6397         ret = I40E_SUCCESS;
6398 DONE:
6399         rte_free(mv_f);
6400         return ret;
6401 }
6402
6403 int
6404 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6405 {
6406         struct i40e_mac_filter *f;
6407         struct i40e_macvlan_filter *mv_f;
6408         int i, vlan_num = 0;
6409         int ret = I40E_SUCCESS;
6410
6411         /* If it's add and we've config it, return */
6412         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6413         if (f != NULL)
6414                 return I40E_SUCCESS;
6415         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6416                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6417
6418                 /**
6419                  * If vlan_num is 0, that's the first time to add mac,
6420                  * set mask for vlan_id 0.
6421                  */
6422                 if (vsi->vlan_num == 0) {
6423                         i40e_set_vlan_filter(vsi, 0, 1);
6424                         vsi->vlan_num = 1;
6425                 }
6426                 vlan_num = vsi->vlan_num;
6427         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6428                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6429                 vlan_num = 1;
6430
6431         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6432         if (mv_f == NULL) {
6433                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6434                 return I40E_ERR_NO_MEMORY;
6435         }
6436
6437         for (i = 0; i < vlan_num; i++) {
6438                 mv_f[i].filter_type = mac_filter->filter_type;
6439                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6440                                 ETH_ADDR_LEN);
6441         }
6442
6443         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6444                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6445                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6446                                         &mac_filter->mac_addr);
6447                 if (ret != I40E_SUCCESS)
6448                         goto DONE;
6449         }
6450
6451         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6452         if (ret != I40E_SUCCESS)
6453                 goto DONE;
6454
6455         /* Add the mac addr into mac list */
6456         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6457         if (f == NULL) {
6458                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6459                 ret = I40E_ERR_NO_MEMORY;
6460                 goto DONE;
6461         }
6462         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6463                         ETH_ADDR_LEN);
6464         f->mac_info.filter_type = mac_filter->filter_type;
6465         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6466         vsi->mac_num++;
6467
6468         ret = I40E_SUCCESS;
6469 DONE:
6470         rte_free(mv_f);
6471
6472         return ret;
6473 }
6474
6475 int
6476 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6477 {
6478         struct i40e_mac_filter *f;
6479         struct i40e_macvlan_filter *mv_f;
6480         int i, vlan_num;
6481         enum rte_mac_filter_type filter_type;
6482         int ret = I40E_SUCCESS;
6483
6484         /* Can't find it, return an error */
6485         f = i40e_find_mac_filter(vsi, addr);
6486         if (f == NULL)
6487                 return I40E_ERR_PARAM;
6488
6489         vlan_num = vsi->vlan_num;
6490         filter_type = f->mac_info.filter_type;
6491         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6492                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6493                 if (vlan_num == 0) {
6494                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6495                         return I40E_ERR_PARAM;
6496                 }
6497         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6498                         filter_type == RTE_MAC_HASH_MATCH)
6499                 vlan_num = 1;
6500
6501         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6502         if (mv_f == NULL) {
6503                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6504                 return I40E_ERR_NO_MEMORY;
6505         }
6506
6507         for (i = 0; i < vlan_num; i++) {
6508                 mv_f[i].filter_type = filter_type;
6509                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6510                                 ETH_ADDR_LEN);
6511         }
6512         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6513                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6514                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6515                 if (ret != I40E_SUCCESS)
6516                         goto DONE;
6517         }
6518
6519         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6520         if (ret != I40E_SUCCESS)
6521                 goto DONE;
6522
6523         /* Remove the mac addr into mac list */
6524         TAILQ_REMOVE(&vsi->mac_list, f, next);
6525         rte_free(f);
6526         vsi->mac_num--;
6527
6528         ret = I40E_SUCCESS;
6529 DONE:
6530         rte_free(mv_f);
6531         return ret;
6532 }
6533
6534 /* Configure hash enable flags for RSS */
6535 uint64_t
6536 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6537 {
6538         uint64_t hena = 0;
6539
6540         if (!flags)
6541                 return hena;
6542
6543         if (flags & ETH_RSS_FRAG_IPV4)
6544                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6545         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6546                 if (type == I40E_MAC_X722) {
6547                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6548                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6549                 } else
6550                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6551         }
6552         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6553                 if (type == I40E_MAC_X722) {
6554                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6555                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6556                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6557                 } else
6558                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6559         }
6560         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6561                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6562         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6563                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6564         if (flags & ETH_RSS_FRAG_IPV6)
6565                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6566         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6567                 if (type == I40E_MAC_X722) {
6568                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6569                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6570                 } else
6571                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6572         }
6573         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6574                 if (type == I40E_MAC_X722) {
6575                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6576                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6577                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6578                 } else
6579                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6580         }
6581         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6582                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6583         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6584                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6585         if (flags & ETH_RSS_L2_PAYLOAD)
6586                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6587
6588         return hena;
6589 }
6590
6591 /* Parse the hash enable flags */
6592 uint64_t
6593 i40e_parse_hena(uint64_t flags)
6594 {
6595         uint64_t rss_hf = 0;
6596
6597         if (!flags)
6598                 return rss_hf;
6599         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6600                 rss_hf |= ETH_RSS_FRAG_IPV4;
6601         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6602                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6603         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6604                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6605         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6606                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6607         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6608                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6609         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6610                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6611         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6612                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6613         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6614                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6615         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6616                 rss_hf |= ETH_RSS_FRAG_IPV6;
6617         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6618                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6620                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6622                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6623         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6624                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6626                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6628                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6630                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6631         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6632                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6633
6634         return rss_hf;
6635 }
6636
6637 /* Disable RSS */
6638 static void
6639 i40e_pf_disable_rss(struct i40e_pf *pf)
6640 {
6641         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6642         uint64_t hena;
6643
6644         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6645         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6646         if (hw->mac.type == I40E_MAC_X722)
6647                 hena &= ~I40E_RSS_HENA_ALL_X722;
6648         else
6649                 hena &= ~I40E_RSS_HENA_ALL;
6650         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6651         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6652         I40E_WRITE_FLUSH(hw);
6653 }
6654
6655 static int
6656 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6657 {
6658         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6659         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6660         int ret = 0;
6661
6662         if (!key || key_len == 0) {
6663                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6664                 return 0;
6665         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6666                 sizeof(uint32_t)) {
6667                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6668                 return -EINVAL;
6669         }
6670
6671         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6672                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6673                         (struct i40e_aqc_get_set_rss_key_data *)key;
6674
6675                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6676                 if (ret)
6677                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6678         } else {
6679                 uint32_t *hash_key = (uint32_t *)key;
6680                 uint16_t i;
6681
6682                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6683                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6684                 I40E_WRITE_FLUSH(hw);
6685         }
6686
6687         return ret;
6688 }
6689
6690 static int
6691 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6692 {
6693         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6694         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6695         int ret;
6696
6697         if (!key || !key_len)
6698                 return -EINVAL;
6699
6700         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6701                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6702                         (struct i40e_aqc_get_set_rss_key_data *)key);
6703                 if (ret) {
6704                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6705                         return ret;
6706                 }
6707         } else {
6708                 uint32_t *key_dw = (uint32_t *)key;
6709                 uint16_t i;
6710
6711                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6712                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6713         }
6714         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6715
6716         return 0;
6717 }
6718
6719 static int
6720 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6721 {
6722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6723         uint64_t rss_hf;
6724         uint64_t hena;
6725         int ret;
6726
6727         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6728                                rss_conf->rss_key_len);
6729         if (ret)
6730                 return ret;
6731
6732         rss_hf = rss_conf->rss_hf;
6733         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6734         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6735         if (hw->mac.type == I40E_MAC_X722)
6736                 hena &= ~I40E_RSS_HENA_ALL_X722;
6737         else
6738                 hena &= ~I40E_RSS_HENA_ALL;
6739         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6740         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6741         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6742         I40E_WRITE_FLUSH(hw);
6743
6744         return 0;
6745 }
6746
6747 static int
6748 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6749                          struct rte_eth_rss_conf *rss_conf)
6750 {
6751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6754         uint64_t hena;
6755
6756         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6757         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6758         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6759                  ? I40E_RSS_HENA_ALL_X722
6760                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6761                 if (rss_hf != 0) /* Enable RSS */
6762                         return -EINVAL;
6763                 return 0; /* Nothing to do */
6764         }
6765         /* RSS enabled */
6766         if (rss_hf == 0) /* Disable RSS */
6767                 return -EINVAL;
6768
6769         return i40e_hw_rss_hash_set(pf, rss_conf);
6770 }
6771
6772 static int
6773 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6774                            struct rte_eth_rss_conf *rss_conf)
6775 {
6776         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778         uint64_t hena;
6779
6780         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6781                          &rss_conf->rss_key_len);
6782
6783         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6784         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6785         rss_conf->rss_hf = i40e_parse_hena(hena);
6786
6787         return 0;
6788 }
6789
6790 static int
6791 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6792 {
6793         switch (filter_type) {
6794         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6795                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6796                 break;
6797         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6798                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6799                 break;
6800         case RTE_TUNNEL_FILTER_IMAC_TENID:
6801                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6802                 break;
6803         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6804                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6805                 break;
6806         case ETH_TUNNEL_FILTER_IMAC:
6807                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6808                 break;
6809         case ETH_TUNNEL_FILTER_OIP:
6810                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6811                 break;
6812         case ETH_TUNNEL_FILTER_IIP:
6813                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6814                 break;
6815         default:
6816                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6817                 return -EINVAL;
6818         }
6819
6820         return 0;
6821 }
6822
6823 /* Convert tunnel filter structure */
6824 static int
6825 i40e_tunnel_filter_convert(
6826         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6827         struct i40e_tunnel_filter *tunnel_filter)
6828 {
6829         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6830                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6831         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6832                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6833         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6834         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6835              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6836             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6837                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6838         else
6839                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6840         tunnel_filter->input.flags = cld_filter->element.flags;
6841         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6842         tunnel_filter->queue = cld_filter->element.queue_number;
6843         rte_memcpy(tunnel_filter->input.general_fields,
6844                    cld_filter->general_fields,
6845                    sizeof(cld_filter->general_fields));
6846
6847         return 0;
6848 }
6849
6850 /* Check if there exists the tunnel filter */
6851 struct i40e_tunnel_filter *
6852 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6853                              const struct i40e_tunnel_filter_input *input)
6854 {
6855         int ret;
6856
6857         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6858         if (ret < 0)
6859                 return NULL;
6860
6861         return tunnel_rule->hash_map[ret];
6862 }
6863
6864 /* Add a tunnel filter into the SW list */
6865 static int
6866 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6867                              struct i40e_tunnel_filter *tunnel_filter)
6868 {
6869         struct i40e_tunnel_rule *rule = &pf->tunnel;
6870         int ret;
6871
6872         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6873         if (ret < 0) {
6874                 PMD_DRV_LOG(ERR,
6875                             "Failed to insert tunnel filter to hash table %d!",
6876                             ret);
6877                 return ret;
6878         }
6879         rule->hash_map[ret] = tunnel_filter;
6880
6881         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6882
6883         return 0;
6884 }
6885
6886 /* Delete a tunnel filter from the SW list */
6887 int
6888 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6889                           struct i40e_tunnel_filter_input *input)
6890 {
6891         struct i40e_tunnel_rule *rule = &pf->tunnel;
6892         struct i40e_tunnel_filter *tunnel_filter;
6893         int ret;
6894
6895         ret = rte_hash_del_key(rule->hash_table, input);
6896         if (ret < 0) {
6897                 PMD_DRV_LOG(ERR,
6898                             "Failed to delete tunnel filter to hash table %d!",
6899                             ret);
6900                 return ret;
6901         }
6902         tunnel_filter = rule->hash_map[ret];
6903         rule->hash_map[ret] = NULL;
6904
6905         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6906         rte_free(tunnel_filter);
6907
6908         return 0;
6909 }
6910
6911 int
6912 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6913                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6914                         uint8_t add)
6915 {
6916         uint16_t ip_type;
6917         uint32_t ipv4_addr;
6918         uint8_t i, tun_type = 0;
6919         /* internal varialbe to convert ipv6 byte order */
6920         uint32_t convert_ipv6[4];
6921         int val, ret = 0;
6922         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6923         struct i40e_vsi *vsi = pf->main_vsi;
6924         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6925         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6926         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6927         struct i40e_tunnel_filter *tunnel, *node;
6928         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6929
6930         cld_filter = rte_zmalloc("tunnel_filter",
6931                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6932         0);
6933
6934         if (NULL == cld_filter) {
6935                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6936                 return -ENOMEM;
6937         }
6938         pfilter = cld_filter;
6939
6940         ether_addr_copy(&tunnel_filter->outer_mac,
6941                         (struct ether_addr *)&pfilter->element.outer_mac);
6942         ether_addr_copy(&tunnel_filter->inner_mac,
6943                         (struct ether_addr *)&pfilter->element.inner_mac);
6944
6945         pfilter->element.inner_vlan =
6946                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6947         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6948                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6949                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6950                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6951                                 &rte_cpu_to_le_32(ipv4_addr),
6952                                 sizeof(pfilter->element.ipaddr.v4.data));
6953         } else {
6954                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6955                 for (i = 0; i < 4; i++) {
6956                         convert_ipv6[i] =
6957                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6958                 }
6959                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6960                            &convert_ipv6,
6961                            sizeof(pfilter->element.ipaddr.v6.data));
6962         }
6963
6964         /* check tunneled type */
6965         switch (tunnel_filter->tunnel_type) {
6966         case RTE_TUNNEL_TYPE_VXLAN:
6967                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6968                 break;
6969         case RTE_TUNNEL_TYPE_NVGRE:
6970                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6971                 break;
6972         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6973                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6974                 break;
6975         default:
6976                 /* Other tunnel types is not supported. */
6977                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6978                 rte_free(cld_filter);
6979                 return -EINVAL;
6980         }
6981
6982         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6983                                        &pfilter->element.flags);
6984         if (val < 0) {
6985                 rte_free(cld_filter);
6986                 return -EINVAL;
6987         }
6988
6989         pfilter->element.flags |= rte_cpu_to_le_16(
6990                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6991                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6992         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6993         pfilter->element.queue_number =
6994                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6995
6996         /* Check if there is the filter in SW list */
6997         memset(&check_filter, 0, sizeof(check_filter));
6998         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6999         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7000         if (add && node) {
7001                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7002                 return -EINVAL;
7003         }
7004
7005         if (!add && !node) {
7006                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7007                 return -EINVAL;
7008         }
7009
7010         if (add) {
7011                 ret = i40e_aq_add_cloud_filters(hw,
7012                                         vsi->seid, &cld_filter->element, 1);
7013                 if (ret < 0) {
7014                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7015                         return -ENOTSUP;
7016                 }
7017                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7018                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7019                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7020         } else {
7021                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7022                                                    &cld_filter->element, 1);
7023                 if (ret < 0) {
7024                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7025                         return -ENOTSUP;
7026                 }
7027                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7028         }
7029
7030         rte_free(cld_filter);
7031         return ret;
7032 }
7033
7034 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7035 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7036 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7037 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7038 #define I40E_TR_GRE_KEY_MASK                    0x400
7039 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7040 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7041
7042 static enum
7043 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7044 {
7045         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7046         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7048         enum i40e_status_code status = I40E_SUCCESS;
7049
7050         memset(&filter_replace, 0,
7051                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7052         memset(&filter_replace_buf, 0,
7053                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7054
7055         /* create L1 filter */
7056         filter_replace.old_filter_type =
7057                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7058         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7059         filter_replace.tr_bit = 0;
7060
7061         /* Prepare the buffer, 3 entries */
7062         filter_replace_buf.data[0] =
7063                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7064         filter_replace_buf.data[0] |=
7065                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7066         filter_replace_buf.data[2] = 0xFF;
7067         filter_replace_buf.data[3] = 0xFF;
7068         filter_replace_buf.data[4] =
7069                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7070         filter_replace_buf.data[4] |=
7071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7072         filter_replace_buf.data[7] = 0xF0;
7073         filter_replace_buf.data[8]
7074                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7075         filter_replace_buf.data[8] |=
7076                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7077         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7078                 I40E_TR_GENEVE_KEY_MASK |
7079                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7080         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7081                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7082                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7083
7084         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7085                                                &filter_replace_buf);
7086         return status;
7087 }
7088
7089 static enum
7090 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7091 {
7092         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7093         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7094         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7095         enum i40e_status_code status = I40E_SUCCESS;
7096
7097         /* For MPLSoUDP */
7098         memset(&filter_replace, 0,
7099                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7100         memset(&filter_replace_buf, 0,
7101                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7102         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7103                 I40E_AQC_MIRROR_CLOUD_FILTER;
7104         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7105         filter_replace.new_filter_type =
7106                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7107         /* Prepare the buffer, 2 entries */
7108         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7109         filter_replace_buf.data[0] |=
7110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7111         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7112         filter_replace_buf.data[4] |=
7113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7114         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7115                                                &filter_replace_buf);
7116         if (status < 0)
7117                 return status;
7118
7119         /* For MPLSoGRE */
7120         memset(&filter_replace, 0,
7121                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7122         memset(&filter_replace_buf, 0,
7123                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7124
7125         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7126                 I40E_AQC_MIRROR_CLOUD_FILTER;
7127         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7128         filter_replace.new_filter_type =
7129                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7130         /* Prepare the buffer, 2 entries */
7131         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7132         filter_replace_buf.data[0] |=
7133                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7134         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7135         filter_replace_buf.data[4] |=
7136                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7137
7138         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7139                                                &filter_replace_buf);
7140         return status;
7141 }
7142
7143 int
7144 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7145                       struct i40e_tunnel_filter_conf *tunnel_filter,
7146                       uint8_t add)
7147 {
7148         uint16_t ip_type;
7149         uint32_t ipv4_addr;
7150         uint8_t i, tun_type = 0;
7151         /* internal variable to convert ipv6 byte order */
7152         uint32_t convert_ipv6[4];
7153         int val, ret = 0;
7154         struct i40e_pf_vf *vf = NULL;
7155         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7156         struct i40e_vsi *vsi;
7157         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7158         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7159         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7160         struct i40e_tunnel_filter *tunnel, *node;
7161         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7162         uint32_t teid_le;
7163         bool big_buffer = 0;
7164
7165         cld_filter = rte_zmalloc("tunnel_filter",
7166                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7167                          0);
7168
7169         if (cld_filter == NULL) {
7170                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7171                 return -ENOMEM;
7172         }
7173         pfilter = cld_filter;
7174
7175         ether_addr_copy(&tunnel_filter->outer_mac,
7176                         (struct ether_addr *)&pfilter->element.outer_mac);
7177         ether_addr_copy(&tunnel_filter->inner_mac,
7178                         (struct ether_addr *)&pfilter->element.inner_mac);
7179
7180         pfilter->element.inner_vlan =
7181                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7182         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7183                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7184                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7185                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7186                                 &rte_cpu_to_le_32(ipv4_addr),
7187                                 sizeof(pfilter->element.ipaddr.v4.data));
7188         } else {
7189                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7190                 for (i = 0; i < 4; i++) {
7191                         convert_ipv6[i] =
7192                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7193                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7194                 }
7195                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7196                            &convert_ipv6,
7197                            sizeof(pfilter->element.ipaddr.v6.data));
7198         }
7199
7200         /* check tunneled type */
7201         switch (tunnel_filter->tunnel_type) {
7202         case I40E_TUNNEL_TYPE_VXLAN:
7203                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7204                 break;
7205         case I40E_TUNNEL_TYPE_NVGRE:
7206                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7207                 break;
7208         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7209                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7210                 break;
7211         case I40E_TUNNEL_TYPE_MPLSoUDP:
7212                 if (!pf->mpls_replace_flag) {
7213                         i40e_replace_mpls_l1_filter(pf);
7214                         i40e_replace_mpls_cloud_filter(pf);
7215                         pf->mpls_replace_flag = 1;
7216                 }
7217                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7218                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7219                         teid_le >> 4;
7220                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7221                         (teid_le & 0xF) << 12;
7222                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7223                         0x40;
7224                 big_buffer = 1;
7225                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7226                 break;
7227         case I40E_TUNNEL_TYPE_MPLSoGRE:
7228                 if (!pf->mpls_replace_flag) {
7229                         i40e_replace_mpls_l1_filter(pf);
7230                         i40e_replace_mpls_cloud_filter(pf);
7231                         pf->mpls_replace_flag = 1;
7232                 }
7233                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7234                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7235                         teid_le >> 4;
7236                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7237                         (teid_le & 0xF) << 12;
7238                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7239                         0x0;
7240                 big_buffer = 1;
7241                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7242                 break;
7243         case I40E_TUNNEL_TYPE_QINQ:
7244                 if (!pf->qinq_replace_flag) {
7245                         ret = i40e_cloud_filter_qinq_create(pf);
7246                         if (ret < 0)
7247                                 PMD_DRV_LOG(DEBUG,
7248                                             "QinQ tunnel filter already created.");
7249                         pf->qinq_replace_flag = 1;
7250                 }
7251                 /*      Add in the General fields the values of
7252                  *      the Outer and Inner VLAN
7253                  *      Big Buffer should be set, see changes in
7254                  *      i40e_aq_add_cloud_filters
7255                  */
7256                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7257                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7258                 big_buffer = 1;
7259                 break;
7260         default:
7261                 /* Other tunnel types is not supported. */
7262                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7263                 rte_free(cld_filter);
7264                 return -EINVAL;
7265         }
7266
7267         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7268                 pfilter->element.flags =
7269                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7270         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7271                 pfilter->element.flags =
7272                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7273         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7274                 pfilter->element.flags |=
7275                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7276         else {
7277                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7278                                                 &pfilter->element.flags);
7279                 if (val < 0) {
7280                         rte_free(cld_filter);
7281                         return -EINVAL;
7282                 }
7283         }
7284
7285         pfilter->element.flags |= rte_cpu_to_le_16(
7286                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7287                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7288         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7289         pfilter->element.queue_number =
7290                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7291
7292         if (!tunnel_filter->is_to_vf)
7293                 vsi = pf->main_vsi;
7294         else {
7295                 if (tunnel_filter->vf_id >= pf->vf_num) {
7296                         PMD_DRV_LOG(ERR, "Invalid argument.");
7297                         return -EINVAL;
7298                 }
7299                 vf = &pf->vfs[tunnel_filter->vf_id];
7300                 vsi = vf->vsi;
7301         }
7302
7303         /* Check if there is the filter in SW list */
7304         memset(&check_filter, 0, sizeof(check_filter));
7305         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7306         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7307         check_filter.vf_id = tunnel_filter->vf_id;
7308         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7309         if (add && node) {
7310                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7311                 return -EINVAL;
7312         }
7313
7314         if (!add && !node) {
7315                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7316                 return -EINVAL;
7317         }
7318
7319         if (add) {
7320                 if (big_buffer)
7321                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7322                                                    vsi->seid, cld_filter, 1);
7323                 else
7324                         ret = i40e_aq_add_cloud_filters(hw,
7325                                         vsi->seid, &cld_filter->element, 1);
7326                 if (ret < 0) {
7327                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7328                         return -ENOTSUP;
7329                 }
7330                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7331                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7332                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7333         } else {
7334                 if (big_buffer)
7335                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7336                                 hw, vsi->seid, cld_filter, 1);
7337                 else
7338                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7339                                                    &cld_filter->element, 1);
7340                 if (ret < 0) {
7341                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7342                         return -ENOTSUP;
7343                 }
7344                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7345         }
7346
7347         rte_free(cld_filter);
7348         return ret;
7349 }
7350
7351 static int
7352 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7353 {
7354         uint8_t i;
7355
7356         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7357                 if (pf->vxlan_ports[i] == port)
7358                         return i;
7359         }
7360
7361         return -1;
7362 }
7363
7364 static int
7365 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7366 {
7367         int  idx, ret;
7368         uint8_t filter_idx;
7369         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7370
7371         idx = i40e_get_vxlan_port_idx(pf, port);
7372
7373         /* Check if port already exists */
7374         if (idx >= 0) {
7375                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7376                 return -EINVAL;
7377         }
7378
7379         /* Now check if there is space to add the new port */
7380         idx = i40e_get_vxlan_port_idx(pf, 0);
7381         if (idx < 0) {
7382                 PMD_DRV_LOG(ERR,
7383                         "Maximum number of UDP ports reached, not adding port %d",
7384                         port);
7385                 return -ENOSPC;
7386         }
7387
7388         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7389                                         &filter_idx, NULL);
7390         if (ret < 0) {
7391                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7392                 return -1;
7393         }
7394
7395         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7396                          port,  filter_idx);
7397
7398         /* New port: add it and mark its index in the bitmap */
7399         pf->vxlan_ports[idx] = port;
7400         pf->vxlan_bitmap |= (1 << idx);
7401
7402         if (!(pf->flags & I40E_FLAG_VXLAN))
7403                 pf->flags |= I40E_FLAG_VXLAN;
7404
7405         return 0;
7406 }
7407
7408 static int
7409 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7410 {
7411         int idx;
7412         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7413
7414         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7415                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7416                 return -EINVAL;
7417         }
7418
7419         idx = i40e_get_vxlan_port_idx(pf, port);
7420
7421         if (idx < 0) {
7422                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7423                 return -EINVAL;
7424         }
7425
7426         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7427                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7428                 return -1;
7429         }
7430
7431         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7432                         port, idx);
7433
7434         pf->vxlan_ports[idx] = 0;
7435         pf->vxlan_bitmap &= ~(1 << idx);
7436
7437         if (!pf->vxlan_bitmap)
7438                 pf->flags &= ~I40E_FLAG_VXLAN;
7439
7440         return 0;
7441 }
7442
7443 /* Add UDP tunneling port */
7444 static int
7445 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7446                              struct rte_eth_udp_tunnel *udp_tunnel)
7447 {
7448         int ret = 0;
7449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7450
7451         if (udp_tunnel == NULL)
7452                 return -EINVAL;
7453
7454         switch (udp_tunnel->prot_type) {
7455         case RTE_TUNNEL_TYPE_VXLAN:
7456                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7457                 break;
7458
7459         case RTE_TUNNEL_TYPE_GENEVE:
7460         case RTE_TUNNEL_TYPE_TEREDO:
7461                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7462                 ret = -1;
7463                 break;
7464
7465         default:
7466                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7467                 ret = -1;
7468                 break;
7469         }
7470
7471         return ret;
7472 }
7473
7474 /* Remove UDP tunneling port */
7475 static int
7476 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7477                              struct rte_eth_udp_tunnel *udp_tunnel)
7478 {
7479         int ret = 0;
7480         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7481
7482         if (udp_tunnel == NULL)
7483                 return -EINVAL;
7484
7485         switch (udp_tunnel->prot_type) {
7486         case RTE_TUNNEL_TYPE_VXLAN:
7487                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7488                 break;
7489         case RTE_TUNNEL_TYPE_GENEVE:
7490         case RTE_TUNNEL_TYPE_TEREDO:
7491                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7492                 ret = -1;
7493                 break;
7494         default:
7495                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7496                 ret = -1;
7497                 break;
7498         }
7499
7500         return ret;
7501 }
7502
7503 /* Calculate the maximum number of contiguous PF queues that are configured */
7504 static int
7505 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7506 {
7507         struct rte_eth_dev_data *data = pf->dev_data;
7508         int i, num;
7509         struct i40e_rx_queue *rxq;
7510
7511         num = 0;
7512         for (i = 0; i < pf->lan_nb_qps; i++) {
7513                 rxq = data->rx_queues[i];
7514                 if (rxq && rxq->q_set)
7515                         num++;
7516                 else
7517                         break;
7518         }
7519
7520         return num;
7521 }
7522
7523 /* Configure RSS */
7524 static int
7525 i40e_pf_config_rss(struct i40e_pf *pf)
7526 {
7527         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7528         struct rte_eth_rss_conf rss_conf;
7529         uint32_t i, lut = 0;
7530         uint16_t j, num;
7531
7532         /*
7533          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7534          * It's necessary to calculate the actual PF queues that are configured.
7535          */
7536         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7537                 num = i40e_pf_calc_configured_queues_num(pf);
7538         else
7539                 num = pf->dev_data->nb_rx_queues;
7540
7541         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7542         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7543                         num);
7544
7545         if (num == 0) {
7546                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7547                 return -ENOTSUP;
7548         }
7549
7550         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7551                 if (j == num)
7552                         j = 0;
7553                 lut = (lut << 8) | (j & ((0x1 <<
7554                         hw->func_caps.rss_table_entry_width) - 1));
7555                 if ((i & 3) == 3)
7556                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7557         }
7558
7559         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7560         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7561                 i40e_pf_disable_rss(pf);
7562                 return 0;
7563         }
7564         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7565                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7566                 /* Random default keys */
7567                 static uint32_t rss_key_default[] = {0x6b793944,
7568                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7569                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7570                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7571
7572                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7573                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7574                                                         sizeof(uint32_t);
7575         }
7576
7577         return i40e_hw_rss_hash_set(pf, &rss_conf);
7578 }
7579
7580 static int
7581 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7582                                struct rte_eth_tunnel_filter_conf *filter)
7583 {
7584         if (pf == NULL || filter == NULL) {
7585                 PMD_DRV_LOG(ERR, "Invalid parameter");
7586                 return -EINVAL;
7587         }
7588
7589         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7590                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7591                 return -EINVAL;
7592         }
7593
7594         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7595                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7596                 return -EINVAL;
7597         }
7598
7599         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7600                 (is_zero_ether_addr(&filter->outer_mac))) {
7601                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7602                 return -EINVAL;
7603         }
7604
7605         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7606                 (is_zero_ether_addr(&filter->inner_mac))) {
7607                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7608                 return -EINVAL;
7609         }
7610
7611         return 0;
7612 }
7613
7614 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7615 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7616 static int
7617 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7618 {
7619         uint32_t val, reg;
7620         int ret = -EINVAL;
7621
7622         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7623         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7624
7625         if (len == 3) {
7626                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7627         } else if (len == 4) {
7628                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7629         } else {
7630                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7631                 return ret;
7632         }
7633
7634         if (reg != val) {
7635                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7636                                                    reg, NULL);
7637                 if (ret != 0)
7638                         return ret;
7639         } else {
7640                 ret = 0;
7641         }
7642         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7643                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7644
7645         return ret;
7646 }
7647
7648 static int
7649 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7650 {
7651         int ret = -EINVAL;
7652
7653         if (!hw || !cfg)
7654                 return -EINVAL;
7655
7656         switch (cfg->cfg_type) {
7657         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7658                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7659                 break;
7660         default:
7661                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7662                 break;
7663         }
7664
7665         return ret;
7666 }
7667
7668 static int
7669 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7670                                enum rte_filter_op filter_op,
7671                                void *arg)
7672 {
7673         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7674         int ret = I40E_ERR_PARAM;
7675
7676         switch (filter_op) {
7677         case RTE_ETH_FILTER_SET:
7678                 ret = i40e_dev_global_config_set(hw,
7679                         (struct rte_eth_global_cfg *)arg);
7680                 break;
7681         default:
7682                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7683                 break;
7684         }
7685
7686         return ret;
7687 }
7688
7689 static int
7690 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7691                           enum rte_filter_op filter_op,
7692                           void *arg)
7693 {
7694         struct rte_eth_tunnel_filter_conf *filter;
7695         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7696         int ret = I40E_SUCCESS;
7697
7698         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7699
7700         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7701                 return I40E_ERR_PARAM;
7702
7703         switch (filter_op) {
7704         case RTE_ETH_FILTER_NOP:
7705                 if (!(pf->flags & I40E_FLAG_VXLAN))
7706                         ret = I40E_NOT_SUPPORTED;
7707                 break;
7708         case RTE_ETH_FILTER_ADD:
7709                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7710                 break;
7711         case RTE_ETH_FILTER_DELETE:
7712                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7713                 break;
7714         default:
7715                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7716                 ret = I40E_ERR_PARAM;
7717                 break;
7718         }
7719
7720         return ret;
7721 }
7722
7723 static int
7724 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7725 {
7726         int ret = 0;
7727         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7728
7729         /* RSS setup */
7730         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7731                 ret = i40e_pf_config_rss(pf);
7732         else
7733                 i40e_pf_disable_rss(pf);
7734
7735         return ret;
7736 }
7737
7738 /* Get the symmetric hash enable configurations per port */
7739 static void
7740 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7741 {
7742         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7743
7744         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7745 }
7746
7747 /* Set the symmetric hash enable configurations per port */
7748 static void
7749 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7750 {
7751         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7752
7753         if (enable > 0) {
7754                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7755                         PMD_DRV_LOG(INFO,
7756                                 "Symmetric hash has already been enabled");
7757                         return;
7758                 }
7759                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7760         } else {
7761                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7762                         PMD_DRV_LOG(INFO,
7763                                 "Symmetric hash has already been disabled");
7764                         return;
7765                 }
7766                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7767         }
7768         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7769         I40E_WRITE_FLUSH(hw);
7770 }
7771
7772 /*
7773  * Get global configurations of hash function type and symmetric hash enable
7774  * per flow type (pctype). Note that global configuration means it affects all
7775  * the ports on the same NIC.
7776  */
7777 static int
7778 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7779                                    struct rte_eth_hash_global_conf *g_cfg)
7780 {
7781         uint32_t reg, mask = I40E_FLOW_TYPES;
7782         uint16_t i;
7783         enum i40e_filter_pctype pctype;
7784
7785         memset(g_cfg, 0, sizeof(*g_cfg));
7786         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7787         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7788                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7789         else
7790                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7791         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7792                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7793
7794         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7795                 if (!(mask & (1UL << i)))
7796                         continue;
7797                 mask &= ~(1UL << i);
7798                 /* Bit set indicats the coresponding flow type is supported */
7799                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7800                 /* if flowtype is invalid, continue */
7801                 if (!I40E_VALID_FLOW(i))
7802                         continue;
7803                 pctype = i40e_flowtype_to_pctype(i);
7804                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7805                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7806                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7807         }
7808
7809         return 0;
7810 }
7811
7812 static int
7813 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7814 {
7815         uint32_t i;
7816         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7817
7818         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7819                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7820                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7821                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7822                                                 g_cfg->hash_func);
7823                 return -EINVAL;
7824         }
7825
7826         /*
7827          * As i40e supports less than 32 flow types, only first 32 bits need to
7828          * be checked.
7829          */
7830         mask0 = g_cfg->valid_bit_mask[0];
7831         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7832                 if (i == 0) {
7833                         /* Check if any unsupported flow type configured */
7834                         if ((mask0 | i40e_mask) ^ i40e_mask)
7835                                 goto mask_err;
7836                 } else {
7837                         if (g_cfg->valid_bit_mask[i])
7838                                 goto mask_err;
7839                 }
7840         }
7841
7842         return 0;
7843
7844 mask_err:
7845         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7846
7847         return -EINVAL;
7848 }
7849
7850 /*
7851  * Set global configurations of hash function type and symmetric hash enable
7852  * per flow type (pctype). Note any modifying global configuration will affect
7853  * all the ports on the same NIC.
7854  */
7855 static int
7856 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7857                                    struct rte_eth_hash_global_conf *g_cfg)
7858 {
7859         int ret;
7860         uint16_t i;
7861         uint32_t reg;
7862         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7863         enum i40e_filter_pctype pctype;
7864
7865         /* Check the input parameters */
7866         ret = i40e_hash_global_config_check(g_cfg);
7867         if (ret < 0)
7868                 return ret;
7869
7870         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7871                 if (!(mask0 & (1UL << i)))
7872                         continue;
7873                 mask0 &= ~(1UL << i);
7874                 /* if flowtype is invalid, continue */
7875                 if (!I40E_VALID_FLOW(i))
7876                         continue;
7877                 pctype = i40e_flowtype_to_pctype(i);
7878                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7879                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7880                 if (hw->mac.type == I40E_MAC_X722) {
7881                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7882                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7883                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7884                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7885                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7886                                   reg);
7887                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7888                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7889                                   reg);
7890                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7891                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7892                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7893                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7894                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7895                                   reg);
7896                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7897                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7898                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7899                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7900                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7901                                   reg);
7902                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7903                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7904                                   reg);
7905                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7906                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7907                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7908                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7909                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7910                                   reg);
7911                         } else {
7912                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7913                                   reg);
7914                         }
7915                 } else {
7916                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7917                 }
7918         }
7919
7920         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7921         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7922                 /* Toeplitz */
7923                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7924                         PMD_DRV_LOG(DEBUG,
7925                                 "Hash function already set to Toeplitz");
7926                         goto out;
7927                 }
7928                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7929         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7930                 /* Simple XOR */
7931                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7932                         PMD_DRV_LOG(DEBUG,
7933                                 "Hash function already set to Simple XOR");
7934                         goto out;
7935                 }
7936                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7937         } else
7938                 /* Use the default, and keep it as it is */
7939                 goto out;
7940
7941         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7942
7943 out:
7944         I40E_WRITE_FLUSH(hw);
7945
7946         return 0;
7947 }
7948
7949 /**
7950  * Valid input sets for hash and flow director filters per PCTYPE
7951  */
7952 static uint64_t
7953 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7954                 enum rte_filter_type filter)
7955 {
7956         uint64_t valid;
7957
7958         static const uint64_t valid_hash_inset_table[] = {
7959                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7960                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7961                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7962                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7963                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7964                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7965                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7966                         I40E_INSET_FLEX_PAYLOAD,
7967                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7968                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7969                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7970                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7971                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7972                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7973                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7974                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7975                         I40E_INSET_FLEX_PAYLOAD,
7976                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7977                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7978                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7979                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7980                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7981                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7982                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7983                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7984                         I40E_INSET_FLEX_PAYLOAD,
7985                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7986                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7987                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7988                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7989                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7990                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7991                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7992                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7993                         I40E_INSET_FLEX_PAYLOAD,
7994                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7995                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7996                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7997                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7998                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7999                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8000                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8001                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8002                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8003                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8004                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8005                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8007                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8008                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8009                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8010                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8011                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8012                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8013                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8014                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8015                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8016                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8017                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8018                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8019                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8020                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8021                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8022                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8023                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8024                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8025                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8026                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8027                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8028                         I40E_INSET_FLEX_PAYLOAD,
8029                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8030                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8031                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8032                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8033                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8034                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8035                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8036                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8037                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8038                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8039                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8041                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8042                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8043                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8044                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8045                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8049                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8050                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8051                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8052                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8053                         I40E_INSET_FLEX_PAYLOAD,
8054                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8055                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8056                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8058                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8059                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8060                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8061                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8062                         I40E_INSET_FLEX_PAYLOAD,
8063                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8064                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8065                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8067                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8068                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8069                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8070                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8071                         I40E_INSET_FLEX_PAYLOAD,
8072                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8076                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8077                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8078                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8079                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8080                         I40E_INSET_FLEX_PAYLOAD,
8081                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8082                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8083                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8084                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8085                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8086                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8087                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8088                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8089                         I40E_INSET_FLEX_PAYLOAD,
8090                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8091                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8092                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8093                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8094                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8095                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8096                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8097                         I40E_INSET_FLEX_PAYLOAD,
8098                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8099                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8100                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8101                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8102                         I40E_INSET_FLEX_PAYLOAD,
8103         };
8104
8105         /**
8106          * Flow director supports only fields defined in
8107          * union rte_eth_fdir_flow.
8108          */
8109         static const uint64_t valid_fdir_inset_table[] = {
8110                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8111                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8112                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8113                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8114                 I40E_INSET_IPV4_TTL,
8115                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8116                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8118                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8119                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8120                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8121                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8122                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8124                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8125                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8126                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8127                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8128                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8129                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8130                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8131                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8132                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8133                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8134                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8136                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8138                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8139                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8140                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8141                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8142                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8144                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8145                 I40E_INSET_SCTP_VT,
8146                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8147                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8150                 I40E_INSET_IPV4_TTL,
8151                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8152                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8154                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8155                 I40E_INSET_IPV6_HOP_LIMIT,
8156                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8157                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8159                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8160                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8162                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8164                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8165                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8166                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8167                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8170                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8172                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8174                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8175                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8176                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8177                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8178                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8179                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8180                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8181                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8184                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8185                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8186                 I40E_INSET_SCTP_VT,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8188                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8190                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8191                 I40E_INSET_IPV6_HOP_LIMIT,
8192                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8193                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8194                 I40E_INSET_LAST_ETHER_TYPE,
8195         };
8196
8197         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8198                 return 0;
8199         if (filter == RTE_ETH_FILTER_HASH)
8200                 valid = valid_hash_inset_table[pctype];
8201         else
8202                 valid = valid_fdir_inset_table[pctype];
8203
8204         return valid;
8205 }
8206
8207 /**
8208  * Validate if the input set is allowed for a specific PCTYPE
8209  */
8210 int
8211 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8212                 enum rte_filter_type filter, uint64_t inset)
8213 {
8214         uint64_t valid;
8215
8216         valid = i40e_get_valid_input_set(pctype, filter);
8217         if (inset & (~valid))
8218                 return -EINVAL;
8219
8220         return 0;
8221 }
8222
8223 /* default input set fields combination per pctype */
8224 uint64_t
8225 i40e_get_default_input_set(uint16_t pctype)
8226 {
8227         static const uint64_t default_inset_table[] = {
8228                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8229                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8230                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8231                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8232                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8233                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8234                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8235                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8236                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8237                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8238                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8240                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8241                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8242                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8243                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8244                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8245                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8246                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8247                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8248                         I40E_INSET_SCTP_VT,
8249                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8250                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8251                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8252                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8253                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8254                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8255                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8256                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8257                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8258                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8259                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8260                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8261                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8262                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8263                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8264                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8265                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8266                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8267                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8268                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8269                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8270                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8271                         I40E_INSET_SCTP_VT,
8272                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8273                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8274                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8275                         I40E_INSET_LAST_ETHER_TYPE,
8276         };
8277
8278         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8279                 return 0;
8280
8281         return default_inset_table[pctype];
8282 }
8283
8284 /**
8285  * Parse the input set from index to logical bit masks
8286  */
8287 static int
8288 i40e_parse_input_set(uint64_t *inset,
8289                      enum i40e_filter_pctype pctype,
8290                      enum rte_eth_input_set_field *field,
8291                      uint16_t size)
8292 {
8293         uint16_t i, j;
8294         int ret = -EINVAL;
8295
8296         static const struct {
8297                 enum rte_eth_input_set_field field;
8298                 uint64_t inset;
8299         } inset_convert_table[] = {
8300                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8301                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8302                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8303                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8304                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8305                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8306                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8307                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8308                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8309                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8310                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8311                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8312                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8313                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8314                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8315                         I40E_INSET_IPV6_NEXT_HDR},
8316                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8317                         I40E_INSET_IPV6_HOP_LIMIT},
8318                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8319                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8320                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8321                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8322                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8323                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8324                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8325                         I40E_INSET_SCTP_VT},
8326                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8327                         I40E_INSET_TUNNEL_DMAC},
8328                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8329                         I40E_INSET_VLAN_TUNNEL},
8330                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8331                         I40E_INSET_TUNNEL_ID},
8332                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8333                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8334                         I40E_INSET_FLEX_PAYLOAD_W1},
8335                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8336                         I40E_INSET_FLEX_PAYLOAD_W2},
8337                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8338                         I40E_INSET_FLEX_PAYLOAD_W3},
8339                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8340                         I40E_INSET_FLEX_PAYLOAD_W4},
8341                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8342                         I40E_INSET_FLEX_PAYLOAD_W5},
8343                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8344                         I40E_INSET_FLEX_PAYLOAD_W6},
8345                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8346                         I40E_INSET_FLEX_PAYLOAD_W7},
8347                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8348                         I40E_INSET_FLEX_PAYLOAD_W8},
8349         };
8350
8351         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8352                 return ret;
8353
8354         /* Only one item allowed for default or all */
8355         if (size == 1) {
8356                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8357                         *inset = i40e_get_default_input_set(pctype);
8358                         return 0;
8359                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8360                         *inset = I40E_INSET_NONE;
8361                         return 0;
8362                 }
8363         }
8364
8365         for (i = 0, *inset = 0; i < size; i++) {
8366                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8367                         if (field[i] == inset_convert_table[j].field) {
8368                                 *inset |= inset_convert_table[j].inset;
8369                                 break;
8370                         }
8371                 }
8372
8373                 /* It contains unsupported input set, return immediately */
8374                 if (j == RTE_DIM(inset_convert_table))
8375                         return ret;
8376         }
8377
8378         return 0;
8379 }
8380
8381 /**
8382  * Translate the input set from bit masks to register aware bit masks
8383  * and vice versa
8384  */
8385 uint64_t
8386 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8387 {
8388         uint64_t val = 0;
8389         uint16_t i;
8390
8391         struct inset_map {
8392                 uint64_t inset;
8393                 uint64_t inset_reg;
8394         };
8395
8396         static const struct inset_map inset_map_common[] = {
8397                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8398                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8399                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8400                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8401                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8402                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8403                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8404                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8405                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8406                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8407                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8408                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8409                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8410                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8411                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8412                 {I40E_INSET_TUNNEL_DMAC,
8413                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8414                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8415                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8416                 {I40E_INSET_TUNNEL_SRC_PORT,
8417                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8418                 {I40E_INSET_TUNNEL_DST_PORT,
8419                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8420                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8421                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8422                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8423                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8424                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8425                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8426                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8427                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8428                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8429         };
8430
8431     /* some different registers map in x722*/
8432         static const struct inset_map inset_map_diff_x722[] = {
8433                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8434                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8435                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8436                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8437         };
8438
8439         static const struct inset_map inset_map_diff_not_x722[] = {
8440                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8441                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8442                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8443                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8444         };
8445
8446         if (input == 0)
8447                 return val;
8448
8449         /* Translate input set to register aware inset */
8450         if (type == I40E_MAC_X722) {
8451                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8452                         if (input & inset_map_diff_x722[i].inset)
8453                                 val |= inset_map_diff_x722[i].inset_reg;
8454                 }
8455         } else {
8456                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8457                         if (input & inset_map_diff_not_x722[i].inset)
8458                                 val |= inset_map_diff_not_x722[i].inset_reg;
8459                 }
8460         }
8461
8462         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8463                 if (input & inset_map_common[i].inset)
8464                         val |= inset_map_common[i].inset_reg;
8465         }
8466
8467         return val;
8468 }
8469
8470 int
8471 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8472 {
8473         uint8_t i, idx = 0;
8474         uint64_t inset_need_mask = inset;
8475
8476         static const struct {
8477                 uint64_t inset;
8478                 uint32_t mask;
8479         } inset_mask_map[] = {
8480                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8481                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8482                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8483                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8484                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8485                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8486                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8487                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8488         };
8489
8490         if (!inset || !mask || !nb_elem)
8491                 return 0;
8492
8493         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8494                 /* Clear the inset bit, if no MASK is required,
8495                  * for example proto + ttl
8496                  */
8497                 if ((inset & inset_mask_map[i].inset) ==
8498                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8499                         inset_need_mask &= ~inset_mask_map[i].inset;
8500                 if (!inset_need_mask)
8501                         return 0;
8502         }
8503         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8504                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8505                     inset_mask_map[i].inset) {
8506                         if (idx >= nb_elem) {
8507                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8508                                 return -EINVAL;
8509                         }
8510                         mask[idx] = inset_mask_map[i].mask;
8511                         idx++;
8512                 }
8513         }
8514
8515         return idx;
8516 }
8517
8518 void
8519 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8520 {
8521         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8522
8523         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8524         if (reg != val)
8525                 i40e_write_rx_ctl(hw, addr, val);
8526         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8527                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8528 }
8529
8530 static void
8531 i40e_filter_input_set_init(struct i40e_pf *pf)
8532 {
8533         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8534         enum i40e_filter_pctype pctype;
8535         uint64_t input_set, inset_reg;
8536         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8537         int num, i;
8538
8539         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8540              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8541                 if (hw->mac.type == I40E_MAC_X722) {
8542                         if (!I40E_VALID_PCTYPE_X722(pctype))
8543                                 continue;
8544                 } else {
8545                         if (!I40E_VALID_PCTYPE(pctype))
8546                                 continue;
8547                 }
8548
8549                 input_set = i40e_get_default_input_set(pctype);
8550
8551                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8552                                                    I40E_INSET_MASK_NUM_REG);
8553                 if (num < 0)
8554                         return;
8555                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8556                                         input_set);
8557
8558                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8559                                       (uint32_t)(inset_reg & UINT32_MAX));
8560                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8561                                      (uint32_t)((inset_reg >>
8562                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8563                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8564                                       (uint32_t)(inset_reg & UINT32_MAX));
8565                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8566                                      (uint32_t)((inset_reg >>
8567                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8568
8569                 for (i = 0; i < num; i++) {
8570                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8571                                              mask_reg[i]);
8572                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8573                                              mask_reg[i]);
8574                 }
8575                 /*clear unused mask registers of the pctype */
8576                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8577                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8578                                              0);
8579                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8580                                              0);
8581                 }
8582                 I40E_WRITE_FLUSH(hw);
8583
8584                 /* store the default input set */
8585                 pf->hash_input_set[pctype] = input_set;
8586                 pf->fdir.input_set[pctype] = input_set;
8587         }
8588 }
8589
8590 int
8591 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8592                          struct rte_eth_input_set_conf *conf)
8593 {
8594         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8595         enum i40e_filter_pctype pctype;
8596         uint64_t input_set, inset_reg = 0;
8597         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8598         int ret, i, num;
8599
8600         if (!conf) {
8601                 PMD_DRV_LOG(ERR, "Invalid pointer");
8602                 return -EFAULT;
8603         }
8604         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8605             conf->op != RTE_ETH_INPUT_SET_ADD) {
8606                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8607                 return -EINVAL;
8608         }
8609
8610         if (!I40E_VALID_FLOW(conf->flow_type)) {
8611                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8612                 return -EINVAL;
8613         }
8614
8615         if (hw->mac.type == I40E_MAC_X722) {
8616                 /* get translated pctype value in fd pctype register */
8617                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8618                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8619                         conf->flow_type)));
8620         } else
8621                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8622
8623         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8624                                    conf->inset_size);
8625         if (ret) {
8626                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8627                 return -EINVAL;
8628         }
8629         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8630                                     input_set) != 0) {
8631                 PMD_DRV_LOG(ERR, "Invalid input set");
8632                 return -EINVAL;
8633         }
8634         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8635                 /* get inset value in register */
8636                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8637                 inset_reg <<= I40E_32_BIT_WIDTH;
8638                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8639                 input_set |= pf->hash_input_set[pctype];
8640         }
8641         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8642                                            I40E_INSET_MASK_NUM_REG);
8643         if (num < 0)
8644                 return -EINVAL;
8645
8646         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8647
8648         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8649                               (uint32_t)(inset_reg & UINT32_MAX));
8650         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8651                              (uint32_t)((inset_reg >>
8652                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8653
8654         for (i = 0; i < num; i++)
8655                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8656                                      mask_reg[i]);
8657         /*clear unused mask registers of the pctype */
8658         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8659                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8660                                      0);
8661         I40E_WRITE_FLUSH(hw);
8662
8663         pf->hash_input_set[pctype] = input_set;
8664         return 0;
8665 }
8666
8667 int
8668 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8669                          struct rte_eth_input_set_conf *conf)
8670 {
8671         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8672         enum i40e_filter_pctype pctype;
8673         uint64_t input_set, inset_reg = 0;
8674         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8675         int ret, i, num;
8676
8677         if (!hw || !conf) {
8678                 PMD_DRV_LOG(ERR, "Invalid pointer");
8679                 return -EFAULT;
8680         }
8681         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8682             conf->op != RTE_ETH_INPUT_SET_ADD) {
8683                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8684                 return -EINVAL;
8685         }
8686
8687         if (!I40E_VALID_FLOW(conf->flow_type)) {
8688                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8689                 return -EINVAL;
8690         }
8691
8692         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8693
8694         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8695                                    conf->inset_size);
8696         if (ret) {
8697                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8698                 return -EINVAL;
8699         }
8700         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8701                                     input_set) != 0) {
8702                 PMD_DRV_LOG(ERR, "Invalid input set");
8703                 return -EINVAL;
8704         }
8705
8706         /* get inset value in register */
8707         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8708         inset_reg <<= I40E_32_BIT_WIDTH;
8709         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8710
8711         /* Can not change the inset reg for flex payload for fdir,
8712          * it is done by writing I40E_PRTQF_FD_FLXINSET
8713          * in i40e_set_flex_mask_on_pctype.
8714          */
8715         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8716                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8717         else
8718                 input_set |= pf->fdir.input_set[pctype];
8719         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8720                                            I40E_INSET_MASK_NUM_REG);
8721         if (num < 0)
8722                 return -EINVAL;
8723
8724         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8725
8726         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8727                               (uint32_t)(inset_reg & UINT32_MAX));
8728         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8729                              (uint32_t)((inset_reg >>
8730                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8731
8732         for (i = 0; i < num; i++)
8733                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8734                                      mask_reg[i]);
8735         /*clear unused mask registers of the pctype */
8736         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8737                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8738                                      0);
8739         I40E_WRITE_FLUSH(hw);
8740
8741         pf->fdir.input_set[pctype] = input_set;
8742         return 0;
8743 }
8744
8745 static int
8746 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8747 {
8748         int ret = 0;
8749
8750         if (!hw || !info) {
8751                 PMD_DRV_LOG(ERR, "Invalid pointer");
8752                 return -EFAULT;
8753         }
8754
8755         switch (info->info_type) {
8756         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8757                 i40e_get_symmetric_hash_enable_per_port(hw,
8758                                         &(info->info.enable));
8759                 break;
8760         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8761                 ret = i40e_get_hash_filter_global_config(hw,
8762                                 &(info->info.global_conf));
8763                 break;
8764         default:
8765                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8766                                                         info->info_type);
8767                 ret = -EINVAL;
8768                 break;
8769         }
8770
8771         return ret;
8772 }
8773
8774 static int
8775 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8776 {
8777         int ret = 0;
8778
8779         if (!hw || !info) {
8780                 PMD_DRV_LOG(ERR, "Invalid pointer");
8781                 return -EFAULT;
8782         }
8783
8784         switch (info->info_type) {
8785         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8786                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8787                 break;
8788         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8789                 ret = i40e_set_hash_filter_global_config(hw,
8790                                 &(info->info.global_conf));
8791                 break;
8792         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8793                 ret = i40e_hash_filter_inset_select(hw,
8794                                                &(info->info.input_set_conf));
8795                 break;
8796
8797         default:
8798                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8799                                                         info->info_type);
8800                 ret = -EINVAL;
8801                 break;
8802         }
8803
8804         return ret;
8805 }
8806
8807 /* Operations for hash function */
8808 static int
8809 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8810                       enum rte_filter_op filter_op,
8811                       void *arg)
8812 {
8813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8814         int ret = 0;
8815
8816         switch (filter_op) {
8817         case RTE_ETH_FILTER_NOP:
8818                 break;
8819         case RTE_ETH_FILTER_GET:
8820                 ret = i40e_hash_filter_get(hw,
8821                         (struct rte_eth_hash_filter_info *)arg);
8822                 break;
8823         case RTE_ETH_FILTER_SET:
8824                 ret = i40e_hash_filter_set(hw,
8825                         (struct rte_eth_hash_filter_info *)arg);
8826                 break;
8827         default:
8828                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8829                                                                 filter_op);
8830                 ret = -ENOTSUP;
8831                 break;
8832         }
8833
8834         return ret;
8835 }
8836
8837 /* Convert ethertype filter structure */
8838 static int
8839 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8840                               struct i40e_ethertype_filter *filter)
8841 {
8842         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8843         filter->input.ether_type = input->ether_type;
8844         filter->flags = input->flags;
8845         filter->queue = input->queue;
8846
8847         return 0;
8848 }
8849
8850 /* Check if there exists the ehtertype filter */
8851 struct i40e_ethertype_filter *
8852 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8853                                 const struct i40e_ethertype_filter_input *input)
8854 {
8855         int ret;
8856
8857         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8858         if (ret < 0)
8859                 return NULL;
8860
8861         return ethertype_rule->hash_map[ret];
8862 }
8863
8864 /* Add ethertype filter in SW list */
8865 static int
8866 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8867                                 struct i40e_ethertype_filter *filter)
8868 {
8869         struct i40e_ethertype_rule *rule = &pf->ethertype;
8870         int ret;
8871
8872         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8873         if (ret < 0) {
8874                 PMD_DRV_LOG(ERR,
8875                             "Failed to insert ethertype filter"
8876                             " to hash table %d!",
8877                             ret);
8878                 return ret;
8879         }
8880         rule->hash_map[ret] = filter;
8881
8882         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8883
8884         return 0;
8885 }
8886
8887 /* Delete ethertype filter in SW list */
8888 int
8889 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8890                              struct i40e_ethertype_filter_input *input)
8891 {
8892         struct i40e_ethertype_rule *rule = &pf->ethertype;
8893         struct i40e_ethertype_filter *filter;
8894         int ret;
8895
8896         ret = rte_hash_del_key(rule->hash_table, input);
8897         if (ret < 0) {
8898                 PMD_DRV_LOG(ERR,
8899                             "Failed to delete ethertype filter"
8900                             " to hash table %d!",
8901                             ret);
8902                 return ret;
8903         }
8904         filter = rule->hash_map[ret];
8905         rule->hash_map[ret] = NULL;
8906
8907         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8908         rte_free(filter);
8909
8910         return 0;
8911 }
8912
8913 /*
8914  * Configure ethertype filter, which can director packet by filtering
8915  * with mac address and ether_type or only ether_type
8916  */
8917 int
8918 i40e_ethertype_filter_set(struct i40e_pf *pf,
8919                         struct rte_eth_ethertype_filter *filter,
8920                         bool add)
8921 {
8922         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8923         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8924         struct i40e_ethertype_filter *ethertype_filter, *node;
8925         struct i40e_ethertype_filter check_filter;
8926         struct i40e_control_filter_stats stats;
8927         uint16_t flags = 0;
8928         int ret;
8929
8930         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8931                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8932                 return -EINVAL;
8933         }
8934         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8935                 filter->ether_type == ETHER_TYPE_IPv6) {
8936                 PMD_DRV_LOG(ERR,
8937                         "unsupported ether_type(0x%04x) in control packet filter.",
8938                         filter->ether_type);
8939                 return -EINVAL;
8940         }
8941         if (filter->ether_type == ETHER_TYPE_VLAN)
8942                 PMD_DRV_LOG(WARNING,
8943                         "filter vlan ether_type in first tag is not supported.");
8944
8945         /* Check if there is the filter in SW list */
8946         memset(&check_filter, 0, sizeof(check_filter));
8947         i40e_ethertype_filter_convert(filter, &check_filter);
8948         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8949                                                &check_filter.input);
8950         if (add && node) {
8951                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8952                 return -EINVAL;
8953         }
8954
8955         if (!add && !node) {
8956                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8957                 return -EINVAL;
8958         }
8959
8960         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8961                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8962         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8963                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8964         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8965
8966         memset(&stats, 0, sizeof(stats));
8967         ret = i40e_aq_add_rem_control_packet_filter(hw,
8968                         filter->mac_addr.addr_bytes,
8969                         filter->ether_type, flags,
8970                         pf->main_vsi->seid,
8971                         filter->queue, add, &stats, NULL);
8972
8973         PMD_DRV_LOG(INFO,
8974                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8975                 ret, stats.mac_etype_used, stats.etype_used,
8976                 stats.mac_etype_free, stats.etype_free);
8977         if (ret < 0)
8978                 return -ENOSYS;
8979
8980         /* Add or delete a filter in SW list */
8981         if (add) {
8982                 ethertype_filter = rte_zmalloc("ethertype_filter",
8983                                        sizeof(*ethertype_filter), 0);
8984                 rte_memcpy(ethertype_filter, &check_filter,
8985                            sizeof(check_filter));
8986                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8987         } else {
8988                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8989         }
8990
8991         return ret;
8992 }
8993
8994 /*
8995  * Handle operations for ethertype filter.
8996  */
8997 static int
8998 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8999                                 enum rte_filter_op filter_op,
9000                                 void *arg)
9001 {
9002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9003         int ret = 0;
9004
9005         if (filter_op == RTE_ETH_FILTER_NOP)
9006                 return ret;
9007
9008         if (arg == NULL) {
9009                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9010                             filter_op);
9011                 return -EINVAL;
9012         }
9013
9014         switch (filter_op) {
9015         case RTE_ETH_FILTER_ADD:
9016                 ret = i40e_ethertype_filter_set(pf,
9017                         (struct rte_eth_ethertype_filter *)arg,
9018                         TRUE);
9019                 break;
9020         case RTE_ETH_FILTER_DELETE:
9021                 ret = i40e_ethertype_filter_set(pf,
9022                         (struct rte_eth_ethertype_filter *)arg,
9023                         FALSE);
9024                 break;
9025         default:
9026                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9027                 ret = -ENOSYS;
9028                 break;
9029         }
9030         return ret;
9031 }
9032
9033 static int
9034 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9035                      enum rte_filter_type filter_type,
9036                      enum rte_filter_op filter_op,
9037                      void *arg)
9038 {
9039         int ret = 0;
9040
9041         if (dev == NULL)
9042                 return -EINVAL;
9043
9044         switch (filter_type) {
9045         case RTE_ETH_FILTER_NONE:
9046                 /* For global configuration */
9047                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9048                 break;
9049         case RTE_ETH_FILTER_HASH:
9050                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9051                 break;
9052         case RTE_ETH_FILTER_MACVLAN:
9053                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9054                 break;
9055         case RTE_ETH_FILTER_ETHERTYPE:
9056                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9057                 break;
9058         case RTE_ETH_FILTER_TUNNEL:
9059                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9060                 break;
9061         case RTE_ETH_FILTER_FDIR:
9062                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9063                 break;
9064         case RTE_ETH_FILTER_GENERIC:
9065                 if (filter_op != RTE_ETH_FILTER_GET)
9066                         return -EINVAL;
9067                 *(const void **)arg = &i40e_flow_ops;
9068                 break;
9069         default:
9070                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9071                                                         filter_type);
9072                 ret = -EINVAL;
9073                 break;
9074         }
9075
9076         return ret;
9077 }
9078
9079 /*
9080  * Check and enable Extended Tag.
9081  * Enabling Extended Tag is important for 40G performance.
9082  */
9083 static void
9084 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9085 {
9086         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9087         uint32_t buf = 0;
9088         int ret;
9089
9090         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9091                                       PCI_DEV_CAP_REG);
9092         if (ret < 0) {
9093                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9094                             PCI_DEV_CAP_REG);
9095                 return;
9096         }
9097         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9098                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9099                 return;
9100         }
9101
9102         buf = 0;
9103         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9104                                       PCI_DEV_CTRL_REG);
9105         if (ret < 0) {
9106                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9107                             PCI_DEV_CTRL_REG);
9108                 return;
9109         }
9110         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9111                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9112                 return;
9113         }
9114         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9115         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9116                                        PCI_DEV_CTRL_REG);
9117         if (ret < 0) {
9118                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9119                             PCI_DEV_CTRL_REG);
9120                 return;
9121         }
9122 }
9123
9124 /*
9125  * As some registers wouldn't be reset unless a global hardware reset,
9126  * hardware initialization is needed to put those registers into an
9127  * expected initial state.
9128  */
9129 static void
9130 i40e_hw_init(struct rte_eth_dev *dev)
9131 {
9132         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9133
9134         i40e_enable_extended_tag(dev);
9135
9136         /* clear the PF Queue Filter control register */
9137         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9138
9139         /* Disable symmetric hash per port */
9140         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9141 }
9142
9143 enum i40e_filter_pctype
9144 i40e_flowtype_to_pctype(uint16_t flow_type)
9145 {
9146         static const enum i40e_filter_pctype pctype_table[] = {
9147                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9148                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9149                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9150                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9151                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9152                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9153                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9154                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9155                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9156                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9157                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9158                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9159                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9160                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9161                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9162                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9163                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9164                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9165                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9166         };
9167
9168         return pctype_table[flow_type];
9169 }
9170
9171 uint16_t
9172 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9173 {
9174         static const uint16_t flowtype_table[] = {
9175                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9176                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9177                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9178                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9179                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9180                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9181                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9182                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9183                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9184                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9185                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9186                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9187                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9188                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9189                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9190                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9191                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9192                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9193                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9194                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9195                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9196                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9197                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9198                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9199                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9200                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9201                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9202                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9203                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9204                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9205                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9206         };
9207
9208         return flowtype_table[pctype];
9209 }
9210
9211 /*
9212  * On X710, performance number is far from the expectation on recent firmware
9213  * versions; on XL710, performance number is also far from the expectation on
9214  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9215  * mode is enabled and port MAC address is equal to the packet destination MAC
9216  * address. The fix for this issue may not be integrated in the following
9217  * firmware version. So the workaround in software driver is needed. It needs
9218  * to modify the initial values of 3 internal only registers for both X710 and
9219  * XL710. Note that the values for X710 or XL710 could be different, and the
9220  * workaround can be removed when it is fixed in firmware in the future.
9221  */
9222
9223 /* For both X710 and XL710 */
9224 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9225 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9226
9227 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9228 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9229
9230 /* For X722 */
9231 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9232 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9233
9234 /* For X710 */
9235 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9236 /* For XL710 */
9237 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9238 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9239
9240 static int
9241 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9242 {
9243         enum i40e_status_code status;
9244         struct i40e_aq_get_phy_abilities_resp phy_ab;
9245         int ret = -ENOTSUP;
9246
9247         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9248                                               NULL);
9249
9250         if (status) {
9251                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9252                         status);
9253                 return ret;
9254         }
9255
9256         return 0;
9257 }
9258
9259 static void
9260 i40e_configure_registers(struct i40e_hw *hw)
9261 {
9262         static struct {
9263                 uint32_t addr;
9264                 uint64_t val;
9265         } reg_table[] = {
9266                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9267                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9268                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9269         };
9270         uint64_t reg;
9271         uint32_t i;
9272         int ret;
9273
9274         for (i = 0; i < RTE_DIM(reg_table); i++) {
9275                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9276                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9277                                 reg_table[i].val =
9278                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9279                         else /* For X710/XL710/XXV710 */
9280                                 reg_table[i].val =
9281                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9282                 }
9283
9284                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9285                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9286                                 reg_table[i].val =
9287                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9288                         else /* For X710/XL710/XXV710 */
9289                                 reg_table[i].val =
9290                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9291                 }
9292
9293                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9294                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9295                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9296                                 reg_table[i].val =
9297                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9298                         else /* For X710 */
9299                                 reg_table[i].val =
9300                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9301                 }
9302
9303                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9304                                                         &reg, NULL);
9305                 if (ret < 0) {
9306                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9307                                                         reg_table[i].addr);
9308                         break;
9309                 }
9310                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9311                                                 reg_table[i].addr, reg);
9312                 if (reg == reg_table[i].val)
9313                         continue;
9314
9315                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9316                                                 reg_table[i].val, NULL);
9317                 if (ret < 0) {
9318                         PMD_DRV_LOG(ERR,
9319                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9320                                 reg_table[i].val, reg_table[i].addr);
9321                         break;
9322                 }
9323                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9324                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9325         }
9326 }
9327
9328 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9329 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9330 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9331 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9332 static int
9333 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9334 {
9335         uint32_t reg;
9336         int ret;
9337
9338         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9339                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9340                 return -EINVAL;
9341         }
9342
9343         /* Configure for double VLAN RX stripping */
9344         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9345         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9346                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9347                 ret = i40e_aq_debug_write_register(hw,
9348                                                    I40E_VSI_TSR(vsi->vsi_id),
9349                                                    reg, NULL);
9350                 if (ret < 0) {
9351                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9352                                     vsi->vsi_id);
9353                         return I40E_ERR_CONFIG;
9354                 }
9355         }
9356
9357         /* Configure for double VLAN TX insertion */
9358         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9359         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9360                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9361                 ret = i40e_aq_debug_write_register(hw,
9362                                                    I40E_VSI_L2TAGSTXVALID(
9363                                                    vsi->vsi_id), reg, NULL);
9364                 if (ret < 0) {
9365                         PMD_DRV_LOG(ERR,
9366                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9367                                 vsi->vsi_id);
9368                         return I40E_ERR_CONFIG;
9369                 }
9370         }
9371
9372         return 0;
9373 }
9374
9375 /**
9376  * i40e_aq_add_mirror_rule
9377  * @hw: pointer to the hardware structure
9378  * @seid: VEB seid to add mirror rule to
9379  * @dst_id: destination vsi seid
9380  * @entries: Buffer which contains the entities to be mirrored
9381  * @count: number of entities contained in the buffer
9382  * @rule_id:the rule_id of the rule to be added
9383  *
9384  * Add a mirror rule for a given veb.
9385  *
9386  **/
9387 static enum i40e_status_code
9388 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9389                         uint16_t seid, uint16_t dst_id,
9390                         uint16_t rule_type, uint16_t *entries,
9391                         uint16_t count, uint16_t *rule_id)
9392 {
9393         struct i40e_aq_desc desc;
9394         struct i40e_aqc_add_delete_mirror_rule cmd;
9395         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9396                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9397                 &desc.params.raw;
9398         uint16_t buff_len;
9399         enum i40e_status_code status;
9400
9401         i40e_fill_default_direct_cmd_desc(&desc,
9402                                           i40e_aqc_opc_add_mirror_rule);
9403         memset(&cmd, 0, sizeof(cmd));
9404
9405         buff_len = sizeof(uint16_t) * count;
9406         desc.datalen = rte_cpu_to_le_16(buff_len);
9407         if (buff_len > 0)
9408                 desc.flags |= rte_cpu_to_le_16(
9409                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9410         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9411                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9412         cmd.num_entries = rte_cpu_to_le_16(count);
9413         cmd.seid = rte_cpu_to_le_16(seid);
9414         cmd.destination = rte_cpu_to_le_16(dst_id);
9415
9416         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9417         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9418         PMD_DRV_LOG(INFO,
9419                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9420                 hw->aq.asq_last_status, resp->rule_id,
9421                 resp->mirror_rules_used, resp->mirror_rules_free);
9422         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9423
9424         return status;
9425 }
9426
9427 /**
9428  * i40e_aq_del_mirror_rule
9429  * @hw: pointer to the hardware structure
9430  * @seid: VEB seid to add mirror rule to
9431  * @entries: Buffer which contains the entities to be mirrored
9432  * @count: number of entities contained in the buffer
9433  * @rule_id:the rule_id of the rule to be delete
9434  *
9435  * Delete a mirror rule for a given veb.
9436  *
9437  **/
9438 static enum i40e_status_code
9439 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9440                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9441                 uint16_t count, uint16_t rule_id)
9442 {
9443         struct i40e_aq_desc desc;
9444         struct i40e_aqc_add_delete_mirror_rule cmd;
9445         uint16_t buff_len = 0;
9446         enum i40e_status_code status;
9447         void *buff = NULL;
9448
9449         i40e_fill_default_direct_cmd_desc(&desc,
9450                                           i40e_aqc_opc_delete_mirror_rule);
9451         memset(&cmd, 0, sizeof(cmd));
9452         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9453                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9454                                                           I40E_AQ_FLAG_RD));
9455                 cmd.num_entries = count;
9456                 buff_len = sizeof(uint16_t) * count;
9457                 desc.datalen = rte_cpu_to_le_16(buff_len);
9458                 buff = (void *)entries;
9459         } else
9460                 /* rule id is filled in destination field for deleting mirror rule */
9461                 cmd.destination = rte_cpu_to_le_16(rule_id);
9462
9463         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9464                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9465         cmd.seid = rte_cpu_to_le_16(seid);
9466
9467         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9468         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9469
9470         return status;
9471 }
9472
9473 /**
9474  * i40e_mirror_rule_set
9475  * @dev: pointer to the hardware structure
9476  * @mirror_conf: mirror rule info
9477  * @sw_id: mirror rule's sw_id
9478  * @on: enable/disable
9479  *
9480  * set a mirror rule.
9481  *
9482  **/
9483 static int
9484 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9485                         struct rte_eth_mirror_conf *mirror_conf,
9486                         uint8_t sw_id, uint8_t on)
9487 {
9488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9490         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9491         struct i40e_mirror_rule *parent = NULL;
9492         uint16_t seid, dst_seid, rule_id;
9493         uint16_t i, j = 0;
9494         int ret;
9495
9496         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9497
9498         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9499                 PMD_DRV_LOG(ERR,
9500                         "mirror rule can not be configured without veb or vfs.");
9501                 return -ENOSYS;
9502         }
9503         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9504                 PMD_DRV_LOG(ERR, "mirror table is full.");
9505                 return -ENOSPC;
9506         }
9507         if (mirror_conf->dst_pool > pf->vf_num) {
9508                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9509                                  mirror_conf->dst_pool);
9510                 return -EINVAL;
9511         }
9512
9513         seid = pf->main_vsi->veb->seid;
9514
9515         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9516                 if (sw_id <= it->index) {
9517                         mirr_rule = it;
9518                         break;
9519                 }
9520                 parent = it;
9521         }
9522         if (mirr_rule && sw_id == mirr_rule->index) {
9523                 if (on) {
9524                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9525                         return -EEXIST;
9526                 } else {
9527                         ret = i40e_aq_del_mirror_rule(hw, seid,
9528                                         mirr_rule->rule_type,
9529                                         mirr_rule->entries,
9530                                         mirr_rule->num_entries, mirr_rule->id);
9531                         if (ret < 0) {
9532                                 PMD_DRV_LOG(ERR,
9533                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9534                                         ret, hw->aq.asq_last_status);
9535                                 return -ENOSYS;
9536                         }
9537                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9538                         rte_free(mirr_rule);
9539                         pf->nb_mirror_rule--;
9540                         return 0;
9541                 }
9542         } else if (!on) {
9543                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9544                 return -ENOENT;
9545         }
9546
9547         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9548                                 sizeof(struct i40e_mirror_rule) , 0);
9549         if (!mirr_rule) {
9550                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9551                 return I40E_ERR_NO_MEMORY;
9552         }
9553         switch (mirror_conf->rule_type) {
9554         case ETH_MIRROR_VLAN:
9555                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9556                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9557                                 mirr_rule->entries[j] =
9558                                         mirror_conf->vlan.vlan_id[i];
9559                                 j++;
9560                         }
9561                 }
9562                 if (j == 0) {
9563                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9564                         rte_free(mirr_rule);
9565                         return -EINVAL;
9566                 }
9567                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9568                 break;
9569         case ETH_MIRROR_VIRTUAL_POOL_UP:
9570         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9571                 /* check if the specified pool bit is out of range */
9572                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9573                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9574                         rte_free(mirr_rule);
9575                         return -EINVAL;
9576                 }
9577                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9578                         if (mirror_conf->pool_mask & (1ULL << i)) {
9579                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9580                                 j++;
9581                         }
9582                 }
9583                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9584                         /* add pf vsi to entries */
9585                         mirr_rule->entries[j] = pf->main_vsi_seid;
9586                         j++;
9587                 }
9588                 if (j == 0) {
9589                         PMD_DRV_LOG(ERR, "pool is not specified.");
9590                         rte_free(mirr_rule);
9591                         return -EINVAL;
9592                 }
9593                 /* egress and ingress in aq commands means from switch but not port */
9594                 mirr_rule->rule_type =
9595                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9596                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9597                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9598                 break;
9599         case ETH_MIRROR_UPLINK_PORT:
9600                 /* egress and ingress in aq commands means from switch but not port*/
9601                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9602                 break;
9603         case ETH_MIRROR_DOWNLINK_PORT:
9604                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9605                 break;
9606         default:
9607                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9608                         mirror_conf->rule_type);
9609                 rte_free(mirr_rule);
9610                 return -EINVAL;
9611         }
9612
9613         /* If the dst_pool is equal to vf_num, consider it as PF */
9614         if (mirror_conf->dst_pool == pf->vf_num)
9615                 dst_seid = pf->main_vsi_seid;
9616         else
9617                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9618
9619         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9620                                       mirr_rule->rule_type, mirr_rule->entries,
9621                                       j, &rule_id);
9622         if (ret < 0) {
9623                 PMD_DRV_LOG(ERR,
9624                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9625                         ret, hw->aq.asq_last_status);
9626                 rte_free(mirr_rule);
9627                 return -ENOSYS;
9628         }
9629
9630         mirr_rule->index = sw_id;
9631         mirr_rule->num_entries = j;
9632         mirr_rule->id = rule_id;
9633         mirr_rule->dst_vsi_seid = dst_seid;
9634
9635         if (parent)
9636                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9637         else
9638                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9639
9640         pf->nb_mirror_rule++;
9641         return 0;
9642 }
9643
9644 /**
9645  * i40e_mirror_rule_reset
9646  * @dev: pointer to the device
9647  * @sw_id: mirror rule's sw_id
9648  *
9649  * reset a mirror rule.
9650  *
9651  **/
9652 static int
9653 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9654 {
9655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9657         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9658         uint16_t seid;
9659         int ret;
9660
9661         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9662
9663         seid = pf->main_vsi->veb->seid;
9664
9665         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9666                 if (sw_id == it->index) {
9667                         mirr_rule = it;
9668                         break;
9669                 }
9670         }
9671         if (mirr_rule) {
9672                 ret = i40e_aq_del_mirror_rule(hw, seid,
9673                                 mirr_rule->rule_type,
9674                                 mirr_rule->entries,
9675                                 mirr_rule->num_entries, mirr_rule->id);
9676                 if (ret < 0) {
9677                         PMD_DRV_LOG(ERR,
9678                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9679                                 ret, hw->aq.asq_last_status);
9680                         return -ENOSYS;
9681                 }
9682                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9683                 rte_free(mirr_rule);
9684                 pf->nb_mirror_rule--;
9685         } else {
9686                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9687                 return -ENOENT;
9688         }
9689         return 0;
9690 }
9691
9692 static uint64_t
9693 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9694 {
9695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9696         uint64_t systim_cycles;
9697
9698         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9699         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9700                         << 32;
9701
9702         return systim_cycles;
9703 }
9704
9705 static uint64_t
9706 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9707 {
9708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9709         uint64_t rx_tstamp;
9710
9711         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9712         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9713                         << 32;
9714
9715         return rx_tstamp;
9716 }
9717
9718 static uint64_t
9719 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9720 {
9721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9722         uint64_t tx_tstamp;
9723
9724         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9725         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9726                         << 32;
9727
9728         return tx_tstamp;
9729 }
9730
9731 static void
9732 i40e_start_timecounters(struct rte_eth_dev *dev)
9733 {
9734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9735         struct i40e_adapter *adapter =
9736                         (struct i40e_adapter *)dev->data->dev_private;
9737         struct rte_eth_link link;
9738         uint32_t tsync_inc_l;
9739         uint32_t tsync_inc_h;
9740
9741         /* Get current link speed. */
9742         memset(&link, 0, sizeof(link));
9743         i40e_dev_link_update(dev, 1);
9744         rte_i40e_dev_atomic_read_link_status(dev, &link);
9745
9746         switch (link.link_speed) {
9747         case ETH_SPEED_NUM_40G:
9748                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9749                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9750                 break;
9751         case ETH_SPEED_NUM_10G:
9752                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9753                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9754                 break;
9755         case ETH_SPEED_NUM_1G:
9756                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9757                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9758                 break;
9759         default:
9760                 tsync_inc_l = 0x0;
9761                 tsync_inc_h = 0x0;
9762         }
9763
9764         /* Set the timesync increment value. */
9765         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9766         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9767
9768         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9769         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9770         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9771
9772         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9773         adapter->systime_tc.cc_shift = 0;
9774         adapter->systime_tc.nsec_mask = 0;
9775
9776         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9777         adapter->rx_tstamp_tc.cc_shift = 0;
9778         adapter->rx_tstamp_tc.nsec_mask = 0;
9779
9780         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9781         adapter->tx_tstamp_tc.cc_shift = 0;
9782         adapter->tx_tstamp_tc.nsec_mask = 0;
9783 }
9784
9785 static int
9786 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9787 {
9788         struct i40e_adapter *adapter =
9789                         (struct i40e_adapter *)dev->data->dev_private;
9790
9791         adapter->systime_tc.nsec += delta;
9792         adapter->rx_tstamp_tc.nsec += delta;
9793         adapter->tx_tstamp_tc.nsec += delta;
9794
9795         return 0;
9796 }
9797
9798 static int
9799 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9800 {
9801         uint64_t ns;
9802         struct i40e_adapter *adapter =
9803                         (struct i40e_adapter *)dev->data->dev_private;
9804
9805         ns = rte_timespec_to_ns(ts);
9806
9807         /* Set the timecounters to a new value. */
9808         adapter->systime_tc.nsec = ns;
9809         adapter->rx_tstamp_tc.nsec = ns;
9810         adapter->tx_tstamp_tc.nsec = ns;
9811
9812         return 0;
9813 }
9814
9815 static int
9816 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9817 {
9818         uint64_t ns, systime_cycles;
9819         struct i40e_adapter *adapter =
9820                         (struct i40e_adapter *)dev->data->dev_private;
9821
9822         systime_cycles = i40e_read_systime_cyclecounter(dev);
9823         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9824         *ts = rte_ns_to_timespec(ns);
9825
9826         return 0;
9827 }
9828
9829 static int
9830 i40e_timesync_enable(struct rte_eth_dev *dev)
9831 {
9832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9833         uint32_t tsync_ctl_l;
9834         uint32_t tsync_ctl_h;
9835
9836         /* Stop the timesync system time. */
9837         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9838         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9839         /* Reset the timesync system time value. */
9840         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9841         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9842
9843         i40e_start_timecounters(dev);
9844
9845         /* Clear timesync registers. */
9846         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9847         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9848         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9849         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9850         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9851         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9852
9853         /* Enable timestamping of PTP packets. */
9854         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9855         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9856
9857         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9858         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9859         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9860
9861         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9862         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9863
9864         return 0;
9865 }
9866
9867 static int
9868 i40e_timesync_disable(struct rte_eth_dev *dev)
9869 {
9870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9871         uint32_t tsync_ctl_l;
9872         uint32_t tsync_ctl_h;
9873
9874         /* Disable timestamping of transmitted PTP packets. */
9875         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9876         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9877
9878         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9879         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9880
9881         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9882         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9883
9884         /* Reset the timesync increment value. */
9885         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9886         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9887
9888         return 0;
9889 }
9890
9891 static int
9892 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9893                                 struct timespec *timestamp, uint32_t flags)
9894 {
9895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9896         struct i40e_adapter *adapter =
9897                 (struct i40e_adapter *)dev->data->dev_private;
9898
9899         uint32_t sync_status;
9900         uint32_t index = flags & 0x03;
9901         uint64_t rx_tstamp_cycles;
9902         uint64_t ns;
9903
9904         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9905         if ((sync_status & (1 << index)) == 0)
9906                 return -EINVAL;
9907
9908         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9909         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9910         *timestamp = rte_ns_to_timespec(ns);
9911
9912         return 0;
9913 }
9914
9915 static int
9916 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9917                                 struct timespec *timestamp)
9918 {
9919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9920         struct i40e_adapter *adapter =
9921                 (struct i40e_adapter *)dev->data->dev_private;
9922
9923         uint32_t sync_status;
9924         uint64_t tx_tstamp_cycles;
9925         uint64_t ns;
9926
9927         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9928         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9929                 return -EINVAL;
9930
9931         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9932         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9933         *timestamp = rte_ns_to_timespec(ns);
9934
9935         return 0;
9936 }
9937
9938 /*
9939  * i40e_parse_dcb_configure - parse dcb configure from user
9940  * @dev: the device being configured
9941  * @dcb_cfg: pointer of the result of parse
9942  * @*tc_map: bit map of enabled traffic classes
9943  *
9944  * Returns 0 on success, negative value on failure
9945  */
9946 static int
9947 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9948                          struct i40e_dcbx_config *dcb_cfg,
9949                          uint8_t *tc_map)
9950 {
9951         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9952         uint8_t i, tc_bw, bw_lf;
9953
9954         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9955
9956         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9957         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9958                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9959                 return -EINVAL;
9960         }
9961
9962         /* assume each tc has the same bw */
9963         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9964         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9965                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9966         /* to ensure the sum of tcbw is equal to 100 */
9967         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9968         for (i = 0; i < bw_lf; i++)
9969                 dcb_cfg->etscfg.tcbwtable[i]++;
9970
9971         /* assume each tc has the same Transmission Selection Algorithm */
9972         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9973                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9974
9975         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9976                 dcb_cfg->etscfg.prioritytable[i] =
9977                                 dcb_rx_conf->dcb_tc[i];
9978
9979         /* FW needs one App to configure HW */
9980         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9981         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9982         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9983         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9984
9985         if (dcb_rx_conf->nb_tcs == 0)
9986                 *tc_map = 1; /* tc0 only */
9987         else
9988                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9989
9990         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9991                 dcb_cfg->pfc.willing = 0;
9992                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9993                 dcb_cfg->pfc.pfcenable = *tc_map;
9994         }
9995         return 0;
9996 }
9997
9998
9999 static enum i40e_status_code
10000 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10001                               struct i40e_aqc_vsi_properties_data *info,
10002                               uint8_t enabled_tcmap)
10003 {
10004         enum i40e_status_code ret;
10005         int i, total_tc = 0;
10006         uint16_t qpnum_per_tc, bsf, qp_idx;
10007         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10008         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10009         uint16_t used_queues;
10010
10011         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10012         if (ret != I40E_SUCCESS)
10013                 return ret;
10014
10015         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10016                 if (enabled_tcmap & (1 << i))
10017                         total_tc++;
10018         }
10019         if (total_tc == 0)
10020                 total_tc = 1;
10021         vsi->enabled_tc = enabled_tcmap;
10022
10023         /* different VSI has different queues assigned */
10024         if (vsi->type == I40E_VSI_MAIN)
10025                 used_queues = dev_data->nb_rx_queues -
10026                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10027         else if (vsi->type == I40E_VSI_VMDQ2)
10028                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10029         else {
10030                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10031                 return I40E_ERR_NO_AVAILABLE_VSI;
10032         }
10033
10034         qpnum_per_tc = used_queues / total_tc;
10035         /* Number of queues per enabled TC */
10036         if (qpnum_per_tc == 0) {
10037                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10038                 return I40E_ERR_INVALID_QP_ID;
10039         }
10040         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10041                                 I40E_MAX_Q_PER_TC);
10042         bsf = rte_bsf32(qpnum_per_tc);
10043
10044         /**
10045          * Configure TC and queue mapping parameters, for enabled TC,
10046          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10047          * default queue will serve it.
10048          */
10049         qp_idx = 0;
10050         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10051                 if (vsi->enabled_tc & (1 << i)) {
10052                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10053                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10054                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10055                         qp_idx += qpnum_per_tc;
10056                 } else
10057                         info->tc_mapping[i] = 0;
10058         }
10059
10060         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10061         if (vsi->type == I40E_VSI_SRIOV) {
10062                 info->mapping_flags |=
10063                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10064                 for (i = 0; i < vsi->nb_qps; i++)
10065                         info->queue_mapping[i] =
10066                                 rte_cpu_to_le_16(vsi->base_queue + i);
10067         } else {
10068                 info->mapping_flags |=
10069                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10070                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10071         }
10072         info->valid_sections |=
10073                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10074
10075         return I40E_SUCCESS;
10076 }
10077
10078 /*
10079  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10080  * @veb: VEB to be configured
10081  * @tc_map: enabled TC bitmap
10082  *
10083  * Returns 0 on success, negative value on failure
10084  */
10085 static enum i40e_status_code
10086 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10087 {
10088         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10089         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10090         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10091         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10092         enum i40e_status_code ret = I40E_SUCCESS;
10093         int i;
10094         uint32_t bw_max;
10095
10096         /* Check if enabled_tc is same as existing or new TCs */
10097         if (veb->enabled_tc == tc_map)
10098                 return ret;
10099
10100         /* configure tc bandwidth */
10101         memset(&veb_bw, 0, sizeof(veb_bw));
10102         veb_bw.tc_valid_bits = tc_map;
10103         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10104         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10105                 if (tc_map & BIT_ULL(i))
10106                         veb_bw.tc_bw_share_credits[i] = 1;
10107         }
10108         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10109                                                    &veb_bw, NULL);
10110         if (ret) {
10111                 PMD_INIT_LOG(ERR,
10112                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10113                         hw->aq.asq_last_status);
10114                 return ret;
10115         }
10116
10117         memset(&ets_query, 0, sizeof(ets_query));
10118         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10119                                                    &ets_query, NULL);
10120         if (ret != I40E_SUCCESS) {
10121                 PMD_DRV_LOG(ERR,
10122                         "Failed to get switch_comp ETS configuration %u",
10123                         hw->aq.asq_last_status);
10124                 return ret;
10125         }
10126         memset(&bw_query, 0, sizeof(bw_query));
10127         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10128                                                   &bw_query, NULL);
10129         if (ret != I40E_SUCCESS) {
10130                 PMD_DRV_LOG(ERR,
10131                         "Failed to get switch_comp bandwidth configuration %u",
10132                         hw->aq.asq_last_status);
10133                 return ret;
10134         }
10135
10136         /* store and print out BW info */
10137         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10138         veb->bw_info.bw_max = ets_query.tc_bw_max;
10139         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10140         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10141         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10142                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10143                      I40E_16_BIT_WIDTH);
10144         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10145                 veb->bw_info.bw_ets_share_credits[i] =
10146                                 bw_query.tc_bw_share_credits[i];
10147                 veb->bw_info.bw_ets_credits[i] =
10148                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10149                 /* 4 bits per TC, 4th bit is reserved */
10150                 veb->bw_info.bw_ets_max[i] =
10151                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10152                                   RTE_LEN2MASK(3, uint8_t));
10153                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10154                             veb->bw_info.bw_ets_share_credits[i]);
10155                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10156                             veb->bw_info.bw_ets_credits[i]);
10157                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10158                             veb->bw_info.bw_ets_max[i]);
10159         }
10160
10161         veb->enabled_tc = tc_map;
10162
10163         return ret;
10164 }
10165
10166
10167 /*
10168  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10169  * @vsi: VSI to be configured
10170  * @tc_map: enabled TC bitmap
10171  *
10172  * Returns 0 on success, negative value on failure
10173  */
10174 static enum i40e_status_code
10175 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10176 {
10177         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10178         struct i40e_vsi_context ctxt;
10179         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10180         enum i40e_status_code ret = I40E_SUCCESS;
10181         int i;
10182
10183         /* Check if enabled_tc is same as existing or new TCs */
10184         if (vsi->enabled_tc == tc_map)
10185                 return ret;
10186
10187         /* configure tc bandwidth */
10188         memset(&bw_data, 0, sizeof(bw_data));
10189         bw_data.tc_valid_bits = tc_map;
10190         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10191         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10192                 if (tc_map & BIT_ULL(i))
10193                         bw_data.tc_bw_credits[i] = 1;
10194         }
10195         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10196         if (ret) {
10197                 PMD_INIT_LOG(ERR,
10198                         "AQ command Config VSI BW allocation per TC failed = %d",
10199                         hw->aq.asq_last_status);
10200                 goto out;
10201         }
10202         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10203                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10204
10205         /* Update Queue Pairs Mapping for currently enabled UPs */
10206         ctxt.seid = vsi->seid;
10207         ctxt.pf_num = hw->pf_id;
10208         ctxt.vf_num = 0;
10209         ctxt.uplink_seid = vsi->uplink_seid;
10210         ctxt.info = vsi->info;
10211         i40e_get_cap(hw);
10212         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10213         if (ret)
10214                 goto out;
10215
10216         /* Update the VSI after updating the VSI queue-mapping information */
10217         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10218         if (ret) {
10219                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10220                         hw->aq.asq_last_status);
10221                 goto out;
10222         }
10223         /* update the local VSI info with updated queue map */
10224         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10225                                         sizeof(vsi->info.tc_mapping));
10226         (void)rte_memcpy(&vsi->info.queue_mapping,
10227                         &ctxt.info.queue_mapping,
10228                 sizeof(vsi->info.queue_mapping));
10229         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10230         vsi->info.valid_sections = 0;
10231
10232         /* query and update current VSI BW information */
10233         ret = i40e_vsi_get_bw_config(vsi);
10234         if (ret) {
10235                 PMD_INIT_LOG(ERR,
10236                          "Failed updating vsi bw info, err %s aq_err %s",
10237                          i40e_stat_str(hw, ret),
10238                          i40e_aq_str(hw, hw->aq.asq_last_status));
10239                 goto out;
10240         }
10241
10242         vsi->enabled_tc = tc_map;
10243
10244 out:
10245         return ret;
10246 }
10247
10248 /*
10249  * i40e_dcb_hw_configure - program the dcb setting to hw
10250  * @pf: pf the configuration is taken on
10251  * @new_cfg: new configuration
10252  * @tc_map: enabled TC bitmap
10253  *
10254  * Returns 0 on success, negative value on failure
10255  */
10256 static enum i40e_status_code
10257 i40e_dcb_hw_configure(struct i40e_pf *pf,
10258                       struct i40e_dcbx_config *new_cfg,
10259                       uint8_t tc_map)
10260 {
10261         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10262         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10263         struct i40e_vsi *main_vsi = pf->main_vsi;
10264         struct i40e_vsi_list *vsi_list;
10265         enum i40e_status_code ret;
10266         int i;
10267         uint32_t val;
10268
10269         /* Use the FW API if FW > v4.4*/
10270         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10271               (hw->aq.fw_maj_ver >= 5))) {
10272                 PMD_INIT_LOG(ERR,
10273                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10274                 return I40E_ERR_FIRMWARE_API_VERSION;
10275         }
10276
10277         /* Check if need reconfiguration */
10278         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10279                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10280                 return I40E_SUCCESS;
10281         }
10282
10283         /* Copy the new config to the current config */
10284         *old_cfg = *new_cfg;
10285         old_cfg->etsrec = old_cfg->etscfg;
10286         ret = i40e_set_dcb_config(hw);
10287         if (ret) {
10288                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10289                          i40e_stat_str(hw, ret),
10290                          i40e_aq_str(hw, hw->aq.asq_last_status));
10291                 return ret;
10292         }
10293         /* set receive Arbiter to RR mode and ETS scheme by default */
10294         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10295                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10296                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10297                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10298                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10299                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10300                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10301                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10302                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10303                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10304                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10305                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10306                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10307         }
10308         /* get local mib to check whether it is configured correctly */
10309         /* IEEE mode */
10310         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10311         /* Get Local DCB Config */
10312         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10313                                      &hw->local_dcbx_config);
10314
10315         /* if Veb is created, need to update TC of it at first */
10316         if (main_vsi->veb) {
10317                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10318                 if (ret)
10319                         PMD_INIT_LOG(WARNING,
10320                                  "Failed configuring TC for VEB seid=%d",
10321                                  main_vsi->veb->seid);
10322         }
10323         /* Update each VSI */
10324         i40e_vsi_config_tc(main_vsi, tc_map);
10325         if (main_vsi->veb) {
10326                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10327                         /* Beside main VSI and VMDQ VSIs, only enable default
10328                          * TC for other VSIs
10329                          */
10330                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10331                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10332                                                          tc_map);
10333                         else
10334                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10335                                                          I40E_DEFAULT_TCMAP);
10336                         if (ret)
10337                                 PMD_INIT_LOG(WARNING,
10338                                         "Failed configuring TC for VSI seid=%d",
10339                                         vsi_list->vsi->seid);
10340                         /* continue */
10341                 }
10342         }
10343         return I40E_SUCCESS;
10344 }
10345
10346 /*
10347  * i40e_dcb_init_configure - initial dcb config
10348  * @dev: device being configured
10349  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10350  *
10351  * Returns 0 on success, negative value on failure
10352  */
10353 static int
10354 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10355 {
10356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10358         int i, ret = 0;
10359
10360         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10361                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10362                 return -ENOTSUP;
10363         }
10364
10365         /* DCB initialization:
10366          * Update DCB configuration from the Firmware and configure
10367          * LLDP MIB change event.
10368          */
10369         if (sw_dcb == TRUE) {
10370                 ret = i40e_init_dcb(hw);
10371                 /* If lldp agent is stopped, the return value from
10372                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10373                  * adminq status. Otherwise, it should return success.
10374                  */
10375                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10376                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10377                         memset(&hw->local_dcbx_config, 0,
10378                                 sizeof(struct i40e_dcbx_config));
10379                         /* set dcb default configuration */
10380                         hw->local_dcbx_config.etscfg.willing = 0;
10381                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10382                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10383                         hw->local_dcbx_config.etscfg.tsatable[0] =
10384                                                 I40E_IEEE_TSA_ETS;
10385                         /* all UPs mapping to TC0 */
10386                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10387                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10388                         hw->local_dcbx_config.etsrec =
10389                                 hw->local_dcbx_config.etscfg;
10390                         hw->local_dcbx_config.pfc.willing = 0;
10391                         hw->local_dcbx_config.pfc.pfccap =
10392                                                 I40E_MAX_TRAFFIC_CLASS;
10393                         /* FW needs one App to configure HW */
10394                         hw->local_dcbx_config.numapps = 1;
10395                         hw->local_dcbx_config.app[0].selector =
10396                                                 I40E_APP_SEL_ETHTYPE;
10397                         hw->local_dcbx_config.app[0].priority = 3;
10398                         hw->local_dcbx_config.app[0].protocolid =
10399                                                 I40E_APP_PROTOID_FCOE;
10400                         ret = i40e_set_dcb_config(hw);
10401                         if (ret) {
10402                                 PMD_INIT_LOG(ERR,
10403                                         "default dcb config fails. err = %d, aq_err = %d.",
10404                                         ret, hw->aq.asq_last_status);
10405                                 return -ENOSYS;
10406                         }
10407                 } else {
10408                         PMD_INIT_LOG(ERR,
10409                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10410                                 ret, hw->aq.asq_last_status);
10411                         return -ENOTSUP;
10412                 }
10413         } else {
10414                 ret = i40e_aq_start_lldp(hw, NULL);
10415                 if (ret != I40E_SUCCESS)
10416                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10417
10418                 ret = i40e_init_dcb(hw);
10419                 if (!ret) {
10420                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10421                                 PMD_INIT_LOG(ERR,
10422                                         "HW doesn't support DCBX offload.");
10423                                 return -ENOTSUP;
10424                         }
10425                 } else {
10426                         PMD_INIT_LOG(ERR,
10427                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10428                                 ret, hw->aq.asq_last_status);
10429                         return -ENOTSUP;
10430                 }
10431         }
10432         return 0;
10433 }
10434
10435 /*
10436  * i40e_dcb_setup - setup dcb related config
10437  * @dev: device being configured
10438  *
10439  * Returns 0 on success, negative value on failure
10440  */
10441 static int
10442 i40e_dcb_setup(struct rte_eth_dev *dev)
10443 {
10444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10445         struct i40e_dcbx_config dcb_cfg;
10446         uint8_t tc_map = 0;
10447         int ret = 0;
10448
10449         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10450                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10451                 return -ENOTSUP;
10452         }
10453
10454         if (pf->vf_num != 0)
10455                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10456
10457         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10458         if (ret) {
10459                 PMD_INIT_LOG(ERR, "invalid dcb config");
10460                 return -EINVAL;
10461         }
10462         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10463         if (ret) {
10464                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10465                 return -ENOSYS;
10466         }
10467
10468         return 0;
10469 }
10470
10471 static int
10472 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10473                       struct rte_eth_dcb_info *dcb_info)
10474 {
10475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10477         struct i40e_vsi *vsi = pf->main_vsi;
10478         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10479         uint16_t bsf, tc_mapping;
10480         int i, j = 0;
10481
10482         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10483                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10484         else
10485                 dcb_info->nb_tcs = 1;
10486         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10487                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10488         for (i = 0; i < dcb_info->nb_tcs; i++)
10489                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10490
10491         /* get queue mapping if vmdq is disabled */
10492         if (!pf->nb_cfg_vmdq_vsi) {
10493                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10494                         if (!(vsi->enabled_tc & (1 << i)))
10495                                 continue;
10496                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10497                         dcb_info->tc_queue.tc_rxq[j][i].base =
10498                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10499                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10500                         dcb_info->tc_queue.tc_txq[j][i].base =
10501                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10502                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10503                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10504                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10505                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10506                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10507                 }
10508                 return 0;
10509         }
10510
10511         /* get queue mapping if vmdq is enabled */
10512         do {
10513                 vsi = pf->vmdq[j].vsi;
10514                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10515                         if (!(vsi->enabled_tc & (1 << i)))
10516                                 continue;
10517                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10518                         dcb_info->tc_queue.tc_rxq[j][i].base =
10519                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10520                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10521                         dcb_info->tc_queue.tc_txq[j][i].base =
10522                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10523                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10524                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10525                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10526                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10527                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10528                 }
10529                 j++;
10530         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10531         return 0;
10532 }
10533
10534 static int
10535 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10536 {
10537         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10540         uint16_t interval =
10541                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10542         uint16_t msix_intr;
10543
10544         msix_intr = intr_handle->intr_vec[queue_id];
10545         if (msix_intr == I40E_MISC_VEC_ID)
10546                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10547                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10548                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10549                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10550                                (interval <<
10551                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10552         else
10553                 I40E_WRITE_REG(hw,
10554                                I40E_PFINT_DYN_CTLN(msix_intr -
10555                                                    I40E_RX_VEC_START),
10556                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10557                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10558                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10559                                (interval <<
10560                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10561
10562         I40E_WRITE_FLUSH(hw);
10563         rte_intr_enable(&pci_dev->intr_handle);
10564
10565         return 0;
10566 }
10567
10568 static int
10569 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10570 {
10571         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10572         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10573         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10574         uint16_t msix_intr;
10575
10576         msix_intr = intr_handle->intr_vec[queue_id];
10577         if (msix_intr == I40E_MISC_VEC_ID)
10578                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10579         else
10580                 I40E_WRITE_REG(hw,
10581                                I40E_PFINT_DYN_CTLN(msix_intr -
10582                                                    I40E_RX_VEC_START),
10583                                0);
10584         I40E_WRITE_FLUSH(hw);
10585
10586         return 0;
10587 }
10588
10589 static int i40e_get_regs(struct rte_eth_dev *dev,
10590                          struct rte_dev_reg_info *regs)
10591 {
10592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10593         uint32_t *ptr_data = regs->data;
10594         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10595         const struct i40e_reg_info *reg_info;
10596
10597         if (ptr_data == NULL) {
10598                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10599                 regs->width = sizeof(uint32_t);
10600                 return 0;
10601         }
10602
10603         /* The first few registers have to be read using AQ operations */
10604         reg_idx = 0;
10605         while (i40e_regs_adminq[reg_idx].name) {
10606                 reg_info = &i40e_regs_adminq[reg_idx++];
10607                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10608                         for (arr_idx2 = 0;
10609                                         arr_idx2 <= reg_info->count2;
10610                                         arr_idx2++) {
10611                                 reg_offset = arr_idx * reg_info->stride1 +
10612                                         arr_idx2 * reg_info->stride2;
10613                                 reg_offset += reg_info->base_addr;
10614                                 ptr_data[reg_offset >> 2] =
10615                                         i40e_read_rx_ctl(hw, reg_offset);
10616                         }
10617         }
10618
10619         /* The remaining registers can be read using primitives */
10620         reg_idx = 0;
10621         while (i40e_regs_others[reg_idx].name) {
10622                 reg_info = &i40e_regs_others[reg_idx++];
10623                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10624                         for (arr_idx2 = 0;
10625                                         arr_idx2 <= reg_info->count2;
10626                                         arr_idx2++) {
10627                                 reg_offset = arr_idx * reg_info->stride1 +
10628                                         arr_idx2 * reg_info->stride2;
10629                                 reg_offset += reg_info->base_addr;
10630                                 ptr_data[reg_offset >> 2] =
10631                                         I40E_READ_REG(hw, reg_offset);
10632                         }
10633         }
10634
10635         return 0;
10636 }
10637
10638 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10639 {
10640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10641
10642         /* Convert word count to byte count */
10643         return hw->nvm.sr_size << 1;
10644 }
10645
10646 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10647                            struct rte_dev_eeprom_info *eeprom)
10648 {
10649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10650         uint16_t *data = eeprom->data;
10651         uint16_t offset, length, cnt_words;
10652         int ret_code;
10653
10654         offset = eeprom->offset >> 1;
10655         length = eeprom->length >> 1;
10656         cnt_words = length;
10657
10658         if (offset > hw->nvm.sr_size ||
10659                 offset + length > hw->nvm.sr_size) {
10660                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10661                 return -EINVAL;
10662         }
10663
10664         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10665
10666         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10667         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10668                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10669                 return -EIO;
10670         }
10671
10672         return 0;
10673 }
10674
10675 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10676                                       struct ether_addr *mac_addr)
10677 {
10678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10679
10680         if (!is_valid_assigned_ether_addr(mac_addr)) {
10681                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10682                 return;
10683         }
10684
10685         /* Flags: 0x3 updates port address */
10686         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10687 }
10688
10689 static int
10690 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10691 {
10692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10693         struct rte_eth_dev_data *dev_data = pf->dev_data;
10694         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10695         int ret = 0;
10696
10697         /* check if mtu is within the allowed range */
10698         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10699                 return -EINVAL;
10700
10701         /* mtu setting is forbidden if port is start */
10702         if (dev_data->dev_started) {
10703                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10704                             dev_data->port_id);
10705                 return -EBUSY;
10706         }
10707
10708         if (frame_size > ETHER_MAX_LEN)
10709                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10710         else
10711                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10712
10713         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10714
10715         return ret;
10716 }
10717
10718 /* Restore ethertype filter */
10719 static void
10720 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10721 {
10722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10723         struct i40e_ethertype_filter_list
10724                 *ethertype_list = &pf->ethertype.ethertype_list;
10725         struct i40e_ethertype_filter *f;
10726         struct i40e_control_filter_stats stats;
10727         uint16_t flags;
10728
10729         TAILQ_FOREACH(f, ethertype_list, rules) {
10730                 flags = 0;
10731                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10732                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10733                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10734                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10735                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10736
10737                 memset(&stats, 0, sizeof(stats));
10738                 i40e_aq_add_rem_control_packet_filter(hw,
10739                                             f->input.mac_addr.addr_bytes,
10740                                             f->input.ether_type,
10741                                             flags, pf->main_vsi->seid,
10742                                             f->queue, 1, &stats, NULL);
10743         }
10744         PMD_DRV_LOG(INFO, "Ethertype filter:"
10745                     " mac_etype_used = %u, etype_used = %u,"
10746                     " mac_etype_free = %u, etype_free = %u",
10747                     stats.mac_etype_used, stats.etype_used,
10748                     stats.mac_etype_free, stats.etype_free);
10749 }
10750
10751 /* Restore tunnel filter */
10752 static void
10753 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10754 {
10755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10756         struct i40e_vsi *vsi;
10757         struct i40e_pf_vf *vf;
10758         struct i40e_tunnel_filter_list
10759                 *tunnel_list = &pf->tunnel.tunnel_list;
10760         struct i40e_tunnel_filter *f;
10761         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10762         bool big_buffer = 0;
10763
10764         TAILQ_FOREACH(f, tunnel_list, rules) {
10765                 if (!f->is_to_vf)
10766                         vsi = pf->main_vsi;
10767                 else {
10768                         vf = &pf->vfs[f->vf_id];
10769                         vsi = vf->vsi;
10770                 }
10771                 memset(&cld_filter, 0, sizeof(cld_filter));
10772                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10773                         (struct ether_addr *)&cld_filter.element.outer_mac);
10774                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10775                         (struct ether_addr *)&cld_filter.element.inner_mac);
10776                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10777                 cld_filter.element.flags = f->input.flags;
10778                 cld_filter.element.tenant_id = f->input.tenant_id;
10779                 cld_filter.element.queue_number = f->queue;
10780                 rte_memcpy(cld_filter.general_fields,
10781                            f->input.general_fields,
10782                            sizeof(f->input.general_fields));
10783
10784                 if (((f->input.flags &
10785                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10786                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10787                     ((f->input.flags &
10788                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10789                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10790                     ((f->input.flags &
10791                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10792                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10793                         big_buffer = 1;
10794
10795                 if (big_buffer)
10796                         i40e_aq_add_cloud_filters_big_buffer(hw,
10797                                              vsi->seid, &cld_filter, 1);
10798                 else
10799                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10800                                                   &cld_filter.element, 1);
10801         }
10802 }
10803
10804 static void
10805 i40e_filter_restore(struct i40e_pf *pf)
10806 {
10807         i40e_ethertype_filter_restore(pf);
10808         i40e_tunnel_filter_restore(pf);
10809         i40e_fdir_filter_restore(pf);
10810 }
10811
10812 static bool
10813 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10814 {
10815         if (strcmp(dev->device->driver->name, drv->driver.name))
10816                 return false;
10817
10818         return true;
10819 }
10820
10821 bool
10822 is_i40e_supported(struct rte_eth_dev *dev)
10823 {
10824         return is_device_supported(dev, &rte_i40e_pmd);
10825 }
10826
10827 /* Create a QinQ cloud filter
10828  *
10829  * The Fortville NIC has limited resources for tunnel filters,
10830  * so we can only reuse existing filters.
10831  *
10832  * In step 1 we define which Field Vector fields can be used for
10833  * filter types.
10834  * As we do not have the inner tag defined as a field,
10835  * we have to define it first, by reusing one of L1 entries.
10836  *
10837  * In step 2 we are replacing one of existing filter types with
10838  * a new one for QinQ.
10839  * As we reusing L1 and replacing L2, some of the default filter
10840  * types will disappear,which depends on L1 and L2 entries we reuse.
10841  *
10842  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10843  *
10844  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10845  *              later when we define the cloud filter.
10846  *      a.      Valid_flags.replace_cloud = 0
10847  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10848  *      c.      New_filter = 0x10
10849  *      d.      TR bit = 0xff (optional, not used here)
10850  *      e.      Buffer – 2 entries:
10851  *              i.      Byte 0 = 8 (outer vlan FV index).
10852  *                      Byte 1 = 0 (rsv)
10853  *                      Byte 2-3 = 0x0fff
10854  *              ii.     Byte 0 = 37 (inner vlan FV index).
10855  *                      Byte 1 =0 (rsv)
10856  *                      Byte 2-3 = 0x0fff
10857  *
10858  * Step 2:
10859  * 2.   Create cloud filter using two L1 filters entries: stag and
10860  *              new filter(outer vlan+ inner vlan)
10861  *      a.      Valid_flags.replace_cloud = 1
10862  *      b.      Old_filter = 1 (instead of outer IP)
10863  *      c.      New_filter = 0x10
10864  *      d.      Buffer – 2 entries:
10865  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10866  *                      Byte 1-3 = 0 (rsv)
10867  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10868  *                      Byte 9-11 = 0 (rsv)
10869  */
10870 static int
10871 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10872 {
10873         int ret = -ENOTSUP;
10874         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10875         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10876         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10877
10878         /* Init */
10879         memset(&filter_replace, 0,
10880                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10881         memset(&filter_replace_buf, 0,
10882                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10883
10884         /* create L1 filter */
10885         filter_replace.old_filter_type =
10886                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10887         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10888         filter_replace.tr_bit = 0;
10889
10890         /* Prepare the buffer, 2 entries */
10891         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10892         filter_replace_buf.data[0] |=
10893                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10894         /* Field Vector 12b mask */
10895         filter_replace_buf.data[2] = 0xff;
10896         filter_replace_buf.data[3] = 0x0f;
10897         filter_replace_buf.data[4] =
10898                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10899         filter_replace_buf.data[4] |=
10900                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10901         /* Field Vector 12b mask */
10902         filter_replace_buf.data[6] = 0xff;
10903         filter_replace_buf.data[7] = 0x0f;
10904         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10905                         &filter_replace_buf);
10906         if (ret != I40E_SUCCESS)
10907                 return ret;
10908
10909         /* Apply the second L2 cloud filter */
10910         memset(&filter_replace, 0,
10911                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10912         memset(&filter_replace_buf, 0,
10913                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10914
10915         /* create L2 filter, input for L2 filter will be L1 filter  */
10916         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10917         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10918         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10919
10920         /* Prepare the buffer, 2 entries */
10921         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10922         filter_replace_buf.data[0] |=
10923                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10924         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10925         filter_replace_buf.data[4] |=
10926                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10927         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10928                         &filter_replace_buf);
10929         return ret;
10930 }
10931
10932 RTE_INIT(i40e_init_log);
10933 static void
10934 i40e_init_log(void)
10935 {
10936         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10937         if (i40e_logtype_init >= 0)
10938                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10939         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10940         if (i40e_logtype_driver >= 0)
10941                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10942 }