4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds */
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
110 static int i40e_dev_configure(struct rte_eth_dev *dev);
111 static int i40e_dev_start(struct rte_eth_dev *dev);
112 static void i40e_dev_stop(struct rte_eth_dev *dev);
113 static void i40e_dev_close(struct rte_eth_dev *dev);
114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
121 struct rte_eth_stats *stats);
122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
128 struct rte_eth_dev_info *dev_info);
129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
141 struct rte_eth_fc_conf *fc_conf);
142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
143 struct rte_eth_pfc_conf *pfc_conf);
144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
145 struct ether_addr *mac_addr,
148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_reta_entry64 *reta_conf,
152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
153 struct rte_eth_rss_reta_entry64 *reta_conf,
156 static int i40e_get_cap(struct i40e_hw *hw);
157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
158 static int i40e_pf_setup(struct i40e_pf *pf);
159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
162 bool offset_loaded, uint64_t *offset, uint64_t *stat);
163 static void i40e_stat_update_48(struct i40e_hw *hw,
169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
170 static void i40e_dev_interrupt_handler(
171 __rte_unused struct rte_intr_handle *handle, void *param);
172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
173 uint32_t base, uint32_t num);
174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
180 static int i40e_veb_release(struct i40e_veb *veb);
181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
182 struct i40e_vsi *vsi);
183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
186 struct i40e_macvlan_filter *mv_f,
188 struct ether_addr *addr);
189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
190 struct i40e_macvlan_filter *mv_f,
193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
195 struct rte_eth_rss_conf *rss_conf);
196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
197 struct rte_eth_rss_conf *rss_conf);
198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
199 struct rte_eth_udp_tunnel *udp_tunnel);
200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
201 struct rte_eth_udp_tunnel *udp_tunnel);
202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
203 struct rte_eth_ethertype_filter *filter,
205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
206 enum rte_filter_op filter_op,
208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
209 enum rte_filter_type filter_type,
210 enum rte_filter_op filter_op,
212 static void i40e_configure_registers(struct i40e_hw *hw);
213 static void i40e_hw_init(struct i40e_hw *hw);
214 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
215 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
216 struct rte_eth_mirror_conf *mirror_conf,
217 uint8_t sw_id, uint8_t on);
218 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
220 static const struct rte_pci_id pci_id_i40e_map[] = {
221 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
222 #include "rte_pci_dev_ids.h"
223 { .vendor_id = 0, /* sentinel */ },
226 static const struct eth_dev_ops i40e_eth_dev_ops = {
227 .dev_configure = i40e_dev_configure,
228 .dev_start = i40e_dev_start,
229 .dev_stop = i40e_dev_stop,
230 .dev_close = i40e_dev_close,
231 .promiscuous_enable = i40e_dev_promiscuous_enable,
232 .promiscuous_disable = i40e_dev_promiscuous_disable,
233 .allmulticast_enable = i40e_dev_allmulticast_enable,
234 .allmulticast_disable = i40e_dev_allmulticast_disable,
235 .dev_set_link_up = i40e_dev_set_link_up,
236 .dev_set_link_down = i40e_dev_set_link_down,
237 .link_update = i40e_dev_link_update,
238 .stats_get = i40e_dev_stats_get,
239 .stats_reset = i40e_dev_stats_reset,
240 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
241 .dev_infos_get = i40e_dev_info_get,
242 .vlan_filter_set = i40e_vlan_filter_set,
243 .vlan_tpid_set = i40e_vlan_tpid_set,
244 .vlan_offload_set = i40e_vlan_offload_set,
245 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
246 .vlan_pvid_set = i40e_vlan_pvid_set,
247 .rx_queue_start = i40e_dev_rx_queue_start,
248 .rx_queue_stop = i40e_dev_rx_queue_stop,
249 .tx_queue_start = i40e_dev_tx_queue_start,
250 .tx_queue_stop = i40e_dev_tx_queue_stop,
251 .rx_queue_setup = i40e_dev_rx_queue_setup,
252 .rx_queue_release = i40e_dev_rx_queue_release,
253 .rx_queue_count = i40e_dev_rx_queue_count,
254 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
255 .tx_queue_setup = i40e_dev_tx_queue_setup,
256 .tx_queue_release = i40e_dev_tx_queue_release,
257 .dev_led_on = i40e_dev_led_on,
258 .dev_led_off = i40e_dev_led_off,
259 .flow_ctrl_set = i40e_flow_ctrl_set,
260 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
261 .mac_addr_add = i40e_macaddr_add,
262 .mac_addr_remove = i40e_macaddr_remove,
263 .reta_update = i40e_dev_rss_reta_update,
264 .reta_query = i40e_dev_rss_reta_query,
265 .rss_hash_update = i40e_dev_rss_hash_update,
266 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
267 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
268 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
269 .filter_ctrl = i40e_dev_filter_ctrl,
270 .mirror_rule_set = i40e_mirror_rule_set,
271 .mirror_rule_reset = i40e_mirror_rule_reset,
274 static struct eth_driver rte_i40e_pmd = {
276 .name = "rte_i40e_pmd",
277 .id_table = pci_id_i40e_map,
278 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
280 .eth_dev_init = eth_i40e_dev_init,
281 .dev_private_size = sizeof(struct i40e_adapter),
285 i40e_align_floor(int n)
289 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
293 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
294 struct rte_eth_link *link)
296 struct rte_eth_link *dst = link;
297 struct rte_eth_link *src = &(dev->data->dev_link);
299 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
300 *(uint64_t *)src) == 0)
307 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
308 struct rte_eth_link *link)
310 struct rte_eth_link *dst = &(dev->data->dev_link);
311 struct rte_eth_link *src = link;
313 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
314 *(uint64_t *)src) == 0)
321 * Driver initialization routine.
322 * Invoked once at EAL init time.
323 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
326 rte_i40e_pmd_init(const char *name __rte_unused,
327 const char *params __rte_unused)
329 PMD_INIT_FUNC_TRACE();
330 rte_eth_driver_register(&rte_i40e_pmd);
335 static struct rte_driver rte_i40e_driver = {
337 .init = rte_i40e_pmd_init,
340 PMD_REGISTER_DRIVER(rte_i40e_driver);
343 * Initialize registers for flexible payload, which should be set by NVM.
344 * This should be removed from code once it is fixed in NVM.
346 #ifndef I40E_GLQF_ORT
347 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
349 #ifndef I40E_GLQF_PIT
350 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
353 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
355 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
356 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
357 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
358 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
359 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
360 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
361 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
362 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
363 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
364 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
366 /* GLQF_PIT Registers */
367 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
368 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
372 eth_i40e_dev_init(struct rte_eth_dev *dev)
374 struct rte_pci_device *pci_dev;
375 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
376 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
377 struct i40e_vsi *vsi;
382 PMD_INIT_FUNC_TRACE();
384 dev->dev_ops = &i40e_eth_dev_ops;
385 dev->rx_pkt_burst = i40e_recv_pkts;
386 dev->tx_pkt_burst = i40e_xmit_pkts;
388 /* for secondary processes, we don't initialise any further as primary
389 * has already done this work. Only check we don't need a different
391 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
392 if (dev->data->scattered_rx)
393 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
396 pci_dev = dev->pci_dev;
397 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
398 pf->adapter->eth_dev = dev;
399 pf->dev_data = dev->data;
401 hw->back = I40E_PF_TO_ADAPTER(pf);
402 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
404 PMD_INIT_LOG(ERR, "Hardware is not available, "
405 "as address is NULL");
409 hw->vendor_id = pci_dev->id.vendor_id;
410 hw->device_id = pci_dev->id.device_id;
411 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
412 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
413 hw->bus.device = pci_dev->addr.devid;
414 hw->bus.func = pci_dev->addr.function;
416 /* Make sure all is clean before doing PF reset */
419 /* Initialize the hardware */
422 /* Reset here to make sure all is clean for each PF */
423 ret = i40e_pf_reset(hw);
425 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
429 /* Initialize the shared code (base driver) */
430 ret = i40e_init_shared_code(hw);
432 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
437 * To work around the NVM issue,initialize registers
438 * for flexible payload by software.
439 * It should be removed once issues are fixed in NVM.
441 i40e_flex_payload_reg_init(hw);
443 /* Initialize the parameters for adminq */
444 i40e_init_adminq_parameter(hw);
445 ret = i40e_init_adminq(hw);
446 if (ret != I40E_SUCCESS) {
447 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
450 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
451 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
452 hw->aq.api_maj_ver, hw->aq.api_min_ver,
453 ((hw->nvm.version >> 12) & 0xf),
454 ((hw->nvm.version >> 4) & 0xff),
455 (hw->nvm.version & 0xf), hw->nvm.eetrack);
458 ret = i40e_aq_stop_lldp(hw, true, NULL);
459 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
460 PMD_INIT_LOG(INFO, "Failed to stop lldp");
463 i40e_clear_pxe_mode(hw);
466 * On X710, performance number is far from the expectation on recent
467 * firmware versions. The fix for this issue may not be integrated in
468 * the following firmware version. So the workaround in software driver
469 * is needed. It needs to modify the initial values of 3 internal only
470 * registers. Note that the workaround can be removed when it is fixed
471 * in firmware in the future.
473 i40e_configure_registers(hw);
475 /* Get hw capabilities */
476 ret = i40e_get_cap(hw);
477 if (ret != I40E_SUCCESS) {
478 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
479 goto err_get_capabilities;
482 /* Initialize parameters for PF */
483 ret = i40e_pf_parameter_init(dev);
485 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
486 goto err_parameter_init;
489 /* Initialize the queue management */
490 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
492 PMD_INIT_LOG(ERR, "Failed to init queue pool");
493 goto err_qp_pool_init;
495 ret = i40e_res_pool_init(&pf->msix_pool, 1,
496 hw->func_caps.num_msix_vectors - 1);
498 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
499 goto err_msix_pool_init;
502 /* Initialize lan hmc */
503 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
504 hw->func_caps.num_rx_qp, 0, 0);
505 if (ret != I40E_SUCCESS) {
506 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
507 goto err_init_lan_hmc;
510 /* Configure lan hmc */
511 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
512 if (ret != I40E_SUCCESS) {
513 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
514 goto err_configure_lan_hmc;
517 /* Get and check the mac address */
518 i40e_get_mac_addr(hw, hw->mac.addr);
519 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
520 PMD_INIT_LOG(ERR, "mac address is not valid");
522 goto err_get_mac_addr;
524 /* Copy the permanent MAC address */
525 ether_addr_copy((struct ether_addr *) hw->mac.addr,
526 (struct ether_addr *) hw->mac.perm_addr);
528 /* Disable flow control */
529 hw->fc.requested_mode = I40E_FC_NONE;
530 i40e_set_fc(hw, &aq_fail, TRUE);
532 /* PF setup, which includes VSI setup */
533 ret = i40e_pf_setup(pf);
535 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
536 goto err_setup_pf_switch;
541 /* Disable double vlan by default */
542 i40e_vsi_config_double_vlan(vsi, FALSE);
544 if (!vsi->max_macaddrs)
545 len = ETHER_ADDR_LEN;
547 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
549 /* Should be after VSI initialized */
550 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
551 if (!dev->data->mac_addrs) {
552 PMD_INIT_LOG(ERR, "Failed to allocated memory "
553 "for storing mac address");
556 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
557 &dev->data->mac_addrs[0]);
559 /* initialize pf host driver to setup SRIOV resource if applicable */
560 i40e_pf_host_init(dev);
562 /* register callback func to eal lib */
563 rte_intr_callback_register(&(pci_dev->intr_handle),
564 i40e_dev_interrupt_handler, (void *)dev);
566 /* configure and enable device interrupt */
567 i40e_pf_config_irq0(hw);
568 i40e_pf_enable_irq0(hw);
570 /* enable uio intr after callback register */
571 rte_intr_enable(&(pci_dev->intr_handle));
573 /* initialize mirror rule list */
574 TAILQ_INIT(&pf->mirror_list);
579 i40e_vsi_release(pf->main_vsi);
582 err_configure_lan_hmc:
583 (void)i40e_shutdown_lan_hmc(hw);
585 i40e_res_pool_destroy(&pf->msix_pool);
587 i40e_res_pool_destroy(&pf->qp_pool);
590 err_get_capabilities:
591 (void)i40e_shutdown_adminq(hw);
597 i40e_dev_configure(struct rte_eth_dev *dev)
599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
600 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
603 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
604 ret = i40e_fdir_setup(pf);
605 if (ret != I40E_SUCCESS) {
606 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
609 ret = i40e_fdir_configure(dev);
611 PMD_DRV_LOG(ERR, "failed to configure fdir.");
615 i40e_fdir_teardown(pf);
617 ret = i40e_dev_init_vlan(dev);
622 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
623 * RSS setting have different requirements.
624 * General PMD driver call sequence are NIC init, configure,
625 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
626 * will try to lookup the VSI that specific queue belongs to if VMDQ
627 * applicable. So, VMDQ setting has to be done before
628 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
629 * For RSS setting, it will try to calculate actual configured RX queue
630 * number, which will be available after rx_queue_setup(). dev_start()
631 * function is good to place RSS setup.
633 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
634 ret = i40e_vmdq_setup(dev);
640 i40e_fdir_teardown(pf);
645 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
647 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
648 uint16_t msix_vect = vsi->msix_intr;
651 for (i = 0; i < vsi->nb_qps; i++) {
652 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
653 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
657 if (vsi->type != I40E_VSI_SRIOV) {
658 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
659 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
663 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
664 vsi->user_param + (msix_vect - 1);
666 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
668 I40E_WRITE_FLUSH(hw);
671 static inline uint16_t
672 i40e_calc_itr_interval(int16_t interval)
674 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
675 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
677 /* Convert to hardware count, as writing each 1 represents 2 us */
682 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
685 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
686 uint16_t msix_vect = vsi->msix_intr;
689 for (i = 0; i < vsi->nb_qps; i++)
690 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
692 /* Bind all RX queues to allocated MSIX interrupt */
693 for (i = 0; i < vsi->nb_qps; i++) {
694 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
695 I40E_QINT_RQCTL_ITR_INDX_MASK |
696 ((vsi->base_queue + i + 1) <<
697 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
698 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
699 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
701 if (i == vsi->nb_qps - 1)
702 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
703 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
706 /* Write first RX queue to Link list register as the head element */
707 if (vsi->type != I40E_VSI_SRIOV) {
709 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
711 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
713 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
714 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
716 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
717 msix_vect - 1), interval);
719 #ifndef I40E_GLINT_CTL
720 #define I40E_GLINT_CTL 0x0003F800
721 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
723 /* Disable auto-mask on enabling of all none-zero interrupt */
724 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
725 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
729 /* num_msix_vectors_vf needs to minus irq0 */
730 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
731 vsi->user_param + (msix_vect - 1);
733 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
734 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
735 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
738 I40E_WRITE_FLUSH(hw);
742 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
744 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
745 uint16_t interval = i40e_calc_itr_interval(\
746 RTE_LIBRTE_I40E_ITR_INTERVAL);
748 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
749 I40E_PFINT_DYN_CTLN_INTENA_MASK |
750 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
751 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
752 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
756 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
758 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
760 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
763 static inline uint8_t
764 i40e_parse_link_speed(uint16_t eth_link_speed)
766 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
768 switch (eth_link_speed) {
769 case ETH_LINK_SPEED_40G:
770 link_speed = I40E_LINK_SPEED_40GB;
772 case ETH_LINK_SPEED_20G:
773 link_speed = I40E_LINK_SPEED_20GB;
775 case ETH_LINK_SPEED_10G:
776 link_speed = I40E_LINK_SPEED_10GB;
778 case ETH_LINK_SPEED_1000:
779 link_speed = I40E_LINK_SPEED_1GB;
781 case ETH_LINK_SPEED_100:
782 link_speed = I40E_LINK_SPEED_100MB;
790 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
792 enum i40e_status_code status;
793 struct i40e_aq_get_phy_abilities_resp phy_ab;
794 struct i40e_aq_set_phy_config phy_conf;
795 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
796 I40E_AQ_PHY_FLAG_PAUSE_RX |
797 I40E_AQ_PHY_FLAG_LOW_POWER;
798 const uint8_t advt = I40E_LINK_SPEED_40GB |
799 I40E_LINK_SPEED_10GB |
800 I40E_LINK_SPEED_1GB |
801 I40E_LINK_SPEED_100MB;
804 /* Skip it on 40G interfaces, as a workaround for the link issue */
805 if (i40e_is_40G_device(hw->device_id))
808 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
813 memset(&phy_conf, 0, sizeof(phy_conf));
815 /* bits 0-2 use the values from get_phy_abilities_resp */
817 abilities |= phy_ab.abilities & mask;
819 /* update ablities and speed */
820 if (abilities & I40E_AQ_PHY_AN_ENABLED)
821 phy_conf.link_speed = advt;
823 phy_conf.link_speed = force_speed;
825 phy_conf.abilities = abilities;
827 /* use get_phy_abilities_resp value for the rest */
828 phy_conf.phy_type = phy_ab.phy_type;
829 phy_conf.eee_capability = phy_ab.eee_capability;
830 phy_conf.eeer = phy_ab.eeer_val;
831 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
833 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
834 phy_ab.abilities, phy_ab.link_speed);
835 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
836 phy_conf.abilities, phy_conf.link_speed);
838 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
846 i40e_apply_link_speed(struct rte_eth_dev *dev)
849 uint8_t abilities = 0;
850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
851 struct rte_eth_conf *conf = &dev->data->dev_conf;
853 speed = i40e_parse_link_speed(conf->link_speed);
854 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
855 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
856 abilities |= I40E_AQ_PHY_AN_ENABLED;
858 abilities |= I40E_AQ_PHY_LINK_ENABLED;
860 return i40e_phy_conf_link(hw, abilities, speed);
864 i40e_dev_start(struct rte_eth_dev *dev)
866 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
867 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
868 struct i40e_vsi *main_vsi = pf->main_vsi;
871 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
872 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
873 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
874 dev->data->dev_conf.link_duplex,
880 ret = i40e_dev_rxtx_init(pf);
881 if (ret != I40E_SUCCESS) {
882 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
886 /* Map queues with MSIX interrupt */
887 i40e_vsi_queues_bind_intr(main_vsi);
888 i40e_vsi_enable_queues_intr(main_vsi);
890 /* Map VMDQ VSI queues with MSIX interrupt */
891 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
892 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
893 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
896 /* enable FDIR MSIX interrupt */
897 if (pf->fdir.fdir_vsi) {
898 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
899 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
902 /* Enable all queues which have been configured */
903 ret = i40e_dev_switch_queues(pf, TRUE);
904 if (ret != I40E_SUCCESS) {
905 PMD_DRV_LOG(ERR, "Failed to enable VSI");
909 /* Enable receiving broadcast packets */
910 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
911 if (ret != I40E_SUCCESS)
912 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
914 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
915 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
917 if (ret != I40E_SUCCESS)
918 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
921 /* Apply link configure */
922 ret = i40e_apply_link_speed(dev);
923 if (I40E_SUCCESS != ret) {
924 PMD_DRV_LOG(ERR, "Fail to apply link setting");
931 i40e_dev_switch_queues(pf, FALSE);
932 i40e_dev_clear_queues(dev);
938 i40e_dev_stop(struct rte_eth_dev *dev)
940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
941 struct i40e_vsi *main_vsi = pf->main_vsi;
942 struct i40e_mirror_rule *p_mirror;
945 /* Disable all queues */
946 i40e_dev_switch_queues(pf, FALSE);
948 /* un-map queues with interrupt registers */
949 i40e_vsi_disable_queues_intr(main_vsi);
950 i40e_vsi_queues_unbind_intr(main_vsi);
952 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
953 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
954 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
957 if (pf->fdir.fdir_vsi) {
958 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
959 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
961 /* Clear all queues and release memory */
962 i40e_dev_clear_queues(dev);
965 i40e_dev_set_link_down(dev);
967 /* Remove all mirror rules */
968 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
969 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
972 pf->nb_mirror_rule = 0;
977 i40e_dev_close(struct rte_eth_dev *dev)
979 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
980 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
983 PMD_INIT_FUNC_TRACE();
987 /* Disable interrupt */
988 i40e_pf_disable_irq0(hw);
989 rte_intr_disable(&(dev->pci_dev->intr_handle));
991 /* shutdown and destroy the HMC */
992 i40e_shutdown_lan_hmc(hw);
994 /* release all the existing VSIs and VEBs */
995 i40e_fdir_teardown(pf);
996 i40e_vsi_release(pf->main_vsi);
998 /* shutdown the adminq */
999 i40e_aq_queue_shutdown(hw, true);
1000 i40e_shutdown_adminq(hw);
1002 i40e_res_pool_destroy(&pf->qp_pool);
1003 i40e_res_pool_destroy(&pf->msix_pool);
1005 /* force a PF reset to clean anything leftover */
1006 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1007 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1008 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1009 I40E_WRITE_FLUSH(hw);
1013 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1015 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017 struct i40e_vsi *vsi = pf->main_vsi;
1020 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1022 if (status != I40E_SUCCESS)
1023 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1025 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1027 if (status != I40E_SUCCESS)
1028 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1033 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1035 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 struct i40e_vsi *vsi = pf->main_vsi;
1040 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1042 if (status != I40E_SUCCESS)
1043 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1045 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1047 if (status != I40E_SUCCESS)
1048 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1052 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1054 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056 struct i40e_vsi *vsi = pf->main_vsi;
1059 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1060 if (ret != I40E_SUCCESS)
1061 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1065 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1067 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1068 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1069 struct i40e_vsi *vsi = pf->main_vsi;
1072 if (dev->data->promiscuous == 1)
1073 return; /* must remain in all_multicast mode */
1075 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1076 vsi->seid, FALSE, NULL);
1077 if (ret != I40E_SUCCESS)
1078 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1082 * Set device link up.
1085 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1087 /* re-apply link speed setting */
1088 return i40e_apply_link_speed(dev);
1092 * Set device link down.
1095 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1097 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1098 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 return i40e_phy_conf_link(hw, abilities, speed);
1105 i40e_dev_link_update(struct rte_eth_dev *dev,
1106 int wait_to_complete)
1108 #define CHECK_INTERVAL 100 /* 100ms */
1109 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1110 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111 struct i40e_link_status link_status;
1112 struct rte_eth_link link, old;
1114 unsigned rep_cnt = MAX_REPEAT_TIME;
1116 memset(&link, 0, sizeof(link));
1117 memset(&old, 0, sizeof(old));
1118 memset(&link_status, 0, sizeof(link_status));
1119 rte_i40e_dev_atomic_read_link_status(dev, &old);
1122 /* Get link status information from hardware */
1123 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1124 if (status != I40E_SUCCESS) {
1125 link.link_speed = ETH_LINK_SPEED_100;
1126 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1127 PMD_DRV_LOG(ERR, "Failed to get link info");
1131 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1132 if (!wait_to_complete)
1135 rte_delay_ms(CHECK_INTERVAL);
1136 } while (!link.link_status && rep_cnt--);
1138 if (!link.link_status)
1141 /* i40e uses full duplex only */
1142 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1144 /* Parse the link status */
1145 switch (link_status.link_speed) {
1146 case I40E_LINK_SPEED_100MB:
1147 link.link_speed = ETH_LINK_SPEED_100;
1149 case I40E_LINK_SPEED_1GB:
1150 link.link_speed = ETH_LINK_SPEED_1000;
1152 case I40E_LINK_SPEED_10GB:
1153 link.link_speed = ETH_LINK_SPEED_10G;
1155 case I40E_LINK_SPEED_20GB:
1156 link.link_speed = ETH_LINK_SPEED_20G;
1158 case I40E_LINK_SPEED_40GB:
1159 link.link_speed = ETH_LINK_SPEED_40G;
1162 link.link_speed = ETH_LINK_SPEED_100;
1167 rte_i40e_dev_atomic_write_link_status(dev, &link);
1168 if (link.link_status == old.link_status)
1174 /* Get all the statistics of a VSI */
1176 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1178 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1179 struct i40e_eth_stats *nes = &vsi->eth_stats;
1180 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1181 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1183 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1184 vsi->offset_loaded, &oes->rx_bytes,
1186 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1187 vsi->offset_loaded, &oes->rx_unicast,
1189 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1190 vsi->offset_loaded, &oes->rx_multicast,
1191 &nes->rx_multicast);
1192 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1193 vsi->offset_loaded, &oes->rx_broadcast,
1194 &nes->rx_broadcast);
1195 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1196 &oes->rx_discards, &nes->rx_discards);
1197 /* GLV_REPC not supported */
1198 /* GLV_RMPC not supported */
1199 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1200 &oes->rx_unknown_protocol,
1201 &nes->rx_unknown_protocol);
1202 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1203 vsi->offset_loaded, &oes->tx_bytes,
1205 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1206 vsi->offset_loaded, &oes->tx_unicast,
1208 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1209 vsi->offset_loaded, &oes->tx_multicast,
1210 &nes->tx_multicast);
1211 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1212 vsi->offset_loaded, &oes->tx_broadcast,
1213 &nes->tx_broadcast);
1214 /* GLV_TDPC not supported */
1215 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1216 &oes->tx_errors, &nes->tx_errors);
1217 vsi->offset_loaded = true;
1219 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1221 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1222 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1223 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1224 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1225 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1226 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1227 nes->rx_unknown_protocol);
1228 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1229 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1230 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1231 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1232 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1233 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1234 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1238 /* Get all statistics of a port */
1240 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1246 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1248 /* Get statistics of struct i40e_eth_stats */
1249 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1250 I40E_GLPRT_GORCL(hw->port),
1251 pf->offset_loaded, &os->eth.rx_bytes,
1253 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1254 I40E_GLPRT_UPRCL(hw->port),
1255 pf->offset_loaded, &os->eth.rx_unicast,
1256 &ns->eth.rx_unicast);
1257 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1258 I40E_GLPRT_MPRCL(hw->port),
1259 pf->offset_loaded, &os->eth.rx_multicast,
1260 &ns->eth.rx_multicast);
1261 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1262 I40E_GLPRT_BPRCL(hw->port),
1263 pf->offset_loaded, &os->eth.rx_broadcast,
1264 &ns->eth.rx_broadcast);
1265 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1266 pf->offset_loaded, &os->eth.rx_discards,
1267 &ns->eth.rx_discards);
1268 /* GLPRT_REPC not supported */
1269 /* GLPRT_RMPC not supported */
1270 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1272 &os->eth.rx_unknown_protocol,
1273 &ns->eth.rx_unknown_protocol);
1274 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1275 I40E_GLPRT_GOTCL(hw->port),
1276 pf->offset_loaded, &os->eth.tx_bytes,
1278 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1279 I40E_GLPRT_UPTCL(hw->port),
1280 pf->offset_loaded, &os->eth.tx_unicast,
1281 &ns->eth.tx_unicast);
1282 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1283 I40E_GLPRT_MPTCL(hw->port),
1284 pf->offset_loaded, &os->eth.tx_multicast,
1285 &ns->eth.tx_multicast);
1286 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1287 I40E_GLPRT_BPTCL(hw->port),
1288 pf->offset_loaded, &os->eth.tx_broadcast,
1289 &ns->eth.tx_broadcast);
1290 /* GLPRT_TEPC not supported */
1292 /* additional port specific stats */
1293 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1294 pf->offset_loaded, &os->tx_dropped_link_down,
1295 &ns->tx_dropped_link_down);
1296 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1297 pf->offset_loaded, &os->crc_errors,
1299 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1300 pf->offset_loaded, &os->illegal_bytes,
1301 &ns->illegal_bytes);
1302 /* GLPRT_ERRBC not supported */
1303 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1304 pf->offset_loaded, &os->mac_local_faults,
1305 &ns->mac_local_faults);
1306 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1307 pf->offset_loaded, &os->mac_remote_faults,
1308 &ns->mac_remote_faults);
1309 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1310 pf->offset_loaded, &os->rx_length_errors,
1311 &ns->rx_length_errors);
1312 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1313 pf->offset_loaded, &os->link_xon_rx,
1315 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1316 pf->offset_loaded, &os->link_xoff_rx,
1318 for (i = 0; i < 8; i++) {
1319 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1321 &os->priority_xon_rx[i],
1322 &ns->priority_xon_rx[i]);
1323 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1325 &os->priority_xoff_rx[i],
1326 &ns->priority_xoff_rx[i]);
1328 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1329 pf->offset_loaded, &os->link_xon_tx,
1331 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1332 pf->offset_loaded, &os->link_xoff_tx,
1334 for (i = 0; i < 8; i++) {
1335 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1337 &os->priority_xon_tx[i],
1338 &ns->priority_xon_tx[i]);
1339 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1341 &os->priority_xoff_tx[i],
1342 &ns->priority_xoff_tx[i]);
1343 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1345 &os->priority_xon_2_xoff[i],
1346 &ns->priority_xon_2_xoff[i]);
1348 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1349 I40E_GLPRT_PRC64L(hw->port),
1350 pf->offset_loaded, &os->rx_size_64,
1352 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1353 I40E_GLPRT_PRC127L(hw->port),
1354 pf->offset_loaded, &os->rx_size_127,
1356 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1357 I40E_GLPRT_PRC255L(hw->port),
1358 pf->offset_loaded, &os->rx_size_255,
1360 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1361 I40E_GLPRT_PRC511L(hw->port),
1362 pf->offset_loaded, &os->rx_size_511,
1364 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1365 I40E_GLPRT_PRC1023L(hw->port),
1366 pf->offset_loaded, &os->rx_size_1023,
1368 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1369 I40E_GLPRT_PRC1522L(hw->port),
1370 pf->offset_loaded, &os->rx_size_1522,
1372 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1373 I40E_GLPRT_PRC9522L(hw->port),
1374 pf->offset_loaded, &os->rx_size_big,
1376 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1377 pf->offset_loaded, &os->rx_undersize,
1379 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1380 pf->offset_loaded, &os->rx_fragments,
1382 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1383 pf->offset_loaded, &os->rx_oversize,
1385 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1386 pf->offset_loaded, &os->rx_jabber,
1388 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1389 I40E_GLPRT_PTC64L(hw->port),
1390 pf->offset_loaded, &os->tx_size_64,
1392 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1393 I40E_GLPRT_PTC127L(hw->port),
1394 pf->offset_loaded, &os->tx_size_127,
1396 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1397 I40E_GLPRT_PTC255L(hw->port),
1398 pf->offset_loaded, &os->tx_size_255,
1400 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1401 I40E_GLPRT_PTC511L(hw->port),
1402 pf->offset_loaded, &os->tx_size_511,
1404 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1405 I40E_GLPRT_PTC1023L(hw->port),
1406 pf->offset_loaded, &os->tx_size_1023,
1408 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1409 I40E_GLPRT_PTC1522L(hw->port),
1410 pf->offset_loaded, &os->tx_size_1522,
1412 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1413 I40E_GLPRT_PTC9522L(hw->port),
1414 pf->offset_loaded, &os->tx_size_big,
1416 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1418 &os->fd_sb_match, &ns->fd_sb_match);
1419 /* GLPRT_MSPDC not supported */
1420 /* GLPRT_XEC not supported */
1422 pf->offset_loaded = true;
1425 i40e_update_vsi_stats(pf->main_vsi);
1427 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1428 ns->eth.rx_broadcast;
1429 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1430 ns->eth.tx_broadcast;
1431 stats->ibytes = ns->eth.rx_bytes;
1432 stats->obytes = ns->eth.tx_bytes;
1433 stats->oerrors = ns->eth.tx_errors;
1434 stats->imcasts = ns->eth.rx_multicast;
1435 stats->fdirmatch = ns->fd_sb_match;
1438 stats->ibadcrc = ns->crc_errors;
1439 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1440 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1441 stats->imissed = ns->eth.rx_discards;
1442 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1444 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1445 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1446 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1447 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1448 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1449 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1450 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1451 ns->eth.rx_unknown_protocol);
1452 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1453 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1454 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1455 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1456 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1457 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1459 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1460 ns->tx_dropped_link_down);
1461 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1462 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1464 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1465 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1466 ns->mac_local_faults);
1467 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1468 ns->mac_remote_faults);
1469 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1470 ns->rx_length_errors);
1471 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1472 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1473 for (i = 0; i < 8; i++) {
1474 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1475 i, ns->priority_xon_rx[i]);
1476 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1477 i, ns->priority_xoff_rx[i]);
1479 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1480 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1481 for (i = 0; i < 8; i++) {
1482 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1483 i, ns->priority_xon_tx[i]);
1484 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1485 i, ns->priority_xoff_tx[i]);
1486 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1487 i, ns->priority_xon_2_xoff[i]);
1489 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1490 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1491 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1492 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1493 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1494 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1495 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1496 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1497 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1498 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1499 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1500 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1501 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1502 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1503 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1504 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1505 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1506 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1507 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1508 ns->mac_short_packet_dropped);
1509 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1510 ns->checksum_error);
1511 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1512 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1515 /* Reset the statistics */
1517 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1519 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1521 /* It results in reloading the start point of each counter */
1522 pf->offset_loaded = false;
1526 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1527 __rte_unused uint16_t queue_id,
1528 __rte_unused uint8_t stat_idx,
1529 __rte_unused uint8_t is_rx)
1531 PMD_INIT_FUNC_TRACE();
1537 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1539 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1540 struct i40e_vsi *vsi = pf->main_vsi;
1542 dev_info->max_rx_queues = vsi->nb_qps;
1543 dev_info->max_tx_queues = vsi->nb_qps;
1544 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1545 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1546 dev_info->max_mac_addrs = vsi->max_macaddrs;
1547 dev_info->max_vfs = dev->pci_dev->max_vfs;
1548 dev_info->rx_offload_capa =
1549 DEV_RX_OFFLOAD_VLAN_STRIP |
1550 DEV_RX_OFFLOAD_QINQ_STRIP |
1551 DEV_RX_OFFLOAD_IPV4_CKSUM |
1552 DEV_RX_OFFLOAD_UDP_CKSUM |
1553 DEV_RX_OFFLOAD_TCP_CKSUM;
1554 dev_info->tx_offload_capa =
1555 DEV_TX_OFFLOAD_VLAN_INSERT |
1556 DEV_TX_OFFLOAD_QINQ_INSERT |
1557 DEV_TX_OFFLOAD_IPV4_CKSUM |
1558 DEV_TX_OFFLOAD_UDP_CKSUM |
1559 DEV_TX_OFFLOAD_TCP_CKSUM |
1560 DEV_TX_OFFLOAD_SCTP_CKSUM |
1561 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1562 DEV_TX_OFFLOAD_TCP_TSO;
1563 dev_info->reta_size = pf->hash_lut_size;
1564 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1566 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1568 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1569 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1570 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1572 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1576 dev_info->default_txconf = (struct rte_eth_txconf) {
1578 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1579 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1580 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1582 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1583 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1584 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1585 ETH_TXQ_FLAGS_NOOFFLOADS,
1588 if (pf->flags & I40E_FLAG_VMDQ) {
1589 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1590 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1591 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1592 pf->max_nb_vmdq_vsi;
1593 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1594 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1595 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1600 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1602 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1603 struct i40e_vsi *vsi = pf->main_vsi;
1604 PMD_INIT_FUNC_TRACE();
1607 return i40e_vsi_add_vlan(vsi, vlan_id);
1609 return i40e_vsi_delete_vlan(vsi, vlan_id);
1613 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1614 __rte_unused uint16_t tpid)
1616 PMD_INIT_FUNC_TRACE();
1620 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1622 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1623 struct i40e_vsi *vsi = pf->main_vsi;
1625 if (mask & ETH_VLAN_STRIP_MASK) {
1626 /* Enable or disable VLAN stripping */
1627 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1628 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1630 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1633 if (mask & ETH_VLAN_EXTEND_MASK) {
1634 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1635 i40e_vsi_config_double_vlan(vsi, TRUE);
1637 i40e_vsi_config_double_vlan(vsi, FALSE);
1642 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1643 __rte_unused uint16_t queue,
1644 __rte_unused int on)
1646 PMD_INIT_FUNC_TRACE();
1650 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1652 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1653 struct i40e_vsi *vsi = pf->main_vsi;
1654 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1655 struct i40e_vsi_vlan_pvid_info info;
1657 memset(&info, 0, sizeof(info));
1660 info.config.pvid = pvid;
1662 info.config.reject.tagged =
1663 data->dev_conf.txmode.hw_vlan_reject_tagged;
1664 info.config.reject.untagged =
1665 data->dev_conf.txmode.hw_vlan_reject_untagged;
1668 return i40e_vsi_vlan_pvid_set(vsi, &info);
1672 i40e_dev_led_on(struct rte_eth_dev *dev)
1674 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675 uint32_t mode = i40e_led_get(hw);
1678 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1684 i40e_dev_led_off(struct rte_eth_dev *dev)
1686 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 uint32_t mode = i40e_led_get(hw);
1690 i40e_led_set(hw, 0, false);
1696 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1697 __rte_unused struct rte_eth_fc_conf *fc_conf)
1699 PMD_INIT_FUNC_TRACE();
1705 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1706 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1708 PMD_INIT_FUNC_TRACE();
1713 /* Add a MAC address, and update filters */
1715 i40e_macaddr_add(struct rte_eth_dev *dev,
1716 struct ether_addr *mac_addr,
1717 __rte_unused uint32_t index,
1720 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1721 struct i40e_mac_filter_info mac_filter;
1722 struct i40e_vsi *vsi;
1725 /* If VMDQ not enabled or configured, return */
1726 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1727 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1728 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1733 if (pool > pf->nb_cfg_vmdq_vsi) {
1734 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1735 pool, pf->nb_cfg_vmdq_vsi);
1739 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1740 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1745 vsi = pf->vmdq[pool - 1].vsi;
1747 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1748 if (ret != I40E_SUCCESS) {
1749 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1754 /* Remove a MAC address, and update filters */
1756 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1758 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1759 struct i40e_vsi *vsi;
1760 struct rte_eth_dev_data *data = dev->data;
1761 struct ether_addr *macaddr;
1766 macaddr = &(data->mac_addrs[index]);
1768 pool_sel = dev->data->mac_pool_sel[index];
1770 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1771 if (pool_sel & (1ULL << i)) {
1775 /* No VMDQ pool enabled or configured */
1776 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1777 (i > pf->nb_cfg_vmdq_vsi)) {
1778 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1782 vsi = pf->vmdq[i - 1].vsi;
1784 ret = i40e_vsi_delete_mac(vsi, macaddr);
1787 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1794 /* Set perfect match or hash match of MAC and VLAN for a VF */
1796 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1797 struct rte_eth_mac_filter *filter,
1801 struct i40e_mac_filter_info mac_filter;
1802 struct ether_addr old_mac;
1803 struct ether_addr *new_mac;
1804 struct i40e_pf_vf *vf = NULL;
1809 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1812 hw = I40E_PF_TO_HW(pf);
1814 if (filter == NULL) {
1815 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1819 new_mac = &filter->mac_addr;
1821 if (is_zero_ether_addr(new_mac)) {
1822 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1826 vf_id = filter->dst_id;
1828 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1829 PMD_DRV_LOG(ERR, "Invalid argument.");
1832 vf = &pf->vfs[vf_id];
1834 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1835 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1840 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1841 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1843 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1846 mac_filter.filter_type = filter->filter_type;
1847 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1848 if (ret != I40E_SUCCESS) {
1849 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1852 ether_addr_copy(new_mac, &pf->dev_addr);
1854 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1856 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1857 if (ret != I40E_SUCCESS) {
1858 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1862 /* Clear device address as it has been removed */
1863 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1864 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1870 /* MAC filter handle */
1872 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1875 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1876 struct rte_eth_mac_filter *filter;
1877 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1878 int ret = I40E_NOT_SUPPORTED;
1880 filter = (struct rte_eth_mac_filter *)(arg);
1882 switch (filter_op) {
1883 case RTE_ETH_FILTER_NOP:
1886 case RTE_ETH_FILTER_ADD:
1887 i40e_pf_disable_irq0(hw);
1889 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1890 i40e_pf_enable_irq0(hw);
1892 case RTE_ETH_FILTER_DELETE:
1893 i40e_pf_disable_irq0(hw);
1895 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1896 i40e_pf_enable_irq0(hw);
1899 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1900 ret = I40E_ERR_PARAM;
1908 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1909 struct rte_eth_rss_reta_entry64 *reta_conf,
1912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915 uint16_t i, j, lut_size = pf->hash_lut_size;
1916 uint16_t idx, shift;
1919 if (reta_size != lut_size ||
1920 reta_size > ETH_RSS_RETA_SIZE_512) {
1921 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1922 "(%d) doesn't match the number hardware can supported "
1923 "(%d)\n", reta_size, lut_size);
1927 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1928 idx = i / RTE_RETA_GROUP_SIZE;
1929 shift = i % RTE_RETA_GROUP_SIZE;
1930 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1934 if (mask == I40E_4_BIT_MASK)
1937 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1938 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1939 if (mask & (0x1 << j))
1940 lut |= reta_conf[idx].reta[shift + j] <<
1943 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1945 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1952 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1953 struct rte_eth_rss_reta_entry64 *reta_conf,
1956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1957 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959 uint16_t i, j, lut_size = pf->hash_lut_size;
1960 uint16_t idx, shift;
1963 if (reta_size != lut_size ||
1964 reta_size > ETH_RSS_RETA_SIZE_512) {
1965 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1966 "(%d) doesn't match the number hardware can supported "
1967 "(%d)\n", reta_size, lut_size);
1971 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1972 idx = i / RTE_RETA_GROUP_SIZE;
1973 shift = i % RTE_RETA_GROUP_SIZE;
1974 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1979 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1980 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1981 if (mask & (0x1 << j))
1982 reta_conf[idx].reta[shift + j] = ((lut >>
1983 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1991 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1992 * @hw: pointer to the HW structure
1993 * @mem: pointer to mem struct to fill out
1994 * @size: size of memory requested
1995 * @alignment: what to align the allocation to
1997 enum i40e_status_code
1998 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1999 struct i40e_dma_mem *mem,
2003 static uint64_t id = 0;
2004 const struct rte_memzone *mz = NULL;
2005 char z_name[RTE_MEMZONE_NAMESIZE];
2008 return I40E_ERR_PARAM;
2011 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2012 #ifdef RTE_LIBRTE_XEN_DOM0
2013 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2016 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2019 return I40E_ERR_NO_MEMORY;
2024 #ifdef RTE_LIBRTE_XEN_DOM0
2025 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2027 mem->pa = mz->phys_addr;
2030 return I40E_SUCCESS;
2034 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2035 * @hw: pointer to the HW structure
2036 * @mem: ptr to mem struct to free
2038 enum i40e_status_code
2039 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2040 struct i40e_dma_mem *mem)
2042 if (!mem || !mem->va)
2043 return I40E_ERR_PARAM;
2048 return I40E_SUCCESS;
2052 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2053 * @hw: pointer to the HW structure
2054 * @mem: pointer to mem struct to fill out
2055 * @size: size of memory requested
2057 enum i40e_status_code
2058 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2059 struct i40e_virt_mem *mem,
2063 return I40E_ERR_PARAM;
2066 mem->va = rte_zmalloc("i40e", size, 0);
2069 return I40E_SUCCESS;
2071 return I40E_ERR_NO_MEMORY;
2075 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2076 * @hw: pointer to the HW structure
2077 * @mem: pointer to mem struct to free
2079 enum i40e_status_code
2080 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2081 struct i40e_virt_mem *mem)
2084 return I40E_ERR_PARAM;
2089 return I40E_SUCCESS;
2093 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2095 rte_spinlock_init(&sp->spinlock);
2099 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2101 rte_spinlock_lock(&sp->spinlock);
2105 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2107 rte_spinlock_unlock(&sp->spinlock);
2111 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2117 * Get the hardware capabilities, which will be parsed
2118 * and saved into struct i40e_hw.
2121 i40e_get_cap(struct i40e_hw *hw)
2123 struct i40e_aqc_list_capabilities_element_resp *buf;
2124 uint16_t len, size = 0;
2127 /* Calculate a huge enough buff for saving response data temporarily */
2128 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2129 I40E_MAX_CAP_ELE_NUM;
2130 buf = rte_zmalloc("i40e", len, 0);
2132 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2133 return I40E_ERR_NO_MEMORY;
2136 /* Get, parse the capabilities and save it to hw */
2137 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2138 i40e_aqc_opc_list_func_capabilities, NULL);
2139 if (ret != I40E_SUCCESS)
2140 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2142 /* Free the temporary buffer after being used */
2149 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2151 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2153 uint16_t sum_queues = 0, sum_vsis, left_queues;
2155 /* First check if FW support SRIOV */
2156 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2157 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2161 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2162 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2163 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2164 /* Allocate queues for pf */
2165 if (hw->func_caps.rss) {
2166 pf->flags |= I40E_FLAG_RSS;
2167 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2168 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2169 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2172 sum_queues = pf->lan_nb_qps;
2173 /* Default VSI is not counted in */
2175 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2177 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2178 pf->flags |= I40E_FLAG_SRIOV;
2179 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2180 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2181 PMD_INIT_LOG(ERR, "Config VF number %u, "
2182 "max supported %u.",
2183 dev->pci_dev->max_vfs,
2184 hw->func_caps.num_vfs);
2187 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2188 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2189 "max support %u queues.",
2190 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2193 pf->vf_num = dev->pci_dev->max_vfs;
2194 sum_queues += pf->vf_nb_qps * pf->vf_num;
2195 sum_vsis += pf->vf_num;
2196 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2197 pf->vf_num, pf->vf_nb_qps);
2201 if (hw->func_caps.vmdq) {
2202 pf->flags |= I40E_FLAG_VMDQ;
2203 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2204 pf->max_nb_vmdq_vsi = 1;
2206 * If VMDQ available, assume a single VSI can be created. Will adjust
2209 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2210 sum_vsis += pf->max_nb_vmdq_vsi;
2212 pf->vmdq_nb_qps = 0;
2213 pf->max_nb_vmdq_vsi = 0;
2215 pf->nb_cfg_vmdq_vsi = 0;
2217 if (hw->func_caps.fd) {
2218 pf->flags |= I40E_FLAG_FDIR;
2219 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2221 * Each flow director consumes one VSI and one queue,
2222 * but can't calculate out predictably here.
2226 if (sum_vsis > pf->max_num_vsi ||
2227 sum_queues > hw->func_caps.num_rx_qp) {
2228 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2229 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2230 pf->max_num_vsi, sum_vsis);
2231 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2232 hw->func_caps.num_rx_qp, sum_queues);
2236 /* Adjust VMDQ setting to support as many VMs as possible */
2237 if (pf->flags & I40E_FLAG_VMDQ) {
2238 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2240 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2241 pf->max_num_vsi - sum_vsis);
2243 /* Limit the max VMDQ number that rte_ether that can support */
2244 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2247 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2248 pf->max_nb_vmdq_vsi);
2249 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2252 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2254 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2255 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2256 sum_vsis, hw->func_caps.num_msix_vectors);
2259 return I40E_SUCCESS;
2263 i40e_pf_get_switch_config(struct i40e_pf *pf)
2265 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2266 struct i40e_aqc_get_switch_config_resp *switch_config;
2267 struct i40e_aqc_switch_config_element_resp *element;
2268 uint16_t start_seid = 0, num_reported;
2271 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2272 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2273 if (!switch_config) {
2274 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2278 /* Get the switch configurations */
2279 ret = i40e_aq_get_switch_config(hw, switch_config,
2280 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2281 if (ret != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2285 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2286 if (num_reported != 1) { /* The number should be 1 */
2287 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2291 /* Parse the switch configuration elements */
2292 element = &(switch_config->element[0]);
2293 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2294 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2295 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2297 PMD_DRV_LOG(INFO, "Unknown element type");
2300 rte_free(switch_config);
2306 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2309 struct pool_entry *entry;
2311 if (pool == NULL || num == 0)
2314 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2315 if (entry == NULL) {
2316 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2320 /* queue heap initialize */
2321 pool->num_free = num;
2322 pool->num_alloc = 0;
2324 LIST_INIT(&pool->alloc_list);
2325 LIST_INIT(&pool->free_list);
2327 /* Initialize element */
2331 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2336 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2338 struct pool_entry *entry;
2343 LIST_FOREACH(entry, &pool->alloc_list, next) {
2344 LIST_REMOVE(entry, next);
2348 LIST_FOREACH(entry, &pool->free_list, next) {
2349 LIST_REMOVE(entry, next);
2354 pool->num_alloc = 0;
2356 LIST_INIT(&pool->alloc_list);
2357 LIST_INIT(&pool->free_list);
2361 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2364 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2365 uint32_t pool_offset;
2369 PMD_DRV_LOG(ERR, "Invalid parameter");
2373 pool_offset = base - pool->base;
2374 /* Lookup in alloc list */
2375 LIST_FOREACH(entry, &pool->alloc_list, next) {
2376 if (entry->base == pool_offset) {
2377 valid_entry = entry;
2378 LIST_REMOVE(entry, next);
2383 /* Not find, return */
2384 if (valid_entry == NULL) {
2385 PMD_DRV_LOG(ERR, "Failed to find entry");
2390 * Found it, move it to free list and try to merge.
2391 * In order to make merge easier, always sort it by qbase.
2392 * Find adjacent prev and last entries.
2395 LIST_FOREACH(entry, &pool->free_list, next) {
2396 if (entry->base > valid_entry->base) {
2404 /* Try to merge with next one*/
2406 /* Merge with next one */
2407 if (valid_entry->base + valid_entry->len == next->base) {
2408 next->base = valid_entry->base;
2409 next->len += valid_entry->len;
2410 rte_free(valid_entry);
2417 /* Merge with previous one */
2418 if (prev->base + prev->len == valid_entry->base) {
2419 prev->len += valid_entry->len;
2420 /* If it merge with next one, remove next node */
2422 LIST_REMOVE(valid_entry, next);
2423 rte_free(valid_entry);
2425 rte_free(valid_entry);
2431 /* Not find any entry to merge, insert */
2434 LIST_INSERT_AFTER(prev, valid_entry, next);
2435 else if (next != NULL)
2436 LIST_INSERT_BEFORE(next, valid_entry, next);
2437 else /* It's empty list, insert to head */
2438 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2441 pool->num_free += valid_entry->len;
2442 pool->num_alloc -= valid_entry->len;
2448 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2451 struct pool_entry *entry, *valid_entry;
2453 if (pool == NULL || num == 0) {
2454 PMD_DRV_LOG(ERR, "Invalid parameter");
2458 if (pool->num_free < num) {
2459 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2460 num, pool->num_free);
2465 /* Lookup in free list and find most fit one */
2466 LIST_FOREACH(entry, &pool->free_list, next) {
2467 if (entry->len >= num) {
2469 if (entry->len == num) {
2470 valid_entry = entry;
2473 if (valid_entry == NULL || valid_entry->len > entry->len)
2474 valid_entry = entry;
2478 /* Not find one to satisfy the request, return */
2479 if (valid_entry == NULL) {
2480 PMD_DRV_LOG(ERR, "No valid entry found");
2484 * The entry have equal queue number as requested,
2485 * remove it from alloc_list.
2487 if (valid_entry->len == num) {
2488 LIST_REMOVE(valid_entry, next);
2491 * The entry have more numbers than requested,
2492 * create a new entry for alloc_list and minus its
2493 * queue base and number in free_list.
2495 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2496 if (entry == NULL) {
2497 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2501 entry->base = valid_entry->base;
2503 valid_entry->base += num;
2504 valid_entry->len -= num;
2505 valid_entry = entry;
2508 /* Insert it into alloc list, not sorted */
2509 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2511 pool->num_free -= valid_entry->len;
2512 pool->num_alloc += valid_entry->len;
2514 return (valid_entry->base + pool->base);
2518 * bitmap_is_subset - Check whether src2 is subset of src1
2521 bitmap_is_subset(uint8_t src1, uint8_t src2)
2523 return !((src1 ^ src2) & src2);
2527 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2529 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2531 /* If DCB is not supported, only default TC is supported */
2532 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2533 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2537 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2538 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2539 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2543 return I40E_SUCCESS;
2547 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2548 struct i40e_vsi_vlan_pvid_info *info)
2551 struct i40e_vsi_context ctxt;
2552 uint8_t vlan_flags = 0;
2555 if (vsi == NULL || info == NULL) {
2556 PMD_DRV_LOG(ERR, "invalid parameters");
2557 return I40E_ERR_PARAM;
2561 vsi->info.pvid = info->config.pvid;
2563 * If insert pvid is enabled, only tagged pkts are
2564 * allowed to be sent out.
2566 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2567 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2570 if (info->config.reject.tagged == 0)
2571 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2573 if (info->config.reject.untagged == 0)
2574 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2576 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2577 I40E_AQ_VSI_PVLAN_MODE_MASK);
2578 vsi->info.port_vlan_flags |= vlan_flags;
2579 vsi->info.valid_sections =
2580 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2581 memset(&ctxt, 0, sizeof(ctxt));
2582 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2583 ctxt.seid = vsi->seid;
2585 hw = I40E_VSI_TO_HW(vsi);
2586 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2587 if (ret != I40E_SUCCESS)
2588 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2594 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2596 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2598 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2600 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2601 if (ret != I40E_SUCCESS)
2605 PMD_DRV_LOG(ERR, "seid not valid");
2609 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2610 tc_bw_data.tc_valid_bits = enabled_tcmap;
2611 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2612 tc_bw_data.tc_bw_credits[i] =
2613 (enabled_tcmap & (1 << i)) ? 1 : 0;
2615 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2616 if (ret != I40E_SUCCESS) {
2617 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2621 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2622 sizeof(vsi->info.qs_handle));
2623 return I40E_SUCCESS;
2627 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2628 struct i40e_aqc_vsi_properties_data *info,
2629 uint8_t enabled_tcmap)
2631 int ret, total_tc = 0, i;
2632 uint16_t qpnum_per_tc, bsf, qp_idx;
2634 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2635 if (ret != I40E_SUCCESS)
2638 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2639 if (enabled_tcmap & (1 << i))
2641 vsi->enabled_tc = enabled_tcmap;
2643 /* Number of queues per enabled TC */
2644 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2645 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2646 bsf = rte_bsf32(qpnum_per_tc);
2648 /* Adjust the queue number to actual queues that can be applied */
2649 vsi->nb_qps = qpnum_per_tc * total_tc;
2652 * Configure TC and queue mapping parameters, for enabled TC,
2653 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2654 * default queue will serve it.
2657 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2658 if (vsi->enabled_tc & (1 << i)) {
2659 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2660 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2661 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2662 qp_idx += qpnum_per_tc;
2664 info->tc_mapping[i] = 0;
2667 /* Associate queue number with VSI */
2668 if (vsi->type == I40E_VSI_SRIOV) {
2669 info->mapping_flags |=
2670 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2671 for (i = 0; i < vsi->nb_qps; i++)
2672 info->queue_mapping[i] =
2673 rte_cpu_to_le_16(vsi->base_queue + i);
2675 info->mapping_flags |=
2676 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2677 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2679 info->valid_sections |=
2680 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2682 return I40E_SUCCESS;
2686 i40e_veb_release(struct i40e_veb *veb)
2688 struct i40e_vsi *vsi;
2691 if (veb == NULL || veb->associate_vsi == NULL)
2694 if (!TAILQ_EMPTY(&veb->head)) {
2695 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2699 vsi = veb->associate_vsi;
2700 hw = I40E_VSI_TO_HW(vsi);
2702 vsi->uplink_seid = veb->uplink_seid;
2703 i40e_aq_delete_element(hw, veb->seid, NULL);
2706 return I40E_SUCCESS;
2710 static struct i40e_veb *
2711 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2713 struct i40e_veb *veb;
2717 if (NULL == pf || vsi == NULL) {
2718 PMD_DRV_LOG(ERR, "veb setup failed, "
2719 "associated VSI shouldn't null");
2722 hw = I40E_PF_TO_HW(pf);
2724 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2726 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2730 veb->associate_vsi = vsi;
2731 TAILQ_INIT(&veb->head);
2732 veb->uplink_seid = vsi->uplink_seid;
2734 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2735 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2737 if (ret != I40E_SUCCESS) {
2738 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2739 hw->aq.asq_last_status);
2743 /* get statistics index */
2744 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2745 &veb->stats_idx, NULL, NULL, NULL);
2746 if (ret != I40E_SUCCESS) {
2747 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2748 hw->aq.asq_last_status);
2752 /* Get VEB bandwidth, to be implemented */
2753 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2754 vsi->uplink_seid = veb->seid;
2763 i40e_vsi_release(struct i40e_vsi *vsi)
2767 struct i40e_vsi_list *vsi_list;
2769 struct i40e_mac_filter *f;
2772 return I40E_SUCCESS;
2774 pf = I40E_VSI_TO_PF(vsi);
2775 hw = I40E_VSI_TO_HW(vsi);
2777 /* VSI has child to attach, release child first */
2779 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2780 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2782 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2784 i40e_veb_release(vsi->veb);
2787 /* Remove all macvlan filters of the VSI */
2788 i40e_vsi_remove_all_macvlan_filter(vsi);
2789 TAILQ_FOREACH(f, &vsi->mac_list, next)
2792 if (vsi->type != I40E_VSI_MAIN) {
2793 /* Remove vsi from parent's sibling list */
2794 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2795 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2796 return I40E_ERR_PARAM;
2798 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2799 &vsi->sib_vsi_list, list);
2801 /* Remove all switch element of the VSI */
2802 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2803 if (ret != I40E_SUCCESS)
2804 PMD_DRV_LOG(ERR, "Failed to delete element");
2806 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2808 if (vsi->type != I40E_VSI_SRIOV)
2809 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2812 return I40E_SUCCESS;
2816 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2819 struct i40e_aqc_remove_macvlan_element_data def_filter;
2820 struct i40e_mac_filter_info filter;
2823 if (vsi->type != I40E_VSI_MAIN)
2824 return I40E_ERR_CONFIG;
2825 memset(&def_filter, 0, sizeof(def_filter));
2826 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2828 def_filter.vlan_tag = 0;
2829 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2830 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2831 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2832 if (ret != I40E_SUCCESS) {
2833 struct i40e_mac_filter *f;
2834 struct ether_addr *mac;
2836 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2838 /* It needs to add the permanent mac into mac list */
2839 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2841 PMD_DRV_LOG(ERR, "failed to allocate memory");
2842 return I40E_ERR_NO_MEMORY;
2844 mac = &f->mac_info.mac_addr;
2845 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2847 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2848 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2853 (void)rte_memcpy(&filter.mac_addr,
2854 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2855 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2856 return i40e_vsi_add_mac(vsi, &filter);
2860 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2862 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2863 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2864 struct i40e_hw *hw = &vsi->adapter->hw;
2868 memset(&bw_config, 0, sizeof(bw_config));
2869 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2870 if (ret != I40E_SUCCESS) {
2871 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2872 hw->aq.asq_last_status);
2876 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2877 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2878 &ets_sla_config, NULL);
2879 if (ret != I40E_SUCCESS) {
2880 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2881 "configuration %u", hw->aq.asq_last_status);
2885 /* Not store the info yet, just print out */
2886 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2887 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2888 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2889 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2890 ets_sla_config.share_credits[i]);
2891 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2892 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2893 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2894 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2903 i40e_vsi_setup(struct i40e_pf *pf,
2904 enum i40e_vsi_type type,
2905 struct i40e_vsi *uplink_vsi,
2906 uint16_t user_param)
2908 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2909 struct i40e_vsi *vsi;
2910 struct i40e_mac_filter_info filter;
2912 struct i40e_vsi_context ctxt;
2913 struct ether_addr broadcast =
2914 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2916 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2917 PMD_DRV_LOG(ERR, "VSI setup failed, "
2918 "VSI link shouldn't be NULL");
2922 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2923 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2924 "uplink VSI should be NULL");
2928 /* If uplink vsi didn't setup VEB, create one first */
2929 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2930 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2932 if (NULL == uplink_vsi->veb) {
2933 PMD_DRV_LOG(ERR, "VEB setup failed");
2938 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2940 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2943 TAILQ_INIT(&vsi->mac_list);
2945 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2946 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2947 vsi->parent_vsi = uplink_vsi;
2948 vsi->user_param = user_param;
2949 /* Allocate queues */
2950 switch (vsi->type) {
2951 case I40E_VSI_MAIN :
2952 vsi->nb_qps = pf->lan_nb_qps;
2954 case I40E_VSI_SRIOV :
2955 vsi->nb_qps = pf->vf_nb_qps;
2957 case I40E_VSI_VMDQ2:
2958 vsi->nb_qps = pf->vmdq_nb_qps;
2961 vsi->nb_qps = pf->fdir_nb_qps;
2967 * The filter status descriptor is reported in rx queue 0,
2968 * while the tx queue for fdir filter programming has no
2969 * such constraints, can be non-zero queues.
2970 * To simplify it, choose FDIR vsi use queue 0 pair.
2971 * To make sure it will use queue 0 pair, queue allocation
2972 * need be done before this function is called
2974 if (type != I40E_VSI_FDIR) {
2975 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2977 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2981 vsi->base_queue = ret;
2983 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2985 /* VF has MSIX interrupt in VF range, don't allocate here */
2986 if (type != I40E_VSI_SRIOV) {
2987 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2989 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2990 goto fail_queue_alloc;
2992 vsi->msix_intr = ret;
2996 if (type == I40E_VSI_MAIN) {
2997 /* For main VSI, no need to add since it's default one */
2998 vsi->uplink_seid = pf->mac_seid;
2999 vsi->seid = pf->main_vsi_seid;
3000 /* Bind queues with specific MSIX interrupt */
3002 * Needs 2 interrupt at least, one for misc cause which will
3003 * enabled from OS side, Another for queues binding the
3004 * interrupt from device side only.
3007 /* Get default VSI parameters from hardware */
3008 memset(&ctxt, 0, sizeof(ctxt));
3009 ctxt.seid = vsi->seid;
3010 ctxt.pf_num = hw->pf_id;
3011 ctxt.uplink_seid = vsi->uplink_seid;
3013 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3014 if (ret != I40E_SUCCESS) {
3015 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3016 goto fail_msix_alloc;
3018 (void)rte_memcpy(&vsi->info, &ctxt.info,
3019 sizeof(struct i40e_aqc_vsi_properties_data));
3020 vsi->vsi_id = ctxt.vsi_number;
3021 vsi->info.valid_sections = 0;
3023 /* Configure tc, enabled TC0 only */
3024 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3026 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3027 goto fail_msix_alloc;
3030 /* TC, queue mapping */
3031 memset(&ctxt, 0, sizeof(ctxt));
3032 vsi->info.valid_sections |=
3033 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3034 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3035 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3036 (void)rte_memcpy(&ctxt.info, &vsi->info,
3037 sizeof(struct i40e_aqc_vsi_properties_data));
3038 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3039 I40E_DEFAULT_TCMAP);
3040 if (ret != I40E_SUCCESS) {
3041 PMD_DRV_LOG(ERR, "Failed to configure "
3042 "TC queue mapping");
3043 goto fail_msix_alloc;
3045 ctxt.seid = vsi->seid;
3046 ctxt.pf_num = hw->pf_id;
3047 ctxt.uplink_seid = vsi->uplink_seid;
3050 /* Update VSI parameters */
3051 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3052 if (ret != I40E_SUCCESS) {
3053 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3054 goto fail_msix_alloc;
3057 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3058 sizeof(vsi->info.tc_mapping));
3059 (void)rte_memcpy(&vsi->info.queue_mapping,
3060 &ctxt.info.queue_mapping,
3061 sizeof(vsi->info.queue_mapping));
3062 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3063 vsi->info.valid_sections = 0;
3065 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3069 * Updating default filter settings are necessary to prevent
3070 * reception of tagged packets.
3071 * Some old firmware configurations load a default macvlan
3072 * filter which accepts both tagged and untagged packets.
3073 * The updating is to use a normal filter instead if needed.
3074 * For NVM 4.2.2 or after, the updating is not needed anymore.
3075 * The firmware with correct configurations load the default
3076 * macvlan filter which is expected and cannot be removed.
3078 i40e_update_default_filter_setting(vsi);
3079 i40e_config_qinq(hw, vsi);
3080 } else if (type == I40E_VSI_SRIOV) {
3081 memset(&ctxt, 0, sizeof(ctxt));
3083 * For other VSI, the uplink_seid equals to uplink VSI's
3084 * uplink_seid since they share same VEB
3086 vsi->uplink_seid = uplink_vsi->uplink_seid;
3087 ctxt.pf_num = hw->pf_id;
3088 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3089 ctxt.uplink_seid = vsi->uplink_seid;
3090 ctxt.connection_type = 0x1;
3091 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3094 * Do not configure switch ID to enable VEB switch by
3095 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3096 * if the source mac address of packet sent from VF is not
3097 * listed in the VEB's mac table, the VEB will switch the
3098 * packet back to the VF. Need to enable it when HW issue
3102 /* Configure port/vlan */
3103 ctxt.info.valid_sections |=
3104 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3105 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3106 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3107 I40E_DEFAULT_TCMAP);
3108 if (ret != I40E_SUCCESS) {
3109 PMD_DRV_LOG(ERR, "Failed to configure "
3110 "TC queue mapping");
3111 goto fail_msix_alloc;
3113 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3114 ctxt.info.valid_sections |=
3115 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3117 * Since VSI is not created yet, only configure parameter,
3118 * will add vsi below.
3121 i40e_config_qinq(hw, vsi);
3122 } else if (type == I40E_VSI_VMDQ2) {
3123 memset(&ctxt, 0, sizeof(ctxt));
3125 * For other VSI, the uplink_seid equals to uplink VSI's
3126 * uplink_seid since they share same VEB
3128 vsi->uplink_seid = uplink_vsi->uplink_seid;
3129 ctxt.pf_num = hw->pf_id;
3131 ctxt.uplink_seid = vsi->uplink_seid;
3132 ctxt.connection_type = 0x1;
3133 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3135 ctxt.info.valid_sections |=
3136 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3137 /* user_param carries flag to enable loop back */
3139 ctxt.info.switch_id =
3140 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3141 ctxt.info.switch_id |=
3142 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3145 /* Configure port/vlan */
3146 ctxt.info.valid_sections |=
3147 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3148 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3149 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3150 I40E_DEFAULT_TCMAP);
3151 if (ret != I40E_SUCCESS) {
3152 PMD_DRV_LOG(ERR, "Failed to configure "
3153 "TC queue mapping");
3154 goto fail_msix_alloc;
3156 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3157 ctxt.info.valid_sections |=
3158 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3159 } else if (type == I40E_VSI_FDIR) {
3160 memset(&ctxt, 0, sizeof(ctxt));
3161 vsi->uplink_seid = uplink_vsi->uplink_seid;
3162 ctxt.pf_num = hw->pf_id;
3164 ctxt.uplink_seid = vsi->uplink_seid;
3165 ctxt.connection_type = 0x1; /* regular data port */
3166 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3167 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3168 I40E_DEFAULT_TCMAP);
3169 if (ret != I40E_SUCCESS) {
3170 PMD_DRV_LOG(ERR, "Failed to configure "
3171 "TC queue mapping.");
3172 goto fail_msix_alloc;
3174 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3175 ctxt.info.valid_sections |=
3176 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3178 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3179 goto fail_msix_alloc;
3182 if (vsi->type != I40E_VSI_MAIN) {
3183 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3184 if (ret != I40E_SUCCESS) {
3185 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3186 hw->aq.asq_last_status);
3187 goto fail_msix_alloc;
3189 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3190 vsi->info.valid_sections = 0;
3191 vsi->seid = ctxt.seid;
3192 vsi->vsi_id = ctxt.vsi_number;
3193 vsi->sib_vsi_list.vsi = vsi;
3194 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3195 &vsi->sib_vsi_list, list);
3198 /* MAC/VLAN configuration */
3199 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3200 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3202 ret = i40e_vsi_add_mac(vsi, &filter);
3203 if (ret != I40E_SUCCESS) {
3204 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3205 goto fail_msix_alloc;
3208 /* Get VSI BW information */
3209 i40e_vsi_dump_bw_config(vsi);
3212 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3214 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3220 /* Configure vlan stripping on or off */
3222 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3224 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3225 struct i40e_vsi_context ctxt;
3227 int ret = I40E_SUCCESS;
3229 /* Check if it has been already on or off */
3230 if (vsi->info.valid_sections &
3231 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3233 if ((vsi->info.port_vlan_flags &
3234 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3235 return 0; /* already on */
3237 if ((vsi->info.port_vlan_flags &
3238 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3239 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3240 return 0; /* already off */
3245 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3247 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3248 vsi->info.valid_sections =
3249 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3250 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3251 vsi->info.port_vlan_flags |= vlan_flags;
3252 ctxt.seid = vsi->seid;
3253 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3254 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3256 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3257 on ? "enable" : "disable");
3263 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3265 struct rte_eth_dev_data *data = dev->data;
3268 /* Apply vlan offload setting */
3269 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3271 /* Apply double-vlan setting, not implemented yet */
3273 /* Apply pvid setting */
3274 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3275 data->dev_conf.txmode.hw_vlan_insert_pvid);
3277 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3283 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3285 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3287 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3291 i40e_update_flow_control(struct i40e_hw *hw)
3293 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3294 struct i40e_link_status link_status;
3295 uint32_t rxfc = 0, txfc = 0, reg;
3299 memset(&link_status, 0, sizeof(link_status));
3300 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3301 if (ret != I40E_SUCCESS) {
3302 PMD_DRV_LOG(ERR, "Failed to get link status information");
3303 goto write_reg; /* Disable flow control */
3306 an_info = hw->phy.link_info.an_info;
3307 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3308 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3309 ret = I40E_ERR_NOT_READY;
3310 goto write_reg; /* Disable flow control */
3313 * If link auto negotiation is enabled, flow control needs to
3314 * be configured according to it
3316 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3317 case I40E_LINK_PAUSE_RXTX:
3320 hw->fc.current_mode = I40E_FC_FULL;
3322 case I40E_AQ_LINK_PAUSE_RX:
3324 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3326 case I40E_AQ_LINK_PAUSE_TX:
3328 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3331 hw->fc.current_mode = I40E_FC_NONE;
3336 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3337 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3338 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3339 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3340 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3341 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3348 i40e_pf_setup(struct i40e_pf *pf)
3350 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3351 struct i40e_filter_control_settings settings;
3352 struct i40e_vsi *vsi;
3355 /* Clear all stats counters */
3356 pf->offset_loaded = FALSE;
3357 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3358 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3360 ret = i40e_pf_get_switch_config(pf);
3361 if (ret != I40E_SUCCESS) {
3362 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3365 if (pf->flags & I40E_FLAG_FDIR) {
3366 /* make queue allocated first, let FDIR use queue pair 0*/
3367 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3368 if (ret != I40E_FDIR_QUEUE_ID) {
3369 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3371 pf->flags &= ~I40E_FLAG_FDIR;
3374 /* main VSI setup */
3375 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3377 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3378 return I40E_ERR_NOT_READY;
3382 /* Configure filter control */
3383 memset(&settings, 0, sizeof(settings));
3384 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3385 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3386 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3387 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3389 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3390 hw->func_caps.rss_table_size);
3391 return I40E_ERR_PARAM;
3393 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3394 "size: %u\n", hw->func_caps.rss_table_size);
3395 pf->hash_lut_size = hw->func_caps.rss_table_size;
3397 /* Enable ethtype and macvlan filters */
3398 settings.enable_ethtype = TRUE;
3399 settings.enable_macvlan = TRUE;
3400 ret = i40e_set_filter_control(hw, &settings);
3402 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3405 /* Update flow control according to the auto negotiation */
3406 i40e_update_flow_control(hw);
3408 return I40E_SUCCESS;
3412 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3418 * Set or clear TX Queue Disable flags,
3419 * which is required by hardware.
3421 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3422 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3424 /* Wait until the request is finished */
3425 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3426 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3427 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3428 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3429 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3435 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3436 return I40E_SUCCESS; /* already on, skip next steps */
3438 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3439 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3441 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3442 return I40E_SUCCESS; /* already off, skip next steps */
3443 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3445 /* Write the register */
3446 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3447 /* Check the result */
3448 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3449 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3450 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3452 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3453 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3456 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3457 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3461 /* Check if it is timeout */
3462 if (j >= I40E_CHK_Q_ENA_COUNT) {
3463 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3464 (on ? "enable" : "disable"), q_idx);
3465 return I40E_ERR_TIMEOUT;
3468 return I40E_SUCCESS;
3471 /* Swith on or off the tx queues */
3473 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3475 struct rte_eth_dev_data *dev_data = pf->dev_data;
3476 struct i40e_tx_queue *txq;
3477 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3481 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3482 txq = dev_data->tx_queues[i];
3483 /* Don't operate the queue if not configured or
3484 * if starting only per queue */
3485 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3488 ret = i40e_dev_tx_queue_start(dev, i);
3490 ret = i40e_dev_tx_queue_stop(dev, i);
3491 if ( ret != I40E_SUCCESS)
3495 return I40E_SUCCESS;
3499 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3504 /* Wait until the request is finished */
3505 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3506 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3507 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3508 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3509 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3514 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3515 return I40E_SUCCESS; /* Already on, skip next steps */
3516 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3518 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3519 return I40E_SUCCESS; /* Already off, skip next steps */
3520 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3523 /* Write the register */
3524 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3525 /* Check the result */
3526 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3527 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3528 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3530 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3531 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3534 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3535 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3540 /* Check if it is timeout */
3541 if (j >= I40E_CHK_Q_ENA_COUNT) {
3542 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3543 (on ? "enable" : "disable"), q_idx);
3544 return I40E_ERR_TIMEOUT;
3547 return I40E_SUCCESS;
3549 /* Switch on or off the rx queues */
3551 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3553 struct rte_eth_dev_data *dev_data = pf->dev_data;
3554 struct i40e_rx_queue *rxq;
3555 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3559 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3560 rxq = dev_data->rx_queues[i];
3561 /* Don't operate the queue if not configured or
3562 * if starting only per queue */
3563 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3566 ret = i40e_dev_rx_queue_start(dev, i);
3568 ret = i40e_dev_rx_queue_stop(dev, i);
3569 if (ret != I40E_SUCCESS)
3573 return I40E_SUCCESS;
3576 /* Switch on or off all the rx/tx queues */
3578 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3583 /* enable rx queues before enabling tx queues */
3584 ret = i40e_dev_switch_rx_queues(pf, on);
3586 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3589 ret = i40e_dev_switch_tx_queues(pf, on);
3591 /* Stop tx queues before stopping rx queues */
3592 ret = i40e_dev_switch_tx_queues(pf, on);
3594 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3597 ret = i40e_dev_switch_rx_queues(pf, on);
3603 /* Initialize VSI for TX */
3605 i40e_dev_tx_init(struct i40e_pf *pf)
3607 struct rte_eth_dev_data *data = pf->dev_data;
3609 uint32_t ret = I40E_SUCCESS;
3610 struct i40e_tx_queue *txq;
3612 for (i = 0; i < data->nb_tx_queues; i++) {
3613 txq = data->tx_queues[i];
3614 if (!txq || !txq->q_set)
3616 ret = i40e_tx_queue_init(txq);
3617 if (ret != I40E_SUCCESS)
3624 /* Initialize VSI for RX */
3626 i40e_dev_rx_init(struct i40e_pf *pf)
3628 struct rte_eth_dev_data *data = pf->dev_data;
3629 int ret = I40E_SUCCESS;
3631 struct i40e_rx_queue *rxq;
3633 i40e_pf_config_mq_rx(pf);
3634 for (i = 0; i < data->nb_rx_queues; i++) {
3635 rxq = data->rx_queues[i];
3636 if (!rxq || !rxq->q_set)
3639 ret = i40e_rx_queue_init(rxq);
3640 if (ret != I40E_SUCCESS) {
3641 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3651 i40e_dev_rxtx_init(struct i40e_pf *pf)
3655 err = i40e_dev_tx_init(pf);
3657 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3660 err = i40e_dev_rx_init(pf);
3662 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3670 i40e_vmdq_setup(struct rte_eth_dev *dev)
3672 struct rte_eth_conf *conf = &dev->data->dev_conf;
3673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3674 int i, err, conf_vsis, j, loop;
3675 struct i40e_vsi *vsi;
3676 struct i40e_vmdq_info *vmdq_info;
3677 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3678 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3681 * Disable interrupt to avoid message from VF. Furthermore, it will
3682 * avoid race condition in VSI creation/destroy.
3684 i40e_pf_disable_irq0(hw);
3686 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3687 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3691 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3692 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3693 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3694 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3695 pf->max_nb_vmdq_vsi);
3699 if (pf->vmdq != NULL) {
3700 PMD_INIT_LOG(INFO, "VMDQ already configured");
3704 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3705 sizeof(*vmdq_info) * conf_vsis, 0);
3707 if (pf->vmdq == NULL) {
3708 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3712 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3714 /* Create VMDQ VSI */
3715 for (i = 0; i < conf_vsis; i++) {
3716 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3717 vmdq_conf->enable_loop_back);
3719 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3723 vmdq_info = &pf->vmdq[i];
3725 vmdq_info->vsi = vsi;
3727 pf->nb_cfg_vmdq_vsi = conf_vsis;
3729 /* Configure Vlan */
3730 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3731 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3732 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3733 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3734 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3735 vmdq_conf->pool_map[i].vlan_id, j);
3737 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3738 vmdq_conf->pool_map[i].vlan_id);
3740 PMD_INIT_LOG(ERR, "Failed to add vlan");
3748 i40e_pf_enable_irq0(hw);
3753 for (i = 0; i < conf_vsis; i++)
3754 if (pf->vmdq[i].vsi == NULL)
3757 i40e_vsi_release(pf->vmdq[i].vsi);
3761 i40e_pf_enable_irq0(hw);
3766 i40e_stat_update_32(struct i40e_hw *hw,
3774 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3778 if (new_data >= *offset)
3779 *stat = (uint64_t)(new_data - *offset);
3781 *stat = (uint64_t)((new_data +
3782 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3786 i40e_stat_update_48(struct i40e_hw *hw,
3795 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3796 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3797 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3802 if (new_data >= *offset)
3803 *stat = new_data - *offset;
3805 *stat = (uint64_t)((new_data +
3806 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3808 *stat &= I40E_48_BIT_MASK;
3813 i40e_pf_disable_irq0(struct i40e_hw *hw)
3815 /* Disable all interrupt types */
3816 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3817 I40E_WRITE_FLUSH(hw);
3822 i40e_pf_enable_irq0(struct i40e_hw *hw)
3824 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3825 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3826 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3827 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3828 I40E_WRITE_FLUSH(hw);
3832 i40e_pf_config_irq0(struct i40e_hw *hw)
3834 /* read pending request and disable first */
3835 i40e_pf_disable_irq0(hw);
3836 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3837 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3838 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3840 /* Link no queues with irq0 */
3841 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3842 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3846 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3848 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3852 uint32_t index, offset, val;
3857 * Try to find which VF trigger a reset, use absolute VF id to access
3858 * since the reg is global register.
3860 for (i = 0; i < pf->vf_num; i++) {
3861 abs_vf_id = hw->func_caps.vf_base_id + i;
3862 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3863 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3864 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3865 /* VFR event occured */
3866 if (val & (0x1 << offset)) {
3869 /* Clear the event first */
3870 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3872 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3874 * Only notify a VF reset event occured,
3875 * don't trigger another SW reset
3877 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3878 if (ret != I40E_SUCCESS)
3879 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3885 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888 struct i40e_arq_event_info info;
3889 uint16_t pending, opcode;
3892 info.buf_len = I40E_AQ_BUF_SZ;
3893 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3894 if (!info.msg_buf) {
3895 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3901 ret = i40e_clean_arq_element(hw, &info, &pending);
3903 if (ret != I40E_SUCCESS) {
3904 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3905 "aq_err: %u", hw->aq.asq_last_status);
3908 opcode = rte_le_to_cpu_16(info.desc.opcode);
3911 case i40e_aqc_opc_send_msg_to_pf:
3912 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3913 i40e_pf_host_handle_vf_msg(dev,
3914 rte_le_to_cpu_16(info.desc.retval),
3915 rte_le_to_cpu_32(info.desc.cookie_high),
3916 rte_le_to_cpu_32(info.desc.cookie_low),
3921 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3926 rte_free(info.msg_buf);
3930 * Interrupt handler is registered as the alarm callback for handling LSC
3931 * interrupt in a definite of time, in order to wait the NIC into a stable
3932 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3933 * no need for link down interrupt.
3936 i40e_dev_interrupt_delayed_handler(void *param)
3938 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3942 /* read interrupt causes again */
3943 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3945 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3946 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3947 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3948 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3949 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3950 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3951 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3952 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3953 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3954 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3955 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3957 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3958 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3959 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3960 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3961 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3963 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3964 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3965 i40e_dev_handle_vfr_event(dev);
3967 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3968 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3969 i40e_dev_handle_aq_msg(dev);
3972 /* handle the link up interrupt in an alarm callback */
3973 i40e_dev_link_update(dev, 0);
3974 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3976 i40e_pf_enable_irq0(hw);
3977 rte_intr_enable(&(dev->pci_dev->intr_handle));
3981 * Interrupt handler triggered by NIC for handling
3982 * specific interrupt.
3985 * Pointer to interrupt handle.
3987 * The address of parameter (struct rte_eth_dev *) regsitered before.
3993 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3996 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3997 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000 /* Disable interrupt */
4001 i40e_pf_disable_irq0(hw);
4003 /* read out interrupt causes */
4004 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4006 /* No interrupt event indicated */
4007 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4008 PMD_DRV_LOG(INFO, "No interrupt event");
4011 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4012 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4013 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4014 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4015 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4016 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4017 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4018 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4019 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4020 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4021 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4022 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4023 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4024 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4025 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4026 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4028 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4029 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4030 i40e_dev_handle_vfr_event(dev);
4032 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4033 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4034 i40e_dev_handle_aq_msg(dev);
4037 /* Link Status Change interrupt */
4038 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4039 #define I40E_US_PER_SECOND 1000000
4040 struct rte_eth_link link;
4042 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4043 memset(&link, 0, sizeof(link));
4044 rte_i40e_dev_atomic_read_link_status(dev, &link);
4045 i40e_dev_link_update(dev, 0);
4048 * For link up interrupt, it needs to wait 1 second to let the
4049 * hardware be a stable state. Otherwise several consecutive
4050 * interrupts can be observed.
4051 * For link down interrupt, no need to wait.
4053 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4054 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4057 _rte_eth_dev_callback_process(dev,
4058 RTE_ETH_EVENT_INTR_LSC);
4062 /* Enable interrupt */
4063 i40e_pf_enable_irq0(hw);
4064 rte_intr_enable(&(dev->pci_dev->intr_handle));
4068 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4069 struct i40e_macvlan_filter *filter,
4072 int ele_num, ele_buff_size;
4073 int num, actual_num, i;
4075 int ret = I40E_SUCCESS;
4076 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4077 struct i40e_aqc_add_macvlan_element_data *req_list;
4079 if (filter == NULL || total == 0)
4080 return I40E_ERR_PARAM;
4081 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4082 ele_buff_size = hw->aq.asq_buf_size;
4084 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4085 if (req_list == NULL) {
4086 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4087 return I40E_ERR_NO_MEMORY;
4092 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4093 memset(req_list, 0, ele_buff_size);
4095 for (i = 0; i < actual_num; i++) {
4096 (void)rte_memcpy(req_list[i].mac_addr,
4097 &filter[num + i].macaddr, ETH_ADDR_LEN);
4098 req_list[i].vlan_tag =
4099 rte_cpu_to_le_16(filter[num + i].vlan_id);
4101 switch (filter[num + i].filter_type) {
4102 case RTE_MAC_PERFECT_MATCH:
4103 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4104 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4106 case RTE_MACVLAN_PERFECT_MATCH:
4107 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4109 case RTE_MAC_HASH_MATCH:
4110 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4111 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4113 case RTE_MACVLAN_HASH_MATCH:
4114 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4117 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4118 ret = I40E_ERR_PARAM;
4122 req_list[i].queue_number = 0;
4124 req_list[i].flags = rte_cpu_to_le_16(flags);
4127 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4129 if (ret != I40E_SUCCESS) {
4130 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4134 } while (num < total);
4142 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4143 struct i40e_macvlan_filter *filter,
4146 int ele_num, ele_buff_size;
4147 int num, actual_num, i;
4149 int ret = I40E_SUCCESS;
4150 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4151 struct i40e_aqc_remove_macvlan_element_data *req_list;
4153 if (filter == NULL || total == 0)
4154 return I40E_ERR_PARAM;
4156 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4157 ele_buff_size = hw->aq.asq_buf_size;
4159 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4160 if (req_list == NULL) {
4161 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4162 return I40E_ERR_NO_MEMORY;
4167 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4168 memset(req_list, 0, ele_buff_size);
4170 for (i = 0; i < actual_num; i++) {
4171 (void)rte_memcpy(req_list[i].mac_addr,
4172 &filter[num + i].macaddr, ETH_ADDR_LEN);
4173 req_list[i].vlan_tag =
4174 rte_cpu_to_le_16(filter[num + i].vlan_id);
4176 switch (filter[num + i].filter_type) {
4177 case RTE_MAC_PERFECT_MATCH:
4178 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4179 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4181 case RTE_MACVLAN_PERFECT_MATCH:
4182 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4184 case RTE_MAC_HASH_MATCH:
4185 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4186 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4188 case RTE_MACVLAN_HASH_MATCH:
4189 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4192 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4193 ret = I40E_ERR_PARAM;
4196 req_list[i].flags = rte_cpu_to_le_16(flags);
4199 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4201 if (ret != I40E_SUCCESS) {
4202 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4206 } while (num < total);
4213 /* Find out specific MAC filter */
4214 static struct i40e_mac_filter *
4215 i40e_find_mac_filter(struct i40e_vsi *vsi,
4216 struct ether_addr *macaddr)
4218 struct i40e_mac_filter *f;
4220 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4221 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4229 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4232 uint32_t vid_idx, vid_bit;
4234 if (vlan_id > ETH_VLAN_ID_MAX)
4237 vid_idx = I40E_VFTA_IDX(vlan_id);
4238 vid_bit = I40E_VFTA_BIT(vlan_id);
4240 if (vsi->vfta[vid_idx] & vid_bit)
4247 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4248 uint16_t vlan_id, bool on)
4250 uint32_t vid_idx, vid_bit;
4252 if (vlan_id > ETH_VLAN_ID_MAX)
4255 vid_idx = I40E_VFTA_IDX(vlan_id);
4256 vid_bit = I40E_VFTA_BIT(vlan_id);
4259 vsi->vfta[vid_idx] |= vid_bit;
4261 vsi->vfta[vid_idx] &= ~vid_bit;
4265 * Find all vlan options for specific mac addr,
4266 * return with actual vlan found.
4269 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4270 struct i40e_macvlan_filter *mv_f,
4271 int num, struct ether_addr *addr)
4277 * Not to use i40e_find_vlan_filter to decrease the loop time,
4278 * although the code looks complex.
4280 if (num < vsi->vlan_num)
4281 return I40E_ERR_PARAM;
4284 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4286 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4287 if (vsi->vfta[j] & (1 << k)) {
4289 PMD_DRV_LOG(ERR, "vlan number "
4291 return I40E_ERR_PARAM;
4293 (void)rte_memcpy(&mv_f[i].macaddr,
4294 addr, ETH_ADDR_LEN);
4296 j * I40E_UINT32_BIT_SIZE + k;
4302 return I40E_SUCCESS;
4306 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4307 struct i40e_macvlan_filter *mv_f,
4312 struct i40e_mac_filter *f;
4314 if (num < vsi->mac_num)
4315 return I40E_ERR_PARAM;
4317 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4319 PMD_DRV_LOG(ERR, "buffer number not match");
4320 return I40E_ERR_PARAM;
4322 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4324 mv_f[i].vlan_id = vlan;
4325 mv_f[i].filter_type = f->mac_info.filter_type;
4329 return I40E_SUCCESS;
4333 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4336 struct i40e_mac_filter *f;
4337 struct i40e_macvlan_filter *mv_f;
4338 int ret = I40E_SUCCESS;
4340 if (vsi == NULL || vsi->mac_num == 0)
4341 return I40E_ERR_PARAM;
4343 /* Case that no vlan is set */
4344 if (vsi->vlan_num == 0)
4347 num = vsi->mac_num * vsi->vlan_num;
4349 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4351 PMD_DRV_LOG(ERR, "failed to allocate memory");
4352 return I40E_ERR_NO_MEMORY;
4356 if (vsi->vlan_num == 0) {
4357 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4358 (void)rte_memcpy(&mv_f[i].macaddr,
4359 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4360 mv_f[i].vlan_id = 0;
4364 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4365 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4366 vsi->vlan_num, &f->mac_info.mac_addr);
4367 if (ret != I40E_SUCCESS)
4373 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4381 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4383 struct i40e_macvlan_filter *mv_f;
4385 int ret = I40E_SUCCESS;
4387 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4388 return I40E_ERR_PARAM;
4390 /* If it's already set, just return */
4391 if (i40e_find_vlan_filter(vsi,vlan))
4392 return I40E_SUCCESS;
4394 mac_num = vsi->mac_num;
4397 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4398 return I40E_ERR_PARAM;
4401 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4404 PMD_DRV_LOG(ERR, "failed to allocate memory");
4405 return I40E_ERR_NO_MEMORY;
4408 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4410 if (ret != I40E_SUCCESS)
4413 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4415 if (ret != I40E_SUCCESS)
4418 i40e_set_vlan_filter(vsi, vlan, 1);
4428 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4430 struct i40e_macvlan_filter *mv_f;
4432 int ret = I40E_SUCCESS;
4435 * Vlan 0 is the generic filter for untagged packets
4436 * and can't be removed.
4438 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4439 return I40E_ERR_PARAM;
4441 /* If can't find it, just return */
4442 if (!i40e_find_vlan_filter(vsi, vlan))
4443 return I40E_ERR_PARAM;
4445 mac_num = vsi->mac_num;
4448 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4449 return I40E_ERR_PARAM;
4452 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4455 PMD_DRV_LOG(ERR, "failed to allocate memory");
4456 return I40E_ERR_NO_MEMORY;
4459 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4461 if (ret != I40E_SUCCESS)
4464 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4466 if (ret != I40E_SUCCESS)
4469 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4470 if (vsi->vlan_num == 1) {
4471 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4472 if (ret != I40E_SUCCESS)
4475 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4476 if (ret != I40E_SUCCESS)
4480 i40e_set_vlan_filter(vsi, vlan, 0);
4490 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4492 struct i40e_mac_filter *f;
4493 struct i40e_macvlan_filter *mv_f;
4494 int i, vlan_num = 0;
4495 int ret = I40E_SUCCESS;
4497 /* If it's add and we've config it, return */
4498 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4500 return I40E_SUCCESS;
4501 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4502 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4505 * If vlan_num is 0, that's the first time to add mac,
4506 * set mask for vlan_id 0.
4508 if (vsi->vlan_num == 0) {
4509 i40e_set_vlan_filter(vsi, 0, 1);
4512 vlan_num = vsi->vlan_num;
4513 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4514 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4517 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4519 PMD_DRV_LOG(ERR, "failed to allocate memory");
4520 return I40E_ERR_NO_MEMORY;
4523 for (i = 0; i < vlan_num; i++) {
4524 mv_f[i].filter_type = mac_filter->filter_type;
4525 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4529 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4530 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4531 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4532 &mac_filter->mac_addr);
4533 if (ret != I40E_SUCCESS)
4537 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4538 if (ret != I40E_SUCCESS)
4541 /* Add the mac addr into mac list */
4542 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4544 PMD_DRV_LOG(ERR, "failed to allocate memory");
4545 ret = I40E_ERR_NO_MEMORY;
4548 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4550 f->mac_info.filter_type = mac_filter->filter_type;
4551 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4562 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4564 struct i40e_mac_filter *f;
4565 struct i40e_macvlan_filter *mv_f;
4567 enum rte_mac_filter_type filter_type;
4568 int ret = I40E_SUCCESS;
4570 /* Can't find it, return an error */
4571 f = i40e_find_mac_filter(vsi, addr);
4573 return I40E_ERR_PARAM;
4575 vlan_num = vsi->vlan_num;
4576 filter_type = f->mac_info.filter_type;
4577 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4578 filter_type == RTE_MACVLAN_HASH_MATCH) {
4579 if (vlan_num == 0) {
4580 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4581 return I40E_ERR_PARAM;
4583 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4584 filter_type == RTE_MAC_HASH_MATCH)
4587 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4589 PMD_DRV_LOG(ERR, "failed to allocate memory");
4590 return I40E_ERR_NO_MEMORY;
4593 for (i = 0; i < vlan_num; i++) {
4594 mv_f[i].filter_type = filter_type;
4595 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4598 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4599 filter_type == RTE_MACVLAN_HASH_MATCH) {
4600 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4601 if (ret != I40E_SUCCESS)
4605 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4606 if (ret != I40E_SUCCESS)
4609 /* Remove the mac addr into mac list */
4610 TAILQ_REMOVE(&vsi->mac_list, f, next);
4620 /* Configure hash enable flags for RSS */
4622 i40e_config_hena(uint64_t flags)
4629 if (flags & ETH_RSS_FRAG_IPV4)
4630 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4631 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4632 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4633 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4634 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4635 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4636 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4637 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4638 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4639 if (flags & ETH_RSS_FRAG_IPV6)
4640 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4641 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4642 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4643 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4644 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4645 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4646 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4647 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4648 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4649 if (flags & ETH_RSS_L2_PAYLOAD)
4650 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4655 /* Parse the hash enable flags */
4657 i40e_parse_hena(uint64_t flags)
4659 uint64_t rss_hf = 0;
4663 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4664 rss_hf |= ETH_RSS_FRAG_IPV4;
4665 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4666 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4667 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4668 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4669 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4670 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4671 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4672 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4673 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4674 rss_hf |= ETH_RSS_FRAG_IPV6;
4675 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4676 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4677 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4678 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4679 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4680 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4681 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4682 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4683 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4684 rss_hf |= ETH_RSS_L2_PAYLOAD;
4691 i40e_pf_disable_rss(struct i40e_pf *pf)
4693 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4696 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4697 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4698 hena &= ~I40E_RSS_HENA_ALL;
4699 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4700 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4701 I40E_WRITE_FLUSH(hw);
4705 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4708 uint8_t hash_key_len;
4713 hash_key = (uint32_t *)(rss_conf->rss_key);
4714 hash_key_len = rss_conf->rss_key_len;
4715 if (hash_key != NULL && hash_key_len >=
4716 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4717 /* Fill in RSS hash key */
4718 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4719 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4722 rss_hf = rss_conf->rss_hf;
4723 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4724 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4725 hena &= ~I40E_RSS_HENA_ALL;
4726 hena |= i40e_config_hena(rss_hf);
4727 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4728 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4729 I40E_WRITE_FLUSH(hw);
4735 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4736 struct rte_eth_rss_conf *rss_conf)
4738 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4742 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4743 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4744 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4745 if (rss_hf != 0) /* Enable RSS */
4747 return 0; /* Nothing to do */
4750 if (rss_hf == 0) /* Disable RSS */
4753 return i40e_hw_rss_hash_set(hw, rss_conf);
4757 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4758 struct rte_eth_rss_conf *rss_conf)
4760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4765 if (hash_key != NULL) {
4766 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4767 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4768 rss_conf->rss_key_len = i * sizeof(uint32_t);
4770 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4771 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4772 rss_conf->rss_hf = i40e_parse_hena(hena);
4778 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4780 switch (filter_type) {
4781 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4782 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4784 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4785 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4787 case RTE_TUNNEL_FILTER_IMAC_TENID:
4788 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4790 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4791 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4793 case ETH_TUNNEL_FILTER_IMAC:
4794 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4797 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4805 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4806 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4810 uint8_t tun_type = 0;
4812 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4813 struct i40e_vsi *vsi = pf->main_vsi;
4814 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4815 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4817 cld_filter = rte_zmalloc("tunnel_filter",
4818 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4821 if (NULL == cld_filter) {
4822 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4825 pfilter = cld_filter;
4827 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4828 sizeof(struct ether_addr));
4829 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4830 sizeof(struct ether_addr));
4832 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4833 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4834 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4835 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4836 &tunnel_filter->ip_addr,
4837 sizeof(pfilter->ipaddr.v4.data));
4839 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4840 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4841 &tunnel_filter->ip_addr,
4842 sizeof(pfilter->ipaddr.v6.data));
4845 /* check tunneled type */
4846 switch (tunnel_filter->tunnel_type) {
4847 case RTE_TUNNEL_TYPE_VXLAN:
4848 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4850 case RTE_TUNNEL_TYPE_NVGRE:
4851 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4854 /* Other tunnel types is not supported. */
4855 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4856 rte_free(cld_filter);
4860 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4863 rte_free(cld_filter);
4867 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4868 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4869 pfilter->tenant_id = tunnel_filter->tenant_id;
4870 pfilter->queue_number = tunnel_filter->queue_id;
4873 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4875 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4878 rte_free(cld_filter);
4883 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4887 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4888 if (pf->vxlan_ports[i] == port)
4896 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4900 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4902 idx = i40e_get_vxlan_port_idx(pf, port);
4904 /* Check if port already exists */
4906 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4910 /* Now check if there is space to add the new port */
4911 idx = i40e_get_vxlan_port_idx(pf, 0);
4913 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4914 "not adding port %d", port);
4918 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4921 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4925 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4928 /* New port: add it and mark its index in the bitmap */
4929 pf->vxlan_ports[idx] = port;
4930 pf->vxlan_bitmap |= (1 << idx);
4932 if (!(pf->flags & I40E_FLAG_VXLAN))
4933 pf->flags |= I40E_FLAG_VXLAN;
4939 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4942 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4944 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4945 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4949 idx = i40e_get_vxlan_port_idx(pf, port);
4952 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4956 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4957 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4961 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4964 pf->vxlan_ports[idx] = 0;
4965 pf->vxlan_bitmap &= ~(1 << idx);
4967 if (!pf->vxlan_bitmap)
4968 pf->flags &= ~I40E_FLAG_VXLAN;
4973 /* Add UDP tunneling port */
4975 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4976 struct rte_eth_udp_tunnel *udp_tunnel)
4979 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4981 if (udp_tunnel == NULL)
4984 switch (udp_tunnel->prot_type) {
4985 case RTE_TUNNEL_TYPE_VXLAN:
4986 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4989 case RTE_TUNNEL_TYPE_GENEVE:
4990 case RTE_TUNNEL_TYPE_TEREDO:
4991 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4996 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5004 /* Remove UDP tunneling port */
5006 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5007 struct rte_eth_udp_tunnel *udp_tunnel)
5010 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5012 if (udp_tunnel == NULL)
5015 switch (udp_tunnel->prot_type) {
5016 case RTE_TUNNEL_TYPE_VXLAN:
5017 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5019 case RTE_TUNNEL_TYPE_GENEVE:
5020 case RTE_TUNNEL_TYPE_TEREDO:
5021 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5025 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5033 /* Calculate the maximum number of contiguous PF queues that are configured */
5035 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5037 struct rte_eth_dev_data *data = pf->dev_data;
5039 struct i40e_rx_queue *rxq;
5042 for (i = 0; i < pf->lan_nb_qps; i++) {
5043 rxq = data->rx_queues[i];
5044 if (rxq && rxq->q_set)
5055 i40e_pf_config_rss(struct i40e_pf *pf)
5057 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5058 struct rte_eth_rss_conf rss_conf;
5059 uint32_t i, lut = 0;
5063 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5064 * It's necessary to calulate the actual PF queues that are configured.
5066 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5067 num = i40e_pf_calc_configured_queues_num(pf);
5068 num = i40e_align_floor(num);
5070 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5072 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5076 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5080 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5083 lut = (lut << 8) | (j & ((0x1 <<
5084 hw->func_caps.rss_table_entry_width) - 1));
5086 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5089 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5090 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5091 i40e_pf_disable_rss(pf);
5094 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5095 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5096 /* Random default keys */
5097 static uint32_t rss_key_default[] = {0x6b793944,
5098 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5099 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5100 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5102 rss_conf.rss_key = (uint8_t *)rss_key_default;
5103 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5107 return i40e_hw_rss_hash_set(hw, &rss_conf);
5111 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5112 struct rte_eth_tunnel_filter_conf *filter)
5114 if (pf == NULL || filter == NULL) {
5115 PMD_DRV_LOG(ERR, "Invalid parameter");
5119 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5120 PMD_DRV_LOG(ERR, "Invalid queue ID");
5124 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5125 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5129 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5130 (is_zero_ether_addr(filter->outer_mac))) {
5131 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5135 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5136 (is_zero_ether_addr(filter->inner_mac))) {
5137 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5145 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5148 struct rte_eth_tunnel_filter_conf *filter;
5149 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5150 int ret = I40E_SUCCESS;
5152 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5154 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5155 return I40E_ERR_PARAM;
5157 switch (filter_op) {
5158 case RTE_ETH_FILTER_NOP:
5159 if (!(pf->flags & I40E_FLAG_VXLAN))
5160 ret = I40E_NOT_SUPPORTED;
5161 case RTE_ETH_FILTER_ADD:
5162 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5164 case RTE_ETH_FILTER_DELETE:
5165 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5168 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5169 ret = I40E_ERR_PARAM;
5177 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5180 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5182 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5183 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5188 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5189 ret = i40e_pf_config_rss(pf);
5191 i40e_pf_disable_rss(pf);
5196 /* Get the symmetric hash enable configurations per port */
5198 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5200 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5202 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5205 /* Set the symmetric hash enable configurations per port */
5207 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5209 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5212 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5213 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5217 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5219 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5220 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5224 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5226 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5227 I40E_WRITE_FLUSH(hw);
5231 * Get global configurations of hash function type and symmetric hash enable
5232 * per flow type (pctype). Note that global configuration means it affects all
5233 * the ports on the same NIC.
5236 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5237 struct rte_eth_hash_global_conf *g_cfg)
5239 uint32_t reg, mask = I40E_FLOW_TYPES;
5241 enum i40e_filter_pctype pctype;
5243 memset(g_cfg, 0, sizeof(*g_cfg));
5244 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5245 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5246 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5248 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5249 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5250 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5252 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5253 if (!(mask & (1UL << i)))
5255 mask &= ~(1UL << i);
5256 /* Bit set indicats the coresponding flow type is supported */
5257 g_cfg->valid_bit_mask[0] |= (1UL << i);
5258 pctype = i40e_flowtype_to_pctype(i);
5259 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5260 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5261 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5268 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5271 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5273 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5274 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5275 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5276 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5282 * As i40e supports less than 32 flow types, only first 32 bits need to
5285 mask0 = g_cfg->valid_bit_mask[0];
5286 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5288 /* Check if any unsupported flow type configured */
5289 if ((mask0 | i40e_mask) ^ i40e_mask)
5292 if (g_cfg->valid_bit_mask[i])
5300 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5306 * Set global configurations of hash function type and symmetric hash enable
5307 * per flow type (pctype). Note any modifying global configuration will affect
5308 * all the ports on the same NIC.
5311 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5312 struct rte_eth_hash_global_conf *g_cfg)
5317 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5318 enum i40e_filter_pctype pctype;
5320 /* Check the input parameters */
5321 ret = i40e_hash_global_config_check(g_cfg);
5325 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5326 if (!(mask0 & (1UL << i)))
5328 mask0 &= ~(1UL << i);
5329 pctype = i40e_flowtype_to_pctype(i);
5330 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5331 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5332 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5335 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5336 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5338 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5339 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5343 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5344 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5346 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5347 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5351 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5353 /* Use the default, and keep it as it is */
5356 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5359 I40E_WRITE_FLUSH(hw);
5365 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5370 PMD_DRV_LOG(ERR, "Invalid pointer");
5374 switch (info->info_type) {
5375 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5376 i40e_get_symmetric_hash_enable_per_port(hw,
5377 &(info->info.enable));
5379 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5380 ret = i40e_get_hash_filter_global_config(hw,
5381 &(info->info.global_conf));
5384 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5394 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5399 PMD_DRV_LOG(ERR, "Invalid pointer");
5403 switch (info->info_type) {
5404 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5405 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5407 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5408 ret = i40e_set_hash_filter_global_config(hw,
5409 &(info->info.global_conf));
5412 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5421 /* Operations for hash function */
5423 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5424 enum rte_filter_op filter_op,
5427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430 switch (filter_op) {
5431 case RTE_ETH_FILTER_NOP:
5433 case RTE_ETH_FILTER_GET:
5434 ret = i40e_hash_filter_get(hw,
5435 (struct rte_eth_hash_filter_info *)arg);
5437 case RTE_ETH_FILTER_SET:
5438 ret = i40e_hash_filter_set(hw,
5439 (struct rte_eth_hash_filter_info *)arg);
5442 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5452 * Configure ethertype filter, which can director packet by filtering
5453 * with mac address and ether_type or only ether_type
5456 i40e_ethertype_filter_set(struct i40e_pf *pf,
5457 struct rte_eth_ethertype_filter *filter,
5460 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5461 struct i40e_control_filter_stats stats;
5465 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5466 PMD_DRV_LOG(ERR, "Invalid queue ID");
5469 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5470 filter->ether_type == ETHER_TYPE_IPv6) {
5471 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5472 " control packet filter.", filter->ether_type);
5475 if (filter->ether_type == ETHER_TYPE_VLAN)
5476 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5479 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5480 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5481 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5482 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5483 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5485 memset(&stats, 0, sizeof(stats));
5486 ret = i40e_aq_add_rem_control_packet_filter(hw,
5487 filter->mac_addr.addr_bytes,
5488 filter->ether_type, flags,
5490 filter->queue, add, &stats, NULL);
5492 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5493 " mac_etype_used = %u, etype_used = %u,"
5494 " mac_etype_free = %u, etype_free = %u\n",
5495 ret, stats.mac_etype_used, stats.etype_used,
5496 stats.mac_etype_free, stats.etype_free);
5503 * Handle operations for ethertype filter.
5506 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5507 enum rte_filter_op filter_op,
5510 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5513 if (filter_op == RTE_ETH_FILTER_NOP)
5517 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5522 switch (filter_op) {
5523 case RTE_ETH_FILTER_ADD:
5524 ret = i40e_ethertype_filter_set(pf,
5525 (struct rte_eth_ethertype_filter *)arg,
5528 case RTE_ETH_FILTER_DELETE:
5529 ret = i40e_ethertype_filter_set(pf,
5530 (struct rte_eth_ethertype_filter *)arg,
5534 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5542 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5543 enum rte_filter_type filter_type,
5544 enum rte_filter_op filter_op,
5552 switch (filter_type) {
5553 case RTE_ETH_FILTER_HASH:
5554 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5556 case RTE_ETH_FILTER_MACVLAN:
5557 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5559 case RTE_ETH_FILTER_ETHERTYPE:
5560 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5562 case RTE_ETH_FILTER_TUNNEL:
5563 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5565 case RTE_ETH_FILTER_FDIR:
5566 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5569 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5579 * As some registers wouldn't be reset unless a global hardware reset,
5580 * hardware initialization is needed to put those registers into an
5581 * expected initial state.
5584 i40e_hw_init(struct i40e_hw *hw)
5586 /* clear the PF Queue Filter control register */
5587 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5589 /* Disable symmetric hash per port */
5590 i40e_set_symmetric_hash_enable_per_port(hw, 0);
5593 enum i40e_filter_pctype
5594 i40e_flowtype_to_pctype(uint16_t flow_type)
5596 static const enum i40e_filter_pctype pctype_table[] = {
5597 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5598 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5599 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5600 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5601 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5602 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5603 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5604 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5605 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5606 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5607 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5608 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5609 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5610 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5611 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5612 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5613 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5614 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5615 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5618 return pctype_table[flow_type];
5622 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5624 static const uint16_t flowtype_table[] = {
5625 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5626 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5627 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5628 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5629 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5630 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5631 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5632 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5633 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5634 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5635 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5636 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5637 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5638 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5639 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5640 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5641 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5642 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5643 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5646 return flowtype_table[pctype];
5650 * On X710, performance number is far from the expectation on recent firmware
5651 * versions; on XL710, performance number is also far from the expectation on
5652 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5653 * mode is enabled and port MAC address is equal to the packet destination MAC
5654 * address. The fix for this issue may not be integrated in the following
5655 * firmware version. So the workaround in software driver is needed. It needs
5656 * to modify the initial values of 3 internal only registers for both X710 and
5657 * XL710. Note that the values for X710 or XL710 could be different, and the
5658 * workaround can be removed when it is fixed in firmware in the future.
5661 /* For both X710 and XL710 */
5662 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5663 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
5665 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5666 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
5669 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
5671 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
5672 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
5675 i40e_configure_registers(struct i40e_hw *hw)
5681 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5682 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5683 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5689 for (i = 0; i < RTE_DIM(reg_table); i++) {
5690 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5691 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5693 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5696 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5699 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5702 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5706 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5707 reg_table[i].addr, reg);
5708 if (reg == reg_table[i].val)
5711 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5712 reg_table[i].val, NULL);
5714 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5715 "address of 0x%"PRIx32, reg_table[i].val,
5719 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5720 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5724 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
5725 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
5726 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
5727 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5729 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5734 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5735 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5739 /* Configure for double VLAN RX stripping */
5740 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5741 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5742 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5743 ret = i40e_aq_debug_write_register(hw,
5744 I40E_VSI_TSR(vsi->vsi_id),
5747 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5749 return I40E_ERR_CONFIG;
5753 /* Configure for double VLAN TX insertion */
5754 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5755 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5756 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5757 ret = i40e_aq_debug_write_register(hw,
5758 I40E_VSI_L2TAGSTXVALID(
5759 vsi->vsi_id), reg, NULL);
5761 PMD_DRV_LOG(ERR, "Failed to update "
5762 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5763 return I40E_ERR_CONFIG;
5771 * i40e_aq_add_mirror_rule
5772 * @hw: pointer to the hardware structure
5773 * @seid: VEB seid to add mirror rule to
5774 * @dst_id: destination vsi seid
5775 * @entries: Buffer which contains the entities to be mirrored
5776 * @count: number of entities contained in the buffer
5777 * @rule_id:the rule_id of the rule to be added
5779 * Add a mirror rule for a given veb.
5782 static enum i40e_status_code
5783 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5784 uint16_t seid, uint16_t dst_id,
5785 uint16_t rule_type, uint16_t *entries,
5786 uint16_t count, uint16_t *rule_id)
5788 struct i40e_aq_desc desc;
5789 struct i40e_aqc_add_delete_mirror_rule *cmd =
5790 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
5791 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5792 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5795 enum i40e_status_code status;
5797 i40e_fill_default_direct_cmd_desc(&desc,
5798 i40e_aqc_opc_add_mirror_rule);
5800 buff_len = sizeof(uint16_t) * count;
5801 desc.datalen = rte_cpu_to_le_16(buff_len);
5803 desc.flags |= rte_cpu_to_le_16(
5804 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5805 cmd->rule_type = rte_cpu_to_le_16(rule_type <<
5806 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5807 cmd->num_entries = rte_cpu_to_le_16(count);
5808 cmd->seid = rte_cpu_to_le_16(seid);
5809 cmd->destination = rte_cpu_to_le_16(dst_id);
5811 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5812 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5814 " mirror_rules_used = %u, mirror_rules_free = %u,",
5815 hw->aq.asq_last_status, resp->rule_id,
5816 resp->mirror_rules_used, resp->mirror_rules_free);
5817 *rule_id = rte_le_to_cpu_16(resp->rule_id);
5823 * i40e_aq_del_mirror_rule
5824 * @hw: pointer to the hardware structure
5825 * @seid: VEB seid to add mirror rule to
5826 * @entries: Buffer which contains the entities to be mirrored
5827 * @count: number of entities contained in the buffer
5828 * @rule_id:the rule_id of the rule to be delete
5830 * Delete a mirror rule for a given veb.
5833 static enum i40e_status_code
5834 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5835 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5836 uint16_t count, uint16_t rule_id)
5838 struct i40e_aq_desc desc;
5839 struct i40e_aqc_add_delete_mirror_rule *cmd =
5840 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
5841 uint16_t buff_len = 0;
5842 enum i40e_status_code status;
5845 i40e_fill_default_direct_cmd_desc(&desc,
5846 i40e_aqc_opc_delete_mirror_rule);
5848 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5849 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5851 cmd->num_entries = count;
5852 buff_len = sizeof(uint16_t) * count;
5853 desc.datalen = rte_cpu_to_le_16(buff_len);
5854 buff = (void *)entries;
5856 /* rule id is filled in destination field for deleting mirror rule */
5857 cmd->destination = rte_cpu_to_le_16(rule_id);
5859 cmd->rule_type = rte_cpu_to_le_16(rule_type <<
5860 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5861 cmd->seid = rte_cpu_to_le_16(seid);
5863 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5869 * i40e_mirror_rule_set
5870 * @dev: pointer to the hardware structure
5871 * @mirror_conf: mirror rule info
5872 * @sw_id: mirror rule's sw_id
5873 * @on: enable/disable
5875 * set a mirror rule.
5879 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5880 struct rte_eth_mirror_conf *mirror_conf,
5881 uint8_t sw_id, uint8_t on)
5883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885 struct i40e_mirror_rule *it, *mirr_rule = NULL;
5886 struct i40e_mirror_rule *parent = NULL;
5887 uint16_t seid, dst_seid, rule_id;
5891 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5893 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5894 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5895 " without veb or vfs.");
5898 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5899 PMD_DRV_LOG(ERR, "mirror table is full.");
5902 if (mirror_conf->dst_pool > pf->vf_num) {
5903 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
5904 mirror_conf->dst_pool);
5908 seid = pf->main_vsi->veb->seid;
5910 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
5911 if (sw_id <= it->index) {
5917 if (mirr_rule && sw_id == mirr_rule->index) {
5919 PMD_DRV_LOG(ERR, "mirror rule exists.");
5922 ret = i40e_aq_del_mirror_rule(hw, seid,
5923 mirr_rule->rule_type,
5925 mirr_rule->num_entries, mirr_rule->id);
5927 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
5928 " ret = %d, aq_err = %d.",
5929 ret, hw->aq.asq_last_status);
5932 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
5933 rte_free(mirr_rule);
5934 pf->nb_mirror_rule--;
5938 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
5942 mirr_rule = rte_zmalloc("i40e_mirror_rule",
5943 sizeof(struct i40e_mirror_rule) , 0);
5945 PMD_DRV_LOG(ERR, "failed to allocate memory");
5946 return I40E_ERR_NO_MEMORY;
5948 switch (mirror_conf->rule_type) {
5949 case ETH_MIRROR_VLAN:
5950 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
5951 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5952 mirr_rule->entries[j] =
5953 mirror_conf->vlan.vlan_id[i];
5958 PMD_DRV_LOG(ERR, "vlan is not specified.");
5959 rte_free(mirr_rule);
5962 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
5964 case ETH_MIRROR_VIRTUAL_POOL_UP:
5965 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
5966 /* check if the specified pool bit is out of range */
5967 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
5968 PMD_DRV_LOG(ERR, "pool mask is out of range.");
5969 rte_free(mirr_rule);
5972 for (i = 0, j = 0; i < pf->vf_num; i++) {
5973 if (mirror_conf->pool_mask & (1ULL << i)) {
5974 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
5978 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
5979 /* add pf vsi to entries */
5980 mirr_rule->entries[j] = pf->main_vsi_seid;
5984 PMD_DRV_LOG(ERR, "pool is not specified.");
5985 rte_free(mirr_rule);
5988 /* egress and ingress in aq commands means from switch but not port */
5989 mirr_rule->rule_type =
5990 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
5991 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
5992 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
5994 case ETH_MIRROR_UPLINK_PORT:
5995 /* egress and ingress in aq commands means from switch but not port*/
5996 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
5998 case ETH_MIRROR_DOWNLINK_PORT:
5999 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6002 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6003 mirror_conf->rule_type);
6004 rte_free(mirr_rule);
6008 /* If the dst_pool is equal to vf_num, consider it as PF */
6009 if (mirror_conf->dst_pool == pf->vf_num)
6010 dst_seid = pf->main_vsi_seid;
6012 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6014 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6015 mirr_rule->rule_type, mirr_rule->entries,
6018 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6019 " ret = %d, aq_err = %d.",
6020 ret, hw->aq.asq_last_status);
6021 rte_free(mirr_rule);
6025 mirr_rule->index = sw_id;
6026 mirr_rule->num_entries = j;
6027 mirr_rule->id = rule_id;
6028 mirr_rule->dst_vsi_seid = dst_seid;
6031 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6033 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6035 pf->nb_mirror_rule++;
6040 * i40e_mirror_rule_reset
6041 * @dev: pointer to the device
6042 * @sw_id: mirror rule's sw_id
6044 * reset a mirror rule.
6048 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6051 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6052 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6056 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6058 seid = pf->main_vsi->veb->seid;
6060 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6061 if (sw_id == it->index) {
6067 ret = i40e_aq_del_mirror_rule(hw, seid,
6068 mirr_rule->rule_type,
6070 mirr_rule->num_entries, mirr_rule->id);
6072 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6073 " status = %d, aq_err = %d.",
6074 ret, hw->aq.asq_last_status);
6077 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6078 rte_free(mirr_rule);
6079 pf->nb_mirror_rule--;
6081 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");