4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 /* The max bandwidth of i40e is 40Gbps. */
247 #define I40E_QOS_BW_MAX 40000
248 /* The bandwidth should be the multiple of 50Mbps. */
249 #define I40E_QOS_BW_GRANULARITY 50
250 /* The min bandwidth weight is 1. */
251 #define I40E_QOS_BW_WEIGHT_MIN 1
252 /* The max bandwidth weight is 127. */
253 #define I40E_QOS_BW_WEIGHT_MAX 127
255 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
256 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
257 static int i40e_dev_configure(struct rte_eth_dev *dev);
258 static int i40e_dev_start(struct rte_eth_dev *dev);
259 static void i40e_dev_stop(struct rte_eth_dev *dev);
260 static void i40e_dev_close(struct rte_eth_dev *dev);
261 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
262 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
263 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
264 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
266 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
267 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
270 struct rte_eth_xstat *xstats, unsigned n);
271 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
272 struct rte_eth_xstat_name *xstats_names,
274 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
275 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
279 static int i40e_fw_version_get(struct rte_eth_dev *dev,
280 char *fw_version, size_t fw_size);
281 static void i40e_dev_info_get(struct rte_eth_dev *dev,
282 struct rte_eth_dev_info *dev_info);
283 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
287 enum rte_vlan_type vlan_type,
289 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
290 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
293 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
294 static int i40e_dev_led_on(struct rte_eth_dev *dev);
295 static int i40e_dev_led_off(struct rte_eth_dev *dev);
296 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
297 struct rte_eth_fc_conf *fc_conf);
298 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
299 struct rte_eth_fc_conf *fc_conf);
300 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
301 struct rte_eth_pfc_conf *pfc_conf);
302 static void i40e_macaddr_add(struct rte_eth_dev *dev,
303 struct ether_addr *mac_addr,
306 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
307 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
308 struct rte_eth_rss_reta_entry64 *reta_conf,
310 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
311 struct rte_eth_rss_reta_entry64 *reta_conf,
314 static int i40e_get_cap(struct i40e_hw *hw);
315 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
316 static int i40e_pf_setup(struct i40e_pf *pf);
317 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
318 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
319 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
320 static int i40e_dcb_setup(struct rte_eth_dev *dev);
321 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
322 bool offset_loaded, uint64_t *offset, uint64_t *stat);
323 static void i40e_stat_update_48(struct i40e_hw *hw,
329 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
330 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
332 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
333 uint32_t base, uint32_t num);
334 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
335 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
337 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
339 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
340 static int i40e_veb_release(struct i40e_veb *veb);
341 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
342 struct i40e_vsi *vsi);
343 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
344 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
345 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
346 struct i40e_macvlan_filter *mv_f,
348 struct ether_addr *addr);
349 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
350 struct i40e_macvlan_filter *mv_f,
353 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
354 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
355 struct rte_eth_rss_conf *rss_conf);
356 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
357 struct rte_eth_rss_conf *rss_conf);
358 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
359 struct rte_eth_udp_tunnel *udp_tunnel);
360 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static void i40e_filter_input_set_init(struct i40e_pf *pf);
363 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
366 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
367 enum rte_filter_type filter_type,
368 enum rte_filter_op filter_op,
370 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
371 struct rte_eth_dcb_info *dcb_info);
372 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
373 static void i40e_configure_registers(struct i40e_hw *hw);
374 static void i40e_hw_init(struct rte_eth_dev *dev);
375 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
376 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
377 struct rte_eth_mirror_conf *mirror_conf,
378 uint8_t sw_id, uint8_t on);
379 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
381 static int i40e_timesync_enable(struct rte_eth_dev *dev);
382 static int i40e_timesync_disable(struct rte_eth_dev *dev);
383 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
384 struct timespec *timestamp,
386 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
387 struct timespec *timestamp);
388 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
390 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
392 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
393 struct timespec *timestamp);
394 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
395 const struct timespec *timestamp);
397 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
399 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
402 static int i40e_get_regs(struct rte_eth_dev *dev,
403 struct rte_dev_reg_info *regs);
405 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
407 static int i40e_get_eeprom(struct rte_eth_dev *dev,
408 struct rte_dev_eeprom_info *eeprom);
410 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
411 struct ether_addr *mac_addr);
413 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
415 static int i40e_ethertype_filter_convert(
416 const struct rte_eth_ethertype_filter *input,
417 struct i40e_ethertype_filter *filter);
418 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
419 struct i40e_ethertype_filter *filter);
421 static int i40e_tunnel_filter_convert(
422 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
423 struct i40e_tunnel_filter *tunnel_filter);
424 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
425 struct i40e_tunnel_filter *tunnel_filter);
426 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
428 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
429 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
430 static void i40e_filter_restore(struct i40e_pf *pf);
432 static const struct rte_pci_id pci_id_i40e_map[] = {
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .promiscuous_enable = i40e_dev_promiscuous_enable,
462 .promiscuous_disable = i40e_dev_promiscuous_disable,
463 .allmulticast_enable = i40e_dev_allmulticast_enable,
464 .allmulticast_disable = i40e_dev_allmulticast_disable,
465 .dev_set_link_up = i40e_dev_set_link_up,
466 .dev_set_link_down = i40e_dev_set_link_down,
467 .link_update = i40e_dev_link_update,
468 .stats_get = i40e_dev_stats_get,
469 .xstats_get = i40e_dev_xstats_get,
470 .xstats_get_names = i40e_dev_xstats_get_names,
471 .stats_reset = i40e_dev_stats_reset,
472 .xstats_reset = i40e_dev_stats_reset,
473 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
474 .fw_version_get = i40e_fw_version_get,
475 .dev_infos_get = i40e_dev_info_get,
476 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
477 .vlan_filter_set = i40e_vlan_filter_set,
478 .vlan_tpid_set = i40e_vlan_tpid_set,
479 .vlan_offload_set = i40e_vlan_offload_set,
480 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
481 .vlan_pvid_set = i40e_vlan_pvid_set,
482 .rx_queue_start = i40e_dev_rx_queue_start,
483 .rx_queue_stop = i40e_dev_rx_queue_stop,
484 .tx_queue_start = i40e_dev_tx_queue_start,
485 .tx_queue_stop = i40e_dev_tx_queue_stop,
486 .rx_queue_setup = i40e_dev_rx_queue_setup,
487 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
488 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
489 .rx_queue_release = i40e_dev_rx_queue_release,
490 .rx_queue_count = i40e_dev_rx_queue_count,
491 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
492 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
493 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
494 .tx_queue_setup = i40e_dev_tx_queue_setup,
495 .tx_queue_release = i40e_dev_tx_queue_release,
496 .dev_led_on = i40e_dev_led_on,
497 .dev_led_off = i40e_dev_led_off,
498 .flow_ctrl_get = i40e_flow_ctrl_get,
499 .flow_ctrl_set = i40e_flow_ctrl_set,
500 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
501 .mac_addr_add = i40e_macaddr_add,
502 .mac_addr_remove = i40e_macaddr_remove,
503 .reta_update = i40e_dev_rss_reta_update,
504 .reta_query = i40e_dev_rss_reta_query,
505 .rss_hash_update = i40e_dev_rss_hash_update,
506 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
507 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
508 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
509 .filter_ctrl = i40e_dev_filter_ctrl,
510 .rxq_info_get = i40e_rxq_info_get,
511 .txq_info_get = i40e_txq_info_get,
512 .mirror_rule_set = i40e_mirror_rule_set,
513 .mirror_rule_reset = i40e_mirror_rule_reset,
514 .timesync_enable = i40e_timesync_enable,
515 .timesync_disable = i40e_timesync_disable,
516 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
517 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
518 .get_dcb_info = i40e_dev_get_dcb_info,
519 .timesync_adjust_time = i40e_timesync_adjust_time,
520 .timesync_read_time = i40e_timesync_read_time,
521 .timesync_write_time = i40e_timesync_write_time,
522 .get_reg = i40e_get_regs,
523 .get_eeprom_length = i40e_get_eeprom_length,
524 .get_eeprom = i40e_get_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
529 /* store statistics names and its offset in stats structure */
530 struct rte_i40e_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
536 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
537 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
538 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
539 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
540 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
541 rx_unknown_protocol)},
542 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
543 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
544 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
545 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
549 sizeof(rte_i40e_stats_strings[0]))
551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
552 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
553 tx_dropped_link_down)},
554 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
555 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
558 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
560 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
562 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
564 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
565 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
566 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
567 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
568 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
569 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
586 mac_short_packet_dropped)},
587 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
590 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
591 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_flow_director_atr_match_packets",
604 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
605 {"rx_flow_director_sb_match_packets",
606 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
607 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
611 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
618 sizeof(rte_i40e_hw_port_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
628 sizeof(rte_i40e_rxq_prio_strings[0]))
630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
631 {"xon_packets", offsetof(struct i40e_hw_port_stats,
633 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
635 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
636 priority_xon_2_xoff)},
639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
640 sizeof(rte_i40e_txq_prio_strings[0]))
642 static struct eth_driver rte_i40e_pmd = {
644 .id_table = pci_id_i40e_map,
645 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
646 .probe = rte_eth_dev_pci_probe,
647 .remove = rte_eth_dev_pci_remove,
649 .eth_dev_init = eth_i40e_dev_init,
650 .eth_dev_uninit = eth_i40e_dev_uninit,
651 .dev_private_size = sizeof(struct i40e_adapter),
655 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
656 struct rte_eth_link *link)
658 struct rte_eth_link *dst = link;
659 struct rte_eth_link *src = &(dev->data->dev_link);
661 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
662 *(uint64_t *)src) == 0)
669 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
670 struct rte_eth_link *link)
672 struct rte_eth_link *dst = &(dev->data->dev_link);
673 struct rte_eth_link *src = link;
675 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
676 *(uint64_t *)src) == 0)
682 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
683 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
684 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
686 #ifndef I40E_GLQF_ORT
687 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
689 #ifndef I40E_GLQF_PIT
690 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
692 #ifndef I40E_GLQF_L3_MAP
693 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
696 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
699 * Initialize registers for flexible payload, which should be set by NVM.
700 * This should be removed from code once it is fixed in NVM.
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
712 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
713 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
715 /* Initialize registers for parsing packet type of QinQ */
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
717 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
720 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
723 * Add a ethertype filter to drop all flow control frames transmitted
727 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
729 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
730 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
731 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
732 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
735 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
736 I40E_FLOW_CONTROL_ETHERTYPE, flags,
737 pf->main_vsi_seid, 0,
741 "Failed to add filter to drop flow control frames from VSIs.");
745 floating_veb_list_handler(__rte_unused const char *key,
746 const char *floating_veb_value,
750 unsigned int count = 0;
753 bool *vf_floating_veb = opaque;
755 while (isblank(*floating_veb_value))
756 floating_veb_value++;
758 /* Reset floating VEB configuration for VFs */
759 for (idx = 0; idx < I40E_MAX_VF; idx++)
760 vf_floating_veb[idx] = false;
764 while (isblank(*floating_veb_value))
765 floating_veb_value++;
766 if (*floating_veb_value == '\0')
769 idx = strtoul(floating_veb_value, &end, 10);
770 if (errno || end == NULL)
772 while (isblank(*end))
776 } else if ((*end == ';') || (*end == '\0')) {
778 if (min == I40E_MAX_VF)
780 if (max >= I40E_MAX_VF)
781 max = I40E_MAX_VF - 1;
782 for (idx = min; idx <= max; idx++) {
783 vf_floating_veb[idx] = true;
790 floating_veb_value = end + 1;
791 } while (*end != '\0');
800 config_vf_floating_veb(struct rte_devargs *devargs,
801 uint16_t floating_veb,
802 bool *vf_floating_veb)
804 struct rte_kvargs *kvlist;
806 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
810 /* All the VFs attach to the floating VEB by default
811 * when the floating VEB is enabled.
813 for (i = 0; i < I40E_MAX_VF; i++)
814 vf_floating_veb[i] = true;
819 kvlist = rte_kvargs_parse(devargs->args, NULL);
823 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
824 rte_kvargs_free(kvlist);
827 /* When the floating_veb_list parameter exists, all the VFs
828 * will attach to the legacy VEB firstly, then configure VFs
829 * to the floating VEB according to the floating_veb_list.
831 if (rte_kvargs_process(kvlist, floating_veb_list,
832 floating_veb_list_handler,
833 vf_floating_veb) < 0) {
834 rte_kvargs_free(kvlist);
837 rte_kvargs_free(kvlist);
841 i40e_check_floating_handler(__rte_unused const char *key,
843 __rte_unused void *opaque)
845 if (strcmp(value, "1"))
852 is_floating_veb_supported(struct rte_devargs *devargs)
854 struct rte_kvargs *kvlist;
855 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
860 kvlist = rte_kvargs_parse(devargs->args, NULL);
864 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
865 rte_kvargs_free(kvlist);
868 /* Floating VEB is enabled when there's key-value:
869 * enable_floating_veb=1
871 if (rte_kvargs_process(kvlist, floating_veb_key,
872 i40e_check_floating_handler, NULL) < 0) {
873 rte_kvargs_free(kvlist);
876 rte_kvargs_free(kvlist);
882 config_floating_veb(struct rte_eth_dev *dev)
884 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
885 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
886 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
888 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
890 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
892 is_floating_veb_supported(pci_dev->device.devargs);
893 config_vf_floating_veb(pci_dev->device.devargs,
895 pf->floating_veb_list);
897 pf->floating_veb = false;
901 #define I40E_L2_TAGS_S_TAG_SHIFT 1
902 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
905 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
908 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
909 char ethertype_hash_name[RTE_HASH_NAMESIZE];
912 struct rte_hash_parameters ethertype_hash_params = {
913 .name = ethertype_hash_name,
914 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
915 .key_len = sizeof(struct i40e_ethertype_filter_input),
916 .hash_func = rte_hash_crc,
917 .hash_func_init_val = 0,
918 .socket_id = rte_socket_id(),
921 /* Initialize ethertype filter rule list and hash */
922 TAILQ_INIT(ðertype_rule->ethertype_list);
923 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
924 "ethertype_%s", dev->data->name);
925 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
926 if (!ethertype_rule->hash_table) {
927 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
930 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
931 sizeof(struct i40e_ethertype_filter *) *
932 I40E_MAX_ETHERTYPE_FILTER_NUM,
934 if (!ethertype_rule->hash_map) {
936 "Failed to allocate memory for ethertype hash map!");
938 goto err_ethertype_hash_map_alloc;
943 err_ethertype_hash_map_alloc:
944 rte_hash_free(ethertype_rule->hash_table);
950 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
952 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
953 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
954 char tunnel_hash_name[RTE_HASH_NAMESIZE];
957 struct rte_hash_parameters tunnel_hash_params = {
958 .name = tunnel_hash_name,
959 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
960 .key_len = sizeof(struct i40e_tunnel_filter_input),
961 .hash_func = rte_hash_crc,
962 .hash_func_init_val = 0,
963 .socket_id = rte_socket_id(),
966 /* Initialize tunnel filter rule list and hash */
967 TAILQ_INIT(&tunnel_rule->tunnel_list);
968 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
969 "tunnel_%s", dev->data->name);
970 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
971 if (!tunnel_rule->hash_table) {
972 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
975 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
976 sizeof(struct i40e_tunnel_filter *) *
977 I40E_MAX_TUNNEL_FILTER_NUM,
979 if (!tunnel_rule->hash_map) {
981 "Failed to allocate memory for tunnel hash map!");
983 goto err_tunnel_hash_map_alloc;
988 err_tunnel_hash_map_alloc:
989 rte_hash_free(tunnel_rule->hash_table);
995 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
997 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
998 struct i40e_fdir_info *fdir_info = &pf->fdir;
999 char fdir_hash_name[RTE_HASH_NAMESIZE];
1002 struct rte_hash_parameters fdir_hash_params = {
1003 .name = fdir_hash_name,
1004 .entries = I40E_MAX_FDIR_FILTER_NUM,
1005 .key_len = sizeof(struct rte_eth_fdir_input),
1006 .hash_func = rte_hash_crc,
1007 .hash_func_init_val = 0,
1008 .socket_id = rte_socket_id(),
1011 /* Initialize flow director filter rule list and hash */
1012 TAILQ_INIT(&fdir_info->fdir_list);
1013 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1014 "fdir_%s", dev->data->name);
1015 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1016 if (!fdir_info->hash_table) {
1017 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1020 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1021 sizeof(struct i40e_fdir_filter *) *
1022 I40E_MAX_FDIR_FILTER_NUM,
1024 if (!fdir_info->hash_map) {
1026 "Failed to allocate memory for fdir hash map!");
1028 goto err_fdir_hash_map_alloc;
1032 err_fdir_hash_map_alloc:
1033 rte_hash_free(fdir_info->hash_table);
1039 eth_i40e_dev_init(struct rte_eth_dev *dev)
1041 struct rte_pci_device *pci_dev;
1042 struct rte_intr_handle *intr_handle;
1043 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045 struct i40e_vsi *vsi;
1048 uint8_t aq_fail = 0;
1050 PMD_INIT_FUNC_TRACE();
1052 dev->dev_ops = &i40e_eth_dev_ops;
1053 dev->rx_pkt_burst = i40e_recv_pkts;
1054 dev->tx_pkt_burst = i40e_xmit_pkts;
1055 dev->tx_pkt_prepare = i40e_prep_pkts;
1057 /* for secondary processes, we don't initialise any further as primary
1058 * has already done this work. Only check we don't need a different
1060 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1061 i40e_set_rx_function(dev);
1062 i40e_set_tx_function(dev);
1065 pci_dev = I40E_DEV_TO_PCI(dev);
1066 intr_handle = &pci_dev->intr_handle;
1068 rte_eth_copy_pci_info(dev, pci_dev);
1069 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1071 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072 pf->adapter->eth_dev = dev;
1073 pf->dev_data = dev->data;
1075 hw->back = I40E_PF_TO_ADAPTER(pf);
1076 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1079 "Hardware is not available, as address is NULL");
1083 hw->vendor_id = pci_dev->id.vendor_id;
1084 hw->device_id = pci_dev->id.device_id;
1085 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087 hw->bus.device = pci_dev->addr.devid;
1088 hw->bus.func = pci_dev->addr.function;
1089 hw->adapter_stopped = 0;
1091 /* Make sure all is clean before doing PF reset */
1094 /* Initialize the hardware */
1097 /* Reset here to make sure all is clean for each PF */
1098 ret = i40e_pf_reset(hw);
1100 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1104 /* Initialize the shared code (base driver) */
1105 ret = i40e_init_shared_code(hw);
1107 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1112 * To work around the NVM issue, initialize registers
1113 * for flexible payload and packet type of QinQ by
1114 * software. It should be removed once issues are fixed
1117 i40e_GLQF_reg_init(hw);
1119 /* Initialize the input set for filters (hash and fd) to default value */
1120 i40e_filter_input_set_init(pf);
1122 /* Initialize the parameters for adminq */
1123 i40e_init_adminq_parameter(hw);
1124 ret = i40e_init_adminq(hw);
1125 if (ret != I40E_SUCCESS) {
1126 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1129 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132 ((hw->nvm.version >> 12) & 0xf),
1133 ((hw->nvm.version >> 4) & 0xff),
1134 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1136 /* initialise the L3_MAP register */
1137 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1140 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1142 /* Need the special FW version to support floating VEB */
1143 config_floating_veb(dev);
1144 /* Clear PXE mode */
1145 i40e_clear_pxe_mode(hw);
1146 ret = i40e_dev_sync_phy_type(hw);
1148 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1149 goto err_sync_phy_type;
1152 * On X710, performance number is far from the expectation on recent
1153 * firmware versions. The fix for this issue may not be integrated in
1154 * the following firmware version. So the workaround in software driver
1155 * is needed. It needs to modify the initial values of 3 internal only
1156 * registers. Note that the workaround can be removed when it is fixed
1157 * in firmware in the future.
1159 i40e_configure_registers(hw);
1161 /* Get hw capabilities */
1162 ret = i40e_get_cap(hw);
1163 if (ret != I40E_SUCCESS) {
1164 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1165 goto err_get_capabilities;
1168 /* Initialize parameters for PF */
1169 ret = i40e_pf_parameter_init(dev);
1171 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1172 goto err_parameter_init;
1175 /* Initialize the queue management */
1176 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1178 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1179 goto err_qp_pool_init;
1181 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1182 hw->func_caps.num_msix_vectors - 1);
1184 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1185 goto err_msix_pool_init;
1188 /* Initialize lan hmc */
1189 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1190 hw->func_caps.num_rx_qp, 0, 0);
1191 if (ret != I40E_SUCCESS) {
1192 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1193 goto err_init_lan_hmc;
1196 /* Configure lan hmc */
1197 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1198 if (ret != I40E_SUCCESS) {
1199 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1200 goto err_configure_lan_hmc;
1203 /* Get and check the mac address */
1204 i40e_get_mac_addr(hw, hw->mac.addr);
1205 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1206 PMD_INIT_LOG(ERR, "mac address is not valid");
1208 goto err_get_mac_addr;
1210 /* Copy the permanent MAC address */
1211 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1212 (struct ether_addr *) hw->mac.perm_addr);
1214 /* Disable flow control */
1215 hw->fc.requested_mode = I40E_FC_NONE;
1216 i40e_set_fc(hw, &aq_fail, TRUE);
1218 /* Set the global registers with default ether type value */
1219 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1220 if (ret != I40E_SUCCESS) {
1222 "Failed to set the default outer VLAN ether type");
1223 goto err_setup_pf_switch;
1226 /* PF setup, which includes VSI setup */
1227 ret = i40e_pf_setup(pf);
1229 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1230 goto err_setup_pf_switch;
1233 /* reset all stats of the device, including pf and main vsi */
1234 i40e_dev_stats_reset(dev);
1238 /* Disable double vlan by default */
1239 i40e_vsi_config_double_vlan(vsi, FALSE);
1241 /* Disable S-TAG identification when floating_veb is disabled */
1242 if (!pf->floating_veb) {
1243 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1244 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1245 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1246 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1250 if (!vsi->max_macaddrs)
1251 len = ETHER_ADDR_LEN;
1253 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1255 /* Should be after VSI initialized */
1256 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1257 if (!dev->data->mac_addrs) {
1259 "Failed to allocated memory for storing mac address");
1262 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1263 &dev->data->mac_addrs[0]);
1265 /* Init dcb to sw mode by default */
1266 ret = i40e_dcb_init_configure(dev, TRUE);
1267 if (ret != I40E_SUCCESS) {
1268 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1269 pf->flags &= ~I40E_FLAG_DCB;
1271 /* Update HW struct after DCB configuration */
1274 /* initialize pf host driver to setup SRIOV resource if applicable */
1275 i40e_pf_host_init(dev);
1277 /* register callback func to eal lib */
1278 rte_intr_callback_register(intr_handle,
1279 i40e_dev_interrupt_handler, dev);
1281 /* configure and enable device interrupt */
1282 i40e_pf_config_irq0(hw, TRUE);
1283 i40e_pf_enable_irq0(hw);
1285 /* enable uio intr after callback register */
1286 rte_intr_enable(intr_handle);
1288 * Add an ethertype filter to drop all flow control frames transmitted
1289 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1292 i40e_add_tx_flow_control_drop_filter(pf);
1294 /* Set the max frame size to 0x2600 by default,
1295 * in case other drivers changed the default value.
1297 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1299 /* initialize mirror rule list */
1300 TAILQ_INIT(&pf->mirror_list);
1302 ret = i40e_init_ethtype_filter_list(dev);
1304 goto err_init_ethtype_filter_list;
1305 ret = i40e_init_tunnel_filter_list(dev);
1307 goto err_init_tunnel_filter_list;
1308 ret = i40e_init_fdir_filter_list(dev);
1310 goto err_init_fdir_filter_list;
1314 err_init_fdir_filter_list:
1315 rte_free(pf->tunnel.hash_table);
1316 rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318 rte_free(pf->ethertype.hash_table);
1319 rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321 rte_free(dev->data->mac_addrs);
1323 i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1326 err_configure_lan_hmc:
1327 (void)i40e_shutdown_lan_hmc(hw);
1329 i40e_res_pool_destroy(&pf->msix_pool);
1331 i40e_res_pool_destroy(&pf->qp_pool);
1334 err_get_capabilities:
1336 (void)i40e_shutdown_adminq(hw);
1342 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1344 struct i40e_ethertype_filter *p_ethertype;
1345 struct i40e_ethertype_rule *ethertype_rule;
1347 ethertype_rule = &pf->ethertype;
1348 /* Remove all ethertype filter rules and hash */
1349 if (ethertype_rule->hash_map)
1350 rte_free(ethertype_rule->hash_map);
1351 if (ethertype_rule->hash_table)
1352 rte_hash_free(ethertype_rule->hash_table);
1354 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1355 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1356 p_ethertype, rules);
1357 rte_free(p_ethertype);
1362 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1364 struct i40e_tunnel_filter *p_tunnel;
1365 struct i40e_tunnel_rule *tunnel_rule;
1367 tunnel_rule = &pf->tunnel;
1368 /* Remove all tunnel director rules and hash */
1369 if (tunnel_rule->hash_map)
1370 rte_free(tunnel_rule->hash_map);
1371 if (tunnel_rule->hash_table)
1372 rte_hash_free(tunnel_rule->hash_table);
1374 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1375 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1381 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1383 struct i40e_fdir_filter *p_fdir;
1384 struct i40e_fdir_info *fdir_info;
1386 fdir_info = &pf->fdir;
1387 /* Remove all flow director rules and hash */
1388 if (fdir_info->hash_map)
1389 rte_free(fdir_info->hash_map);
1390 if (fdir_info->hash_table)
1391 rte_hash_free(fdir_info->hash_table);
1393 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1394 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1400 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1403 struct rte_pci_device *pci_dev;
1404 struct rte_intr_handle *intr_handle;
1406 struct i40e_filter_control_settings settings;
1407 struct rte_flow *p_flow;
1409 uint8_t aq_fail = 0;
1411 PMD_INIT_FUNC_TRACE();
1413 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1416 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1417 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418 pci_dev = I40E_DEV_TO_PCI(dev);
1419 intr_handle = &pci_dev->intr_handle;
1421 if (hw->adapter_stopped == 0)
1422 i40e_dev_close(dev);
1424 dev->dev_ops = NULL;
1425 dev->rx_pkt_burst = NULL;
1426 dev->tx_pkt_burst = NULL;
1428 /* Clear PXE mode */
1429 i40e_clear_pxe_mode(hw);
1431 /* Unconfigure filter control */
1432 memset(&settings, 0, sizeof(settings));
1433 ret = i40e_set_filter_control(hw, &settings);
1435 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1438 /* Disable flow control */
1439 hw->fc.requested_mode = I40E_FC_NONE;
1440 i40e_set_fc(hw, &aq_fail, TRUE);
1442 /* uninitialize pf host driver */
1443 i40e_pf_host_uninit(dev);
1445 rte_free(dev->data->mac_addrs);
1446 dev->data->mac_addrs = NULL;
1448 /* disable uio intr before callback unregister */
1449 rte_intr_disable(intr_handle);
1451 /* register callback func to eal lib */
1452 rte_intr_callback_unregister(intr_handle,
1453 i40e_dev_interrupt_handler, dev);
1455 i40e_rm_ethtype_filter_list(pf);
1456 i40e_rm_tunnel_filter_list(pf);
1457 i40e_rm_fdir_filter_list(pf);
1459 /* Remove all flows */
1460 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1461 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1469 i40e_dev_configure(struct rte_eth_dev *dev)
1471 struct i40e_adapter *ad =
1472 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1474 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1477 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1478 * bulk allocation or vector Rx preconditions we will reset it.
1480 ad->rx_bulk_alloc_allowed = true;
1481 ad->rx_vec_allowed = true;
1482 ad->tx_simple_allowed = true;
1483 ad->tx_vec_allowed = true;
1485 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1486 ret = i40e_fdir_setup(pf);
1487 if (ret != I40E_SUCCESS) {
1488 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1491 ret = i40e_fdir_configure(dev);
1493 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1497 i40e_fdir_teardown(pf);
1499 ret = i40e_dev_init_vlan(dev);
1504 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1505 * RSS setting have different requirements.
1506 * General PMD driver call sequence are NIC init, configure,
1507 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1508 * will try to lookup the VSI that specific queue belongs to if VMDQ
1509 * applicable. So, VMDQ setting has to be done before
1510 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1511 * For RSS setting, it will try to calculate actual configured RX queue
1512 * number, which will be available after rx_queue_setup(). dev_start()
1513 * function is good to place RSS setup.
1515 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1516 ret = i40e_vmdq_setup(dev);
1521 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1522 ret = i40e_dcb_setup(dev);
1524 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1529 TAILQ_INIT(&pf->flow_list);
1534 /* need to release vmdq resource if exists */
1535 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1536 i40e_vsi_release(pf->vmdq[i].vsi);
1537 pf->vmdq[i].vsi = NULL;
1542 /* need to release fdir resource if exists */
1543 i40e_fdir_teardown(pf);
1548 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1550 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1551 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1552 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1554 uint16_t msix_vect = vsi->msix_intr;
1557 for (i = 0; i < vsi->nb_qps; i++) {
1558 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1559 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1563 if (vsi->type != I40E_VSI_SRIOV) {
1564 if (!rte_intr_allow_others(intr_handle)) {
1565 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1566 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1568 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1571 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1572 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1574 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1579 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1580 vsi->user_param + (msix_vect - 1);
1582 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1583 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1585 I40E_WRITE_FLUSH(hw);
1589 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1590 int base_queue, int nb_queue)
1594 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1596 /* Bind all RX queues to allocated MSIX interrupt */
1597 for (i = 0; i < nb_queue; i++) {
1598 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1599 I40E_QINT_RQCTL_ITR_INDX_MASK |
1600 ((base_queue + i + 1) <<
1601 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1602 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1603 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1605 if (i == nb_queue - 1)
1606 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1607 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1610 /* Write first RX queue to Link list register as the head element */
1611 if (vsi->type != I40E_VSI_SRIOV) {
1613 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1615 if (msix_vect == I40E_MISC_VEC_ID) {
1616 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1618 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1620 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1622 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1625 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1627 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1629 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1631 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1638 if (msix_vect == I40E_MISC_VEC_ID) {
1640 I40E_VPINT_LNKLST0(vsi->user_param),
1642 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1644 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1646 /* num_msix_vectors_vf needs to minus irq0 */
1647 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1648 vsi->user_param + (msix_vect - 1);
1650 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1652 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1654 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1658 I40E_WRITE_FLUSH(hw);
1662 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1664 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1665 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1666 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1667 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1668 uint16_t msix_vect = vsi->msix_intr;
1669 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1670 uint16_t queue_idx = 0;
1675 for (i = 0; i < vsi->nb_qps; i++) {
1676 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1677 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1680 /* INTENA flag is not auto-cleared for interrupt */
1681 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1682 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1684 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1685 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1687 /* VF bind interrupt */
1688 if (vsi->type == I40E_VSI_SRIOV) {
1689 __vsi_queues_bind_intr(vsi, msix_vect,
1690 vsi->base_queue, vsi->nb_qps);
1694 /* PF & VMDq bind interrupt */
1695 if (rte_intr_dp_is_en(intr_handle)) {
1696 if (vsi->type == I40E_VSI_MAIN) {
1699 } else if (vsi->type == I40E_VSI_VMDQ2) {
1700 struct i40e_vsi *main_vsi =
1701 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1702 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1707 for (i = 0; i < vsi->nb_used_qps; i++) {
1709 if (!rte_intr_allow_others(intr_handle))
1710 /* allow to share MISC_VEC_ID */
1711 msix_vect = I40E_MISC_VEC_ID;
1713 /* no enough msix_vect, map all to one */
1714 __vsi_queues_bind_intr(vsi, msix_vect,
1715 vsi->base_queue + i,
1716 vsi->nb_used_qps - i);
1717 for (; !!record && i < vsi->nb_used_qps; i++)
1718 intr_handle->intr_vec[queue_idx + i] =
1722 /* 1:1 queue/msix_vect mapping */
1723 __vsi_queues_bind_intr(vsi, msix_vect,
1724 vsi->base_queue + i, 1);
1726 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1736 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1737 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1738 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1739 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1740 uint16_t interval = i40e_calc_itr_interval(\
1741 RTE_LIBRTE_I40E_ITR_INTERVAL);
1742 uint16_t msix_intr, i;
1744 if (rte_intr_allow_others(intr_handle))
1745 for (i = 0; i < vsi->nb_msix; i++) {
1746 msix_intr = vsi->msix_intr + i;
1747 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1748 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1749 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1750 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1752 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1755 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1756 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1757 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1758 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1760 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1762 I40E_WRITE_FLUSH(hw);
1766 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1768 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1769 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1770 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1771 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1772 uint16_t msix_intr, i;
1774 if (rte_intr_allow_others(intr_handle))
1775 for (i = 0; i < vsi->nb_msix; i++) {
1776 msix_intr = vsi->msix_intr + i;
1777 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1781 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1783 I40E_WRITE_FLUSH(hw);
1786 static inline uint8_t
1787 i40e_parse_link_speeds(uint16_t link_speeds)
1789 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1791 if (link_speeds & ETH_LINK_SPEED_40G)
1792 link_speed |= I40E_LINK_SPEED_40GB;
1793 if (link_speeds & ETH_LINK_SPEED_25G)
1794 link_speed |= I40E_LINK_SPEED_25GB;
1795 if (link_speeds & ETH_LINK_SPEED_20G)
1796 link_speed |= I40E_LINK_SPEED_20GB;
1797 if (link_speeds & ETH_LINK_SPEED_10G)
1798 link_speed |= I40E_LINK_SPEED_10GB;
1799 if (link_speeds & ETH_LINK_SPEED_1G)
1800 link_speed |= I40E_LINK_SPEED_1GB;
1801 if (link_speeds & ETH_LINK_SPEED_100M)
1802 link_speed |= I40E_LINK_SPEED_100MB;
1808 i40e_phy_conf_link(struct i40e_hw *hw,
1810 uint8_t force_speed)
1812 enum i40e_status_code status;
1813 struct i40e_aq_get_phy_abilities_resp phy_ab;
1814 struct i40e_aq_set_phy_config phy_conf;
1815 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_PAUSE_RX |
1818 I40E_AQ_PHY_FLAG_LOW_POWER;
1819 const uint8_t advt = I40E_LINK_SPEED_40GB |
1820 I40E_LINK_SPEED_25GB |
1821 I40E_LINK_SPEED_10GB |
1822 I40E_LINK_SPEED_1GB |
1823 I40E_LINK_SPEED_100MB;
1827 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1832 memset(&phy_conf, 0, sizeof(phy_conf));
1834 /* bits 0-2 use the values from get_phy_abilities_resp */
1836 abilities |= phy_ab.abilities & mask;
1838 /* update ablities and speed */
1839 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1840 phy_conf.link_speed = advt;
1842 phy_conf.link_speed = force_speed;
1844 phy_conf.abilities = abilities;
1846 /* use get_phy_abilities_resp value for the rest */
1847 phy_conf.phy_type = phy_ab.phy_type;
1848 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1849 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1850 phy_conf.eee_capability = phy_ab.eee_capability;
1851 phy_conf.eeer = phy_ab.eeer_val;
1852 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1854 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1855 phy_ab.abilities, phy_ab.link_speed);
1856 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1857 phy_conf.abilities, phy_conf.link_speed);
1859 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1863 return I40E_SUCCESS;
1867 i40e_apply_link_speed(struct rte_eth_dev *dev)
1870 uint8_t abilities = 0;
1871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 struct rte_eth_conf *conf = &dev->data->dev_conf;
1874 speed = i40e_parse_link_speeds(conf->link_speeds);
1875 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1876 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1877 abilities |= I40E_AQ_PHY_AN_ENABLED;
1878 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1880 /* Skip changing speed on 40G interfaces, FW does not support */
1881 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1882 speed = I40E_LINK_SPEED_UNKNOWN;
1883 abilities |= I40E_AQ_PHY_AN_ENABLED;
1886 return i40e_phy_conf_link(hw, abilities, speed);
1890 i40e_dev_start(struct rte_eth_dev *dev)
1892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894 struct i40e_vsi *main_vsi = pf->main_vsi;
1896 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1897 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1898 uint32_t intr_vector = 0;
1899 struct i40e_vsi *vsi;
1901 hw->adapter_stopped = 0;
1903 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1904 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1905 dev->data->port_id);
1909 rte_intr_disable(intr_handle);
1911 if ((rte_intr_cap_multiple(intr_handle) ||
1912 !RTE_ETH_DEV_SRIOV(dev).active) &&
1913 dev->data->dev_conf.intr_conf.rxq != 0) {
1914 intr_vector = dev->data->nb_rx_queues;
1915 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1920 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1921 intr_handle->intr_vec =
1922 rte_zmalloc("intr_vec",
1923 dev->data->nb_rx_queues * sizeof(int),
1925 if (!intr_handle->intr_vec) {
1927 "Failed to allocate %d rx_queues intr_vec",
1928 dev->data->nb_rx_queues);
1933 /* Initialize VSI */
1934 ret = i40e_dev_rxtx_init(pf);
1935 if (ret != I40E_SUCCESS) {
1936 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1940 /* Map queues with MSIX interrupt */
1941 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1942 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1943 i40e_vsi_queues_bind_intr(main_vsi);
1944 i40e_vsi_enable_queues_intr(main_vsi);
1946 /* Map VMDQ VSI queues with MSIX interrupt */
1947 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1948 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1949 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1950 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1953 /* enable FDIR MSIX interrupt */
1954 if (pf->fdir.fdir_vsi) {
1955 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1956 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1959 /* Enable all queues which have been configured */
1960 ret = i40e_dev_switch_queues(pf, TRUE);
1961 if (ret != I40E_SUCCESS) {
1962 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1966 /* Enable receiving broadcast packets */
1967 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1968 if (ret != I40E_SUCCESS)
1969 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1971 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1972 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1974 if (ret != I40E_SUCCESS)
1975 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1978 /* Enable the VLAN promiscuous mode. */
1980 for (i = 0; i < pf->vf_num; i++) {
1981 vsi = pf->vfs[i].vsi;
1982 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1987 /* Apply link configure */
1988 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1989 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1990 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1991 ETH_LINK_SPEED_40G)) {
1992 PMD_DRV_LOG(ERR, "Invalid link setting");
1995 ret = i40e_apply_link_speed(dev);
1996 if (I40E_SUCCESS != ret) {
1997 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2001 if (!rte_intr_allow_others(intr_handle)) {
2002 rte_intr_callback_unregister(intr_handle,
2003 i40e_dev_interrupt_handler,
2005 /* configure and enable device interrupt */
2006 i40e_pf_config_irq0(hw, FALSE);
2007 i40e_pf_enable_irq0(hw);
2009 if (dev->data->dev_conf.intr_conf.lsc != 0)
2011 "lsc won't enable because of no intr multiplex");
2012 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2013 ret = i40e_aq_set_phy_int_mask(hw,
2014 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2015 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2016 I40E_AQ_EVENT_MEDIA_NA), NULL);
2017 if (ret != I40E_SUCCESS)
2018 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2020 /* Call get_link_info aq commond to enable LSE */
2021 i40e_dev_link_update(dev, 0);
2024 /* enable uio intr after callback register */
2025 rte_intr_enable(intr_handle);
2027 i40e_filter_restore(pf);
2029 return I40E_SUCCESS;
2032 i40e_dev_switch_queues(pf, FALSE);
2033 i40e_dev_clear_queues(dev);
2039 i40e_dev_stop(struct rte_eth_dev *dev)
2041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2042 struct i40e_vsi *main_vsi = pf->main_vsi;
2043 struct i40e_mirror_rule *p_mirror;
2044 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2045 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2048 /* Disable all queues */
2049 i40e_dev_switch_queues(pf, FALSE);
2051 /* un-map queues with interrupt registers */
2052 i40e_vsi_disable_queues_intr(main_vsi);
2053 i40e_vsi_queues_unbind_intr(main_vsi);
2055 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2056 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2057 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2060 if (pf->fdir.fdir_vsi) {
2061 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2062 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2064 /* Clear all queues and release memory */
2065 i40e_dev_clear_queues(dev);
2068 i40e_dev_set_link_down(dev);
2070 /* Remove all mirror rules */
2071 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2072 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2075 pf->nb_mirror_rule = 0;
2077 if (!rte_intr_allow_others(intr_handle))
2078 /* resume to the default handler */
2079 rte_intr_callback_register(intr_handle,
2080 i40e_dev_interrupt_handler,
2083 /* Clean datapath event and queue/vec mapping */
2084 rte_intr_efd_disable(intr_handle);
2085 if (intr_handle->intr_vec) {
2086 rte_free(intr_handle->intr_vec);
2087 intr_handle->intr_vec = NULL;
2092 i40e_dev_close(struct rte_eth_dev *dev)
2094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2097 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101 PMD_INIT_FUNC_TRACE();
2104 hw->adapter_stopped = 1;
2105 i40e_dev_free_queues(dev);
2107 /* Disable interrupt */
2108 i40e_pf_disable_irq0(hw);
2109 rte_intr_disable(intr_handle);
2111 /* shutdown and destroy the HMC */
2112 i40e_shutdown_lan_hmc(hw);
2114 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2115 i40e_vsi_release(pf->vmdq[i].vsi);
2116 pf->vmdq[i].vsi = NULL;
2121 /* release all the existing VSIs and VEBs */
2122 i40e_fdir_teardown(pf);
2123 i40e_vsi_release(pf->main_vsi);
2125 /* shutdown the adminq */
2126 i40e_aq_queue_shutdown(hw, true);
2127 i40e_shutdown_adminq(hw);
2129 i40e_res_pool_destroy(&pf->qp_pool);
2130 i40e_res_pool_destroy(&pf->msix_pool);
2132 /* force a PF reset to clean anything leftover */
2133 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2134 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2135 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2136 I40E_WRITE_FLUSH(hw);
2140 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2142 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct i40e_vsi *vsi = pf->main_vsi;
2147 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2149 if (status != I40E_SUCCESS)
2150 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2152 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2154 if (status != I40E_SUCCESS)
2155 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2160 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2162 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2163 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 struct i40e_vsi *vsi = pf->main_vsi;
2167 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2169 if (status != I40E_SUCCESS)
2170 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2172 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2174 if (status != I40E_SUCCESS)
2175 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2179 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 struct i40e_vsi *vsi = pf->main_vsi;
2186 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2187 if (ret != I40E_SUCCESS)
2188 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2192 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2194 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2195 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196 struct i40e_vsi *vsi = pf->main_vsi;
2199 if (dev->data->promiscuous == 1)
2200 return; /* must remain in all_multicast mode */
2202 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2203 vsi->seid, FALSE, NULL);
2204 if (ret != I40E_SUCCESS)
2205 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2209 * Set device link up.
2212 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2214 /* re-apply link speed setting */
2215 return i40e_apply_link_speed(dev);
2219 * Set device link down.
2222 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2224 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2225 uint8_t abilities = 0;
2226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2229 return i40e_phy_conf_link(hw, abilities, speed);
2233 i40e_dev_link_update(struct rte_eth_dev *dev,
2234 int wait_to_complete)
2236 #define CHECK_INTERVAL 100 /* 100ms */
2237 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_link_status link_status;
2240 struct rte_eth_link link, old;
2242 unsigned rep_cnt = MAX_REPEAT_TIME;
2243 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2245 memset(&link, 0, sizeof(link));
2246 memset(&old, 0, sizeof(old));
2247 memset(&link_status, 0, sizeof(link_status));
2248 rte_i40e_dev_atomic_read_link_status(dev, &old);
2251 /* Get link status information from hardware */
2252 status = i40e_aq_get_link_info(hw, enable_lse,
2253 &link_status, NULL);
2254 if (status != I40E_SUCCESS) {
2255 link.link_speed = ETH_SPEED_NUM_100M;
2256 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2257 PMD_DRV_LOG(ERR, "Failed to get link info");
2261 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2262 if (!wait_to_complete || link.link_status)
2265 rte_delay_ms(CHECK_INTERVAL);
2266 } while (--rep_cnt);
2268 if (!link.link_status)
2271 /* i40e uses full duplex only */
2272 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2274 /* Parse the link status */
2275 switch (link_status.link_speed) {
2276 case I40E_LINK_SPEED_100MB:
2277 link.link_speed = ETH_SPEED_NUM_100M;
2279 case I40E_LINK_SPEED_1GB:
2280 link.link_speed = ETH_SPEED_NUM_1G;
2282 case I40E_LINK_SPEED_10GB:
2283 link.link_speed = ETH_SPEED_NUM_10G;
2285 case I40E_LINK_SPEED_20GB:
2286 link.link_speed = ETH_SPEED_NUM_20G;
2288 case I40E_LINK_SPEED_25GB:
2289 link.link_speed = ETH_SPEED_NUM_25G;
2291 case I40E_LINK_SPEED_40GB:
2292 link.link_speed = ETH_SPEED_NUM_40G;
2295 link.link_speed = ETH_SPEED_NUM_100M;
2299 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2300 ETH_LINK_SPEED_FIXED);
2303 rte_i40e_dev_atomic_write_link_status(dev, &link);
2304 if (link.link_status == old.link_status)
2310 /* Get all the statistics of a VSI */
2312 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2314 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2315 struct i40e_eth_stats *nes = &vsi->eth_stats;
2316 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2317 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2319 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2320 vsi->offset_loaded, &oes->rx_bytes,
2322 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2323 vsi->offset_loaded, &oes->rx_unicast,
2325 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2326 vsi->offset_loaded, &oes->rx_multicast,
2327 &nes->rx_multicast);
2328 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2329 vsi->offset_loaded, &oes->rx_broadcast,
2330 &nes->rx_broadcast);
2331 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2332 &oes->rx_discards, &nes->rx_discards);
2333 /* GLV_REPC not supported */
2334 /* GLV_RMPC not supported */
2335 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2336 &oes->rx_unknown_protocol,
2337 &nes->rx_unknown_protocol);
2338 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2339 vsi->offset_loaded, &oes->tx_bytes,
2341 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2342 vsi->offset_loaded, &oes->tx_unicast,
2344 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2345 vsi->offset_loaded, &oes->tx_multicast,
2346 &nes->tx_multicast);
2347 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2348 vsi->offset_loaded, &oes->tx_broadcast,
2349 &nes->tx_broadcast);
2350 /* GLV_TDPC not supported */
2351 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2352 &oes->tx_errors, &nes->tx_errors);
2353 vsi->offset_loaded = true;
2355 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2357 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2358 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2359 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2360 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2361 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2362 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2363 nes->rx_unknown_protocol);
2364 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2365 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2366 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2367 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2368 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2369 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2370 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2375 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2378 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2379 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2381 /* Get statistics of struct i40e_eth_stats */
2382 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2383 I40E_GLPRT_GORCL(hw->port),
2384 pf->offset_loaded, &os->eth.rx_bytes,
2386 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2387 I40E_GLPRT_UPRCL(hw->port),
2388 pf->offset_loaded, &os->eth.rx_unicast,
2389 &ns->eth.rx_unicast);
2390 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2391 I40E_GLPRT_MPRCL(hw->port),
2392 pf->offset_loaded, &os->eth.rx_multicast,
2393 &ns->eth.rx_multicast);
2394 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2395 I40E_GLPRT_BPRCL(hw->port),
2396 pf->offset_loaded, &os->eth.rx_broadcast,
2397 &ns->eth.rx_broadcast);
2398 /* Workaround: CRC size should not be included in byte statistics,
2399 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2401 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2402 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2404 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2405 pf->offset_loaded, &os->eth.rx_discards,
2406 &ns->eth.rx_discards);
2407 /* GLPRT_REPC not supported */
2408 /* GLPRT_RMPC not supported */
2409 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2411 &os->eth.rx_unknown_protocol,
2412 &ns->eth.rx_unknown_protocol);
2413 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2414 I40E_GLPRT_GOTCL(hw->port),
2415 pf->offset_loaded, &os->eth.tx_bytes,
2417 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2418 I40E_GLPRT_UPTCL(hw->port),
2419 pf->offset_loaded, &os->eth.tx_unicast,
2420 &ns->eth.tx_unicast);
2421 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2422 I40E_GLPRT_MPTCL(hw->port),
2423 pf->offset_loaded, &os->eth.tx_multicast,
2424 &ns->eth.tx_multicast);
2425 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2426 I40E_GLPRT_BPTCL(hw->port),
2427 pf->offset_loaded, &os->eth.tx_broadcast,
2428 &ns->eth.tx_broadcast);
2429 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2430 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2431 /* GLPRT_TEPC not supported */
2433 /* additional port specific stats */
2434 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2435 pf->offset_loaded, &os->tx_dropped_link_down,
2436 &ns->tx_dropped_link_down);
2437 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2438 pf->offset_loaded, &os->crc_errors,
2440 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2441 pf->offset_loaded, &os->illegal_bytes,
2442 &ns->illegal_bytes);
2443 /* GLPRT_ERRBC not supported */
2444 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2445 pf->offset_loaded, &os->mac_local_faults,
2446 &ns->mac_local_faults);
2447 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2448 pf->offset_loaded, &os->mac_remote_faults,
2449 &ns->mac_remote_faults);
2450 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2451 pf->offset_loaded, &os->rx_length_errors,
2452 &ns->rx_length_errors);
2453 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2454 pf->offset_loaded, &os->link_xon_rx,
2456 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2457 pf->offset_loaded, &os->link_xoff_rx,
2459 for (i = 0; i < 8; i++) {
2460 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2462 &os->priority_xon_rx[i],
2463 &ns->priority_xon_rx[i]);
2464 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2466 &os->priority_xoff_rx[i],
2467 &ns->priority_xoff_rx[i]);
2469 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2470 pf->offset_loaded, &os->link_xon_tx,
2472 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2473 pf->offset_loaded, &os->link_xoff_tx,
2475 for (i = 0; i < 8; i++) {
2476 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2478 &os->priority_xon_tx[i],
2479 &ns->priority_xon_tx[i]);
2480 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2482 &os->priority_xoff_tx[i],
2483 &ns->priority_xoff_tx[i]);
2484 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2486 &os->priority_xon_2_xoff[i],
2487 &ns->priority_xon_2_xoff[i]);
2489 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2490 I40E_GLPRT_PRC64L(hw->port),
2491 pf->offset_loaded, &os->rx_size_64,
2493 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2494 I40E_GLPRT_PRC127L(hw->port),
2495 pf->offset_loaded, &os->rx_size_127,
2497 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2498 I40E_GLPRT_PRC255L(hw->port),
2499 pf->offset_loaded, &os->rx_size_255,
2501 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2502 I40E_GLPRT_PRC511L(hw->port),
2503 pf->offset_loaded, &os->rx_size_511,
2505 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2506 I40E_GLPRT_PRC1023L(hw->port),
2507 pf->offset_loaded, &os->rx_size_1023,
2509 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2510 I40E_GLPRT_PRC1522L(hw->port),
2511 pf->offset_loaded, &os->rx_size_1522,
2513 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2514 I40E_GLPRT_PRC9522L(hw->port),
2515 pf->offset_loaded, &os->rx_size_big,
2517 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2518 pf->offset_loaded, &os->rx_undersize,
2520 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2521 pf->offset_loaded, &os->rx_fragments,
2523 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2524 pf->offset_loaded, &os->rx_oversize,
2526 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2527 pf->offset_loaded, &os->rx_jabber,
2529 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2530 I40E_GLPRT_PTC64L(hw->port),
2531 pf->offset_loaded, &os->tx_size_64,
2533 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2534 I40E_GLPRT_PTC127L(hw->port),
2535 pf->offset_loaded, &os->tx_size_127,
2537 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2538 I40E_GLPRT_PTC255L(hw->port),
2539 pf->offset_loaded, &os->tx_size_255,
2541 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2542 I40E_GLPRT_PTC511L(hw->port),
2543 pf->offset_loaded, &os->tx_size_511,
2545 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2546 I40E_GLPRT_PTC1023L(hw->port),
2547 pf->offset_loaded, &os->tx_size_1023,
2549 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2550 I40E_GLPRT_PTC1522L(hw->port),
2551 pf->offset_loaded, &os->tx_size_1522,
2553 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2554 I40E_GLPRT_PTC9522L(hw->port),
2555 pf->offset_loaded, &os->tx_size_big,
2557 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2559 &os->fd_sb_match, &ns->fd_sb_match);
2560 /* GLPRT_MSPDC not supported */
2561 /* GLPRT_XEC not supported */
2563 pf->offset_loaded = true;
2566 i40e_update_vsi_stats(pf->main_vsi);
2569 /* Get all statistics of a port */
2571 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2573 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2578 /* call read registers - updates values, now write them to struct */
2579 i40e_read_stats_registers(pf, hw);
2581 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2582 pf->main_vsi->eth_stats.rx_multicast +
2583 pf->main_vsi->eth_stats.rx_broadcast -
2584 pf->main_vsi->eth_stats.rx_discards;
2585 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2586 pf->main_vsi->eth_stats.tx_multicast +
2587 pf->main_vsi->eth_stats.tx_broadcast;
2588 stats->ibytes = ns->eth.rx_bytes;
2589 stats->obytes = ns->eth.tx_bytes;
2590 stats->oerrors = ns->eth.tx_errors +
2591 pf->main_vsi->eth_stats.tx_errors;
2594 stats->imissed = ns->eth.rx_discards +
2595 pf->main_vsi->eth_stats.rx_discards;
2596 stats->ierrors = ns->crc_errors +
2597 ns->rx_length_errors + ns->rx_undersize +
2598 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2600 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2601 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2602 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2603 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2604 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2605 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2606 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2607 ns->eth.rx_unknown_protocol);
2608 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2609 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2610 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2611 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2612 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2613 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2615 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2616 ns->tx_dropped_link_down);
2617 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2618 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2620 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2621 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2622 ns->mac_local_faults);
2623 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2624 ns->mac_remote_faults);
2625 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2626 ns->rx_length_errors);
2627 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2628 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2629 for (i = 0; i < 8; i++) {
2630 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2631 i, ns->priority_xon_rx[i]);
2632 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2633 i, ns->priority_xoff_rx[i]);
2635 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2636 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2637 for (i = 0; i < 8; i++) {
2638 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2639 i, ns->priority_xon_tx[i]);
2640 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2641 i, ns->priority_xoff_tx[i]);
2642 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2643 i, ns->priority_xon_2_xoff[i]);
2645 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2646 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2647 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2648 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2649 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2650 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2651 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2652 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2653 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2654 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2655 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2656 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2657 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2658 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2659 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2660 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2661 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2662 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2663 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2664 ns->mac_short_packet_dropped);
2665 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2666 ns->checksum_error);
2667 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2668 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2671 /* Reset the statistics */
2673 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2675 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678 /* Mark PF and VSI stats to update the offset, aka "reset" */
2679 pf->offset_loaded = false;
2681 pf->main_vsi->offset_loaded = false;
2683 /* read the stats, reading current register values into offset */
2684 i40e_read_stats_registers(pf, hw);
2688 i40e_xstats_calc_num(void)
2690 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2691 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2692 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2695 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2696 struct rte_eth_xstat_name *xstats_names,
2697 __rte_unused unsigned limit)
2702 if (xstats_names == NULL)
2703 return i40e_xstats_calc_num();
2705 /* Note: limit checked in rte_eth_xstats_names() */
2707 /* Get stats from i40e_eth_stats struct */
2708 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2709 snprintf(xstats_names[count].name,
2710 sizeof(xstats_names[count].name),
2711 "%s", rte_i40e_stats_strings[i].name);
2715 /* Get individiual stats from i40e_hw_port struct */
2716 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2717 snprintf(xstats_names[count].name,
2718 sizeof(xstats_names[count].name),
2719 "%s", rte_i40e_hw_port_strings[i].name);
2723 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2724 for (prio = 0; prio < 8; prio++) {
2725 snprintf(xstats_names[count].name,
2726 sizeof(xstats_names[count].name),
2727 "rx_priority%u_%s", prio,
2728 rte_i40e_rxq_prio_strings[i].name);
2733 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2734 for (prio = 0; prio < 8; prio++) {
2735 snprintf(xstats_names[count].name,
2736 sizeof(xstats_names[count].name),
2737 "tx_priority%u_%s", prio,
2738 rte_i40e_txq_prio_strings[i].name);
2746 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2749 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751 unsigned i, count, prio;
2752 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2754 count = i40e_xstats_calc_num();
2758 i40e_read_stats_registers(pf, hw);
2765 /* Get stats from i40e_eth_stats struct */
2766 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2767 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2768 rte_i40e_stats_strings[i].offset);
2769 xstats[count].id = count;
2773 /* Get individiual stats from i40e_hw_port struct */
2774 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2775 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2776 rte_i40e_hw_port_strings[i].offset);
2777 xstats[count].id = count;
2781 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2782 for (prio = 0; prio < 8; prio++) {
2783 xstats[count].value =
2784 *(uint64_t *)(((char *)hw_stats) +
2785 rte_i40e_rxq_prio_strings[i].offset +
2786 (sizeof(uint64_t) * prio));
2787 xstats[count].id = count;
2792 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2793 for (prio = 0; prio < 8; prio++) {
2794 xstats[count].value =
2795 *(uint64_t *)(((char *)hw_stats) +
2796 rte_i40e_txq_prio_strings[i].offset +
2797 (sizeof(uint64_t) * prio));
2798 xstats[count].id = count;
2807 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2808 __rte_unused uint16_t queue_id,
2809 __rte_unused uint8_t stat_idx,
2810 __rte_unused uint8_t is_rx)
2812 PMD_INIT_FUNC_TRACE();
2818 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826 full_ver = hw->nvm.oem_ver;
2827 ver = (u8)(full_ver >> 24);
2828 build = (u16)((full_ver >> 8) & 0xffff);
2829 patch = (u8)(full_ver & 0xff);
2831 ret = snprintf(fw_version, fw_size,
2832 "%d.%d%d 0x%08x %d.%d.%d",
2833 ((hw->nvm.version >> 12) & 0xf),
2834 ((hw->nvm.version >> 4) & 0xff),
2835 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2838 ret += 1; /* add the size of '\0' */
2839 if (fw_size < (u32)ret)
2846 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2848 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850 struct i40e_vsi *vsi = pf->main_vsi;
2851 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2853 dev_info->pci_dev = pci_dev;
2854 dev_info->max_rx_queues = vsi->nb_qps;
2855 dev_info->max_tx_queues = vsi->nb_qps;
2856 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2857 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2858 dev_info->max_mac_addrs = vsi->max_macaddrs;
2859 dev_info->max_vfs = pci_dev->max_vfs;
2860 dev_info->rx_offload_capa =
2861 DEV_RX_OFFLOAD_VLAN_STRIP |
2862 DEV_RX_OFFLOAD_QINQ_STRIP |
2863 DEV_RX_OFFLOAD_IPV4_CKSUM |
2864 DEV_RX_OFFLOAD_UDP_CKSUM |
2865 DEV_RX_OFFLOAD_TCP_CKSUM;
2866 dev_info->tx_offload_capa =
2867 DEV_TX_OFFLOAD_VLAN_INSERT |
2868 DEV_TX_OFFLOAD_QINQ_INSERT |
2869 DEV_TX_OFFLOAD_IPV4_CKSUM |
2870 DEV_TX_OFFLOAD_UDP_CKSUM |
2871 DEV_TX_OFFLOAD_TCP_CKSUM |
2872 DEV_TX_OFFLOAD_SCTP_CKSUM |
2873 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2874 DEV_TX_OFFLOAD_TCP_TSO |
2875 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2876 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2877 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2878 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2879 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2881 dev_info->reta_size = pf->hash_lut_size;
2882 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2884 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2886 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2887 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2888 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2890 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2894 dev_info->default_txconf = (struct rte_eth_txconf) {
2896 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2897 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2898 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2900 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2901 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2902 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2903 ETH_TXQ_FLAGS_NOOFFLOADS,
2906 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2907 .nb_max = I40E_MAX_RING_DESC,
2908 .nb_min = I40E_MIN_RING_DESC,
2909 .nb_align = I40E_ALIGN_RING_DESC,
2912 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2913 .nb_max = I40E_MAX_RING_DESC,
2914 .nb_min = I40E_MIN_RING_DESC,
2915 .nb_align = I40E_ALIGN_RING_DESC,
2916 .nb_seg_max = I40E_TX_MAX_SEG,
2917 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2920 if (pf->flags & I40E_FLAG_VMDQ) {
2921 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2922 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2923 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2924 pf->max_nb_vmdq_vsi;
2925 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2926 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2927 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2930 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2932 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2933 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2935 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2938 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2942 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2944 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2945 struct i40e_vsi *vsi = pf->main_vsi;
2946 PMD_INIT_FUNC_TRACE();
2949 return i40e_vsi_add_vlan(vsi, vlan_id);
2951 return i40e_vsi_delete_vlan(vsi, vlan_id);
2955 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2956 enum rte_vlan_type vlan_type,
2959 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960 uint64_t reg_r = 0, reg_w = 0;
2961 uint16_t reg_id = 0;
2963 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2965 switch (vlan_type) {
2966 case ETH_VLAN_TYPE_OUTER:
2972 case ETH_VLAN_TYPE_INNER:
2978 "Unsupported vlan type in single vlan.");
2984 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2987 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2989 if (ret != I40E_SUCCESS) {
2991 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2997 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3000 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3001 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3002 if (reg_r == reg_w) {
3004 PMD_DRV_LOG(DEBUG, "No need to write");
3008 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3010 if (ret != I40E_SUCCESS) {
3013 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3018 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3025 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3027 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3028 struct i40e_vsi *vsi = pf->main_vsi;
3030 if (mask & ETH_VLAN_FILTER_MASK) {
3031 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3032 i40e_vsi_config_vlan_filter(vsi, TRUE);
3034 i40e_vsi_config_vlan_filter(vsi, FALSE);
3037 if (mask & ETH_VLAN_STRIP_MASK) {
3038 /* Enable or disable VLAN stripping */
3039 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3040 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3042 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3045 if (mask & ETH_VLAN_EXTEND_MASK) {
3046 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3047 i40e_vsi_config_double_vlan(vsi, TRUE);
3048 /* Set global registers with default ether type value */
3049 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3051 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3055 i40e_vsi_config_double_vlan(vsi, FALSE);
3060 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3061 __rte_unused uint16_t queue,
3062 __rte_unused int on)
3064 PMD_INIT_FUNC_TRACE();
3068 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3070 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3071 struct i40e_vsi *vsi = pf->main_vsi;
3072 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3073 struct i40e_vsi_vlan_pvid_info info;
3075 memset(&info, 0, sizeof(info));
3078 info.config.pvid = pvid;
3080 info.config.reject.tagged =
3081 data->dev_conf.txmode.hw_vlan_reject_tagged;
3082 info.config.reject.untagged =
3083 data->dev_conf.txmode.hw_vlan_reject_untagged;
3086 return i40e_vsi_vlan_pvid_set(vsi, &info);
3090 i40e_dev_led_on(struct rte_eth_dev *dev)
3092 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3093 uint32_t mode = i40e_led_get(hw);
3096 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3102 i40e_dev_led_off(struct rte_eth_dev *dev)
3104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105 uint32_t mode = i40e_led_get(hw);
3108 i40e_led_set(hw, 0, false);
3114 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3116 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119 fc_conf->pause_time = pf->fc_conf.pause_time;
3120 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3121 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3123 /* Return current mode according to actual setting*/
3124 switch (hw->fc.current_mode) {
3126 fc_conf->mode = RTE_FC_FULL;
3128 case I40E_FC_TX_PAUSE:
3129 fc_conf->mode = RTE_FC_TX_PAUSE;
3131 case I40E_FC_RX_PAUSE:
3132 fc_conf->mode = RTE_FC_RX_PAUSE;
3136 fc_conf->mode = RTE_FC_NONE;
3143 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3145 uint32_t mflcn_reg, fctrl_reg, reg;
3146 uint32_t max_high_water;
3147 uint8_t i, aq_failure;
3151 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3152 [RTE_FC_NONE] = I40E_FC_NONE,
3153 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3154 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3155 [RTE_FC_FULL] = I40E_FC_FULL
3158 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3160 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3161 if ((fc_conf->high_water > max_high_water) ||
3162 (fc_conf->high_water < fc_conf->low_water)) {
3164 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3169 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3170 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3173 pf->fc_conf.pause_time = fc_conf->pause_time;
3174 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3175 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3177 PMD_INIT_FUNC_TRACE();
3179 /* All the link flow control related enable/disable register
3180 * configuration is handle by the F/W
3182 err = i40e_set_fc(hw, &aq_failure, true);
3186 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3187 /* Configure flow control refresh threshold,
3188 * the value for stat_tx_pause_refresh_timer[8]
3189 * is used for global pause operation.
3193 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3194 pf->fc_conf.pause_time);
3196 /* configure the timer value included in transmitted pause
3198 * the value for stat_tx_pause_quanta[8] is used for global
3201 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3202 pf->fc_conf.pause_time);
3204 fctrl_reg = I40E_READ_REG(hw,
3205 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3207 if (fc_conf->mac_ctrl_frame_fwd != 0)
3208 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3210 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3212 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3215 /* Configure pause time (2 TCs per register) */
3216 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3217 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3218 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3220 /* Configure flow control refresh threshold value */
3221 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3222 pf->fc_conf.pause_time / 2);
3224 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3226 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3227 *depending on configuration
3229 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3230 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3231 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3233 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3234 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3237 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3240 /* config the water marker both based on the packets and bytes */
3241 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3242 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3243 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3244 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3245 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3246 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3247 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3248 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3250 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3251 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3254 I40E_WRITE_FLUSH(hw);
3260 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3261 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3263 PMD_INIT_FUNC_TRACE();
3268 /* Add a MAC address, and update filters */
3270 i40e_macaddr_add(struct rte_eth_dev *dev,
3271 struct ether_addr *mac_addr,
3272 __rte_unused uint32_t index,
3275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3276 struct i40e_mac_filter_info mac_filter;
3277 struct i40e_vsi *vsi;
3280 /* If VMDQ not enabled or configured, return */
3281 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3282 !pf->nb_cfg_vmdq_vsi)) {
3283 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3284 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3289 if (pool > pf->nb_cfg_vmdq_vsi) {
3290 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3291 pool, pf->nb_cfg_vmdq_vsi);
3295 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3296 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3297 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3299 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3304 vsi = pf->vmdq[pool - 1].vsi;
3306 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3307 if (ret != I40E_SUCCESS) {
3308 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3313 /* Remove a MAC address, and update filters */
3315 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3317 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3318 struct i40e_vsi *vsi;
3319 struct rte_eth_dev_data *data = dev->data;
3320 struct ether_addr *macaddr;
3325 macaddr = &(data->mac_addrs[index]);
3327 pool_sel = dev->data->mac_pool_sel[index];
3329 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3330 if (pool_sel & (1ULL << i)) {
3334 /* No VMDQ pool enabled or configured */
3335 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3336 (i > pf->nb_cfg_vmdq_vsi)) {
3338 "No VMDQ pool enabled/configured");
3341 vsi = pf->vmdq[i - 1].vsi;
3343 ret = i40e_vsi_delete_mac(vsi, macaddr);
3346 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3353 /* Set perfect match or hash match of MAC and VLAN for a VF */
3355 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3356 struct rte_eth_mac_filter *filter,
3360 struct i40e_mac_filter_info mac_filter;
3361 struct ether_addr old_mac;
3362 struct ether_addr *new_mac;
3363 struct i40e_pf_vf *vf = NULL;
3368 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3371 hw = I40E_PF_TO_HW(pf);
3373 if (filter == NULL) {
3374 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3378 new_mac = &filter->mac_addr;
3380 if (is_zero_ether_addr(new_mac)) {
3381 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3385 vf_id = filter->dst_id;
3387 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3388 PMD_DRV_LOG(ERR, "Invalid argument.");
3391 vf = &pf->vfs[vf_id];
3393 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3394 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3399 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3400 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3402 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3405 mac_filter.filter_type = filter->filter_type;
3406 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3407 if (ret != I40E_SUCCESS) {
3408 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3411 ether_addr_copy(new_mac, &pf->dev_addr);
3413 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3415 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3416 if (ret != I40E_SUCCESS) {
3417 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3421 /* Clear device address as it has been removed */
3422 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3423 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3429 /* MAC filter handle */
3431 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3435 struct rte_eth_mac_filter *filter;
3436 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3437 int ret = I40E_NOT_SUPPORTED;
3439 filter = (struct rte_eth_mac_filter *)(arg);
3441 switch (filter_op) {
3442 case RTE_ETH_FILTER_NOP:
3445 case RTE_ETH_FILTER_ADD:
3446 i40e_pf_disable_irq0(hw);
3448 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3449 i40e_pf_enable_irq0(hw);
3451 case RTE_ETH_FILTER_DELETE:
3452 i40e_pf_disable_irq0(hw);
3454 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3455 i40e_pf_enable_irq0(hw);
3458 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3459 ret = I40E_ERR_PARAM;
3467 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3469 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3470 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3476 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3477 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3480 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3484 uint32_t *lut_dw = (uint32_t *)lut;
3485 uint16_t i, lut_size_dw = lut_size / 4;
3487 for (i = 0; i < lut_size_dw; i++)
3488 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3495 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3504 pf = I40E_VSI_TO_PF(vsi);
3505 hw = I40E_VSI_TO_HW(vsi);
3507 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3508 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3511 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3515 uint32_t *lut_dw = (uint32_t *)lut;
3516 uint16_t i, lut_size_dw = lut_size / 4;
3518 for (i = 0; i < lut_size_dw; i++)
3519 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3520 I40E_WRITE_FLUSH(hw);
3527 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3528 struct rte_eth_rss_reta_entry64 *reta_conf,
3531 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3532 uint16_t i, lut_size = pf->hash_lut_size;
3533 uint16_t idx, shift;
3537 if (reta_size != lut_size ||
3538 reta_size > ETH_RSS_RETA_SIZE_512) {
3540 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3541 reta_size, lut_size);
3545 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3547 PMD_DRV_LOG(ERR, "No memory can be allocated");
3550 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3553 for (i = 0; i < reta_size; i++) {
3554 idx = i / RTE_RETA_GROUP_SIZE;
3555 shift = i % RTE_RETA_GROUP_SIZE;
3556 if (reta_conf[idx].mask & (1ULL << shift))
3557 lut[i] = reta_conf[idx].reta[shift];
3559 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3568 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3569 struct rte_eth_rss_reta_entry64 *reta_conf,
3572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3573 uint16_t i, lut_size = pf->hash_lut_size;
3574 uint16_t idx, shift;
3578 if (reta_size != lut_size ||
3579 reta_size > ETH_RSS_RETA_SIZE_512) {
3581 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3582 reta_size, lut_size);
3586 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3588 PMD_DRV_LOG(ERR, "No memory can be allocated");
3592 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3595 for (i = 0; i < reta_size; i++) {
3596 idx = i / RTE_RETA_GROUP_SIZE;
3597 shift = i % RTE_RETA_GROUP_SIZE;
3598 if (reta_conf[idx].mask & (1ULL << shift))
3599 reta_conf[idx].reta[shift] = lut[i];
3609 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3610 * @hw: pointer to the HW structure
3611 * @mem: pointer to mem struct to fill out
3612 * @size: size of memory requested
3613 * @alignment: what to align the allocation to
3615 enum i40e_status_code
3616 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3617 struct i40e_dma_mem *mem,
3621 const struct rte_memzone *mz = NULL;
3622 char z_name[RTE_MEMZONE_NAMESIZE];
3625 return I40E_ERR_PARAM;
3627 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3628 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3629 alignment, RTE_PGSIZE_2M);
3631 return I40E_ERR_NO_MEMORY;
3635 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3636 mem->zone = (const void *)mz;
3638 "memzone %s allocated with physical address: %"PRIu64,
3641 return I40E_SUCCESS;
3645 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3646 * @hw: pointer to the HW structure
3647 * @mem: ptr to mem struct to free
3649 enum i40e_status_code
3650 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3651 struct i40e_dma_mem *mem)
3654 return I40E_ERR_PARAM;
3657 "memzone %s to be freed with physical address: %"PRIu64,
3658 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3659 rte_memzone_free((const struct rte_memzone *)mem->zone);
3664 return I40E_SUCCESS;
3668 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3669 * @hw: pointer to the HW structure
3670 * @mem: pointer to mem struct to fill out
3671 * @size: size of memory requested
3673 enum i40e_status_code
3674 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3675 struct i40e_virt_mem *mem,
3679 return I40E_ERR_PARAM;
3682 mem->va = rte_zmalloc("i40e", size, 0);
3685 return I40E_SUCCESS;
3687 return I40E_ERR_NO_MEMORY;
3691 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3692 * @hw: pointer to the HW structure
3693 * @mem: pointer to mem struct to free
3695 enum i40e_status_code
3696 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3697 struct i40e_virt_mem *mem)
3700 return I40E_ERR_PARAM;
3705 return I40E_SUCCESS;
3709 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3711 rte_spinlock_init(&sp->spinlock);
3715 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3717 rte_spinlock_lock(&sp->spinlock);
3721 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3723 rte_spinlock_unlock(&sp->spinlock);
3727 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3733 * Get the hardware capabilities, which will be parsed
3734 * and saved into struct i40e_hw.
3737 i40e_get_cap(struct i40e_hw *hw)
3739 struct i40e_aqc_list_capabilities_element_resp *buf;
3740 uint16_t len, size = 0;
3743 /* Calculate a huge enough buff for saving response data temporarily */
3744 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3745 I40E_MAX_CAP_ELE_NUM;
3746 buf = rte_zmalloc("i40e", len, 0);
3748 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3749 return I40E_ERR_NO_MEMORY;
3752 /* Get, parse the capabilities and save it to hw */
3753 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3754 i40e_aqc_opc_list_func_capabilities, NULL);
3755 if (ret != I40E_SUCCESS)
3756 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3758 /* Free the temporary buffer after being used */
3765 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3767 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3768 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3769 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3770 uint16_t qp_count = 0, vsi_count = 0;
3772 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3773 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3776 /* Add the parameter init for LFC */
3777 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3778 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3779 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3781 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3782 pf->max_num_vsi = hw->func_caps.num_vsis;
3783 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3784 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3785 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3787 /* FDir queue/VSI allocation */
3788 pf->fdir_qp_offset = 0;
3789 if (hw->func_caps.fd) {
3790 pf->flags |= I40E_FLAG_FDIR;
3791 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3793 pf->fdir_nb_qps = 0;
3795 qp_count += pf->fdir_nb_qps;
3798 /* LAN queue/VSI allocation */
3799 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3800 if (!hw->func_caps.rss) {
3803 pf->flags |= I40E_FLAG_RSS;
3804 if (hw->mac.type == I40E_MAC_X722)
3805 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3806 pf->lan_nb_qps = pf->lan_nb_qp_max;
3808 qp_count += pf->lan_nb_qps;
3811 /* VF queue/VSI allocation */
3812 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3813 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3814 pf->flags |= I40E_FLAG_SRIOV;
3815 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3816 pf->vf_num = pci_dev->max_vfs;
3818 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3819 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3824 qp_count += pf->vf_nb_qps * pf->vf_num;
3825 vsi_count += pf->vf_num;
3827 /* VMDq queue/VSI allocation */
3828 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3829 pf->vmdq_nb_qps = 0;
3830 pf->max_nb_vmdq_vsi = 0;
3831 if (hw->func_caps.vmdq) {
3832 if (qp_count < hw->func_caps.num_tx_qp &&
3833 vsi_count < hw->func_caps.num_vsis) {
3834 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3835 qp_count) / pf->vmdq_nb_qp_max;
3837 /* Limit the maximum number of VMDq vsi to the maximum
3838 * ethdev can support
3840 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3841 hw->func_caps.num_vsis - vsi_count);
3842 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3844 if (pf->max_nb_vmdq_vsi) {
3845 pf->flags |= I40E_FLAG_VMDQ;
3846 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3848 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3849 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3850 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3853 "No enough queues left for VMDq");
3856 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3859 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3860 vsi_count += pf->max_nb_vmdq_vsi;
3862 if (hw->func_caps.dcb)
3863 pf->flags |= I40E_FLAG_DCB;
3865 if (qp_count > hw->func_caps.num_tx_qp) {
3867 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3868 qp_count, hw->func_caps.num_tx_qp);
3871 if (vsi_count > hw->func_caps.num_vsis) {
3873 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3874 vsi_count, hw->func_caps.num_vsis);
3882 i40e_pf_get_switch_config(struct i40e_pf *pf)
3884 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3885 struct i40e_aqc_get_switch_config_resp *switch_config;
3886 struct i40e_aqc_switch_config_element_resp *element;
3887 uint16_t start_seid = 0, num_reported;
3890 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3891 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3892 if (!switch_config) {
3893 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3897 /* Get the switch configurations */
3898 ret = i40e_aq_get_switch_config(hw, switch_config,
3899 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3900 if (ret != I40E_SUCCESS) {
3901 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3904 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3905 if (num_reported != 1) { /* The number should be 1 */
3906 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3910 /* Parse the switch configuration elements */
3911 element = &(switch_config->element[0]);
3912 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3913 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3914 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3916 PMD_DRV_LOG(INFO, "Unknown element type");
3919 rte_free(switch_config);
3925 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3928 struct pool_entry *entry;
3930 if (pool == NULL || num == 0)
3933 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3934 if (entry == NULL) {
3935 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3939 /* queue heap initialize */
3940 pool->num_free = num;
3941 pool->num_alloc = 0;
3943 LIST_INIT(&pool->alloc_list);
3944 LIST_INIT(&pool->free_list);
3946 /* Initialize element */
3950 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3955 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3957 struct pool_entry *entry, *next_entry;
3962 for (entry = LIST_FIRST(&pool->alloc_list);
3963 entry && (next_entry = LIST_NEXT(entry, next), 1);
3964 entry = next_entry) {
3965 LIST_REMOVE(entry, next);
3969 for (entry = LIST_FIRST(&pool->free_list);
3970 entry && (next_entry = LIST_NEXT(entry, next), 1);
3971 entry = next_entry) {
3972 LIST_REMOVE(entry, next);
3977 pool->num_alloc = 0;
3979 LIST_INIT(&pool->alloc_list);
3980 LIST_INIT(&pool->free_list);
3984 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3987 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3988 uint32_t pool_offset;
3992 PMD_DRV_LOG(ERR, "Invalid parameter");
3996 pool_offset = base - pool->base;
3997 /* Lookup in alloc list */
3998 LIST_FOREACH(entry, &pool->alloc_list, next) {
3999 if (entry->base == pool_offset) {
4000 valid_entry = entry;
4001 LIST_REMOVE(entry, next);
4006 /* Not find, return */
4007 if (valid_entry == NULL) {
4008 PMD_DRV_LOG(ERR, "Failed to find entry");
4013 * Found it, move it to free list and try to merge.
4014 * In order to make merge easier, always sort it by qbase.
4015 * Find adjacent prev and last entries.
4018 LIST_FOREACH(entry, &pool->free_list, next) {
4019 if (entry->base > valid_entry->base) {
4027 /* Try to merge with next one*/
4029 /* Merge with next one */
4030 if (valid_entry->base + valid_entry->len == next->base) {
4031 next->base = valid_entry->base;
4032 next->len += valid_entry->len;
4033 rte_free(valid_entry);
4040 /* Merge with previous one */
4041 if (prev->base + prev->len == valid_entry->base) {
4042 prev->len += valid_entry->len;
4043 /* If it merge with next one, remove next node */
4045 LIST_REMOVE(valid_entry, next);
4046 rte_free(valid_entry);
4048 rte_free(valid_entry);
4054 /* Not find any entry to merge, insert */
4057 LIST_INSERT_AFTER(prev, valid_entry, next);
4058 else if (next != NULL)
4059 LIST_INSERT_BEFORE(next, valid_entry, next);
4060 else /* It's empty list, insert to head */
4061 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4064 pool->num_free += valid_entry->len;
4065 pool->num_alloc -= valid_entry->len;
4071 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4074 struct pool_entry *entry, *valid_entry;
4076 if (pool == NULL || num == 0) {
4077 PMD_DRV_LOG(ERR, "Invalid parameter");
4081 if (pool->num_free < num) {
4082 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4083 num, pool->num_free);
4088 /* Lookup in free list and find most fit one */
4089 LIST_FOREACH(entry, &pool->free_list, next) {
4090 if (entry->len >= num) {
4092 if (entry->len == num) {
4093 valid_entry = entry;
4096 if (valid_entry == NULL || valid_entry->len > entry->len)
4097 valid_entry = entry;
4101 /* Not find one to satisfy the request, return */
4102 if (valid_entry == NULL) {
4103 PMD_DRV_LOG(ERR, "No valid entry found");
4107 * The entry have equal queue number as requested,
4108 * remove it from alloc_list.
4110 if (valid_entry->len == num) {
4111 LIST_REMOVE(valid_entry, next);
4114 * The entry have more numbers than requested,
4115 * create a new entry for alloc_list and minus its
4116 * queue base and number in free_list.
4118 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4119 if (entry == NULL) {
4121 "Failed to allocate memory for resource pool");
4124 entry->base = valid_entry->base;
4126 valid_entry->base += num;
4127 valid_entry->len -= num;
4128 valid_entry = entry;
4131 /* Insert it into alloc list, not sorted */
4132 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4134 pool->num_free -= valid_entry->len;
4135 pool->num_alloc += valid_entry->len;
4137 return valid_entry->base + pool->base;
4141 * bitmap_is_subset - Check whether src2 is subset of src1
4144 bitmap_is_subset(uint8_t src1, uint8_t src2)
4146 return !((src1 ^ src2) & src2);
4149 static enum i40e_status_code
4150 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4152 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4154 /* If DCB is not supported, only default TC is supported */
4155 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4156 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4157 return I40E_NOT_SUPPORTED;
4160 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4162 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4163 hw->func_caps.enabled_tcmap, enabled_tcmap);
4164 return I40E_NOT_SUPPORTED;
4166 return I40E_SUCCESS;
4170 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4171 struct i40e_vsi_vlan_pvid_info *info)
4174 struct i40e_vsi_context ctxt;
4175 uint8_t vlan_flags = 0;
4178 if (vsi == NULL || info == NULL) {
4179 PMD_DRV_LOG(ERR, "invalid parameters");
4180 return I40E_ERR_PARAM;
4184 vsi->info.pvid = info->config.pvid;
4186 * If insert pvid is enabled, only tagged pkts are
4187 * allowed to be sent out.
4189 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4190 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4193 if (info->config.reject.tagged == 0)
4194 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4196 if (info->config.reject.untagged == 0)
4197 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4199 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4200 I40E_AQ_VSI_PVLAN_MODE_MASK);
4201 vsi->info.port_vlan_flags |= vlan_flags;
4202 vsi->info.valid_sections =
4203 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4204 memset(&ctxt, 0, sizeof(ctxt));
4205 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4206 ctxt.seid = vsi->seid;
4208 hw = I40E_VSI_TO_HW(vsi);
4209 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4210 if (ret != I40E_SUCCESS)
4211 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4217 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4219 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4221 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4223 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4224 if (ret != I40E_SUCCESS)
4228 PMD_DRV_LOG(ERR, "seid not valid");
4232 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4233 tc_bw_data.tc_valid_bits = enabled_tcmap;
4234 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4235 tc_bw_data.tc_bw_credits[i] =
4236 (enabled_tcmap & (1 << i)) ? 1 : 0;
4238 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4239 if (ret != I40E_SUCCESS) {
4240 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4244 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4245 sizeof(vsi->info.qs_handle));
4246 return I40E_SUCCESS;
4249 static enum i40e_status_code
4250 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4251 struct i40e_aqc_vsi_properties_data *info,
4252 uint8_t enabled_tcmap)
4254 enum i40e_status_code ret;
4255 int i, total_tc = 0;
4256 uint16_t qpnum_per_tc, bsf, qp_idx;
4258 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4259 if (ret != I40E_SUCCESS)
4262 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4263 if (enabled_tcmap & (1 << i))
4265 vsi->enabled_tc = enabled_tcmap;
4267 /* Number of queues per enabled TC */
4268 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4269 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4270 bsf = rte_bsf32(qpnum_per_tc);
4272 /* Adjust the queue number to actual queues that can be applied */
4273 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4274 vsi->nb_qps = qpnum_per_tc * total_tc;
4277 * Configure TC and queue mapping parameters, for enabled TC,
4278 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4279 * default queue will serve it.
4282 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4283 if (vsi->enabled_tc & (1 << i)) {
4284 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4285 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4286 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4287 qp_idx += qpnum_per_tc;
4289 info->tc_mapping[i] = 0;
4292 /* Associate queue number with VSI */
4293 if (vsi->type == I40E_VSI_SRIOV) {
4294 info->mapping_flags |=
4295 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4296 for (i = 0; i < vsi->nb_qps; i++)
4297 info->queue_mapping[i] =
4298 rte_cpu_to_le_16(vsi->base_queue + i);
4300 info->mapping_flags |=
4301 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4302 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4304 info->valid_sections |=
4305 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4307 return I40E_SUCCESS;
4311 i40e_veb_release(struct i40e_veb *veb)
4313 struct i40e_vsi *vsi;
4319 if (!TAILQ_EMPTY(&veb->head)) {
4320 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4323 /* associate_vsi field is NULL for floating VEB */
4324 if (veb->associate_vsi != NULL) {
4325 vsi = veb->associate_vsi;
4326 hw = I40E_VSI_TO_HW(vsi);
4328 vsi->uplink_seid = veb->uplink_seid;
4331 veb->associate_pf->main_vsi->floating_veb = NULL;
4332 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4335 i40e_aq_delete_element(hw, veb->seid, NULL);
4337 return I40E_SUCCESS;
4341 static struct i40e_veb *
4342 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4344 struct i40e_veb *veb;
4350 "veb setup failed, associated PF shouldn't null");
4353 hw = I40E_PF_TO_HW(pf);
4355 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4357 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4361 veb->associate_vsi = vsi;
4362 veb->associate_pf = pf;
4363 TAILQ_INIT(&veb->head);
4364 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4366 /* create floating veb if vsi is NULL */
4368 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4369 I40E_DEFAULT_TCMAP, false,
4370 &veb->seid, false, NULL);
4372 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4373 true, &veb->seid, false, NULL);
4376 if (ret != I40E_SUCCESS) {
4377 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4378 hw->aq.asq_last_status);
4381 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4383 /* get statistics index */
4384 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4385 &veb->stats_idx, NULL, NULL, NULL);
4386 if (ret != I40E_SUCCESS) {
4387 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4388 hw->aq.asq_last_status);
4391 /* Get VEB bandwidth, to be implemented */
4392 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4394 vsi->uplink_seid = veb->seid;
4403 i40e_vsi_release(struct i40e_vsi *vsi)
4407 struct i40e_vsi_list *vsi_list;
4410 struct i40e_mac_filter *f;
4411 uint16_t user_param;
4414 return I40E_SUCCESS;
4419 user_param = vsi->user_param;
4421 pf = I40E_VSI_TO_PF(vsi);
4422 hw = I40E_VSI_TO_HW(vsi);
4424 /* VSI has child to attach, release child first */
4426 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4427 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4430 i40e_veb_release(vsi->veb);
4433 if (vsi->floating_veb) {
4434 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4435 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4440 /* Remove all macvlan filters of the VSI */
4441 i40e_vsi_remove_all_macvlan_filter(vsi);
4442 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4445 if (vsi->type != I40E_VSI_MAIN &&
4446 ((vsi->type != I40E_VSI_SRIOV) ||
4447 !pf->floating_veb_list[user_param])) {
4448 /* Remove vsi from parent's sibling list */
4449 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4450 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4451 return I40E_ERR_PARAM;
4453 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4454 &vsi->sib_vsi_list, list);
4456 /* Remove all switch element of the VSI */
4457 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4458 if (ret != I40E_SUCCESS)
4459 PMD_DRV_LOG(ERR, "Failed to delete element");
4462 if ((vsi->type == I40E_VSI_SRIOV) &&
4463 pf->floating_veb_list[user_param]) {
4464 /* Remove vsi from parent's sibling list */
4465 if (vsi->parent_vsi == NULL ||
4466 vsi->parent_vsi->floating_veb == NULL) {
4467 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4468 return I40E_ERR_PARAM;
4470 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4471 &vsi->sib_vsi_list, list);
4473 /* Remove all switch element of the VSI */
4474 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4475 if (ret != I40E_SUCCESS)
4476 PMD_DRV_LOG(ERR, "Failed to delete element");
4479 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4481 if (vsi->type != I40E_VSI_SRIOV)
4482 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4485 return I40E_SUCCESS;
4489 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4491 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4492 struct i40e_aqc_remove_macvlan_element_data def_filter;
4493 struct i40e_mac_filter_info filter;
4496 if (vsi->type != I40E_VSI_MAIN)
4497 return I40E_ERR_CONFIG;
4498 memset(&def_filter, 0, sizeof(def_filter));
4499 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4501 def_filter.vlan_tag = 0;
4502 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4503 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4504 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4505 if (ret != I40E_SUCCESS) {
4506 struct i40e_mac_filter *f;
4507 struct ether_addr *mac;
4509 PMD_DRV_LOG(WARNING,
4510 "Cannot remove the default macvlan filter");
4511 /* It needs to add the permanent mac into mac list */
4512 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4514 PMD_DRV_LOG(ERR, "failed to allocate memory");
4515 return I40E_ERR_NO_MEMORY;
4517 mac = &f->mac_info.mac_addr;
4518 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4520 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4521 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4526 (void)rte_memcpy(&filter.mac_addr,
4527 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4528 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4529 return i40e_vsi_add_mac(vsi, &filter);
4533 * i40e_vsi_get_bw_config - Query VSI BW Information
4534 * @vsi: the VSI to be queried
4536 * Returns 0 on success, negative value on failure
4538 static enum i40e_status_code
4539 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4541 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4542 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4543 struct i40e_hw *hw = &vsi->adapter->hw;
4548 memset(&bw_config, 0, sizeof(bw_config));
4549 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4550 if (ret != I40E_SUCCESS) {
4551 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4552 hw->aq.asq_last_status);
4556 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4557 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4558 &ets_sla_config, NULL);
4559 if (ret != I40E_SUCCESS) {
4561 "VSI failed to get TC bandwdith configuration %u",
4562 hw->aq.asq_last_status);
4566 /* store and print out BW info */
4567 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4568 vsi->bw_info.bw_max = bw_config.max_bw;
4569 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4570 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4571 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4572 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4574 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4575 vsi->bw_info.bw_ets_share_credits[i] =
4576 ets_sla_config.share_credits[i];
4577 vsi->bw_info.bw_ets_credits[i] =
4578 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4579 /* 4 bits per TC, 4th bit is reserved */
4580 vsi->bw_info.bw_ets_max[i] =
4581 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4582 RTE_LEN2MASK(3, uint8_t));
4583 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4584 vsi->bw_info.bw_ets_share_credits[i]);
4585 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4586 vsi->bw_info.bw_ets_credits[i]);
4587 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4588 vsi->bw_info.bw_ets_max[i]);
4591 return I40E_SUCCESS;
4594 /* i40e_enable_pf_lb
4595 * @pf: pointer to the pf structure
4597 * allow loopback on pf
4600 i40e_enable_pf_lb(struct i40e_pf *pf)
4602 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4603 struct i40e_vsi_context ctxt;
4606 /* Use the FW API if FW >= v5.0 */
4607 if (hw->aq.fw_maj_ver < 5) {
4608 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4612 memset(&ctxt, 0, sizeof(ctxt));
4613 ctxt.seid = pf->main_vsi_seid;
4614 ctxt.pf_num = hw->pf_id;
4615 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4617 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4618 ret, hw->aq.asq_last_status);
4621 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4622 ctxt.info.valid_sections =
4623 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4624 ctxt.info.switch_id |=
4625 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4627 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4629 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4630 hw->aq.asq_last_status);
4635 i40e_vsi_setup(struct i40e_pf *pf,
4636 enum i40e_vsi_type type,
4637 struct i40e_vsi *uplink_vsi,
4638 uint16_t user_param)
4640 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4641 struct i40e_vsi *vsi;
4642 struct i40e_mac_filter_info filter;
4644 struct i40e_vsi_context ctxt;
4645 struct ether_addr broadcast =
4646 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4648 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4649 uplink_vsi == NULL) {
4651 "VSI setup failed, VSI link shouldn't be NULL");
4655 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4657 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4662 * 1.type is not MAIN and uplink vsi is not NULL
4663 * If uplink vsi didn't setup VEB, create one first under veb field
4664 * 2.type is SRIOV and the uplink is NULL
4665 * If floating VEB is NULL, create one veb under floating veb field
4668 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4669 uplink_vsi->veb == NULL) {
4670 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4672 if (uplink_vsi->veb == NULL) {
4673 PMD_DRV_LOG(ERR, "VEB setup failed");
4676 /* set ALLOWLOOPBACk on pf, when veb is created */
4677 i40e_enable_pf_lb(pf);
4680 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4681 pf->main_vsi->floating_veb == NULL) {
4682 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4684 if (pf->main_vsi->floating_veb == NULL) {
4685 PMD_DRV_LOG(ERR, "VEB setup failed");
4690 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4692 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4695 TAILQ_INIT(&vsi->mac_list);
4697 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4698 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4699 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4700 vsi->user_param = user_param;
4701 vsi->vlan_anti_spoof_on = 0;
4702 vsi->vlan_filter_on = 0;
4703 /* Allocate queues */
4704 switch (vsi->type) {
4705 case I40E_VSI_MAIN :
4706 vsi->nb_qps = pf->lan_nb_qps;
4708 case I40E_VSI_SRIOV :
4709 vsi->nb_qps = pf->vf_nb_qps;
4711 case I40E_VSI_VMDQ2:
4712 vsi->nb_qps = pf->vmdq_nb_qps;
4715 vsi->nb_qps = pf->fdir_nb_qps;
4721 * The filter status descriptor is reported in rx queue 0,
4722 * while the tx queue for fdir filter programming has no
4723 * such constraints, can be non-zero queues.
4724 * To simplify it, choose FDIR vsi use queue 0 pair.
4725 * To make sure it will use queue 0 pair, queue allocation
4726 * need be done before this function is called
4728 if (type != I40E_VSI_FDIR) {
4729 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4731 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4735 vsi->base_queue = ret;
4737 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4739 /* VF has MSIX interrupt in VF range, don't allocate here */
4740 if (type == I40E_VSI_MAIN) {
4741 ret = i40e_res_pool_alloc(&pf->msix_pool,
4742 RTE_MIN(vsi->nb_qps,
4743 RTE_MAX_RXTX_INTR_VEC_ID));
4745 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4747 goto fail_queue_alloc;
4749 vsi->msix_intr = ret;
4750 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4751 } else if (type != I40E_VSI_SRIOV) {
4752 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4754 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4755 goto fail_queue_alloc;
4757 vsi->msix_intr = ret;
4765 if (type == I40E_VSI_MAIN) {
4766 /* For main VSI, no need to add since it's default one */
4767 vsi->uplink_seid = pf->mac_seid;
4768 vsi->seid = pf->main_vsi_seid;
4769 /* Bind queues with specific MSIX interrupt */
4771 * Needs 2 interrupt at least, one for misc cause which will
4772 * enabled from OS side, Another for queues binding the
4773 * interrupt from device side only.
4776 /* Get default VSI parameters from hardware */
4777 memset(&ctxt, 0, sizeof(ctxt));
4778 ctxt.seid = vsi->seid;
4779 ctxt.pf_num = hw->pf_id;
4780 ctxt.uplink_seid = vsi->uplink_seid;
4782 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4783 if (ret != I40E_SUCCESS) {
4784 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4785 goto fail_msix_alloc;
4787 (void)rte_memcpy(&vsi->info, &ctxt.info,
4788 sizeof(struct i40e_aqc_vsi_properties_data));
4789 vsi->vsi_id = ctxt.vsi_number;
4790 vsi->info.valid_sections = 0;
4792 /* Configure tc, enabled TC0 only */
4793 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4795 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4796 goto fail_msix_alloc;
4799 /* TC, queue mapping */
4800 memset(&ctxt, 0, sizeof(ctxt));
4801 vsi->info.valid_sections |=
4802 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4803 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4804 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4805 (void)rte_memcpy(&ctxt.info, &vsi->info,
4806 sizeof(struct i40e_aqc_vsi_properties_data));
4807 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4808 I40E_DEFAULT_TCMAP);
4809 if (ret != I40E_SUCCESS) {
4811 "Failed to configure TC queue mapping");
4812 goto fail_msix_alloc;
4814 ctxt.seid = vsi->seid;
4815 ctxt.pf_num = hw->pf_id;
4816 ctxt.uplink_seid = vsi->uplink_seid;
4819 /* Update VSI parameters */
4820 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4821 if (ret != I40E_SUCCESS) {
4822 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4823 goto fail_msix_alloc;
4826 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4827 sizeof(vsi->info.tc_mapping));
4828 (void)rte_memcpy(&vsi->info.queue_mapping,
4829 &ctxt.info.queue_mapping,
4830 sizeof(vsi->info.queue_mapping));
4831 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4832 vsi->info.valid_sections = 0;
4834 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4838 * Updating default filter settings are necessary to prevent
4839 * reception of tagged packets.
4840 * Some old firmware configurations load a default macvlan
4841 * filter which accepts both tagged and untagged packets.
4842 * The updating is to use a normal filter instead if needed.
4843 * For NVM 4.2.2 or after, the updating is not needed anymore.
4844 * The firmware with correct configurations load the default
4845 * macvlan filter which is expected and cannot be removed.
4847 i40e_update_default_filter_setting(vsi);
4848 i40e_config_qinq(hw, vsi);
4849 } else if (type == I40E_VSI_SRIOV) {
4850 memset(&ctxt, 0, sizeof(ctxt));
4852 * For other VSI, the uplink_seid equals to uplink VSI's
4853 * uplink_seid since they share same VEB
4855 if (uplink_vsi == NULL)
4856 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4858 vsi->uplink_seid = uplink_vsi->uplink_seid;
4859 ctxt.pf_num = hw->pf_id;
4860 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4861 ctxt.uplink_seid = vsi->uplink_seid;
4862 ctxt.connection_type = 0x1;
4863 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4865 /* Use the VEB configuration if FW >= v5.0 */
4866 if (hw->aq.fw_maj_ver >= 5) {
4867 /* Configure switch ID */
4868 ctxt.info.valid_sections |=
4869 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4870 ctxt.info.switch_id =
4871 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4874 /* Configure port/vlan */
4875 ctxt.info.valid_sections |=
4876 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4877 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4878 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4879 hw->func_caps.enabled_tcmap);
4880 if (ret != I40E_SUCCESS) {
4882 "Failed to configure TC queue mapping");
4883 goto fail_msix_alloc;
4886 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4887 ctxt.info.valid_sections |=
4888 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4890 * Since VSI is not created yet, only configure parameter,
4891 * will add vsi below.
4894 i40e_config_qinq(hw, vsi);
4895 } else if (type == I40E_VSI_VMDQ2) {
4896 memset(&ctxt, 0, sizeof(ctxt));
4898 * For other VSI, the uplink_seid equals to uplink VSI's
4899 * uplink_seid since they share same VEB
4901 vsi->uplink_seid = uplink_vsi->uplink_seid;
4902 ctxt.pf_num = hw->pf_id;
4904 ctxt.uplink_seid = vsi->uplink_seid;
4905 ctxt.connection_type = 0x1;
4906 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4908 ctxt.info.valid_sections |=
4909 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4910 /* user_param carries flag to enable loop back */
4912 ctxt.info.switch_id =
4913 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4914 ctxt.info.switch_id |=
4915 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4918 /* Configure port/vlan */
4919 ctxt.info.valid_sections |=
4920 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4921 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4922 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4923 I40E_DEFAULT_TCMAP);
4924 if (ret != I40E_SUCCESS) {
4926 "Failed to configure TC queue mapping");
4927 goto fail_msix_alloc;
4929 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4930 ctxt.info.valid_sections |=
4931 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4932 } else if (type == I40E_VSI_FDIR) {
4933 memset(&ctxt, 0, sizeof(ctxt));
4934 vsi->uplink_seid = uplink_vsi->uplink_seid;
4935 ctxt.pf_num = hw->pf_id;
4937 ctxt.uplink_seid = vsi->uplink_seid;
4938 ctxt.connection_type = 0x1; /* regular data port */
4939 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4940 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4941 I40E_DEFAULT_TCMAP);
4942 if (ret != I40E_SUCCESS) {
4944 "Failed to configure TC queue mapping.");
4945 goto fail_msix_alloc;
4947 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4948 ctxt.info.valid_sections |=
4949 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4951 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4952 goto fail_msix_alloc;
4955 if (vsi->type != I40E_VSI_MAIN) {
4956 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4957 if (ret != I40E_SUCCESS) {
4958 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4959 hw->aq.asq_last_status);
4960 goto fail_msix_alloc;
4962 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4963 vsi->info.valid_sections = 0;
4964 vsi->seid = ctxt.seid;
4965 vsi->vsi_id = ctxt.vsi_number;
4966 vsi->sib_vsi_list.vsi = vsi;
4967 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4968 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4969 &vsi->sib_vsi_list, list);
4971 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4972 &vsi->sib_vsi_list, list);
4976 /* MAC/VLAN configuration */
4977 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4978 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4980 ret = i40e_vsi_add_mac(vsi, &filter);
4981 if (ret != I40E_SUCCESS) {
4982 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4983 goto fail_msix_alloc;
4986 /* Get VSI BW information */
4987 i40e_vsi_get_bw_config(vsi);
4990 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4992 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4998 /* Configure vlan filter on or off */
5000 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5003 struct i40e_mac_filter *f;
5005 struct i40e_mac_filter_info *mac_filter;
5006 enum rte_mac_filter_type desired_filter;
5007 int ret = I40E_SUCCESS;
5010 /* Filter to match MAC and VLAN */
5011 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5013 /* Filter to match only MAC */
5014 desired_filter = RTE_MAC_PERFECT_MATCH;
5019 mac_filter = rte_zmalloc("mac_filter_info_data",
5020 num * sizeof(*mac_filter), 0);
5021 if (mac_filter == NULL) {
5022 PMD_DRV_LOG(ERR, "failed to allocate memory");
5023 return I40E_ERR_NO_MEMORY;
5028 /* Remove all existing mac */
5029 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5030 mac_filter[i] = f->mac_info;
5031 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5033 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5034 on ? "enable" : "disable");
5040 /* Override with new filter */
5041 for (i = 0; i < num; i++) {
5042 mac_filter[i].filter_type = desired_filter;
5043 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5045 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5046 on ? "enable" : "disable");
5052 rte_free(mac_filter);
5056 /* Configure vlan stripping on or off */
5058 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5060 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5061 struct i40e_vsi_context ctxt;
5063 int ret = I40E_SUCCESS;
5065 /* Check if it has been already on or off */
5066 if (vsi->info.valid_sections &
5067 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5069 if ((vsi->info.port_vlan_flags &
5070 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5071 return 0; /* already on */
5073 if ((vsi->info.port_vlan_flags &
5074 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5075 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5076 return 0; /* already off */
5081 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5083 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5084 vsi->info.valid_sections =
5085 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5086 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5087 vsi->info.port_vlan_flags |= vlan_flags;
5088 ctxt.seid = vsi->seid;
5089 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5090 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5092 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5093 on ? "enable" : "disable");
5099 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5101 struct rte_eth_dev_data *data = dev->data;
5105 /* Apply vlan offload setting */
5106 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5107 i40e_vlan_offload_set(dev, mask);
5109 /* Apply double-vlan setting, not implemented yet */
5111 /* Apply pvid setting */
5112 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5113 data->dev_conf.txmode.hw_vlan_insert_pvid);
5115 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5121 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5123 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5125 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5129 i40e_update_flow_control(struct i40e_hw *hw)
5131 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5132 struct i40e_link_status link_status;
5133 uint32_t rxfc = 0, txfc = 0, reg;
5137 memset(&link_status, 0, sizeof(link_status));
5138 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5139 if (ret != I40E_SUCCESS) {
5140 PMD_DRV_LOG(ERR, "Failed to get link status information");
5141 goto write_reg; /* Disable flow control */
5144 an_info = hw->phy.link_info.an_info;
5145 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5146 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5147 ret = I40E_ERR_NOT_READY;
5148 goto write_reg; /* Disable flow control */
5151 * If link auto negotiation is enabled, flow control needs to
5152 * be configured according to it
5154 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5155 case I40E_LINK_PAUSE_RXTX:
5158 hw->fc.current_mode = I40E_FC_FULL;
5160 case I40E_AQ_LINK_PAUSE_RX:
5162 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5164 case I40E_AQ_LINK_PAUSE_TX:
5166 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5169 hw->fc.current_mode = I40E_FC_NONE;
5174 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5175 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5176 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5177 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5178 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5179 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5186 i40e_pf_setup(struct i40e_pf *pf)
5188 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5189 struct i40e_filter_control_settings settings;
5190 struct i40e_vsi *vsi;
5193 /* Clear all stats counters */
5194 pf->offset_loaded = FALSE;
5195 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5196 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5198 ret = i40e_pf_get_switch_config(pf);
5199 if (ret != I40E_SUCCESS) {
5200 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5203 if (pf->flags & I40E_FLAG_FDIR) {
5204 /* make queue allocated first, let FDIR use queue pair 0*/
5205 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5206 if (ret != I40E_FDIR_QUEUE_ID) {
5208 "queue allocation fails for FDIR: ret =%d",
5210 pf->flags &= ~I40E_FLAG_FDIR;
5213 /* main VSI setup */
5214 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5216 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5217 return I40E_ERR_NOT_READY;
5221 /* Configure filter control */
5222 memset(&settings, 0, sizeof(settings));
5223 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5224 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5225 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5226 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5228 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5229 hw->func_caps.rss_table_size);
5230 return I40E_ERR_PARAM;
5232 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5233 hw->func_caps.rss_table_size);
5234 pf->hash_lut_size = hw->func_caps.rss_table_size;
5236 /* Enable ethtype and macvlan filters */
5237 settings.enable_ethtype = TRUE;
5238 settings.enable_macvlan = TRUE;
5239 ret = i40e_set_filter_control(hw, &settings);
5241 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5244 /* Update flow control according to the auto negotiation */
5245 i40e_update_flow_control(hw);
5247 return I40E_SUCCESS;
5251 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5257 * Set or clear TX Queue Disable flags,
5258 * which is required by hardware.
5260 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5261 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5263 /* Wait until the request is finished */
5264 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5265 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5266 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5267 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5268 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5274 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5275 return I40E_SUCCESS; /* already on, skip next steps */
5277 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5278 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5280 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5281 return I40E_SUCCESS; /* already off, skip next steps */
5282 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5284 /* Write the register */
5285 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5286 /* Check the result */
5287 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5288 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5289 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5291 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5292 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5295 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5296 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5300 /* Check if it is timeout */
5301 if (j >= I40E_CHK_Q_ENA_COUNT) {
5302 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5303 (on ? "enable" : "disable"), q_idx);
5304 return I40E_ERR_TIMEOUT;
5307 return I40E_SUCCESS;
5310 /* Swith on or off the tx queues */
5312 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5314 struct rte_eth_dev_data *dev_data = pf->dev_data;
5315 struct i40e_tx_queue *txq;
5316 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5320 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5321 txq = dev_data->tx_queues[i];
5322 /* Don't operate the queue if not configured or
5323 * if starting only per queue */
5324 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5327 ret = i40e_dev_tx_queue_start(dev, i);
5329 ret = i40e_dev_tx_queue_stop(dev, i);
5330 if ( ret != I40E_SUCCESS)
5334 return I40E_SUCCESS;
5338 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5343 /* Wait until the request is finished */
5344 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5345 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5346 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5347 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5348 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5353 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5354 return I40E_SUCCESS; /* Already on, skip next steps */
5355 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5357 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5358 return I40E_SUCCESS; /* Already off, skip next steps */
5359 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5362 /* Write the register */
5363 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5364 /* Check the result */
5365 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5366 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5367 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5369 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5370 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5373 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5374 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5379 /* Check if it is timeout */
5380 if (j >= I40E_CHK_Q_ENA_COUNT) {
5381 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5382 (on ? "enable" : "disable"), q_idx);
5383 return I40E_ERR_TIMEOUT;
5386 return I40E_SUCCESS;
5388 /* Switch on or off the rx queues */
5390 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5392 struct rte_eth_dev_data *dev_data = pf->dev_data;
5393 struct i40e_rx_queue *rxq;
5394 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5398 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5399 rxq = dev_data->rx_queues[i];
5400 /* Don't operate the queue if not configured or
5401 * if starting only per queue */
5402 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5405 ret = i40e_dev_rx_queue_start(dev, i);
5407 ret = i40e_dev_rx_queue_stop(dev, i);
5408 if (ret != I40E_SUCCESS)
5412 return I40E_SUCCESS;
5415 /* Switch on or off all the rx/tx queues */
5417 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5422 /* enable rx queues before enabling tx queues */
5423 ret = i40e_dev_switch_rx_queues(pf, on);
5425 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5428 ret = i40e_dev_switch_tx_queues(pf, on);
5430 /* Stop tx queues before stopping rx queues */
5431 ret = i40e_dev_switch_tx_queues(pf, on);
5433 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5436 ret = i40e_dev_switch_rx_queues(pf, on);
5442 /* Initialize VSI for TX */
5444 i40e_dev_tx_init(struct i40e_pf *pf)
5446 struct rte_eth_dev_data *data = pf->dev_data;
5448 uint32_t ret = I40E_SUCCESS;
5449 struct i40e_tx_queue *txq;
5451 for (i = 0; i < data->nb_tx_queues; i++) {
5452 txq = data->tx_queues[i];
5453 if (!txq || !txq->q_set)
5455 ret = i40e_tx_queue_init(txq);
5456 if (ret != I40E_SUCCESS)
5459 if (ret == I40E_SUCCESS)
5460 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5466 /* Initialize VSI for RX */
5468 i40e_dev_rx_init(struct i40e_pf *pf)
5470 struct rte_eth_dev_data *data = pf->dev_data;
5471 int ret = I40E_SUCCESS;
5473 struct i40e_rx_queue *rxq;
5475 i40e_pf_config_mq_rx(pf);
5476 for (i = 0; i < data->nb_rx_queues; i++) {
5477 rxq = data->rx_queues[i];
5478 if (!rxq || !rxq->q_set)
5481 ret = i40e_rx_queue_init(rxq);
5482 if (ret != I40E_SUCCESS) {
5484 "Failed to do RX queue initialization");
5488 if (ret == I40E_SUCCESS)
5489 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5496 i40e_dev_rxtx_init(struct i40e_pf *pf)
5500 err = i40e_dev_tx_init(pf);
5502 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5505 err = i40e_dev_rx_init(pf);
5507 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5515 i40e_vmdq_setup(struct rte_eth_dev *dev)
5517 struct rte_eth_conf *conf = &dev->data->dev_conf;
5518 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5519 int i, err, conf_vsis, j, loop;
5520 struct i40e_vsi *vsi;
5521 struct i40e_vmdq_info *vmdq_info;
5522 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5523 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5526 * Disable interrupt to avoid message from VF. Furthermore, it will
5527 * avoid race condition in VSI creation/destroy.
5529 i40e_pf_disable_irq0(hw);
5531 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5532 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5536 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5537 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5538 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5539 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5540 pf->max_nb_vmdq_vsi);
5544 if (pf->vmdq != NULL) {
5545 PMD_INIT_LOG(INFO, "VMDQ already configured");
5549 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5550 sizeof(*vmdq_info) * conf_vsis, 0);
5552 if (pf->vmdq == NULL) {
5553 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5557 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5559 /* Create VMDQ VSI */
5560 for (i = 0; i < conf_vsis; i++) {
5561 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5562 vmdq_conf->enable_loop_back);
5564 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5568 vmdq_info = &pf->vmdq[i];
5570 vmdq_info->vsi = vsi;
5572 pf->nb_cfg_vmdq_vsi = conf_vsis;
5574 /* Configure Vlan */
5575 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5576 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5577 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5578 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5579 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5580 vmdq_conf->pool_map[i].vlan_id, j);
5582 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5583 vmdq_conf->pool_map[i].vlan_id);
5585 PMD_INIT_LOG(ERR, "Failed to add vlan");
5593 i40e_pf_enable_irq0(hw);
5598 for (i = 0; i < conf_vsis; i++)
5599 if (pf->vmdq[i].vsi == NULL)
5602 i40e_vsi_release(pf->vmdq[i].vsi);
5606 i40e_pf_enable_irq0(hw);
5611 i40e_stat_update_32(struct i40e_hw *hw,
5619 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5623 if (new_data >= *offset)
5624 *stat = (uint64_t)(new_data - *offset);
5626 *stat = (uint64_t)((new_data +
5627 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5631 i40e_stat_update_48(struct i40e_hw *hw,
5640 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5641 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5642 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5647 if (new_data >= *offset)
5648 *stat = new_data - *offset;
5650 *stat = (uint64_t)((new_data +
5651 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5653 *stat &= I40E_48_BIT_MASK;
5658 i40e_pf_disable_irq0(struct i40e_hw *hw)
5660 /* Disable all interrupt types */
5661 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5662 I40E_WRITE_FLUSH(hw);
5667 i40e_pf_enable_irq0(struct i40e_hw *hw)
5669 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5670 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5671 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5672 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5673 I40E_WRITE_FLUSH(hw);
5677 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5679 /* read pending request and disable first */
5680 i40e_pf_disable_irq0(hw);
5681 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5682 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5683 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5686 /* Link no queues with irq0 */
5687 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5688 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5692 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5698 uint32_t index, offset, val;
5703 * Try to find which VF trigger a reset, use absolute VF id to access
5704 * since the reg is global register.
5706 for (i = 0; i < pf->vf_num; i++) {
5707 abs_vf_id = hw->func_caps.vf_base_id + i;
5708 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5709 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5710 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5711 /* VFR event occured */
5712 if (val & (0x1 << offset)) {
5715 /* Clear the event first */
5716 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5718 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5720 * Only notify a VF reset event occured,
5721 * don't trigger another SW reset
5723 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5724 if (ret != I40E_SUCCESS)
5725 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5731 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5733 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5734 struct i40e_virtchnl_pf_event event;
5737 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5738 event.event_data.link_event.link_status =
5739 dev->data->dev_link.link_status;
5740 event.event_data.link_event.link_speed =
5741 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5743 for (i = 0; i < pf->vf_num; i++)
5744 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5745 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5749 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5751 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752 struct i40e_arq_event_info info;
5753 uint16_t pending, opcode;
5756 info.buf_len = I40E_AQ_BUF_SZ;
5757 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5758 if (!info.msg_buf) {
5759 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5765 ret = i40e_clean_arq_element(hw, &info, &pending);
5767 if (ret != I40E_SUCCESS) {
5769 "Failed to read msg from AdminQ, aq_err: %u",
5770 hw->aq.asq_last_status);
5773 opcode = rte_le_to_cpu_16(info.desc.opcode);
5776 case i40e_aqc_opc_send_msg_to_pf:
5777 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5778 i40e_pf_host_handle_vf_msg(dev,
5779 rte_le_to_cpu_16(info.desc.retval),
5780 rte_le_to_cpu_32(info.desc.cookie_high),
5781 rte_le_to_cpu_32(info.desc.cookie_low),
5785 case i40e_aqc_opc_get_link_status:
5786 ret = i40e_dev_link_update(dev, 0);
5788 i40e_notify_all_vfs_link_status(dev);
5789 _rte_eth_dev_callback_process(dev,
5790 RTE_ETH_EVENT_INTR_LSC, NULL);
5794 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5799 rte_free(info.msg_buf);
5803 * Interrupt handler triggered by NIC for handling
5804 * specific interrupt.
5807 * Pointer to interrupt handle.
5809 * The address of parameter (struct rte_eth_dev *) regsitered before.
5815 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5818 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5822 /* Disable interrupt */
5823 i40e_pf_disable_irq0(hw);
5825 /* read out interrupt causes */
5826 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5828 /* No interrupt event indicated */
5829 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5830 PMD_DRV_LOG(INFO, "No interrupt event");
5833 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5834 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5835 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5836 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5837 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5838 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5839 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5840 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5841 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5842 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5843 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5844 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5845 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5846 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5847 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5848 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5850 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5851 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5852 i40e_dev_handle_vfr_event(dev);
5854 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5855 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5856 i40e_dev_handle_aq_msg(dev);
5860 /* Enable interrupt */
5861 i40e_pf_enable_irq0(hw);
5862 rte_intr_enable(intr_handle);
5866 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5867 struct i40e_macvlan_filter *filter,
5870 int ele_num, ele_buff_size;
5871 int num, actual_num, i;
5873 int ret = I40E_SUCCESS;
5874 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5875 struct i40e_aqc_add_macvlan_element_data *req_list;
5877 if (filter == NULL || total == 0)
5878 return I40E_ERR_PARAM;
5879 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5880 ele_buff_size = hw->aq.asq_buf_size;
5882 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5883 if (req_list == NULL) {
5884 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5885 return I40E_ERR_NO_MEMORY;
5890 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5891 memset(req_list, 0, ele_buff_size);
5893 for (i = 0; i < actual_num; i++) {
5894 (void)rte_memcpy(req_list[i].mac_addr,
5895 &filter[num + i].macaddr, ETH_ADDR_LEN);
5896 req_list[i].vlan_tag =
5897 rte_cpu_to_le_16(filter[num + i].vlan_id);
5899 switch (filter[num + i].filter_type) {
5900 case RTE_MAC_PERFECT_MATCH:
5901 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5902 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5904 case RTE_MACVLAN_PERFECT_MATCH:
5905 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5907 case RTE_MAC_HASH_MATCH:
5908 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5909 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5911 case RTE_MACVLAN_HASH_MATCH:
5912 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5915 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5916 ret = I40E_ERR_PARAM;
5920 req_list[i].queue_number = 0;
5922 req_list[i].flags = rte_cpu_to_le_16(flags);
5925 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5927 if (ret != I40E_SUCCESS) {
5928 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5932 } while (num < total);
5940 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5941 struct i40e_macvlan_filter *filter,
5944 int ele_num, ele_buff_size;
5945 int num, actual_num, i;
5947 int ret = I40E_SUCCESS;
5948 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5949 struct i40e_aqc_remove_macvlan_element_data *req_list;
5951 if (filter == NULL || total == 0)
5952 return I40E_ERR_PARAM;
5954 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5955 ele_buff_size = hw->aq.asq_buf_size;
5957 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5958 if (req_list == NULL) {
5959 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5960 return I40E_ERR_NO_MEMORY;
5965 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5966 memset(req_list, 0, ele_buff_size);
5968 for (i = 0; i < actual_num; i++) {
5969 (void)rte_memcpy(req_list[i].mac_addr,
5970 &filter[num + i].macaddr, ETH_ADDR_LEN);
5971 req_list[i].vlan_tag =
5972 rte_cpu_to_le_16(filter[num + i].vlan_id);
5974 switch (filter[num + i].filter_type) {
5975 case RTE_MAC_PERFECT_MATCH:
5976 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5977 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5979 case RTE_MACVLAN_PERFECT_MATCH:
5980 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5982 case RTE_MAC_HASH_MATCH:
5983 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5984 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5986 case RTE_MACVLAN_HASH_MATCH:
5987 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5990 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5991 ret = I40E_ERR_PARAM;
5994 req_list[i].flags = rte_cpu_to_le_16(flags);
5997 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5999 if (ret != I40E_SUCCESS) {
6000 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6004 } while (num < total);
6011 /* Find out specific MAC filter */
6012 static struct i40e_mac_filter *
6013 i40e_find_mac_filter(struct i40e_vsi *vsi,
6014 struct ether_addr *macaddr)
6016 struct i40e_mac_filter *f;
6018 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6019 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6027 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6030 uint32_t vid_idx, vid_bit;
6032 if (vlan_id > ETH_VLAN_ID_MAX)
6035 vid_idx = I40E_VFTA_IDX(vlan_id);
6036 vid_bit = I40E_VFTA_BIT(vlan_id);
6038 if (vsi->vfta[vid_idx] & vid_bit)
6045 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6046 uint16_t vlan_id, bool on)
6048 uint32_t vid_idx, vid_bit;
6050 vid_idx = I40E_VFTA_IDX(vlan_id);
6051 vid_bit = I40E_VFTA_BIT(vlan_id);
6054 vsi->vfta[vid_idx] |= vid_bit;
6056 vsi->vfta[vid_idx] &= ~vid_bit;
6060 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6061 uint16_t vlan_id, bool on)
6063 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6064 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6067 if (vlan_id > ETH_VLAN_ID_MAX)
6070 i40e_store_vlan_filter(vsi, vlan_id, on);
6072 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6075 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6078 ret = i40e_aq_add_vlan(hw, vsi->seid,
6079 &vlan_data, 1, NULL);
6080 if (ret != I40E_SUCCESS)
6081 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6083 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6084 &vlan_data, 1, NULL);
6085 if (ret != I40E_SUCCESS)
6087 "Failed to remove vlan filter");
6092 * Find all vlan options for specific mac addr,
6093 * return with actual vlan found.
6096 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6097 struct i40e_macvlan_filter *mv_f,
6098 int num, struct ether_addr *addr)
6104 * Not to use i40e_find_vlan_filter to decrease the loop time,
6105 * although the code looks complex.
6107 if (num < vsi->vlan_num)
6108 return I40E_ERR_PARAM;
6111 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6113 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6114 if (vsi->vfta[j] & (1 << k)) {
6117 "vlan number doesn't match");
6118 return I40E_ERR_PARAM;
6120 (void)rte_memcpy(&mv_f[i].macaddr,
6121 addr, ETH_ADDR_LEN);
6123 j * I40E_UINT32_BIT_SIZE + k;
6129 return I40E_SUCCESS;
6133 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6134 struct i40e_macvlan_filter *mv_f,
6139 struct i40e_mac_filter *f;
6141 if (num < vsi->mac_num)
6142 return I40E_ERR_PARAM;
6144 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6146 PMD_DRV_LOG(ERR, "buffer number not match");
6147 return I40E_ERR_PARAM;
6149 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6151 mv_f[i].vlan_id = vlan;
6152 mv_f[i].filter_type = f->mac_info.filter_type;
6156 return I40E_SUCCESS;
6160 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6163 struct i40e_mac_filter *f;
6164 struct i40e_macvlan_filter *mv_f;
6165 int ret = I40E_SUCCESS;
6167 if (vsi == NULL || vsi->mac_num == 0)
6168 return I40E_ERR_PARAM;
6170 /* Case that no vlan is set */
6171 if (vsi->vlan_num == 0)
6174 num = vsi->mac_num * vsi->vlan_num;
6176 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6178 PMD_DRV_LOG(ERR, "failed to allocate memory");
6179 return I40E_ERR_NO_MEMORY;
6183 if (vsi->vlan_num == 0) {
6184 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6185 (void)rte_memcpy(&mv_f[i].macaddr,
6186 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6187 mv_f[i].filter_type = f->mac_info.filter_type;
6188 mv_f[i].vlan_id = 0;
6192 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6193 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6194 vsi->vlan_num, &f->mac_info.mac_addr);
6195 if (ret != I40E_SUCCESS)
6197 for (j = i; j < i + vsi->vlan_num; j++)
6198 mv_f[j].filter_type = f->mac_info.filter_type;
6203 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6211 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6213 struct i40e_macvlan_filter *mv_f;
6215 int ret = I40E_SUCCESS;
6217 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6218 return I40E_ERR_PARAM;
6220 /* If it's already set, just return */
6221 if (i40e_find_vlan_filter(vsi,vlan))
6222 return I40E_SUCCESS;
6224 mac_num = vsi->mac_num;
6227 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6228 return I40E_ERR_PARAM;
6231 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6234 PMD_DRV_LOG(ERR, "failed to allocate memory");
6235 return I40E_ERR_NO_MEMORY;
6238 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6240 if (ret != I40E_SUCCESS)
6243 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6245 if (ret != I40E_SUCCESS)
6248 i40e_set_vlan_filter(vsi, vlan, 1);
6258 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6260 struct i40e_macvlan_filter *mv_f;
6262 int ret = I40E_SUCCESS;
6265 * Vlan 0 is the generic filter for untagged packets
6266 * and can't be removed.
6268 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6269 return I40E_ERR_PARAM;
6271 /* If can't find it, just return */
6272 if (!i40e_find_vlan_filter(vsi, vlan))
6273 return I40E_ERR_PARAM;
6275 mac_num = vsi->mac_num;
6278 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6279 return I40E_ERR_PARAM;
6282 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6285 PMD_DRV_LOG(ERR, "failed to allocate memory");
6286 return I40E_ERR_NO_MEMORY;
6289 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6291 if (ret != I40E_SUCCESS)
6294 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6296 if (ret != I40E_SUCCESS)
6299 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6300 if (vsi->vlan_num == 1) {
6301 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6302 if (ret != I40E_SUCCESS)
6305 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6306 if (ret != I40E_SUCCESS)
6310 i40e_set_vlan_filter(vsi, vlan, 0);
6320 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6322 struct i40e_mac_filter *f;
6323 struct i40e_macvlan_filter *mv_f;
6324 int i, vlan_num = 0;
6325 int ret = I40E_SUCCESS;
6327 /* If it's add and we've config it, return */
6328 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6330 return I40E_SUCCESS;
6331 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6332 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6335 * If vlan_num is 0, that's the first time to add mac,
6336 * set mask for vlan_id 0.
6338 if (vsi->vlan_num == 0) {
6339 i40e_set_vlan_filter(vsi, 0, 1);
6342 vlan_num = vsi->vlan_num;
6343 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6344 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6347 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6349 PMD_DRV_LOG(ERR, "failed to allocate memory");
6350 return I40E_ERR_NO_MEMORY;
6353 for (i = 0; i < vlan_num; i++) {
6354 mv_f[i].filter_type = mac_filter->filter_type;
6355 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6359 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6360 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6361 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6362 &mac_filter->mac_addr);
6363 if (ret != I40E_SUCCESS)
6367 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6368 if (ret != I40E_SUCCESS)
6371 /* Add the mac addr into mac list */
6372 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6374 PMD_DRV_LOG(ERR, "failed to allocate memory");
6375 ret = I40E_ERR_NO_MEMORY;
6378 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6380 f->mac_info.filter_type = mac_filter->filter_type;
6381 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6392 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6394 struct i40e_mac_filter *f;
6395 struct i40e_macvlan_filter *mv_f;
6397 enum rte_mac_filter_type filter_type;
6398 int ret = I40E_SUCCESS;
6400 /* Can't find it, return an error */
6401 f = i40e_find_mac_filter(vsi, addr);
6403 return I40E_ERR_PARAM;
6405 vlan_num = vsi->vlan_num;
6406 filter_type = f->mac_info.filter_type;
6407 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6408 filter_type == RTE_MACVLAN_HASH_MATCH) {
6409 if (vlan_num == 0) {
6410 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6411 return I40E_ERR_PARAM;
6413 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6414 filter_type == RTE_MAC_HASH_MATCH)
6417 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6419 PMD_DRV_LOG(ERR, "failed to allocate memory");
6420 return I40E_ERR_NO_MEMORY;
6423 for (i = 0; i < vlan_num; i++) {
6424 mv_f[i].filter_type = filter_type;
6425 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6428 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6429 filter_type == RTE_MACVLAN_HASH_MATCH) {
6430 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6431 if (ret != I40E_SUCCESS)
6435 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6436 if (ret != I40E_SUCCESS)
6439 /* Remove the mac addr into mac list */
6440 TAILQ_REMOVE(&vsi->mac_list, f, next);
6450 /* Configure hash enable flags for RSS */
6452 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6459 if (flags & ETH_RSS_FRAG_IPV4)
6460 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6461 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6462 if (type == I40E_MAC_X722) {
6463 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6464 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6466 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6468 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6469 if (type == I40E_MAC_X722) {
6470 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6471 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6472 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6474 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6476 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6477 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6478 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6479 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6480 if (flags & ETH_RSS_FRAG_IPV6)
6481 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6482 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6483 if (type == I40E_MAC_X722) {
6484 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6485 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6487 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6489 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6490 if (type == I40E_MAC_X722) {
6491 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6492 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6493 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6495 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6497 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6498 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6499 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6500 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6501 if (flags & ETH_RSS_L2_PAYLOAD)
6502 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6507 /* Parse the hash enable flags */
6509 i40e_parse_hena(uint64_t flags)
6511 uint64_t rss_hf = 0;
6515 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6516 rss_hf |= ETH_RSS_FRAG_IPV4;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6518 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6519 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6520 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6521 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6522 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6523 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6524 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6525 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6526 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6527 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6528 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6529 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6530 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6531 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6532 rss_hf |= ETH_RSS_FRAG_IPV6;
6533 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6534 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6535 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6536 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6537 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6538 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6539 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6540 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6541 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6542 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6543 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6544 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6545 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6546 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6547 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6548 rss_hf |= ETH_RSS_L2_PAYLOAD;
6555 i40e_pf_disable_rss(struct i40e_pf *pf)
6557 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6560 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6561 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6562 if (hw->mac.type == I40E_MAC_X722)
6563 hena &= ~I40E_RSS_HENA_ALL_X722;
6565 hena &= ~I40E_RSS_HENA_ALL;
6566 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6567 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6568 I40E_WRITE_FLUSH(hw);
6572 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6574 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6575 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6578 if (!key || key_len == 0) {
6579 PMD_DRV_LOG(DEBUG, "No key to be configured");
6581 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6583 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6587 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6588 struct i40e_aqc_get_set_rss_key_data *key_dw =
6589 (struct i40e_aqc_get_set_rss_key_data *)key;
6591 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6593 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6595 uint32_t *hash_key = (uint32_t *)key;
6598 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6599 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6600 I40E_WRITE_FLUSH(hw);
6607 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6609 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6610 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6613 if (!key || !key_len)
6616 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6617 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6618 (struct i40e_aqc_get_set_rss_key_data *)key);
6620 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6624 uint32_t *key_dw = (uint32_t *)key;
6627 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6628 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6630 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6636 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6638 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6643 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6644 rss_conf->rss_key_len);
6648 rss_hf = rss_conf->rss_hf;
6649 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6650 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6651 if (hw->mac.type == I40E_MAC_X722)
6652 hena &= ~I40E_RSS_HENA_ALL_X722;
6654 hena &= ~I40E_RSS_HENA_ALL;
6655 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6656 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6657 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6658 I40E_WRITE_FLUSH(hw);
6664 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6665 struct rte_eth_rss_conf *rss_conf)
6667 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6669 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6672 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6673 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6674 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6675 ? I40E_RSS_HENA_ALL_X722
6676 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6677 if (rss_hf != 0) /* Enable RSS */
6679 return 0; /* Nothing to do */
6682 if (rss_hf == 0) /* Disable RSS */
6685 return i40e_hw_rss_hash_set(pf, rss_conf);
6689 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6690 struct rte_eth_rss_conf *rss_conf)
6692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6697 &rss_conf->rss_key_len);
6699 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6700 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6701 rss_conf->rss_hf = i40e_parse_hena(hena);
6707 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6709 switch (filter_type) {
6710 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6711 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6713 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6714 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6716 case RTE_TUNNEL_FILTER_IMAC_TENID:
6717 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6719 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6720 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6722 case ETH_TUNNEL_FILTER_IMAC:
6723 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6725 case ETH_TUNNEL_FILTER_OIP:
6726 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6728 case ETH_TUNNEL_FILTER_IIP:
6729 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6732 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6739 /* Convert tunnel filter structure */
6741 i40e_tunnel_filter_convert(
6742 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6743 struct i40e_tunnel_filter *tunnel_filter)
6745 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6746 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6747 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6748 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6749 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6750 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6751 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6752 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6753 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6755 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6756 tunnel_filter->input.flags = cld_filter->element.flags;
6757 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6758 tunnel_filter->queue = cld_filter->element.queue_number;
6759 rte_memcpy(tunnel_filter->input.general_fields,
6760 cld_filter->general_fields,
6761 sizeof(cld_filter->general_fields));
6766 /* Check if there exists the tunnel filter */
6767 struct i40e_tunnel_filter *
6768 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6769 const struct i40e_tunnel_filter_input *input)
6773 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6777 return tunnel_rule->hash_map[ret];
6780 /* Add a tunnel filter into the SW list */
6782 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6783 struct i40e_tunnel_filter *tunnel_filter)
6785 struct i40e_tunnel_rule *rule = &pf->tunnel;
6788 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6791 "Failed to insert tunnel filter to hash table %d!",
6795 rule->hash_map[ret] = tunnel_filter;
6797 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6802 /* Delete a tunnel filter from the SW list */
6804 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6805 struct i40e_tunnel_filter_input *input)
6807 struct i40e_tunnel_rule *rule = &pf->tunnel;
6808 struct i40e_tunnel_filter *tunnel_filter;
6811 ret = rte_hash_del_key(rule->hash_table, input);
6814 "Failed to delete tunnel filter to hash table %d!",
6818 tunnel_filter = rule->hash_map[ret];
6819 rule->hash_map[ret] = NULL;
6821 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6822 rte_free(tunnel_filter);
6828 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6829 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6834 uint8_t i, tun_type = 0;
6835 /* internal varialbe to convert ipv6 byte order */
6836 uint32_t convert_ipv6[4];
6838 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6839 struct i40e_vsi *vsi = pf->main_vsi;
6840 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6841 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6842 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6843 struct i40e_tunnel_filter *tunnel, *node;
6844 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6846 cld_filter = rte_zmalloc("tunnel_filter",
6847 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6850 if (NULL == cld_filter) {
6851 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6854 pfilter = cld_filter;
6856 ether_addr_copy(&tunnel_filter->outer_mac,
6857 (struct ether_addr *)&pfilter->element.outer_mac);
6858 ether_addr_copy(&tunnel_filter->inner_mac,
6859 (struct ether_addr *)&pfilter->element.inner_mac);
6861 pfilter->element.inner_vlan =
6862 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6863 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6864 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6865 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6866 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6867 &rte_cpu_to_le_32(ipv4_addr),
6868 sizeof(pfilter->element.ipaddr.v4.data));
6870 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6871 for (i = 0; i < 4; i++) {
6873 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6875 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6877 sizeof(pfilter->element.ipaddr.v6.data));
6880 /* check tunneled type */
6881 switch (tunnel_filter->tunnel_type) {
6882 case RTE_TUNNEL_TYPE_VXLAN:
6883 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6885 case RTE_TUNNEL_TYPE_NVGRE:
6886 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6888 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6889 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6892 /* Other tunnel types is not supported. */
6893 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6894 rte_free(cld_filter);
6898 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6899 &pfilter->element.flags);
6901 rte_free(cld_filter);
6905 pfilter->element.flags |= rte_cpu_to_le_16(
6906 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6907 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6908 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6909 pfilter->element.queue_number =
6910 rte_cpu_to_le_16(tunnel_filter->queue_id);
6912 /* Check if there is the filter in SW list */
6913 memset(&check_filter, 0, sizeof(check_filter));
6914 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6915 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6917 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6921 if (!add && !node) {
6922 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6927 ret = i40e_aq_add_cloud_filters(hw,
6928 vsi->seid, &cld_filter->element, 1);
6930 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6933 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6934 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6935 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6937 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6938 &cld_filter->element, 1);
6940 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6943 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6946 rte_free(cld_filter);
6950 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6951 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6952 #define I40E_TR_GENEVE_KEY_MASK 0x8
6953 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6954 #define I40E_TR_GRE_KEY_MASK 0x400
6955 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6956 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6959 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6961 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6962 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6963 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6964 enum i40e_status_code status = I40E_SUCCESS;
6966 memset(&filter_replace, 0,
6967 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6968 memset(&filter_replace_buf, 0,
6969 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6971 /* create L1 filter */
6972 filter_replace.old_filter_type =
6973 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6974 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6975 filter_replace.tr_bit = 0;
6977 /* Prepare the buffer, 3 entries */
6978 filter_replace_buf.data[0] =
6979 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6980 filter_replace_buf.data[0] |=
6981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6982 filter_replace_buf.data[2] = 0xFF;
6983 filter_replace_buf.data[3] = 0xFF;
6984 filter_replace_buf.data[4] =
6985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6986 filter_replace_buf.data[4] |=
6987 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6988 filter_replace_buf.data[7] = 0xF0;
6989 filter_replace_buf.data[8]
6990 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6991 filter_replace_buf.data[8] |=
6992 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6993 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6994 I40E_TR_GENEVE_KEY_MASK |
6995 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6996 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6997 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6998 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7000 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7001 &filter_replace_buf);
7006 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7008 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7009 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7010 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7011 enum i40e_status_code status = I40E_SUCCESS;
7014 memset(&filter_replace, 0,
7015 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7016 memset(&filter_replace_buf, 0,
7017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7018 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7019 I40E_AQC_MIRROR_CLOUD_FILTER;
7020 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7021 filter_replace.new_filter_type =
7022 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7023 /* Prepare the buffer, 2 entries */
7024 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7025 filter_replace_buf.data[0] |=
7026 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7027 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7028 filter_replace_buf.data[4] |=
7029 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7030 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7031 &filter_replace_buf);
7036 memset(&filter_replace, 0,
7037 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7038 memset(&filter_replace_buf, 0,
7039 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7041 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7042 I40E_AQC_MIRROR_CLOUD_FILTER;
7043 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7044 filter_replace.new_filter_type =
7045 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7046 /* Prepare the buffer, 2 entries */
7047 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7048 filter_replace_buf.data[0] |=
7049 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7050 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7051 filter_replace_buf.data[4] |=
7052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7054 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7055 &filter_replace_buf);
7060 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7061 struct i40e_tunnel_filter_conf *tunnel_filter,
7066 uint8_t i, tun_type = 0;
7067 /* internal variable to convert ipv6 byte order */
7068 uint32_t convert_ipv6[4];
7070 struct i40e_pf_vf *vf = NULL;
7071 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7072 struct i40e_vsi *vsi;
7073 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7074 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7075 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7076 struct i40e_tunnel_filter *tunnel, *node;
7077 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7079 bool big_buffer = 0;
7081 cld_filter = rte_zmalloc("tunnel_filter",
7082 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7085 if (cld_filter == NULL) {
7086 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7089 pfilter = cld_filter;
7091 ether_addr_copy(&tunnel_filter->outer_mac,
7092 (struct ether_addr *)&pfilter->element.outer_mac);
7093 ether_addr_copy(&tunnel_filter->inner_mac,
7094 (struct ether_addr *)&pfilter->element.inner_mac);
7096 pfilter->element.inner_vlan =
7097 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7098 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7099 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7100 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7101 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7102 &rte_cpu_to_le_32(ipv4_addr),
7103 sizeof(pfilter->element.ipaddr.v4.data));
7105 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7106 for (i = 0; i < 4; i++) {
7108 rte_cpu_to_le_32(rte_be_to_cpu_32(
7109 tunnel_filter->ip_addr.ipv6_addr[i]));
7111 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7113 sizeof(pfilter->element.ipaddr.v6.data));
7116 /* check tunneled type */
7117 switch (tunnel_filter->tunnel_type) {
7118 case I40E_TUNNEL_TYPE_VXLAN:
7119 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7121 case I40E_TUNNEL_TYPE_NVGRE:
7122 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7124 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7125 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7127 case I40E_TUNNEL_TYPE_MPLSoUDP:
7128 if (!pf->mpls_replace_flag) {
7129 i40e_replace_mpls_l1_filter(pf);
7130 i40e_replace_mpls_cloud_filter(pf);
7131 pf->mpls_replace_flag = 1;
7133 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7134 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7136 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7137 (teid_le & 0xF) << 12;
7138 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7141 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7143 case I40E_TUNNEL_TYPE_MPLSoGRE:
7144 if (!pf->mpls_replace_flag) {
7145 i40e_replace_mpls_l1_filter(pf);
7146 i40e_replace_mpls_cloud_filter(pf);
7147 pf->mpls_replace_flag = 1;
7149 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7152 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7153 (teid_le & 0xF) << 12;
7154 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7157 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7159 case I40E_TUNNEL_TYPE_QINQ:
7160 if (!pf->qinq_replace_flag) {
7161 ret = i40e_cloud_filter_qinq_create(pf);
7164 "Failed to create a qinq tunnel filter.");
7165 pf->qinq_replace_flag = 1;
7167 /* Add in the General fields the values of
7168 * the Outer and Inner VLAN
7169 * Big Buffer should be set, see changes in
7170 * i40e_aq_add_cloud_filters
7172 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7173 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7177 /* Other tunnel types is not supported. */
7178 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7179 rte_free(cld_filter);
7183 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7184 pfilter->element.flags =
7185 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7186 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7187 pfilter->element.flags =
7188 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7189 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7190 pfilter->element.flags |=
7191 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7193 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7194 &pfilter->element.flags);
7196 rte_free(cld_filter);
7201 pfilter->element.flags |= rte_cpu_to_le_16(
7202 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7203 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7204 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7205 pfilter->element.queue_number =
7206 rte_cpu_to_le_16(tunnel_filter->queue_id);
7208 if (!tunnel_filter->is_to_vf)
7211 if (tunnel_filter->vf_id >= pf->vf_num) {
7212 PMD_DRV_LOG(ERR, "Invalid argument.");
7215 vf = &pf->vfs[tunnel_filter->vf_id];
7219 /* Check if there is the filter in SW list */
7220 memset(&check_filter, 0, sizeof(check_filter));
7221 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7222 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7224 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7228 if (!add && !node) {
7229 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7235 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7236 vsi->seid, cld_filter, 1);
7238 ret = i40e_aq_add_cloud_filters(hw,
7239 vsi->seid, &cld_filter->element, 1);
7241 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7244 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7245 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7246 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7249 ret = i40e_aq_remove_cloud_filters_big_buffer(
7250 hw, vsi->seid, cld_filter, 1);
7252 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7253 &cld_filter->element, 1);
7255 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7258 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7261 rte_free(cld_filter);
7266 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7270 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7271 if (pf->vxlan_ports[i] == port)
7279 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7283 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7285 idx = i40e_get_vxlan_port_idx(pf, port);
7287 /* Check if port already exists */
7289 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7293 /* Now check if there is space to add the new port */
7294 idx = i40e_get_vxlan_port_idx(pf, 0);
7297 "Maximum number of UDP ports reached, not adding port %d",
7302 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7305 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7309 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7312 /* New port: add it and mark its index in the bitmap */
7313 pf->vxlan_ports[idx] = port;
7314 pf->vxlan_bitmap |= (1 << idx);
7316 if (!(pf->flags & I40E_FLAG_VXLAN))
7317 pf->flags |= I40E_FLAG_VXLAN;
7323 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7326 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7328 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7329 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7333 idx = i40e_get_vxlan_port_idx(pf, port);
7336 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7340 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7341 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7345 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7348 pf->vxlan_ports[idx] = 0;
7349 pf->vxlan_bitmap &= ~(1 << idx);
7351 if (!pf->vxlan_bitmap)
7352 pf->flags &= ~I40E_FLAG_VXLAN;
7357 /* Add UDP tunneling port */
7359 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7360 struct rte_eth_udp_tunnel *udp_tunnel)
7363 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7365 if (udp_tunnel == NULL)
7368 switch (udp_tunnel->prot_type) {
7369 case RTE_TUNNEL_TYPE_VXLAN:
7370 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7373 case RTE_TUNNEL_TYPE_GENEVE:
7374 case RTE_TUNNEL_TYPE_TEREDO:
7375 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7380 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7388 /* Remove UDP tunneling port */
7390 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7391 struct rte_eth_udp_tunnel *udp_tunnel)
7394 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7396 if (udp_tunnel == NULL)
7399 switch (udp_tunnel->prot_type) {
7400 case RTE_TUNNEL_TYPE_VXLAN:
7401 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7403 case RTE_TUNNEL_TYPE_GENEVE:
7404 case RTE_TUNNEL_TYPE_TEREDO:
7405 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7409 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7417 /* Calculate the maximum number of contiguous PF queues that are configured */
7419 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7421 struct rte_eth_dev_data *data = pf->dev_data;
7423 struct i40e_rx_queue *rxq;
7426 for (i = 0; i < pf->lan_nb_qps; i++) {
7427 rxq = data->rx_queues[i];
7428 if (rxq && rxq->q_set)
7439 i40e_pf_config_rss(struct i40e_pf *pf)
7441 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7442 struct rte_eth_rss_conf rss_conf;
7443 uint32_t i, lut = 0;
7447 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7448 * It's necessary to calulate the actual PF queues that are configured.
7450 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7451 num = i40e_pf_calc_configured_queues_num(pf);
7453 num = pf->dev_data->nb_rx_queues;
7455 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7456 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7460 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7464 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7467 lut = (lut << 8) | (j & ((0x1 <<
7468 hw->func_caps.rss_table_entry_width) - 1));
7470 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7473 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7474 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7475 i40e_pf_disable_rss(pf);
7478 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7479 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7480 /* Random default keys */
7481 static uint32_t rss_key_default[] = {0x6b793944,
7482 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7483 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7484 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7486 rss_conf.rss_key = (uint8_t *)rss_key_default;
7487 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7491 return i40e_hw_rss_hash_set(pf, &rss_conf);
7495 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7496 struct rte_eth_tunnel_filter_conf *filter)
7498 if (pf == NULL || filter == NULL) {
7499 PMD_DRV_LOG(ERR, "Invalid parameter");
7503 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7504 PMD_DRV_LOG(ERR, "Invalid queue ID");
7508 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7509 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7513 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7514 (is_zero_ether_addr(&filter->outer_mac))) {
7515 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7519 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7520 (is_zero_ether_addr(&filter->inner_mac))) {
7521 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7528 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7529 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7531 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7536 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7537 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7540 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7541 } else if (len == 4) {
7542 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7544 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7549 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7556 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7557 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7563 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7570 switch (cfg->cfg_type) {
7571 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7572 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7575 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7583 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7584 enum rte_filter_op filter_op,
7587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7588 int ret = I40E_ERR_PARAM;
7590 switch (filter_op) {
7591 case RTE_ETH_FILTER_SET:
7592 ret = i40e_dev_global_config_set(hw,
7593 (struct rte_eth_global_cfg *)arg);
7596 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7604 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7605 enum rte_filter_op filter_op,
7608 struct rte_eth_tunnel_filter_conf *filter;
7609 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7610 int ret = I40E_SUCCESS;
7612 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7614 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7615 return I40E_ERR_PARAM;
7617 switch (filter_op) {
7618 case RTE_ETH_FILTER_NOP:
7619 if (!(pf->flags & I40E_FLAG_VXLAN))
7620 ret = I40E_NOT_SUPPORTED;
7622 case RTE_ETH_FILTER_ADD:
7623 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7625 case RTE_ETH_FILTER_DELETE:
7626 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7629 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7630 ret = I40E_ERR_PARAM;
7638 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7641 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7644 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7645 ret = i40e_pf_config_rss(pf);
7647 i40e_pf_disable_rss(pf);
7652 /* Get the symmetric hash enable configurations per port */
7654 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7656 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7658 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7661 /* Set the symmetric hash enable configurations per port */
7663 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7665 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7668 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7670 "Symmetric hash has already been enabled");
7673 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7675 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7677 "Symmetric hash has already been disabled");
7680 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7682 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7683 I40E_WRITE_FLUSH(hw);
7687 * Get global configurations of hash function type and symmetric hash enable
7688 * per flow type (pctype). Note that global configuration means it affects all
7689 * the ports on the same NIC.
7692 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7693 struct rte_eth_hash_global_conf *g_cfg)
7695 uint32_t reg, mask = I40E_FLOW_TYPES;
7697 enum i40e_filter_pctype pctype;
7699 memset(g_cfg, 0, sizeof(*g_cfg));
7700 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7701 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7702 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7704 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7705 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7706 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7708 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7709 if (!(mask & (1UL << i)))
7711 mask &= ~(1UL << i);
7712 /* Bit set indicats the coresponding flow type is supported */
7713 g_cfg->valid_bit_mask[0] |= (1UL << i);
7714 /* if flowtype is invalid, continue */
7715 if (!I40E_VALID_FLOW(i))
7717 pctype = i40e_flowtype_to_pctype(i);
7718 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7719 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7720 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7727 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7730 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7732 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7733 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7734 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7735 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7741 * As i40e supports less than 32 flow types, only first 32 bits need to
7744 mask0 = g_cfg->valid_bit_mask[0];
7745 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7747 /* Check if any unsupported flow type configured */
7748 if ((mask0 | i40e_mask) ^ i40e_mask)
7751 if (g_cfg->valid_bit_mask[i])
7759 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7765 * Set global configurations of hash function type and symmetric hash enable
7766 * per flow type (pctype). Note any modifying global configuration will affect
7767 * all the ports on the same NIC.
7770 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7771 struct rte_eth_hash_global_conf *g_cfg)
7776 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7777 enum i40e_filter_pctype pctype;
7779 /* Check the input parameters */
7780 ret = i40e_hash_global_config_check(g_cfg);
7784 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7785 if (!(mask0 & (1UL << i)))
7787 mask0 &= ~(1UL << i);
7788 /* if flowtype is invalid, continue */
7789 if (!I40E_VALID_FLOW(i))
7791 pctype = i40e_flowtype_to_pctype(i);
7792 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7793 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7794 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7797 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7798 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7800 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7802 "Hash function already set to Toeplitz");
7805 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7806 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7808 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7810 "Hash function already set to Simple XOR");
7813 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7815 /* Use the default, and keep it as it is */
7818 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7821 I40E_WRITE_FLUSH(hw);
7827 * Valid input sets for hash and flow director filters per PCTYPE
7830 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7831 enum rte_filter_type filter)
7835 static const uint64_t valid_hash_inset_table[] = {
7836 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7837 I40E_INSET_DMAC | I40E_INSET_SMAC |
7838 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7839 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7840 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7841 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7842 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7843 I40E_INSET_FLEX_PAYLOAD,
7844 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7845 I40E_INSET_DMAC | I40E_INSET_SMAC |
7846 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7847 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7848 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7849 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7850 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7851 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7852 I40E_INSET_FLEX_PAYLOAD,
7853 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7854 I40E_INSET_DMAC | I40E_INSET_SMAC |
7855 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7856 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7857 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7858 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7859 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7860 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7861 I40E_INSET_FLEX_PAYLOAD,
7862 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7863 I40E_INSET_DMAC | I40E_INSET_SMAC |
7864 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7865 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7866 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7867 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7868 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7869 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7870 I40E_INSET_FLEX_PAYLOAD,
7871 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7872 I40E_INSET_DMAC | I40E_INSET_SMAC |
7873 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7874 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7875 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7876 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7877 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7878 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7879 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7880 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7881 I40E_INSET_DMAC | I40E_INSET_SMAC |
7882 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7883 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7884 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7885 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7886 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7887 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7888 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7889 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7890 I40E_INSET_DMAC | I40E_INSET_SMAC |
7891 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7892 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7893 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7894 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7895 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7896 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7897 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7898 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7899 I40E_INSET_DMAC | I40E_INSET_SMAC |
7900 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7901 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7902 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7903 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7904 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7905 I40E_INSET_FLEX_PAYLOAD,
7906 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7907 I40E_INSET_DMAC | I40E_INSET_SMAC |
7908 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7909 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7910 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7911 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7912 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7913 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7914 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7915 I40E_INSET_DMAC | I40E_INSET_SMAC |
7916 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7917 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7918 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7919 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7920 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7921 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7922 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7923 I40E_INSET_DMAC | I40E_INSET_SMAC |
7924 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7925 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7926 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7927 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7928 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7929 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7930 I40E_INSET_FLEX_PAYLOAD,
7931 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7932 I40E_INSET_DMAC | I40E_INSET_SMAC |
7933 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7934 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7935 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7936 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7937 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7938 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7939 I40E_INSET_FLEX_PAYLOAD,
7940 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7941 I40E_INSET_DMAC | I40E_INSET_SMAC |
7942 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7943 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7944 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7945 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7946 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7947 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7948 I40E_INSET_FLEX_PAYLOAD,
7949 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7950 I40E_INSET_DMAC | I40E_INSET_SMAC |
7951 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7952 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7953 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7954 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7955 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7956 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7957 I40E_INSET_FLEX_PAYLOAD,
7958 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7959 I40E_INSET_DMAC | I40E_INSET_SMAC |
7960 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7961 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7962 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7963 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7964 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7965 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7966 I40E_INSET_FLEX_PAYLOAD,
7967 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7968 I40E_INSET_DMAC | I40E_INSET_SMAC |
7969 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7970 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7971 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7972 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7973 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7974 I40E_INSET_FLEX_PAYLOAD,
7975 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7976 I40E_INSET_DMAC | I40E_INSET_SMAC |
7977 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7978 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7979 I40E_INSET_FLEX_PAYLOAD,
7983 * Flow director supports only fields defined in
7984 * union rte_eth_fdir_flow.
7986 static const uint64_t valid_fdir_inset_table[] = {
7987 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7988 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7989 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7990 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7991 I40E_INSET_IPV4_TTL,
7992 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7993 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7994 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7995 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7996 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7997 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7998 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7999 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8000 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8001 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8002 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8003 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8004 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8005 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8006 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8007 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8008 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8009 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8010 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8011 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8012 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8013 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8015 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8016 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8017 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8018 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8019 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8020 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8021 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8023 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8024 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8025 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8026 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8027 I40E_INSET_IPV4_TTL,
8028 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8031 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8032 I40E_INSET_IPV6_HOP_LIMIT,
8033 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8034 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8035 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8036 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8037 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8038 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8039 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8041 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8042 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8043 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8044 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8046 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8047 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8048 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8049 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8050 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8051 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8052 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8053 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8054 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8055 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8056 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8057 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8058 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8060 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8061 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8062 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8064 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8065 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8067 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8068 I40E_INSET_IPV6_HOP_LIMIT,
8069 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8070 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8071 I40E_INSET_LAST_ETHER_TYPE,
8074 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8076 if (filter == RTE_ETH_FILTER_HASH)
8077 valid = valid_hash_inset_table[pctype];
8079 valid = valid_fdir_inset_table[pctype];
8085 * Validate if the input set is allowed for a specific PCTYPE
8088 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8089 enum rte_filter_type filter, uint64_t inset)
8093 valid = i40e_get_valid_input_set(pctype, filter);
8094 if (inset & (~valid))
8100 /* default input set fields combination per pctype */
8102 i40e_get_default_input_set(uint16_t pctype)
8104 static const uint64_t default_inset_table[] = {
8105 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8106 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8107 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8108 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8109 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8110 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8111 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8112 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8113 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8114 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8115 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8116 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8117 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8118 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8119 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8120 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8121 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8122 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8123 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8124 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8126 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8127 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8128 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8129 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8130 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8131 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8132 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8133 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8134 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8135 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8136 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8137 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8138 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8139 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8140 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8141 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8142 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8143 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8144 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8145 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8146 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8147 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8149 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8150 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8151 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8152 I40E_INSET_LAST_ETHER_TYPE,
8155 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8158 return default_inset_table[pctype];
8162 * Parse the input set from index to logical bit masks
8165 i40e_parse_input_set(uint64_t *inset,
8166 enum i40e_filter_pctype pctype,
8167 enum rte_eth_input_set_field *field,
8173 static const struct {
8174 enum rte_eth_input_set_field field;
8176 } inset_convert_table[] = {
8177 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8178 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8179 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8180 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8181 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8182 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8183 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8184 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8185 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8186 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8187 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8188 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8189 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8190 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8191 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8192 I40E_INSET_IPV6_NEXT_HDR},
8193 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8194 I40E_INSET_IPV6_HOP_LIMIT},
8195 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8196 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8197 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8198 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8199 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8200 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8201 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8202 I40E_INSET_SCTP_VT},
8203 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8204 I40E_INSET_TUNNEL_DMAC},
8205 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8206 I40E_INSET_VLAN_TUNNEL},
8207 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8208 I40E_INSET_TUNNEL_ID},
8209 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8210 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8211 I40E_INSET_FLEX_PAYLOAD_W1},
8212 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8213 I40E_INSET_FLEX_PAYLOAD_W2},
8214 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8215 I40E_INSET_FLEX_PAYLOAD_W3},
8216 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8217 I40E_INSET_FLEX_PAYLOAD_W4},
8218 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8219 I40E_INSET_FLEX_PAYLOAD_W5},
8220 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8221 I40E_INSET_FLEX_PAYLOAD_W6},
8222 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8223 I40E_INSET_FLEX_PAYLOAD_W7},
8224 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8225 I40E_INSET_FLEX_PAYLOAD_W8},
8228 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8231 /* Only one item allowed for default or all */
8233 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8234 *inset = i40e_get_default_input_set(pctype);
8236 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8237 *inset = I40E_INSET_NONE;
8242 for (i = 0, *inset = 0; i < size; i++) {
8243 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8244 if (field[i] == inset_convert_table[j].field) {
8245 *inset |= inset_convert_table[j].inset;
8250 /* It contains unsupported input set, return immediately */
8251 if (j == RTE_DIM(inset_convert_table))
8259 * Translate the input set from bit masks to register aware bit masks
8263 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8273 static const struct inset_map inset_map_common[] = {
8274 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8275 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8276 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8277 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8278 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8279 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8280 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8281 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8282 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8283 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8284 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8285 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8286 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8287 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8288 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8289 {I40E_INSET_TUNNEL_DMAC,
8290 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8291 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8292 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8293 {I40E_INSET_TUNNEL_SRC_PORT,
8294 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8295 {I40E_INSET_TUNNEL_DST_PORT,
8296 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8297 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8298 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8299 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8300 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8301 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8302 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8303 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8304 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8305 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8308 /* some different registers map in x722*/
8309 static const struct inset_map inset_map_diff_x722[] = {
8310 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8311 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8312 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8313 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8316 static const struct inset_map inset_map_diff_not_x722[] = {
8317 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8318 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8319 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8320 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8326 /* Translate input set to register aware inset */
8327 if (type == I40E_MAC_X722) {
8328 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8329 if (input & inset_map_diff_x722[i].inset)
8330 val |= inset_map_diff_x722[i].inset_reg;
8333 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8334 if (input & inset_map_diff_not_x722[i].inset)
8335 val |= inset_map_diff_not_x722[i].inset_reg;
8339 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8340 if (input & inset_map_common[i].inset)
8341 val |= inset_map_common[i].inset_reg;
8348 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8351 uint64_t inset_need_mask = inset;
8353 static const struct {
8356 } inset_mask_map[] = {
8357 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8358 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8359 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8360 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8361 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8362 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8363 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8364 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8367 if (!inset || !mask || !nb_elem)
8370 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8371 /* Clear the inset bit, if no MASK is required,
8372 * for example proto + ttl
8374 if ((inset & inset_mask_map[i].inset) ==
8375 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8376 inset_need_mask &= ~inset_mask_map[i].inset;
8377 if (!inset_need_mask)
8380 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8381 if ((inset_need_mask & inset_mask_map[i].inset) ==
8382 inset_mask_map[i].inset) {
8383 if (idx >= nb_elem) {
8384 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8387 mask[idx] = inset_mask_map[i].mask;
8396 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8398 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8400 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8402 i40e_write_rx_ctl(hw, addr, val);
8403 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8404 (uint32_t)i40e_read_rx_ctl(hw, addr));
8408 i40e_filter_input_set_init(struct i40e_pf *pf)
8410 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8411 enum i40e_filter_pctype pctype;
8412 uint64_t input_set, inset_reg;
8413 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8416 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8417 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8418 if (hw->mac.type == I40E_MAC_X722) {
8419 if (!I40E_VALID_PCTYPE_X722(pctype))
8422 if (!I40E_VALID_PCTYPE(pctype))
8426 input_set = i40e_get_default_input_set(pctype);
8428 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8429 I40E_INSET_MASK_NUM_REG);
8432 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8435 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8436 (uint32_t)(inset_reg & UINT32_MAX));
8437 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8438 (uint32_t)((inset_reg >>
8439 I40E_32_BIT_WIDTH) & UINT32_MAX));
8440 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8441 (uint32_t)(inset_reg & UINT32_MAX));
8442 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8443 (uint32_t)((inset_reg >>
8444 I40E_32_BIT_WIDTH) & UINT32_MAX));
8446 for (i = 0; i < num; i++) {
8447 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8449 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8452 /*clear unused mask registers of the pctype */
8453 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8454 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8456 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8459 I40E_WRITE_FLUSH(hw);
8461 /* store the default input set */
8462 pf->hash_input_set[pctype] = input_set;
8463 pf->fdir.input_set[pctype] = input_set;
8468 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8469 struct rte_eth_input_set_conf *conf)
8471 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8472 enum i40e_filter_pctype pctype;
8473 uint64_t input_set, inset_reg = 0;
8474 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8478 PMD_DRV_LOG(ERR, "Invalid pointer");
8481 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8482 conf->op != RTE_ETH_INPUT_SET_ADD) {
8483 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8487 if (!I40E_VALID_FLOW(conf->flow_type)) {
8488 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8492 if (hw->mac.type == I40E_MAC_X722) {
8493 /* get translated pctype value in fd pctype register */
8494 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8495 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8498 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8500 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8503 PMD_DRV_LOG(ERR, "Failed to parse input set");
8506 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8508 PMD_DRV_LOG(ERR, "Invalid input set");
8511 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8512 /* get inset value in register */
8513 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8514 inset_reg <<= I40E_32_BIT_WIDTH;
8515 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8516 input_set |= pf->hash_input_set[pctype];
8518 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8519 I40E_INSET_MASK_NUM_REG);
8523 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8525 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8526 (uint32_t)(inset_reg & UINT32_MAX));
8527 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8528 (uint32_t)((inset_reg >>
8529 I40E_32_BIT_WIDTH) & UINT32_MAX));
8531 for (i = 0; i < num; i++)
8532 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8534 /*clear unused mask registers of the pctype */
8535 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8536 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8538 I40E_WRITE_FLUSH(hw);
8540 pf->hash_input_set[pctype] = input_set;
8545 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8546 struct rte_eth_input_set_conf *conf)
8548 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8549 enum i40e_filter_pctype pctype;
8550 uint64_t input_set, inset_reg = 0;
8551 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8555 PMD_DRV_LOG(ERR, "Invalid pointer");
8558 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8559 conf->op != RTE_ETH_INPUT_SET_ADD) {
8560 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8564 if (!I40E_VALID_FLOW(conf->flow_type)) {
8565 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8569 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8571 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8574 PMD_DRV_LOG(ERR, "Failed to parse input set");
8577 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8579 PMD_DRV_LOG(ERR, "Invalid input set");
8583 /* get inset value in register */
8584 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8585 inset_reg <<= I40E_32_BIT_WIDTH;
8586 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8588 /* Can not change the inset reg for flex payload for fdir,
8589 * it is done by writing I40E_PRTQF_FD_FLXINSET
8590 * in i40e_set_flex_mask_on_pctype.
8592 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8593 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8595 input_set |= pf->fdir.input_set[pctype];
8596 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8597 I40E_INSET_MASK_NUM_REG);
8601 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8603 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8604 (uint32_t)(inset_reg & UINT32_MAX));
8605 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8606 (uint32_t)((inset_reg >>
8607 I40E_32_BIT_WIDTH) & UINT32_MAX));
8609 for (i = 0; i < num; i++)
8610 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8612 /*clear unused mask registers of the pctype */
8613 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8614 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8616 I40E_WRITE_FLUSH(hw);
8618 pf->fdir.input_set[pctype] = input_set;
8623 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8628 PMD_DRV_LOG(ERR, "Invalid pointer");
8632 switch (info->info_type) {
8633 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8634 i40e_get_symmetric_hash_enable_per_port(hw,
8635 &(info->info.enable));
8637 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8638 ret = i40e_get_hash_filter_global_config(hw,
8639 &(info->info.global_conf));
8642 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8652 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8657 PMD_DRV_LOG(ERR, "Invalid pointer");
8661 switch (info->info_type) {
8662 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8663 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8665 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8666 ret = i40e_set_hash_filter_global_config(hw,
8667 &(info->info.global_conf));
8669 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8670 ret = i40e_hash_filter_inset_select(hw,
8671 &(info->info.input_set_conf));
8675 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8684 /* Operations for hash function */
8686 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8687 enum rte_filter_op filter_op,
8690 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8693 switch (filter_op) {
8694 case RTE_ETH_FILTER_NOP:
8696 case RTE_ETH_FILTER_GET:
8697 ret = i40e_hash_filter_get(hw,
8698 (struct rte_eth_hash_filter_info *)arg);
8700 case RTE_ETH_FILTER_SET:
8701 ret = i40e_hash_filter_set(hw,
8702 (struct rte_eth_hash_filter_info *)arg);
8705 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8714 /* Convert ethertype filter structure */
8716 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8717 struct i40e_ethertype_filter *filter)
8719 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8720 filter->input.ether_type = input->ether_type;
8721 filter->flags = input->flags;
8722 filter->queue = input->queue;
8727 /* Check if there exists the ehtertype filter */
8728 struct i40e_ethertype_filter *
8729 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8730 const struct i40e_ethertype_filter_input *input)
8734 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8738 return ethertype_rule->hash_map[ret];
8741 /* Add ethertype filter in SW list */
8743 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8744 struct i40e_ethertype_filter *filter)
8746 struct i40e_ethertype_rule *rule = &pf->ethertype;
8749 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8752 "Failed to insert ethertype filter"
8753 " to hash table %d!",
8757 rule->hash_map[ret] = filter;
8759 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8764 /* Delete ethertype filter in SW list */
8766 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8767 struct i40e_ethertype_filter_input *input)
8769 struct i40e_ethertype_rule *rule = &pf->ethertype;
8770 struct i40e_ethertype_filter *filter;
8773 ret = rte_hash_del_key(rule->hash_table, input);
8776 "Failed to delete ethertype filter"
8777 " to hash table %d!",
8781 filter = rule->hash_map[ret];
8782 rule->hash_map[ret] = NULL;
8784 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8791 * Configure ethertype filter, which can director packet by filtering
8792 * with mac address and ether_type or only ether_type
8795 i40e_ethertype_filter_set(struct i40e_pf *pf,
8796 struct rte_eth_ethertype_filter *filter,
8799 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8800 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8801 struct i40e_ethertype_filter *ethertype_filter, *node;
8802 struct i40e_ethertype_filter check_filter;
8803 struct i40e_control_filter_stats stats;
8807 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8808 PMD_DRV_LOG(ERR, "Invalid queue ID");
8811 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8812 filter->ether_type == ETHER_TYPE_IPv6) {
8814 "unsupported ether_type(0x%04x) in control packet filter.",
8815 filter->ether_type);
8818 if (filter->ether_type == ETHER_TYPE_VLAN)
8819 PMD_DRV_LOG(WARNING,
8820 "filter vlan ether_type in first tag is not supported.");
8822 /* Check if there is the filter in SW list */
8823 memset(&check_filter, 0, sizeof(check_filter));
8824 i40e_ethertype_filter_convert(filter, &check_filter);
8825 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8826 &check_filter.input);
8828 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8832 if (!add && !node) {
8833 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8837 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8838 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8839 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8840 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8841 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8843 memset(&stats, 0, sizeof(stats));
8844 ret = i40e_aq_add_rem_control_packet_filter(hw,
8845 filter->mac_addr.addr_bytes,
8846 filter->ether_type, flags,
8848 filter->queue, add, &stats, NULL);
8851 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8852 ret, stats.mac_etype_used, stats.etype_used,
8853 stats.mac_etype_free, stats.etype_free);
8857 /* Add or delete a filter in SW list */
8859 ethertype_filter = rte_zmalloc("ethertype_filter",
8860 sizeof(*ethertype_filter), 0);
8861 rte_memcpy(ethertype_filter, &check_filter,
8862 sizeof(check_filter));
8863 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8865 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8872 * Handle operations for ethertype filter.
8875 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8876 enum rte_filter_op filter_op,
8879 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8882 if (filter_op == RTE_ETH_FILTER_NOP)
8886 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8891 switch (filter_op) {
8892 case RTE_ETH_FILTER_ADD:
8893 ret = i40e_ethertype_filter_set(pf,
8894 (struct rte_eth_ethertype_filter *)arg,
8897 case RTE_ETH_FILTER_DELETE:
8898 ret = i40e_ethertype_filter_set(pf,
8899 (struct rte_eth_ethertype_filter *)arg,
8903 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8911 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8912 enum rte_filter_type filter_type,
8913 enum rte_filter_op filter_op,
8921 switch (filter_type) {
8922 case RTE_ETH_FILTER_NONE:
8923 /* For global configuration */
8924 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8926 case RTE_ETH_FILTER_HASH:
8927 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8929 case RTE_ETH_FILTER_MACVLAN:
8930 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8932 case RTE_ETH_FILTER_ETHERTYPE:
8933 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8935 case RTE_ETH_FILTER_TUNNEL:
8936 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8938 case RTE_ETH_FILTER_FDIR:
8939 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8941 case RTE_ETH_FILTER_GENERIC:
8942 if (filter_op != RTE_ETH_FILTER_GET)
8944 *(const void **)arg = &i40e_flow_ops;
8947 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8957 * Check and enable Extended Tag.
8958 * Enabling Extended Tag is important for 40G performance.
8961 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8963 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8967 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8970 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8974 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8975 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8980 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8983 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8987 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8988 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8991 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8992 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8995 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9002 * As some registers wouldn't be reset unless a global hardware reset,
9003 * hardware initialization is needed to put those registers into an
9004 * expected initial state.
9007 i40e_hw_init(struct rte_eth_dev *dev)
9009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9011 i40e_enable_extended_tag(dev);
9013 /* clear the PF Queue Filter control register */
9014 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9016 /* Disable symmetric hash per port */
9017 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9020 enum i40e_filter_pctype
9021 i40e_flowtype_to_pctype(uint16_t flow_type)
9023 static const enum i40e_filter_pctype pctype_table[] = {
9024 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9025 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9026 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9027 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9028 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9029 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9030 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9031 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9032 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9033 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9034 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9035 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9036 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9037 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9038 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9039 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9040 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9041 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9042 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9045 return pctype_table[flow_type];
9049 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9051 static const uint16_t flowtype_table[] = {
9052 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9053 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9054 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9055 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9056 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9057 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9058 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9059 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9060 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9061 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9062 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9063 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9064 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9065 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9066 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9067 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9068 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9069 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9070 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9071 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9072 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9073 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9074 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9075 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9076 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9077 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9078 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9079 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9080 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9081 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9082 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9085 return flowtype_table[pctype];
9089 * On X710, performance number is far from the expectation on recent firmware
9090 * versions; on XL710, performance number is also far from the expectation on
9091 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9092 * mode is enabled and port MAC address is equal to the packet destination MAC
9093 * address. The fix for this issue may not be integrated in the following
9094 * firmware version. So the workaround in software driver is needed. It needs
9095 * to modify the initial values of 3 internal only registers for both X710 and
9096 * XL710. Note that the values for X710 or XL710 could be different, and the
9097 * workaround can be removed when it is fixed in firmware in the future.
9100 /* For both X710 and XL710 */
9101 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9102 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9104 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9105 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9108 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9109 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9112 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9114 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9115 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9118 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9120 enum i40e_status_code status;
9121 struct i40e_aq_get_phy_abilities_resp phy_ab;
9124 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9134 i40e_configure_registers(struct i40e_hw *hw)
9140 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9141 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9142 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9148 for (i = 0; i < RTE_DIM(reg_table); i++) {
9149 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9150 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9152 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9153 else /* For X710/XL710/XXV710 */
9155 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9158 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9159 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9161 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9162 else /* For X710/XL710/XXV710 */
9164 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9167 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9168 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9169 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9171 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9174 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9177 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9180 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9184 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9185 reg_table[i].addr, reg);
9186 if (reg == reg_table[i].val)
9189 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9190 reg_table[i].val, NULL);
9193 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9194 reg_table[i].val, reg_table[i].addr);
9197 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9198 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9202 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9203 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9204 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9205 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9207 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9212 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9213 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9217 /* Configure for double VLAN RX stripping */
9218 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9219 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9220 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9221 ret = i40e_aq_debug_write_register(hw,
9222 I40E_VSI_TSR(vsi->vsi_id),
9225 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9227 return I40E_ERR_CONFIG;
9231 /* Configure for double VLAN TX insertion */
9232 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9233 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9234 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9235 ret = i40e_aq_debug_write_register(hw,
9236 I40E_VSI_L2TAGSTXVALID(
9237 vsi->vsi_id), reg, NULL);
9240 "Failed to update VSI_L2TAGSTXVALID[%d]",
9242 return I40E_ERR_CONFIG;
9250 * i40e_aq_add_mirror_rule
9251 * @hw: pointer to the hardware structure
9252 * @seid: VEB seid to add mirror rule to
9253 * @dst_id: destination vsi seid
9254 * @entries: Buffer which contains the entities to be mirrored
9255 * @count: number of entities contained in the buffer
9256 * @rule_id:the rule_id of the rule to be added
9258 * Add a mirror rule for a given veb.
9261 static enum i40e_status_code
9262 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9263 uint16_t seid, uint16_t dst_id,
9264 uint16_t rule_type, uint16_t *entries,
9265 uint16_t count, uint16_t *rule_id)
9267 struct i40e_aq_desc desc;
9268 struct i40e_aqc_add_delete_mirror_rule cmd;
9269 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9270 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9273 enum i40e_status_code status;
9275 i40e_fill_default_direct_cmd_desc(&desc,
9276 i40e_aqc_opc_add_mirror_rule);
9277 memset(&cmd, 0, sizeof(cmd));
9279 buff_len = sizeof(uint16_t) * count;
9280 desc.datalen = rte_cpu_to_le_16(buff_len);
9282 desc.flags |= rte_cpu_to_le_16(
9283 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9284 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9285 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9286 cmd.num_entries = rte_cpu_to_le_16(count);
9287 cmd.seid = rte_cpu_to_le_16(seid);
9288 cmd.destination = rte_cpu_to_le_16(dst_id);
9290 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9291 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9293 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9294 hw->aq.asq_last_status, resp->rule_id,
9295 resp->mirror_rules_used, resp->mirror_rules_free);
9296 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9302 * i40e_aq_del_mirror_rule
9303 * @hw: pointer to the hardware structure
9304 * @seid: VEB seid to add mirror rule to
9305 * @entries: Buffer which contains the entities to be mirrored
9306 * @count: number of entities contained in the buffer
9307 * @rule_id:the rule_id of the rule to be delete
9309 * Delete a mirror rule for a given veb.
9312 static enum i40e_status_code
9313 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9314 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9315 uint16_t count, uint16_t rule_id)
9317 struct i40e_aq_desc desc;
9318 struct i40e_aqc_add_delete_mirror_rule cmd;
9319 uint16_t buff_len = 0;
9320 enum i40e_status_code status;
9323 i40e_fill_default_direct_cmd_desc(&desc,
9324 i40e_aqc_opc_delete_mirror_rule);
9325 memset(&cmd, 0, sizeof(cmd));
9326 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9327 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9329 cmd.num_entries = count;
9330 buff_len = sizeof(uint16_t) * count;
9331 desc.datalen = rte_cpu_to_le_16(buff_len);
9332 buff = (void *)entries;
9334 /* rule id is filled in destination field for deleting mirror rule */
9335 cmd.destination = rte_cpu_to_le_16(rule_id);
9337 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9338 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9339 cmd.seid = rte_cpu_to_le_16(seid);
9341 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9342 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9348 * i40e_mirror_rule_set
9349 * @dev: pointer to the hardware structure
9350 * @mirror_conf: mirror rule info
9351 * @sw_id: mirror rule's sw_id
9352 * @on: enable/disable
9354 * set a mirror rule.
9358 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9359 struct rte_eth_mirror_conf *mirror_conf,
9360 uint8_t sw_id, uint8_t on)
9362 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9364 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9365 struct i40e_mirror_rule *parent = NULL;
9366 uint16_t seid, dst_seid, rule_id;
9370 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9372 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9374 "mirror rule can not be configured without veb or vfs.");
9377 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9378 PMD_DRV_LOG(ERR, "mirror table is full.");
9381 if (mirror_conf->dst_pool > pf->vf_num) {
9382 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9383 mirror_conf->dst_pool);
9387 seid = pf->main_vsi->veb->seid;
9389 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9390 if (sw_id <= it->index) {
9396 if (mirr_rule && sw_id == mirr_rule->index) {
9398 PMD_DRV_LOG(ERR, "mirror rule exists.");
9401 ret = i40e_aq_del_mirror_rule(hw, seid,
9402 mirr_rule->rule_type,
9404 mirr_rule->num_entries, mirr_rule->id);
9407 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9408 ret, hw->aq.asq_last_status);
9411 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9412 rte_free(mirr_rule);
9413 pf->nb_mirror_rule--;
9417 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9421 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9422 sizeof(struct i40e_mirror_rule) , 0);
9424 PMD_DRV_LOG(ERR, "failed to allocate memory");
9425 return I40E_ERR_NO_MEMORY;
9427 switch (mirror_conf->rule_type) {
9428 case ETH_MIRROR_VLAN:
9429 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9430 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9431 mirr_rule->entries[j] =
9432 mirror_conf->vlan.vlan_id[i];
9437 PMD_DRV_LOG(ERR, "vlan is not specified.");
9438 rte_free(mirr_rule);
9441 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9443 case ETH_MIRROR_VIRTUAL_POOL_UP:
9444 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9445 /* check if the specified pool bit is out of range */
9446 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9447 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9448 rte_free(mirr_rule);
9451 for (i = 0, j = 0; i < pf->vf_num; i++) {
9452 if (mirror_conf->pool_mask & (1ULL << i)) {
9453 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9457 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9458 /* add pf vsi to entries */
9459 mirr_rule->entries[j] = pf->main_vsi_seid;
9463 PMD_DRV_LOG(ERR, "pool is not specified.");
9464 rte_free(mirr_rule);
9467 /* egress and ingress in aq commands means from switch but not port */
9468 mirr_rule->rule_type =
9469 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9470 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9471 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9473 case ETH_MIRROR_UPLINK_PORT:
9474 /* egress and ingress in aq commands means from switch but not port*/
9475 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9477 case ETH_MIRROR_DOWNLINK_PORT:
9478 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9481 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9482 mirror_conf->rule_type);
9483 rte_free(mirr_rule);
9487 /* If the dst_pool is equal to vf_num, consider it as PF */
9488 if (mirror_conf->dst_pool == pf->vf_num)
9489 dst_seid = pf->main_vsi_seid;
9491 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9493 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9494 mirr_rule->rule_type, mirr_rule->entries,
9498 "failed to add mirror rule: ret = %d, aq_err = %d.",
9499 ret, hw->aq.asq_last_status);
9500 rte_free(mirr_rule);
9504 mirr_rule->index = sw_id;
9505 mirr_rule->num_entries = j;
9506 mirr_rule->id = rule_id;
9507 mirr_rule->dst_vsi_seid = dst_seid;
9510 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9512 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9514 pf->nb_mirror_rule++;
9519 * i40e_mirror_rule_reset
9520 * @dev: pointer to the device
9521 * @sw_id: mirror rule's sw_id
9523 * reset a mirror rule.
9527 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9530 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9531 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9535 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9537 seid = pf->main_vsi->veb->seid;
9539 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9540 if (sw_id == it->index) {
9546 ret = i40e_aq_del_mirror_rule(hw, seid,
9547 mirr_rule->rule_type,
9549 mirr_rule->num_entries, mirr_rule->id);
9552 "failed to remove mirror rule: status = %d, aq_err = %d.",
9553 ret, hw->aq.asq_last_status);
9556 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9557 rte_free(mirr_rule);
9558 pf->nb_mirror_rule--;
9560 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9567 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9570 uint64_t systim_cycles;
9572 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9573 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9576 return systim_cycles;
9580 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9582 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9585 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9586 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9593 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9595 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9598 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9599 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9606 i40e_start_timecounters(struct rte_eth_dev *dev)
9608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9609 struct i40e_adapter *adapter =
9610 (struct i40e_adapter *)dev->data->dev_private;
9611 struct rte_eth_link link;
9612 uint32_t tsync_inc_l;
9613 uint32_t tsync_inc_h;
9615 /* Get current link speed. */
9616 memset(&link, 0, sizeof(link));
9617 i40e_dev_link_update(dev, 1);
9618 rte_i40e_dev_atomic_read_link_status(dev, &link);
9620 switch (link.link_speed) {
9621 case ETH_SPEED_NUM_40G:
9622 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9623 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9625 case ETH_SPEED_NUM_10G:
9626 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9627 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9629 case ETH_SPEED_NUM_1G:
9630 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9631 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9638 /* Set the timesync increment value. */
9639 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9640 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9642 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9643 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9644 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9646 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9647 adapter->systime_tc.cc_shift = 0;
9648 adapter->systime_tc.nsec_mask = 0;
9650 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9651 adapter->rx_tstamp_tc.cc_shift = 0;
9652 adapter->rx_tstamp_tc.nsec_mask = 0;
9654 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9655 adapter->tx_tstamp_tc.cc_shift = 0;
9656 adapter->tx_tstamp_tc.nsec_mask = 0;
9660 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9662 struct i40e_adapter *adapter =
9663 (struct i40e_adapter *)dev->data->dev_private;
9665 adapter->systime_tc.nsec += delta;
9666 adapter->rx_tstamp_tc.nsec += delta;
9667 adapter->tx_tstamp_tc.nsec += delta;
9673 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9676 struct i40e_adapter *adapter =
9677 (struct i40e_adapter *)dev->data->dev_private;
9679 ns = rte_timespec_to_ns(ts);
9681 /* Set the timecounters to a new value. */
9682 adapter->systime_tc.nsec = ns;
9683 adapter->rx_tstamp_tc.nsec = ns;
9684 adapter->tx_tstamp_tc.nsec = ns;
9690 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9692 uint64_t ns, systime_cycles;
9693 struct i40e_adapter *adapter =
9694 (struct i40e_adapter *)dev->data->dev_private;
9696 systime_cycles = i40e_read_systime_cyclecounter(dev);
9697 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9698 *ts = rte_ns_to_timespec(ns);
9704 i40e_timesync_enable(struct rte_eth_dev *dev)
9706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9707 uint32_t tsync_ctl_l;
9708 uint32_t tsync_ctl_h;
9710 /* Stop the timesync system time. */
9711 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9712 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9713 /* Reset the timesync system time value. */
9714 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9715 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9717 i40e_start_timecounters(dev);
9719 /* Clear timesync registers. */
9720 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9721 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9722 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9723 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9724 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9725 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9727 /* Enable timestamping of PTP packets. */
9728 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9729 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9731 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9732 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9733 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9735 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9736 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9742 i40e_timesync_disable(struct rte_eth_dev *dev)
9744 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9745 uint32_t tsync_ctl_l;
9746 uint32_t tsync_ctl_h;
9748 /* Disable timestamping of transmitted PTP packets. */
9749 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9750 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9752 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9753 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9755 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9756 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9758 /* Reset the timesync increment value. */
9759 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9760 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9766 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9767 struct timespec *timestamp, uint32_t flags)
9769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9770 struct i40e_adapter *adapter =
9771 (struct i40e_adapter *)dev->data->dev_private;
9773 uint32_t sync_status;
9774 uint32_t index = flags & 0x03;
9775 uint64_t rx_tstamp_cycles;
9778 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9779 if ((sync_status & (1 << index)) == 0)
9782 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9783 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9784 *timestamp = rte_ns_to_timespec(ns);
9790 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9791 struct timespec *timestamp)
9793 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9794 struct i40e_adapter *adapter =
9795 (struct i40e_adapter *)dev->data->dev_private;
9797 uint32_t sync_status;
9798 uint64_t tx_tstamp_cycles;
9801 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9802 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9805 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9806 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9807 *timestamp = rte_ns_to_timespec(ns);
9813 * i40e_parse_dcb_configure - parse dcb configure from user
9814 * @dev: the device being configured
9815 * @dcb_cfg: pointer of the result of parse
9816 * @*tc_map: bit map of enabled traffic classes
9818 * Returns 0 on success, negative value on failure
9821 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9822 struct i40e_dcbx_config *dcb_cfg,
9825 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9826 uint8_t i, tc_bw, bw_lf;
9828 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9830 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9831 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9832 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9836 /* assume each tc has the same bw */
9837 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9838 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9839 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9840 /* to ensure the sum of tcbw is equal to 100 */
9841 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9842 for (i = 0; i < bw_lf; i++)
9843 dcb_cfg->etscfg.tcbwtable[i]++;
9845 /* assume each tc has the same Transmission Selection Algorithm */
9846 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9847 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9849 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9850 dcb_cfg->etscfg.prioritytable[i] =
9851 dcb_rx_conf->dcb_tc[i];
9853 /* FW needs one App to configure HW */
9854 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9855 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9856 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9857 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9859 if (dcb_rx_conf->nb_tcs == 0)
9860 *tc_map = 1; /* tc0 only */
9862 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9864 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9865 dcb_cfg->pfc.willing = 0;
9866 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9867 dcb_cfg->pfc.pfcenable = *tc_map;
9873 static enum i40e_status_code
9874 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9875 struct i40e_aqc_vsi_properties_data *info,
9876 uint8_t enabled_tcmap)
9878 enum i40e_status_code ret;
9879 int i, total_tc = 0;
9880 uint16_t qpnum_per_tc, bsf, qp_idx;
9881 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9882 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9883 uint16_t used_queues;
9885 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9886 if (ret != I40E_SUCCESS)
9889 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9890 if (enabled_tcmap & (1 << i))
9895 vsi->enabled_tc = enabled_tcmap;
9897 /* different VSI has different queues assigned */
9898 if (vsi->type == I40E_VSI_MAIN)
9899 used_queues = dev_data->nb_rx_queues -
9900 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9901 else if (vsi->type == I40E_VSI_VMDQ2)
9902 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9904 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9905 return I40E_ERR_NO_AVAILABLE_VSI;
9908 qpnum_per_tc = used_queues / total_tc;
9909 /* Number of queues per enabled TC */
9910 if (qpnum_per_tc == 0) {
9911 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9912 return I40E_ERR_INVALID_QP_ID;
9914 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9916 bsf = rte_bsf32(qpnum_per_tc);
9919 * Configure TC and queue mapping parameters, for enabled TC,
9920 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9921 * default queue will serve it.
9924 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9925 if (vsi->enabled_tc & (1 << i)) {
9926 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9927 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9928 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9929 qp_idx += qpnum_per_tc;
9931 info->tc_mapping[i] = 0;
9934 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9935 if (vsi->type == I40E_VSI_SRIOV) {
9936 info->mapping_flags |=
9937 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9938 for (i = 0; i < vsi->nb_qps; i++)
9939 info->queue_mapping[i] =
9940 rte_cpu_to_le_16(vsi->base_queue + i);
9942 info->mapping_flags |=
9943 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9944 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9946 info->valid_sections |=
9947 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9949 return I40E_SUCCESS;
9953 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9954 * @veb: VEB to be configured
9955 * @tc_map: enabled TC bitmap
9957 * Returns 0 on success, negative value on failure
9959 static enum i40e_status_code
9960 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9962 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9963 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9964 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9965 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9966 enum i40e_status_code ret = I40E_SUCCESS;
9970 /* Check if enabled_tc is same as existing or new TCs */
9971 if (veb->enabled_tc == tc_map)
9974 /* configure tc bandwidth */
9975 memset(&veb_bw, 0, sizeof(veb_bw));
9976 veb_bw.tc_valid_bits = tc_map;
9977 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9978 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9979 if (tc_map & BIT_ULL(i))
9980 veb_bw.tc_bw_share_credits[i] = 1;
9982 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9986 "AQ command Config switch_comp BW allocation per TC failed = %d",
9987 hw->aq.asq_last_status);
9991 memset(&ets_query, 0, sizeof(ets_query));
9992 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9994 if (ret != I40E_SUCCESS) {
9996 "Failed to get switch_comp ETS configuration %u",
9997 hw->aq.asq_last_status);
10000 memset(&bw_query, 0, sizeof(bw_query));
10001 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10003 if (ret != I40E_SUCCESS) {
10005 "Failed to get switch_comp bandwidth configuration %u",
10006 hw->aq.asq_last_status);
10010 /* store and print out BW info */
10011 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10012 veb->bw_info.bw_max = ets_query.tc_bw_max;
10013 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10014 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10015 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10016 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10017 I40E_16_BIT_WIDTH);
10018 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10019 veb->bw_info.bw_ets_share_credits[i] =
10020 bw_query.tc_bw_share_credits[i];
10021 veb->bw_info.bw_ets_credits[i] =
10022 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10023 /* 4 bits per TC, 4th bit is reserved */
10024 veb->bw_info.bw_ets_max[i] =
10025 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10026 RTE_LEN2MASK(3, uint8_t));
10027 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10028 veb->bw_info.bw_ets_share_credits[i]);
10029 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10030 veb->bw_info.bw_ets_credits[i]);
10031 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10032 veb->bw_info.bw_ets_max[i]);
10035 veb->enabled_tc = tc_map;
10042 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10043 * @vsi: VSI to be configured
10044 * @tc_map: enabled TC bitmap
10046 * Returns 0 on success, negative value on failure
10048 static enum i40e_status_code
10049 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10051 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10052 struct i40e_vsi_context ctxt;
10053 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10054 enum i40e_status_code ret = I40E_SUCCESS;
10057 /* Check if enabled_tc is same as existing or new TCs */
10058 if (vsi->enabled_tc == tc_map)
10061 /* configure tc bandwidth */
10062 memset(&bw_data, 0, sizeof(bw_data));
10063 bw_data.tc_valid_bits = tc_map;
10064 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10065 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10066 if (tc_map & BIT_ULL(i))
10067 bw_data.tc_bw_credits[i] = 1;
10069 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10072 "AQ command Config VSI BW allocation per TC failed = %d",
10073 hw->aq.asq_last_status);
10076 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10077 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10079 /* Update Queue Pairs Mapping for currently enabled UPs */
10080 ctxt.seid = vsi->seid;
10081 ctxt.pf_num = hw->pf_id;
10083 ctxt.uplink_seid = vsi->uplink_seid;
10084 ctxt.info = vsi->info;
10086 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10090 /* Update the VSI after updating the VSI queue-mapping information */
10091 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10093 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10094 hw->aq.asq_last_status);
10097 /* update the local VSI info with updated queue map */
10098 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10099 sizeof(vsi->info.tc_mapping));
10100 (void)rte_memcpy(&vsi->info.queue_mapping,
10101 &ctxt.info.queue_mapping,
10102 sizeof(vsi->info.queue_mapping));
10103 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10104 vsi->info.valid_sections = 0;
10106 /* query and update current VSI BW information */
10107 ret = i40e_vsi_get_bw_config(vsi);
10110 "Failed updating vsi bw info, err %s aq_err %s",
10111 i40e_stat_str(hw, ret),
10112 i40e_aq_str(hw, hw->aq.asq_last_status));
10116 vsi->enabled_tc = tc_map;
10123 * i40e_dcb_hw_configure - program the dcb setting to hw
10124 * @pf: pf the configuration is taken on
10125 * @new_cfg: new configuration
10126 * @tc_map: enabled TC bitmap
10128 * Returns 0 on success, negative value on failure
10130 static enum i40e_status_code
10131 i40e_dcb_hw_configure(struct i40e_pf *pf,
10132 struct i40e_dcbx_config *new_cfg,
10135 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10136 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10137 struct i40e_vsi *main_vsi = pf->main_vsi;
10138 struct i40e_vsi_list *vsi_list;
10139 enum i40e_status_code ret;
10143 /* Use the FW API if FW > v4.4*/
10144 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10145 (hw->aq.fw_maj_ver >= 5))) {
10147 "FW < v4.4, can not use FW LLDP API to configure DCB");
10148 return I40E_ERR_FIRMWARE_API_VERSION;
10151 /* Check if need reconfiguration */
10152 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10153 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10154 return I40E_SUCCESS;
10157 /* Copy the new config to the current config */
10158 *old_cfg = *new_cfg;
10159 old_cfg->etsrec = old_cfg->etscfg;
10160 ret = i40e_set_dcb_config(hw);
10162 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10163 i40e_stat_str(hw, ret),
10164 i40e_aq_str(hw, hw->aq.asq_last_status));
10167 /* set receive Arbiter to RR mode and ETS scheme by default */
10168 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10169 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10170 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10171 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10172 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10173 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10174 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10175 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10176 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10177 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10178 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10179 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10180 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10182 /* get local mib to check whether it is configured correctly */
10184 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10185 /* Get Local DCB Config */
10186 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10187 &hw->local_dcbx_config);
10189 /* if Veb is created, need to update TC of it at first */
10190 if (main_vsi->veb) {
10191 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10193 PMD_INIT_LOG(WARNING,
10194 "Failed configuring TC for VEB seid=%d",
10195 main_vsi->veb->seid);
10197 /* Update each VSI */
10198 i40e_vsi_config_tc(main_vsi, tc_map);
10199 if (main_vsi->veb) {
10200 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10201 /* Beside main VSI and VMDQ VSIs, only enable default
10202 * TC for other VSIs
10204 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10205 ret = i40e_vsi_config_tc(vsi_list->vsi,
10208 ret = i40e_vsi_config_tc(vsi_list->vsi,
10209 I40E_DEFAULT_TCMAP);
10211 PMD_INIT_LOG(WARNING,
10212 "Failed configuring TC for VSI seid=%d",
10213 vsi_list->vsi->seid);
10217 return I40E_SUCCESS;
10221 * i40e_dcb_init_configure - initial dcb config
10222 * @dev: device being configured
10223 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10225 * Returns 0 on success, negative value on failure
10228 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10230 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10231 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10234 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10235 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10239 /* DCB initialization:
10240 * Update DCB configuration from the Firmware and configure
10241 * LLDP MIB change event.
10243 if (sw_dcb == TRUE) {
10244 ret = i40e_init_dcb(hw);
10245 /* If lldp agent is stopped, the return value from
10246 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10247 * adminq status. Otherwise, it should return success.
10249 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10250 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10251 memset(&hw->local_dcbx_config, 0,
10252 sizeof(struct i40e_dcbx_config));
10253 /* set dcb default configuration */
10254 hw->local_dcbx_config.etscfg.willing = 0;
10255 hw->local_dcbx_config.etscfg.maxtcs = 0;
10256 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10257 hw->local_dcbx_config.etscfg.tsatable[0] =
10259 /* all UPs mapping to TC0 */
10260 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10261 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10262 hw->local_dcbx_config.etsrec =
10263 hw->local_dcbx_config.etscfg;
10264 hw->local_dcbx_config.pfc.willing = 0;
10265 hw->local_dcbx_config.pfc.pfccap =
10266 I40E_MAX_TRAFFIC_CLASS;
10267 hw->local_dcbx_config.pfc.pfcenable =
10268 I40E_DEFAULT_TCMAP;
10269 /* FW needs one App to configure HW */
10270 hw->local_dcbx_config.numapps = 1;
10271 hw->local_dcbx_config.app[0].selector =
10272 I40E_APP_SEL_ETHTYPE;
10273 hw->local_dcbx_config.app[0].priority = 3;
10274 hw->local_dcbx_config.app[0].protocolid =
10275 I40E_APP_PROTOID_FCOE;
10276 ret = i40e_set_dcb_config(hw);
10279 "default dcb config fails. err = %d, aq_err = %d.",
10280 ret, hw->aq.asq_last_status);
10285 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10286 ret, hw->aq.asq_last_status);
10290 ret = i40e_aq_start_lldp(hw, NULL);
10291 if (ret != I40E_SUCCESS)
10292 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10294 ret = i40e_init_dcb(hw);
10296 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10298 "HW doesn't support DCBX offload.");
10303 "DCBX configuration failed, err = %d, aq_err = %d.",
10304 ret, hw->aq.asq_last_status);
10312 * i40e_dcb_setup - setup dcb related config
10313 * @dev: device being configured
10315 * Returns 0 on success, negative value on failure
10318 i40e_dcb_setup(struct rte_eth_dev *dev)
10320 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10321 struct i40e_dcbx_config dcb_cfg;
10322 uint8_t tc_map = 0;
10325 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10326 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10330 if (pf->vf_num != 0)
10331 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10333 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10335 PMD_INIT_LOG(ERR, "invalid dcb config");
10338 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10340 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10348 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10349 struct rte_eth_dcb_info *dcb_info)
10351 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10352 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10353 struct i40e_vsi *vsi = pf->main_vsi;
10354 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10355 uint16_t bsf, tc_mapping;
10358 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10359 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10361 dcb_info->nb_tcs = 1;
10362 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10363 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10364 for (i = 0; i < dcb_info->nb_tcs; i++)
10365 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10367 /* get queue mapping if vmdq is disabled */
10368 if (!pf->nb_cfg_vmdq_vsi) {
10369 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10370 if (!(vsi->enabled_tc & (1 << i)))
10372 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10373 dcb_info->tc_queue.tc_rxq[j][i].base =
10374 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10375 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10376 dcb_info->tc_queue.tc_txq[j][i].base =
10377 dcb_info->tc_queue.tc_rxq[j][i].base;
10378 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10379 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10380 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10381 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10382 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10387 /* get queue mapping if vmdq is enabled */
10389 vsi = pf->vmdq[j].vsi;
10390 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10391 if (!(vsi->enabled_tc & (1 << i)))
10393 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10394 dcb_info->tc_queue.tc_rxq[j][i].base =
10395 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10396 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10397 dcb_info->tc_queue.tc_txq[j][i].base =
10398 dcb_info->tc_queue.tc_rxq[j][i].base;
10399 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10400 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10401 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10402 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10403 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10406 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10411 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10413 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10414 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10416 uint16_t interval =
10417 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10418 uint16_t msix_intr;
10420 msix_intr = intr_handle->intr_vec[queue_id];
10421 if (msix_intr == I40E_MISC_VEC_ID)
10422 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10423 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10424 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10425 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10427 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10430 I40E_PFINT_DYN_CTLN(msix_intr -
10431 I40E_RX_VEC_START),
10432 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10433 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10434 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10436 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10438 I40E_WRITE_FLUSH(hw);
10439 rte_intr_enable(&pci_dev->intr_handle);
10445 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10447 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10448 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10449 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10450 uint16_t msix_intr;
10452 msix_intr = intr_handle->intr_vec[queue_id];
10453 if (msix_intr == I40E_MISC_VEC_ID)
10454 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10457 I40E_PFINT_DYN_CTLN(msix_intr -
10458 I40E_RX_VEC_START),
10460 I40E_WRITE_FLUSH(hw);
10465 static int i40e_get_regs(struct rte_eth_dev *dev,
10466 struct rte_dev_reg_info *regs)
10468 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10469 uint32_t *ptr_data = regs->data;
10470 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10471 const struct i40e_reg_info *reg_info;
10473 if (ptr_data == NULL) {
10474 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10475 regs->width = sizeof(uint32_t);
10479 /* The first few registers have to be read using AQ operations */
10481 while (i40e_regs_adminq[reg_idx].name) {
10482 reg_info = &i40e_regs_adminq[reg_idx++];
10483 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10485 arr_idx2 <= reg_info->count2;
10487 reg_offset = arr_idx * reg_info->stride1 +
10488 arr_idx2 * reg_info->stride2;
10489 reg_offset += reg_info->base_addr;
10490 ptr_data[reg_offset >> 2] =
10491 i40e_read_rx_ctl(hw, reg_offset);
10495 /* The remaining registers can be read using primitives */
10497 while (i40e_regs_others[reg_idx].name) {
10498 reg_info = &i40e_regs_others[reg_idx++];
10499 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10501 arr_idx2 <= reg_info->count2;
10503 reg_offset = arr_idx * reg_info->stride1 +
10504 arr_idx2 * reg_info->stride2;
10505 reg_offset += reg_info->base_addr;
10506 ptr_data[reg_offset >> 2] =
10507 I40E_READ_REG(hw, reg_offset);
10514 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10516 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10518 /* Convert word count to byte count */
10519 return hw->nvm.sr_size << 1;
10522 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10523 struct rte_dev_eeprom_info *eeprom)
10525 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10526 uint16_t *data = eeprom->data;
10527 uint16_t offset, length, cnt_words;
10530 offset = eeprom->offset >> 1;
10531 length = eeprom->length >> 1;
10532 cnt_words = length;
10534 if (offset > hw->nvm.sr_size ||
10535 offset + length > hw->nvm.sr_size) {
10536 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10540 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10542 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10543 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10544 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10551 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10552 struct ether_addr *mac_addr)
10554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10556 if (!is_valid_assigned_ether_addr(mac_addr)) {
10557 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10561 /* Flags: 0x3 updates port address */
10562 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10566 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10568 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10569 struct rte_eth_dev_data *dev_data = pf->dev_data;
10570 uint32_t frame_size = mtu + ETHER_HDR_LEN
10571 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10574 /* check if mtu is within the allowed range */
10575 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10578 /* mtu setting is forbidden if port is start */
10579 if (dev_data->dev_started) {
10580 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10581 dev_data->port_id);
10585 if (frame_size > ETHER_MAX_LEN)
10586 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10588 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10590 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10595 /* Restore ethertype filter */
10597 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10599 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10600 struct i40e_ethertype_filter_list
10601 *ethertype_list = &pf->ethertype.ethertype_list;
10602 struct i40e_ethertype_filter *f;
10603 struct i40e_control_filter_stats stats;
10606 TAILQ_FOREACH(f, ethertype_list, rules) {
10608 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10609 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10610 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10611 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10612 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10614 memset(&stats, 0, sizeof(stats));
10615 i40e_aq_add_rem_control_packet_filter(hw,
10616 f->input.mac_addr.addr_bytes,
10617 f->input.ether_type,
10618 flags, pf->main_vsi->seid,
10619 f->queue, 1, &stats, NULL);
10621 PMD_DRV_LOG(INFO, "Ethertype filter:"
10622 " mac_etype_used = %u, etype_used = %u,"
10623 " mac_etype_free = %u, etype_free = %u",
10624 stats.mac_etype_used, stats.etype_used,
10625 stats.mac_etype_free, stats.etype_free);
10628 /* Restore tunnel filter */
10630 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10632 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10633 struct i40e_vsi *vsi = pf->main_vsi;
10634 struct i40e_tunnel_filter_list
10635 *tunnel_list = &pf->tunnel.tunnel_list;
10636 struct i40e_tunnel_filter *f;
10637 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10638 bool big_buffer = 0;
10640 TAILQ_FOREACH(f, tunnel_list, rules) {
10641 memset(&cld_filter, 0, sizeof(cld_filter));
10642 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10643 (struct ether_addr *)&cld_filter.element.outer_mac);
10644 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10645 (struct ether_addr *)&cld_filter.element.inner_mac);
10646 cld_filter.element.inner_vlan = f->input.inner_vlan;
10647 cld_filter.element.flags = f->input.flags;
10648 cld_filter.element.tenant_id = f->input.tenant_id;
10649 cld_filter.element.queue_number = f->queue;
10650 rte_memcpy(cld_filter.general_fields,
10651 f->input.general_fields,
10652 sizeof(f->input.general_fields));
10654 if (((f->input.flags &
10655 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10656 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10658 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10659 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE))
10663 i40e_aq_add_cloud_filters_big_buffer(hw,
10664 vsi->seid, &cld_filter, 1);
10666 i40e_aq_add_cloud_filters(hw, vsi->seid,
10667 &cld_filter.element, 1);
10672 i40e_filter_restore(struct i40e_pf *pf)
10674 i40e_ethertype_filter_restore(pf);
10675 i40e_tunnel_filter_restore(pf);
10676 i40e_fdir_filter_restore(pf);
10680 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10682 if (strcmp(dev->driver->pci_drv.driver.name,
10683 drv->pci_drv.driver.name))
10690 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10692 struct rte_eth_dev *dev;
10693 struct i40e_pf *pf;
10695 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10697 dev = &rte_eth_devices[port];
10699 if (!is_device_supported(dev, &rte_i40e_pmd))
10702 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10704 if (vf >= pf->vf_num || !pf->vfs) {
10705 PMD_DRV_LOG(ERR, "Invalid argument.");
10709 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10715 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10717 struct rte_eth_dev *dev;
10718 struct i40e_pf *pf;
10719 struct i40e_vsi *vsi;
10720 struct i40e_hw *hw;
10721 struct i40e_vsi_context ctxt;
10724 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10726 dev = &rte_eth_devices[port];
10728 if (!is_device_supported(dev, &rte_i40e_pmd))
10731 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10733 if (vf_id >= pf->vf_num || !pf->vfs) {
10734 PMD_DRV_LOG(ERR, "Invalid argument.");
10738 vsi = pf->vfs[vf_id].vsi;
10740 PMD_DRV_LOG(ERR, "Invalid VSI.");
10744 /* Check if it has been already on or off */
10745 if (vsi->info.valid_sections &
10746 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10748 if ((vsi->info.sec_flags &
10749 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10750 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10751 return 0; /* already on */
10753 if ((vsi->info.sec_flags &
10754 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10755 return 0; /* already off */
10759 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10761 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10763 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10765 memset(&ctxt, 0, sizeof(ctxt));
10766 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10767 ctxt.seid = vsi->seid;
10769 hw = I40E_VSI_TO_HW(vsi);
10770 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10771 if (ret != I40E_SUCCESS) {
10773 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10780 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10784 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10785 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10788 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10792 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10793 if (!(vsi->vfta[j] & (1 << k)))
10796 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10800 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10802 ret = i40e_aq_add_vlan(hw, vsi->seid,
10803 &vlan_data, 1, NULL);
10805 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10806 &vlan_data, 1, NULL);
10807 if (ret != I40E_SUCCESS) {
10809 "Failed to add/rm vlan filter");
10815 return I40E_SUCCESS;
10819 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10821 struct rte_eth_dev *dev;
10822 struct i40e_pf *pf;
10823 struct i40e_vsi *vsi;
10824 struct i40e_hw *hw;
10825 struct i40e_vsi_context ctxt;
10828 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10830 dev = &rte_eth_devices[port];
10832 if (!is_device_supported(dev, &rte_i40e_pmd))
10835 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10837 if (vf_id >= pf->vf_num || !pf->vfs) {
10838 PMD_DRV_LOG(ERR, "Invalid argument.");
10842 vsi = pf->vfs[vf_id].vsi;
10844 PMD_DRV_LOG(ERR, "Invalid VSI.");
10848 /* Check if it has been already on or off */
10849 if (vsi->vlan_anti_spoof_on == on)
10850 return 0; /* already on or off */
10852 vsi->vlan_anti_spoof_on = on;
10853 if (!vsi->vlan_filter_on) {
10854 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10856 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10861 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10863 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10865 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10867 memset(&ctxt, 0, sizeof(ctxt));
10868 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10869 ctxt.seid = vsi->seid;
10871 hw = I40E_VSI_TO_HW(vsi);
10872 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10873 if (ret != I40E_SUCCESS) {
10875 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10882 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10884 struct i40e_mac_filter *f;
10885 struct i40e_macvlan_filter *mv_f;
10887 enum rte_mac_filter_type filter_type;
10888 int ret = I40E_SUCCESS;
10891 /* remove all the MACs */
10892 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10893 vlan_num = vsi->vlan_num;
10894 filter_type = f->mac_info.filter_type;
10895 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10896 filter_type == RTE_MACVLAN_HASH_MATCH) {
10897 if (vlan_num == 0) {
10898 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10899 return I40E_ERR_PARAM;
10901 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10902 filter_type == RTE_MAC_HASH_MATCH)
10905 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10907 PMD_DRV_LOG(ERR, "failed to allocate memory");
10908 return I40E_ERR_NO_MEMORY;
10911 for (i = 0; i < vlan_num; i++) {
10912 mv_f[i].filter_type = filter_type;
10913 (void)rte_memcpy(&mv_f[i].macaddr,
10914 &f->mac_info.mac_addr,
10917 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10918 filter_type == RTE_MACVLAN_HASH_MATCH) {
10919 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10920 &f->mac_info.mac_addr);
10921 if (ret != I40E_SUCCESS) {
10927 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10928 if (ret != I40E_SUCCESS) {
10934 ret = I40E_SUCCESS;
10941 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10943 struct i40e_mac_filter *f;
10944 struct i40e_macvlan_filter *mv_f;
10945 int i, vlan_num = 0;
10946 int ret = I40E_SUCCESS;
10949 /* restore all the MACs */
10950 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10951 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10952 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10954 * If vlan_num is 0, that's the first time to add mac,
10955 * set mask for vlan_id 0.
10957 if (vsi->vlan_num == 0) {
10958 i40e_set_vlan_filter(vsi, 0, 1);
10961 vlan_num = vsi->vlan_num;
10962 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10963 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10966 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10968 PMD_DRV_LOG(ERR, "failed to allocate memory");
10969 return I40E_ERR_NO_MEMORY;
10972 for (i = 0; i < vlan_num; i++) {
10973 mv_f[i].filter_type = f->mac_info.filter_type;
10974 (void)rte_memcpy(&mv_f[i].macaddr,
10975 &f->mac_info.mac_addr,
10979 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10980 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10981 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10982 &f->mac_info.mac_addr);
10983 if (ret != I40E_SUCCESS) {
10989 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10990 if (ret != I40E_SUCCESS) {
10996 ret = I40E_SUCCESS;
11003 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
11005 struct i40e_vsi_context ctxt;
11006 struct i40e_hw *hw;
11012 hw = I40E_VSI_TO_HW(vsi);
11014 /* Use the FW API if FW >= v5.0 */
11015 if (hw->aq.fw_maj_ver < 5) {
11016 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
11020 /* Check if it has been already on or off */
11021 if (vsi->info.valid_sections &
11022 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11024 if ((vsi->info.switch_id &
11025 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11026 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11027 return 0; /* already on */
11029 if ((vsi->info.switch_id &
11030 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11031 return 0; /* already off */
11035 /* remove all the MAC and VLAN first */
11036 ret = i40e_vsi_rm_mac_filter(vsi);
11038 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11041 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11042 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11044 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11049 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11051 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11053 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11055 memset(&ctxt, 0, sizeof(ctxt));
11056 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11057 ctxt.seid = vsi->seid;
11059 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11060 if (ret != I40E_SUCCESS) {
11061 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11065 /* add all the MAC and VLAN back */
11066 ret = i40e_vsi_restore_mac_filter(vsi);
11069 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11070 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11079 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11081 struct rte_eth_dev *dev;
11082 struct i40e_pf *pf;
11083 struct i40e_pf_vf *vf;
11084 struct i40e_vsi *vsi;
11088 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11090 dev = &rte_eth_devices[port];
11092 if (!is_device_supported(dev, &rte_i40e_pmd))
11095 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11097 /* setup PF TX loopback */
11098 vsi = pf->main_vsi;
11099 ret = i40e_vsi_set_tx_loopback(vsi, on);
11103 /* setup TX loopback for all the VFs */
11105 /* if no VF, do nothing. */
11109 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11110 vf = &pf->vfs[vf_id];
11113 ret = i40e_vsi_set_tx_loopback(vsi, on);
11122 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11124 struct rte_eth_dev *dev;
11125 struct i40e_pf *pf;
11126 struct i40e_vsi *vsi;
11127 struct i40e_hw *hw;
11130 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11132 dev = &rte_eth_devices[port];
11134 if (!is_device_supported(dev, &rte_i40e_pmd))
11137 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11139 if (vf_id >= pf->vf_num || !pf->vfs) {
11140 PMD_DRV_LOG(ERR, "Invalid argument.");
11144 vsi = pf->vfs[vf_id].vsi;
11146 PMD_DRV_LOG(ERR, "Invalid VSI.");
11150 hw = I40E_VSI_TO_HW(vsi);
11152 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11154 if (ret != I40E_SUCCESS) {
11156 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11163 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11165 struct rte_eth_dev *dev;
11166 struct i40e_pf *pf;
11167 struct i40e_vsi *vsi;
11168 struct i40e_hw *hw;
11171 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11173 dev = &rte_eth_devices[port];
11175 if (!is_device_supported(dev, &rte_i40e_pmd))
11178 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11180 if (vf_id >= pf->vf_num || !pf->vfs) {
11181 PMD_DRV_LOG(ERR, "Invalid argument.");
11185 vsi = pf->vfs[vf_id].vsi;
11187 PMD_DRV_LOG(ERR, "Invalid VSI.");
11191 hw = I40E_VSI_TO_HW(vsi);
11193 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11195 if (ret != I40E_SUCCESS) {
11197 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11204 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11205 struct ether_addr *mac_addr)
11207 struct i40e_mac_filter *f;
11208 struct rte_eth_dev *dev;
11209 struct i40e_pf_vf *vf;
11210 struct i40e_vsi *vsi;
11211 struct i40e_pf *pf;
11214 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11217 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11219 dev = &rte_eth_devices[port];
11221 if (!is_device_supported(dev, &rte_i40e_pmd))
11224 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11226 if (vf_id >= pf->vf_num || !pf->vfs)
11229 vf = &pf->vfs[vf_id];
11232 PMD_DRV_LOG(ERR, "Invalid VSI.");
11236 ether_addr_copy(mac_addr, &vf->mac_addr);
11238 /* Remove all existing mac */
11239 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11240 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11245 /* Set vlan strip on/off for specific VF from host */
11247 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11249 struct rte_eth_dev *dev;
11250 struct i40e_pf *pf;
11251 struct i40e_vsi *vsi;
11254 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11256 dev = &rte_eth_devices[port];
11258 if (!is_device_supported(dev, &rte_i40e_pmd))
11261 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11263 if (vf_id >= pf->vf_num || !pf->vfs) {
11264 PMD_DRV_LOG(ERR, "Invalid argument.");
11268 vsi = pf->vfs[vf_id].vsi;
11273 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11274 if (ret != I40E_SUCCESS) {
11276 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11282 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11285 struct rte_eth_dev *dev;
11286 struct i40e_pf *pf;
11287 struct i40e_hw *hw;
11288 struct i40e_vsi *vsi;
11289 struct i40e_vsi_context ctxt;
11292 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11294 if (vlan_id > ETHER_MAX_VLAN_ID) {
11295 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11299 dev = &rte_eth_devices[port];
11301 if (!is_device_supported(dev, &rte_i40e_pmd))
11304 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11305 hw = I40E_PF_TO_HW(pf);
11308 * return -ENODEV if SRIOV not enabled, VF number not configured
11309 * or no queue assigned.
11311 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11312 pf->vf_nb_qps == 0)
11315 if (vf_id >= pf->vf_num || !pf->vfs) {
11316 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11320 vsi = pf->vfs[vf_id].vsi;
11322 PMD_DRV_LOG(ERR, "Invalid VSI.");
11326 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11327 vsi->info.pvid = vlan_id;
11329 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11331 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11333 memset(&ctxt, 0, sizeof(ctxt));
11334 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11335 ctxt.seid = vsi->seid;
11337 hw = I40E_VSI_TO_HW(vsi);
11338 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11339 if (ret != I40E_SUCCESS) {
11341 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11347 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11350 struct rte_eth_dev *dev;
11351 struct i40e_pf *pf;
11352 struct i40e_vsi *vsi;
11353 struct i40e_hw *hw;
11354 struct i40e_mac_filter_info filter;
11355 struct ether_addr broadcast = {
11356 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11359 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11362 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11366 dev = &rte_eth_devices[port];
11368 if (!is_device_supported(dev, &rte_i40e_pmd))
11371 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11372 hw = I40E_PF_TO_HW(pf);
11374 if (vf_id >= pf->vf_num || !pf->vfs) {
11375 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11380 * return -ENODEV if SRIOV not enabled, VF number not configured
11381 * or no queue assigned.
11383 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11384 pf->vf_nb_qps == 0) {
11385 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11389 vsi = pf->vfs[vf_id].vsi;
11391 PMD_DRV_LOG(ERR, "Invalid VSI.");
11396 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11397 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11398 ret = i40e_vsi_add_mac(vsi, &filter);
11400 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11403 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11405 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11413 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11415 struct rte_eth_dev *dev;
11416 struct i40e_pf *pf;
11417 struct i40e_hw *hw;
11418 struct i40e_vsi *vsi;
11419 struct i40e_vsi_context ctxt;
11422 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11425 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11429 dev = &rte_eth_devices[port];
11431 if (!is_device_supported(dev, &rte_i40e_pmd))
11434 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11435 hw = I40E_PF_TO_HW(pf);
11438 * return -ENODEV if SRIOV not enabled, VF number not configured
11439 * or no queue assigned.
11441 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11442 pf->vf_nb_qps == 0) {
11443 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11447 if (vf_id >= pf->vf_num || !pf->vfs) {
11448 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11452 vsi = pf->vfs[vf_id].vsi;
11454 PMD_DRV_LOG(ERR, "Invalid VSI.");
11458 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11460 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11461 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11463 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11464 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11467 memset(&ctxt, 0, sizeof(ctxt));
11468 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11469 ctxt.seid = vsi->seid;
11471 hw = I40E_VSI_TO_HW(vsi);
11472 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11473 if (ret != I40E_SUCCESS) {
11475 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11481 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11482 uint64_t vf_mask, uint8_t on)
11484 struct rte_eth_dev *dev;
11485 struct i40e_pf *pf;
11486 struct i40e_hw *hw;
11487 struct i40e_vsi *vsi;
11489 int ret = I40E_SUCCESS;
11491 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11493 dev = &rte_eth_devices[port];
11495 if (!is_device_supported(dev, &rte_i40e_pmd))
11498 if (vlan_id > ETHER_MAX_VLAN_ID) {
11499 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11503 if (vf_mask == 0) {
11504 PMD_DRV_LOG(ERR, "No VF.");
11509 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11513 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11514 hw = I40E_PF_TO_HW(pf);
11517 * return -ENODEV if SRIOV not enabled, VF number not configured
11518 * or no queue assigned.
11520 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11521 pf->vf_nb_qps == 0) {
11522 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11526 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11527 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11528 vsi = pf->vfs[vf_idx].vsi;
11530 if (!vsi->vlan_filter_on) {
11531 vsi->vlan_filter_on = true;
11532 if (!vsi->vlan_anti_spoof_on)
11533 i40e_add_rm_all_vlan_filter(
11536 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
11538 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11540 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11545 if (ret != I40E_SUCCESS) {
11547 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11554 rte_pmd_i40e_get_vf_stats(uint8_t port,
11556 struct rte_eth_stats *stats)
11558 struct rte_eth_dev *dev;
11559 struct i40e_pf *pf;
11560 struct i40e_vsi *vsi;
11562 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11564 dev = &rte_eth_devices[port];
11566 if (!is_device_supported(dev, &rte_i40e_pmd))
11569 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11571 if (vf_id >= pf->vf_num || !pf->vfs) {
11572 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11576 vsi = pf->vfs[vf_id].vsi;
11578 PMD_DRV_LOG(ERR, "Invalid VSI.");
11582 i40e_update_vsi_stats(vsi);
11584 stats->ipackets = vsi->eth_stats.rx_unicast +
11585 vsi->eth_stats.rx_multicast +
11586 vsi->eth_stats.rx_broadcast;
11587 stats->opackets = vsi->eth_stats.tx_unicast +
11588 vsi->eth_stats.tx_multicast +
11589 vsi->eth_stats.tx_broadcast;
11590 stats->ibytes = vsi->eth_stats.rx_bytes;
11591 stats->obytes = vsi->eth_stats.tx_bytes;
11592 stats->ierrors = vsi->eth_stats.rx_discards;
11593 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11599 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11602 struct rte_eth_dev *dev;
11603 struct i40e_pf *pf;
11604 struct i40e_vsi *vsi;
11606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11608 dev = &rte_eth_devices[port];
11610 if (!is_device_supported(dev, &rte_i40e_pmd))
11613 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11615 if (vf_id >= pf->vf_num || !pf->vfs) {
11616 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11620 vsi = pf->vfs[vf_id].vsi;
11622 PMD_DRV_LOG(ERR, "Invalid VSI.");
11626 vsi->offset_loaded = false;
11627 i40e_update_vsi_stats(vsi);
11633 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11635 struct rte_eth_dev *dev;
11636 struct i40e_pf *pf;
11637 struct i40e_vsi *vsi;
11638 struct i40e_hw *hw;
11642 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11644 dev = &rte_eth_devices[port];
11646 if (!is_device_supported(dev, &rte_i40e_pmd))
11649 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11651 if (vf_id >= pf->vf_num || !pf->vfs) {
11652 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11656 vsi = pf->vfs[vf_id].vsi;
11658 PMD_DRV_LOG(ERR, "Invalid VSI.");
11662 if (bw > I40E_QOS_BW_MAX) {
11663 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11668 if (bw % I40E_QOS_BW_GRANULARITY) {
11669 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11670 I40E_QOS_BW_GRANULARITY);
11674 bw /= I40E_QOS_BW_GRANULARITY;
11676 hw = I40E_VSI_TO_HW(vsi);
11679 if (bw == vsi->bw_info.bw_limit) {
11681 "No change for VF max bandwidth. Nothing to do.");
11686 * VF bandwidth limitation and TC bandwidth limitation cannot be
11687 * enabled in parallel, quit if TC bandwidth limitation is enabled.
11689 * If bw is 0, means disable bandwidth limitation. Then no need to
11690 * check TC bandwidth limitation.
11693 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11694 if ((vsi->enabled_tc & BIT_ULL(i)) &&
11695 vsi->bw_info.bw_ets_credits[i])
11698 if (i != I40E_MAX_TRAFFIC_CLASS) {
11700 "TC max bandwidth has been set on this VF,"
11701 " please disable it first.");
11706 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11709 "Failed to set VF %d bandwidth, err(%d).",
11714 /* Store the configuration. */
11715 vsi->bw_info.bw_limit = (uint16_t)bw;
11716 vsi->bw_info.bw_max = 0;
11722 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11723 uint8_t tc_num, uint8_t *bw_weight)
11725 struct rte_eth_dev *dev;
11726 struct i40e_pf *pf;
11727 struct i40e_vsi *vsi;
11728 struct i40e_hw *hw;
11729 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11733 bool b_change = false;
11735 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11737 dev = &rte_eth_devices[port];
11739 if (!is_device_supported(dev, &rte_i40e_pmd))
11742 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11744 if (vf_id >= pf->vf_num || !pf->vfs) {
11745 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11749 vsi = pf->vfs[vf_id].vsi;
11751 PMD_DRV_LOG(ERR, "Invalid VSI.");
11755 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11756 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11757 I40E_MAX_TRAFFIC_CLASS);
11762 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11763 if (vsi->enabled_tc & BIT_ULL(i))
11766 if (sum != tc_num) {
11768 "Weight should be set for all %d enabled TCs.",
11774 for (i = 0; i < tc_num; i++) {
11775 if (!bw_weight[i]) {
11777 "The weight should be 1 at least.");
11780 sum += bw_weight[i];
11784 "The summary of the TC weight should be 100.");
11789 * Create the configuration for all the TCs.
11791 memset(&tc_bw, 0, sizeof(tc_bw));
11792 tc_bw.tc_valid_bits = vsi->enabled_tc;
11794 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11795 if (vsi->enabled_tc & BIT_ULL(i)) {
11796 if (bw_weight[j] !=
11797 vsi->bw_info.bw_ets_share_credits[i])
11800 tc_bw.tc_bw_credits[i] = bw_weight[j];
11808 "No change for TC allocated bandwidth."
11809 " Nothing to do.");
11813 hw = I40E_VSI_TO_HW(vsi);
11815 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11818 "Failed to set VF %d TC bandwidth weight, err(%d).",
11823 /* Store the configuration. */
11825 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11826 if (vsi->enabled_tc & BIT_ULL(i)) {
11827 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11836 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11837 uint8_t tc_no, uint32_t bw)
11839 struct rte_eth_dev *dev;
11840 struct i40e_pf *pf;
11841 struct i40e_vsi *vsi;
11842 struct i40e_hw *hw;
11843 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11847 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11849 dev = &rte_eth_devices[port];
11851 if (!is_device_supported(dev, &rte_i40e_pmd))
11854 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11856 if (vf_id >= pf->vf_num || !pf->vfs) {
11857 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11861 vsi = pf->vfs[vf_id].vsi;
11863 PMD_DRV_LOG(ERR, "Invalid VSI.");
11867 if (bw > I40E_QOS_BW_MAX) {
11868 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11873 if (bw % I40E_QOS_BW_GRANULARITY) {
11874 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11875 I40E_QOS_BW_GRANULARITY);
11879 bw /= I40E_QOS_BW_GRANULARITY;
11881 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11882 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11883 I40E_MAX_TRAFFIC_CLASS);
11887 hw = I40E_VSI_TO_HW(vsi);
11889 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11890 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11896 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11898 "No change for TC max bandwidth. Nothing to do.");
11903 * VF bandwidth limitation and TC bandwidth limitation cannot be
11904 * enabled in parallel, disable VF bandwidth limitation if it's
11906 * If bw is 0, means disable bandwidth limitation. Then no need to
11907 * care about VF bandwidth limitation configuration.
11909 if (bw && vsi->bw_info.bw_limit) {
11910 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11913 "Failed to disable VF(%d)"
11914 " bandwidth limitation, err(%d).",
11920 "VF max bandwidth is disabled according"
11921 " to TC max bandwidth setting.");
11925 * Get all the TCs' info to create a whole picture.
11926 * Because the incremental change isn't permitted.
11928 memset(&tc_bw, 0, sizeof(tc_bw));
11929 tc_bw.tc_valid_bits = vsi->enabled_tc;
11930 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11931 if (vsi->enabled_tc & BIT_ULL(i)) {
11932 tc_bw.tc_bw_credits[i] =
11934 vsi->bw_info.bw_ets_credits[i]);
11937 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11939 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11942 "Failed to set VF %d TC %d max bandwidth, err(%d).",
11943 vf_id, tc_no, ret);
11947 /* Store the configuration. */
11948 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
11954 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
11956 struct rte_eth_dev *dev;
11957 struct i40e_pf *pf;
11958 struct i40e_vsi *vsi;
11959 struct i40e_veb *veb;
11960 struct i40e_hw *hw;
11961 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
11965 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11967 dev = &rte_eth_devices[port];
11969 if (!is_device_supported(dev, &rte_i40e_pmd))
11972 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11974 vsi = pf->main_vsi;
11976 PMD_DRV_LOG(ERR, "Invalid VSI.");
11982 PMD_DRV_LOG(ERR, "Invalid VEB.");
11986 if ((tc_map & veb->enabled_tc) != tc_map) {
11988 "TC bitmap isn't the subset of enabled TCs 0x%x.",
11993 if (tc_map == veb->strict_prio_tc) {
11994 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
11998 hw = I40E_VSI_TO_HW(vsi);
12000 /* Disable DCBx if it's the first time to set strict priority. */
12001 if (!veb->strict_prio_tc) {
12002 ret = i40e_aq_stop_lldp(hw, true, NULL);
12005 "Failed to disable DCBx as it's already"
12009 "DCBx is disabled according to strict"
12010 " priority setting.");
12013 memset(&ets_data, 0, sizeof(ets_data));
12014 ets_data.tc_valid_bits = veb->enabled_tc;
12015 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
12016 ets_data.tc_strict_priority_flags = tc_map;
12017 /* Get all TCs' bandwidth. */
12018 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12019 if (veb->enabled_tc & BIT_ULL(i)) {
12020 /* For rubust, if bandwidth is 0, use 1 instead. */
12021 if (veb->bw_info.bw_ets_share_credits[i])
12022 ets_data.tc_bw_share_credits[i] =
12023 veb->bw_info.bw_ets_share_credits[i];
12025 ets_data.tc_bw_share_credits[i] =
12026 I40E_QOS_BW_WEIGHT_MIN;
12030 if (!veb->strict_prio_tc)
12031 ret = i40e_aq_config_switch_comp_ets(
12032 hw, veb->uplink_seid,
12033 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12036 ret = i40e_aq_config_switch_comp_ets(
12037 hw, veb->uplink_seid,
12038 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12041 ret = i40e_aq_config_switch_comp_ets(
12042 hw, veb->uplink_seid,
12043 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12048 "Failed to set TCs' strict priority mode."
12053 veb->strict_prio_tc = tc_map;
12055 /* Enable DCBx again, if all the TCs' strict priority disabled. */
12057 ret = i40e_aq_start_lldp(hw, NULL);
12060 "Failed to enable DCBx, err(%d).", ret);
12065 "DCBx is enabled again according to strict"
12066 " priority setting.");
12072 #define I40E_PROFILE_INFO_SIZE 48
12073 #define I40E_MAX_PROFILE_NUM 16
12076 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12077 uint32_t track_id, uint8_t *profile_info_sec,
12080 struct i40e_profile_section_header *sec = NULL;
12081 struct i40e_profile_info *pinfo;
12083 sec = (struct i40e_profile_section_header *)profile_info_sec;
12085 sec->data_end = sizeof(struct i40e_profile_section_header) +
12086 sizeof(struct i40e_profile_info);
12087 sec->section.type = SECTION_TYPE_INFO;
12088 sec->section.offset = sizeof(struct i40e_profile_section_header);
12089 sec->section.size = sizeof(struct i40e_profile_info);
12090 pinfo = (struct i40e_profile_info *)(profile_info_sec +
12091 sec->section.offset);
12092 pinfo->track_id = track_id;
12093 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12094 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12096 pinfo->op = I40E_DDP_ADD_TRACKID;
12098 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12101 static enum i40e_status_code
12102 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12104 enum i40e_status_code status = I40E_SUCCESS;
12105 struct i40e_profile_section_header *sec;
12107 uint32_t offset = 0;
12110 sec = (struct i40e_profile_section_header *)profile_info_sec;
12111 track_id = ((struct i40e_profile_info *)(profile_info_sec +
12112 sec->section.offset))->track_id;
12114 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12115 track_id, &offset, &info, NULL);
12117 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12118 "offset %d, info %d",
12124 #define I40E_PROFILE_INFO_SIZE 48
12125 #define I40E_MAX_PROFILE_NUM 16
12127 /* Check if the profile info exists */
12129 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12131 struct rte_eth_dev *dev = &rte_eth_devices[port];
12132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12134 struct rte_pmd_i40e_profile_list *p_list;
12135 struct rte_pmd_i40e_profile_info *pinfo, *p;
12139 buff = rte_zmalloc("pinfo_list",
12140 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12143 PMD_DRV_LOG(ERR, "failed to allocate memory");
12147 ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12148 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12151 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12155 p_list = (struct rte_pmd_i40e_profile_list *)buff;
12156 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12157 sizeof(struct i40e_profile_section_header));
12158 for (i = 0; i < p_list->p_count; i++) {
12159 p = &p_list->p_info[i];
12160 if ((pinfo->track_id == p->track_id) &&
12161 !memcmp(&pinfo->version, &p->version,
12162 sizeof(struct i40e_ddp_version)) &&
12163 !memcmp(&pinfo->name, &p->name,
12164 I40E_DDP_NAME_SIZE)) {
12165 PMD_DRV_LOG(INFO, "Profile exists.");
12176 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12178 enum rte_pmd_i40e_package_op op)
12180 struct rte_eth_dev *dev;
12181 struct i40e_hw *hw;
12182 struct i40e_package_header *pkg_hdr;
12183 struct i40e_generic_seg_header *profile_seg_hdr;
12184 struct i40e_generic_seg_header *metadata_seg_hdr;
12186 uint8_t *profile_info_sec;
12188 enum i40e_status_code status = I40E_SUCCESS;
12190 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12192 dev = &rte_eth_devices[port];
12194 if (!is_device_supported(dev, &rte_i40e_pmd))
12197 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12199 if (size < (sizeof(struct i40e_package_header) +
12200 sizeof(struct i40e_metadata_segment) +
12201 sizeof(uint32_t) * 2)) {
12202 PMD_DRV_LOG(ERR, "Buff is invalid.");
12206 pkg_hdr = (struct i40e_package_header *)buff;
12209 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12213 if (pkg_hdr->segment_count < 2) {
12214 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12218 /* Find metadata segment */
12219 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12221 if (!metadata_seg_hdr) {
12222 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12225 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12227 /* Find profile segment */
12228 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12230 if (!profile_seg_hdr) {
12231 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12235 profile_info_sec = rte_zmalloc("i40e_profile_info",
12236 sizeof(struct i40e_profile_section_header) +
12237 sizeof(struct i40e_profile_info),
12239 if (!profile_info_sec) {
12240 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12244 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12245 /* Check if the profile exists */
12246 i40e_generate_profile_info_sec(
12247 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12248 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12249 track_id, profile_info_sec, 1);
12250 is_exist = i40e_check_profile_info(port, profile_info_sec);
12251 if (is_exist > 0) {
12252 PMD_DRV_LOG(ERR, "Profile already exists.");
12253 rte_free(profile_info_sec);
12255 } else if (is_exist < 0) {
12256 PMD_DRV_LOG(ERR, "Failed to check profile.");
12257 rte_free(profile_info_sec);
12261 /* Write profile to HW */
12262 status = i40e_write_profile(hw,
12263 (struct i40e_profile_segment *)profile_seg_hdr,
12266 PMD_DRV_LOG(ERR, "Failed to write profile.");
12267 rte_free(profile_info_sec);
12271 /* Add profile info to info list */
12272 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12274 PMD_DRV_LOG(ERR, "Failed to add profile info.");
12276 PMD_DRV_LOG(ERR, "Operation not supported.");
12278 rte_free(profile_info_sec);
12283 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12285 struct rte_eth_dev *dev;
12286 struct i40e_hw *hw;
12287 enum i40e_status_code status = I40E_SUCCESS;
12289 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12291 dev = &rte_eth_devices[port];
12293 if (!is_device_supported(dev, &rte_i40e_pmd))
12296 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12299 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12301 status = i40e_aq_get_ddp_list(hw, (void *)buff,
12307 /* Create a QinQ cloud filter
12309 * The Fortville NIC has limited resources for tunnel filters,
12310 * so we can only reuse existing filters.
12312 * In step 1 we define which Field Vector fields can be used for
12314 * As we do not have the inner tag defined as a field,
12315 * we have to define it first, by reusing one of L1 entries.
12317 * In step 2 we are replacing one of existing filter types with
12318 * a new one for QinQ.
12319 * As we reusing L1 and replacing L2, some of the default filter
12320 * types will disappear,which depends on L1 and L2 entries we reuse.
12322 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12324 * 1. Create L1 filter of outer vlan (12b) which will be in use
12325 * later when we define the cloud filter.
12326 * a. Valid_flags.replace_cloud = 0
12327 * b. Old_filter = 10 (Stag_Inner_Vlan)
12328 * c. New_filter = 0x10
12329 * d. TR bit = 0xff (optional, not used here)
12330 * e. Buffer – 2 entries:
12331 * i. Byte 0 = 8 (outer vlan FV index).
12333 * Byte 2-3 = 0x0fff
12334 * ii. Byte 0 = 37 (inner vlan FV index).
12336 * Byte 2-3 = 0x0fff
12339 * 2. Create cloud filter using two L1 filters entries: stag and
12340 * new filter(outer vlan+ inner vlan)
12341 * a. Valid_flags.replace_cloud = 1
12342 * b. Old_filter = 1 (instead of outer IP)
12343 * c. New_filter = 0x10
12344 * d. Buffer – 2 entries:
12345 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12346 * Byte 1-3 = 0 (rsv)
12347 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12348 * Byte 9-11 = 0 (rsv)
12351 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12353 int ret = -ENOTSUP;
12354 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12355 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12356 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12359 memset(&filter_replace, 0,
12360 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12361 memset(&filter_replace_buf, 0,
12362 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12364 /* create L1 filter */
12365 filter_replace.old_filter_type =
12366 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12367 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12368 filter_replace.tr_bit = 0;
12370 /* Prepare the buffer, 2 entries */
12371 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12372 filter_replace_buf.data[0] |=
12373 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12374 /* Field Vector 12b mask */
12375 filter_replace_buf.data[2] = 0xff;
12376 filter_replace_buf.data[3] = 0x0f;
12377 filter_replace_buf.data[4] =
12378 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12379 filter_replace_buf.data[4] |=
12380 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12381 /* Field Vector 12b mask */
12382 filter_replace_buf.data[6] = 0xff;
12383 filter_replace_buf.data[7] = 0x0f;
12384 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12385 &filter_replace_buf);
12386 if (ret != I40E_SUCCESS)
12389 /* Apply the second L2 cloud filter */
12390 memset(&filter_replace, 0,
12391 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12392 memset(&filter_replace_buf, 0,
12393 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12395 /* create L2 filter, input for L2 filter will be L1 filter */
12396 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12397 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12398 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12400 /* Prepare the buffer, 2 entries */
12401 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12402 filter_replace_buf.data[0] |=
12403 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12404 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12405 filter_replace_buf.data[4] |=
12406 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12407 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12408 &filter_replace_buf);