1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
30 #include <rte_os_shim.h>
32 #include "i40e_logs.h"
33 #include "base/i40e_prototype.h"
34 #include "base/i40e_adminq_cmd.h"
35 #include "base/i40e_type.h"
36 #include "base/i40e_register.h"
37 #include "base/i40e_dcb.h"
38 #include "i40e_ethdev.h"
39 #include "i40e_rxtx.h"
41 #include "i40e_regs.h"
42 #include "rte_pmd_i40e.h"
43 #include "i40e_hash.h"
45 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
46 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
47 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
49 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
51 #define I40E_CLEAR_PXE_WAIT_MS 200
52 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
53 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
55 /* Maximun number of capability elements */
56 #define I40E_MAX_CAP_ELE_NUM 128
58 /* Wait count and interval */
59 #define I40E_CHK_Q_ENA_COUNT 1000
60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
62 /* Maximun number of VSI */
63 #define I40E_MAX_NUM_VSIS (384UL)
65 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
67 /* Flow control default timer */
68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
70 /* Flow control enable fwd bit */
71 #define I40E_PRTMAC_FWD_CTRL 0x00000001
73 /* Receive Packet Buffer size */
74 #define I40E_RXPBSIZE (968 * 1024)
77 #define I40E_KILOSHIFT 10
79 /* Flow control default high water */
80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Flow control default low water */
83 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
85 /* Receive Average Packet Size in Byte*/
86 #define I40E_PACKET_AVERAGE_SIZE 128
88 /* Mask of PF interrupt causes */
89 #define I40E_PFINT_ICR0_ENA_MASK ( \
90 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_GRST_MASK | \
93 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
94 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
95 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
96 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
97 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
98 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
100 #define I40E_FLOW_TYPES ( \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
106 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
110 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
111 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
113 /* Additional timesync values. */
114 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
115 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
116 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
117 #define I40E_PRTTSYN_TSYNENA 0x80000000
118 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
119 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
122 * Below are values for writing un-exposed registers suggested
125 /* Destination MAC address */
126 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
127 /* Source MAC address */
128 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
130 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
132 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
133 /* Single VLAN tag in the inner L2 header */
134 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
135 /* Source IPv4 address */
136 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
137 /* Destination IPv4 address */
138 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
139 /* Source IPv4 address for X722 */
140 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
141 /* Destination IPv4 address for X722 */
142 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
143 /* IPv4 Protocol for X722 */
144 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
145 /* IPv4 Time to Live for X722 */
146 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
147 /* IPv4 Type of Service (TOS) */
148 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
150 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
151 /* IPv4 Time to Live */
152 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
153 /* Source IPv6 address */
154 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
155 /* Destination IPv6 address */
156 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
157 /* IPv6 Traffic Class (TC) */
158 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
159 /* IPv6 Next Header */
160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
164 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
165 /* Destination L4 port */
166 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
167 /* SCTP verification tag */
168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
171 /* Source port of tunneling UDP */
172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
173 /* Destination port of tunneling UDP */
174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
175 /* UDP Tunneling ID, NVGRE/GRE key */
176 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
177 /* Last ether type */
178 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
179 /* Tunneling outer destination IPv4 address */
180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
181 /* Tunneling outer destination IPv6 address */
182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
183 /* 1st word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
185 /* 2nd word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
187 /* 3rd word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
189 /* 4th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
191 /* 5th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
193 /* 6th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
195 /* 7th word of flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
197 /* 8th word of flex payload */
198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
199 /* all 8 words flex payload */
200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
201 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
203 #define I40E_TRANSLATE_INSET 0
204 #define I40E_TRANSLATE_REG 1
206 #define I40E_INSET_IPV4_TOS_MASK 0x0000FF00UL
207 #define I40E_INSET_IPV4_TTL_MASK 0x000000FFUL
208 #define I40E_INSET_IPV4_PROTO_MASK 0x0000FF00UL
209 #define I40E_INSET_IPV6_TC_MASK 0x0000F00FUL
210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x0000FF00UL
211 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000000FFUL
213 /* PCI offset for querying capability */
214 #define PCI_DEV_CAP_REG 0xA4
215 /* PCI offset for enabling/disabling Extended Tag */
216 #define PCI_DEV_CTRL_REG 0xA8
217 /* Bit mask of Extended Tag capability */
218 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
219 /* Bit shift of Extended Tag enable/disable */
220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
221 /* Bit mask of Extended Tag enable/disable */
222 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
224 #define I40E_GLQF_PIT_IPV4_START 2
225 #define I40E_GLQF_PIT_IPV4_COUNT 2
226 #define I40E_GLQF_PIT_IPV6_START 4
227 #define I40E_GLQF_PIT_IPV6_COUNT 2
229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
230 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
231 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
234 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
235 I40E_GLQF_PIT_DEST_OFF_SHIFT)
237 #define I40E_GLQF_PIT_FSIZE_GET(a) (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
238 I40E_GLQF_PIT_FSIZE_SHIFT)
240 #define I40E_GLQF_PIT_BUILD(off, mask) (((off) << 16) | (mask))
241 #define I40E_FDIR_FIELD_OFFSET(a) ((a) >> 1)
243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
245 static int i40e_dev_configure(struct rte_eth_dev *dev);
246 static int i40e_dev_start(struct rte_eth_dev *dev);
247 static int i40e_dev_stop(struct rte_eth_dev *dev);
248 static int i40e_dev_close(struct rte_eth_dev *dev);
249 static int i40e_dev_reset(struct rte_eth_dev *dev);
250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
259 struct rte_eth_xstat *xstats, unsigned n);
260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
261 struct rte_eth_xstat_name *xstats_names,
263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
265 char *fw_version, size_t fw_size);
266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
267 struct rte_eth_dev_info *dev_info);
268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
272 enum rte_vlan_type vlan_type,
274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
282 struct rte_eth_fc_conf *fc_conf);
283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
284 struct rte_eth_fc_conf *fc_conf);
285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
286 struct rte_eth_pfc_conf *pfc_conf);
287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
288 struct rte_ether_addr *mac_addr,
291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
293 struct rte_eth_rss_reta_entry64 *reta_conf,
295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
296 struct rte_eth_rss_reta_entry64 *reta_conf,
299 static int i40e_get_cap(struct i40e_hw *hw);
300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
301 static int i40e_pf_setup(struct i40e_pf *pf);
302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
306 bool offset_loaded, uint64_t *offset, uint64_t *stat);
307 static void i40e_stat_update_48(struct i40e_hw *hw,
313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
314 static void i40e_dev_interrupt_handler(void *param);
315 static void i40e_dev_alarm_handler(void *param);
316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
317 uint32_t base, uint32_t num);
318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
324 static int i40e_veb_release(struct i40e_veb *veb);
325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
326 struct i40e_vsi *vsi);
327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
329 struct i40e_macvlan_filter *mv_f,
332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
334 struct rte_eth_rss_conf *rss_conf);
335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
336 struct rte_eth_rss_conf *rss_conf);
337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
338 struct rte_eth_udp_tunnel *udp_tunnel);
339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
340 struct rte_eth_udp_tunnel *udp_tunnel);
341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
343 const struct rte_flow_ops **ops);
344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
347 static void i40e_configure_registers(struct i40e_hw *hw);
348 static void i40e_hw_init(struct rte_eth_dev *dev);
349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
351 static int i40e_timesync_enable(struct rte_eth_dev *dev);
352 static int i40e_timesync_disable(struct rte_eth_dev *dev);
353 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp,
356 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
360 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
362 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
363 struct timespec *timestamp);
364 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
365 const struct timespec *timestamp);
367 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
369 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
372 static int i40e_get_regs(struct rte_eth_dev *dev,
373 struct rte_dev_reg_info *regs);
375 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
377 static int i40e_get_eeprom(struct rte_eth_dev *dev,
378 struct rte_dev_eeprom_info *eeprom);
380 static int i40e_get_module_info(struct rte_eth_dev *dev,
381 struct rte_eth_dev_module_info *modinfo);
382 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
383 struct rte_dev_eeprom_info *info);
385 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
386 struct rte_ether_addr *mac_addr);
388 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
390 static int i40e_ethertype_filter_convert(
391 const struct rte_eth_ethertype_filter *input,
392 struct i40e_ethertype_filter *filter);
393 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
394 struct i40e_ethertype_filter *filter);
396 static int i40e_tunnel_filter_convert(
397 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
398 struct i40e_tunnel_filter *tunnel_filter);
399 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
400 struct i40e_tunnel_filter *tunnel_filter);
401 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
403 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
404 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
405 static void i40e_filter_restore(struct i40e_pf *pf);
406 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .dev_reset = i40e_dev_reset,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .tx_queue_setup = i40e_dev_tx_queue_setup,
481 .tx_queue_release = i40e_dev_tx_queue_release,
482 .dev_led_on = i40e_dev_led_on,
483 .dev_led_off = i40e_dev_led_off,
484 .flow_ctrl_get = i40e_flow_ctrl_get,
485 .flow_ctrl_set = i40e_flow_ctrl_set,
486 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
487 .mac_addr_add = i40e_macaddr_add,
488 .mac_addr_remove = i40e_macaddr_remove,
489 .reta_update = i40e_dev_rss_reta_update,
490 .reta_query = i40e_dev_rss_reta_query,
491 .rss_hash_update = i40e_dev_rss_hash_update,
492 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
493 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
494 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
495 .flow_ops_get = i40e_dev_flow_ops_get,
496 .rxq_info_get = i40e_rxq_info_get,
497 .txq_info_get = i40e_txq_info_get,
498 .rx_burst_mode_get = i40e_rx_burst_mode_get,
499 .tx_burst_mode_get = i40e_tx_burst_mode_get,
500 .timesync_enable = i40e_timesync_enable,
501 .timesync_disable = i40e_timesync_disable,
502 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
503 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
504 .get_dcb_info = i40e_dev_get_dcb_info,
505 .timesync_adjust_time = i40e_timesync_adjust_time,
506 .timesync_read_time = i40e_timesync_read_time,
507 .timesync_write_time = i40e_timesync_write_time,
508 .get_reg = i40e_get_regs,
509 .get_eeprom_length = i40e_get_eeprom_length,
510 .get_eeprom = i40e_get_eeprom,
511 .get_module_info = i40e_get_module_info,
512 .get_module_eeprom = i40e_get_module_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
515 .tm_ops_get = i40e_tm_ops_get,
516 .tx_done_cleanup = i40e_tx_done_cleanup,
517 .get_monitor_addr = i40e_get_monitor_addr,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"rx_size_error_packets", offsetof(struct i40e_pf, rx_err1) -
534 offsetof(struct i40e_pf, stats)},
535 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
536 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
537 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
538 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
541 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
542 sizeof(rte_i40e_stats_strings[0]))
544 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
545 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
546 tx_dropped_link_down)},
547 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
548 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
551 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
553 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
555 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
557 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
558 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
559 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
560 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
561 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
562 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
578 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
579 mac_short_packet_dropped)},
580 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
583 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
584 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
596 {"rx_flow_director_atr_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
598 {"rx_flow_director_sb_match_packets",
599 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
600 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
604 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
606 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
610 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
611 sizeof(rte_i40e_hw_port_strings[0]))
613 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
614 {"xon_packets", offsetof(struct i40e_hw_port_stats,
616 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
621 sizeof(rte_i40e_rxq_prio_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
628 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
629 priority_xon_2_xoff)},
632 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
633 sizeof(rte_i40e_txq_prio_strings[0]))
636 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
637 struct rte_pci_device *pci_dev)
639 char name[RTE_ETH_NAME_MAX_LEN];
640 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
643 if (pci_dev->device.devargs) {
644 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
650 if (eth_da.nb_representor_ports > 0 &&
651 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
652 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
653 pci_dev->device.devargs->args);
657 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
658 sizeof(struct i40e_adapter),
659 eth_dev_pci_specific_init, pci_dev,
660 eth_i40e_dev_init, NULL);
662 if (retval || eth_da.nb_representor_ports < 1)
665 /* probe VF representor ports */
666 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
667 pci_dev->device.name);
669 if (pf_ethdev == NULL)
672 for (i = 0; i < eth_da.nb_representor_ports; i++) {
673 struct i40e_vf_representor representor = {
674 .vf_id = eth_da.representor_ports[i],
675 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
676 pf_ethdev->data->dev_private)->switch_domain_id,
677 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
678 pf_ethdev->data->dev_private)
681 /* representor port net_bdf_port */
682 snprintf(name, sizeof(name), "net_%s_representor_%d",
683 pci_dev->device.name, eth_da.representor_ports[i]);
685 retval = rte_eth_dev_create(&pci_dev->device, name,
686 sizeof(struct i40e_vf_representor), NULL, NULL,
687 i40e_vf_representor_init, &representor);
690 PMD_DRV_LOG(ERR, "failed to create i40e vf "
691 "representor %s.", name);
697 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
699 struct rte_eth_dev *ethdev;
701 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
705 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
706 return rte_eth_dev_pci_generic_remove(pci_dev,
707 i40e_vf_representor_uninit);
709 return rte_eth_dev_pci_generic_remove(pci_dev,
710 eth_i40e_dev_uninit);
713 static struct rte_pci_driver rte_i40e_pmd = {
714 .id_table = pci_id_i40e_map,
715 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
716 .probe = eth_i40e_pci_probe,
717 .remove = eth_i40e_pci_remove,
721 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
724 uint32_t ori_reg_val;
725 struct rte_eth_dev_data *dev_data =
726 ((struct i40e_adapter *)hw->back)->pf.dev_data;
727 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
729 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
730 i40e_write_rx_ctl(hw, reg_addr, reg_val);
731 if (ori_reg_val != reg_val)
733 "i40e device %s changed global register [0x%08x]."
734 " original: 0x%08x, new: 0x%08x",
735 dev->device->name, reg_addr, ori_reg_val, reg_val);
738 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
739 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
740 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
742 #ifndef I40E_GLQF_ORT
743 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
745 #ifndef I40E_GLQF_PIT
746 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
748 #ifndef I40E_GLQF_L3_MAP
749 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
752 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
755 * Initialize registers for parsing packet type of QinQ
756 * This should be removed from code once proper
757 * configuration API is added to avoid configuration conflicts
758 * between ports of the same device.
760 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
761 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
764 static inline void i40e_config_automask(struct i40e_pf *pf)
766 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
769 /* INTENA flag is not auto-cleared for interrupt */
770 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
771 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
772 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
774 /* If support multi-driver, PF will use INT0. */
775 if (!pf->support_multi_driver)
776 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
778 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
781 static inline void i40e_clear_automask(struct i40e_pf *pf)
783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
786 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
787 val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
788 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
790 if (!pf->support_multi_driver)
791 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
793 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
796 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
799 * Add a ethertype filter to drop all flow control frames transmitted
803 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
805 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
806 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
807 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
808 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
811 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
812 I40E_FLOW_CONTROL_ETHERTYPE, flags,
813 pf->main_vsi_seid, 0,
817 "Failed to add filter to drop flow control frames from VSIs.");
821 floating_veb_list_handler(__rte_unused const char *key,
822 const char *floating_veb_value,
826 unsigned int count = 0;
829 bool *vf_floating_veb = opaque;
831 while (isblank(*floating_veb_value))
832 floating_veb_value++;
834 /* Reset floating VEB configuration for VFs */
835 for (idx = 0; idx < I40E_MAX_VF; idx++)
836 vf_floating_veb[idx] = false;
840 while (isblank(*floating_veb_value))
841 floating_veb_value++;
842 if (*floating_veb_value == '\0')
845 idx = strtoul(floating_veb_value, &end, 10);
846 if (errno || end == NULL)
850 while (isblank(*end))
854 } else if ((*end == ';') || (*end == '\0')) {
856 if (min == I40E_MAX_VF)
858 if (max >= I40E_MAX_VF)
859 max = I40E_MAX_VF - 1;
860 for (idx = min; idx <= max; idx++) {
861 vf_floating_veb[idx] = true;
868 floating_veb_value = end + 1;
869 } while (*end != '\0');
878 config_vf_floating_veb(struct rte_devargs *devargs,
879 uint16_t floating_veb,
880 bool *vf_floating_veb)
882 struct rte_kvargs *kvlist;
884 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
888 /* All the VFs attach to the floating VEB by default
889 * when the floating VEB is enabled.
891 for (i = 0; i < I40E_MAX_VF; i++)
892 vf_floating_veb[i] = true;
897 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
901 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
902 rte_kvargs_free(kvlist);
905 /* When the floating_veb_list parameter exists, all the VFs
906 * will attach to the legacy VEB firstly, then configure VFs
907 * to the floating VEB according to the floating_veb_list.
909 if (rte_kvargs_process(kvlist, floating_veb_list,
910 floating_veb_list_handler,
911 vf_floating_veb) < 0) {
912 rte_kvargs_free(kvlist);
915 rte_kvargs_free(kvlist);
919 i40e_check_floating_handler(__rte_unused const char *key,
921 __rte_unused void *opaque)
923 if (strcmp(value, "1"))
930 is_floating_veb_supported(struct rte_devargs *devargs)
932 struct rte_kvargs *kvlist;
933 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
938 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
942 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
943 rte_kvargs_free(kvlist);
946 /* Floating VEB is enabled when there's key-value:
947 * enable_floating_veb=1
949 if (rte_kvargs_process(kvlist, floating_veb_key,
950 i40e_check_floating_handler, NULL) < 0) {
951 rte_kvargs_free(kvlist);
954 rte_kvargs_free(kvlist);
960 config_floating_veb(struct rte_eth_dev *dev)
962 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
968 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
970 is_floating_veb_supported(pci_dev->device.devargs);
971 config_vf_floating_veb(pci_dev->device.devargs,
973 pf->floating_veb_list);
975 pf->floating_veb = false;
979 #define I40E_L2_TAGS_S_TAG_SHIFT 1
980 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
983 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
985 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
986 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
987 char ethertype_hash_name[RTE_HASH_NAMESIZE];
990 struct rte_hash_parameters ethertype_hash_params = {
991 .name = ethertype_hash_name,
992 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
993 .key_len = sizeof(struct i40e_ethertype_filter_input),
994 .hash_func = rte_hash_crc,
995 .hash_func_init_val = 0,
996 .socket_id = rte_socket_id(),
999 /* Initialize ethertype filter rule list and hash */
1000 TAILQ_INIT(ðertype_rule->ethertype_list);
1001 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1002 "ethertype_%s", dev->device->name);
1003 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
1004 if (!ethertype_rule->hash_table) {
1005 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1008 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1009 sizeof(struct i40e_ethertype_filter *) *
1010 I40E_MAX_ETHERTYPE_FILTER_NUM,
1012 if (!ethertype_rule->hash_map) {
1014 "Failed to allocate memory for ethertype hash map!");
1016 goto err_ethertype_hash_map_alloc;
1021 err_ethertype_hash_map_alloc:
1022 rte_hash_free(ethertype_rule->hash_table);
1028 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1030 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1032 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1035 struct rte_hash_parameters tunnel_hash_params = {
1036 .name = tunnel_hash_name,
1037 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1038 .key_len = sizeof(struct i40e_tunnel_filter_input),
1039 .hash_func = rte_hash_crc,
1040 .hash_func_init_val = 0,
1041 .socket_id = rte_socket_id(),
1044 /* Initialize tunnel filter rule list and hash */
1045 TAILQ_INIT(&tunnel_rule->tunnel_list);
1046 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1047 "tunnel_%s", dev->device->name);
1048 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1049 if (!tunnel_rule->hash_table) {
1050 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1053 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1054 sizeof(struct i40e_tunnel_filter *) *
1055 I40E_MAX_TUNNEL_FILTER_NUM,
1057 if (!tunnel_rule->hash_map) {
1059 "Failed to allocate memory for tunnel hash map!");
1061 goto err_tunnel_hash_map_alloc;
1066 err_tunnel_hash_map_alloc:
1067 rte_hash_free(tunnel_rule->hash_table);
1073 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1077 struct i40e_fdir_info *fdir_info = &pf->fdir;
1078 char fdir_hash_name[RTE_HASH_NAMESIZE];
1079 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1080 uint32_t best = hw->func_caps.fd_filters_best_effort;
1081 enum i40e_filter_pctype pctype;
1082 struct rte_bitmap *bmp = NULL;
1088 struct rte_hash_parameters fdir_hash_params = {
1089 .name = fdir_hash_name,
1090 .entries = I40E_MAX_FDIR_FILTER_NUM,
1091 .key_len = sizeof(struct i40e_fdir_input),
1092 .hash_func = rte_hash_crc,
1093 .hash_func_init_val = 0,
1094 .socket_id = rte_socket_id(),
1097 /* Initialize flow director filter rule list and hash */
1098 TAILQ_INIT(&fdir_info->fdir_list);
1099 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1100 "fdir_%s", dev->device->name);
1101 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1102 if (!fdir_info->hash_table) {
1103 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1107 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1108 sizeof(struct i40e_fdir_filter *) *
1109 I40E_MAX_FDIR_FILTER_NUM,
1111 if (!fdir_info->hash_map) {
1113 "Failed to allocate memory for fdir hash map!");
1115 goto err_fdir_hash_map_alloc;
1118 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1119 sizeof(struct i40e_fdir_filter) *
1120 I40E_MAX_FDIR_FILTER_NUM,
1123 if (!fdir_info->fdir_filter_array) {
1125 "Failed to allocate memory for fdir filter array!");
1127 goto err_fdir_filter_array_alloc;
1130 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1131 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1132 pf->fdir.flow_count[pctype] = 0;
1134 fdir_info->fdir_space_size = alloc + best;
1135 fdir_info->fdir_actual_cnt = 0;
1136 fdir_info->fdir_guarantee_total_space = alloc;
1137 fdir_info->fdir_guarantee_free_space =
1138 fdir_info->fdir_guarantee_total_space;
1140 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1142 fdir_info->fdir_flow_pool.pool =
1143 rte_zmalloc("i40e_fdir_entry",
1144 sizeof(struct i40e_fdir_entry) *
1145 fdir_info->fdir_space_size,
1148 if (!fdir_info->fdir_flow_pool.pool) {
1150 "Failed to allocate memory for bitmap flow!");
1152 goto err_fdir_bitmap_flow_alloc;
1155 for (i = 0; i < fdir_info->fdir_space_size; i++)
1156 fdir_info->fdir_flow_pool.pool[i].idx = i;
1159 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1160 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1163 "Failed to allocate memory for fdir bitmap!");
1165 goto err_fdir_mem_alloc;
1167 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1170 "Failed to initialization fdir bitmap!");
1172 goto err_fdir_bmp_alloc;
1174 for (i = 0; i < fdir_info->fdir_space_size; i++)
1175 rte_bitmap_set(bmp, i);
1177 fdir_info->fdir_flow_pool.bitmap = bmp;
1184 rte_free(fdir_info->fdir_flow_pool.pool);
1185 err_fdir_bitmap_flow_alloc:
1186 rte_free(fdir_info->fdir_filter_array);
1187 err_fdir_filter_array_alloc:
1188 rte_free(fdir_info->hash_map);
1189 err_fdir_hash_map_alloc:
1190 rte_hash_free(fdir_info->hash_table);
1196 i40e_init_customized_info(struct i40e_pf *pf)
1200 /* Initialize customized pctype */
1201 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1202 pf->customized_pctype[i].index = i;
1203 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1204 pf->customized_pctype[i].valid = false;
1207 pf->gtp_support = false;
1208 pf->esp_support = false;
1212 i40e_init_filter_invalidation(struct i40e_pf *pf)
1214 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1215 struct i40e_fdir_info *fdir_info = &pf->fdir;
1216 uint32_t glqf_ctl_reg = 0;
1218 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1219 if (!pf->support_multi_driver) {
1220 fdir_info->fdir_invalprio = 1;
1221 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1222 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1223 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1225 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1226 fdir_info->fdir_invalprio = 1;
1227 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1229 fdir_info->fdir_invalprio = 0;
1230 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1236 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240 struct i40e_queue_regions *info = &pf->queue_region;
1243 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1244 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1246 memset(info, 0, sizeof(struct i40e_queue_regions));
1250 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1255 unsigned long support_multi_driver;
1258 pf = (struct i40e_pf *)opaque;
1261 support_multi_driver = strtoul(value, &end, 10);
1262 if (errno != 0 || end == value || *end != 0) {
1263 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1267 if (support_multi_driver == 1 || support_multi_driver == 0)
1268 pf->support_multi_driver = (bool)support_multi_driver;
1270 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1271 "enable global configuration by default."
1272 ETH_I40E_SUPPORT_MULTI_DRIVER);
1277 i40e_support_multi_driver(struct rte_eth_dev *dev)
1279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1280 struct rte_kvargs *kvlist;
1283 /* Enable global configuration by default */
1284 pf->support_multi_driver = false;
1286 if (!dev->device->devargs)
1289 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1293 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1294 if (!kvargs_count) {
1295 rte_kvargs_free(kvlist);
1299 if (kvargs_count > 1)
1300 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1301 "the first invalid or last valid one is used !",
1302 ETH_I40E_SUPPORT_MULTI_DRIVER);
1304 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1305 i40e_parse_multi_drv_handler, pf) < 0) {
1306 rte_kvargs_free(kvlist);
1310 rte_kvargs_free(kvlist);
1315 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1316 uint32_t reg_addr, uint64_t reg_val,
1317 struct i40e_asq_cmd_details *cmd_details)
1319 uint64_t ori_reg_val;
1320 struct rte_eth_dev_data *dev_data =
1321 ((struct i40e_adapter *)hw->back)->pf.dev_data;
1322 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
1325 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1326 if (ret != I40E_SUCCESS) {
1328 "Fail to debug read from 0x%08x",
1333 if (ori_reg_val != reg_val)
1334 PMD_DRV_LOG(WARNING,
1335 "i40e device %s changed global register [0x%08x]."
1336 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1337 dev->device->name, reg_addr, ori_reg_val, reg_val);
1339 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1343 read_vf_msg_config(__rte_unused const char *key,
1347 struct i40e_vf_msg_cfg *cfg = opaque;
1349 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1350 &cfg->ignore_second) != 3) {
1351 memset(cfg, 0, sizeof(*cfg));
1352 PMD_DRV_LOG(ERR, "format error! example: "
1353 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1358 * If the message validation function been enabled, the 'period'
1359 * and 'ignore_second' must greater than 0.
1361 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1362 memset(cfg, 0, sizeof(*cfg));
1363 PMD_DRV_LOG(ERR, "%s error! the second and third"
1364 " number must be greater than 0!",
1365 ETH_I40E_VF_MSG_CFG);
1373 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1374 struct i40e_vf_msg_cfg *msg_cfg)
1376 struct rte_kvargs *kvlist;
1380 memset(msg_cfg, 0, sizeof(*msg_cfg));
1382 if (!dev->device->devargs)
1385 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1389 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1393 if (kvargs_count > 1) {
1394 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1395 ETH_I40E_VF_MSG_CFG);
1400 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1401 read_vf_msg_config, msg_cfg) < 0)
1405 rte_kvargs_free(kvlist);
1409 #define I40E_ALARM_INTERVAL 50000 /* us */
1412 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1414 struct rte_pci_device *pci_dev;
1415 struct rte_intr_handle *intr_handle;
1416 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1417 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418 struct i40e_vsi *vsi;
1421 uint8_t aq_fail = 0;
1423 PMD_INIT_FUNC_TRACE();
1425 dev->dev_ops = &i40e_eth_dev_ops;
1426 dev->rx_queue_count = i40e_dev_rx_queue_count;
1427 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1428 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1429 dev->rx_pkt_burst = i40e_recv_pkts;
1430 dev->tx_pkt_burst = i40e_xmit_pkts;
1431 dev->tx_pkt_prepare = i40e_prep_pkts;
1433 /* for secondary processes, we don't initialise any further as primary
1434 * has already done this work. Only check we don't need a different
1436 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1437 i40e_set_rx_function(dev);
1438 i40e_set_tx_function(dev);
1441 i40e_set_default_ptype_table(dev);
1442 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1443 intr_handle = &pci_dev->intr_handle;
1445 rte_eth_copy_pci_info(dev, pci_dev);
1447 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1448 pf->dev_data = dev->data;
1450 hw->back = I40E_PF_TO_ADAPTER(pf);
1451 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1454 "Hardware is not available, as address is NULL");
1458 hw->vendor_id = pci_dev->id.vendor_id;
1459 hw->device_id = pci_dev->id.device_id;
1460 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1461 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1462 hw->bus.device = pci_dev->addr.devid;
1463 hw->bus.func = pci_dev->addr.function;
1464 hw->adapter_stopped = 0;
1465 hw->adapter_closed = 0;
1467 /* Init switch device pointer */
1468 hw->switch_dev = NULL;
1471 * Switch Tag value should not be identical to either the First Tag
1472 * or Second Tag values. So set something other than common Ethertype
1473 * for internal switching.
1475 hw->switch_tag = 0xffff;
1477 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1478 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1479 PMD_INIT_LOG(ERR, "\nERROR: "
1480 "Firmware recovery mode detected. Limiting functionality.\n"
1481 "Refer to the Intel(R) Ethernet Adapters and Devices "
1482 "User Guide for details on firmware recovery mode.");
1486 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1487 /* Check if need to support multi-driver */
1488 i40e_support_multi_driver(dev);
1490 /* Make sure all is clean before doing PF reset */
1493 /* Reset here to make sure all is clean for each PF */
1494 ret = i40e_pf_reset(hw);
1496 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1500 /* Initialize the shared code (base driver) */
1501 ret = i40e_init_shared_code(hw);
1503 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1507 /* Initialize the parameters for adminq */
1508 i40e_init_adminq_parameter(hw);
1509 ret = i40e_init_adminq(hw);
1510 if (ret != I40E_SUCCESS) {
1511 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1514 /* Firmware of SFP x722 does not support 802.1ad frames ability */
1515 if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1516 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1517 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1519 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1520 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1521 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1522 ((hw->nvm.version >> 12) & 0xf),
1523 ((hw->nvm.version >> 4) & 0xff),
1524 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1526 /* Initialize the hardware */
1529 i40e_config_automask(pf);
1531 i40e_set_default_pctype_table(dev);
1534 * To work around the NVM issue, initialize registers
1535 * for packet type of QinQ by software.
1536 * It should be removed once issues are fixed in NVM.
1538 if (!pf->support_multi_driver)
1539 i40e_GLQF_reg_init(hw);
1541 /* Initialize the input set for filters (hash and fd) to default value */
1542 i40e_filter_input_set_init(pf);
1544 /* initialise the L3_MAP register */
1545 if (!pf->support_multi_driver) {
1546 ret = i40e_aq_debug_write_global_register(hw,
1547 I40E_GLQF_L3_MAP(40),
1550 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1553 "Global register 0x%08x is changed with 0x28",
1554 I40E_GLQF_L3_MAP(40));
1557 /* Need the special FW version to support floating VEB */
1558 config_floating_veb(dev);
1559 /* Clear PXE mode */
1560 i40e_clear_pxe_mode(hw);
1561 i40e_dev_sync_phy_type(hw);
1564 * On X710, performance number is far from the expectation on recent
1565 * firmware versions. The fix for this issue may not be integrated in
1566 * the following firmware version. So the workaround in software driver
1567 * is needed. It needs to modify the initial values of 3 internal only
1568 * registers. Note that the workaround can be removed when it is fixed
1569 * in firmware in the future.
1571 i40e_configure_registers(hw);
1573 /* Get hw capabilities */
1574 ret = i40e_get_cap(hw);
1575 if (ret != I40E_SUCCESS) {
1576 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1577 goto err_get_capabilities;
1580 /* Initialize parameters for PF */
1581 ret = i40e_pf_parameter_init(dev);
1583 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1584 goto err_parameter_init;
1587 /* Initialize the queue management */
1588 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1590 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1591 goto err_qp_pool_init;
1593 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1594 hw->func_caps.num_msix_vectors - 1);
1596 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1597 goto err_msix_pool_init;
1600 /* Initialize lan hmc */
1601 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1602 hw->func_caps.num_rx_qp, 0, 0);
1603 if (ret != I40E_SUCCESS) {
1604 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1605 goto err_init_lan_hmc;
1608 /* Configure lan hmc */
1609 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1610 if (ret != I40E_SUCCESS) {
1611 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1612 goto err_configure_lan_hmc;
1615 /* Get and check the mac address */
1616 i40e_get_mac_addr(hw, hw->mac.addr);
1617 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1618 PMD_INIT_LOG(ERR, "mac address is not valid");
1620 goto err_get_mac_addr;
1622 /* Copy the permanent MAC address */
1623 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1624 (struct rte_ether_addr *)hw->mac.perm_addr);
1626 /* Disable flow control */
1627 hw->fc.requested_mode = I40E_FC_NONE;
1628 i40e_set_fc(hw, &aq_fail, TRUE);
1630 /* Set the global registers with default ether type value */
1631 if (!pf->support_multi_driver) {
1632 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1633 RTE_ETHER_TYPE_VLAN);
1634 if (ret != I40E_SUCCESS) {
1636 "Failed to set the default outer "
1638 goto err_setup_pf_switch;
1642 /* PF setup, which includes VSI setup */
1643 ret = i40e_pf_setup(pf);
1645 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1646 goto err_setup_pf_switch;
1651 /* Disable double vlan by default */
1652 i40e_vsi_config_double_vlan(vsi, FALSE);
1654 /* Disable S-TAG identification when floating_veb is disabled */
1655 if (!pf->floating_veb) {
1656 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1657 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1658 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1659 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1663 if (!vsi->max_macaddrs)
1664 len = RTE_ETHER_ADDR_LEN;
1666 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1668 /* Should be after VSI initialized */
1669 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1670 if (!dev->data->mac_addrs) {
1672 "Failed to allocated memory for storing mac address");
1675 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1676 &dev->data->mac_addrs[0]);
1678 /* Init dcb to sw mode by default */
1679 ret = i40e_dcb_init_configure(dev, TRUE);
1680 if (ret != I40E_SUCCESS) {
1681 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1682 pf->flags &= ~I40E_FLAG_DCB;
1684 /* Update HW struct after DCB configuration */
1687 /* initialize pf host driver to setup SRIOV resource if applicable */
1688 i40e_pf_host_init(dev);
1690 /* register callback func to eal lib */
1691 rte_intr_callback_register(intr_handle,
1692 i40e_dev_interrupt_handler, dev);
1694 /* configure and enable device interrupt */
1695 i40e_pf_config_irq0(hw, TRUE);
1696 i40e_pf_enable_irq0(hw);
1698 /* enable uio intr after callback register */
1699 rte_intr_enable(intr_handle);
1701 /* By default disable flexible payload in global configuration */
1702 if (!pf->support_multi_driver)
1703 i40e_flex_payload_reg_set_default(hw);
1706 * Add an ethertype filter to drop all flow control frames transmitted
1707 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1710 i40e_add_tx_flow_control_drop_filter(pf);
1712 /* Set the max frame size to 0x2600 by default,
1713 * in case other drivers changed the default value.
1715 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1717 /* initialize RSS rule list */
1718 TAILQ_INIT(&pf->rss_config_list);
1720 /* initialize Traffic Manager configuration */
1721 i40e_tm_conf_init(dev);
1723 /* Initialize customized information */
1724 i40e_init_customized_info(pf);
1726 /* Initialize the filter invalidation configuration */
1727 i40e_init_filter_invalidation(pf);
1729 ret = i40e_init_ethtype_filter_list(dev);
1731 goto err_init_ethtype_filter_list;
1732 ret = i40e_init_tunnel_filter_list(dev);
1734 goto err_init_tunnel_filter_list;
1735 ret = i40e_init_fdir_filter_list(dev);
1737 goto err_init_fdir_filter_list;
1739 /* initialize queue region configuration */
1740 i40e_init_queue_region_conf(dev);
1742 /* reset all stats of the device, including pf and main vsi */
1743 i40e_dev_stats_reset(dev);
1747 err_init_fdir_filter_list:
1748 rte_hash_free(pf->tunnel.hash_table);
1749 rte_free(pf->tunnel.hash_map);
1750 err_init_tunnel_filter_list:
1751 rte_hash_free(pf->ethertype.hash_table);
1752 rte_free(pf->ethertype.hash_map);
1753 err_init_ethtype_filter_list:
1754 rte_intr_callback_unregister(intr_handle,
1755 i40e_dev_interrupt_handler, dev);
1756 rte_free(dev->data->mac_addrs);
1757 dev->data->mac_addrs = NULL;
1759 i40e_vsi_release(pf->main_vsi);
1760 err_setup_pf_switch:
1762 err_configure_lan_hmc:
1763 (void)i40e_shutdown_lan_hmc(hw);
1765 i40e_res_pool_destroy(&pf->msix_pool);
1767 i40e_res_pool_destroy(&pf->qp_pool);
1770 err_get_capabilities:
1771 (void)i40e_shutdown_adminq(hw);
1777 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1779 struct i40e_ethertype_filter *p_ethertype;
1780 struct i40e_ethertype_rule *ethertype_rule;
1782 ethertype_rule = &pf->ethertype;
1783 /* Remove all ethertype filter rules and hash */
1784 if (ethertype_rule->hash_map)
1785 rte_free(ethertype_rule->hash_map);
1786 if (ethertype_rule->hash_table)
1787 rte_hash_free(ethertype_rule->hash_table);
1789 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1790 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1791 p_ethertype, rules);
1792 rte_free(p_ethertype);
1797 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1799 struct i40e_tunnel_filter *p_tunnel;
1800 struct i40e_tunnel_rule *tunnel_rule;
1802 tunnel_rule = &pf->tunnel;
1803 /* Remove all tunnel director rules and hash */
1804 if (tunnel_rule->hash_map)
1805 rte_free(tunnel_rule->hash_map);
1806 if (tunnel_rule->hash_table)
1807 rte_hash_free(tunnel_rule->hash_table);
1809 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1810 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1816 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1818 struct i40e_fdir_filter *p_fdir;
1819 struct i40e_fdir_info *fdir_info;
1821 fdir_info = &pf->fdir;
1823 /* Remove all flow director rules */
1824 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1825 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1829 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1831 struct i40e_fdir_info *fdir_info;
1833 fdir_info = &pf->fdir;
1835 /* flow director memory cleanup */
1836 if (fdir_info->hash_map)
1837 rte_free(fdir_info->hash_map);
1838 if (fdir_info->hash_table)
1839 rte_hash_free(fdir_info->hash_table);
1840 if (fdir_info->fdir_flow_pool.bitmap)
1841 rte_free(fdir_info->fdir_flow_pool.bitmap);
1842 if (fdir_info->fdir_flow_pool.pool)
1843 rte_free(fdir_info->fdir_flow_pool.pool);
1844 if (fdir_info->fdir_filter_array)
1845 rte_free(fdir_info->fdir_filter_array);
1848 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1851 * Disable by default flexible payload
1852 * for corresponding L2/L3/L4 layers.
1854 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1855 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1856 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1860 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1864 PMD_INIT_FUNC_TRACE();
1866 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1869 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 if (hw->adapter_closed == 0)
1872 i40e_dev_close(dev);
1878 i40e_dev_configure(struct rte_eth_dev *dev)
1880 struct i40e_adapter *ad =
1881 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1882 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1887 ret = i40e_dev_sync_phy_type(hw);
1891 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1892 * bulk allocation or vector Rx preconditions we will reset it.
1894 ad->rx_bulk_alloc_allowed = true;
1895 ad->rx_vec_allowed = true;
1896 ad->tx_simple_allowed = true;
1897 ad->tx_vec_allowed = true;
1899 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1900 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1902 /* Only legacy filter API needs the following fdir config. So when the
1903 * legacy filter API is deprecated, the following codes should also be
1906 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1907 ret = i40e_fdir_setup(pf);
1908 if (ret != I40E_SUCCESS) {
1909 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1912 ret = i40e_fdir_configure(dev);
1914 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1918 i40e_fdir_teardown(pf);
1920 ret = i40e_dev_init_vlan(dev);
1925 * General PMD driver call sequence are NIC init, configure,
1926 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1927 * will try to lookup the VSI that specific queue belongs to if VMDQ
1928 * applicable. So, VMDQ setting has to be done before
1929 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1930 * For RSS setting, it will try to calculate actual configured RX queue
1931 * number, which will be available after rx_queue_setup(). dev_start()
1932 * function is good to place RSS setup.
1934 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1935 ret = i40e_vmdq_setup(dev);
1940 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1941 ret = i40e_dcb_setup(dev);
1943 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1948 TAILQ_INIT(&pf->flow_list);
1953 /* need to release vmdq resource if exists */
1954 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955 i40e_vsi_release(pf->vmdq[i].vsi);
1956 pf->vmdq[i].vsi = NULL;
1961 /* Need to release fdir resource if exists.
1962 * Only legacy filter API needs the following fdir config. So when the
1963 * legacy filter API is deprecated, the following code should also be
1966 i40e_fdir_teardown(pf);
1971 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1973 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
1974 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1975 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1976 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1977 uint16_t msix_vect = vsi->msix_intr;
1980 for (i = 0; i < vsi->nb_qps; i++) {
1981 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1982 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1986 if (vsi->type != I40E_VSI_SRIOV) {
1987 if (!rte_intr_allow_others(intr_handle)) {
1988 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1989 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1991 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1994 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1995 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1997 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2002 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2003 vsi->user_param + (msix_vect - 1);
2005 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2006 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2008 I40E_WRITE_FLUSH(hw);
2012 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2013 int base_queue, int nb_queue,
2018 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2019 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2021 /* Bind all RX queues to allocated MSIX interrupt */
2022 for (i = 0; i < nb_queue; i++) {
2023 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2024 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2025 ((base_queue + i + 1) <<
2026 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2027 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2028 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2030 if (i == nb_queue - 1)
2031 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2032 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2035 /* Write first RX queue to Link list register as the head element */
2036 if (vsi->type != I40E_VSI_SRIOV) {
2038 i40e_calc_itr_interval(1, pf->support_multi_driver);
2040 if (msix_vect == I40E_MISC_VEC_ID) {
2041 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2043 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2045 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2047 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2050 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2052 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2054 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2056 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2063 if (msix_vect == I40E_MISC_VEC_ID) {
2065 I40E_VPINT_LNKLST0(vsi->user_param),
2067 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2069 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2071 /* num_msix_vectors_vf needs to minus irq0 */
2072 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2073 vsi->user_param + (msix_vect - 1);
2075 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2077 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2079 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2083 I40E_WRITE_FLUSH(hw);
2087 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2089 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2090 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2091 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2092 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2093 uint16_t msix_vect = vsi->msix_intr;
2094 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2095 uint16_t queue_idx = 0;
2099 for (i = 0; i < vsi->nb_qps; i++) {
2100 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2101 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2104 /* VF bind interrupt */
2105 if (vsi->type == I40E_VSI_SRIOV) {
2106 if (vsi->nb_msix == 0) {
2107 PMD_DRV_LOG(ERR, "No msix resource");
2110 __vsi_queues_bind_intr(vsi, msix_vect,
2111 vsi->base_queue, vsi->nb_qps,
2116 /* PF & VMDq bind interrupt */
2117 if (rte_intr_dp_is_en(intr_handle)) {
2118 if (vsi->type == I40E_VSI_MAIN) {
2121 } else if (vsi->type == I40E_VSI_VMDQ2) {
2122 struct i40e_vsi *main_vsi =
2123 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2124 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2129 for (i = 0; i < vsi->nb_used_qps; i++) {
2130 if (vsi->nb_msix == 0) {
2131 PMD_DRV_LOG(ERR, "No msix resource");
2133 } else if (nb_msix <= 1) {
2134 if (!rte_intr_allow_others(intr_handle))
2135 /* allow to share MISC_VEC_ID */
2136 msix_vect = I40E_MISC_VEC_ID;
2138 /* no enough msix_vect, map all to one */
2139 __vsi_queues_bind_intr(vsi, msix_vect,
2140 vsi->base_queue + i,
2141 vsi->nb_used_qps - i,
2143 for (; !!record && i < vsi->nb_used_qps; i++)
2144 intr_handle->intr_vec[queue_idx + i] =
2148 /* 1:1 queue/msix_vect mapping */
2149 __vsi_queues_bind_intr(vsi, msix_vect,
2150 vsi->base_queue + i, 1,
2153 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2163 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2165 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2167 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2168 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2169 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2170 uint16_t msix_intr, i;
2172 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2173 for (i = 0; i < vsi->nb_msix; i++) {
2174 msix_intr = vsi->msix_intr + i;
2175 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2176 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2177 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2178 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2181 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2182 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2183 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2184 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2186 I40E_WRITE_FLUSH(hw);
2190 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2192 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2193 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2194 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2195 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2196 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2197 uint16_t msix_intr, i;
2199 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2200 for (i = 0; i < vsi->nb_msix; i++) {
2201 msix_intr = vsi->msix_intr + i;
2202 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2203 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2206 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2207 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2209 I40E_WRITE_FLUSH(hw);
2212 static inline uint8_t
2213 i40e_parse_link_speeds(uint16_t link_speeds)
2215 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2217 if (link_speeds & ETH_LINK_SPEED_40G)
2218 link_speed |= I40E_LINK_SPEED_40GB;
2219 if (link_speeds & ETH_LINK_SPEED_25G)
2220 link_speed |= I40E_LINK_SPEED_25GB;
2221 if (link_speeds & ETH_LINK_SPEED_20G)
2222 link_speed |= I40E_LINK_SPEED_20GB;
2223 if (link_speeds & ETH_LINK_SPEED_10G)
2224 link_speed |= I40E_LINK_SPEED_10GB;
2225 if (link_speeds & ETH_LINK_SPEED_1G)
2226 link_speed |= I40E_LINK_SPEED_1GB;
2227 if (link_speeds & ETH_LINK_SPEED_100M)
2228 link_speed |= I40E_LINK_SPEED_100MB;
2234 i40e_phy_conf_link(struct i40e_hw *hw,
2236 uint8_t force_speed,
2239 enum i40e_status_code status;
2240 struct i40e_aq_get_phy_abilities_resp phy_ab;
2241 struct i40e_aq_set_phy_config phy_conf;
2242 enum i40e_aq_phy_type cnt;
2243 uint8_t avail_speed;
2244 uint32_t phy_type_mask = 0;
2246 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2247 I40E_AQ_PHY_FLAG_PAUSE_RX |
2248 I40E_AQ_PHY_FLAG_PAUSE_RX |
2249 I40E_AQ_PHY_FLAG_LOW_POWER;
2252 /* To get phy capabilities of available speeds. */
2253 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2256 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2260 avail_speed = phy_ab.link_speed;
2262 /* To get the current phy config. */
2263 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2266 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2271 /* If link needs to go up and it is in autoneg mode the speed is OK,
2272 * no need to set up again.
2274 if (is_up && phy_ab.phy_type != 0 &&
2275 abilities & I40E_AQ_PHY_AN_ENABLED &&
2276 phy_ab.link_speed != 0)
2277 return I40E_SUCCESS;
2279 memset(&phy_conf, 0, sizeof(phy_conf));
2281 /* bits 0-2 use the values from get_phy_abilities_resp */
2283 abilities |= phy_ab.abilities & mask;
2285 phy_conf.abilities = abilities;
2287 /* If link needs to go up, but the force speed is not supported,
2288 * Warn users and config the default available speeds.
2290 if (is_up && !(force_speed & avail_speed)) {
2291 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2292 phy_conf.link_speed = avail_speed;
2294 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2297 /* PHY type mask needs to include each type except PHY type extension */
2298 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2299 phy_type_mask |= 1 << cnt;
2301 /* use get_phy_abilities_resp value for the rest */
2302 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2303 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2304 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2305 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2306 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2307 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2308 phy_conf.eee_capability = phy_ab.eee_capability;
2309 phy_conf.eeer = phy_ab.eeer_val;
2310 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2312 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2313 phy_ab.abilities, phy_ab.link_speed);
2314 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2315 phy_conf.abilities, phy_conf.link_speed);
2317 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2321 return I40E_SUCCESS;
2325 i40e_apply_link_speed(struct rte_eth_dev *dev)
2328 uint8_t abilities = 0;
2329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330 struct rte_eth_conf *conf = &dev->data->dev_conf;
2332 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2333 I40E_AQ_PHY_LINK_ENABLED;
2335 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2336 conf->link_speeds = ETH_LINK_SPEED_40G |
2337 ETH_LINK_SPEED_25G |
2338 ETH_LINK_SPEED_20G |
2339 ETH_LINK_SPEED_10G |
2341 ETH_LINK_SPEED_100M;
2343 abilities |= I40E_AQ_PHY_AN_ENABLED;
2345 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2347 speed = i40e_parse_link_speeds(conf->link_speeds);
2349 return i40e_phy_conf_link(hw, abilities, speed, true);
2353 i40e_dev_start(struct rte_eth_dev *dev)
2355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357 struct i40e_vsi *main_vsi = pf->main_vsi;
2359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2361 uint32_t intr_vector = 0;
2362 struct i40e_vsi *vsi;
2363 uint16_t nb_rxq, nb_txq;
2365 hw->adapter_stopped = 0;
2367 rte_intr_disable(intr_handle);
2369 if ((rte_intr_cap_multiple(intr_handle) ||
2370 !RTE_ETH_DEV_SRIOV(dev).active) &&
2371 dev->data->dev_conf.intr_conf.rxq != 0) {
2372 intr_vector = dev->data->nb_rx_queues;
2373 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2378 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2379 intr_handle->intr_vec =
2380 rte_zmalloc("intr_vec",
2381 dev->data->nb_rx_queues * sizeof(int),
2383 if (!intr_handle->intr_vec) {
2385 "Failed to allocate %d rx_queues intr_vec",
2386 dev->data->nb_rx_queues);
2391 /* Initialize VSI */
2392 ret = i40e_dev_rxtx_init(pf);
2393 if (ret != I40E_SUCCESS) {
2394 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2398 /* Map queues with MSIX interrupt */
2399 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2400 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2401 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2404 i40e_vsi_enable_queues_intr(main_vsi);
2406 /* Map VMDQ VSI queues with MSIX interrupt */
2407 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2408 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2409 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2410 I40E_ITR_INDEX_DEFAULT);
2413 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2416 /* Enable all queues which have been configured */
2417 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2418 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2423 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2424 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2429 /* Enable receiving broadcast packets */
2430 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2431 if (ret != I40E_SUCCESS)
2432 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2434 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2435 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2437 if (ret != I40E_SUCCESS)
2438 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2441 /* Enable the VLAN promiscuous mode. */
2443 for (i = 0; i < pf->vf_num; i++) {
2444 vsi = pf->vfs[i].vsi;
2445 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2450 /* Enable mac loopback mode */
2451 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2452 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2453 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2454 if (ret != I40E_SUCCESS) {
2455 PMD_DRV_LOG(ERR, "fail to set loopback link");
2460 /* Apply link configure */
2461 ret = i40e_apply_link_speed(dev);
2462 if (I40E_SUCCESS != ret) {
2463 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2467 if (!rte_intr_allow_others(intr_handle)) {
2468 rte_intr_callback_unregister(intr_handle,
2469 i40e_dev_interrupt_handler,
2471 /* configure and enable device interrupt */
2472 i40e_pf_config_irq0(hw, FALSE);
2473 i40e_pf_enable_irq0(hw);
2475 if (dev->data->dev_conf.intr_conf.lsc != 0)
2477 "lsc won't enable because of no intr multiplex");
2479 ret = i40e_aq_set_phy_int_mask(hw,
2480 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2481 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2482 I40E_AQ_EVENT_MEDIA_NA), NULL);
2483 if (ret != I40E_SUCCESS)
2484 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2486 /* Call get_link_info aq commond to enable/disable LSE */
2487 i40e_dev_link_update(dev, 0);
2490 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2491 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2492 i40e_dev_alarm_handler, dev);
2494 /* enable uio intr after callback register */
2495 rte_intr_enable(intr_handle);
2498 i40e_filter_restore(pf);
2500 if (pf->tm_conf.root && !pf->tm_conf.committed)
2501 PMD_DRV_LOG(WARNING,
2502 "please call hierarchy_commit() "
2503 "before starting the port");
2505 return I40E_SUCCESS;
2508 for (i = 0; i < nb_txq; i++)
2509 i40e_dev_tx_queue_stop(dev, i);
2511 for (i = 0; i < nb_rxq; i++)
2512 i40e_dev_rx_queue_stop(dev, i);
2518 i40e_dev_stop(struct rte_eth_dev *dev)
2520 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2521 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 struct i40e_vsi *main_vsi = pf->main_vsi;
2523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2524 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2527 if (hw->adapter_stopped == 1)
2530 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2531 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2532 rte_intr_enable(intr_handle);
2535 /* Disable all queues */
2536 for (i = 0; i < dev->data->nb_tx_queues; i++)
2537 i40e_dev_tx_queue_stop(dev, i);
2539 for (i = 0; i < dev->data->nb_rx_queues; i++)
2540 i40e_dev_rx_queue_stop(dev, i);
2542 /* un-map queues with interrupt registers */
2543 i40e_vsi_disable_queues_intr(main_vsi);
2544 i40e_vsi_queues_unbind_intr(main_vsi);
2546 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2547 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2548 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2551 /* Clear all queues and release memory */
2552 i40e_dev_clear_queues(dev);
2555 i40e_dev_set_link_down(dev);
2557 if (!rte_intr_allow_others(intr_handle))
2558 /* resume to the default handler */
2559 rte_intr_callback_register(intr_handle,
2560 i40e_dev_interrupt_handler,
2563 /* Clean datapath event and queue/vec mapping */
2564 rte_intr_efd_disable(intr_handle);
2565 if (intr_handle->intr_vec) {
2566 rte_free(intr_handle->intr_vec);
2567 intr_handle->intr_vec = NULL;
2570 /* reset hierarchy commit */
2571 pf->tm_conf.committed = false;
2573 hw->adapter_stopped = 1;
2574 dev->data->dev_started = 0;
2576 pf->adapter->rss_reta_updated = 0;
2582 i40e_dev_close(struct rte_eth_dev *dev)
2584 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2585 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2588 struct i40e_filter_control_settings settings;
2589 struct rte_flow *p_flow;
2593 uint8_t aq_fail = 0;
2596 PMD_INIT_FUNC_TRACE();
2597 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2600 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2602 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2605 ret = i40e_dev_stop(dev);
2607 i40e_dev_free_queues(dev);
2609 /* Disable interrupt */
2610 i40e_pf_disable_irq0(hw);
2611 rte_intr_disable(intr_handle);
2614 * Only legacy filter API needs the following fdir config. So when the
2615 * legacy filter API is deprecated, the following code should also be
2618 i40e_fdir_teardown(pf);
2620 /* shutdown and destroy the HMC */
2621 i40e_shutdown_lan_hmc(hw);
2623 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2624 i40e_vsi_release(pf->vmdq[i].vsi);
2625 pf->vmdq[i].vsi = NULL;
2630 /* release all the existing VSIs and VEBs */
2631 i40e_vsi_release(pf->main_vsi);
2633 /* shutdown the adminq */
2634 i40e_aq_queue_shutdown(hw, true);
2635 i40e_shutdown_adminq(hw);
2637 i40e_res_pool_destroy(&pf->qp_pool);
2638 i40e_res_pool_destroy(&pf->msix_pool);
2640 /* Disable flexible payload in global configuration */
2641 if (!pf->support_multi_driver)
2642 i40e_flex_payload_reg_set_default(hw);
2644 /* force a PF reset to clean anything leftover */
2645 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2646 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2647 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2648 I40E_WRITE_FLUSH(hw);
2650 /* Clear PXE mode */
2651 i40e_clear_pxe_mode(hw);
2653 /* Unconfigure filter control */
2654 memset(&settings, 0, sizeof(settings));
2655 ret = i40e_set_filter_control(hw, &settings);
2657 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2660 /* Disable flow control */
2661 hw->fc.requested_mode = I40E_FC_NONE;
2662 i40e_set_fc(hw, &aq_fail, TRUE);
2664 /* uninitialize pf host driver */
2665 i40e_pf_host_uninit(dev);
2668 ret = rte_intr_callback_unregister(intr_handle,
2669 i40e_dev_interrupt_handler, dev);
2670 if (ret >= 0 || ret == -ENOENT) {
2672 } else if (ret != -EAGAIN) {
2674 "intr callback unregister failed: %d",
2677 i40e_msec_delay(500);
2678 } while (retries++ < 5);
2680 i40e_rm_ethtype_filter_list(pf);
2681 i40e_rm_tunnel_filter_list(pf);
2682 i40e_rm_fdir_filter_list(pf);
2684 /* Remove all flows */
2685 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2686 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2687 /* Do not free FDIR flows since they are static allocated */
2688 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2692 /* release the fdir static allocated memory */
2693 i40e_fdir_memory_cleanup(pf);
2695 /* Remove all Traffic Manager configuration */
2696 i40e_tm_conf_uninit(dev);
2698 i40e_clear_automask(pf);
2700 hw->adapter_closed = 1;
2705 * Reset PF device only to re-initialize resources in PMD layer
2708 i40e_dev_reset(struct rte_eth_dev *dev)
2712 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2713 * its VF to make them align with it. The detailed notification
2714 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2715 * To avoid unexpected behavior in VF, currently reset of PF with
2716 * SR-IOV activation is not supported. It might be supported later.
2718 if (dev->data->sriov.active)
2721 ret = eth_i40e_dev_uninit(dev);
2725 ret = eth_i40e_dev_init(dev, NULL);
2731 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2733 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735 struct i40e_vsi *vsi = pf->main_vsi;
2738 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2740 if (status != I40E_SUCCESS) {
2741 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2745 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2747 if (status != I40E_SUCCESS) {
2748 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2749 /* Rollback unicast promiscuous mode */
2750 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2759 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2762 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763 struct i40e_vsi *vsi = pf->main_vsi;
2766 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2768 if (status != I40E_SUCCESS) {
2769 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2773 /* must remain in all_multicast mode */
2774 if (dev->data->all_multicast == 1)
2777 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2779 if (status != I40E_SUCCESS) {
2780 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2781 /* Rollback unicast promiscuous mode */
2782 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2791 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2793 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2794 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 struct i40e_vsi *vsi = pf->main_vsi;
2798 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2799 if (ret != I40E_SUCCESS) {
2800 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2808 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2815 if (dev->data->promiscuous == 1)
2816 return 0; /* must remain in all_multicast mode */
2818 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2819 vsi->seid, FALSE, NULL);
2820 if (ret != I40E_SUCCESS) {
2821 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2829 * Set device link up.
2832 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2834 /* re-apply link speed setting */
2835 return i40e_apply_link_speed(dev);
2839 * Set device link down.
2842 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2844 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2845 uint8_t abilities = 0;
2846 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2849 return i40e_phy_conf_link(hw, abilities, speed, false);
2852 static __rte_always_inline void
2853 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2855 /* Link status registers and values*/
2856 #define I40E_REG_LINK_UP 0x40000080
2857 #define I40E_PRTMAC_MACC 0x001E24E0
2858 #define I40E_REG_MACC_25GB 0x00020000
2859 #define I40E_REG_SPEED_MASK 0x38000000
2860 #define I40E_REG_SPEED_0 0x00000000
2861 #define I40E_REG_SPEED_1 0x08000000
2862 #define I40E_REG_SPEED_2 0x10000000
2863 #define I40E_REG_SPEED_3 0x18000000
2864 #define I40E_REG_SPEED_4 0x20000000
2865 uint32_t link_speed;
2868 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA(0));
2869 link_speed = reg_val & I40E_REG_SPEED_MASK;
2870 reg_val &= I40E_REG_LINK_UP;
2871 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2873 if (unlikely(link->link_status == 0))
2876 /* Parse the link status */
2877 switch (link_speed) {
2878 case I40E_REG_SPEED_0:
2879 link->link_speed = ETH_SPEED_NUM_100M;
2881 case I40E_REG_SPEED_1:
2882 link->link_speed = ETH_SPEED_NUM_1G;
2884 case I40E_REG_SPEED_2:
2885 if (hw->mac.type == I40E_MAC_X722)
2886 link->link_speed = ETH_SPEED_NUM_2_5G;
2888 link->link_speed = ETH_SPEED_NUM_10G;
2890 case I40E_REG_SPEED_3:
2891 if (hw->mac.type == I40E_MAC_X722) {
2892 link->link_speed = ETH_SPEED_NUM_5G;
2894 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2896 if (reg_val & I40E_REG_MACC_25GB)
2897 link->link_speed = ETH_SPEED_NUM_25G;
2899 link->link_speed = ETH_SPEED_NUM_40G;
2902 case I40E_REG_SPEED_4:
2903 if (hw->mac.type == I40E_MAC_X722)
2904 link->link_speed = ETH_SPEED_NUM_10G;
2906 link->link_speed = ETH_SPEED_NUM_20G;
2909 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2914 static __rte_always_inline void
2915 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2916 bool enable_lse, int wait_to_complete)
2918 #define CHECK_INTERVAL 100 /* 100ms */
2919 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2920 uint32_t rep_cnt = MAX_REPEAT_TIME;
2921 struct i40e_link_status link_status;
2924 memset(&link_status, 0, sizeof(link_status));
2927 memset(&link_status, 0, sizeof(link_status));
2929 /* Get link status information from hardware */
2930 status = i40e_aq_get_link_info(hw, enable_lse,
2931 &link_status, NULL);
2932 if (unlikely(status != I40E_SUCCESS)) {
2933 link->link_speed = ETH_SPEED_NUM_NONE;
2934 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2935 PMD_DRV_LOG(ERR, "Failed to get link info");
2939 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2940 if (!wait_to_complete || link->link_status)
2943 rte_delay_ms(CHECK_INTERVAL);
2944 } while (--rep_cnt);
2946 /* Parse the link status */
2947 switch (link_status.link_speed) {
2948 case I40E_LINK_SPEED_100MB:
2949 link->link_speed = ETH_SPEED_NUM_100M;
2951 case I40E_LINK_SPEED_1GB:
2952 link->link_speed = ETH_SPEED_NUM_1G;
2954 case I40E_LINK_SPEED_10GB:
2955 link->link_speed = ETH_SPEED_NUM_10G;
2957 case I40E_LINK_SPEED_20GB:
2958 link->link_speed = ETH_SPEED_NUM_20G;
2960 case I40E_LINK_SPEED_25GB:
2961 link->link_speed = ETH_SPEED_NUM_25G;
2963 case I40E_LINK_SPEED_40GB:
2964 link->link_speed = ETH_SPEED_NUM_40G;
2967 if (link->link_status)
2968 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2970 link->link_speed = ETH_SPEED_NUM_NONE;
2976 i40e_dev_link_update(struct rte_eth_dev *dev,
2977 int wait_to_complete)
2979 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980 struct rte_eth_link link;
2981 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2984 memset(&link, 0, sizeof(link));
2986 /* i40e uses full duplex only */
2987 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2988 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2989 ETH_LINK_SPEED_FIXED);
2991 if (!wait_to_complete && !enable_lse)
2992 update_link_reg(hw, &link);
2994 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2997 rte_eth_linkstatus_get(hw->switch_dev, &link);
2999 ret = rte_eth_linkstatus_set(dev, &link);
3000 i40e_notify_all_vfs_link_status(dev);
3006 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3007 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3008 uint64_t *stat, uint64_t *prev_stat)
3010 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3011 /* enlarge the limitation when statistics counters overflowed */
3012 if (offset_loaded) {
3013 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3014 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3015 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3020 /* Get all the statistics of a VSI */
3022 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3024 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3025 struct i40e_eth_stats *nes = &vsi->eth_stats;
3026 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3027 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3029 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3030 vsi->offset_loaded, &oes->rx_bytes,
3031 &nes->rx_bytes, &vsi->prev_rx_bytes);
3032 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3033 vsi->offset_loaded, &oes->rx_unicast,
3035 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3036 vsi->offset_loaded, &oes->rx_multicast,
3037 &nes->rx_multicast);
3038 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3039 vsi->offset_loaded, &oes->rx_broadcast,
3040 &nes->rx_broadcast);
3041 /* exclude CRC bytes */
3042 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3043 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3045 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3046 &oes->rx_discards, &nes->rx_discards);
3047 /* GLV_REPC not supported */
3048 /* GLV_RMPC not supported */
3049 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3050 &oes->rx_unknown_protocol,
3051 &nes->rx_unknown_protocol);
3052 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3053 vsi->offset_loaded, &oes->tx_bytes,
3054 &nes->tx_bytes, &vsi->prev_tx_bytes);
3055 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3056 vsi->offset_loaded, &oes->tx_unicast,
3058 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3059 vsi->offset_loaded, &oes->tx_multicast,
3060 &nes->tx_multicast);
3061 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3062 vsi->offset_loaded, &oes->tx_broadcast,
3063 &nes->tx_broadcast);
3064 /* GLV_TDPC not supported */
3065 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3066 &oes->tx_errors, &nes->tx_errors);
3067 vsi->offset_loaded = true;
3069 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3071 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3072 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3073 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3074 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3075 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3076 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3077 nes->rx_unknown_protocol);
3078 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3079 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3080 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3081 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3082 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3083 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3084 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3089 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3092 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3093 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3095 /* Get rx/tx bytes of internal transfer packets */
3096 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3097 I40E_GLV_GORCL(hw->port),
3099 &pf->internal_stats_offset.rx_bytes,
3100 &pf->internal_stats.rx_bytes,
3101 &pf->internal_prev_rx_bytes);
3102 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3103 I40E_GLV_GOTCL(hw->port),
3105 &pf->internal_stats_offset.tx_bytes,
3106 &pf->internal_stats.tx_bytes,
3107 &pf->internal_prev_tx_bytes);
3108 /* Get total internal rx packet count */
3109 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3110 I40E_GLV_UPRCL(hw->port),
3112 &pf->internal_stats_offset.rx_unicast,
3113 &pf->internal_stats.rx_unicast);
3114 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3115 I40E_GLV_MPRCL(hw->port),
3117 &pf->internal_stats_offset.rx_multicast,
3118 &pf->internal_stats.rx_multicast);
3119 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3120 I40E_GLV_BPRCL(hw->port),
3122 &pf->internal_stats_offset.rx_broadcast,
3123 &pf->internal_stats.rx_broadcast);
3124 /* Get total internal tx packet count */
3125 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3126 I40E_GLV_UPTCL(hw->port),
3128 &pf->internal_stats_offset.tx_unicast,
3129 &pf->internal_stats.tx_unicast);
3130 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3131 I40E_GLV_MPTCL(hw->port),
3133 &pf->internal_stats_offset.tx_multicast,
3134 &pf->internal_stats.tx_multicast);
3135 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3136 I40E_GLV_BPTCL(hw->port),
3138 &pf->internal_stats_offset.tx_broadcast,
3139 &pf->internal_stats.tx_broadcast);
3141 /* exclude CRC size */
3142 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3143 pf->internal_stats.rx_multicast +
3144 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3146 /* Get statistics of struct i40e_eth_stats */
3147 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3148 I40E_GLPRT_GORCL(hw->port),
3149 pf->offset_loaded, &os->eth.rx_bytes,
3150 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3151 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3152 I40E_GLPRT_UPRCL(hw->port),
3153 pf->offset_loaded, &os->eth.rx_unicast,
3154 &ns->eth.rx_unicast);
3155 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3156 I40E_GLPRT_MPRCL(hw->port),
3157 pf->offset_loaded, &os->eth.rx_multicast,
3158 &ns->eth.rx_multicast);
3159 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3160 I40E_GLPRT_BPRCL(hw->port),
3161 pf->offset_loaded, &os->eth.rx_broadcast,
3162 &ns->eth.rx_broadcast);
3163 /* Workaround: CRC size should not be included in byte statistics,
3164 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3167 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3168 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3170 /* exclude internal rx bytes
3171 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3172 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3174 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3176 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3177 ns->eth.rx_bytes = 0;
3179 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3181 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3182 ns->eth.rx_unicast = 0;
3184 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3186 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3187 ns->eth.rx_multicast = 0;
3189 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3191 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3192 ns->eth.rx_broadcast = 0;
3194 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3196 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3197 pf->offset_loaded, &os->eth.rx_discards,
3198 &ns->eth.rx_discards);
3199 /* GLPRT_REPC not supported */
3200 /* GLPRT_RMPC not supported */
3201 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3203 &os->eth.rx_unknown_protocol,
3204 &ns->eth.rx_unknown_protocol);
3205 i40e_stat_update_48(hw, I40E_GL_RXERR1_H(hw->pf_id + I40E_MAX_VF),
3206 I40E_GL_RXERR1_L(hw->pf_id + I40E_MAX_VF),
3207 pf->offset_loaded, &pf->rx_err1_offset,
3209 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3210 I40E_GLPRT_GOTCL(hw->port),
3211 pf->offset_loaded, &os->eth.tx_bytes,
3212 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3213 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3214 I40E_GLPRT_UPTCL(hw->port),
3215 pf->offset_loaded, &os->eth.tx_unicast,
3216 &ns->eth.tx_unicast);
3217 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3218 I40E_GLPRT_MPTCL(hw->port),
3219 pf->offset_loaded, &os->eth.tx_multicast,
3220 &ns->eth.tx_multicast);
3221 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3222 I40E_GLPRT_BPTCL(hw->port),
3223 pf->offset_loaded, &os->eth.tx_broadcast,
3224 &ns->eth.tx_broadcast);
3225 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3226 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3228 /* exclude internal tx bytes
3229 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3230 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3232 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3234 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3235 ns->eth.tx_bytes = 0;
3237 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3239 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3240 ns->eth.tx_unicast = 0;
3242 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3244 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3245 ns->eth.tx_multicast = 0;
3247 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3249 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3250 ns->eth.tx_broadcast = 0;
3252 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3254 /* GLPRT_TEPC not supported */
3256 /* additional port specific stats */
3257 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3258 pf->offset_loaded, &os->tx_dropped_link_down,
3259 &ns->tx_dropped_link_down);
3260 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3261 pf->offset_loaded, &os->crc_errors,
3263 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3264 pf->offset_loaded, &os->illegal_bytes,
3265 &ns->illegal_bytes);
3266 /* GLPRT_ERRBC not supported */
3267 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3268 pf->offset_loaded, &os->mac_local_faults,
3269 &ns->mac_local_faults);
3270 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3271 pf->offset_loaded, &os->mac_remote_faults,
3272 &ns->mac_remote_faults);
3273 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3274 pf->offset_loaded, &os->rx_length_errors,
3275 &ns->rx_length_errors);
3276 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3277 pf->offset_loaded, &os->link_xon_rx,
3279 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3280 pf->offset_loaded, &os->link_xoff_rx,
3282 for (i = 0; i < 8; i++) {
3283 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3285 &os->priority_xon_rx[i],
3286 &ns->priority_xon_rx[i]);
3287 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3289 &os->priority_xoff_rx[i],
3290 &ns->priority_xoff_rx[i]);
3292 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3293 pf->offset_loaded, &os->link_xon_tx,
3295 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3296 pf->offset_loaded, &os->link_xoff_tx,
3298 for (i = 0; i < 8; i++) {
3299 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3301 &os->priority_xon_tx[i],
3302 &ns->priority_xon_tx[i]);
3303 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3305 &os->priority_xoff_tx[i],
3306 &ns->priority_xoff_tx[i]);
3307 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3309 &os->priority_xon_2_xoff[i],
3310 &ns->priority_xon_2_xoff[i]);
3312 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3313 I40E_GLPRT_PRC64L(hw->port),
3314 pf->offset_loaded, &os->rx_size_64,
3316 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3317 I40E_GLPRT_PRC127L(hw->port),
3318 pf->offset_loaded, &os->rx_size_127,
3320 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3321 I40E_GLPRT_PRC255L(hw->port),
3322 pf->offset_loaded, &os->rx_size_255,
3324 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3325 I40E_GLPRT_PRC511L(hw->port),
3326 pf->offset_loaded, &os->rx_size_511,
3328 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3329 I40E_GLPRT_PRC1023L(hw->port),
3330 pf->offset_loaded, &os->rx_size_1023,
3332 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3333 I40E_GLPRT_PRC1522L(hw->port),
3334 pf->offset_loaded, &os->rx_size_1522,
3336 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3337 I40E_GLPRT_PRC9522L(hw->port),
3338 pf->offset_loaded, &os->rx_size_big,
3340 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3341 pf->offset_loaded, &os->rx_undersize,
3343 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3344 pf->offset_loaded, &os->rx_fragments,
3346 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3347 pf->offset_loaded, &os->rx_oversize,
3349 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3350 pf->offset_loaded, &os->rx_jabber,
3352 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3353 I40E_GLPRT_PTC64L(hw->port),
3354 pf->offset_loaded, &os->tx_size_64,
3356 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3357 I40E_GLPRT_PTC127L(hw->port),
3358 pf->offset_loaded, &os->tx_size_127,
3360 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3361 I40E_GLPRT_PTC255L(hw->port),
3362 pf->offset_loaded, &os->tx_size_255,
3364 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3365 I40E_GLPRT_PTC511L(hw->port),
3366 pf->offset_loaded, &os->tx_size_511,
3368 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3369 I40E_GLPRT_PTC1023L(hw->port),
3370 pf->offset_loaded, &os->tx_size_1023,
3372 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3373 I40E_GLPRT_PTC1522L(hw->port),
3374 pf->offset_loaded, &os->tx_size_1522,
3376 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3377 I40E_GLPRT_PTC9522L(hw->port),
3378 pf->offset_loaded, &os->tx_size_big,
3380 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3382 &os->fd_sb_match, &ns->fd_sb_match);
3383 /* GLPRT_MSPDC not supported */
3384 /* GLPRT_XEC not supported */
3386 pf->offset_loaded = true;
3389 i40e_update_vsi_stats(pf->main_vsi);
3392 /* Get all statistics of a port */
3394 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3399 struct i40e_vsi *vsi;
3402 /* call read registers - updates values, now write them to struct */
3403 i40e_read_stats_registers(pf, hw);
3405 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3406 pf->main_vsi->eth_stats.rx_multicast +
3407 pf->main_vsi->eth_stats.rx_broadcast -
3408 pf->main_vsi->eth_stats.rx_discards -
3410 stats->opackets = ns->eth.tx_unicast +
3411 ns->eth.tx_multicast +
3412 ns->eth.tx_broadcast;
3413 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3414 stats->obytes = ns->eth.tx_bytes;
3415 stats->oerrors = ns->eth.tx_errors +
3416 pf->main_vsi->eth_stats.tx_errors;
3419 stats->imissed = ns->eth.rx_discards +
3420 pf->main_vsi->eth_stats.rx_discards;
3421 stats->ierrors = ns->crc_errors +
3422 ns->rx_length_errors + ns->rx_undersize +
3423 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
3427 for (i = 0; i < pf->vf_num; i++) {
3428 vsi = pf->vfs[i].vsi;
3429 i40e_update_vsi_stats(vsi);
3431 stats->ipackets += (vsi->eth_stats.rx_unicast +
3432 vsi->eth_stats.rx_multicast +
3433 vsi->eth_stats.rx_broadcast -
3434 vsi->eth_stats.rx_discards);
3435 stats->ibytes += vsi->eth_stats.rx_bytes;
3436 stats->oerrors += vsi->eth_stats.tx_errors;
3437 stats->imissed += vsi->eth_stats.rx_discards;
3441 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3442 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3443 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3444 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3445 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3446 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3447 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3448 ns->eth.rx_unknown_protocol);
3449 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3450 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3451 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3452 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3453 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3454 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3456 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3457 ns->tx_dropped_link_down);
3458 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3459 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3461 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3462 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3463 ns->mac_local_faults);
3464 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3465 ns->mac_remote_faults);
3466 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3467 ns->rx_length_errors);
3468 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3469 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3470 for (i = 0; i < 8; i++) {
3471 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3472 i, ns->priority_xon_rx[i]);
3473 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3474 i, ns->priority_xoff_rx[i]);
3476 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3477 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3478 for (i = 0; i < 8; i++) {
3479 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3480 i, ns->priority_xon_tx[i]);
3481 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3482 i, ns->priority_xoff_tx[i]);
3483 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3484 i, ns->priority_xon_2_xoff[i]);
3486 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3487 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3488 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3489 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3490 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3491 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3492 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3493 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3494 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3495 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3496 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3497 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3498 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3499 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3500 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3501 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3502 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3503 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3504 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3505 ns->mac_short_packet_dropped);
3506 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3507 ns->checksum_error);
3508 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3509 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3513 /* Reset the statistics */
3515 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3517 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520 /* Mark PF and VSI stats to update the offset, aka "reset" */
3521 pf->offset_loaded = false;
3523 pf->main_vsi->offset_loaded = false;
3525 /* read the stats, reading current register values into offset */
3526 i40e_read_stats_registers(pf, hw);
3532 i40e_xstats_calc_num(void)
3534 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3535 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3536 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3539 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3540 struct rte_eth_xstat_name *xstats_names,
3541 __rte_unused unsigned limit)
3546 if (xstats_names == NULL)
3547 return i40e_xstats_calc_num();
3549 /* Note: limit checked in rte_eth_xstats_names() */
3551 /* Get stats from i40e_eth_stats struct */
3552 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3553 strlcpy(xstats_names[count].name,
3554 rte_i40e_stats_strings[i].name,
3555 sizeof(xstats_names[count].name));
3559 /* Get individiual stats from i40e_hw_port struct */
3560 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3561 strlcpy(xstats_names[count].name,
3562 rte_i40e_hw_port_strings[i].name,
3563 sizeof(xstats_names[count].name));
3567 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3568 for (prio = 0; prio < 8; prio++) {
3569 snprintf(xstats_names[count].name,
3570 sizeof(xstats_names[count].name),
3571 "rx_priority%u_%s", prio,
3572 rte_i40e_rxq_prio_strings[i].name);
3577 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3578 for (prio = 0; prio < 8; prio++) {
3579 snprintf(xstats_names[count].name,
3580 sizeof(xstats_names[count].name),
3581 "tx_priority%u_%s", prio,
3582 rte_i40e_txq_prio_strings[i].name);
3590 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3593 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 unsigned i, count, prio;
3596 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3598 count = i40e_xstats_calc_num();
3602 i40e_read_stats_registers(pf, hw);
3609 /* Get stats from i40e_eth_stats struct */
3610 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3611 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3612 rte_i40e_stats_strings[i].offset);
3613 xstats[count].id = count;
3617 /* Get individiual stats from i40e_hw_port struct */
3618 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3619 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3620 rte_i40e_hw_port_strings[i].offset);
3621 xstats[count].id = count;
3625 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3626 for (prio = 0; prio < 8; prio++) {
3627 xstats[count].value =
3628 *(uint64_t *)(((char *)hw_stats) +
3629 rte_i40e_rxq_prio_strings[i].offset +
3630 (sizeof(uint64_t) * prio));
3631 xstats[count].id = count;
3636 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3637 for (prio = 0; prio < 8; prio++) {
3638 xstats[count].value =
3639 *(uint64_t *)(((char *)hw_stats) +
3640 rte_i40e_txq_prio_strings[i].offset +
3641 (sizeof(uint64_t) * prio));
3642 xstats[count].id = count;
3651 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659 full_ver = hw->nvm.oem_ver;
3660 ver = (u8)(full_ver >> 24);
3661 build = (u16)((full_ver >> 8) & 0xffff);
3662 patch = (u8)(full_ver & 0xff);
3664 ret = snprintf(fw_version, fw_size,
3665 "%d.%d%d 0x%08x %d.%d.%d",
3666 ((hw->nvm.version >> 12) & 0xf),
3667 ((hw->nvm.version >> 4) & 0xff),
3668 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3673 ret += 1; /* add the size of '\0' */
3674 if (fw_size < (size_t)ret)
3681 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3682 * the Rx data path does not hang if the FW LLDP is stopped.
3683 * return true if lldp need to stop
3684 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3687 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3690 char ver_str[64] = {0};
3691 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693 i40e_fw_version_get(dev, ver_str, 64);
3694 nvm_ver = atof(ver_str);
3695 if ((hw->mac.type == I40E_MAC_X722 ||
3696 hw->mac.type == I40E_MAC_X722_VF) &&
3697 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3699 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3706 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710 struct i40e_vsi *vsi = pf->main_vsi;
3711 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3713 dev_info->max_rx_queues = vsi->nb_qps;
3714 dev_info->max_tx_queues = vsi->nb_qps;
3715 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3716 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3717 dev_info->max_mac_addrs = vsi->max_macaddrs;
3718 dev_info->max_vfs = pci_dev->max_vfs;
3719 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3720 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3721 dev_info->rx_queue_offload_capa = 0;
3722 dev_info->rx_offload_capa =
3723 DEV_RX_OFFLOAD_VLAN_STRIP |
3724 DEV_RX_OFFLOAD_QINQ_STRIP |
3725 DEV_RX_OFFLOAD_IPV4_CKSUM |
3726 DEV_RX_OFFLOAD_UDP_CKSUM |
3727 DEV_RX_OFFLOAD_TCP_CKSUM |
3728 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3729 DEV_RX_OFFLOAD_KEEP_CRC |
3730 DEV_RX_OFFLOAD_SCATTER |
3731 DEV_RX_OFFLOAD_VLAN_EXTEND |
3732 DEV_RX_OFFLOAD_VLAN_FILTER |
3733 DEV_RX_OFFLOAD_RSS_HASH;
3735 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3736 dev_info->tx_offload_capa =
3737 DEV_TX_OFFLOAD_VLAN_INSERT |
3738 DEV_TX_OFFLOAD_QINQ_INSERT |
3739 DEV_TX_OFFLOAD_IPV4_CKSUM |
3740 DEV_TX_OFFLOAD_UDP_CKSUM |
3741 DEV_TX_OFFLOAD_TCP_CKSUM |
3742 DEV_TX_OFFLOAD_SCTP_CKSUM |
3743 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3744 DEV_TX_OFFLOAD_TCP_TSO |
3745 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3746 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3747 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3748 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3749 DEV_TX_OFFLOAD_MULTI_SEGS |
3750 dev_info->tx_queue_offload_capa;
3751 dev_info->dev_capa =
3752 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3753 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3755 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3757 dev_info->reta_size = pf->hash_lut_size;
3758 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3760 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3762 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3763 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3764 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3766 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3771 dev_info->default_txconf = (struct rte_eth_txconf) {
3773 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3774 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3775 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3777 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3778 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3782 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3783 .nb_max = I40E_MAX_RING_DESC,
3784 .nb_min = I40E_MIN_RING_DESC,
3785 .nb_align = I40E_ALIGN_RING_DESC,
3788 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3789 .nb_max = I40E_MAX_RING_DESC,
3790 .nb_min = I40E_MIN_RING_DESC,
3791 .nb_align = I40E_ALIGN_RING_DESC,
3792 .nb_seg_max = I40E_TX_MAX_SEG,
3793 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3796 if (pf->flags & I40E_FLAG_VMDQ) {
3797 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3798 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3799 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3800 pf->max_nb_vmdq_vsi;
3801 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3802 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3803 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3806 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3808 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3809 dev_info->default_rxportconf.nb_queues = 2;
3810 dev_info->default_txportconf.nb_queues = 2;
3811 if (dev->data->nb_rx_queues == 1)
3812 dev_info->default_rxportconf.ring_size = 2048;
3814 dev_info->default_rxportconf.ring_size = 1024;
3815 if (dev->data->nb_tx_queues == 1)
3816 dev_info->default_txportconf.ring_size = 1024;
3818 dev_info->default_txportconf.ring_size = 512;
3820 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3822 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3823 dev_info->default_rxportconf.nb_queues = 1;
3824 dev_info->default_txportconf.nb_queues = 1;
3825 dev_info->default_rxportconf.ring_size = 256;
3826 dev_info->default_txportconf.ring_size = 256;
3829 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3830 dev_info->default_rxportconf.nb_queues = 1;
3831 dev_info->default_txportconf.nb_queues = 1;
3832 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3833 dev_info->default_rxportconf.ring_size = 512;
3834 dev_info->default_txportconf.ring_size = 256;
3836 dev_info->default_rxportconf.ring_size = 256;
3837 dev_info->default_txportconf.ring_size = 256;
3840 dev_info->default_rxportconf.burst_size = 32;
3841 dev_info->default_txportconf.burst_size = 32;
3847 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3850 struct i40e_vsi *vsi = pf->main_vsi;
3851 PMD_INIT_FUNC_TRACE();
3854 return i40e_vsi_add_vlan(vsi, vlan_id);
3856 return i40e_vsi_delete_vlan(vsi, vlan_id);
3860 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3861 enum rte_vlan_type vlan_type,
3862 uint16_t tpid, int qinq)
3864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867 uint16_t reg_id = 3;
3871 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3875 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3877 if (ret != I40E_SUCCESS) {
3879 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3884 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3887 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3888 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3889 if (reg_r == reg_w) {
3890 PMD_DRV_LOG(DEBUG, "No need to write");
3894 ret = i40e_aq_debug_write_global_register(hw,
3895 I40E_GL_SWT_L2TAGCTRL(reg_id),
3897 if (ret != I40E_SUCCESS) {
3899 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3904 "Global register 0x%08x is changed with value 0x%08x",
3905 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3911 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3912 enum rte_vlan_type vlan_type,
3915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3917 int qinq = dev->data->dev_conf.rxmode.offloads &
3918 DEV_RX_OFFLOAD_VLAN_EXTEND;
3921 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3922 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3923 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3925 "Unsupported vlan type.");
3929 if (pf->support_multi_driver) {
3930 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3934 /* 802.1ad frames ability is added in NVM API 1.7*/
3935 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3937 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3938 hw->first_tag = rte_cpu_to_le_16(tpid);
3939 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3940 hw->second_tag = rte_cpu_to_le_16(tpid);
3942 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3943 hw->second_tag = rte_cpu_to_le_16(tpid);
3945 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3946 if (ret != I40E_SUCCESS) {
3948 "Set switch config failed aq_err: %d",
3949 hw->aq.asq_last_status);
3953 /* If NVM API < 1.7, keep the register setting */
3954 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3960 /* Configure outer vlan stripping on or off in QinQ mode */
3962 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3964 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3965 int ret = I40E_SUCCESS;
3968 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3969 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3973 /* Configure for outer VLAN RX stripping */
3974 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
3977 reg |= I40E_VSI_TSR_QINQ_STRIP;
3979 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
3981 ret = i40e_aq_debug_write_register(hw,
3982 I40E_VSI_TSR(vsi->vsi_id),
3985 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
3987 return I40E_ERR_CONFIG;
3994 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3997 struct i40e_vsi *vsi = pf->main_vsi;
3998 struct rte_eth_rxmode *rxmode;
4000 rxmode = &dev->data->dev_conf.rxmode;
4001 if (mask & ETH_VLAN_FILTER_MASK) {
4002 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4003 i40e_vsi_config_vlan_filter(vsi, TRUE);
4005 i40e_vsi_config_vlan_filter(vsi, FALSE);
4008 if (mask & ETH_VLAN_STRIP_MASK) {
4009 /* Enable or disable VLAN stripping */
4010 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4011 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4013 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4016 if (mask & ETH_VLAN_EXTEND_MASK) {
4017 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4018 i40e_vsi_config_double_vlan(vsi, TRUE);
4019 /* Set global registers with default ethertype. */
4020 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4021 RTE_ETHER_TYPE_VLAN);
4022 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4023 RTE_ETHER_TYPE_VLAN);
4026 i40e_vsi_config_double_vlan(vsi, FALSE);
4029 if (mask & ETH_QINQ_STRIP_MASK) {
4030 /* Enable or disable outer VLAN stripping */
4031 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4032 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4034 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4041 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4042 __rte_unused uint16_t queue,
4043 __rte_unused int on)
4045 PMD_INIT_FUNC_TRACE();
4049 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4051 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4052 struct i40e_vsi *vsi = pf->main_vsi;
4053 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4054 struct i40e_vsi_vlan_pvid_info info;
4056 memset(&info, 0, sizeof(info));
4059 info.config.pvid = pvid;
4061 info.config.reject.tagged =
4062 data->dev_conf.txmode.hw_vlan_reject_tagged;
4063 info.config.reject.untagged =
4064 data->dev_conf.txmode.hw_vlan_reject_untagged;
4067 return i40e_vsi_vlan_pvid_set(vsi, &info);
4071 i40e_dev_led_on(struct rte_eth_dev *dev)
4073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074 uint32_t mode = i40e_led_get(hw);
4077 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4083 i40e_dev_led_off(struct rte_eth_dev *dev)
4085 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086 uint32_t mode = i40e_led_get(hw);
4089 i40e_led_set(hw, 0, false);
4095 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4100 fc_conf->pause_time = pf->fc_conf.pause_time;
4102 /* read out from register, in case they are modified by other port */
4103 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4104 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4105 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4106 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4108 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4109 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4111 /* Return current mode according to actual setting*/
4112 switch (hw->fc.current_mode) {
4114 fc_conf->mode = RTE_FC_FULL;
4116 case I40E_FC_TX_PAUSE:
4117 fc_conf->mode = RTE_FC_TX_PAUSE;
4119 case I40E_FC_RX_PAUSE:
4120 fc_conf->mode = RTE_FC_RX_PAUSE;
4124 fc_conf->mode = RTE_FC_NONE;
4131 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4133 uint32_t mflcn_reg, fctrl_reg, reg;
4134 uint32_t max_high_water;
4135 uint8_t i, aq_failure;
4139 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4140 [RTE_FC_NONE] = I40E_FC_NONE,
4141 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4142 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4143 [RTE_FC_FULL] = I40E_FC_FULL
4146 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4148 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4149 if ((fc_conf->high_water > max_high_water) ||
4150 (fc_conf->high_water < fc_conf->low_water)) {
4152 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4157 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4158 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4159 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4161 pf->fc_conf.pause_time = fc_conf->pause_time;
4162 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4163 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4165 PMD_INIT_FUNC_TRACE();
4167 /* All the link flow control related enable/disable register
4168 * configuration is handle by the F/W
4170 err = i40e_set_fc(hw, &aq_failure, true);
4174 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4175 /* Configure flow control refresh threshold,
4176 * the value for stat_tx_pause_refresh_timer[8]
4177 * is used for global pause operation.
4181 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4182 pf->fc_conf.pause_time);
4184 /* configure the timer value included in transmitted pause
4186 * the value for stat_tx_pause_quanta[8] is used for global
4189 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4190 pf->fc_conf.pause_time);
4192 fctrl_reg = I40E_READ_REG(hw,
4193 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4195 if (fc_conf->mac_ctrl_frame_fwd != 0)
4196 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4198 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4200 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4203 /* Configure pause time (2 TCs per register) */
4204 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4205 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4206 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4208 /* Configure flow control refresh threshold value */
4209 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4210 pf->fc_conf.pause_time / 2);
4212 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4214 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4215 *depending on configuration
4217 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4218 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4219 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4221 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4222 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4225 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4228 if (!pf->support_multi_driver) {
4229 /* config water marker both based on the packets and bytes */
4230 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4231 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4232 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4233 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4234 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4235 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4236 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4237 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4239 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4240 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4244 "Water marker configuration is not supported.");
4247 I40E_WRITE_FLUSH(hw);
4253 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4254 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4256 PMD_INIT_FUNC_TRACE();
4261 /* Add a MAC address, and update filters */
4263 i40e_macaddr_add(struct rte_eth_dev *dev,
4264 struct rte_ether_addr *mac_addr,
4265 __rte_unused uint32_t index,
4268 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4269 struct i40e_mac_filter_info mac_filter;
4270 struct i40e_vsi *vsi;
4271 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4274 /* If VMDQ not enabled or configured, return */
4275 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4276 !pf->nb_cfg_vmdq_vsi)) {
4277 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4278 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4283 if (pool > pf->nb_cfg_vmdq_vsi) {
4284 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4285 pool, pf->nb_cfg_vmdq_vsi);
4289 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4290 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4291 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4293 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4298 vsi = pf->vmdq[pool - 1].vsi;
4300 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4301 if (ret != I40E_SUCCESS) {
4302 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4308 /* Remove a MAC address, and update filters */
4310 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4312 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4313 struct i40e_vsi *vsi;
4314 struct rte_eth_dev_data *data = dev->data;
4315 struct rte_ether_addr *macaddr;
4320 macaddr = &(data->mac_addrs[index]);
4322 pool_sel = dev->data->mac_pool_sel[index];
4324 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4325 if (pool_sel & (1ULL << i)) {
4329 /* No VMDQ pool enabled or configured */
4330 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4331 (i > pf->nb_cfg_vmdq_vsi)) {
4333 "No VMDQ pool enabled/configured");
4336 vsi = pf->vmdq[i - 1].vsi;
4338 ret = i40e_vsi_delete_mac(vsi, macaddr);
4341 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4349 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4351 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4352 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4359 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4360 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4361 vsi->type != I40E_VSI_SRIOV,
4364 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4368 uint32_t *lut_dw = (uint32_t *)lut;
4369 uint16_t i, lut_size_dw = lut_size / 4;
4371 if (vsi->type == I40E_VSI_SRIOV) {
4372 for (i = 0; i <= lut_size_dw; i++) {
4373 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4374 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4377 for (i = 0; i < lut_size_dw; i++)
4378 lut_dw[i] = I40E_READ_REG(hw,
4387 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4395 pf = I40E_VSI_TO_PF(vsi);
4396 hw = I40E_VSI_TO_HW(vsi);
4398 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4399 enum i40e_status_code status;
4401 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4402 vsi->type != I40E_VSI_SRIOV,
4406 "Failed to update RSS lookup table, error status: %d",
4411 uint32_t *lut_dw = (uint32_t *)lut;
4412 uint16_t i, lut_size_dw = lut_size / 4;
4414 if (vsi->type == I40E_VSI_SRIOV) {
4415 for (i = 0; i < lut_size_dw; i++)
4418 I40E_VFQF_HLUT1(i, vsi->user_param),
4421 for (i = 0; i < lut_size_dw; i++)
4422 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4425 I40E_WRITE_FLUSH(hw);
4432 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4433 struct rte_eth_rss_reta_entry64 *reta_conf,
4436 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4437 uint16_t i, lut_size = pf->hash_lut_size;
4438 uint16_t idx, shift;
4442 if (reta_size != lut_size ||
4443 reta_size > ETH_RSS_RETA_SIZE_512) {
4445 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4446 reta_size, lut_size);
4450 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4452 PMD_DRV_LOG(ERR, "No memory can be allocated");
4455 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4458 for (i = 0; i < reta_size; i++) {
4459 idx = i / RTE_RETA_GROUP_SIZE;
4460 shift = i % RTE_RETA_GROUP_SIZE;
4461 if (reta_conf[idx].mask & (1ULL << shift))
4462 lut[i] = reta_conf[idx].reta[shift];
4464 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4466 pf->adapter->rss_reta_updated = 1;
4475 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4476 struct rte_eth_rss_reta_entry64 *reta_conf,
4479 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4480 uint16_t i, lut_size = pf->hash_lut_size;
4481 uint16_t idx, shift;
4485 if (reta_size != lut_size ||
4486 reta_size > ETH_RSS_RETA_SIZE_512) {
4488 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4489 reta_size, lut_size);
4493 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4495 PMD_DRV_LOG(ERR, "No memory can be allocated");
4499 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4502 for (i = 0; i < reta_size; i++) {
4503 idx = i / RTE_RETA_GROUP_SIZE;
4504 shift = i % RTE_RETA_GROUP_SIZE;
4505 if (reta_conf[idx].mask & (1ULL << shift))
4506 reta_conf[idx].reta[shift] = lut[i];
4516 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4517 * @hw: pointer to the HW structure
4518 * @mem: pointer to mem struct to fill out
4519 * @size: size of memory requested
4520 * @alignment: what to align the allocation to
4522 enum i40e_status_code
4523 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4524 struct i40e_dma_mem *mem,
4528 static uint64_t i40e_dma_memzone_id;
4529 const struct rte_memzone *mz = NULL;
4530 char z_name[RTE_MEMZONE_NAMESIZE];
4533 return I40E_ERR_PARAM;
4535 snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
4536 __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
4537 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4538 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4540 return I40E_ERR_NO_MEMORY;
4545 mem->zone = (const void *)mz;
4547 "memzone %s allocated with physical address: %"PRIu64,
4550 return I40E_SUCCESS;
4554 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4555 * @hw: pointer to the HW structure
4556 * @mem: ptr to mem struct to free
4558 enum i40e_status_code
4559 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4560 struct i40e_dma_mem *mem)
4563 return I40E_ERR_PARAM;
4566 "memzone %s to be freed with physical address: %"PRIu64,
4567 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4568 rte_memzone_free((const struct rte_memzone *)mem->zone);
4573 return I40E_SUCCESS;
4577 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4578 * @hw: pointer to the HW structure
4579 * @mem: pointer to mem struct to fill out
4580 * @size: size of memory requested
4582 enum i40e_status_code
4583 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4584 struct i40e_virt_mem *mem,
4588 return I40E_ERR_PARAM;
4591 mem->va = rte_zmalloc("i40e", size, 0);
4594 return I40E_SUCCESS;
4596 return I40E_ERR_NO_MEMORY;
4600 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4601 * @hw: pointer to the HW structure
4602 * @mem: pointer to mem struct to free
4604 enum i40e_status_code
4605 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4606 struct i40e_virt_mem *mem)
4609 return I40E_ERR_PARAM;
4614 return I40E_SUCCESS;
4618 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4620 rte_spinlock_init(&sp->spinlock);
4624 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4626 rte_spinlock_lock(&sp->spinlock);
4630 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4632 rte_spinlock_unlock(&sp->spinlock);
4636 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4642 * Get the hardware capabilities, which will be parsed
4643 * and saved into struct i40e_hw.
4646 i40e_get_cap(struct i40e_hw *hw)
4648 struct i40e_aqc_list_capabilities_element_resp *buf;
4649 uint16_t len, size = 0;
4652 /* Calculate a huge enough buff for saving response data temporarily */
4653 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4654 I40E_MAX_CAP_ELE_NUM;
4655 buf = rte_zmalloc("i40e", len, 0);
4657 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4658 return I40E_ERR_NO_MEMORY;
4661 /* Get, parse the capabilities and save it to hw */
4662 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4663 i40e_aqc_opc_list_func_capabilities, NULL);
4664 if (ret != I40E_SUCCESS)
4665 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4667 /* Free the temporary buffer after being used */
4673 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4675 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4683 pf = (struct i40e_pf *)opaque;
4687 num = strtoul(value, &end, 0);
4688 if (errno != 0 || end == value || *end != 0) {
4689 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4690 "kept the value = %hu", value, pf->vf_nb_qp_max);
4694 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4695 pf->vf_nb_qp_max = (uint16_t)num;
4697 /* here return 0 to make next valid same argument work */
4698 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4699 "power of 2 and equal or less than 16 !, Now it is "
4700 "kept the value = %hu", num, pf->vf_nb_qp_max);
4705 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4708 struct rte_kvargs *kvlist;
4711 /* set default queue number per VF as 4 */
4712 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4714 if (dev->device->devargs == NULL)
4717 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4721 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4722 if (!kvargs_count) {
4723 rte_kvargs_free(kvlist);
4727 if (kvargs_count > 1)
4728 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4729 "the first invalid or last valid one is used !",
4730 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4732 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4733 i40e_pf_parse_vf_queue_number_handler, pf);
4735 rte_kvargs_free(kvlist);
4741 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4743 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4744 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4745 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4746 uint16_t qp_count = 0, vsi_count = 0;
4748 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4749 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4753 i40e_pf_config_vf_rxq_number(dev);
4755 /* Add the parameter init for LFC */
4756 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4757 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4758 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4760 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4761 pf->max_num_vsi = hw->func_caps.num_vsis;
4762 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4763 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4765 /* FDir queue/VSI allocation */
4766 pf->fdir_qp_offset = 0;
4767 if (hw->func_caps.fd) {
4768 pf->flags |= I40E_FLAG_FDIR;
4769 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4771 pf->fdir_nb_qps = 0;
4773 qp_count += pf->fdir_nb_qps;
4776 /* LAN queue/VSI allocation */
4777 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4778 if (!hw->func_caps.rss) {
4781 pf->flags |= I40E_FLAG_RSS;
4782 if (hw->mac.type == I40E_MAC_X722)
4783 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4784 pf->lan_nb_qps = pf->lan_nb_qp_max;
4786 qp_count += pf->lan_nb_qps;
4789 /* VF queue/VSI allocation */
4790 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4791 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4792 pf->flags |= I40E_FLAG_SRIOV;
4793 pf->vf_nb_qps = pf->vf_nb_qp_max;
4794 pf->vf_num = pci_dev->max_vfs;
4796 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4797 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4802 qp_count += pf->vf_nb_qps * pf->vf_num;
4803 vsi_count += pf->vf_num;
4805 /* VMDq queue/VSI allocation */
4806 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4807 pf->vmdq_nb_qps = 0;
4808 pf->max_nb_vmdq_vsi = 0;
4809 if (hw->func_caps.vmdq) {
4810 if (qp_count < hw->func_caps.num_tx_qp &&
4811 vsi_count < hw->func_caps.num_vsis) {
4812 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4813 qp_count) / pf->vmdq_nb_qp_max;
4815 /* Limit the maximum number of VMDq vsi to the maximum
4816 * ethdev can support
4818 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4819 hw->func_caps.num_vsis - vsi_count);
4820 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4822 if (pf->max_nb_vmdq_vsi) {
4823 pf->flags |= I40E_FLAG_VMDQ;
4824 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4826 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4827 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4828 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4831 "No enough queues left for VMDq");
4834 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4837 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4838 vsi_count += pf->max_nb_vmdq_vsi;
4840 if (hw->func_caps.dcb)
4841 pf->flags |= I40E_FLAG_DCB;
4843 if (qp_count > hw->func_caps.num_tx_qp) {
4845 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4846 qp_count, hw->func_caps.num_tx_qp);
4849 if (vsi_count > hw->func_caps.num_vsis) {
4851 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4852 vsi_count, hw->func_caps.num_vsis);
4860 i40e_pf_get_switch_config(struct i40e_pf *pf)
4862 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4863 struct i40e_aqc_get_switch_config_resp *switch_config;
4864 struct i40e_aqc_switch_config_element_resp *element;
4865 uint16_t start_seid = 0, num_reported;
4868 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4869 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4870 if (!switch_config) {
4871 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4875 /* Get the switch configurations */
4876 ret = i40e_aq_get_switch_config(hw, switch_config,
4877 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4878 if (ret != I40E_SUCCESS) {
4879 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4882 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4883 if (num_reported != 1) { /* The number should be 1 */
4884 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4888 /* Parse the switch configuration elements */
4889 element = &(switch_config->element[0]);
4890 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4891 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4892 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4894 PMD_DRV_LOG(INFO, "Unknown element type");
4897 rte_free(switch_config);
4903 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4906 struct pool_entry *entry;
4908 if (pool == NULL || num == 0)
4911 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4912 if (entry == NULL) {
4913 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4917 /* queue heap initialize */
4918 pool->num_free = num;
4919 pool->num_alloc = 0;
4921 LIST_INIT(&pool->alloc_list);
4922 LIST_INIT(&pool->free_list);
4924 /* Initialize element */
4928 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4933 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4935 struct pool_entry *entry, *next_entry;
4940 for (entry = LIST_FIRST(&pool->alloc_list);
4941 entry && (next_entry = LIST_NEXT(entry, next), 1);
4942 entry = next_entry) {
4943 LIST_REMOVE(entry, next);
4947 for (entry = LIST_FIRST(&pool->free_list);
4948 entry && (next_entry = LIST_NEXT(entry, next), 1);
4949 entry = next_entry) {
4950 LIST_REMOVE(entry, next);
4955 pool->num_alloc = 0;
4957 LIST_INIT(&pool->alloc_list);
4958 LIST_INIT(&pool->free_list);
4962 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4965 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4966 uint32_t pool_offset;
4971 PMD_DRV_LOG(ERR, "Invalid parameter");
4975 pool_offset = base - pool->base;
4976 /* Lookup in alloc list */
4977 LIST_FOREACH(entry, &pool->alloc_list, next) {
4978 if (entry->base == pool_offset) {
4979 valid_entry = entry;
4980 LIST_REMOVE(entry, next);
4985 /* Not find, return */
4986 if (valid_entry == NULL) {
4987 PMD_DRV_LOG(ERR, "Failed to find entry");
4992 * Found it, move it to free list and try to merge.
4993 * In order to make merge easier, always sort it by qbase.
4994 * Find adjacent prev and last entries.
4997 LIST_FOREACH(entry, &pool->free_list, next) {
4998 if (entry->base > valid_entry->base) {
5006 len = valid_entry->len;
5007 /* Try to merge with next one*/
5009 /* Merge with next one */
5010 if (valid_entry->base + len == next->base) {
5011 next->base = valid_entry->base;
5013 rte_free(valid_entry);
5020 /* Merge with previous one */
5021 if (prev->base + prev->len == valid_entry->base) {
5023 /* If it merge with next one, remove next node */
5025 LIST_REMOVE(valid_entry, next);
5026 rte_free(valid_entry);
5029 rte_free(valid_entry);
5036 /* Not find any entry to merge, insert */
5039 LIST_INSERT_AFTER(prev, valid_entry, next);
5040 else if (next != NULL)
5041 LIST_INSERT_BEFORE(next, valid_entry, next);
5042 else /* It's empty list, insert to head */
5043 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5046 pool->num_free += len;
5047 pool->num_alloc -= len;
5053 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5056 struct pool_entry *entry, *valid_entry;
5058 if (pool == NULL || num == 0) {
5059 PMD_DRV_LOG(ERR, "Invalid parameter");
5063 if (pool->num_free < num) {
5064 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5065 num, pool->num_free);
5070 /* Lookup in free list and find most fit one */
5071 LIST_FOREACH(entry, &pool->free_list, next) {
5072 if (entry->len >= num) {
5074 if (entry->len == num) {
5075 valid_entry = entry;
5078 if (valid_entry == NULL || valid_entry->len > entry->len)
5079 valid_entry = entry;
5083 /* Not find one to satisfy the request, return */
5084 if (valid_entry == NULL) {
5085 PMD_DRV_LOG(ERR, "No valid entry found");
5089 * The entry have equal queue number as requested,
5090 * remove it from alloc_list.
5092 if (valid_entry->len == num) {
5093 LIST_REMOVE(valid_entry, next);
5096 * The entry have more numbers than requested,
5097 * create a new entry for alloc_list and minus its
5098 * queue base and number in free_list.
5100 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5101 if (entry == NULL) {
5103 "Failed to allocate memory for resource pool");
5106 entry->base = valid_entry->base;
5108 valid_entry->base += num;
5109 valid_entry->len -= num;
5110 valid_entry = entry;
5113 /* Insert it into alloc list, not sorted */
5114 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5116 pool->num_free -= valid_entry->len;
5117 pool->num_alloc += valid_entry->len;
5119 return valid_entry->base + pool->base;
5123 * bitmap_is_subset - Check whether src2 is subset of src1
5126 bitmap_is_subset(uint8_t src1, uint8_t src2)
5128 return !((src1 ^ src2) & src2);
5131 static enum i40e_status_code
5132 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5134 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5136 /* If DCB is not supported, only default TC is supported */
5137 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5138 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5139 return I40E_NOT_SUPPORTED;
5142 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5144 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5145 hw->func_caps.enabled_tcmap, enabled_tcmap);
5146 return I40E_NOT_SUPPORTED;
5148 return I40E_SUCCESS;
5152 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5153 struct i40e_vsi_vlan_pvid_info *info)
5156 struct i40e_vsi_context ctxt;
5157 uint8_t vlan_flags = 0;
5160 if (vsi == NULL || info == NULL) {
5161 PMD_DRV_LOG(ERR, "invalid parameters");
5162 return I40E_ERR_PARAM;
5166 vsi->info.pvid = info->config.pvid;
5168 * If insert pvid is enabled, only tagged pkts are
5169 * allowed to be sent out.
5171 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5172 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5175 if (info->config.reject.tagged == 0)
5176 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5178 if (info->config.reject.untagged == 0)
5179 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5181 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5182 I40E_AQ_VSI_PVLAN_MODE_MASK);
5183 vsi->info.port_vlan_flags |= vlan_flags;
5184 vsi->info.valid_sections =
5185 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5186 memset(&ctxt, 0, sizeof(ctxt));
5187 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5188 ctxt.seid = vsi->seid;
5190 hw = I40E_VSI_TO_HW(vsi);
5191 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5192 if (ret != I40E_SUCCESS)
5193 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5199 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5201 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5203 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5205 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5206 if (ret != I40E_SUCCESS)
5210 PMD_DRV_LOG(ERR, "seid not valid");
5214 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5215 tc_bw_data.tc_valid_bits = enabled_tcmap;
5216 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5217 tc_bw_data.tc_bw_credits[i] =
5218 (enabled_tcmap & (1 << i)) ? 1 : 0;
5220 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5221 if (ret != I40E_SUCCESS) {
5222 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5226 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5227 sizeof(vsi->info.qs_handle));
5228 return I40E_SUCCESS;
5231 static enum i40e_status_code
5232 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5233 struct i40e_aqc_vsi_properties_data *info,
5234 uint8_t enabled_tcmap)
5236 enum i40e_status_code ret;
5237 int i, total_tc = 0;
5238 uint16_t qpnum_per_tc, bsf, qp_idx;
5240 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5241 if (ret != I40E_SUCCESS)
5244 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5245 if (enabled_tcmap & (1 << i))
5249 vsi->enabled_tc = enabled_tcmap;
5251 /* Number of queues per enabled TC */
5252 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5253 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5254 bsf = rte_bsf32(qpnum_per_tc);
5256 /* Adjust the queue number to actual queues that can be applied */
5257 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5258 vsi->nb_qps = qpnum_per_tc * total_tc;
5261 * Configure TC and queue mapping parameters, for enabled TC,
5262 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5263 * default queue will serve it.
5266 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5267 if (vsi->enabled_tc & (1 << i)) {
5268 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5269 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5270 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5271 qp_idx += qpnum_per_tc;
5273 info->tc_mapping[i] = 0;
5276 /* Associate queue number with VSI */
5277 if (vsi->type == I40E_VSI_SRIOV) {
5278 info->mapping_flags |=
5279 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5280 for (i = 0; i < vsi->nb_qps; i++)
5281 info->queue_mapping[i] =
5282 rte_cpu_to_le_16(vsi->base_queue + i);
5284 info->mapping_flags |=
5285 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5286 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5288 info->valid_sections |=
5289 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5291 return I40E_SUCCESS;
5295 i40e_veb_release(struct i40e_veb *veb)
5297 struct i40e_vsi *vsi;
5303 if (!TAILQ_EMPTY(&veb->head)) {
5304 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5307 /* associate_vsi field is NULL for floating VEB */
5308 if (veb->associate_vsi != NULL) {
5309 vsi = veb->associate_vsi;
5310 hw = I40E_VSI_TO_HW(vsi);
5312 vsi->uplink_seid = veb->uplink_seid;
5315 veb->associate_pf->main_vsi->floating_veb = NULL;
5316 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5319 i40e_aq_delete_element(hw, veb->seid, NULL);
5321 return I40E_SUCCESS;
5325 static struct i40e_veb *
5326 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5328 struct i40e_veb *veb;
5334 "veb setup failed, associated PF shouldn't null");
5337 hw = I40E_PF_TO_HW(pf);
5339 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5341 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5345 veb->associate_vsi = vsi;
5346 veb->associate_pf = pf;
5347 TAILQ_INIT(&veb->head);
5348 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5350 /* create floating veb if vsi is NULL */
5352 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5353 I40E_DEFAULT_TCMAP, false,
5354 &veb->seid, false, NULL);
5356 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5357 true, &veb->seid, false, NULL);
5360 if (ret != I40E_SUCCESS) {
5361 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5362 hw->aq.asq_last_status);
5365 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5367 /* get statistics index */
5368 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5369 &veb->stats_idx, NULL, NULL, NULL);
5370 if (ret != I40E_SUCCESS) {
5371 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5372 hw->aq.asq_last_status);
5375 /* Get VEB bandwidth, to be implemented */
5376 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5378 vsi->uplink_seid = veb->seid;
5387 i40e_vsi_release(struct i40e_vsi *vsi)
5391 struct i40e_vsi_list *vsi_list;
5394 struct i40e_mac_filter *f;
5395 uint16_t user_param;
5398 return I40E_SUCCESS;
5403 user_param = vsi->user_param;
5405 pf = I40E_VSI_TO_PF(vsi);
5406 hw = I40E_VSI_TO_HW(vsi);
5408 /* VSI has child to attach, release child first */
5410 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5411 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5414 i40e_veb_release(vsi->veb);
5417 if (vsi->floating_veb) {
5418 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head,
5420 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5425 /* Remove all macvlan filters of the VSI */
5426 i40e_vsi_remove_all_macvlan_filter(vsi);
5427 RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5430 if (vsi->type != I40E_VSI_MAIN &&
5431 ((vsi->type != I40E_VSI_SRIOV) ||
5432 !pf->floating_veb_list[user_param])) {
5433 /* Remove vsi from parent's sibling list */
5434 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5435 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5436 return I40E_ERR_PARAM;
5438 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5439 &vsi->sib_vsi_list, list);
5441 /* Remove all switch element of the VSI */
5442 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5443 if (ret != I40E_SUCCESS)
5444 PMD_DRV_LOG(ERR, "Failed to delete element");
5447 if ((vsi->type == I40E_VSI_SRIOV) &&
5448 pf->floating_veb_list[user_param]) {
5449 /* Remove vsi from parent's sibling list */
5450 if (vsi->parent_vsi == NULL ||
5451 vsi->parent_vsi->floating_veb == NULL) {
5452 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5453 return I40E_ERR_PARAM;
5455 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5456 &vsi->sib_vsi_list, list);
5458 /* Remove all switch element of the VSI */
5459 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5460 if (ret != I40E_SUCCESS)
5461 PMD_DRV_LOG(ERR, "Failed to delete element");
5464 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5466 if (vsi->type != I40E_VSI_SRIOV)
5467 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5470 return I40E_SUCCESS;
5474 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5476 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5477 struct i40e_aqc_remove_macvlan_element_data def_filter;
5478 struct i40e_mac_filter_info filter;
5481 if (vsi->type != I40E_VSI_MAIN)
5482 return I40E_ERR_CONFIG;
5483 memset(&def_filter, 0, sizeof(def_filter));
5484 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5486 def_filter.vlan_tag = 0;
5487 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5488 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5489 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5490 if (ret != I40E_SUCCESS) {
5491 struct i40e_mac_filter *f;
5492 struct rte_ether_addr *mac;
5495 "Cannot remove the default macvlan filter");
5496 /* It needs to add the permanent mac into mac list */
5497 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5499 PMD_DRV_LOG(ERR, "failed to allocate memory");
5500 return I40E_ERR_NO_MEMORY;
5502 mac = &f->mac_info.mac_addr;
5503 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5505 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5506 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5511 rte_memcpy(&filter.mac_addr,
5512 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5513 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5514 return i40e_vsi_add_mac(vsi, &filter);
5518 * i40e_vsi_get_bw_config - Query VSI BW Information
5519 * @vsi: the VSI to be queried
5521 * Returns 0 on success, negative value on failure
5523 static enum i40e_status_code
5524 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5526 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5527 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5528 struct i40e_hw *hw = &vsi->adapter->hw;
5533 memset(&bw_config, 0, sizeof(bw_config));
5534 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5535 if (ret != I40E_SUCCESS) {
5536 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5537 hw->aq.asq_last_status);
5541 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5542 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5543 &ets_sla_config, NULL);
5544 if (ret != I40E_SUCCESS) {
5546 "VSI failed to get TC bandwdith configuration %u",
5547 hw->aq.asq_last_status);
5551 /* store and print out BW info */
5552 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5553 vsi->bw_info.bw_max = bw_config.max_bw;
5554 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5555 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5556 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5557 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5559 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5560 vsi->bw_info.bw_ets_share_credits[i] =
5561 ets_sla_config.share_credits[i];
5562 vsi->bw_info.bw_ets_credits[i] =
5563 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5564 /* 4 bits per TC, 4th bit is reserved */
5565 vsi->bw_info.bw_ets_max[i] =
5566 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5567 RTE_LEN2MASK(3, uint8_t));
5568 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5569 vsi->bw_info.bw_ets_share_credits[i]);
5570 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5571 vsi->bw_info.bw_ets_credits[i]);
5572 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5573 vsi->bw_info.bw_ets_max[i]);
5576 return I40E_SUCCESS;
5579 /* i40e_enable_pf_lb
5580 * @pf: pointer to the pf structure
5582 * allow loopback on pf
5585 i40e_enable_pf_lb(struct i40e_pf *pf)
5587 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5588 struct i40e_vsi_context ctxt;
5591 /* Use the FW API if FW >= v5.0 */
5592 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5593 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5597 memset(&ctxt, 0, sizeof(ctxt));
5598 ctxt.seid = pf->main_vsi_seid;
5599 ctxt.pf_num = hw->pf_id;
5600 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5602 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5603 ret, hw->aq.asq_last_status);
5606 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5607 ctxt.info.valid_sections =
5608 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5609 ctxt.info.switch_id |=
5610 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5612 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5614 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5615 hw->aq.asq_last_status);
5620 i40e_vsi_setup(struct i40e_pf *pf,
5621 enum i40e_vsi_type type,
5622 struct i40e_vsi *uplink_vsi,
5623 uint16_t user_param)
5625 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5626 struct i40e_vsi *vsi;
5627 struct i40e_mac_filter_info filter;
5629 struct i40e_vsi_context ctxt;
5630 struct rte_ether_addr broadcast =
5631 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5633 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5634 uplink_vsi == NULL) {
5636 "VSI setup failed, VSI link shouldn't be NULL");
5640 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5642 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5647 * 1.type is not MAIN and uplink vsi is not NULL
5648 * If uplink vsi didn't setup VEB, create one first under veb field
5649 * 2.type is SRIOV and the uplink is NULL
5650 * If floating VEB is NULL, create one veb under floating veb field
5653 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5654 uplink_vsi->veb == NULL) {
5655 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5657 if (uplink_vsi->veb == NULL) {
5658 PMD_DRV_LOG(ERR, "VEB setup failed");
5661 /* set ALLOWLOOPBACk on pf, when veb is created */
5662 i40e_enable_pf_lb(pf);
5665 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5666 pf->main_vsi->floating_veb == NULL) {
5667 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5669 if (pf->main_vsi->floating_veb == NULL) {
5670 PMD_DRV_LOG(ERR, "VEB setup failed");
5675 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5677 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5680 TAILQ_INIT(&vsi->mac_list);
5682 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5683 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5684 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5685 vsi->user_param = user_param;
5686 vsi->vlan_anti_spoof_on = 0;
5687 vsi->vlan_filter_on = 0;
5688 /* Allocate queues */
5689 switch (vsi->type) {
5690 case I40E_VSI_MAIN :
5691 vsi->nb_qps = pf->lan_nb_qps;
5693 case I40E_VSI_SRIOV :
5694 vsi->nb_qps = pf->vf_nb_qps;
5696 case I40E_VSI_VMDQ2:
5697 vsi->nb_qps = pf->vmdq_nb_qps;
5700 vsi->nb_qps = pf->fdir_nb_qps;
5706 * The filter status descriptor is reported in rx queue 0,
5707 * while the tx queue for fdir filter programming has no
5708 * such constraints, can be non-zero queues.
5709 * To simplify it, choose FDIR vsi use queue 0 pair.
5710 * To make sure it will use queue 0 pair, queue allocation
5711 * need be done before this function is called
5713 if (type != I40E_VSI_FDIR) {
5714 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5716 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5720 vsi->base_queue = ret;
5722 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5724 /* VF has MSIX interrupt in VF range, don't allocate here */
5725 if (type == I40E_VSI_MAIN) {
5726 if (pf->support_multi_driver) {
5727 /* If support multi-driver, need to use INT0 instead of
5728 * allocating from msix pool. The Msix pool is init from
5729 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5730 * to 1 without calling i40e_res_pool_alloc.
5735 ret = i40e_res_pool_alloc(&pf->msix_pool,
5736 RTE_MIN(vsi->nb_qps,
5737 RTE_MAX_RXTX_INTR_VEC_ID));
5740 "VSI MAIN %d get heap failed %d",
5742 goto fail_queue_alloc;
5744 vsi->msix_intr = ret;
5745 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5746 RTE_MAX_RXTX_INTR_VEC_ID);
5748 } else if (type != I40E_VSI_SRIOV) {
5749 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5751 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5752 if (type != I40E_VSI_FDIR)
5753 goto fail_queue_alloc;
5757 vsi->msix_intr = ret;
5766 if (type == I40E_VSI_MAIN) {
5767 /* For main VSI, no need to add since it's default one */
5768 vsi->uplink_seid = pf->mac_seid;
5769 vsi->seid = pf->main_vsi_seid;
5770 /* Bind queues with specific MSIX interrupt */
5772 * Needs 2 interrupt at least, one for misc cause which will
5773 * enabled from OS side, Another for queues binding the
5774 * interrupt from device side only.
5777 /* Get default VSI parameters from hardware */
5778 memset(&ctxt, 0, sizeof(ctxt));
5779 ctxt.seid = vsi->seid;
5780 ctxt.pf_num = hw->pf_id;
5781 ctxt.uplink_seid = vsi->uplink_seid;
5783 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5784 if (ret != I40E_SUCCESS) {
5785 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5786 goto fail_msix_alloc;
5788 rte_memcpy(&vsi->info, &ctxt.info,
5789 sizeof(struct i40e_aqc_vsi_properties_data));
5790 vsi->vsi_id = ctxt.vsi_number;
5791 vsi->info.valid_sections = 0;
5793 /* Configure tc, enabled TC0 only */
5794 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5796 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5797 goto fail_msix_alloc;
5800 /* TC, queue mapping */
5801 memset(&ctxt, 0, sizeof(ctxt));
5802 vsi->info.valid_sections |=
5803 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5804 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5805 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5806 rte_memcpy(&ctxt.info, &vsi->info,
5807 sizeof(struct i40e_aqc_vsi_properties_data));
5808 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5809 I40E_DEFAULT_TCMAP);
5810 if (ret != I40E_SUCCESS) {
5812 "Failed to configure TC queue mapping");
5813 goto fail_msix_alloc;
5815 ctxt.seid = vsi->seid;
5816 ctxt.pf_num = hw->pf_id;
5817 ctxt.uplink_seid = vsi->uplink_seid;
5820 /* Update VSI parameters */
5821 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5822 if (ret != I40E_SUCCESS) {
5823 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5824 goto fail_msix_alloc;
5827 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5828 sizeof(vsi->info.tc_mapping));
5829 rte_memcpy(&vsi->info.queue_mapping,
5830 &ctxt.info.queue_mapping,
5831 sizeof(vsi->info.queue_mapping));
5832 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5833 vsi->info.valid_sections = 0;
5835 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5839 * Updating default filter settings are necessary to prevent
5840 * reception of tagged packets.
5841 * Some old firmware configurations load a default macvlan
5842 * filter which accepts both tagged and untagged packets.
5843 * The updating is to use a normal filter instead if needed.
5844 * For NVM 4.2.2 or after, the updating is not needed anymore.
5845 * The firmware with correct configurations load the default
5846 * macvlan filter which is expected and cannot be removed.
5848 i40e_update_default_filter_setting(vsi);
5849 i40e_config_qinq(hw, vsi);
5850 } else if (type == I40E_VSI_SRIOV) {
5851 memset(&ctxt, 0, sizeof(ctxt));
5853 * For other VSI, the uplink_seid equals to uplink VSI's
5854 * uplink_seid since they share same VEB
5856 if (uplink_vsi == NULL)
5857 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5859 vsi->uplink_seid = uplink_vsi->uplink_seid;
5860 ctxt.pf_num = hw->pf_id;
5861 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5862 ctxt.uplink_seid = vsi->uplink_seid;
5863 ctxt.connection_type = 0x1;
5864 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5866 /* Use the VEB configuration if FW >= v5.0 */
5867 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5868 /* Configure switch ID */
5869 ctxt.info.valid_sections |=
5870 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5871 ctxt.info.switch_id =
5872 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5875 /* Configure port/vlan */
5876 ctxt.info.valid_sections |=
5877 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5878 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5879 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5880 hw->func_caps.enabled_tcmap);
5881 if (ret != I40E_SUCCESS) {
5883 "Failed to configure TC queue mapping");
5884 goto fail_msix_alloc;
5887 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5888 ctxt.info.valid_sections |=
5889 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5891 * Since VSI is not created yet, only configure parameter,
5892 * will add vsi below.
5895 i40e_config_qinq(hw, vsi);
5896 } else if (type == I40E_VSI_VMDQ2) {
5897 memset(&ctxt, 0, sizeof(ctxt));
5899 * For other VSI, the uplink_seid equals to uplink VSI's
5900 * uplink_seid since they share same VEB
5902 vsi->uplink_seid = uplink_vsi->uplink_seid;
5903 ctxt.pf_num = hw->pf_id;
5905 ctxt.uplink_seid = vsi->uplink_seid;
5906 ctxt.connection_type = 0x1;
5907 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5909 ctxt.info.valid_sections |=
5910 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5911 /* user_param carries flag to enable loop back */
5913 ctxt.info.switch_id =
5914 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5915 ctxt.info.switch_id |=
5916 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5919 /* Configure port/vlan */
5920 ctxt.info.valid_sections |=
5921 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5922 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5923 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5924 I40E_DEFAULT_TCMAP);
5925 if (ret != I40E_SUCCESS) {
5927 "Failed to configure TC queue mapping");
5928 goto fail_msix_alloc;
5930 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5931 ctxt.info.valid_sections |=
5932 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5933 } else if (type == I40E_VSI_FDIR) {
5934 memset(&ctxt, 0, sizeof(ctxt));
5935 vsi->uplink_seid = uplink_vsi->uplink_seid;
5936 ctxt.pf_num = hw->pf_id;
5938 ctxt.uplink_seid = vsi->uplink_seid;
5939 ctxt.connection_type = 0x1; /* regular data port */
5940 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5941 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5942 I40E_DEFAULT_TCMAP);
5943 if (ret != I40E_SUCCESS) {
5945 "Failed to configure TC queue mapping.");
5946 goto fail_msix_alloc;
5948 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5949 ctxt.info.valid_sections |=
5950 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5952 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5953 goto fail_msix_alloc;
5956 if (vsi->type != I40E_VSI_MAIN) {
5957 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5958 if (ret != I40E_SUCCESS) {
5959 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5960 hw->aq.asq_last_status);
5961 goto fail_msix_alloc;
5963 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5964 vsi->info.valid_sections = 0;
5965 vsi->seid = ctxt.seid;
5966 vsi->vsi_id = ctxt.vsi_number;
5967 vsi->sib_vsi_list.vsi = vsi;
5968 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5969 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5970 &vsi->sib_vsi_list, list);
5972 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5973 &vsi->sib_vsi_list, list);
5977 /* MAC/VLAN configuration */
5978 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5979 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5981 ret = i40e_vsi_add_mac(vsi, &filter);
5982 if (ret != I40E_SUCCESS) {
5983 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5984 goto fail_msix_alloc;
5987 /* Get VSI BW information */
5988 i40e_vsi_get_bw_config(vsi);
5991 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5993 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5999 /* Configure vlan filter on or off */
6001 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6004 struct i40e_mac_filter *f;
6006 struct i40e_mac_filter_info *mac_filter;
6007 enum i40e_mac_filter_type desired_filter;
6008 int ret = I40E_SUCCESS;
6011 /* Filter to match MAC and VLAN */
6012 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6014 /* Filter to match only MAC */
6015 desired_filter = I40E_MAC_PERFECT_MATCH;
6020 mac_filter = rte_zmalloc("mac_filter_info_data",
6021 num * sizeof(*mac_filter), 0);
6022 if (mac_filter == NULL) {
6023 PMD_DRV_LOG(ERR, "failed to allocate memory");
6024 return I40E_ERR_NO_MEMORY;
6029 /* Remove all existing mac */
6030 RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6031 mac_filter[i] = f->mac_info;
6032 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6034 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6035 on ? "enable" : "disable");
6041 /* Override with new filter */
6042 for (i = 0; i < num; i++) {
6043 mac_filter[i].filter_type = desired_filter;
6044 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6046 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6047 on ? "enable" : "disable");
6053 rte_free(mac_filter);
6057 /* Configure vlan stripping on or off */
6059 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6061 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6062 struct i40e_vsi_context ctxt;
6064 int ret = I40E_SUCCESS;
6066 /* Check if it has been already on or off */
6067 if (vsi->info.valid_sections &
6068 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6070 if ((vsi->info.port_vlan_flags &
6071 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6072 return 0; /* already on */
6074 if ((vsi->info.port_vlan_flags &
6075 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6076 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6077 return 0; /* already off */
6082 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6084 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6085 vsi->info.valid_sections =
6086 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6087 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6088 vsi->info.port_vlan_flags |= vlan_flags;
6089 ctxt.seid = vsi->seid;
6090 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6091 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6093 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6094 on ? "enable" : "disable");
6100 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6102 struct rte_eth_dev_data *data = dev->data;
6106 /* Apply vlan offload setting */
6107 mask = ETH_VLAN_STRIP_MASK |
6108 ETH_QINQ_STRIP_MASK |
6109 ETH_VLAN_FILTER_MASK |
6110 ETH_VLAN_EXTEND_MASK;
6111 ret = i40e_vlan_offload_set(dev, mask);
6113 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6117 /* Apply pvid setting */
6118 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6119 data->dev_conf.txmode.hw_vlan_insert_pvid);
6121 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6127 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6129 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6131 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6135 i40e_update_flow_control(struct i40e_hw *hw)
6137 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6138 struct i40e_link_status link_status;
6139 uint32_t rxfc = 0, txfc = 0, reg;
6143 memset(&link_status, 0, sizeof(link_status));
6144 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6145 if (ret != I40E_SUCCESS) {
6146 PMD_DRV_LOG(ERR, "Failed to get link status information");
6147 goto write_reg; /* Disable flow control */
6150 an_info = hw->phy.link_info.an_info;
6151 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6152 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6153 ret = I40E_ERR_NOT_READY;
6154 goto write_reg; /* Disable flow control */
6157 * If link auto negotiation is enabled, flow control needs to
6158 * be configured according to it
6160 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6161 case I40E_LINK_PAUSE_RXTX:
6164 hw->fc.current_mode = I40E_FC_FULL;
6166 case I40E_AQ_LINK_PAUSE_RX:
6168 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6170 case I40E_AQ_LINK_PAUSE_TX:
6172 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6175 hw->fc.current_mode = I40E_FC_NONE;
6180 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6181 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6182 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6183 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6184 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6185 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6192 i40e_pf_setup(struct i40e_pf *pf)
6194 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6195 struct i40e_filter_control_settings settings;
6196 struct i40e_vsi *vsi;
6199 /* Clear all stats counters */
6200 pf->offset_loaded = FALSE;
6201 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6202 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6203 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6204 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6206 pf->rx_err1_offset = 0;
6208 ret = i40e_pf_get_switch_config(pf);
6209 if (ret != I40E_SUCCESS) {
6210 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6214 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6216 PMD_INIT_LOG(WARNING,
6217 "failed to allocate switch domain for device %d", ret);
6219 if (pf->flags & I40E_FLAG_FDIR) {
6220 /* make queue allocated first, let FDIR use queue pair 0*/
6221 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6222 if (ret != I40E_FDIR_QUEUE_ID) {
6224 "queue allocation fails for FDIR: ret =%d",
6226 pf->flags &= ~I40E_FLAG_FDIR;
6229 /* main VSI setup */
6230 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6232 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6233 return I40E_ERR_NOT_READY;
6237 /* Configure filter control */
6238 memset(&settings, 0, sizeof(settings));
6239 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6240 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6241 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6242 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6244 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6245 hw->func_caps.rss_table_size);
6246 return I40E_ERR_PARAM;
6248 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6249 hw->func_caps.rss_table_size);
6250 pf->hash_lut_size = hw->func_caps.rss_table_size;
6252 /* Enable ethtype and macvlan filters */
6253 settings.enable_ethtype = TRUE;
6254 settings.enable_macvlan = TRUE;
6255 ret = i40e_set_filter_control(hw, &settings);
6257 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6260 /* Update flow control according to the auto negotiation */
6261 i40e_update_flow_control(hw);
6263 return I40E_SUCCESS;
6267 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6273 * Set or clear TX Queue Disable flags,
6274 * which is required by hardware.
6276 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6277 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6279 /* Wait until the request is finished */
6280 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6281 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6282 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6283 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6284 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6290 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6291 return I40E_SUCCESS; /* already on, skip next steps */
6293 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6294 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6296 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6297 return I40E_SUCCESS; /* already off, skip next steps */
6298 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6300 /* Write the register */
6301 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6302 /* Check the result */
6303 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6304 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6305 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6307 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6308 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6311 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6312 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6316 /* Check if it is timeout */
6317 if (j >= I40E_CHK_Q_ENA_COUNT) {
6318 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6319 (on ? "enable" : "disable"), q_idx);
6320 return I40E_ERR_TIMEOUT;
6323 return I40E_SUCCESS;
6327 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6332 /* Wait until the request is finished */
6333 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6334 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6335 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6336 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6337 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6342 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6343 return I40E_SUCCESS; /* Already on, skip next steps */
6344 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6346 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6347 return I40E_SUCCESS; /* Already off, skip next steps */
6348 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6351 /* Write the register */
6352 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6353 /* Check the result */
6354 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6355 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6356 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6358 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6359 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6362 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6363 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6368 /* Check if it is timeout */
6369 if (j >= I40E_CHK_Q_ENA_COUNT) {
6370 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6371 (on ? "enable" : "disable"), q_idx);
6372 return I40E_ERR_TIMEOUT;
6375 return I40E_SUCCESS;
6378 /* Initialize VSI for TX */
6380 i40e_dev_tx_init(struct i40e_pf *pf)
6382 struct rte_eth_dev_data *data = pf->dev_data;
6384 uint32_t ret = I40E_SUCCESS;
6385 struct i40e_tx_queue *txq;
6387 for (i = 0; i < data->nb_tx_queues; i++) {
6388 txq = data->tx_queues[i];
6389 if (!txq || !txq->q_set)
6391 ret = i40e_tx_queue_init(txq);
6392 if (ret != I40E_SUCCESS)
6395 if (ret == I40E_SUCCESS)
6396 i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
6401 /* Initialize VSI for RX */
6403 i40e_dev_rx_init(struct i40e_pf *pf)
6405 struct rte_eth_dev_data *data = pf->dev_data;
6406 int ret = I40E_SUCCESS;
6408 struct i40e_rx_queue *rxq;
6410 i40e_pf_config_rss(pf);
6411 for (i = 0; i < data->nb_rx_queues; i++) {
6412 rxq = data->rx_queues[i];
6413 if (!rxq || !rxq->q_set)
6416 ret = i40e_rx_queue_init(rxq);
6417 if (ret != I40E_SUCCESS) {
6419 "Failed to do RX queue initialization");
6423 if (ret == I40E_SUCCESS)
6424 i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
6430 i40e_dev_rxtx_init(struct i40e_pf *pf)
6434 err = i40e_dev_tx_init(pf);
6436 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6439 err = i40e_dev_rx_init(pf);
6441 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6449 i40e_vmdq_setup(struct rte_eth_dev *dev)
6451 struct rte_eth_conf *conf = &dev->data->dev_conf;
6452 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6453 int i, err, conf_vsis, j, loop;
6454 struct i40e_vsi *vsi;
6455 struct i40e_vmdq_info *vmdq_info;
6456 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6457 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6460 * Disable interrupt to avoid message from VF. Furthermore, it will
6461 * avoid race condition in VSI creation/destroy.
6463 i40e_pf_disable_irq0(hw);
6465 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6466 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6470 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6471 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6472 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6473 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6474 pf->max_nb_vmdq_vsi);
6478 if (pf->vmdq != NULL) {
6479 PMD_INIT_LOG(INFO, "VMDQ already configured");
6483 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6484 sizeof(*vmdq_info) * conf_vsis, 0);
6486 if (pf->vmdq == NULL) {
6487 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6491 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6493 /* Create VMDQ VSI */
6494 for (i = 0; i < conf_vsis; i++) {
6495 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6496 vmdq_conf->enable_loop_back);
6498 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6502 vmdq_info = &pf->vmdq[i];
6504 vmdq_info->vsi = vsi;
6506 pf->nb_cfg_vmdq_vsi = conf_vsis;
6508 /* Configure Vlan */
6509 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6510 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6511 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6512 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6513 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6514 vmdq_conf->pool_map[i].vlan_id, j);
6516 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6517 vmdq_conf->pool_map[i].vlan_id);
6519 PMD_INIT_LOG(ERR, "Failed to add vlan");
6527 i40e_pf_enable_irq0(hw);
6532 for (i = 0; i < conf_vsis; i++)
6533 if (pf->vmdq[i].vsi == NULL)
6536 i40e_vsi_release(pf->vmdq[i].vsi);
6540 i40e_pf_enable_irq0(hw);
6545 i40e_stat_update_32(struct i40e_hw *hw,
6553 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6557 if (new_data >= *offset)
6558 *stat = (uint64_t)(new_data - *offset);
6560 *stat = (uint64_t)((new_data +
6561 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6565 i40e_stat_update_48(struct i40e_hw *hw,
6574 if (hw->device_id == I40E_DEV_ID_QEMU) {
6575 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6576 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6577 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6579 new_data = I40E_READ_REG64(hw, loreg);
6585 if (new_data >= *offset)
6586 *stat = new_data - *offset;
6588 *stat = (uint64_t)((new_data +
6589 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6591 *stat &= I40E_48_BIT_MASK;
6596 i40e_pf_disable_irq0(struct i40e_hw *hw)
6598 /* Disable all interrupt types */
6599 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6600 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6601 I40E_WRITE_FLUSH(hw);
6606 i40e_pf_enable_irq0(struct i40e_hw *hw)
6608 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6609 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6610 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6611 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6612 I40E_WRITE_FLUSH(hw);
6616 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6618 /* read pending request and disable first */
6619 i40e_pf_disable_irq0(hw);
6620 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6621 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6622 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6625 /* Link no queues with irq0 */
6626 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6627 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6631 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6633 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6634 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6637 uint32_t index, offset, val;
6642 * Try to find which VF trigger a reset, use absolute VF id to access
6643 * since the reg is global register.
6645 for (i = 0; i < pf->vf_num; i++) {
6646 abs_vf_id = hw->func_caps.vf_base_id + i;
6647 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6648 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6649 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6650 /* VFR event occurred */
6651 if (val & (0x1 << offset)) {
6654 /* Clear the event first */
6655 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6657 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6659 * Only notify a VF reset event occurred,
6660 * don't trigger another SW reset
6662 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6663 if (ret != I40E_SUCCESS)
6664 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6670 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6672 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6675 for (i = 0; i < pf->vf_num; i++)
6676 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6680 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6683 struct i40e_arq_event_info info;
6684 uint16_t pending, opcode;
6687 info.buf_len = I40E_AQ_BUF_SZ;
6688 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6689 if (!info.msg_buf) {
6690 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6696 ret = i40e_clean_arq_element(hw, &info, &pending);
6698 if (ret != I40E_SUCCESS) {
6700 "Failed to read msg from AdminQ, aq_err: %u",
6701 hw->aq.asq_last_status);
6704 opcode = rte_le_to_cpu_16(info.desc.opcode);
6707 case i40e_aqc_opc_send_msg_to_pf:
6708 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6709 i40e_pf_host_handle_vf_msg(dev,
6710 rte_le_to_cpu_16(info.desc.retval),
6711 rte_le_to_cpu_32(info.desc.cookie_high),
6712 rte_le_to_cpu_32(info.desc.cookie_low),
6716 case i40e_aqc_opc_get_link_status:
6717 ret = i40e_dev_link_update(dev, 0);
6719 rte_eth_dev_callback_process(dev,
6720 RTE_ETH_EVENT_INTR_LSC, NULL);
6723 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6728 rte_free(info.msg_buf);
6732 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6734 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6735 #define I40E_MDD_CLEAR16 0xFFFF
6736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6737 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6738 bool mdd_detected = false;
6739 struct i40e_pf_vf *vf;
6743 /* find what triggered the MDD event */
6744 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6745 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6746 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6747 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6748 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6749 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6750 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6751 I40E_GL_MDET_TX_EVENT_SHIFT;
6752 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6753 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6754 hw->func_caps.base_queue;
6755 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6756 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6757 event, queue, pf_num, vf_num, dev->data->name);
6758 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6759 mdd_detected = true;
6761 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6762 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6763 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6764 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6765 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6766 I40E_GL_MDET_RX_EVENT_SHIFT;
6767 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6768 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6769 hw->func_caps.base_queue;
6771 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6772 "queue %d of function 0x%02x device %s\n",
6773 event, queue, func, dev->data->name);
6774 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6775 mdd_detected = true;
6779 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6780 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6781 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6782 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6784 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6785 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6786 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6788 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6792 /* see if one of the VFs needs its hand slapped */
6793 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6795 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6796 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6797 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6799 vf->num_mdd_events++;
6800 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6802 i, vf->num_mdd_events);
6805 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6806 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6807 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6809 vf->num_mdd_events++;
6810 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6812 i, vf->num_mdd_events);
6818 * Interrupt handler triggered by NIC for handling
6819 * specific interrupt.
6822 * Pointer to interrupt handle.
6824 * The address of parameter (struct rte_eth_dev *) regsitered before.
6830 i40e_dev_interrupt_handler(void *param)
6832 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6836 /* Disable interrupt */
6837 i40e_pf_disable_irq0(hw);
6839 /* read out interrupt causes */
6840 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6842 /* No interrupt event indicated */
6843 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6844 PMD_DRV_LOG(INFO, "No interrupt event");
6847 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6848 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6849 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6850 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6851 i40e_handle_mdd_event(dev);
6853 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6854 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6855 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6856 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6857 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6858 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6859 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6860 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6861 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6862 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6864 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6865 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6866 i40e_dev_handle_vfr_event(dev);
6868 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6869 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6870 i40e_dev_handle_aq_msg(dev);
6874 /* Enable interrupt */
6875 i40e_pf_enable_irq0(hw);
6879 i40e_dev_alarm_handler(void *param)
6881 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885 /* Disable interrupt */
6886 i40e_pf_disable_irq0(hw);
6888 /* read out interrupt causes */
6889 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6891 /* No interrupt event indicated */
6892 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6894 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6895 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6896 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6897 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6898 i40e_handle_mdd_event(dev);
6900 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6901 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6902 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6903 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6904 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6905 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6906 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6907 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6908 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6909 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6911 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6912 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6913 i40e_dev_handle_vfr_event(dev);
6915 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6916 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6917 i40e_dev_handle_aq_msg(dev);
6921 /* Enable interrupt */
6922 i40e_pf_enable_irq0(hw);
6923 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6924 i40e_dev_alarm_handler, dev);
6928 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6929 struct i40e_macvlan_filter *filter,
6932 int ele_num, ele_buff_size;
6933 int num, actual_num, i;
6935 int ret = I40E_SUCCESS;
6936 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6937 struct i40e_aqc_add_macvlan_element_data *req_list;
6939 if (filter == NULL || total == 0)
6940 return I40E_ERR_PARAM;
6941 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6942 ele_buff_size = hw->aq.asq_buf_size;
6944 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6945 if (req_list == NULL) {
6946 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6947 return I40E_ERR_NO_MEMORY;
6952 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6953 memset(req_list, 0, ele_buff_size);
6955 for (i = 0; i < actual_num; i++) {
6956 rte_memcpy(req_list[i].mac_addr,
6957 &filter[num + i].macaddr, ETH_ADDR_LEN);
6958 req_list[i].vlan_tag =
6959 rte_cpu_to_le_16(filter[num + i].vlan_id);
6961 switch (filter[num + i].filter_type) {
6962 case I40E_MAC_PERFECT_MATCH:
6963 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6964 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6966 case I40E_MACVLAN_PERFECT_MATCH:
6967 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6969 case I40E_MAC_HASH_MATCH:
6970 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6971 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6973 case I40E_MACVLAN_HASH_MATCH:
6974 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6977 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6978 ret = I40E_ERR_PARAM;
6982 req_list[i].queue_number = 0;
6984 req_list[i].flags = rte_cpu_to_le_16(flags);
6987 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6989 if (ret != I40E_SUCCESS) {
6990 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6994 } while (num < total);
7002 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7003 struct i40e_macvlan_filter *filter,
7006 int ele_num, ele_buff_size;
7007 int num, actual_num, i;
7009 int ret = I40E_SUCCESS;
7010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7011 struct i40e_aqc_remove_macvlan_element_data *req_list;
7012 enum i40e_admin_queue_err aq_status;
7014 if (filter == NULL || total == 0)
7015 return I40E_ERR_PARAM;
7017 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7018 ele_buff_size = hw->aq.asq_buf_size;
7020 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7021 if (req_list == NULL) {
7022 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7023 return I40E_ERR_NO_MEMORY;
7028 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7029 memset(req_list, 0, ele_buff_size);
7031 for (i = 0; i < actual_num; i++) {
7032 rte_memcpy(req_list[i].mac_addr,
7033 &filter[num + i].macaddr, ETH_ADDR_LEN);
7034 req_list[i].vlan_tag =
7035 rte_cpu_to_le_16(filter[num + i].vlan_id);
7037 switch (filter[num + i].filter_type) {
7038 case I40E_MAC_PERFECT_MATCH:
7039 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7040 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7042 case I40E_MACVLAN_PERFECT_MATCH:
7043 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7045 case I40E_MAC_HASH_MATCH:
7046 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7047 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7049 case I40E_MACVLAN_HASH_MATCH:
7050 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7053 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7054 ret = I40E_ERR_PARAM;
7057 req_list[i].flags = rte_cpu_to_le_16(flags);
7060 ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, req_list,
7061 actual_num, NULL, &aq_status);
7063 if (ret != I40E_SUCCESS) {
7064 /* Do not report as an error when firmware returns ENOENT */
7065 if (aq_status == I40E_AQ_RC_ENOENT) {
7068 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7073 } while (num < total);
7080 /* Find out specific MAC filter */
7081 static struct i40e_mac_filter *
7082 i40e_find_mac_filter(struct i40e_vsi *vsi,
7083 struct rte_ether_addr *macaddr)
7085 struct i40e_mac_filter *f;
7087 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7088 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7096 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7099 uint32_t vid_idx, vid_bit;
7101 if (vlan_id > ETH_VLAN_ID_MAX)
7104 vid_idx = I40E_VFTA_IDX(vlan_id);
7105 vid_bit = I40E_VFTA_BIT(vlan_id);
7107 if (vsi->vfta[vid_idx] & vid_bit)
7114 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7115 uint16_t vlan_id, bool on)
7117 uint32_t vid_idx, vid_bit;
7119 vid_idx = I40E_VFTA_IDX(vlan_id);
7120 vid_bit = I40E_VFTA_BIT(vlan_id);
7123 vsi->vfta[vid_idx] |= vid_bit;
7125 vsi->vfta[vid_idx] &= ~vid_bit;
7129 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7130 uint16_t vlan_id, bool on)
7132 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7133 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7136 if (vlan_id > ETH_VLAN_ID_MAX)
7139 i40e_store_vlan_filter(vsi, vlan_id, on);
7141 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7144 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7147 ret = i40e_aq_add_vlan(hw, vsi->seid,
7148 &vlan_data, 1, NULL);
7149 if (ret != I40E_SUCCESS)
7150 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7152 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7153 &vlan_data, 1, NULL);
7154 if (ret != I40E_SUCCESS)
7156 "Failed to remove vlan filter");
7161 * Find all vlan options for specific mac addr,
7162 * return with actual vlan found.
7165 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7166 struct i40e_macvlan_filter *mv_f,
7167 int num, struct rte_ether_addr *addr)
7173 * Not to use i40e_find_vlan_filter to decrease the loop time,
7174 * although the code looks complex.
7176 if (num < vsi->vlan_num)
7177 return I40E_ERR_PARAM;
7180 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7182 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7183 if (vsi->vfta[j] & (1 << k)) {
7186 "vlan number doesn't match");
7187 return I40E_ERR_PARAM;
7189 rte_memcpy(&mv_f[i].macaddr,
7190 addr, ETH_ADDR_LEN);
7192 j * I40E_UINT32_BIT_SIZE + k;
7198 return I40E_SUCCESS;
7202 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7203 struct i40e_macvlan_filter *mv_f,
7208 struct i40e_mac_filter *f;
7210 if (num < vsi->mac_num)
7211 return I40E_ERR_PARAM;
7213 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7215 PMD_DRV_LOG(ERR, "buffer number not match");
7216 return I40E_ERR_PARAM;
7218 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7220 mv_f[i].vlan_id = vlan;
7221 mv_f[i].filter_type = f->mac_info.filter_type;
7225 return I40E_SUCCESS;
7229 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7232 struct i40e_mac_filter *f;
7233 struct i40e_macvlan_filter *mv_f;
7234 int ret = I40E_SUCCESS;
7236 if (vsi == NULL || vsi->mac_num == 0)
7237 return I40E_ERR_PARAM;
7239 /* Case that no vlan is set */
7240 if (vsi->vlan_num == 0)
7243 num = vsi->mac_num * vsi->vlan_num;
7245 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7247 PMD_DRV_LOG(ERR, "failed to allocate memory");
7248 return I40E_ERR_NO_MEMORY;
7252 if (vsi->vlan_num == 0) {
7253 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7254 rte_memcpy(&mv_f[i].macaddr,
7255 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7256 mv_f[i].filter_type = f->mac_info.filter_type;
7257 mv_f[i].vlan_id = 0;
7261 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7262 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7263 vsi->vlan_num, &f->mac_info.mac_addr);
7264 if (ret != I40E_SUCCESS)
7266 for (j = i; j < i + vsi->vlan_num; j++)
7267 mv_f[j].filter_type = f->mac_info.filter_type;
7272 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7280 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7282 struct i40e_macvlan_filter *mv_f;
7284 int ret = I40E_SUCCESS;
7286 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7287 return I40E_ERR_PARAM;
7289 /* If it's already set, just return */
7290 if (i40e_find_vlan_filter(vsi,vlan))
7291 return I40E_SUCCESS;
7293 mac_num = vsi->mac_num;
7296 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7297 return I40E_ERR_PARAM;
7300 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7303 PMD_DRV_LOG(ERR, "failed to allocate memory");
7304 return I40E_ERR_NO_MEMORY;
7307 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7309 if (ret != I40E_SUCCESS)
7312 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7314 if (ret != I40E_SUCCESS)
7317 i40e_set_vlan_filter(vsi, vlan, 1);
7327 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7329 struct i40e_macvlan_filter *mv_f;
7331 int ret = I40E_SUCCESS;
7334 * Vlan 0 is the generic filter for untagged packets
7335 * and can't be removed.
7337 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7338 return I40E_ERR_PARAM;
7340 /* If can't find it, just return */
7341 if (!i40e_find_vlan_filter(vsi, vlan))
7342 return I40E_ERR_PARAM;
7344 mac_num = vsi->mac_num;
7347 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7348 return I40E_ERR_PARAM;
7351 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7354 PMD_DRV_LOG(ERR, "failed to allocate memory");
7355 return I40E_ERR_NO_MEMORY;
7358 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7360 if (ret != I40E_SUCCESS)
7363 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7365 if (ret != I40E_SUCCESS)
7368 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7369 if (vsi->vlan_num == 1) {
7370 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7371 if (ret != I40E_SUCCESS)
7374 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7375 if (ret != I40E_SUCCESS)
7379 i40e_set_vlan_filter(vsi, vlan, 0);
7389 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7391 struct i40e_mac_filter *f;
7392 struct i40e_macvlan_filter *mv_f;
7393 int i, vlan_num = 0;
7394 int ret = I40E_SUCCESS;
7396 /* If it's add and we've config it, return */
7397 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7399 return I40E_SUCCESS;
7400 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7401 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7404 * If vlan_num is 0, that's the first time to add mac,
7405 * set mask for vlan_id 0.
7407 if (vsi->vlan_num == 0) {
7408 i40e_set_vlan_filter(vsi, 0, 1);
7411 vlan_num = vsi->vlan_num;
7412 } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7413 mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7416 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7418 PMD_DRV_LOG(ERR, "failed to allocate memory");
7419 return I40E_ERR_NO_MEMORY;
7422 for (i = 0; i < vlan_num; i++) {
7423 mv_f[i].filter_type = mac_filter->filter_type;
7424 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7428 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7429 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7430 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7431 &mac_filter->mac_addr);
7432 if (ret != I40E_SUCCESS)
7436 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7437 if (ret != I40E_SUCCESS)
7440 /* Add the mac addr into mac list */
7441 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7443 PMD_DRV_LOG(ERR, "failed to allocate memory");
7444 ret = I40E_ERR_NO_MEMORY;
7447 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7449 f->mac_info.filter_type = mac_filter->filter_type;
7450 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7461 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7463 struct i40e_mac_filter *f;
7464 struct i40e_macvlan_filter *mv_f;
7466 enum i40e_mac_filter_type filter_type;
7467 int ret = I40E_SUCCESS;
7469 /* Can't find it, return an error */
7470 f = i40e_find_mac_filter(vsi, addr);
7472 return I40E_ERR_PARAM;
7474 vlan_num = vsi->vlan_num;
7475 filter_type = f->mac_info.filter_type;
7476 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7477 filter_type == I40E_MACVLAN_HASH_MATCH) {
7478 if (vlan_num == 0) {
7479 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7480 return I40E_ERR_PARAM;
7482 } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7483 filter_type == I40E_MAC_HASH_MATCH)
7486 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7488 PMD_DRV_LOG(ERR, "failed to allocate memory");
7489 return I40E_ERR_NO_MEMORY;
7492 for (i = 0; i < vlan_num; i++) {
7493 mv_f[i].filter_type = filter_type;
7494 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7497 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7498 filter_type == I40E_MACVLAN_HASH_MATCH) {
7499 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7500 if (ret != I40E_SUCCESS)
7504 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7505 if (ret != I40E_SUCCESS)
7508 /* Remove the mac addr into mac list */
7509 TAILQ_REMOVE(&vsi->mac_list, f, next);
7519 /* Configure hash enable flags for RSS */
7521 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7529 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7530 if (flags & (1ULL << i))
7531 hena |= adapter->pctypes_tbl[i];
7537 /* Parse the hash enable flags */
7539 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7541 uint64_t rss_hf = 0;
7547 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7548 if (flags & adapter->pctypes_tbl[i])
7549 rss_hf |= (1ULL << i);
7556 i40e_pf_disable_rss(struct i40e_pf *pf)
7558 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7560 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7561 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7562 I40E_WRITE_FLUSH(hw);
7566 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7568 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7569 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7570 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7571 I40E_VFQF_HKEY_MAX_INDEX :
7572 I40E_PFQF_HKEY_MAX_INDEX;
7574 if (!key || key_len == 0) {
7575 PMD_DRV_LOG(DEBUG, "No key to be configured");
7577 } else if (key_len != (key_idx + 1) *
7579 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7583 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7584 struct i40e_aqc_get_set_rss_key_data *key_dw =
7585 (struct i40e_aqc_get_set_rss_key_data *)key;
7586 enum i40e_status_code status =
7587 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7591 "Failed to configure RSS key via AQ, error status: %d",
7596 uint32_t *hash_key = (uint32_t *)key;
7599 if (vsi->type == I40E_VSI_SRIOV) {
7600 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7603 I40E_VFQF_HKEY1(i, vsi->user_param),
7607 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7608 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7611 I40E_WRITE_FLUSH(hw);
7618 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7620 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7621 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7625 if (!key || !key_len)
7628 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7629 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7630 (struct i40e_aqc_get_set_rss_key_data *)key);
7632 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7636 uint32_t *key_dw = (uint32_t *)key;
7639 if (vsi->type == I40E_VSI_SRIOV) {
7640 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7641 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7642 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7644 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7647 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7648 reg = I40E_PFQF_HKEY(i);
7649 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7651 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7659 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7661 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7665 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7666 rss_conf->rss_key_len);
7670 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7671 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7672 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7673 I40E_WRITE_FLUSH(hw);
7679 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7680 struct rte_eth_rss_conf *rss_conf)
7682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7684 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7687 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7688 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7690 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7691 if (rss_hf != 0) /* Enable RSS */
7693 return 0; /* Nothing to do */
7696 if (rss_hf == 0) /* Disable RSS */
7699 return i40e_hw_rss_hash_set(pf, rss_conf);
7703 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7704 struct rte_eth_rss_conf *rss_conf)
7706 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7707 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7714 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7715 &rss_conf->rss_key_len);
7719 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7720 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7721 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7727 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7729 switch (filter_type) {
7730 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7731 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7733 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7734 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7736 case RTE_TUNNEL_FILTER_IMAC_TENID:
7737 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7739 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7740 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7742 case ETH_TUNNEL_FILTER_IMAC:
7743 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7745 case ETH_TUNNEL_FILTER_OIP:
7746 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7748 case ETH_TUNNEL_FILTER_IIP:
7749 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7752 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7759 /* Convert tunnel filter structure */
7761 i40e_tunnel_filter_convert(
7762 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7763 struct i40e_tunnel_filter *tunnel_filter)
7765 rte_ether_addr_copy((struct rte_ether_addr *)
7766 &cld_filter->element.outer_mac,
7767 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7768 rte_ether_addr_copy((struct rte_ether_addr *)
7769 &cld_filter->element.inner_mac,
7770 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7771 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7772 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7773 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7774 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7775 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7777 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7778 tunnel_filter->input.flags = cld_filter->element.flags;
7779 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7780 tunnel_filter->queue = cld_filter->element.queue_number;
7781 rte_memcpy(tunnel_filter->input.general_fields,
7782 cld_filter->general_fields,
7783 sizeof(cld_filter->general_fields));
7788 /* Check if there exists the tunnel filter */
7789 struct i40e_tunnel_filter *
7790 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7791 const struct i40e_tunnel_filter_input *input)
7795 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7799 return tunnel_rule->hash_map[ret];
7802 /* Add a tunnel filter into the SW list */
7804 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7805 struct i40e_tunnel_filter *tunnel_filter)
7807 struct i40e_tunnel_rule *rule = &pf->tunnel;
7810 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7813 "Failed to insert tunnel filter to hash table %d!",
7817 rule->hash_map[ret] = tunnel_filter;
7819 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7824 /* Delete a tunnel filter from the SW list */
7826 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7827 struct i40e_tunnel_filter_input *input)
7829 struct i40e_tunnel_rule *rule = &pf->tunnel;
7830 struct i40e_tunnel_filter *tunnel_filter;
7833 ret = rte_hash_del_key(rule->hash_table, input);
7836 "Failed to delete tunnel filter to hash table %d!",
7840 tunnel_filter = rule->hash_map[ret];
7841 rule->hash_map[ret] = NULL;
7843 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7844 rte_free(tunnel_filter);
7849 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7850 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7851 #define I40E_TR_GENEVE_KEY_MASK 0x8
7852 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7853 #define I40E_TR_GRE_KEY_MASK 0x400
7854 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7855 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7856 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7857 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7858 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7859 #define I40E_DIRECTION_INGRESS_KEY 0x8000
7860 #define I40E_TR_L4_TYPE_TCP 0x2
7861 #define I40E_TR_L4_TYPE_UDP 0x4
7862 #define I40E_TR_L4_TYPE_SCTP 0x8
7865 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7867 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7868 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7869 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7870 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7871 enum i40e_status_code status = I40E_SUCCESS;
7873 if (pf->support_multi_driver) {
7874 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7875 return I40E_NOT_SUPPORTED;
7878 memset(&filter_replace, 0,
7879 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7880 memset(&filter_replace_buf, 0,
7881 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7883 /* create L1 filter */
7884 filter_replace.old_filter_type =
7885 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7886 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7887 filter_replace.tr_bit = 0;
7889 /* Prepare the buffer, 3 entries */
7890 filter_replace_buf.data[0] =
7891 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7892 filter_replace_buf.data[0] |=
7893 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7894 filter_replace_buf.data[2] = 0xFF;
7895 filter_replace_buf.data[3] = 0xFF;
7896 filter_replace_buf.data[4] =
7897 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7898 filter_replace_buf.data[4] |=
7899 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7900 filter_replace_buf.data[7] = 0xF0;
7901 filter_replace_buf.data[8]
7902 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7903 filter_replace_buf.data[8] |=
7904 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7905 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7906 I40E_TR_GENEVE_KEY_MASK |
7907 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7908 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7909 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7910 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7912 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7913 &filter_replace_buf);
7914 if (!status && (filter_replace.old_filter_type !=
7915 filter_replace.new_filter_type))
7916 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7917 " original: 0x%x, new: 0x%x",
7919 filter_replace.old_filter_type,
7920 filter_replace.new_filter_type);
7926 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7928 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7929 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7930 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7931 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7932 enum i40e_status_code status = I40E_SUCCESS;
7934 if (pf->support_multi_driver) {
7935 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7936 return I40E_NOT_SUPPORTED;
7940 memset(&filter_replace, 0,
7941 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7942 memset(&filter_replace_buf, 0,
7943 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7944 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7945 I40E_AQC_MIRROR_CLOUD_FILTER;
7946 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7947 filter_replace.new_filter_type =
7948 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7949 /* Prepare the buffer, 2 entries */
7950 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7951 filter_replace_buf.data[0] |=
7952 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7953 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7954 filter_replace_buf.data[4] |=
7955 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7956 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7957 &filter_replace_buf);
7960 if (filter_replace.old_filter_type !=
7961 filter_replace.new_filter_type)
7962 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7963 " original: 0x%x, new: 0x%x",
7965 filter_replace.old_filter_type,
7966 filter_replace.new_filter_type);
7969 memset(&filter_replace, 0,
7970 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7971 memset(&filter_replace_buf, 0,
7972 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7974 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7975 I40E_AQC_MIRROR_CLOUD_FILTER;
7976 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7977 filter_replace.new_filter_type =
7978 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7979 /* Prepare the buffer, 2 entries */
7980 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7981 filter_replace_buf.data[0] |=
7982 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7983 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7984 filter_replace_buf.data[4] |=
7985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7987 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7988 &filter_replace_buf);
7989 if (!status && (filter_replace.old_filter_type !=
7990 filter_replace.new_filter_type))
7991 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7992 " original: 0x%x, new: 0x%x",
7994 filter_replace.old_filter_type,
7995 filter_replace.new_filter_type);
8000 static enum i40e_status_code
8001 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8003 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8004 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8005 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8006 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8007 enum i40e_status_code status = I40E_SUCCESS;
8009 if (pf->support_multi_driver) {
8010 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8011 return I40E_NOT_SUPPORTED;
8015 memset(&filter_replace, 0,
8016 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8017 memset(&filter_replace_buf, 0,
8018 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8019 /* create L1 filter */
8020 filter_replace.old_filter_type =
8021 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8022 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8023 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8024 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8025 /* Prepare the buffer, 2 entries */
8026 filter_replace_buf.data[0] =
8027 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8028 filter_replace_buf.data[0] |=
8029 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8030 filter_replace_buf.data[2] = 0xFF;
8031 filter_replace_buf.data[3] = 0xFF;
8032 filter_replace_buf.data[4] =
8033 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8034 filter_replace_buf.data[4] |=
8035 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8036 filter_replace_buf.data[6] = 0xFF;
8037 filter_replace_buf.data[7] = 0xFF;
8038 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8039 &filter_replace_buf);
8042 if (filter_replace.old_filter_type !=
8043 filter_replace.new_filter_type)
8044 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8045 " original: 0x%x, new: 0x%x",
8047 filter_replace.old_filter_type,
8048 filter_replace.new_filter_type);
8051 memset(&filter_replace, 0,
8052 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8053 memset(&filter_replace_buf, 0,
8054 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8055 /* create L1 filter */
8056 filter_replace.old_filter_type =
8057 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8058 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8059 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8060 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8061 /* Prepare the buffer, 2 entries */
8062 filter_replace_buf.data[0] =
8063 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8064 filter_replace_buf.data[0] |=
8065 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8066 filter_replace_buf.data[2] = 0xFF;
8067 filter_replace_buf.data[3] = 0xFF;
8068 filter_replace_buf.data[4] =
8069 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8070 filter_replace_buf.data[4] |=
8071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072 filter_replace_buf.data[6] = 0xFF;
8073 filter_replace_buf.data[7] = 0xFF;
8075 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8076 &filter_replace_buf);
8077 if (!status && (filter_replace.old_filter_type !=
8078 filter_replace.new_filter_type))
8079 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8080 " original: 0x%x, new: 0x%x",
8082 filter_replace.old_filter_type,
8083 filter_replace.new_filter_type);
8089 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8091 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8092 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8093 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8094 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8095 enum i40e_status_code status = I40E_SUCCESS;
8097 if (pf->support_multi_driver) {
8098 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8099 return I40E_NOT_SUPPORTED;
8103 memset(&filter_replace, 0,
8104 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8105 memset(&filter_replace_buf, 0,
8106 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8107 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8108 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8109 filter_replace.new_filter_type =
8110 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8111 /* Prepare the buffer, 2 entries */
8112 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8113 filter_replace_buf.data[0] |=
8114 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8115 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8116 filter_replace_buf.data[4] |=
8117 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8118 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8119 &filter_replace_buf);
8122 if (filter_replace.old_filter_type !=
8123 filter_replace.new_filter_type)
8124 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8125 " original: 0x%x, new: 0x%x",
8127 filter_replace.old_filter_type,
8128 filter_replace.new_filter_type);
8131 memset(&filter_replace, 0,
8132 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8133 memset(&filter_replace_buf, 0,
8134 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8135 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8136 filter_replace.old_filter_type =
8137 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8138 filter_replace.new_filter_type =
8139 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8140 /* Prepare the buffer, 2 entries */
8141 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8142 filter_replace_buf.data[0] |=
8143 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8144 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8145 filter_replace_buf.data[4] |=
8146 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8148 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8149 &filter_replace_buf);
8150 if (!status && (filter_replace.old_filter_type !=
8151 filter_replace.new_filter_type))
8152 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8153 " original: 0x%x, new: 0x%x",
8155 filter_replace.old_filter_type,
8156 filter_replace.new_filter_type);
8161 static enum i40e_status_code
8162 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8163 enum i40e_l4_port_type l4_port_type)
8165 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8166 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8167 enum i40e_status_code status = I40E_SUCCESS;
8168 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8169 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8171 if (pf->support_multi_driver) {
8172 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8173 return I40E_NOT_SUPPORTED;
8176 memset(&filter_replace, 0,
8177 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8178 memset(&filter_replace_buf, 0,
8179 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8181 /* create L1 filter */
8182 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8183 filter_replace.old_filter_type =
8184 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8185 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8186 filter_replace_buf.data[8] =
8187 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8189 filter_replace.old_filter_type =
8190 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8191 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8192 filter_replace_buf.data[8] =
8193 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8196 filter_replace.tr_bit = 0;
8197 /* Prepare the buffer, 3 entries */
8198 filter_replace_buf.data[0] =
8199 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8200 filter_replace_buf.data[0] |=
8201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8202 filter_replace_buf.data[2] = 0x00;
8203 filter_replace_buf.data[3] =
8204 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8205 filter_replace_buf.data[4] =
8206 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8207 filter_replace_buf.data[4] |=
8208 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8209 filter_replace_buf.data[5] = 0x00;
8210 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8211 I40E_TR_L4_TYPE_TCP |
8212 I40E_TR_L4_TYPE_SCTP;
8213 filter_replace_buf.data[7] = 0x00;
8214 filter_replace_buf.data[8] |=
8215 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8216 filter_replace_buf.data[9] = 0x00;
8217 filter_replace_buf.data[10] = 0xFF;
8218 filter_replace_buf.data[11] = 0xFF;
8220 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8221 &filter_replace_buf);
8222 if (!status && filter_replace.old_filter_type !=
8223 filter_replace.new_filter_type)
8224 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8225 " original: 0x%x, new: 0x%x",
8227 filter_replace.old_filter_type,
8228 filter_replace.new_filter_type);
8233 static enum i40e_status_code
8234 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8235 enum i40e_l4_port_type l4_port_type)
8237 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8238 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8239 enum i40e_status_code status = I40E_SUCCESS;
8240 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8241 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8243 if (pf->support_multi_driver) {
8244 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8245 return I40E_NOT_SUPPORTED;
8248 memset(&filter_replace, 0,
8249 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8250 memset(&filter_replace_buf, 0,
8251 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8253 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8254 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8255 filter_replace.new_filter_type =
8256 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8257 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8259 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8260 filter_replace.new_filter_type =
8261 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8262 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8265 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8266 filter_replace.tr_bit = 0;
8267 /* Prepare the buffer, 2 entries */
8268 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8269 filter_replace_buf.data[0] |=
8270 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8271 filter_replace_buf.data[4] |=
8272 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8273 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8274 &filter_replace_buf);
8276 if (!status && filter_replace.old_filter_type !=
8277 filter_replace.new_filter_type)
8278 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8279 " original: 0x%x, new: 0x%x",
8281 filter_replace.old_filter_type,
8282 filter_replace.new_filter_type);
8288 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8289 struct i40e_tunnel_filter_conf *tunnel_filter,
8293 uint32_t ipv4_addr, ipv4_addr_le;
8294 uint8_t i, tun_type = 0;
8295 /* internal variable to convert ipv6 byte order */
8296 uint32_t convert_ipv6[4];
8298 struct i40e_pf_vf *vf = NULL;
8299 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8300 struct i40e_vsi *vsi;
8301 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8302 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8303 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8304 struct i40e_tunnel_filter *tunnel, *node;
8305 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8307 bool big_buffer = 0;
8309 cld_filter = rte_zmalloc("tunnel_filter",
8310 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8313 if (cld_filter == NULL) {
8314 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8317 pfilter = cld_filter;
8319 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8320 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8321 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8322 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8324 pfilter->element.inner_vlan =
8325 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8326 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8327 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8328 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8329 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8330 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8332 sizeof(pfilter->element.ipaddr.v4.data));
8334 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8335 for (i = 0; i < 4; i++) {
8337 rte_cpu_to_le_32(rte_be_to_cpu_32(
8338 tunnel_filter->ip_addr.ipv6_addr[i]));
8340 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8342 sizeof(pfilter->element.ipaddr.v6.data));
8345 /* check tunneled type */
8346 switch (tunnel_filter->tunnel_type) {
8347 case I40E_TUNNEL_TYPE_VXLAN:
8348 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8350 case I40E_TUNNEL_TYPE_NVGRE:
8351 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8353 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8354 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8356 case I40E_TUNNEL_TYPE_MPLSoUDP:
8357 if (!pf->mpls_replace_flag) {
8358 i40e_replace_mpls_l1_filter(pf);
8359 i40e_replace_mpls_cloud_filter(pf);
8360 pf->mpls_replace_flag = 1;
8362 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8363 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8365 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8366 (teid_le & 0xF) << 12;
8367 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8370 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8372 case I40E_TUNNEL_TYPE_MPLSoGRE:
8373 if (!pf->mpls_replace_flag) {
8374 i40e_replace_mpls_l1_filter(pf);
8375 i40e_replace_mpls_cloud_filter(pf);
8376 pf->mpls_replace_flag = 1;
8378 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8379 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8381 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8382 (teid_le & 0xF) << 12;
8383 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8386 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8388 case I40E_TUNNEL_TYPE_GTPC:
8389 if (!pf->gtp_replace_flag) {
8390 i40e_replace_gtp_l1_filter(pf);
8391 i40e_replace_gtp_cloud_filter(pf);
8392 pf->gtp_replace_flag = 1;
8394 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8395 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8396 (teid_le >> 16) & 0xFFFF;
8397 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8399 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8403 case I40E_TUNNEL_TYPE_GTPU:
8404 if (!pf->gtp_replace_flag) {
8405 i40e_replace_gtp_l1_filter(pf);
8406 i40e_replace_gtp_cloud_filter(pf);
8407 pf->gtp_replace_flag = 1;
8409 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8410 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8411 (teid_le >> 16) & 0xFFFF;
8412 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8414 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8418 case I40E_TUNNEL_TYPE_QINQ:
8419 if (!pf->qinq_replace_flag) {
8420 ret = i40e_cloud_filter_qinq_create(pf);
8423 "QinQ tunnel filter already created.");
8424 pf->qinq_replace_flag = 1;
8426 /* Add in the General fields the values of
8427 * the Outer and Inner VLAN
8428 * Big Buffer should be set, see changes in
8429 * i40e_aq_add_cloud_filters
8431 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8432 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8435 case I40E_CLOUD_TYPE_UDP:
8436 case I40E_CLOUD_TYPE_TCP:
8437 case I40E_CLOUD_TYPE_SCTP:
8438 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8439 if (!pf->sport_replace_flag) {
8440 i40e_replace_port_l1_filter(pf,
8441 tunnel_filter->l4_port_type);
8442 i40e_replace_port_cloud_filter(pf,
8443 tunnel_filter->l4_port_type);
8444 pf->sport_replace_flag = 1;
8446 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8447 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8448 I40E_DIRECTION_INGRESS_KEY;
8450 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8451 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8452 I40E_TR_L4_TYPE_UDP;
8453 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8454 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8455 I40E_TR_L4_TYPE_TCP;
8457 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8458 I40E_TR_L4_TYPE_SCTP;
8460 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8461 (teid_le >> 16) & 0xFFFF;
8464 if (!pf->dport_replace_flag) {
8465 i40e_replace_port_l1_filter(pf,
8466 tunnel_filter->l4_port_type);
8467 i40e_replace_port_cloud_filter(pf,
8468 tunnel_filter->l4_port_type);
8469 pf->dport_replace_flag = 1;
8471 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8472 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8473 I40E_DIRECTION_INGRESS_KEY;
8475 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8476 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8477 I40E_TR_L4_TYPE_UDP;
8478 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8479 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8480 I40E_TR_L4_TYPE_TCP;
8482 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8483 I40E_TR_L4_TYPE_SCTP;
8485 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8486 (teid_le >> 16) & 0xFFFF;
8492 /* Other tunnel types is not supported. */
8493 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8494 rte_free(cld_filter);
8498 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8499 pfilter->element.flags =
8500 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8501 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8502 pfilter->element.flags =
8503 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8504 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8505 pfilter->element.flags =
8506 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8507 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8508 pfilter->element.flags =
8509 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8510 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8511 pfilter->element.flags |=
8512 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8513 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8514 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8515 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8516 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8517 pfilter->element.flags |=
8518 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8520 pfilter->element.flags |=
8521 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8523 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8524 &pfilter->element.flags);
8526 rte_free(cld_filter);
8531 pfilter->element.flags |= rte_cpu_to_le_16(
8532 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8533 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8534 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8535 pfilter->element.queue_number =
8536 rte_cpu_to_le_16(tunnel_filter->queue_id);
8538 if (!tunnel_filter->is_to_vf)
8541 if (tunnel_filter->vf_id >= pf->vf_num) {
8542 PMD_DRV_LOG(ERR, "Invalid argument.");
8543 rte_free(cld_filter);
8546 vf = &pf->vfs[tunnel_filter->vf_id];
8550 /* Check if there is the filter in SW list */
8551 memset(&check_filter, 0, sizeof(check_filter));
8552 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8553 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8554 check_filter.vf_id = tunnel_filter->vf_id;
8555 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8557 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8558 rte_free(cld_filter);
8562 if (!add && !node) {
8563 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8564 rte_free(cld_filter);
8570 ret = i40e_aq_add_cloud_filters_bb(hw,
8571 vsi->seid, cld_filter, 1);
8573 ret = i40e_aq_add_cloud_filters(hw,
8574 vsi->seid, &cld_filter->element, 1);
8576 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8577 rte_free(cld_filter);
8580 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8581 if (tunnel == NULL) {
8582 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8583 rte_free(cld_filter);
8587 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8588 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8593 ret = i40e_aq_rem_cloud_filters_bb(
8594 hw, vsi->seid, cld_filter, 1);
8596 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8597 &cld_filter->element, 1);
8599 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8600 rte_free(cld_filter);
8603 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8606 rte_free(cld_filter);
8611 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8615 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8616 if (pf->vxlan_ports[i] == port)
8624 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8627 uint8_t filter_idx = 0;
8628 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8630 idx = i40e_get_vxlan_port_idx(pf, port);
8632 /* Check if port already exists */
8634 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8638 /* Now check if there is space to add the new port */
8639 idx = i40e_get_vxlan_port_idx(pf, 0);
8642 "Maximum number of UDP ports reached, not adding port %d",
8647 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8650 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8654 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8657 /* New port: add it and mark its index in the bitmap */
8658 pf->vxlan_ports[idx] = port;
8659 pf->vxlan_bitmap |= (1 << idx);
8661 if (!(pf->flags & I40E_FLAG_VXLAN))
8662 pf->flags |= I40E_FLAG_VXLAN;
8668 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8671 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8673 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8674 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8678 idx = i40e_get_vxlan_port_idx(pf, port);
8681 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8685 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8686 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8690 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8693 pf->vxlan_ports[idx] = 0;
8694 pf->vxlan_bitmap &= ~(1 << idx);
8696 if (!pf->vxlan_bitmap)
8697 pf->flags &= ~I40E_FLAG_VXLAN;
8702 /* Add UDP tunneling port */
8704 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8705 struct rte_eth_udp_tunnel *udp_tunnel)
8708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8710 if (udp_tunnel == NULL)
8713 switch (udp_tunnel->prot_type) {
8714 case RTE_TUNNEL_TYPE_VXLAN:
8715 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8716 I40E_AQC_TUNNEL_TYPE_VXLAN);
8718 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8719 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8720 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8722 case RTE_TUNNEL_TYPE_GENEVE:
8723 case RTE_TUNNEL_TYPE_TEREDO:
8724 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8729 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8737 /* Remove UDP tunneling port */
8739 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8740 struct rte_eth_udp_tunnel *udp_tunnel)
8743 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8745 if (udp_tunnel == NULL)
8748 switch (udp_tunnel->prot_type) {
8749 case RTE_TUNNEL_TYPE_VXLAN:
8750 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8751 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8753 case RTE_TUNNEL_TYPE_GENEVE:
8754 case RTE_TUNNEL_TYPE_TEREDO:
8755 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8759 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8767 /* Calculate the maximum number of contiguous PF queues that are configured */
8769 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8771 struct rte_eth_dev_data *data = pf->dev_data;
8773 struct i40e_rx_queue *rxq;
8776 for (i = 0; i < pf->lan_nb_qps; i++) {
8777 rxq = data->rx_queues[i];
8778 if (rxq && rxq->q_set)
8787 /* Reset the global configure of hash function and input sets */
8789 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8791 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8792 uint32_t reg, reg_val;
8795 /* Reset global RSS function sets */
8796 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8797 if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8798 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8799 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8802 for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8806 if (hw->mac.type == I40E_MAC_X722)
8807 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8811 /* Reset pctype insets */
8812 inset = i40e_get_default_input_set(i);
8814 pf->hash_input_set[pctype] = inset;
8815 inset = i40e_translate_input_set_reg(hw->mac.type,
8818 reg = I40E_GLQF_HASH_INSET(0, pctype);
8819 i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8820 reg = I40E_GLQF_HASH_INSET(1, pctype);
8821 i40e_check_write_global_reg(hw, reg,
8822 (uint32_t)(inset >> 32));
8824 /* Clear unused mask registers of the pctype */
8825 for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8826 reg = I40E_GLQF_HASH_MSK(j, pctype);
8827 i40e_check_write_global_reg(hw, reg, 0);
8831 /* Reset pctype symmetric sets */
8832 reg = I40E_GLQF_HSYM(pctype);
8833 reg_val = i40e_read_rx_ctl(hw, reg);
8834 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8835 reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8836 i40e_write_global_rx_ctl(hw, reg, reg_val);
8839 I40E_WRITE_FLUSH(hw);
8843 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8845 struct i40e_hw *hw = &pf->adapter->hw;
8846 uint8_t lut[ETH_RSS_RETA_SIZE_512];
8850 /* If both VMDQ and RSS enabled, not all of PF queues are
8851 * configured. It's necessary to calculate the actual PF
8852 * queues that are configured.
8854 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8855 num = i40e_pf_calc_configured_queues_num(pf);
8857 num = pf->dev_data->nb_rx_queues;
8859 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8863 for (i = 0; i < hw->func_caps.rss_table_size; i++)
8864 lut[i] = (uint8_t)(i % (uint32_t)num);
8866 return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8870 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8872 const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8877 rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8879 pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8880 static uint32_t rss_key_default[] = {0x6b793944,
8881 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8882 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8883 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8885 rss_key = (uint8_t *)rss_key_default;
8888 return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8892 i40e_pf_rss_reset(struct i40e_pf *pf)
8894 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8898 pf->hash_filter_enabled = 0;
8899 i40e_pf_disable_rss(pf);
8900 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8902 if (!pf->support_multi_driver)
8903 i40e_pf_global_rss_reset(pf);
8905 /* Reset RETA table */
8906 if (pf->adapter->rss_reta_updated == 0) {
8907 ret = i40e_pf_reset_rss_reta(pf);
8912 return i40e_pf_reset_rss_key(pf);
8917 i40e_pf_config_rss(struct i40e_pf *pf)
8920 enum rte_eth_rx_mq_mode mq_mode;
8921 uint64_t rss_hf, hena;
8924 ret = i40e_pf_rss_reset(pf);
8926 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8930 rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8931 mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8932 if (!(rss_hf & pf->adapter->flow_types_mask) ||
8933 !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8936 hw = I40E_PF_TO_HW(pf);
8937 hena = i40e_config_hena(pf->adapter, rss_hf);
8938 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8939 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8940 I40E_WRITE_FLUSH(hw);
8945 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8946 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8948 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8950 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8954 if (pf->support_multi_driver) {
8955 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8959 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8960 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8963 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8964 } else if (len == 4) {
8965 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8967 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8972 ret = i40e_aq_debug_write_global_register(hw,
8973 I40E_GL_PRS_FVBM(2),
8977 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8978 "with value 0x%08x",
8979 I40E_GL_PRS_FVBM(2), reg);
8983 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8984 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8989 /* Set the symmetric hash enable configurations per port */
8991 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8993 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8996 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
8999 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9001 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9004 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9006 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9007 I40E_WRITE_FLUSH(hw);
9011 * Valid input sets for hash and flow director filters per PCTYPE
9014 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9015 enum rte_filter_type filter)
9019 static const uint64_t valid_hash_inset_table[] = {
9020 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9021 I40E_INSET_DMAC | I40E_INSET_SMAC |
9022 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9023 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9024 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9025 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9026 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9027 I40E_INSET_FLEX_PAYLOAD,
9028 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9029 I40E_INSET_DMAC | I40E_INSET_SMAC |
9030 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9031 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9032 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9033 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9034 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9035 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9036 I40E_INSET_FLEX_PAYLOAD,
9037 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9038 I40E_INSET_DMAC | I40E_INSET_SMAC |
9039 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9040 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9041 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9042 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9043 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9044 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9045 I40E_INSET_FLEX_PAYLOAD,
9046 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9047 I40E_INSET_DMAC | I40E_INSET_SMAC |
9048 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9049 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9050 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9051 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9052 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9053 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9054 I40E_INSET_FLEX_PAYLOAD,
9055 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9056 I40E_INSET_DMAC | I40E_INSET_SMAC |
9057 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9058 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9059 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9060 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9061 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9062 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9063 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9064 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9065 I40E_INSET_DMAC | I40E_INSET_SMAC |
9066 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9067 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9068 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9069 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9070 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9071 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9072 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9073 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9074 I40E_INSET_DMAC | I40E_INSET_SMAC |
9075 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9076 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9077 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9078 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9079 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9080 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9081 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9082 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9083 I40E_INSET_DMAC | I40E_INSET_SMAC |
9084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9086 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9087 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9088 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9089 I40E_INSET_FLEX_PAYLOAD,
9090 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9091 I40E_INSET_DMAC | I40E_INSET_SMAC |
9092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9094 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9095 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9096 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9097 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9098 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9099 I40E_INSET_DMAC | I40E_INSET_SMAC |
9100 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9101 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9102 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9103 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9104 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9105 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9106 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9107 I40E_INSET_DMAC | I40E_INSET_SMAC |
9108 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9109 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9110 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9111 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9112 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9113 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9114 I40E_INSET_FLEX_PAYLOAD,
9115 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9116 I40E_INSET_DMAC | I40E_INSET_SMAC |
9117 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9118 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9119 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9120 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9121 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9122 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9123 I40E_INSET_FLEX_PAYLOAD,
9124 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9125 I40E_INSET_DMAC | I40E_INSET_SMAC |
9126 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9127 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9128 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9129 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9130 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9131 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9132 I40E_INSET_FLEX_PAYLOAD,
9133 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9134 I40E_INSET_DMAC | I40E_INSET_SMAC |
9135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9137 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9138 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9139 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9140 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9141 I40E_INSET_FLEX_PAYLOAD,
9142 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9143 I40E_INSET_DMAC | I40E_INSET_SMAC |
9144 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9146 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9147 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9148 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9149 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9150 I40E_INSET_FLEX_PAYLOAD,
9151 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9152 I40E_INSET_DMAC | I40E_INSET_SMAC |
9153 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9155 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9156 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9157 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9158 I40E_INSET_FLEX_PAYLOAD,
9159 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9160 I40E_INSET_DMAC | I40E_INSET_SMAC |
9161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9162 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9163 I40E_INSET_FLEX_PAYLOAD,
9167 * Flow director supports only fields defined in
9168 * union rte_eth_fdir_flow.
9170 static const uint64_t valid_fdir_inset_table[] = {
9171 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9173 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9174 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9175 I40E_INSET_IPV4_TTL,
9176 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9177 I40E_INSET_DMAC | I40E_INSET_SMAC |
9178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9179 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9180 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9181 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9182 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9184 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9185 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9187 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9188 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9189 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9190 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9191 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9192 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9193 I40E_INSET_DMAC | I40E_INSET_SMAC |
9194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9196 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9198 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9201 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9204 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9205 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9206 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9207 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9209 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9210 I40E_INSET_DMAC | I40E_INSET_SMAC |
9211 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9212 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9213 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9214 I40E_INSET_IPV4_TTL,
9215 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9216 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9217 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9218 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9219 I40E_INSET_IPV6_HOP_LIMIT,
9220 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9221 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9222 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9223 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9224 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9225 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9226 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9227 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9228 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9229 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9230 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9231 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9232 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9233 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9234 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9235 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9236 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9237 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9238 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9239 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9240 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9241 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9242 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9243 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9244 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9245 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9246 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9247 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9248 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9249 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9251 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9252 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9253 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9254 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9255 I40E_INSET_IPV6_HOP_LIMIT,
9256 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9257 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9258 I40E_INSET_LAST_ETHER_TYPE,
9261 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9263 if (filter == RTE_ETH_FILTER_HASH)
9264 valid = valid_hash_inset_table[pctype];
9266 valid = valid_fdir_inset_table[pctype];
9272 * Validate if the input set is allowed for a specific PCTYPE
9275 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9276 enum rte_filter_type filter, uint64_t inset)
9280 valid = i40e_get_valid_input_set(pctype, filter);
9281 if (inset & (~valid))
9287 /* default input set fields combination per pctype */
9289 i40e_get_default_input_set(uint16_t pctype)
9291 static const uint64_t default_inset_table[] = {
9292 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9293 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9294 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9295 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9296 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9297 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9298 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9299 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9300 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9301 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9302 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9303 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9304 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9305 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9306 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9307 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9308 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9309 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9310 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9311 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9313 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9314 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9315 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9316 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9317 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9318 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9319 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9320 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9321 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9322 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9323 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9324 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9325 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9326 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9327 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9328 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9329 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9330 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9331 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9332 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9333 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9334 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9336 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9337 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9338 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9339 I40E_INSET_LAST_ETHER_TYPE,
9342 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9345 return default_inset_table[pctype];
9349 * Translate the input set from bit masks to register aware bit masks
9353 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9363 static const struct inset_map inset_map_common[] = {
9364 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9365 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9366 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9367 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9368 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9369 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9370 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9371 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9372 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9373 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9374 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9375 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9376 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9377 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9378 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9379 {I40E_INSET_TUNNEL_DMAC,
9380 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9381 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9382 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9383 {I40E_INSET_TUNNEL_SRC_PORT,
9384 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9385 {I40E_INSET_TUNNEL_DST_PORT,
9386 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9387 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9388 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9389 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9390 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9391 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9392 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9393 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9394 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9395 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9398 /* some different registers map in x722*/
9399 static const struct inset_map inset_map_diff_x722[] = {
9400 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9401 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9402 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9403 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9406 static const struct inset_map inset_map_diff_not_x722[] = {
9407 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9408 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9409 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9410 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9416 /* Translate input set to register aware inset */
9417 if (type == I40E_MAC_X722) {
9418 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9419 if (input & inset_map_diff_x722[i].inset)
9420 val |= inset_map_diff_x722[i].inset_reg;
9423 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9424 if (input & inset_map_diff_not_x722[i].inset)
9425 val |= inset_map_diff_not_x722[i].inset_reg;
9429 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9430 if (input & inset_map_common[i].inset)
9431 val |= inset_map_common[i].inset_reg;
9438 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9439 uint32_t pit_reg_count, uint32_t hdr_off)
9441 const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9442 uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9443 uint32_t i, reg_val, src_off, count;
9445 for (i = pit_reg_start; i < pit_reg_end; i++) {
9446 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9448 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9449 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9451 if (src_off <= field_off && (src_off + count) > field_off)
9455 if (i >= pit_reg_end) {
9457 "Hardware GLQF_PIT configuration does not support this field mask");
9461 return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9465 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9466 uint32_t *mask, uint8_t nb_elem)
9468 static const uint64_t mask_inset[] = {
9469 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9470 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9472 static const struct {
9476 } inset_mask_offset_map[] = {
9477 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9478 offsetof(struct rte_ipv4_hdr, type_of_service) },
9480 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9481 offsetof(struct rte_ipv4_hdr, next_proto_id) },
9483 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9484 offsetof(struct rte_ipv4_hdr, time_to_live) },
9486 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9487 offsetof(struct rte_ipv6_hdr, vtc_flow) },
9489 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9490 offsetof(struct rte_ipv6_hdr, proto) },
9492 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9493 offsetof(struct rte_ipv6_hdr, hop_limits) },
9503 for (i = 0; i < RTE_DIM(mask_inset); i++) {
9504 /* Clear the inset bit, if no MASK is required,
9505 * for example proto + ttl
9507 if ((mask_inset[i] & inset) == mask_inset[i]) {
9508 inset &= ~mask_inset[i];
9514 for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9515 uint32_t pit_start, pit_count;
9518 if (!(inset_mask_offset_map[i].inset & inset))
9521 if (inset_mask_offset_map[i].inset &
9522 (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9523 I40E_INSET_IPV4_TTL)) {
9524 pit_start = I40E_GLQF_PIT_IPV4_START;
9525 pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9527 pit_start = I40E_GLQF_PIT_IPV6_START;
9528 pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9531 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9532 inset_mask_offset_map[i].offset);
9537 if (idx >= nb_elem) {
9539 "Configuration of inset mask out of range %u",
9544 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9545 inset_mask_offset_map[i].mask);
9553 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9555 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9557 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9559 i40e_write_rx_ctl(hw, addr, val);
9560 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9561 (uint32_t)i40e_read_rx_ctl(hw, addr));
9565 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9567 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9568 struct rte_eth_dev_data *dev_data =
9569 ((struct i40e_adapter *)hw->back)->pf.dev_data;
9570 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
9573 i40e_write_rx_ctl(hw, addr, val);
9574 PMD_DRV_LOG(WARNING,
9575 "i40e device %s changed global register [0x%08x]."
9576 " original: 0x%08x, new: 0x%08x",
9577 dev->device->name, addr, reg,
9578 (uint32_t)i40e_read_rx_ctl(hw, addr));
9583 i40e_filter_input_set_init(struct i40e_pf *pf)
9585 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9586 enum i40e_filter_pctype pctype;
9587 uint64_t input_set, inset_reg;
9588 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9592 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9593 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9594 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9596 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9599 input_set = i40e_get_default_input_set(pctype);
9601 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9602 I40E_INSET_MASK_NUM_REG);
9605 if (pf->support_multi_driver && num > 0) {
9606 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9609 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9612 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9613 (uint32_t)(inset_reg & UINT32_MAX));
9614 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9615 (uint32_t)((inset_reg >>
9616 I40E_32_BIT_WIDTH) & UINT32_MAX));
9617 if (!pf->support_multi_driver) {
9618 i40e_check_write_global_reg(hw,
9619 I40E_GLQF_HASH_INSET(0, pctype),
9620 (uint32_t)(inset_reg & UINT32_MAX));
9621 i40e_check_write_global_reg(hw,
9622 I40E_GLQF_HASH_INSET(1, pctype),
9623 (uint32_t)((inset_reg >>
9624 I40E_32_BIT_WIDTH) & UINT32_MAX));
9626 for (i = 0; i < num; i++) {
9627 i40e_check_write_global_reg(hw,
9628 I40E_GLQF_FD_MSK(i, pctype),
9630 i40e_check_write_global_reg(hw,
9631 I40E_GLQF_HASH_MSK(i, pctype),
9634 /*clear unused mask registers of the pctype */
9635 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9636 i40e_check_write_global_reg(hw,
9637 I40E_GLQF_FD_MSK(i, pctype),
9639 i40e_check_write_global_reg(hw,
9640 I40E_GLQF_HASH_MSK(i, pctype),
9644 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9646 I40E_WRITE_FLUSH(hw);
9648 /* store the default input set */
9649 if (!pf->support_multi_driver)
9650 pf->hash_input_set[pctype] = input_set;
9651 pf->fdir.input_set[pctype] = input_set;
9656 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9657 uint32_t pctype, bool add)
9659 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9660 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9661 uint64_t inset_reg = 0;
9664 if (pf->support_multi_driver) {
9666 "Modify input set is not permitted when multi-driver enabled.");
9670 /* For X722, get translated pctype in fd pctype register */
9671 if (hw->mac.type == I40E_MAC_X722)
9672 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9675 /* get inset value in register */
9676 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9677 inset_reg <<= I40E_32_BIT_WIDTH;
9678 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9679 input_set |= pf->hash_input_set[pctype];
9681 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9682 I40E_INSET_MASK_NUM_REG);
9686 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9688 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9689 (uint32_t)(inset_reg & UINT32_MAX));
9690 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9691 (uint32_t)((inset_reg >>
9692 I40E_32_BIT_WIDTH) & UINT32_MAX));
9694 for (i = 0; i < num; i++)
9695 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9697 /*clear unused mask registers of the pctype */
9698 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9699 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9701 I40E_WRITE_FLUSH(hw);
9703 pf->hash_input_set[pctype] = input_set;
9707 /* Convert ethertype filter structure */
9709 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9710 struct i40e_ethertype_filter *filter)
9712 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9713 RTE_ETHER_ADDR_LEN);
9714 filter->input.ether_type = input->ether_type;
9715 filter->flags = input->flags;
9716 filter->queue = input->queue;
9721 /* Check if there exists the ehtertype filter */
9722 struct i40e_ethertype_filter *
9723 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9724 const struct i40e_ethertype_filter_input *input)
9728 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9732 return ethertype_rule->hash_map[ret];
9735 /* Add ethertype filter in SW list */
9737 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9738 struct i40e_ethertype_filter *filter)
9740 struct i40e_ethertype_rule *rule = &pf->ethertype;
9743 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9746 "Failed to insert ethertype filter"
9747 " to hash table %d!",
9751 rule->hash_map[ret] = filter;
9753 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9758 /* Delete ethertype filter in SW list */
9760 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9761 struct i40e_ethertype_filter_input *input)
9763 struct i40e_ethertype_rule *rule = &pf->ethertype;
9764 struct i40e_ethertype_filter *filter;
9767 ret = rte_hash_del_key(rule->hash_table, input);
9770 "Failed to delete ethertype filter"
9771 " to hash table %d!",
9775 filter = rule->hash_map[ret];
9776 rule->hash_map[ret] = NULL;
9778 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9785 * Configure ethertype filter, which can director packet by filtering
9786 * with mac address and ether_type or only ether_type
9789 i40e_ethertype_filter_set(struct i40e_pf *pf,
9790 struct rte_eth_ethertype_filter *filter,
9793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9794 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9795 struct i40e_ethertype_filter *ethertype_filter, *node;
9796 struct i40e_ethertype_filter check_filter;
9797 struct i40e_control_filter_stats stats;
9801 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9802 PMD_DRV_LOG(ERR, "Invalid queue ID");
9805 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9806 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9808 "unsupported ether_type(0x%04x) in control packet filter.",
9809 filter->ether_type);
9812 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9813 PMD_DRV_LOG(WARNING,
9814 "filter vlan ether_type in first tag is not supported.");
9816 /* Check if there is the filter in SW list */
9817 memset(&check_filter, 0, sizeof(check_filter));
9818 i40e_ethertype_filter_convert(filter, &check_filter);
9819 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9820 &check_filter.input);
9822 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9826 if (!add && !node) {
9827 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9831 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9832 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9833 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9834 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9835 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9837 memset(&stats, 0, sizeof(stats));
9838 ret = i40e_aq_add_rem_control_packet_filter(hw,
9839 filter->mac_addr.addr_bytes,
9840 filter->ether_type, flags,
9842 filter->queue, add, &stats, NULL);
9845 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9846 ret, stats.mac_etype_used, stats.etype_used,
9847 stats.mac_etype_free, stats.etype_free);
9851 /* Add or delete a filter in SW list */
9853 ethertype_filter = rte_zmalloc("ethertype_filter",
9854 sizeof(*ethertype_filter), 0);
9855 if (ethertype_filter == NULL) {
9856 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9860 rte_memcpy(ethertype_filter, &check_filter,
9861 sizeof(check_filter));
9862 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9864 rte_free(ethertype_filter);
9866 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9873 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9874 const struct rte_flow_ops **ops)
9879 *ops = &i40e_flow_ops;
9884 * Check and enable Extended Tag.
9885 * Enabling Extended Tag is important for 40G performance.
9888 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9890 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9894 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9897 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9901 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9902 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9907 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9910 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9914 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9915 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9918 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9919 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9922 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9929 * As some registers wouldn't be reset unless a global hardware reset,
9930 * hardware initialization is needed to put those registers into an
9931 * expected initial state.
9934 i40e_hw_init(struct rte_eth_dev *dev)
9936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9938 i40e_enable_extended_tag(dev);
9940 /* clear the PF Queue Filter control register */
9941 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9943 /* Disable symmetric hash per port */
9944 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9948 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9949 * however this function will return only one highest pctype index,
9950 * which is not quite correct. This is known problem of i40e driver
9951 * and needs to be fixed later.
9953 enum i40e_filter_pctype
9954 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9957 uint64_t pctype_mask;
9959 if (flow_type < I40E_FLOW_TYPE_MAX) {
9960 pctype_mask = adapter->pctypes_tbl[flow_type];
9961 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9962 if (pctype_mask & (1ULL << i))
9963 return (enum i40e_filter_pctype)i;
9966 return I40E_FILTER_PCTYPE_INVALID;
9970 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9971 enum i40e_filter_pctype pctype)
9974 uint64_t pctype_mask = 1ULL << pctype;
9976 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9978 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9982 return RTE_ETH_FLOW_UNKNOWN;
9986 * On X710, performance number is far from the expectation on recent firmware
9987 * versions; on XL710, performance number is also far from the expectation on
9988 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9989 * mode is enabled and port MAC address is equal to the packet destination MAC
9990 * address. The fix for this issue may not be integrated in the following
9991 * firmware version. So the workaround in software driver is needed. It needs
9992 * to modify the initial values of 3 internal only registers for both X710 and
9993 * XL710. Note that the values for X710 or XL710 could be different, and the
9994 * workaround can be removed when it is fixed in firmware in the future.
9997 /* For both X710 and XL710 */
9998 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9999 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10000 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10002 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10003 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10006 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10007 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10010 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10012 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10013 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10016 * GL_SWR_PM_UP_THR:
10017 * The value is not impacted from the link speed, its value is set according
10018 * to the total number of ports for a better pipe-monitor configuration.
10021 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10023 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10024 .device_id = (dev), \
10025 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10027 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10028 .device_id = (dev), \
10029 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10031 static const struct {
10032 uint16_t device_id;
10034 } swr_pm_table[] = {
10035 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10036 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10037 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10038 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10039 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10041 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10042 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10043 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10044 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10045 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10046 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10047 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10051 if (value == NULL) {
10052 PMD_DRV_LOG(ERR, "value is NULL");
10056 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10057 if (hw->device_id == swr_pm_table[i].device_id) {
10058 *value = swr_pm_table[i].val;
10060 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10062 hw->device_id, *value);
10071 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10073 enum i40e_status_code status;
10074 struct i40e_aq_get_phy_abilities_resp phy_ab;
10075 int ret = -ENOTSUP;
10078 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10082 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10085 rte_delay_us(100000);
10087 status = i40e_aq_get_phy_capabilities(hw, false,
10088 true, &phy_ab, NULL);
10096 i40e_configure_registers(struct i40e_hw *hw)
10102 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10103 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10104 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10110 for (i = 0; i < RTE_DIM(reg_table); i++) {
10111 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10112 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10114 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10115 else /* For X710/XL710/XXV710 */
10116 if (hw->aq.fw_maj_ver < 6)
10118 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10121 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10124 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10125 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10127 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10128 else /* For X710/XL710/XXV710 */
10130 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10133 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10136 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10137 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10138 "GL_SWR_PM_UP_THR value fixup",
10143 reg_table[i].val = cfg_val;
10146 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10149 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10150 reg_table[i].addr);
10153 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10154 reg_table[i].addr, reg);
10155 if (reg == reg_table[i].val)
10158 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10159 reg_table[i].val, NULL);
10162 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10163 reg_table[i].val, reg_table[i].addr);
10166 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10167 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10171 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10172 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10173 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10175 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10180 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10181 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10185 /* Configure for double VLAN RX stripping */
10186 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10187 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10188 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10189 ret = i40e_aq_debug_write_register(hw,
10190 I40E_VSI_TSR(vsi->vsi_id),
10193 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10195 return I40E_ERR_CONFIG;
10199 /* Configure for double VLAN TX insertion */
10200 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10201 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10202 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10203 ret = i40e_aq_debug_write_register(hw,
10204 I40E_VSI_L2TAGSTXVALID(
10205 vsi->vsi_id), reg, NULL);
10208 "Failed to update VSI_L2TAGSTXVALID[%d]",
10210 return I40E_ERR_CONFIG;
10218 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10220 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10221 uint64_t systim_cycles;
10223 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10224 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10227 return systim_cycles;
10231 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10233 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10234 uint64_t rx_tstamp;
10236 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10237 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10244 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10246 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10247 uint64_t tx_tstamp;
10249 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10250 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10257 i40e_start_timecounters(struct rte_eth_dev *dev)
10259 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10260 struct i40e_adapter *adapter = dev->data->dev_private;
10261 struct rte_eth_link link;
10262 uint32_t tsync_inc_l;
10263 uint32_t tsync_inc_h;
10265 /* Get current link speed. */
10266 i40e_dev_link_update(dev, 1);
10267 rte_eth_linkstatus_get(dev, &link);
10269 switch (link.link_speed) {
10270 case ETH_SPEED_NUM_40G:
10271 case ETH_SPEED_NUM_25G:
10272 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10273 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10275 case ETH_SPEED_NUM_10G:
10276 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10277 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10279 case ETH_SPEED_NUM_1G:
10280 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10281 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10288 /* Set the timesync increment value. */
10289 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10290 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10292 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10293 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10294 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10296 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10297 adapter->systime_tc.cc_shift = 0;
10298 adapter->systime_tc.nsec_mask = 0;
10300 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10301 adapter->rx_tstamp_tc.cc_shift = 0;
10302 adapter->rx_tstamp_tc.nsec_mask = 0;
10304 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10305 adapter->tx_tstamp_tc.cc_shift = 0;
10306 adapter->tx_tstamp_tc.nsec_mask = 0;
10310 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10312 struct i40e_adapter *adapter = dev->data->dev_private;
10314 adapter->systime_tc.nsec += delta;
10315 adapter->rx_tstamp_tc.nsec += delta;
10316 adapter->tx_tstamp_tc.nsec += delta;
10322 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10325 struct i40e_adapter *adapter = dev->data->dev_private;
10327 ns = rte_timespec_to_ns(ts);
10329 /* Set the timecounters to a new value. */
10330 adapter->systime_tc.nsec = ns;
10331 adapter->rx_tstamp_tc.nsec = ns;
10332 adapter->tx_tstamp_tc.nsec = ns;
10338 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10340 uint64_t ns, systime_cycles;
10341 struct i40e_adapter *adapter = dev->data->dev_private;
10343 systime_cycles = i40e_read_systime_cyclecounter(dev);
10344 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10345 *ts = rte_ns_to_timespec(ns);
10351 i40e_timesync_enable(struct rte_eth_dev *dev)
10353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10354 uint32_t tsync_ctl_l;
10355 uint32_t tsync_ctl_h;
10357 /* Stop the timesync system time. */
10358 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10359 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10360 /* Reset the timesync system time value. */
10361 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10362 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10364 i40e_start_timecounters(dev);
10366 /* Clear timesync registers. */
10367 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10368 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10369 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10370 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10371 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10372 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10374 /* Enable timestamping of PTP packets. */
10375 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10376 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10378 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10379 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10380 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10382 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10383 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10389 i40e_timesync_disable(struct rte_eth_dev *dev)
10391 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10392 uint32_t tsync_ctl_l;
10393 uint32_t tsync_ctl_h;
10395 /* Disable timestamping of transmitted PTP packets. */
10396 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10397 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10399 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10400 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10402 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10403 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10405 /* Reset the timesync increment value. */
10406 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10407 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10413 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10414 struct timespec *timestamp, uint32_t flags)
10416 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10417 struct i40e_adapter *adapter = dev->data->dev_private;
10418 uint32_t sync_status;
10419 uint32_t index = flags & 0x03;
10420 uint64_t rx_tstamp_cycles;
10423 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10424 if ((sync_status & (1 << index)) == 0)
10427 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10428 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10429 *timestamp = rte_ns_to_timespec(ns);
10435 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10436 struct timespec *timestamp)
10438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10439 struct i40e_adapter *adapter = dev->data->dev_private;
10440 uint32_t sync_status;
10441 uint64_t tx_tstamp_cycles;
10444 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10445 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10448 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10449 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10450 *timestamp = rte_ns_to_timespec(ns);
10456 * i40e_parse_dcb_configure - parse dcb configure from user
10457 * @dev: the device being configured
10458 * @dcb_cfg: pointer of the result of parse
10459 * @*tc_map: bit map of enabled traffic classes
10461 * Returns 0 on success, negative value on failure
10464 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10465 struct i40e_dcbx_config *dcb_cfg,
10468 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10469 uint8_t i, tc_bw, bw_lf;
10471 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10473 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10474 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10475 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10479 /* assume each tc has the same bw */
10480 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10481 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10482 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10483 /* to ensure the sum of tcbw is equal to 100 */
10484 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10485 for (i = 0; i < bw_lf; i++)
10486 dcb_cfg->etscfg.tcbwtable[i]++;
10488 /* assume each tc has the same Transmission Selection Algorithm */
10489 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10490 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10492 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10493 dcb_cfg->etscfg.prioritytable[i] =
10494 dcb_rx_conf->dcb_tc[i];
10496 /* FW needs one App to configure HW */
10497 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10498 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10499 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10500 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10502 if (dcb_rx_conf->nb_tcs == 0)
10503 *tc_map = 1; /* tc0 only */
10505 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10507 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10508 dcb_cfg->pfc.willing = 0;
10509 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10510 dcb_cfg->pfc.pfcenable = *tc_map;
10516 static enum i40e_status_code
10517 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10518 struct i40e_aqc_vsi_properties_data *info,
10519 uint8_t enabled_tcmap)
10521 enum i40e_status_code ret;
10522 int i, total_tc = 0;
10523 uint16_t qpnum_per_tc, bsf, qp_idx;
10524 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10525 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10526 uint16_t used_queues;
10528 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10529 if (ret != I40E_SUCCESS)
10532 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10533 if (enabled_tcmap & (1 << i))
10538 vsi->enabled_tc = enabled_tcmap;
10540 /* different VSI has different queues assigned */
10541 if (vsi->type == I40E_VSI_MAIN)
10542 used_queues = dev_data->nb_rx_queues -
10543 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10544 else if (vsi->type == I40E_VSI_VMDQ2)
10545 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10547 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10548 return I40E_ERR_NO_AVAILABLE_VSI;
10551 qpnum_per_tc = used_queues / total_tc;
10552 /* Number of queues per enabled TC */
10553 if (qpnum_per_tc == 0) {
10554 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10555 return I40E_ERR_INVALID_QP_ID;
10557 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10558 I40E_MAX_Q_PER_TC);
10559 bsf = rte_bsf32(qpnum_per_tc);
10562 * Configure TC and queue mapping parameters, for enabled TC,
10563 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10564 * default queue will serve it.
10567 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10568 if (vsi->enabled_tc & (1 << i)) {
10569 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10570 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10571 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10572 qp_idx += qpnum_per_tc;
10574 info->tc_mapping[i] = 0;
10577 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10578 if (vsi->type == I40E_VSI_SRIOV) {
10579 info->mapping_flags |=
10580 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10581 for (i = 0; i < vsi->nb_qps; i++)
10582 info->queue_mapping[i] =
10583 rte_cpu_to_le_16(vsi->base_queue + i);
10585 info->mapping_flags |=
10586 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10587 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10589 info->valid_sections |=
10590 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10592 return I40E_SUCCESS;
10596 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10597 * @veb: VEB to be configured
10598 * @tc_map: enabled TC bitmap
10600 * Returns 0 on success, negative value on failure
10602 static enum i40e_status_code
10603 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10605 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10606 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10607 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10608 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10609 enum i40e_status_code ret = I40E_SUCCESS;
10613 /* Check if enabled_tc is same as existing or new TCs */
10614 if (veb->enabled_tc == tc_map)
10617 /* configure tc bandwidth */
10618 memset(&veb_bw, 0, sizeof(veb_bw));
10619 veb_bw.tc_valid_bits = tc_map;
10620 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10621 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10622 if (tc_map & BIT_ULL(i))
10623 veb_bw.tc_bw_share_credits[i] = 1;
10625 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10629 "AQ command Config switch_comp BW allocation per TC failed = %d",
10630 hw->aq.asq_last_status);
10634 memset(&ets_query, 0, sizeof(ets_query));
10635 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10637 if (ret != I40E_SUCCESS) {
10639 "Failed to get switch_comp ETS configuration %u",
10640 hw->aq.asq_last_status);
10643 memset(&bw_query, 0, sizeof(bw_query));
10644 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10646 if (ret != I40E_SUCCESS) {
10648 "Failed to get switch_comp bandwidth configuration %u",
10649 hw->aq.asq_last_status);
10653 /* store and print out BW info */
10654 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10655 veb->bw_info.bw_max = ets_query.tc_bw_max;
10656 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10657 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10658 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10659 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10660 I40E_16_BIT_WIDTH);
10661 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10662 veb->bw_info.bw_ets_share_credits[i] =
10663 bw_query.tc_bw_share_credits[i];
10664 veb->bw_info.bw_ets_credits[i] =
10665 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10666 /* 4 bits per TC, 4th bit is reserved */
10667 veb->bw_info.bw_ets_max[i] =
10668 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10669 RTE_LEN2MASK(3, uint8_t));
10670 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10671 veb->bw_info.bw_ets_share_credits[i]);
10672 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10673 veb->bw_info.bw_ets_credits[i]);
10674 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10675 veb->bw_info.bw_ets_max[i]);
10678 veb->enabled_tc = tc_map;
10685 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10686 * @vsi: VSI to be configured
10687 * @tc_map: enabled TC bitmap
10689 * Returns 0 on success, negative value on failure
10691 static enum i40e_status_code
10692 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10694 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10695 struct i40e_vsi_context ctxt;
10696 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10697 enum i40e_status_code ret = I40E_SUCCESS;
10700 /* Check if enabled_tc is same as existing or new TCs */
10701 if (vsi->enabled_tc == tc_map)
10704 /* configure tc bandwidth */
10705 memset(&bw_data, 0, sizeof(bw_data));
10706 bw_data.tc_valid_bits = tc_map;
10707 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10708 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10709 if (tc_map & BIT_ULL(i))
10710 bw_data.tc_bw_credits[i] = 1;
10712 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10715 "AQ command Config VSI BW allocation per TC failed = %d",
10716 hw->aq.asq_last_status);
10719 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10720 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10722 /* Update Queue Pairs Mapping for currently enabled UPs */
10723 ctxt.seid = vsi->seid;
10724 ctxt.pf_num = hw->pf_id;
10726 ctxt.uplink_seid = vsi->uplink_seid;
10727 ctxt.info = vsi->info;
10729 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10733 /* Update the VSI after updating the VSI queue-mapping information */
10734 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10736 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10737 hw->aq.asq_last_status);
10740 /* update the local VSI info with updated queue map */
10741 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10742 sizeof(vsi->info.tc_mapping));
10743 rte_memcpy(&vsi->info.queue_mapping,
10744 &ctxt.info.queue_mapping,
10745 sizeof(vsi->info.queue_mapping));
10746 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10747 vsi->info.valid_sections = 0;
10749 /* query and update current VSI BW information */
10750 ret = i40e_vsi_get_bw_config(vsi);
10753 "Failed updating vsi bw info, err %s aq_err %s",
10754 i40e_stat_str(hw, ret),
10755 i40e_aq_str(hw, hw->aq.asq_last_status));
10759 vsi->enabled_tc = tc_map;
10766 * i40e_dcb_hw_configure - program the dcb setting to hw
10767 * @pf: pf the configuration is taken on
10768 * @new_cfg: new configuration
10769 * @tc_map: enabled TC bitmap
10771 * Returns 0 on success, negative value on failure
10773 static enum i40e_status_code
10774 i40e_dcb_hw_configure(struct i40e_pf *pf,
10775 struct i40e_dcbx_config *new_cfg,
10778 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10779 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10780 struct i40e_vsi *main_vsi = pf->main_vsi;
10781 struct i40e_vsi_list *vsi_list;
10782 enum i40e_status_code ret;
10786 /* Use the FW API if FW > v4.4*/
10787 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10788 (hw->aq.fw_maj_ver >= 5))) {
10790 "FW < v4.4, can not use FW LLDP API to configure DCB");
10791 return I40E_ERR_FIRMWARE_API_VERSION;
10794 /* Check if need reconfiguration */
10795 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10796 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10797 return I40E_SUCCESS;
10800 /* Copy the new config to the current config */
10801 *old_cfg = *new_cfg;
10802 old_cfg->etsrec = old_cfg->etscfg;
10803 ret = i40e_set_dcb_config(hw);
10805 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10806 i40e_stat_str(hw, ret),
10807 i40e_aq_str(hw, hw->aq.asq_last_status));
10810 /* set receive Arbiter to RR mode and ETS scheme by default */
10811 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10812 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10813 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10814 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10815 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10816 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10817 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10818 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10819 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10820 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10821 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10822 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10823 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10825 /* get local mib to check whether it is configured correctly */
10827 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10828 /* Get Local DCB Config */
10829 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10830 &hw->local_dcbx_config);
10832 /* if Veb is created, need to update TC of it at first */
10833 if (main_vsi->veb) {
10834 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10836 PMD_INIT_LOG(WARNING,
10837 "Failed configuring TC for VEB seid=%d",
10838 main_vsi->veb->seid);
10840 /* Update each VSI */
10841 i40e_vsi_config_tc(main_vsi, tc_map);
10842 if (main_vsi->veb) {
10843 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10844 /* Beside main VSI and VMDQ VSIs, only enable default
10845 * TC for other VSIs
10847 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10848 ret = i40e_vsi_config_tc(vsi_list->vsi,
10851 ret = i40e_vsi_config_tc(vsi_list->vsi,
10852 I40E_DEFAULT_TCMAP);
10854 PMD_INIT_LOG(WARNING,
10855 "Failed configuring TC for VSI seid=%d",
10856 vsi_list->vsi->seid);
10860 return I40E_SUCCESS;
10864 * i40e_dcb_init_configure - initial dcb config
10865 * @dev: device being configured
10866 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10868 * Returns 0 on success, negative value on failure
10871 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10877 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10878 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10882 /* DCB initialization:
10883 * Update DCB configuration from the Firmware and configure
10884 * LLDP MIB change event.
10886 if (sw_dcb == TRUE) {
10887 /* Stopping lldp is necessary for DPDK, but it will cause
10888 * DCB init failed. For i40e_init_dcb(), the prerequisite
10889 * for successful initialization of DCB is that LLDP is
10890 * enabled. So it is needed to start lldp before DCB init
10891 * and stop it after initialization.
10893 ret = i40e_aq_start_lldp(hw, true, NULL);
10894 if (ret != I40E_SUCCESS)
10895 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10897 ret = i40e_init_dcb(hw, true);
10898 /* If lldp agent is stopped, the return value from
10899 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10900 * adminq status. Otherwise, it should return success.
10902 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10903 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10904 memset(&hw->local_dcbx_config, 0,
10905 sizeof(struct i40e_dcbx_config));
10906 /* set dcb default configuration */
10907 hw->local_dcbx_config.etscfg.willing = 0;
10908 hw->local_dcbx_config.etscfg.maxtcs = 0;
10909 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10910 hw->local_dcbx_config.etscfg.tsatable[0] =
10912 /* all UPs mapping to TC0 */
10913 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10914 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10915 hw->local_dcbx_config.etsrec =
10916 hw->local_dcbx_config.etscfg;
10917 hw->local_dcbx_config.pfc.willing = 0;
10918 hw->local_dcbx_config.pfc.pfccap =
10919 I40E_MAX_TRAFFIC_CLASS;
10920 /* FW needs one App to configure HW */
10921 hw->local_dcbx_config.numapps = 1;
10922 hw->local_dcbx_config.app[0].selector =
10923 I40E_APP_SEL_ETHTYPE;
10924 hw->local_dcbx_config.app[0].priority = 3;
10925 hw->local_dcbx_config.app[0].protocolid =
10926 I40E_APP_PROTOID_FCOE;
10927 ret = i40e_set_dcb_config(hw);
10930 "default dcb config fails. err = %d, aq_err = %d.",
10931 ret, hw->aq.asq_last_status);
10936 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10937 ret, hw->aq.asq_last_status);
10941 if (i40e_need_stop_lldp(dev)) {
10942 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
10943 if (ret != I40E_SUCCESS)
10944 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
10947 ret = i40e_aq_start_lldp(hw, true, NULL);
10948 if (ret != I40E_SUCCESS)
10949 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10951 ret = i40e_init_dcb(hw, true);
10953 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10955 "HW doesn't support DCBX offload.");
10960 "DCBX configuration failed, err = %d, aq_err = %d.",
10961 ret, hw->aq.asq_last_status);
10969 * i40e_dcb_setup - setup dcb related config
10970 * @dev: device being configured
10972 * Returns 0 on success, negative value on failure
10975 i40e_dcb_setup(struct rte_eth_dev *dev)
10977 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10978 struct i40e_dcbx_config dcb_cfg;
10979 uint8_t tc_map = 0;
10982 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10983 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10987 if (pf->vf_num != 0)
10988 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10990 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10992 PMD_INIT_LOG(ERR, "invalid dcb config");
10995 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10997 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11005 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11006 struct rte_eth_dcb_info *dcb_info)
11008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11010 struct i40e_vsi *vsi = pf->main_vsi;
11011 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11012 uint16_t bsf, tc_mapping;
11015 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11016 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11018 dcb_info->nb_tcs = 1;
11019 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11020 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11021 for (i = 0; i < dcb_info->nb_tcs; i++)
11022 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11024 /* get queue mapping if vmdq is disabled */
11025 if (!pf->nb_cfg_vmdq_vsi) {
11026 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11027 if (!(vsi->enabled_tc & (1 << i)))
11029 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11030 dcb_info->tc_queue.tc_rxq[j][i].base =
11031 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11032 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11033 dcb_info->tc_queue.tc_txq[j][i].base =
11034 dcb_info->tc_queue.tc_rxq[j][i].base;
11035 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11036 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11037 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11038 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11039 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11044 /* get queue mapping if vmdq is enabled */
11046 vsi = pf->vmdq[j].vsi;
11047 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11048 if (!(vsi->enabled_tc & (1 << i)))
11050 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11051 dcb_info->tc_queue.tc_rxq[j][i].base =
11052 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11053 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11054 dcb_info->tc_queue.tc_txq[j][i].base =
11055 dcb_info->tc_queue.tc_rxq[j][i].base;
11056 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11057 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11058 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11059 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11060 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11063 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11068 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11070 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11071 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11072 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11073 uint16_t msix_intr;
11075 msix_intr = intr_handle->intr_vec[queue_id];
11076 if (msix_intr == I40E_MISC_VEC_ID)
11077 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11078 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11079 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11080 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11083 I40E_PFINT_DYN_CTLN(msix_intr -
11084 I40E_RX_VEC_START),
11085 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11086 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11087 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11089 I40E_WRITE_FLUSH(hw);
11090 rte_intr_ack(&pci_dev->intr_handle);
11096 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11098 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11099 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101 uint16_t msix_intr;
11103 msix_intr = intr_handle->intr_vec[queue_id];
11104 if (msix_intr == I40E_MISC_VEC_ID)
11105 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11106 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11109 I40E_PFINT_DYN_CTLN(msix_intr -
11110 I40E_RX_VEC_START),
11111 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11112 I40E_WRITE_FLUSH(hw);
11118 * This function is used to check if the register is valid.
11119 * Below is the valid registers list for X722 only:
11123 * 0x208e00--0x209000
11124 * 0x20be00--0x20c000
11125 * 0x263c00--0x264000
11126 * 0x265c00--0x266000
11128 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11130 if ((type != I40E_MAC_X722) &&
11131 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11132 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11133 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11134 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11135 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11136 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11137 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11143 static int i40e_get_regs(struct rte_eth_dev *dev,
11144 struct rte_dev_reg_info *regs)
11146 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11147 uint32_t *ptr_data = regs->data;
11148 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11149 const struct i40e_reg_info *reg_info;
11151 if (ptr_data == NULL) {
11152 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11153 regs->width = sizeof(uint32_t);
11157 /* The first few registers have to be read using AQ operations */
11159 while (i40e_regs_adminq[reg_idx].name) {
11160 reg_info = &i40e_regs_adminq[reg_idx++];
11161 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11163 arr_idx2 <= reg_info->count2;
11165 reg_offset = arr_idx * reg_info->stride1 +
11166 arr_idx2 * reg_info->stride2;
11167 reg_offset += reg_info->base_addr;
11168 ptr_data[reg_offset >> 2] =
11169 i40e_read_rx_ctl(hw, reg_offset);
11173 /* The remaining registers can be read using primitives */
11175 while (i40e_regs_others[reg_idx].name) {
11176 reg_info = &i40e_regs_others[reg_idx++];
11177 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11179 arr_idx2 <= reg_info->count2;
11181 reg_offset = arr_idx * reg_info->stride1 +
11182 arr_idx2 * reg_info->stride2;
11183 reg_offset += reg_info->base_addr;
11184 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11185 ptr_data[reg_offset >> 2] = 0;
11187 ptr_data[reg_offset >> 2] =
11188 I40E_READ_REG(hw, reg_offset);
11195 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11197 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11199 /* Convert word count to byte count */
11200 return hw->nvm.sr_size << 1;
11203 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11204 struct rte_dev_eeprom_info *eeprom)
11206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11207 uint16_t *data = eeprom->data;
11208 uint16_t offset, length, cnt_words;
11211 offset = eeprom->offset >> 1;
11212 length = eeprom->length >> 1;
11213 cnt_words = length;
11215 if (offset > hw->nvm.sr_size ||
11216 offset + length > hw->nvm.sr_size) {
11217 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11221 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11223 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11224 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11225 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11232 static int i40e_get_module_info(struct rte_eth_dev *dev,
11233 struct rte_eth_dev_module_info *modinfo)
11235 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11236 uint32_t sff8472_comp = 0;
11237 uint32_t sff8472_swap = 0;
11238 uint32_t sff8636_rev = 0;
11239 i40e_status status;
11242 /* Check if firmware supports reading module EEPROM. */
11243 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11245 "Module EEPROM memory read not supported. "
11246 "Please update the NVM image.\n");
11250 status = i40e_update_link_info(hw);
11254 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11256 "Cannot read module EEPROM memory. "
11257 "No module connected.\n");
11261 type = hw->phy.link_info.module_type[0];
11264 case I40E_MODULE_TYPE_SFP:
11265 status = i40e_aq_get_phy_register(hw,
11266 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11267 I40E_I2C_EEPROM_DEV_ADDR, 1,
11268 I40E_MODULE_SFF_8472_COMP,
11269 &sff8472_comp, NULL);
11273 status = i40e_aq_get_phy_register(hw,
11274 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11275 I40E_I2C_EEPROM_DEV_ADDR, 1,
11276 I40E_MODULE_SFF_8472_SWAP,
11277 &sff8472_swap, NULL);
11281 /* Check if the module requires address swap to access
11282 * the other EEPROM memory page.
11284 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11285 PMD_DRV_LOG(WARNING,
11286 "Module address swap to access "
11287 "page 0xA2 is not supported.\n");
11288 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11289 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11290 } else if (sff8472_comp == 0x00) {
11291 /* Module is not SFF-8472 compliant */
11292 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11293 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11295 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11296 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11299 case I40E_MODULE_TYPE_QSFP_PLUS:
11300 /* Read from memory page 0. */
11301 status = i40e_aq_get_phy_register(hw,
11302 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11304 I40E_MODULE_REVISION_ADDR,
11305 &sff8636_rev, NULL);
11308 /* Determine revision compliance byte */
11309 if (sff8636_rev > 0x02) {
11310 /* Module is SFF-8636 compliant */
11311 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11312 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11314 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11315 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11318 case I40E_MODULE_TYPE_QSFP28:
11319 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11320 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11323 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11329 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11330 struct rte_dev_eeprom_info *info)
11332 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11333 bool is_sfp = false;
11334 i40e_status status;
11336 uint32_t value = 0;
11339 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11343 for (i = 0; i < info->length; i++) {
11344 u32 offset = i + info->offset;
11345 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11347 /* Check if we need to access the other memory page */
11349 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11350 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11351 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11354 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11355 /* Compute memory page number and offset. */
11356 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11360 status = i40e_aq_get_phy_register(hw,
11361 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11362 addr, 1, offset, &value, NULL);
11365 data[i] = (uint8_t)value;
11370 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11371 struct rte_ether_addr *mac_addr)
11373 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11374 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11375 struct i40e_vsi *vsi = pf->main_vsi;
11376 struct i40e_mac_filter_info mac_filter;
11377 struct i40e_mac_filter *f;
11380 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11381 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11385 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11386 if (rte_is_same_ether_addr(&pf->dev_addr,
11387 &f->mac_info.mac_addr))
11392 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11396 mac_filter = f->mac_info;
11397 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11398 if (ret != I40E_SUCCESS) {
11399 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11402 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11403 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11404 if (ret != I40E_SUCCESS) {
11405 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11408 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11410 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11411 mac_addr->addr_bytes, NULL);
11412 if (ret != I40E_SUCCESS) {
11413 PMD_DRV_LOG(ERR, "Failed to change mac");
11421 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused)
11423 /* mtu setting is forbidden if port is start */
11424 if (dev->data->dev_started != 0) {
11425 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11426 dev->data->port_id);
11433 /* Restore ethertype filter */
11435 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11437 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11438 struct i40e_ethertype_filter_list
11439 *ethertype_list = &pf->ethertype.ethertype_list;
11440 struct i40e_ethertype_filter *f;
11441 struct i40e_control_filter_stats stats;
11444 TAILQ_FOREACH(f, ethertype_list, rules) {
11446 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11447 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11448 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11449 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11450 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11452 memset(&stats, 0, sizeof(stats));
11453 i40e_aq_add_rem_control_packet_filter(hw,
11454 f->input.mac_addr.addr_bytes,
11455 f->input.ether_type,
11456 flags, pf->main_vsi->seid,
11457 f->queue, 1, &stats, NULL);
11459 PMD_DRV_LOG(INFO, "Ethertype filter:"
11460 " mac_etype_used = %u, etype_used = %u,"
11461 " mac_etype_free = %u, etype_free = %u",
11462 stats.mac_etype_used, stats.etype_used,
11463 stats.mac_etype_free, stats.etype_free);
11466 /* Restore tunnel filter */
11468 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11470 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11471 struct i40e_vsi *vsi;
11472 struct i40e_pf_vf *vf;
11473 struct i40e_tunnel_filter_list
11474 *tunnel_list = &pf->tunnel.tunnel_list;
11475 struct i40e_tunnel_filter *f;
11476 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11477 bool big_buffer = 0;
11479 TAILQ_FOREACH(f, tunnel_list, rules) {
11481 vsi = pf->main_vsi;
11483 vf = &pf->vfs[f->vf_id];
11486 memset(&cld_filter, 0, sizeof(cld_filter));
11487 rte_ether_addr_copy((struct rte_ether_addr *)
11488 &f->input.outer_mac,
11489 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11490 rte_ether_addr_copy((struct rte_ether_addr *)
11491 &f->input.inner_mac,
11492 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11493 cld_filter.element.inner_vlan = f->input.inner_vlan;
11494 cld_filter.element.flags = f->input.flags;
11495 cld_filter.element.tenant_id = f->input.tenant_id;
11496 cld_filter.element.queue_number = f->queue;
11497 rte_memcpy(cld_filter.general_fields,
11498 f->input.general_fields,
11499 sizeof(f->input.general_fields));
11501 if (((f->input.flags &
11502 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11503 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11505 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11506 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11508 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11509 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11513 i40e_aq_add_cloud_filters_bb(hw,
11514 vsi->seid, &cld_filter, 1);
11516 i40e_aq_add_cloud_filters(hw, vsi->seid,
11517 &cld_filter.element, 1);
11522 i40e_filter_restore(struct i40e_pf *pf)
11524 i40e_ethertype_filter_restore(pf);
11525 i40e_tunnel_filter_restore(pf);
11526 i40e_fdir_filter_restore(pf);
11527 (void)i40e_hash_filter_restore(pf);
11531 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11533 if (strcmp(dev->device->driver->name, drv->driver.name))
11540 is_i40e_supported(struct rte_eth_dev *dev)
11542 return is_device_supported(dev, &rte_i40e_pmd);
11545 struct i40e_customized_pctype*
11546 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11550 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11551 if (pf->customized_pctype[i].index == index)
11552 return &pf->customized_pctype[i];
11558 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11559 uint32_t pkg_size, uint32_t proto_num,
11560 struct rte_pmd_i40e_proto_info *proto,
11561 enum rte_pmd_i40e_package_op op)
11563 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11564 uint32_t pctype_num;
11565 struct rte_pmd_i40e_ptype_info *pctype;
11566 uint32_t buff_size;
11567 struct i40e_customized_pctype *new_pctype = NULL;
11569 uint8_t pctype_value;
11574 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11575 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11576 PMD_DRV_LOG(ERR, "Unsupported operation.");
11580 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11581 (uint8_t *)&pctype_num, sizeof(pctype_num),
11582 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11584 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11588 PMD_DRV_LOG(INFO, "No new pctype added");
11592 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11593 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11595 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11598 /* get information about new pctype list */
11599 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11600 (uint8_t *)pctype, buff_size,
11601 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11603 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11608 /* Update customized pctype. */
11609 for (i = 0; i < pctype_num; i++) {
11610 pctype_value = pctype[i].ptype_id;
11611 memset(name, 0, sizeof(name));
11612 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11613 proto_id = pctype[i].protocols[j];
11614 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11616 for (n = 0; n < proto_num; n++) {
11617 if (proto[n].proto_id != proto_id)
11619 strlcat(name, proto[n].name, sizeof(name));
11620 strlcat(name, "_", sizeof(name));
11624 name[strlen(name) - 1] = '\0';
11625 PMD_DRV_LOG(INFO, "name = %s\n", name);
11626 if (!strcmp(name, "GTPC"))
11628 i40e_find_customized_pctype(pf,
11629 I40E_CUSTOMIZED_GTPC);
11630 else if (!strcmp(name, "GTPU_IPV4"))
11632 i40e_find_customized_pctype(pf,
11633 I40E_CUSTOMIZED_GTPU_IPV4);
11634 else if (!strcmp(name, "GTPU_IPV6"))
11636 i40e_find_customized_pctype(pf,
11637 I40E_CUSTOMIZED_GTPU_IPV6);
11638 else if (!strcmp(name, "GTPU"))
11640 i40e_find_customized_pctype(pf,
11641 I40E_CUSTOMIZED_GTPU);
11642 else if (!strcmp(name, "IPV4_L2TPV3"))
11644 i40e_find_customized_pctype(pf,
11645 I40E_CUSTOMIZED_IPV4_L2TPV3);
11646 else if (!strcmp(name, "IPV6_L2TPV3"))
11648 i40e_find_customized_pctype(pf,
11649 I40E_CUSTOMIZED_IPV6_L2TPV3);
11650 else if (!strcmp(name, "IPV4_ESP"))
11652 i40e_find_customized_pctype(pf,
11653 I40E_CUSTOMIZED_ESP_IPV4);
11654 else if (!strcmp(name, "IPV6_ESP"))
11656 i40e_find_customized_pctype(pf,
11657 I40E_CUSTOMIZED_ESP_IPV6);
11658 else if (!strcmp(name, "IPV4_UDP_ESP"))
11660 i40e_find_customized_pctype(pf,
11661 I40E_CUSTOMIZED_ESP_IPV4_UDP);
11662 else if (!strcmp(name, "IPV6_UDP_ESP"))
11664 i40e_find_customized_pctype(pf,
11665 I40E_CUSTOMIZED_ESP_IPV6_UDP);
11666 else if (!strcmp(name, "IPV4_AH"))
11668 i40e_find_customized_pctype(pf,
11669 I40E_CUSTOMIZED_AH_IPV4);
11670 else if (!strcmp(name, "IPV6_AH"))
11672 i40e_find_customized_pctype(pf,
11673 I40E_CUSTOMIZED_AH_IPV6);
11675 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11676 new_pctype->pctype = pctype_value;
11677 new_pctype->valid = true;
11679 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11680 new_pctype->valid = false;
11690 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11691 uint32_t pkg_size, uint32_t proto_num,
11692 struct rte_pmd_i40e_proto_info *proto,
11693 enum rte_pmd_i40e_package_op op)
11695 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11696 uint16_t port_id = dev->data->port_id;
11697 uint32_t ptype_num;
11698 struct rte_pmd_i40e_ptype_info *ptype;
11699 uint32_t buff_size;
11701 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11706 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11707 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11708 PMD_DRV_LOG(ERR, "Unsupported operation.");
11712 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11713 rte_pmd_i40e_ptype_mapping_reset(port_id);
11717 /* get information about new ptype num */
11718 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11719 (uint8_t *)&ptype_num, sizeof(ptype_num),
11720 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11722 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11726 PMD_DRV_LOG(INFO, "No new ptype added");
11730 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11731 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11733 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11737 /* get information about new ptype list */
11738 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11739 (uint8_t *)ptype, buff_size,
11740 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11742 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11747 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11748 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11749 if (!ptype_mapping) {
11750 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11755 /* Update ptype mapping table. */
11756 for (i = 0; i < ptype_num; i++) {
11757 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11758 ptype_mapping[i].sw_ptype = 0;
11760 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11761 proto_id = ptype[i].protocols[j];
11762 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11764 for (n = 0; n < proto_num; n++) {
11765 if (proto[n].proto_id != proto_id)
11767 memset(name, 0, sizeof(name));
11768 strcpy(name, proto[n].name);
11769 PMD_DRV_LOG(INFO, "name = %s\n", name);
11770 if (!strncasecmp(name, "PPPOE", 5))
11771 ptype_mapping[i].sw_ptype |=
11772 RTE_PTYPE_L2_ETHER_PPPOE;
11773 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11775 ptype_mapping[i].sw_ptype |=
11776 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11777 ptype_mapping[i].sw_ptype |=
11779 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11781 ptype_mapping[i].sw_ptype |=
11782 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11783 ptype_mapping[i].sw_ptype |=
11784 RTE_PTYPE_INNER_L4_FRAG;
11785 } else if (!strncasecmp(name, "OIPV4", 5)) {
11786 ptype_mapping[i].sw_ptype |=
11787 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11789 } else if (!strncasecmp(name, "IPV4", 4) &&
11791 ptype_mapping[i].sw_ptype |=
11792 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11793 else if (!strncasecmp(name, "IPV4", 4) &&
11795 ptype_mapping[i].sw_ptype |=
11796 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11797 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11799 ptype_mapping[i].sw_ptype |=
11800 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11801 ptype_mapping[i].sw_ptype |=
11803 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11805 ptype_mapping[i].sw_ptype |=
11806 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11807 ptype_mapping[i].sw_ptype |=
11808 RTE_PTYPE_INNER_L4_FRAG;
11809 } else if (!strncasecmp(name, "OIPV6", 5)) {
11810 ptype_mapping[i].sw_ptype |=
11811 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11813 } else if (!strncasecmp(name, "IPV6", 4) &&
11815 ptype_mapping[i].sw_ptype |=
11816 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11817 else if (!strncasecmp(name, "IPV6", 4) &&
11819 ptype_mapping[i].sw_ptype |=
11820 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11821 else if (!strncasecmp(name, "UDP", 3) &&
11823 ptype_mapping[i].sw_ptype |=
11825 else if (!strncasecmp(name, "UDP", 3) &&
11827 ptype_mapping[i].sw_ptype |=
11828 RTE_PTYPE_INNER_L4_UDP;
11829 else if (!strncasecmp(name, "TCP", 3) &&
11831 ptype_mapping[i].sw_ptype |=
11833 else if (!strncasecmp(name, "TCP", 3) &&
11835 ptype_mapping[i].sw_ptype |=
11836 RTE_PTYPE_INNER_L4_TCP;
11837 else if (!strncasecmp(name, "SCTP", 4) &&
11839 ptype_mapping[i].sw_ptype |=
11841 else if (!strncasecmp(name, "SCTP", 4) &&
11843 ptype_mapping[i].sw_ptype |=
11844 RTE_PTYPE_INNER_L4_SCTP;
11845 else if ((!strncasecmp(name, "ICMP", 4) ||
11846 !strncasecmp(name, "ICMPV6", 6)) &&
11848 ptype_mapping[i].sw_ptype |=
11850 else if ((!strncasecmp(name, "ICMP", 4) ||
11851 !strncasecmp(name, "ICMPV6", 6)) &&
11853 ptype_mapping[i].sw_ptype |=
11854 RTE_PTYPE_INNER_L4_ICMP;
11855 else if (!strncasecmp(name, "GTPC", 4)) {
11856 ptype_mapping[i].sw_ptype |=
11857 RTE_PTYPE_TUNNEL_GTPC;
11859 } else if (!strncasecmp(name, "GTPU", 4)) {
11860 ptype_mapping[i].sw_ptype |=
11861 RTE_PTYPE_TUNNEL_GTPU;
11863 } else if (!strncasecmp(name, "ESP", 3)) {
11864 ptype_mapping[i].sw_ptype |=
11865 RTE_PTYPE_TUNNEL_ESP;
11867 } else if (!strncasecmp(name, "GRENAT", 6)) {
11868 ptype_mapping[i].sw_ptype |=
11869 RTE_PTYPE_TUNNEL_GRENAT;
11871 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
11872 !strncasecmp(name, "L2TPV2", 6) ||
11873 !strncasecmp(name, "L2TPV3", 6)) {
11874 ptype_mapping[i].sw_ptype |=
11875 RTE_PTYPE_TUNNEL_L2TP;
11884 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11887 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
11889 rte_free(ptype_mapping);
11895 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11896 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11898 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11899 uint32_t proto_num;
11900 struct rte_pmd_i40e_proto_info *proto;
11901 uint32_t buff_size;
11905 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11906 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11907 PMD_DRV_LOG(ERR, "Unsupported operation.");
11911 /* get information about protocol number */
11912 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11913 (uint8_t *)&proto_num, sizeof(proto_num),
11914 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11916 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11920 PMD_DRV_LOG(INFO, "No new protocol added");
11924 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11925 proto = rte_zmalloc("new_proto", buff_size, 0);
11927 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11931 /* get information about protocol list */
11932 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11933 (uint8_t *)proto, buff_size,
11934 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11936 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11941 /* Check if GTP is supported. */
11942 for (i = 0; i < proto_num; i++) {
11943 if (!strncmp(proto[i].name, "GTP", 3)) {
11944 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11945 pf->gtp_support = true;
11947 pf->gtp_support = false;
11952 /* Check if ESP is supported. */
11953 for (i = 0; i < proto_num; i++) {
11954 if (!strncmp(proto[i].name, "ESP", 3)) {
11955 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11956 pf->esp_support = true;
11958 pf->esp_support = false;
11963 /* Update customized pctype info */
11964 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11965 proto_num, proto, op);
11967 PMD_DRV_LOG(INFO, "No pctype is updated.");
11969 /* Update customized ptype info */
11970 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11971 proto_num, proto, op);
11973 PMD_DRV_LOG(INFO, "No ptype is updated.");
11978 /* Create a QinQ cloud filter
11980 * The Fortville NIC has limited resources for tunnel filters,
11981 * so we can only reuse existing filters.
11983 * In step 1 we define which Field Vector fields can be used for
11985 * As we do not have the inner tag defined as a field,
11986 * we have to define it first, by reusing one of L1 entries.
11988 * In step 2 we are replacing one of existing filter types with
11989 * a new one for QinQ.
11990 * As we reusing L1 and replacing L2, some of the default filter
11991 * types will disappear,which depends on L1 and L2 entries we reuse.
11993 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11995 * 1. Create L1 filter of outer vlan (12b) which will be in use
11996 * later when we define the cloud filter.
11997 * a. Valid_flags.replace_cloud = 0
11998 * b. Old_filter = 10 (Stag_Inner_Vlan)
11999 * c. New_filter = 0x10
12000 * d. TR bit = 0xff (optional, not used here)
12001 * e. Buffer – 2 entries:
12002 * i. Byte 0 = 8 (outer vlan FV index).
12004 * Byte 2-3 = 0x0fff
12005 * ii. Byte 0 = 37 (inner vlan FV index).
12007 * Byte 2-3 = 0x0fff
12010 * 2. Create cloud filter using two L1 filters entries: stag and
12011 * new filter(outer vlan+ inner vlan)
12012 * a. Valid_flags.replace_cloud = 1
12013 * b. Old_filter = 1 (instead of outer IP)
12014 * c. New_filter = 0x10
12015 * d. Buffer – 2 entries:
12016 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12017 * Byte 1-3 = 0 (rsv)
12018 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12019 * Byte 9-11 = 0 (rsv)
12022 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12024 int ret = -ENOTSUP;
12025 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12026 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12027 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12028 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
12030 if (pf->support_multi_driver) {
12031 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12036 memset(&filter_replace, 0,
12037 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12038 memset(&filter_replace_buf, 0,
12039 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12041 /* create L1 filter */
12042 filter_replace.old_filter_type =
12043 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12044 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12045 filter_replace.tr_bit = 0;
12047 /* Prepare the buffer, 2 entries */
12048 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12049 filter_replace_buf.data[0] |=
12050 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12051 /* Field Vector 12b mask */
12052 filter_replace_buf.data[2] = 0xff;
12053 filter_replace_buf.data[3] = 0x0f;
12054 filter_replace_buf.data[4] =
12055 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12056 filter_replace_buf.data[4] |=
12057 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12058 /* Field Vector 12b mask */
12059 filter_replace_buf.data[6] = 0xff;
12060 filter_replace_buf.data[7] = 0x0f;
12061 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12062 &filter_replace_buf);
12063 if (ret != I40E_SUCCESS)
12066 if (filter_replace.old_filter_type !=
12067 filter_replace.new_filter_type)
12068 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12069 " original: 0x%x, new: 0x%x",
12071 filter_replace.old_filter_type,
12072 filter_replace.new_filter_type);
12074 /* Apply the second L2 cloud filter */
12075 memset(&filter_replace, 0,
12076 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12077 memset(&filter_replace_buf, 0,
12078 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12080 /* create L2 filter, input for L2 filter will be L1 filter */
12081 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12082 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12083 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12085 /* Prepare the buffer, 2 entries */
12086 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12087 filter_replace_buf.data[0] |=
12088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12089 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12090 filter_replace_buf.data[4] |=
12091 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12092 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12093 &filter_replace_buf);
12094 if (!ret && (filter_replace.old_filter_type !=
12095 filter_replace.new_filter_type))
12096 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12097 " original: 0x%x, new: 0x%x",
12099 filter_replace.old_filter_type,
12100 filter_replace.new_filter_type);
12105 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12106 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12107 #ifdef RTE_ETHDEV_DEBUG_RX
12108 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12110 #ifdef RTE_ETHDEV_DEBUG_TX
12111 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12114 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12115 ETH_I40E_FLOATING_VEB_ARG "=1"
12116 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12117 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12118 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");